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1053d35f RR |
1 | /****************************************************************************** |
2 | * | |
128e63ef | 3 | * Copyright(c) 2003 - 2013 Intel Corporation. All rights reserved. |
1053d35f RR |
4 | * |
5 | * Portions of this file are derived from the ipw3945 project, as well | |
6 | * as portions of the ieee80211 subsystem header files. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of version 2 of the GNU General Public License as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
20 | * | |
21 | * The full GNU General Public License is included in this distribution in the | |
22 | * file called LICENSE. | |
23 | * | |
24 | * Contact Information: | |
759ef89f | 25 | * Intel Linux Wireless <ilw@linux.intel.com> |
1053d35f RR |
26 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
27 | * | |
28 | *****************************************************************************/ | |
fd4abac5 | 29 | #include <linux/etherdevice.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
253a634c | 31 | #include <linux/sched.h> |
253a634c | 32 | |
522376d2 EG |
33 | #include "iwl-debug.h" |
34 | #include "iwl-csr.h" | |
35 | #include "iwl-prph.h" | |
1053d35f | 36 | #include "iwl-io.h" |
ed277c93 | 37 | #include "iwl-op-mode.h" |
6468a01a | 38 | #include "internal.h" |
6238b008 | 39 | /* FIXME: need to abstract out TX command (once we know what it looks like) */ |
1023fdc4 | 40 | #include "dvm/commands.h" |
1053d35f | 41 | |
522376d2 EG |
42 | #define IWL_TX_CRC_SIZE 4 |
43 | #define IWL_TX_DELIMITER_SIZE 4 | |
44 | ||
f02831be EG |
45 | /*************** DMA-QUEUE-GENERAL-FUNCTIONS ***** |
46 | * DMA services | |
47 | * | |
48 | * Theory of operation | |
49 | * | |
50 | * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer | |
51 | * of buffer descriptors, each of which points to one or more data buffers for | |
52 | * the device to read from or fill. Driver and device exchange status of each | |
53 | * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty | |
54 | * entries in each circular buffer, to protect against confusing empty and full | |
55 | * queue states. | |
56 | * | |
57 | * The device reads or writes the data in the queues via the device's several | |
58 | * DMA/FIFO channels. Each queue is mapped to a single DMA channel. | |
59 | * | |
60 | * For Tx queue, there are low mark and high mark limits. If, after queuing | |
61 | * the packet for Tx, free space become < low mark, Tx queue stopped. When | |
62 | * reclaiming packets (on 'tx done IRQ), if free space become > high mark, | |
63 | * Tx queue resumed. | |
64 | * | |
65 | ***************************************************/ | |
66 | static int iwl_queue_space(const struct iwl_queue *q) | |
67 | { | |
68 | int s = q->read_ptr - q->write_ptr; | |
69 | ||
70 | if (q->read_ptr > q->write_ptr) | |
71 | s -= q->n_bd; | |
72 | ||
73 | if (s <= 0) | |
74 | s += q->n_window; | |
75 | /* keep some reserve to not confuse empty and full situations */ | |
76 | s -= 2; | |
77 | if (s < 0) | |
78 | s = 0; | |
79 | return s; | |
80 | } | |
81 | ||
82 | /* | |
83 | * iwl_queue_init - Initialize queue's high/low-water and read/write indexes | |
84 | */ | |
85 | static int iwl_queue_init(struct iwl_queue *q, int count, int slots_num, u32 id) | |
86 | { | |
87 | q->n_bd = count; | |
88 | q->n_window = slots_num; | |
89 | q->id = id; | |
90 | ||
91 | /* count must be power-of-two size, otherwise iwl_queue_inc_wrap | |
92 | * and iwl_queue_dec_wrap are broken. */ | |
93 | if (WARN_ON(!is_power_of_2(count))) | |
94 | return -EINVAL; | |
95 | ||
96 | /* slots_num must be power-of-two size, otherwise | |
97 | * get_cmd_index is broken. */ | |
98 | if (WARN_ON(!is_power_of_2(slots_num))) | |
99 | return -EINVAL; | |
100 | ||
101 | q->low_mark = q->n_window / 4; | |
102 | if (q->low_mark < 4) | |
103 | q->low_mark = 4; | |
104 | ||
105 | q->high_mark = q->n_window / 8; | |
106 | if (q->high_mark < 2) | |
107 | q->high_mark = 2; | |
108 | ||
109 | q->write_ptr = 0; | |
110 | q->read_ptr = 0; | |
111 | ||
112 | return 0; | |
113 | } | |
114 | ||
f02831be EG |
115 | static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, |
116 | struct iwl_dma_ptr *ptr, size_t size) | |
117 | { | |
118 | if (WARN_ON(ptr->addr)) | |
119 | return -EINVAL; | |
120 | ||
121 | ptr->addr = dma_alloc_coherent(trans->dev, size, | |
122 | &ptr->dma, GFP_KERNEL); | |
123 | if (!ptr->addr) | |
124 | return -ENOMEM; | |
125 | ptr->size = size; | |
126 | return 0; | |
127 | } | |
128 | ||
129 | static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, | |
130 | struct iwl_dma_ptr *ptr) | |
131 | { | |
132 | if (unlikely(!ptr->addr)) | |
133 | return; | |
134 | ||
135 | dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma); | |
136 | memset(ptr, 0, sizeof(*ptr)); | |
137 | } | |
138 | ||
139 | static void iwl_pcie_txq_stuck_timer(unsigned long data) | |
140 | { | |
141 | struct iwl_txq *txq = (void *)data; | |
142 | struct iwl_queue *q = &txq->q; | |
143 | struct iwl_trans_pcie *trans_pcie = txq->trans_pcie; | |
144 | struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie); | |
145 | u32 scd_sram_addr = trans_pcie->scd_base_addr + | |
146 | SCD_TX_STTS_QUEUE_OFFSET(txq->q.id); | |
147 | u8 buf[16]; | |
148 | int i; | |
149 | ||
150 | spin_lock(&txq->lock); | |
151 | /* check if triggered erroneously */ | |
152 | if (txq->q.read_ptr == txq->q.write_ptr) { | |
153 | spin_unlock(&txq->lock); | |
154 | return; | |
155 | } | |
156 | spin_unlock(&txq->lock); | |
157 | ||
158 | IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id, | |
159 | jiffies_to_msecs(trans_pcie->wd_timeout)); | |
160 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | |
161 | txq->q.read_ptr, txq->q.write_ptr); | |
162 | ||
4fd442db | 163 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
f02831be EG |
164 | |
165 | iwl_print_hex_error(trans, buf, sizeof(buf)); | |
166 | ||
167 | for (i = 0; i < FH_TCSR_CHNL_NUM; i++) | |
168 | IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i, | |
169 | iwl_read_direct32(trans, FH_TX_TRB_REG(i))); | |
170 | ||
171 | for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) { | |
172 | u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i)); | |
173 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | |
174 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | |
175 | u32 tbl_dw = | |
4fd442db EG |
176 | iwl_trans_read_mem32(trans, |
177 | trans_pcie->scd_base_addr + | |
178 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | |
f02831be EG |
179 | |
180 | if (i & 0x1) | |
181 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | |
182 | else | |
183 | tbl_dw = tbl_dw & 0x0000FFFF; | |
184 | ||
185 | IWL_ERR(trans, | |
186 | "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", | |
187 | i, active ? "" : "in", fifo, tbl_dw, | |
188 | iwl_read_prph(trans, | |
189 | SCD_QUEUE_RDPTR(i)) & (txq->q.n_bd - 1), | |
190 | iwl_read_prph(trans, SCD_QUEUE_WRPTR(i))); | |
191 | } | |
192 | ||
193 | for (i = q->read_ptr; i != q->write_ptr; | |
38c0f334 | 194 | i = iwl_queue_inc_wrap(i, q->n_bd)) |
f02831be | 195 | IWL_ERR(trans, "scratch %d = 0x%08x\n", i, |
38c0f334 | 196 | le32_to_cpu(txq->scratchbufs[i].scratch)); |
f02831be EG |
197 | |
198 | iwl_op_mode_nic_error(trans->op_mode); | |
199 | } | |
200 | ||
990aa6d7 EG |
201 | /* |
202 | * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array | |
48d42c42 | 203 | */ |
f02831be EG |
204 | static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans, |
205 | struct iwl_txq *txq, u16 byte_cnt) | |
48d42c42 | 206 | { |
105183b1 | 207 | struct iwlagn_scd_bc_tbl *scd_bc_tbl; |
20d3b647 | 208 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
209 | int write_ptr = txq->q.write_ptr; |
210 | int txq_id = txq->q.id; | |
211 | u8 sec_ctl = 0; | |
212 | u8 sta_id = 0; | |
213 | u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE; | |
214 | __le16 bc_ent; | |
132f98c2 | 215 | struct iwl_tx_cmd *tx_cmd = |
bf8440e6 | 216 | (void *) txq->entries[txq->q.write_ptr].cmd->payload; |
48d42c42 | 217 | |
105183b1 EG |
218 | scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; |
219 | ||
48d42c42 EG |
220 | WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX); |
221 | ||
132f98c2 EG |
222 | sta_id = tx_cmd->sta_id; |
223 | sec_ctl = tx_cmd->sec_ctl; | |
48d42c42 EG |
224 | |
225 | switch (sec_ctl & TX_CMD_SEC_MSK) { | |
226 | case TX_CMD_SEC_CCM: | |
4325f6ca | 227 | len += IEEE80211_CCMP_MIC_LEN; |
48d42c42 EG |
228 | break; |
229 | case TX_CMD_SEC_TKIP: | |
4325f6ca | 230 | len += IEEE80211_TKIP_ICV_LEN; |
48d42c42 EG |
231 | break; |
232 | case TX_CMD_SEC_WEP: | |
4325f6ca | 233 | len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN; |
48d42c42 EG |
234 | break; |
235 | } | |
236 | ||
046db346 EG |
237 | if (trans_pcie->bc_table_dword) |
238 | len = DIV_ROUND_UP(len, 4); | |
239 | ||
240 | bc_ent = cpu_to_le16(len | (sta_id << 12)); | |
48d42c42 EG |
241 | |
242 | scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent; | |
243 | ||
244 | if (write_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
245 | scd_bc_tbl[txq_id]. | |
246 | tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent; | |
247 | } | |
248 | ||
f02831be EG |
249 | static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans, |
250 | struct iwl_txq *txq) | |
251 | { | |
252 | struct iwl_trans_pcie *trans_pcie = | |
253 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
254 | struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr; | |
255 | int txq_id = txq->q.id; | |
256 | int read_ptr = txq->q.read_ptr; | |
257 | u8 sta_id = 0; | |
258 | __le16 bc_ent; | |
259 | struct iwl_tx_cmd *tx_cmd = | |
260 | (void *)txq->entries[txq->q.read_ptr].cmd->payload; | |
261 | ||
262 | WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX); | |
263 | ||
264 | if (txq_id != trans_pcie->cmd_queue) | |
265 | sta_id = tx_cmd->sta_id; | |
266 | ||
267 | bc_ent = cpu_to_le16(1 | (sta_id << 12)); | |
268 | scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent; | |
269 | ||
270 | if (read_ptr < TFD_QUEUE_SIZE_BC_DUP) | |
271 | scd_bc_tbl[txq_id]. | |
272 | tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent; | |
273 | } | |
274 | ||
990aa6d7 EG |
275 | /* |
276 | * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware | |
fd4abac5 | 277 | */ |
990aa6d7 | 278 | void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq) |
fd4abac5 TW |
279 | { |
280 | u32 reg = 0; | |
fd4abac5 TW |
281 | int txq_id = txq->q.id; |
282 | ||
283 | if (txq->need_update == 0) | |
7bfedc59 | 284 | return; |
fd4abac5 | 285 | |
035f7ff2 | 286 | if (trans->cfg->base_params->shadow_reg_enable) { |
f81c1f48 | 287 | /* shadow register enabled */ |
1042db2a | 288 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
289 | txq->q.write_ptr | (txq_id << 8)); |
290 | } else { | |
47107e84 DF |
291 | struct iwl_trans_pcie *trans_pcie = |
292 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
f81c1f48 | 293 | /* if we're trying to save power */ |
01d651d4 | 294 | if (test_bit(STATUS_TPOWER_PMI, &trans_pcie->status)) { |
f81c1f48 WYG |
295 | /* wake up nic if it's powered down ... |
296 | * uCode will wake up, and interrupt us again, so next | |
297 | * time we'll skip this part. */ | |
1042db2a | 298 | reg = iwl_read32(trans, CSR_UCODE_DRV_GP1); |
fd4abac5 | 299 | |
f81c1f48 | 300 | if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) { |
fd656935 | 301 | IWL_DEBUG_INFO(trans, |
f81c1f48 WYG |
302 | "Tx queue %d requesting wakeup," |
303 | " GP1 = 0x%x\n", txq_id, reg); | |
1042db2a | 304 | iwl_set_bit(trans, CSR_GP_CNTRL, |
f81c1f48 WYG |
305 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
306 | return; | |
307 | } | |
fd4abac5 | 308 | |
1c3fea82 EG |
309 | IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, |
310 | txq->q.write_ptr); | |
311 | ||
1042db2a | 312 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, |
fd4abac5 | 313 | txq->q.write_ptr | (txq_id << 8)); |
fd4abac5 | 314 | |
f81c1f48 WYG |
315 | /* |
316 | * else not in power-save mode, | |
317 | * uCode will never sleep when we're | |
318 | * trying to tx (during RFKILL, we're not trying to tx). | |
319 | */ | |
320 | } else | |
1042db2a | 321 | iwl_write32(trans, HBUS_TARG_WRPTR, |
f81c1f48 WYG |
322 | txq->q.write_ptr | (txq_id << 8)); |
323 | } | |
fd4abac5 | 324 | txq->need_update = 0; |
fd4abac5 | 325 | } |
fd4abac5 | 326 | |
f02831be | 327 | static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
328 | { |
329 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
330 | ||
331 | dma_addr_t addr = get_unaligned_le32(&tb->lo); | |
332 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
333 | addr |= | |
334 | ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16; | |
335 | ||
336 | return addr; | |
337 | } | |
338 | ||
f02831be | 339 | static inline u16 iwl_pcie_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx) |
214d14d4 JB |
340 | { |
341 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
342 | ||
343 | return le16_to_cpu(tb->hi_n_len) >> 4; | |
344 | } | |
345 | ||
f02831be EG |
346 | static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx, |
347 | dma_addr_t addr, u16 len) | |
214d14d4 JB |
348 | { |
349 | struct iwl_tfd_tb *tb = &tfd->tbs[idx]; | |
350 | u16 hi_n_len = len << 4; | |
351 | ||
352 | put_unaligned_le32(addr, &tb->lo); | |
353 | if (sizeof(dma_addr_t) > sizeof(u32)) | |
354 | hi_n_len |= ((addr >> 16) >> 16) & 0xF; | |
355 | ||
356 | tb->hi_n_len = cpu_to_le16(hi_n_len); | |
357 | ||
358 | tfd->num_tbs = idx + 1; | |
359 | } | |
360 | ||
f02831be | 361 | static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd) |
214d14d4 JB |
362 | { |
363 | return tfd->num_tbs & 0x1f; | |
364 | } | |
365 | ||
f02831be | 366 | static void iwl_pcie_tfd_unmap(struct iwl_trans *trans, |
98891754 JB |
367 | struct iwl_cmd_meta *meta, |
368 | struct iwl_tfd *tfd) | |
214d14d4 | 369 | { |
214d14d4 JB |
370 | int i; |
371 | int num_tbs; | |
372 | ||
214d14d4 | 373 | /* Sanity check on number of chunks */ |
f02831be | 374 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); |
214d14d4 JB |
375 | |
376 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
6d8f6eeb | 377 | IWL_ERR(trans, "Too many chunks: %i\n", num_tbs); |
214d14d4 JB |
378 | /* @todo issue fatal error, it is quite serious situation */ |
379 | return; | |
380 | } | |
381 | ||
38c0f334 | 382 | /* first TB is never freed - it's the scratchbuf data */ |
214d14d4 | 383 | |
214d14d4 | 384 | for (i = 1; i < num_tbs; i++) |
f02831be | 385 | dma_unmap_single(trans->dev, iwl_pcie_tfd_tb_get_addr(tfd, i), |
98891754 JB |
386 | iwl_pcie_tfd_tb_get_len(tfd, i), |
387 | DMA_TO_DEVICE); | |
ebed633c EG |
388 | |
389 | tfd->num_tbs = 0; | |
4ce7cc2b JB |
390 | } |
391 | ||
990aa6d7 EG |
392 | /* |
393 | * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] | |
6d8f6eeb | 394 | * @trans - transport private data |
4ce7cc2b | 395 | * @txq - tx queue |
ebed633c | 396 | * @dma_dir - the direction of the DMA mapping |
4ce7cc2b JB |
397 | * |
398 | * Does NOT advance any TFD circular buffer read/write indexes | |
399 | * Does NOT free the TFD itself (which is within circular buffer) | |
400 | */ | |
98891754 | 401 | static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq) |
4ce7cc2b JB |
402 | { |
403 | struct iwl_tfd *tfd_tmp = txq->tfds; | |
4ce7cc2b | 404 | |
ebed633c EG |
405 | /* rd_ptr is bounded by n_bd and idx is bounded by n_window */ |
406 | int rd_ptr = txq->q.read_ptr; | |
407 | int idx = get_cmd_index(&txq->q, rd_ptr); | |
408 | ||
015c15e1 JB |
409 | lockdep_assert_held(&txq->lock); |
410 | ||
ebed633c | 411 | /* We have only q->n_window txq->entries, but we use q->n_bd tfds */ |
98891754 | 412 | iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]); |
214d14d4 JB |
413 | |
414 | /* free SKB */ | |
bf8440e6 | 415 | if (txq->entries) { |
214d14d4 JB |
416 | struct sk_buff *skb; |
417 | ||
ebed633c | 418 | skb = txq->entries[idx].skb; |
214d14d4 | 419 | |
909e9b23 EG |
420 | /* Can be called from irqs-disabled context |
421 | * If skb is not NULL, it means that the whole queue is being | |
422 | * freed and that the queue is not empty - free the skb | |
423 | */ | |
214d14d4 | 424 | if (skb) { |
ed277c93 | 425 | iwl_op_mode_free_skb(trans->op_mode, skb); |
ebed633c | 426 | txq->entries[idx].skb = NULL; |
214d14d4 JB |
427 | } |
428 | } | |
429 | } | |
430 | ||
f02831be EG |
431 | static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq, |
432 | dma_addr_t addr, u16 len, u8 reset) | |
214d14d4 JB |
433 | { |
434 | struct iwl_queue *q; | |
435 | struct iwl_tfd *tfd, *tfd_tmp; | |
436 | u32 num_tbs; | |
437 | ||
438 | q = &txq->q; | |
4ce7cc2b | 439 | tfd_tmp = txq->tfds; |
214d14d4 JB |
440 | tfd = &tfd_tmp[q->write_ptr]; |
441 | ||
f02831be EG |
442 | if (reset) |
443 | memset(tfd, 0, sizeof(*tfd)); | |
444 | ||
445 | num_tbs = iwl_pcie_tfd_get_num_tbs(tfd); | |
446 | ||
447 | /* Each TFD can point to a maximum 20 Tx buffers */ | |
448 | if (num_tbs >= IWL_NUM_OF_TBS) { | |
449 | IWL_ERR(trans, "Error can not send more than %d chunks\n", | |
450 | IWL_NUM_OF_TBS); | |
451 | return -EINVAL; | |
452 | } | |
453 | ||
1092b9bc EP |
454 | if (WARN(addr & ~IWL_TX_DMA_MASK, |
455 | "Unaligned address = %llx\n", (unsigned long long)addr)) | |
f02831be EG |
456 | return -EINVAL; |
457 | ||
f02831be EG |
458 | iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len); |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | static int iwl_pcie_txq_alloc(struct iwl_trans *trans, | |
464 | struct iwl_txq *txq, int slots_num, | |
465 | u32 txq_id) | |
466 | { | |
467 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
468 | size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX; | |
38c0f334 | 469 | size_t scratchbuf_sz; |
f02831be EG |
470 | int i; |
471 | ||
472 | if (WARN_ON(txq->entries || txq->tfds)) | |
473 | return -EINVAL; | |
474 | ||
475 | setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer, | |
476 | (unsigned long)txq); | |
477 | txq->trans_pcie = trans_pcie; | |
478 | ||
479 | txq->q.n_window = slots_num; | |
480 | ||
481 | txq->entries = kcalloc(slots_num, | |
482 | sizeof(struct iwl_pcie_txq_entry), | |
483 | GFP_KERNEL); | |
484 | ||
485 | if (!txq->entries) | |
486 | goto error; | |
487 | ||
488 | if (txq_id == trans_pcie->cmd_queue) | |
489 | for (i = 0; i < slots_num; i++) { | |
490 | txq->entries[i].cmd = | |
491 | kmalloc(sizeof(struct iwl_device_cmd), | |
492 | GFP_KERNEL); | |
493 | if (!txq->entries[i].cmd) | |
494 | goto error; | |
495 | } | |
496 | ||
497 | /* Circular buffer of transmit frame descriptors (TFDs), | |
498 | * shared with device */ | |
499 | txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz, | |
500 | &txq->q.dma_addr, GFP_KERNEL); | |
d0320f75 | 501 | if (!txq->tfds) |
f02831be | 502 | goto error; |
38c0f334 JB |
503 | |
504 | BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs)); | |
505 | BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) != | |
506 | sizeof(struct iwl_cmd_header) + | |
507 | offsetof(struct iwl_tx_cmd, scratch)); | |
508 | ||
509 | scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num; | |
510 | ||
511 | txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz, | |
512 | &txq->scratchbufs_dma, | |
513 | GFP_KERNEL); | |
514 | if (!txq->scratchbufs) | |
515 | goto err_free_tfds; | |
516 | ||
f02831be EG |
517 | txq->q.id = txq_id; |
518 | ||
519 | return 0; | |
38c0f334 JB |
520 | err_free_tfds: |
521 | dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr); | |
f02831be EG |
522 | error: |
523 | if (txq->entries && txq_id == trans_pcie->cmd_queue) | |
524 | for (i = 0; i < slots_num; i++) | |
525 | kfree(txq->entries[i].cmd); | |
526 | kfree(txq->entries); | |
527 | txq->entries = NULL; | |
528 | ||
529 | return -ENOMEM; | |
530 | ||
531 | } | |
532 | ||
533 | static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, | |
534 | int slots_num, u32 txq_id) | |
535 | { | |
536 | int ret; | |
537 | ||
538 | txq->need_update = 0; | |
539 | ||
540 | /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise | |
541 | * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */ | |
542 | BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1)); | |
543 | ||
544 | /* Initialize queue's high/low-water marks, and head/tail indexes */ | |
545 | ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num, | |
546 | txq_id); | |
547 | if (ret) | |
548 | return ret; | |
549 | ||
550 | spin_lock_init(&txq->lock); | |
551 | ||
552 | /* | |
553 | * Tell nic where to find circular buffer of Tx Frame Descriptors for | |
554 | * given Tx queue, and enable the DMA channel used for that queue. | |
555 | * Circular buffer (TFD queue in DRAM) physical base address */ | |
556 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
557 | txq->q.dma_addr >> 8); | |
558 | ||
559 | return 0; | |
560 | } | |
561 | ||
562 | /* | |
563 | * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's | |
564 | */ | |
565 | static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id) | |
566 | { | |
567 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
568 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
569 | struct iwl_queue *q = &txq->q; | |
f02831be EG |
570 | |
571 | if (!q->n_bd) | |
572 | return; | |
573 | ||
f02831be EG |
574 | spin_lock_bh(&txq->lock); |
575 | while (q->write_ptr != q->read_ptr) { | |
b967613d EG |
576 | IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n", |
577 | txq_id, q->read_ptr); | |
98891754 | 578 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be EG |
579 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd); |
580 | } | |
b967613d | 581 | txq->active = false; |
f02831be | 582 | spin_unlock_bh(&txq->lock); |
8a487b1a EG |
583 | |
584 | /* just in case - this queue may have been stopped */ | |
585 | iwl_wake_queue(trans, txq); | |
f02831be EG |
586 | } |
587 | ||
588 | /* | |
589 | * iwl_pcie_txq_free - Deallocate DMA queue. | |
590 | * @txq: Transmit queue to deallocate. | |
591 | * | |
592 | * Empty queue by removing and destroying all BD's. | |
593 | * Free all buffers. | |
594 | * 0-fill, but do not free "txq" descriptor structure. | |
595 | */ | |
596 | static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id) | |
597 | { | |
598 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
599 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
600 | struct device *dev = trans->dev; | |
601 | int i; | |
602 | ||
603 | if (WARN_ON(!txq)) | |
604 | return; | |
605 | ||
606 | iwl_pcie_txq_unmap(trans, txq_id); | |
607 | ||
608 | /* De-alloc array of command/tx buffers */ | |
609 | if (txq_id == trans_pcie->cmd_queue) | |
610 | for (i = 0; i < txq->q.n_window; i++) { | |
611 | kfree(txq->entries[i].cmd); | |
f02831be EG |
612 | kfree(txq->entries[i].free_buf); |
613 | } | |
614 | ||
615 | /* De-alloc circular buffer of TFDs */ | |
616 | if (txq->q.n_bd) { | |
617 | dma_free_coherent(dev, sizeof(struct iwl_tfd) * | |
618 | txq->q.n_bd, txq->tfds, txq->q.dma_addr); | |
d21fa2da | 619 | txq->q.dma_addr = 0; |
38c0f334 JB |
620 | |
621 | dma_free_coherent(dev, | |
622 | sizeof(*txq->scratchbufs) * txq->q.n_window, | |
623 | txq->scratchbufs, txq->scratchbufs_dma); | |
f02831be EG |
624 | } |
625 | ||
626 | kfree(txq->entries); | |
627 | txq->entries = NULL; | |
628 | ||
629 | del_timer_sync(&txq->stuck_timer); | |
630 | ||
631 | /* 0-fill queue descriptor structure */ | |
632 | memset(txq, 0, sizeof(*txq)); | |
633 | } | |
634 | ||
635 | /* | |
636 | * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask | |
637 | */ | |
638 | static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask) | |
639 | { | |
640 | struct iwl_trans_pcie __maybe_unused *trans_pcie = | |
641 | IWL_TRANS_GET_PCIE_TRANS(trans); | |
642 | ||
643 | iwl_write_prph(trans, SCD_TXFACT, mask); | |
644 | } | |
645 | ||
646 | void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) | |
647 | { | |
648 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
22dc3c95 | 649 | int nq = trans->cfg->base_params->num_of_queues; |
f02831be EG |
650 | int chan; |
651 | u32 reg_val; | |
22dc3c95 JB |
652 | int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) - |
653 | SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32); | |
f02831be EG |
654 | |
655 | /* make sure all queue are not stopped/used */ | |
656 | memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped)); | |
657 | memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used)); | |
658 | ||
659 | trans_pcie->scd_base_addr = | |
660 | iwl_read_prph(trans, SCD_SRAM_BASE_ADDR); | |
661 | ||
662 | WARN_ON(scd_base_addr != 0 && | |
663 | scd_base_addr != trans_pcie->scd_base_addr); | |
664 | ||
22dc3c95 JB |
665 | /* reset context data, TX status and translation data */ |
666 | iwl_trans_write_mem(trans, trans_pcie->scd_base_addr + | |
667 | SCD_CONTEXT_MEM_LOWER_BOUND, | |
668 | NULL, clear_dwords); | |
f02831be EG |
669 | |
670 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | |
671 | trans_pcie->scd_bc_tbls.dma >> 10); | |
672 | ||
673 | /* The chain extension of the SCD doesn't work well. This feature is | |
674 | * enabled by default by the HW, so we need to disable it manually. | |
675 | */ | |
676 | iwl_write_prph(trans, SCD_CHAINEXT_EN, 0); | |
677 | ||
678 | iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue, | |
679 | trans_pcie->cmd_fifo); | |
680 | ||
681 | /* Activate all Tx DMA/FIFO channels */ | |
682 | iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7)); | |
683 | ||
684 | /* Enable DMA channel */ | |
685 | for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++) | |
686 | iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan), | |
687 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
688 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | |
689 | ||
690 | /* Update FH chicken bits */ | |
691 | reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG); | |
692 | iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG, | |
693 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | |
694 | ||
695 | /* Enable L1-Active */ | |
696 | iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, | |
697 | APMG_PCIDEV_STT_VAL_L1_ACT_DIS); | |
698 | } | |
699 | ||
ddaf5a5b JB |
700 | void iwl_trans_pcie_tx_reset(struct iwl_trans *trans) |
701 | { | |
702 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
703 | int txq_id; | |
704 | ||
705 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
706 | txq_id++) { | |
707 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
708 | ||
709 | iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id), | |
710 | txq->q.dma_addr >> 8); | |
711 | iwl_pcie_txq_unmap(trans, txq_id); | |
712 | txq->q.read_ptr = 0; | |
713 | txq->q.write_ptr = 0; | |
714 | } | |
715 | ||
716 | /* Tell NIC where to find the "keep warm" buffer */ | |
717 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
718 | trans_pcie->kw.dma >> 4); | |
719 | ||
720 | iwl_pcie_tx_start(trans, trans_pcie->scd_base_addr); | |
721 | } | |
722 | ||
f02831be EG |
723 | /* |
724 | * iwl_pcie_tx_stop - Stop all Tx DMA channels | |
725 | */ | |
726 | int iwl_pcie_tx_stop(struct iwl_trans *trans) | |
727 | { | |
728 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
729 | int ch, txq_id, ret; | |
730 | unsigned long flags; | |
731 | ||
732 | /* Turn off all Tx DMA fifos */ | |
733 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
734 | ||
735 | iwl_pcie_txq_set_sched(trans, 0); | |
736 | ||
737 | /* Stop each Tx DMA channel, and wait for it to be idle */ | |
738 | for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) { | |
739 | iwl_write_direct32(trans, | |
740 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | |
741 | ret = iwl_poll_direct_bit(trans, FH_TSSR_TX_STATUS_REG, | |
742 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 1000); | |
743 | if (ret < 0) | |
744 | IWL_ERR(trans, | |
745 | "Failing on timeout while stopping DMA channel %d [0x%08x]\n", | |
746 | ch, | |
747 | iwl_read_direct32(trans, | |
748 | FH_TSSR_TX_STATUS_REG)); | |
749 | } | |
750 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
751 | ||
752 | if (!trans_pcie->txq) { | |
753 | IWL_WARN(trans, | |
754 | "Stopping tx queues that aren't allocated...\n"); | |
755 | return 0; | |
756 | } | |
757 | ||
758 | /* Unmap DMA from host system and free skb's */ | |
759 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
760 | txq_id++) | |
761 | iwl_pcie_txq_unmap(trans, txq_id); | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
766 | /* | |
767 | * iwl_trans_tx_free - Free TXQ Context | |
768 | * | |
769 | * Destroy all TX DMA queues and structures | |
770 | */ | |
771 | void iwl_pcie_tx_free(struct iwl_trans *trans) | |
772 | { | |
773 | int txq_id; | |
774 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
775 | ||
776 | /* Tx queues */ | |
777 | if (trans_pcie->txq) { | |
778 | for (txq_id = 0; | |
779 | txq_id < trans->cfg->base_params->num_of_queues; txq_id++) | |
780 | iwl_pcie_txq_free(trans, txq_id); | |
781 | } | |
782 | ||
783 | kfree(trans_pcie->txq); | |
784 | trans_pcie->txq = NULL; | |
785 | ||
786 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw); | |
787 | ||
788 | iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls); | |
789 | } | |
790 | ||
791 | /* | |
792 | * iwl_pcie_tx_alloc - allocate TX context | |
793 | * Allocate all Tx DMA structures and initialize them | |
794 | */ | |
795 | static int iwl_pcie_tx_alloc(struct iwl_trans *trans) | |
796 | { | |
797 | int ret; | |
798 | int txq_id, slots_num; | |
799 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
800 | ||
801 | u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues * | |
802 | sizeof(struct iwlagn_scd_bc_tbl); | |
803 | ||
804 | /*It is not allowed to alloc twice, so warn when this happens. | |
805 | * We cannot rely on the previous allocation, so free and fail */ | |
806 | if (WARN_ON(trans_pcie->txq)) { | |
807 | ret = -EINVAL; | |
808 | goto error; | |
809 | } | |
810 | ||
811 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls, | |
812 | scd_bc_tbls_size); | |
813 | if (ret) { | |
814 | IWL_ERR(trans, "Scheduler BC Table allocation failed\n"); | |
815 | goto error; | |
816 | } | |
817 | ||
818 | /* Alloc keep-warm buffer */ | |
819 | ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE); | |
820 | if (ret) { | |
821 | IWL_ERR(trans, "Keep Warm allocation failed\n"); | |
822 | goto error; | |
823 | } | |
824 | ||
825 | trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues, | |
826 | sizeof(struct iwl_txq), GFP_KERNEL); | |
827 | if (!trans_pcie->txq) { | |
828 | IWL_ERR(trans, "Not enough memory for txq\n"); | |
829 | ret = ENOMEM; | |
830 | goto error; | |
831 | } | |
832 | ||
833 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
834 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
835 | txq_id++) { | |
836 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
837 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
838 | ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id], | |
839 | slots_num, txq_id); | |
840 | if (ret) { | |
841 | IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id); | |
842 | goto error; | |
843 | } | |
844 | } | |
845 | ||
846 | return 0; | |
847 | ||
848 | error: | |
849 | iwl_pcie_tx_free(trans); | |
850 | ||
851 | return ret; | |
852 | } | |
853 | int iwl_pcie_tx_init(struct iwl_trans *trans) | |
854 | { | |
855 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
856 | int ret; | |
857 | int txq_id, slots_num; | |
858 | unsigned long flags; | |
859 | bool alloc = false; | |
860 | ||
861 | if (!trans_pcie->txq) { | |
862 | ret = iwl_pcie_tx_alloc(trans); | |
863 | if (ret) | |
864 | goto error; | |
865 | alloc = true; | |
866 | } | |
867 | ||
868 | spin_lock_irqsave(&trans_pcie->irq_lock, flags); | |
869 | ||
870 | /* Turn off all Tx DMA fifos */ | |
871 | iwl_write_prph(trans, SCD_TXFACT, 0); | |
872 | ||
873 | /* Tell NIC where to find the "keep warm" buffer */ | |
874 | iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG, | |
875 | trans_pcie->kw.dma >> 4); | |
876 | ||
877 | spin_unlock_irqrestore(&trans_pcie->irq_lock, flags); | |
878 | ||
879 | /* Alloc and init all Tx queues, including the command queue (#4/#9) */ | |
880 | for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues; | |
881 | txq_id++) { | |
882 | slots_num = (txq_id == trans_pcie->cmd_queue) ? | |
883 | TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; | |
884 | ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id], | |
885 | slots_num, txq_id); | |
886 | if (ret) { | |
887 | IWL_ERR(trans, "Tx %d queue init failed\n", txq_id); | |
888 | goto error; | |
889 | } | |
890 | } | |
891 | ||
892 | return 0; | |
893 | error: | |
894 | /*Upon error, free only if we allocated something */ | |
895 | if (alloc) | |
896 | iwl_pcie_tx_free(trans); | |
897 | return ret; | |
898 | } | |
899 | ||
900 | static inline void iwl_pcie_txq_progress(struct iwl_trans_pcie *trans_pcie, | |
901 | struct iwl_txq *txq) | |
902 | { | |
903 | if (!trans_pcie->wd_timeout) | |
904 | return; | |
905 | ||
906 | /* | |
907 | * if empty delete timer, otherwise move timer forward | |
908 | * since we're making progress on this queue | |
909 | */ | |
910 | if (txq->q.read_ptr == txq->q.write_ptr) | |
911 | del_timer(&txq->stuck_timer); | |
912 | else | |
913 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
914 | } | |
915 | ||
916 | /* Frees buffers until index _not_ inclusive */ | |
f6d497cd EG |
917 | void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, |
918 | struct sk_buff_head *skbs) | |
f02831be EG |
919 | { |
920 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); | |
921 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
f6d497cd EG |
922 | /* n_bd is usually 256 => n_bd - 1 = 0xff */ |
923 | int tfd_num = ssn & (txq->q.n_bd - 1); | |
f02831be EG |
924 | struct iwl_queue *q = &txq->q; |
925 | int last_to_free; | |
f02831be EG |
926 | |
927 | /* This function is not meant to release cmd queue*/ | |
928 | if (WARN_ON(txq_id == trans_pcie->cmd_queue)) | |
f6d497cd | 929 | return; |
214d14d4 | 930 | |
2bfb5092 | 931 | spin_lock_bh(&txq->lock); |
f6d497cd | 932 | |
b967613d EG |
933 | if (!txq->active) { |
934 | IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n", | |
935 | txq_id, ssn); | |
936 | goto out; | |
937 | } | |
938 | ||
f6d497cd EG |
939 | if (txq->q.read_ptr == tfd_num) |
940 | goto out; | |
941 | ||
942 | IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n", | |
943 | txq_id, txq->q.read_ptr, tfd_num, ssn); | |
214d14d4 | 944 | |
f02831be EG |
945 | /*Since we free until index _not_ inclusive, the one before index is |
946 | * the last we will free. This one must be used */ | |
f6d497cd | 947 | last_to_free = iwl_queue_dec_wrap(tfd_num, q->n_bd); |
f02831be | 948 | |
6ca6ebc1 | 949 | if (!iwl_queue_used(q, last_to_free)) { |
f02831be EG |
950 | IWL_ERR(trans, |
951 | "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n", | |
952 | __func__, txq_id, last_to_free, q->n_bd, | |
953 | q->write_ptr, q->read_ptr); | |
f6d497cd | 954 | goto out; |
214d14d4 JB |
955 | } |
956 | ||
f02831be | 957 | if (WARN_ON(!skb_queue_empty(skbs))) |
f6d497cd | 958 | goto out; |
214d14d4 | 959 | |
f02831be | 960 | for (; |
f6d497cd | 961 | q->read_ptr != tfd_num; |
f02831be | 962 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { |
214d14d4 | 963 | |
f02831be EG |
964 | if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL)) |
965 | continue; | |
214d14d4 | 966 | |
f02831be | 967 | __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb); |
214d14d4 | 968 | |
f02831be | 969 | txq->entries[txq->q.read_ptr].skb = NULL; |
fd4abac5 | 970 | |
f02831be | 971 | iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq); |
fd4abac5 | 972 | |
98891754 | 973 | iwl_pcie_txq_free_tfd(trans, txq); |
f02831be | 974 | } |
fd4abac5 | 975 | |
f02831be EG |
976 | iwl_pcie_txq_progress(trans_pcie, txq); |
977 | ||
f6d497cd EG |
978 | if (iwl_queue_space(&txq->q) > txq->q.low_mark) |
979 | iwl_wake_queue(trans, txq); | |
980 | out: | |
2bfb5092 | 981 | spin_unlock_bh(&txq->lock); |
1053d35f RR |
982 | } |
983 | ||
f02831be EG |
984 | /* |
985 | * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd | |
986 | * | |
987 | * When FW advances 'R' index, all entries between old and new 'R' index | |
988 | * need to be reclaimed. As result, some free space forms. If there is | |
989 | * enough free space (> low mark), wake the stack that feeds us. | |
990 | */ | |
991 | static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx) | |
48d42c42 | 992 | { |
f02831be EG |
993 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
994 | struct iwl_txq *txq = &trans_pcie->txq[txq_id]; | |
995 | struct iwl_queue *q = &txq->q; | |
996 | int nfreed = 0; | |
48d42c42 | 997 | |
f02831be | 998 | lockdep_assert_held(&txq->lock); |
48d42c42 | 999 | |
6ca6ebc1 | 1000 | if ((idx >= q->n_bd) || (!iwl_queue_used(q, idx))) { |
f02831be EG |
1001 | IWL_ERR(trans, |
1002 | "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n", | |
1003 | __func__, txq_id, idx, q->n_bd, | |
1004 | q->write_ptr, q->read_ptr); | |
1005 | return; | |
1006 | } | |
48d42c42 | 1007 | |
f02831be EG |
1008 | for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; |
1009 | q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { | |
48d42c42 | 1010 | |
f02831be EG |
1011 | if (nfreed++ > 0) { |
1012 | IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n", | |
1013 | idx, q->write_ptr, q->read_ptr); | |
1014 | iwl_op_mode_nic_error(trans->op_mode); | |
1015 | } | |
1016 | } | |
1017 | ||
1018 | iwl_pcie_txq_progress(trans_pcie, txq); | |
48d42c42 EG |
1019 | } |
1020 | ||
f02831be | 1021 | static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, |
1ce8658c | 1022 | u16 txq_id) |
48d42c42 | 1023 | { |
20d3b647 | 1024 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
48d42c42 EG |
1025 | u32 tbl_dw_addr; |
1026 | u32 tbl_dw; | |
1027 | u16 scd_q2ratid; | |
1028 | ||
1029 | scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK; | |
1030 | ||
105183b1 | 1031 | tbl_dw_addr = trans_pcie->scd_base_addr + |
48d42c42 EG |
1032 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1033 | ||
4fd442db | 1034 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
48d42c42 EG |
1035 | |
1036 | if (txq_id & 0x1) | |
1037 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | |
1038 | else | |
1039 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | |
1040 | ||
4fd442db | 1041 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
48d42c42 EG |
1042 | |
1043 | return 0; | |
1044 | } | |
1045 | ||
f02831be EG |
1046 | static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans, |
1047 | u16 txq_id) | |
48d42c42 EG |
1048 | { |
1049 | /* Simply stop the queue, but don't change any configuration; | |
1050 | * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ | |
1042db2a | 1051 | iwl_write_prph(trans, |
48d42c42 EG |
1052 | SCD_QUEUE_STATUS_BITS(txq_id), |
1053 | (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| | |
1054 | (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); | |
1055 | } | |
1056 | ||
bd5f6a34 EG |
1057 | /* Receiver address (actually, Rx station's index into station table), |
1058 | * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */ | |
1059 | #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid)) | |
1060 | ||
f02831be EG |
1061 | void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, |
1062 | int sta_id, int tid, int frame_limit, u16 ssn) | |
48d42c42 | 1063 | { |
9eae88fa | 1064 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
4beaf6c2 | 1065 | |
9eae88fa JB |
1066 | if (test_and_set_bit(txq_id, trans_pcie->queue_used)) |
1067 | WARN_ONCE(1, "queue %d already used - expect issues", txq_id); | |
48d42c42 | 1068 | |
48d42c42 | 1069 | /* Stop this Tx queue before configuring it */ |
f02831be | 1070 | iwl_pcie_txq_set_inactive(trans, txq_id); |
48d42c42 | 1071 | |
4beaf6c2 EG |
1072 | /* Set this queue as a chain-building queue unless it is CMD queue */ |
1073 | if (txq_id != trans_pcie->cmd_queue) | |
1074 | iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id)); | |
1075 | ||
1076 | /* If this queue is mapped to a certain station: it is an AGG queue */ | |
881acd89 | 1077 | if (sta_id >= 0) { |
4beaf6c2 | 1078 | u16 ra_tid = BUILD_RAxTID(sta_id, tid); |
48d42c42 | 1079 | |
4beaf6c2 | 1080 | /* Map receiver-address / traffic-ID to this queue */ |
f02831be | 1081 | iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id); |
48d42c42 | 1082 | |
4beaf6c2 EG |
1083 | /* enable aggregations for the queue */ |
1084 | iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
68972c46 | 1085 | trans_pcie->txq[txq_id].ampdu = true; |
1ce8658c EG |
1086 | } else { |
1087 | /* | |
1088 | * disable aggregations for the queue, this will also make the | |
1089 | * ra_tid mapping configuration irrelevant since it is now a | |
1090 | * non-AGG queue. | |
1091 | */ | |
1092 | iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id)); | |
4beaf6c2 | 1093 | } |
48d42c42 EG |
1094 | |
1095 | /* Place first TFD at index corresponding to start sequence number. | |
1096 | * Assumes that ssn_idx is valid (!= 0xFFF) */ | |
822e8b2a EG |
1097 | trans_pcie->txq[txq_id].q.read_ptr = (ssn & 0xff); |
1098 | trans_pcie->txq[txq_id].q.write_ptr = (ssn & 0xff); | |
1ce8658c EG |
1099 | |
1100 | iwl_write_direct32(trans, HBUS_TARG_WRPTR, | |
1101 | (ssn & 0xff) | (txq_id << 8)); | |
1102 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | |
48d42c42 EG |
1103 | |
1104 | /* Set up Tx window size and frame limit for this queue */ | |
4fd442db | 1105 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
4beaf6c2 | 1106 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); |
4fd442db | 1107 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
9eae88fa JB |
1108 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1109 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | |
1110 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | |
1111 | ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & | |
1112 | SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK)); | |
48d42c42 | 1113 | |
48d42c42 | 1114 | /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ |
1ce8658c EG |
1115 | iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id), |
1116 | (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) | | |
1117 | (fifo << SCD_QUEUE_STTS_REG_POS_TXF) | | |
1118 | (1 << SCD_QUEUE_STTS_REG_POS_WSL) | | |
1119 | SCD_QUEUE_STTS_REG_MSK); | |
b967613d | 1120 | trans_pcie->txq[txq_id].active = true; |
1ce8658c EG |
1121 | IWL_DEBUG_TX_QUEUES(trans, "Activate queue %d on FIFO %d WrPtr: %d\n", |
1122 | txq_id, fifo, ssn & 0xff); | |
4beaf6c2 EG |
1123 | } |
1124 | ||
f02831be | 1125 | void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id) |
288712a6 | 1126 | { |
8ad71bef | 1127 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
986ea6c9 EG |
1128 | u32 stts_addr = trans_pcie->scd_base_addr + |
1129 | SCD_TX_STTS_QUEUE_OFFSET(txq_id); | |
1130 | static const u32 zero_val[4] = {}; | |
288712a6 | 1131 | |
9eae88fa JB |
1132 | if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) { |
1133 | WARN_ONCE(1, "queue %d not used", txq_id); | |
1134 | return; | |
48d42c42 EG |
1135 | } |
1136 | ||
f02831be | 1137 | iwl_pcie_txq_set_inactive(trans, txq_id); |
ac928f8d | 1138 | |
4fd442db EG |
1139 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1140 | ARRAY_SIZE(zero_val)); | |
986ea6c9 | 1141 | |
990aa6d7 | 1142 | iwl_pcie_txq_unmap(trans, txq_id); |
68972c46 | 1143 | trans_pcie->txq[txq_id].ampdu = false; |
6c3fd3f0 | 1144 | |
1ce8658c | 1145 | IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id); |
48d42c42 EG |
1146 | } |
1147 | ||
fd4abac5 TW |
1148 | /*************** HOST COMMAND QUEUE FUNCTIONS *****/ |
1149 | ||
990aa6d7 | 1150 | /* |
f02831be | 1151 | * iwl_pcie_enqueue_hcmd - enqueue a uCode command |
fd4abac5 | 1152 | * @priv: device private data point |
e89044d7 | 1153 | * @cmd: a pointer to the ucode command structure |
fd4abac5 | 1154 | * |
e89044d7 EP |
1155 | * The function returns < 0 values to indicate the operation |
1156 | * failed. On success, it returns the index (>= 0) of command in the | |
fd4abac5 TW |
1157 | * command queue. |
1158 | */ | |
f02831be EG |
1159 | static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, |
1160 | struct iwl_host_cmd *cmd) | |
fd4abac5 | 1161 | { |
8ad71bef | 1162 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1163 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
fd4abac5 | 1164 | struct iwl_queue *q = &txq->q; |
c2acea8e JB |
1165 | struct iwl_device_cmd *out_cmd; |
1166 | struct iwl_cmd_meta *out_meta; | |
f4feb8ac | 1167 | void *dup_buf = NULL; |
fd4abac5 | 1168 | dma_addr_t phys_addr; |
f4feb8ac | 1169 | int idx; |
38c0f334 | 1170 | u16 copy_size, cmd_size, scratch_size; |
4ce7cc2b JB |
1171 | bool had_nocopy = false; |
1172 | int i; | |
96791422 | 1173 | u32 cmd_pos; |
1afbfb60 JB |
1174 | const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD]; |
1175 | u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD]; | |
fd4abac5 | 1176 | |
4ce7cc2b JB |
1177 | copy_size = sizeof(out_cmd->hdr); |
1178 | cmd_size = sizeof(out_cmd->hdr); | |
1179 | ||
1180 | /* need one for the header if the first is NOCOPY */ | |
1afbfb60 | 1181 | BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1); |
4ce7cc2b | 1182 | |
1afbfb60 | 1183 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1184 | cmddata[i] = cmd->data[i]; |
1185 | cmdlen[i] = cmd->len[i]; | |
1186 | ||
4ce7cc2b JB |
1187 | if (!cmd->len[i]) |
1188 | continue; | |
8a964f44 | 1189 | |
38c0f334 JB |
1190 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1191 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1192 | int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1193 | |
1194 | if (copy > cmdlen[i]) | |
1195 | copy = cmdlen[i]; | |
1196 | cmdlen[i] -= copy; | |
1197 | cmddata[i] += copy; | |
1198 | copy_size += copy; | |
1199 | } | |
1200 | ||
4ce7cc2b JB |
1201 | if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) { |
1202 | had_nocopy = true; | |
f4feb8ac JB |
1203 | if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) { |
1204 | idx = -EINVAL; | |
1205 | goto free_dup_buf; | |
1206 | } | |
1207 | } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) { | |
1208 | /* | |
1209 | * This is also a chunk that isn't copied | |
1210 | * to the static buffer so set had_nocopy. | |
1211 | */ | |
1212 | had_nocopy = true; | |
1213 | ||
1214 | /* only allowed once */ | |
1215 | if (WARN_ON(dup_buf)) { | |
1216 | idx = -EINVAL; | |
1217 | goto free_dup_buf; | |
1218 | } | |
1219 | ||
8a964f44 | 1220 | dup_buf = kmemdup(cmddata[i], cmdlen[i], |
f4feb8ac JB |
1221 | GFP_ATOMIC); |
1222 | if (!dup_buf) | |
1223 | return -ENOMEM; | |
4ce7cc2b JB |
1224 | } else { |
1225 | /* NOCOPY must not be followed by normal! */ | |
f4feb8ac JB |
1226 | if (WARN_ON(had_nocopy)) { |
1227 | idx = -EINVAL; | |
1228 | goto free_dup_buf; | |
1229 | } | |
8a964f44 | 1230 | copy_size += cmdlen[i]; |
4ce7cc2b JB |
1231 | } |
1232 | cmd_size += cmd->len[i]; | |
1233 | } | |
fd4abac5 | 1234 | |
3e41ace5 JB |
1235 | /* |
1236 | * If any of the command structures end up being larger than | |
4ce7cc2b JB |
1237 | * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically |
1238 | * allocated into separate TFDs, then we will need to | |
1239 | * increase the size of the buffers. | |
3e41ace5 | 1240 | */ |
2a79e45e JB |
1241 | if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE, |
1242 | "Command %s (%#x) is too large (%d bytes)\n", | |
990aa6d7 | 1243 | get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) { |
f4feb8ac JB |
1244 | idx = -EINVAL; |
1245 | goto free_dup_buf; | |
1246 | } | |
fd4abac5 | 1247 | |
015c15e1 | 1248 | spin_lock_bh(&txq->lock); |
3598e177 | 1249 | |
c2acea8e | 1250 | if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) { |
015c15e1 | 1251 | spin_unlock_bh(&txq->lock); |
3598e177 | 1252 | |
6d8f6eeb | 1253 | IWL_ERR(trans, "No space in command queue\n"); |
0e781842 | 1254 | iwl_op_mode_cmd_queue_full(trans->op_mode); |
f4feb8ac JB |
1255 | idx = -ENOSPC; |
1256 | goto free_dup_buf; | |
fd4abac5 TW |
1257 | } |
1258 | ||
4ce7cc2b | 1259 | idx = get_cmd_index(q, q->write_ptr); |
bf8440e6 JB |
1260 | out_cmd = txq->entries[idx].cmd; |
1261 | out_meta = &txq->entries[idx].meta; | |
c2acea8e | 1262 | |
8ce73f3a | 1263 | memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */ |
c2acea8e JB |
1264 | if (cmd->flags & CMD_WANT_SKB) |
1265 | out_meta->source = cmd; | |
fd4abac5 | 1266 | |
4ce7cc2b | 1267 | /* set up the header */ |
fd4abac5 | 1268 | |
4ce7cc2b | 1269 | out_cmd->hdr.cmd = cmd->id; |
fd4abac5 | 1270 | out_cmd->hdr.flags = 0; |
cefeaa5f | 1271 | out_cmd->hdr.sequence = |
c6f600fc | 1272 | cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) | |
cefeaa5f | 1273 | INDEX_TO_SEQ(q->write_ptr)); |
4ce7cc2b JB |
1274 | |
1275 | /* and copy the data that needs to be copied */ | |
96791422 | 1276 | cmd_pos = offsetof(struct iwl_device_cmd, payload); |
8a964f44 | 1277 | copy_size = sizeof(out_cmd->hdr); |
1afbfb60 | 1278 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 JB |
1279 | int copy = 0; |
1280 | ||
cc904c71 | 1281 | if (!cmd->len[i]) |
4ce7cc2b | 1282 | continue; |
8a964f44 | 1283 | |
38c0f334 JB |
1284 | /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */ |
1285 | if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) { | |
1286 | copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size; | |
8a964f44 JB |
1287 | |
1288 | if (copy > cmd->len[i]) | |
1289 | copy = cmd->len[i]; | |
1290 | } | |
1291 | ||
1292 | /* copy everything if not nocopy/dup */ | |
1293 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | | |
1294 | IWL_HCMD_DFL_DUP))) | |
1295 | copy = cmd->len[i]; | |
1296 | ||
1297 | if (copy) { | |
1298 | memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy); | |
1299 | cmd_pos += copy; | |
1300 | copy_size += copy; | |
1301 | } | |
96791422 EG |
1302 | } |
1303 | ||
d9fb6465 | 1304 | IWL_DEBUG_HC(trans, |
20d3b647 | 1305 | "Sending command %s (#%x), seq: 0x%04X, %d bytes at %d[%d]:%d\n", |
990aa6d7 | 1306 | get_cmd_string(trans_pcie, out_cmd->hdr.cmd), |
20d3b647 JB |
1307 | out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence), |
1308 | cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue); | |
4ce7cc2b | 1309 | |
38c0f334 JB |
1310 | /* start the TFD with the scratchbuf */ |
1311 | scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE); | |
1312 | memcpy(&txq->scratchbufs[q->write_ptr], &out_cmd->hdr, scratch_size); | |
1313 | iwl_pcie_txq_build_tfd(trans, txq, | |
1314 | iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr), | |
1315 | scratch_size, 1); | |
1316 | ||
1317 | /* map first command fragment, if any remains */ | |
1318 | if (copy_size > scratch_size) { | |
1319 | phys_addr = dma_map_single(trans->dev, | |
1320 | ((u8 *)&out_cmd->hdr) + scratch_size, | |
1321 | copy_size - scratch_size, | |
1322 | DMA_TO_DEVICE); | |
1323 | if (dma_mapping_error(trans->dev, phys_addr)) { | |
1324 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1325 | &txq->tfds[q->write_ptr]); | |
1326 | idx = -ENOMEM; | |
1327 | goto out; | |
1328 | } | |
8a964f44 | 1329 | |
38c0f334 JB |
1330 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, |
1331 | copy_size - scratch_size, 0); | |
2c46f72e JB |
1332 | } |
1333 | ||
8a964f44 | 1334 | /* map the remaining (adjusted) nocopy/dup fragments */ |
1afbfb60 | 1335 | for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) { |
8a964f44 | 1336 | const void *data = cmddata[i]; |
f4feb8ac | 1337 | |
8a964f44 | 1338 | if (!cmdlen[i]) |
4ce7cc2b | 1339 | continue; |
f4feb8ac JB |
1340 | if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY | |
1341 | IWL_HCMD_DFL_DUP))) | |
4ce7cc2b | 1342 | continue; |
f4feb8ac JB |
1343 | if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) |
1344 | data = dup_buf; | |
1345 | phys_addr = dma_map_single(trans->dev, (void *)data, | |
98891754 | 1346 | cmdlen[i], DMA_TO_DEVICE); |
1042db2a | 1347 | if (dma_mapping_error(trans->dev, phys_addr)) { |
f02831be | 1348 | iwl_pcie_tfd_unmap(trans, out_meta, |
98891754 | 1349 | &txq->tfds[q->write_ptr]); |
4ce7cc2b JB |
1350 | idx = -ENOMEM; |
1351 | goto out; | |
1352 | } | |
1353 | ||
8a964f44 | 1354 | iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], 0); |
4ce7cc2b | 1355 | } |
df833b1d | 1356 | |
afaf6b57 | 1357 | out_meta->flags = cmd->flags; |
f4feb8ac JB |
1358 | if (WARN_ON_ONCE(txq->entries[idx].free_buf)) |
1359 | kfree(txq->entries[idx].free_buf); | |
1360 | txq->entries[idx].free_buf = dup_buf; | |
2c46f72e JB |
1361 | |
1362 | txq->need_update = 1; | |
1363 | ||
8a964f44 | 1364 | trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr); |
df833b1d | 1365 | |
7c5ba4a8 JB |
1366 | /* start timer if queue currently empty */ |
1367 | if (q->read_ptr == q->write_ptr && trans_pcie->wd_timeout) | |
1368 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1369 | ||
fd4abac5 TW |
1370 | /* Increment and update queue's write index */ |
1371 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
990aa6d7 | 1372 | iwl_pcie_txq_inc_wr_ptr(trans, txq); |
fd4abac5 | 1373 | |
2c46f72e | 1374 | out: |
015c15e1 | 1375 | spin_unlock_bh(&txq->lock); |
f4feb8ac JB |
1376 | free_dup_buf: |
1377 | if (idx < 0) | |
1378 | kfree(dup_buf); | |
7bfedc59 | 1379 | return idx; |
fd4abac5 TW |
1380 | } |
1381 | ||
990aa6d7 EG |
1382 | /* |
1383 | * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them | |
17b88929 | 1384 | * @rxb: Rx buffer to reclaim |
247c61d6 EG |
1385 | * @handler_status: return value of the handler of the command |
1386 | * (put in setup_rx_handlers) | |
17b88929 TW |
1387 | * |
1388 | * If an Rx buffer has an async callback associated with it the callback | |
1389 | * will be executed. The attached skb (if present) will only be freed | |
1390 | * if the callback returns 1 | |
1391 | */ | |
990aa6d7 EG |
1392 | void iwl_pcie_hcmd_complete(struct iwl_trans *trans, |
1393 | struct iwl_rx_cmd_buffer *rxb, int handler_status) | |
17b88929 | 1394 | { |
2f301227 | 1395 | struct iwl_rx_packet *pkt = rxb_addr(rxb); |
17b88929 TW |
1396 | u16 sequence = le16_to_cpu(pkt->hdr.sequence); |
1397 | int txq_id = SEQ_TO_QUEUE(sequence); | |
1398 | int index = SEQ_TO_INDEX(sequence); | |
17b88929 | 1399 | int cmd_index; |
c2acea8e JB |
1400 | struct iwl_device_cmd *cmd; |
1401 | struct iwl_cmd_meta *meta; | |
8ad71bef | 1402 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
990aa6d7 | 1403 | struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue]; |
17b88929 TW |
1404 | |
1405 | /* If a Tx command is being handled and it isn't in the actual | |
1406 | * command queue then there a command routing bug has been introduced | |
1407 | * in the queue management code. */ | |
c6f600fc | 1408 | if (WARN(txq_id != trans_pcie->cmd_queue, |
13bb9483 | 1409 | "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n", |
20d3b647 JB |
1410 | txq_id, trans_pcie->cmd_queue, sequence, |
1411 | trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr, | |
1412 | trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) { | |
3e10caeb | 1413 | iwl_print_hex_error(trans, pkt, 32); |
55d6a3cd | 1414 | return; |
01ef9323 | 1415 | } |
17b88929 | 1416 | |
2bfb5092 | 1417 | spin_lock_bh(&txq->lock); |
015c15e1 | 1418 | |
4ce7cc2b | 1419 | cmd_index = get_cmd_index(&txq->q, index); |
bf8440e6 JB |
1420 | cmd = txq->entries[cmd_index].cmd; |
1421 | meta = &txq->entries[cmd_index].meta; | |
17b88929 | 1422 | |
98891754 | 1423 | iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]); |
c33de625 | 1424 | |
17b88929 | 1425 | /* Input error checking is done when commands are added to queue. */ |
c2acea8e | 1426 | if (meta->flags & CMD_WANT_SKB) { |
48a2d66f | 1427 | struct page *p = rxb_steal_page(rxb); |
65b94a4a | 1428 | |
65b94a4a JB |
1429 | meta->source->resp_pkt = pkt; |
1430 | meta->source->_rx_page_addr = (unsigned long)page_address(p); | |
b2cf410c | 1431 | meta->source->_rx_page_order = trans_pcie->rx_page_order; |
247c61d6 | 1432 | meta->source->handler_status = handler_status; |
247c61d6 | 1433 | } |
2624e96c | 1434 | |
f02831be | 1435 | iwl_pcie_cmdq_reclaim(trans, txq_id, index); |
17b88929 | 1436 | |
c2acea8e | 1437 | if (!(meta->flags & CMD_ASYNC)) { |
74fda971 | 1438 | if (!test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
05c89b91 WYG |
1439 | IWL_WARN(trans, |
1440 | "HCMD_ACTIVE already clear for command %s\n", | |
990aa6d7 | 1441 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
05c89b91 | 1442 | } |
74fda971 | 1443 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
6d8f6eeb | 1444 | IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1445 | get_cmd_string(trans_pcie, cmd->hdr.cmd)); |
f946b529 | 1446 | wake_up(&trans_pcie->wait_command_queue); |
17b88929 | 1447 | } |
3598e177 | 1448 | |
dd487449 | 1449 | meta->flags = 0; |
3598e177 | 1450 | |
2bfb5092 | 1451 | spin_unlock_bh(&txq->lock); |
17b88929 | 1452 | } |
253a634c | 1453 | |
253a634c EG |
1454 | #define HOST_COMPLETE_TIMEOUT (2 * HZ) |
1455 | ||
f02831be EG |
1456 | static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans, |
1457 | struct iwl_host_cmd *cmd) | |
253a634c | 1458 | { |
d9fb6465 | 1459 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1460 | int ret; |
1461 | ||
1462 | /* An asynchronous command can not expect an SKB to be set. */ | |
1463 | if (WARN_ON(cmd->flags & CMD_WANT_SKB)) | |
1464 | return -EINVAL; | |
1465 | ||
f02831be | 1466 | ret = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c | 1467 | if (ret < 0) { |
721c32f7 | 1468 | IWL_ERR(trans, |
b36b110c | 1469 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1470 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1471 | return ret; |
1472 | } | |
1473 | return 0; | |
1474 | } | |
1475 | ||
f02831be EG |
1476 | static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans, |
1477 | struct iwl_host_cmd *cmd) | |
253a634c | 1478 | { |
8ad71bef | 1479 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
253a634c EG |
1480 | int cmd_idx; |
1481 | int ret; | |
1482 | ||
6d8f6eeb | 1483 | IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n", |
990aa6d7 | 1484 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1485 | |
2cc39c94 | 1486 | if (WARN_ON(test_and_set_bit(STATUS_HCMD_ACTIVE, |
74fda971 | 1487 | &trans_pcie->status))) { |
2cc39c94 | 1488 | IWL_ERR(trans, "Command %s: a command is already active!\n", |
990aa6d7 | 1489 | get_cmd_string(trans_pcie, cmd->id)); |
2cc39c94 JB |
1490 | return -EIO; |
1491 | } | |
1492 | ||
6d8f6eeb | 1493 | IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n", |
990aa6d7 | 1494 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c | 1495 | |
f02831be | 1496 | cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd); |
253a634c EG |
1497 | if (cmd_idx < 0) { |
1498 | ret = cmd_idx; | |
74fda971 | 1499 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
721c32f7 | 1500 | IWL_ERR(trans, |
b36b110c | 1501 | "Error sending %s: enqueue_hcmd failed: %d\n", |
990aa6d7 | 1502 | get_cmd_string(trans_pcie, cmd->id), ret); |
253a634c EG |
1503 | return ret; |
1504 | } | |
1505 | ||
f946b529 | 1506 | ret = wait_event_timeout(trans_pcie->wait_command_queue, |
20d3b647 JB |
1507 | !test_bit(STATUS_HCMD_ACTIVE, |
1508 | &trans_pcie->status), | |
1509 | HOST_COMPLETE_TIMEOUT); | |
253a634c | 1510 | if (!ret) { |
74fda971 | 1511 | if (test_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status)) { |
990aa6d7 | 1512 | struct iwl_txq *txq = |
c6f600fc | 1513 | &trans_pcie->txq[trans_pcie->cmd_queue]; |
d10630af WYG |
1514 | struct iwl_queue *q = &txq->q; |
1515 | ||
721c32f7 | 1516 | IWL_ERR(trans, |
253a634c | 1517 | "Error sending %s: time out after %dms.\n", |
990aa6d7 | 1518 | get_cmd_string(trans_pcie, cmd->id), |
253a634c EG |
1519 | jiffies_to_msecs(HOST_COMPLETE_TIMEOUT)); |
1520 | ||
721c32f7 | 1521 | IWL_ERR(trans, |
d10630af WYG |
1522 | "Current CMD queue read_ptr %d write_ptr %d\n", |
1523 | q->read_ptr, q->write_ptr); | |
1524 | ||
74fda971 | 1525 | clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status); |
d9fb6465 JB |
1526 | IWL_DEBUG_INFO(trans, |
1527 | "Clearing HCMD_ACTIVE for command %s\n", | |
990aa6d7 | 1528 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1529 | ret = -ETIMEDOUT; |
1530 | goto cancel; | |
1531 | } | |
1532 | } | |
1533 | ||
d18aa87f JB |
1534 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) { |
1535 | IWL_ERR(trans, "FW error in SYNC CMD %s\n", | |
990aa6d7 | 1536 | get_cmd_string(trans_pcie, cmd->id)); |
b656fa33 | 1537 | dump_stack(); |
d18aa87f JB |
1538 | ret = -EIO; |
1539 | goto cancel; | |
1540 | } | |
1541 | ||
1094fa26 EH |
1542 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
1543 | test_bit(STATUS_RFKILL, &trans_pcie->status)) { | |
f946b529 EG |
1544 | IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n"); |
1545 | ret = -ERFKILL; | |
1546 | goto cancel; | |
1547 | } | |
1548 | ||
65b94a4a | 1549 | if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) { |
6d8f6eeb | 1550 | IWL_ERR(trans, "Error: Response NULL in '%s'\n", |
990aa6d7 | 1551 | get_cmd_string(trans_pcie, cmd->id)); |
253a634c EG |
1552 | ret = -EIO; |
1553 | goto cancel; | |
1554 | } | |
1555 | ||
1556 | return 0; | |
1557 | ||
1558 | cancel: | |
1559 | if (cmd->flags & CMD_WANT_SKB) { | |
1560 | /* | |
1561 | * Cancel the CMD_WANT_SKB flag for the cmd in the | |
1562 | * TX cmd queue. Otherwise in case the cmd comes | |
1563 | * in later, it will possibly set an invalid | |
1564 | * address (cmd->meta.source). | |
1565 | */ | |
bf8440e6 JB |
1566 | trans_pcie->txq[trans_pcie->cmd_queue]. |
1567 | entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB; | |
253a634c | 1568 | } |
9cac4943 | 1569 | |
65b94a4a JB |
1570 | if (cmd->resp_pkt) { |
1571 | iwl_free_resp(cmd); | |
1572 | cmd->resp_pkt = NULL; | |
253a634c EG |
1573 | } |
1574 | ||
1575 | return ret; | |
1576 | } | |
1577 | ||
f02831be | 1578 | int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd) |
253a634c | 1579 | { |
f946b529 EG |
1580 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
1581 | ||
d18aa87f JB |
1582 | if (test_bit(STATUS_FW_ERROR, &trans_pcie->status)) |
1583 | return -EIO; | |
1584 | ||
4f59334b EH |
1585 | if (!(cmd->flags & CMD_SEND_IN_RFKILL) && |
1586 | test_bit(STATUS_RFKILL, &trans_pcie->status)) { | |
754d7d9e EG |
1587 | IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n", |
1588 | cmd->id); | |
f946b529 | 1589 | return -ERFKILL; |
754d7d9e | 1590 | } |
f946b529 | 1591 | |
253a634c | 1592 | if (cmd->flags & CMD_ASYNC) |
f02831be | 1593 | return iwl_pcie_send_hcmd_async(trans, cmd); |
253a634c | 1594 | |
f946b529 | 1595 | /* We still can fail on RFKILL that can be asserted while we wait */ |
f02831be | 1596 | return iwl_pcie_send_hcmd_sync(trans, cmd); |
253a634c EG |
1597 | } |
1598 | ||
f02831be EG |
1599 | int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, |
1600 | struct iwl_device_cmd *dev_cmd, int txq_id) | |
a0eaad71 | 1601 | { |
8ad71bef | 1602 | struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
f02831be EG |
1603 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
1604 | struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload; | |
1605 | struct iwl_cmd_meta *out_meta; | |
1606 | struct iwl_txq *txq; | |
1607 | struct iwl_queue *q; | |
38c0f334 JB |
1608 | dma_addr_t tb0_phys, tb1_phys, scratch_phys; |
1609 | void *tb1_addr; | |
1610 | u16 len, tb1_len, tb2_len; | |
f02831be EG |
1611 | u8 wait_write_ptr = 0; |
1612 | __le16 fc = hdr->frame_control; | |
1613 | u8 hdr_len = ieee80211_hdrlen(fc); | |
68972c46 | 1614 | u16 wifi_seq; |
f02831be EG |
1615 | |
1616 | txq = &trans_pcie->txq[txq_id]; | |
1617 | q = &txq->q; | |
a0eaad71 | 1618 | |
961de6a5 JB |
1619 | if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used), |
1620 | "TX on unused queue %d\n", txq_id)) | |
f02831be | 1621 | return -EINVAL; |
39644e9a | 1622 | |
f02831be | 1623 | spin_lock(&txq->lock); |
015c15e1 | 1624 | |
f02831be EG |
1625 | /* In AGG mode, the index in the ring must correspond to the WiFi |
1626 | * sequence number. This is a HW requirements to help the SCD to parse | |
1627 | * the BA. | |
1628 | * Check here that the packets are in the right place on the ring. | |
1629 | */ | |
9a886586 | 1630 | wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
1092b9bc | 1631 | WARN_ONCE(txq->ampdu && |
68972c46 | 1632 | (wifi_seq & 0xff) != q->write_ptr, |
f02831be EG |
1633 | "Q: %d WiFi Seq %d tfdNum %d", |
1634 | txq_id, wifi_seq, q->write_ptr); | |
f02831be EG |
1635 | |
1636 | /* Set up driver data for this TFD */ | |
1637 | txq->entries[q->write_ptr].skb = skb; | |
1638 | txq->entries[q->write_ptr].cmd = dev_cmd; | |
1639 | ||
1640 | dev_cmd->hdr.cmd = REPLY_TX; | |
1641 | dev_cmd->hdr.sequence = | |
1642 | cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) | | |
1643 | INDEX_TO_SEQ(q->write_ptr))); | |
1644 | ||
38c0f334 JB |
1645 | tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr); |
1646 | scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) + | |
1647 | offsetof(struct iwl_tx_cmd, scratch); | |
1648 | ||
1649 | tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); | |
1650 | tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys); | |
1651 | ||
f02831be EG |
1652 | /* Set up first empty entry in queue's array of Tx/cmd buffers */ |
1653 | out_meta = &txq->entries[q->write_ptr].meta; | |
a0eaad71 | 1654 | |
f02831be | 1655 | /* |
38c0f334 JB |
1656 | * The second TB (tb1) points to the remainder of the TX command |
1657 | * and the 802.11 header - dword aligned size | |
1658 | * (This calculation modifies the TX command, so do it before the | |
1659 | * setup of the first TB) | |
f02831be | 1660 | */ |
38c0f334 JB |
1661 | len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) + |
1662 | hdr_len - IWL_HCMD_SCRATCHBUF_SIZE; | |
1092b9bc | 1663 | tb1_len = ALIGN(len, 4); |
f02831be EG |
1664 | |
1665 | /* Tell NIC about any 2-byte padding after MAC header */ | |
38c0f334 | 1666 | if (tb1_len != len) |
f02831be EG |
1667 | tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; |
1668 | ||
38c0f334 JB |
1669 | /* The first TB points to the scratchbuf data - min_copy bytes */ |
1670 | memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr, | |
1671 | IWL_HCMD_SCRATCHBUF_SIZE); | |
1672 | iwl_pcie_txq_build_tfd(trans, txq, tb0_phys, | |
1673 | IWL_HCMD_SCRATCHBUF_SIZE, 1); | |
f02831be | 1674 | |
38c0f334 JB |
1675 | /* there must be data left over for TB1 or this code must be changed */ |
1676 | BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE); | |
1677 | ||
1678 | /* map the data for TB1 */ | |
1679 | tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE; | |
1680 | tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE); | |
1681 | if (unlikely(dma_mapping_error(trans->dev, tb1_phys))) | |
1682 | goto out_err; | |
1683 | iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, 0); | |
a0eaad71 | 1684 | |
38c0f334 JB |
1685 | /* |
1686 | * Set up TFD's third entry to point directly to remainder | |
1687 | * of skb, if any (802.11 null frames have no payload). | |
1688 | */ | |
1689 | tb2_len = skb->len - hdr_len; | |
1690 | if (tb2_len > 0) { | |
1691 | dma_addr_t tb2_phys = dma_map_single(trans->dev, | |
1692 | skb->data + hdr_len, | |
1693 | tb2_len, DMA_TO_DEVICE); | |
1694 | if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) { | |
1695 | iwl_pcie_tfd_unmap(trans, out_meta, | |
1696 | &txq->tfds[q->write_ptr]); | |
f02831be EG |
1697 | goto out_err; |
1698 | } | |
38c0f334 | 1699 | iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, 0); |
f02831be | 1700 | } |
a0eaad71 | 1701 | |
f02831be EG |
1702 | /* Set up entry for this TFD in Tx byte-count array */ |
1703 | iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len)); | |
a0eaad71 | 1704 | |
f02831be EG |
1705 | trace_iwlwifi_dev_tx(trans->dev, skb, |
1706 | &txq->tfds[txq->q.write_ptr], | |
1707 | sizeof(struct iwl_tfd), | |
38c0f334 JB |
1708 | &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len, |
1709 | skb->data + hdr_len, tb2_len); | |
f02831be | 1710 | trace_iwlwifi_dev_tx_data(trans->dev, skb, |
38c0f334 JB |
1711 | skb->data + hdr_len, tb2_len); |
1712 | ||
1713 | if (!ieee80211_has_morefrags(fc)) { | |
1714 | txq->need_update = 1; | |
1715 | } else { | |
1716 | wait_write_ptr = 1; | |
1717 | txq->need_update = 0; | |
1718 | } | |
7c5ba4a8 | 1719 | |
f02831be EG |
1720 | /* start timer if queue currently empty */ |
1721 | if (txq->need_update && q->read_ptr == q->write_ptr && | |
1722 | trans_pcie->wd_timeout) | |
1723 | mod_timer(&txq->stuck_timer, jiffies + trans_pcie->wd_timeout); | |
1724 | ||
1725 | /* Tell device the write index *just past* this latest filled TFD */ | |
1726 | q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd); | |
1727 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1728 | ||
1729 | /* | |
1730 | * At this point the frame is "transmitted" successfully | |
1731 | * and we will get a TX status notification eventually, | |
1732 | * regardless of the value of ret. "ret" only indicates | |
1733 | * whether or not we should update the write pointer. | |
1734 | */ | |
1735 | if (iwl_queue_space(q) < q->high_mark) { | |
1736 | if (wait_write_ptr) { | |
1737 | txq->need_update = 1; | |
1738 | iwl_pcie_txq_inc_wr_ptr(trans, txq); | |
1739 | } else { | |
1740 | iwl_stop_queue(trans, txq); | |
1741 | } | |
1742 | } | |
1743 | spin_unlock(&txq->lock); | |
1744 | return 0; | |
1745 | out_err: | |
1746 | spin_unlock(&txq->lock); | |
1747 | return -1; | |
a0eaad71 | 1748 | } |