[deliverable/linux.git] / drivers / net / wireless / marvell / mwifiex / pcie.h

/* @file mwifiex_pcie.h
 *
 * @brief This file contains definitions for PCI-E interface.
 * driver.
 *
 * Copyright (C) 2011-2014, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_PCIE_H
#define	_MWIFIEX_PCIE_H

#include    <linux/pci.h>
#include    <linux/pcieport_if.h>
#include    <linux/interrupt.h>

#include    "decl.h"
#include    "main.h"

#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
#define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
#define PCIE8997_DEFAULT_FW_NAME "mrvl/pcie8997_uapsta.bin"

#define PCIE_VENDOR_ID_MARVELL              (0x11ab)
#define PCIE_DEVICE_ID_MARVELL_88W8766P		(0x2b30)
#define PCIE_DEVICE_ID_MARVELL_88W8897		(0x2b38)
#define PCIE_DEVICE_ID_MARVELL_88W8997		(0x2b42)

/* Constants for Buffer Descriptor (BD) rings */
#define MWIFIEX_MAX_TXRX_BD			0x20
#define MWIFIEX_TXBD_MASK			0x3F
#define MWIFIEX_RXBD_MASK			0x3F

#define MWIFIEX_MAX_EVT_BD			0x08
#define MWIFIEX_EVTBD_MASK			0x0f

/* PCIE INTERNAL REGISTERS */
#define PCIE_SCRATCH_0_REG				0xC10
#define PCIE_SCRATCH_1_REG				0xC14
#define PCIE_CPU_INT_EVENT				0xC18
#define PCIE_CPU_INT_STATUS				0xC1C
#define PCIE_HOST_INT_STATUS				0xC30
#define PCIE_HOST_INT_MASK				0xC34
#define PCIE_HOST_INT_STATUS_MASK			0xC3C
#define PCIE_SCRATCH_2_REG				0xC40
#define PCIE_SCRATCH_3_REG				0xC44
#define PCIE_SCRATCH_4_REG				0xCD0
#define PCIE_SCRATCH_5_REG				0xCD4
#define PCIE_SCRATCH_6_REG				0xCD8
#define PCIE_SCRATCH_7_REG				0xCDC
#define PCIE_SCRATCH_8_REG				0xCE0
#define PCIE_SCRATCH_9_REG				0xCE4
#define PCIE_SCRATCH_10_REG				0xCE8
#define PCIE_SCRATCH_11_REG				0xCEC
#define PCIE_SCRATCH_12_REG				0xCF0
#define PCIE_RD_DATA_PTR_Q0_Q1                          0xC08C
#define PCIE_WR_DATA_PTR_Q0_Q1                          0xC05C

#define CPU_INTR_DNLD_RDY				BIT(0)
#define CPU_INTR_DOOR_BELL				BIT(1)
#define CPU_INTR_SLEEP_CFM_DONE			BIT(2)
#define CPU_INTR_RESET					BIT(3)
#define CPU_INTR_EVENT_DONE				BIT(5)

#define HOST_INTR_DNLD_DONE				BIT(0)
#define HOST_INTR_UPLD_RDY				BIT(1)
#define HOST_INTR_CMD_DONE				BIT(2)
#define HOST_INTR_EVENT_RDY				BIT(3)
#define HOST_INTR_MASK					(HOST_INTR_DNLD_DONE | \
							 HOST_INTR_UPLD_RDY  | \
							 HOST_INTR_CMD_DONE  | \
							 HOST_INTR_EVENT_RDY)

#define MWIFIEX_BD_FLAG_ROLLOVER_IND			BIT(7)
#define MWIFIEX_BD_FLAG_FIRST_DESC			BIT(0)
#define MWIFIEX_BD_FLAG_LAST_DESC			BIT(1)
#define MWIFIEX_BD_FLAG_SOP				BIT(0)
#define MWIFIEX_BD_FLAG_EOP				BIT(1)
#define MWIFIEX_BD_FLAG_XS_SOP				BIT(2)
#define MWIFIEX_BD_FLAG_XS_EOP				BIT(3)
#define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND		BIT(7)
#define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND			BIT(10)
#define MWIFIEX_BD_FLAG_TX_START_PTR			BIT(16)
#define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND			BIT(26)

/* Max retry number of command write */
#define MAX_WRITE_IOMEM_RETRY				2
/* Define PCIE block size for firmware download */
#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD		256
/* FW awake cookie after FW ready */
#define FW_AWAKE_COOKIE						(0xAA55AA55)
#define MWIFIEX_DEF_SLEEP_COOKIE			0xBEEFBEEF
#define MWIFIEX_MAX_DELAY_COUNT				5

struct mwifiex_pcie_card_reg {
	u16 cmd_addr_lo;
	u16 cmd_addr_hi;
	u16 fw_status;
	u16 cmd_size;
	u16 cmdrsp_addr_lo;
	u16 cmdrsp_addr_hi;
	u16 tx_rdptr;
	u16 tx_wrptr;
	u16 rx_rdptr;
	u16 rx_wrptr;
	u16 evt_rdptr;
	u16 evt_wrptr;
	u16 drv_rdy;
	u16 tx_start_ptr;
	u32 tx_mask;
	u32 tx_wrap_mask;
	u32 rx_mask;
	u32 rx_wrap_mask;
	u32 tx_rollover_ind;
	u32 rx_rollover_ind;
	u32 evt_rollover_ind;
	u8 ring_flag_sop;
	u8 ring_flag_eop;
	u8 ring_flag_xs_sop;
	u8 ring_flag_xs_eop;
	u32 ring_tx_start_ptr;
	u8 pfu_enabled;
	u8 sleep_cookie;
	u16 fw_dump_ctrl;
	u16 fw_dump_start;
	u16 fw_dump_end;
	u8 fw_dump_host_ready;
	u8 fw_dump_read_done;
	u8 msix_support;
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = PCIE_SCRATCH_6_REG,
	.tx_wrptr = PCIE_SCRATCH_7_REG,
	.rx_rdptr = PCIE_SCRATCH_8_REG,
	.rx_wrptr = PCIE_SCRATCH_9_REG,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 0,
	.tx_mask = MWIFIEX_TXBD_MASK,
	.tx_wrap_mask = 0,
	.rx_mask = MWIFIEX_RXBD_MASK,
	.rx_wrap_mask = 0,
	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.ring_flag_sop = 0,
	.ring_flag_eop = 0,
	.ring_flag_xs_sop = 0,
	.ring_flag_xs_eop = 0,
	.ring_tx_start_ptr = 0,
	.pfu_enabled = 0,
	.sleep_cookie = 1,
	.msix_support = 0,
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 16,
	.tx_mask = 0x03FF0000,
	.tx_wrap_mask = 0x07FF0000,
	.rx_mask = 0x000003FF,
	.rx_wrap_mask = 0x000007FF,
	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	.pfu_enabled = 1,
	.sleep_cookie = 0,
	.fw_dump_ctrl = 0xcf4,
	.fw_dump_start = 0xcf8,
	.fw_dump_end = 0xcff,
	.fw_dump_host_ready = 0xee,
	.fw_dump_read_done = 0xfe,
	.msix_support = 0,
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = 0xC1A4,
	.tx_wrptr = 0xC174,
	.rx_rdptr = 0xC174,
	.rx_wrptr = 0xC1A4,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 16,
	.tx_mask = 0x0FFF0000,
	.tx_wrap_mask = 0x1FFF0000,
	.rx_mask = 0x00000FFF,
	.rx_wrap_mask = 0x00001FFF,
	.tx_rollover_ind = BIT(28),
	.rx_rollover_ind = BIT(12),
	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	.pfu_enabled = 1,
	.sleep_cookie = 0,
	.fw_dump_ctrl = 0xcf4,
	.fw_dump_start = 0xcf8,
	.fw_dump_end = 0xcff,
	.fw_dump_host_ready = 0xcc,
	.fw_dump_read_done = 0xdd,
	.msix_support = 1,
};

static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
	{"ITCM", NULL, 0, 0xF0},
	{"DTCM", NULL, 0, 0xF1},
	{"SQRAM", NULL, 0, 0xF2},
	{"IRAM", NULL, 0, 0xF3},
	{"APU", NULL, 0, 0xF4},
	{"CIU", NULL, 0, 0xF5},
	{"ICU", NULL, 0, 0xF6},
	{"MAC", NULL, 0, 0xF7},
};

static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
	{"DUMP", NULL, 0, 0xDD},
};

struct mwifiex_pcie_device {
	const char *firmware;
	const struct mwifiex_pcie_card_reg *reg;
	u16 blksz_fw_dl;
	u16 tx_buf_size;
	bool can_dump_fw;
	struct memory_type_mapping *mem_type_mapping_tbl;
	u8 num_mem_types;
	bool can_ext_scan;
};

static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
	.firmware       = PCIE8766_DEFAULT_FW_NAME,
	.reg            = &mwifiex_reg_8766,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.can_dump_fw = false,
	.can_ext_scan = true,
};

static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
	.firmware       = PCIE8897_DEFAULT_FW_NAME,
	.reg            = &mwifiex_reg_8897,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	.can_dump_fw = true,
	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
	.can_ext_scan = true,
};

static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
	.firmware       = PCIE8997_DEFAULT_FW_NAME,
	.reg            = &mwifiex_reg_8997,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	.can_dump_fw = true,
	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
	.can_ext_scan = true,
};

struct mwifiex_evt_buf_desc {
	u64 paddr;
	u16 len;
	u16 flags;
} __packed;

struct mwifiex_pcie_buf_desc {
	u64 paddr;
	u16 len;
	u16 flags;
} __packed;

struct mwifiex_pfu_buf_desc {
	u16 flags;
	u16 offset;
	u16 frag_len;
	u16 len;
	u64 paddr;
	u32 reserved;
} __packed;

#define MWIFIEX_NUM_MSIX_VECTORS   4

struct mwifiex_msix_context {
	struct pci_dev *dev;
	u16 msg_id;
};

struct pcie_service_card {
	struct pci_dev *dev;
	struct mwifiex_adapter *adapter;
	struct mwifiex_pcie_device pcie;

	u8 txbd_flush;
	u32 txbd_wrptr;
	u32 txbd_rdptr;
	u32 txbd_ring_size;
	u8 *txbd_ring_vbase;
	dma_addr_t txbd_ring_pbase;
	void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];

	u32 rxbd_wrptr;
	u32 rxbd_rdptr;
	u32 rxbd_ring_size;
	u8 *rxbd_ring_vbase;
	dma_addr_t rxbd_ring_pbase;
	void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];

	u32 evtbd_wrptr;
	u32 evtbd_rdptr;
	u32 evtbd_ring_size;
	u8 *evtbd_ring_vbase;
	dma_addr_t evtbd_ring_pbase;
	void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];

	struct sk_buff *cmd_buf;
	struct sk_buff *cmdrsp_buf;
	u8 *sleep_cookie_vbase;
	dma_addr_t sleep_cookie_pbase;
	void __iomem *pci_mmap;
	void __iomem *pci_mmap1;
	int msi_enable;
	int msix_enable;
#ifdef CONFIG_PCI
	struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
#endif
	struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
	struct mwifiex_msix_context share_irq_ctx;
};

static inline int
mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
{
	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;

	switch (card->dev->device) {
	case PCIE_DEVICE_ID_MARVELL_88W8766P:
		if (((card->txbd_wrptr & reg->tx_mask) ==
		     (rdptr & reg->tx_mask)) &&
		    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
		     (rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	case PCIE_DEVICE_ID_MARVELL_88W8897:
	case PCIE_DEVICE_ID_MARVELL_88W8997:
		if (((card->txbd_wrptr & reg->tx_mask) ==
		     (rdptr & reg->tx_mask)) &&
		    ((card->txbd_wrptr & reg->tx_rollover_ind) ==
			(rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	}

	return 0;
}

static inline int
mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
{
	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;

	switch (card->dev->device) {
	case PCIE_DEVICE_ID_MARVELL_88W8766P:
		if (((card->txbd_wrptr & reg->tx_mask) !=
		     (card->txbd_rdptr & reg->tx_mask)) ||
		    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
		     (card->txbd_rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	case PCIE_DEVICE_ID_MARVELL_88W8897:
	case PCIE_DEVICE_ID_MARVELL_88W8997:
		if (((card->txbd_wrptr & reg->tx_mask) !=
		     (card->txbd_rdptr & reg->tx_mask)) ||
		    ((card->txbd_wrptr & reg->tx_rollover_ind) ==
		     (card->txbd_rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	}

	return 0;
}

#endif /* _MWIFIEX_PCIE_H */
Commit	Line	Data
d930faee AK	1	/* @file mwifiex_pcie.h
	2	*
	3	* @brief This file contains definitions for PCI-E interface.
	4	* driver.
	5	*
65da33f5	6	* Copyright (C) 2011-2014, Marvell International Ltd.
d930faee AK	7	*
	8	* This software file (the "File") is distributed by Marvell International
	9	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	10	* (the "License"). You may use, redistribute and/or modify this File in
	11	* accordance with the terms and conditions of the License, a copy of which
	12	* is available by writing to the Free Software Foundation, Inc.,
	13	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	14	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	15	*
	16	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	17	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	18	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	19	* this warranty disclaimer.
	20	*/
	21
	22	#ifndef _MWIFIEX_PCIE_H
	23	#define _MWIFIEX_PCIE_H
	24
	25	#include <linux/pci.h>
	26	#include <linux/pcieport_if.h>
	27	#include <linux/interrupt.h>
	28
9a862322	29	#include "decl.h"
d930faee AK	30	#include "main.h"
	31
	32	#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
ca8f2112	33	#define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
6d85ef00	34	#define PCIE8997_DEFAULT_FW_NAME "mrvl/pcie8997_uapsta.bin"
ca8f2112 AP	35
	36	#define PCIE_VENDOR_ID_MARVELL (0x11ab)
	37	#define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
	38	#define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
6d85ef00	39	#define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42)
d930faee AK	40
	41	/* Constants for Buffer Descriptor (BD) rings */
	42	#define MWIFIEX_MAX_TXRX_BD 0x20
	43	#define MWIFIEX_TXBD_MASK 0x3F
	44	#define MWIFIEX_RXBD_MASK 0x3F
	45
2703a668 AP	46	#define MWIFIEX_MAX_EVT_BD 0x08
2703a668 AP	47	#define MWIFIEX_EVTBD_MASK 0x0f
d930faee AK	48
	49	/* PCIE INTERNAL REGISTERS */
	50	#define PCIE_SCRATCH_0_REG 0xC10
	51	#define PCIE_SCRATCH_1_REG 0xC14
	52	#define PCIE_CPU_INT_EVENT 0xC18
	53	#define PCIE_CPU_INT_STATUS 0xC1C
	54	#define PCIE_HOST_INT_STATUS 0xC30
	55	#define PCIE_HOST_INT_MASK 0xC34
	56	#define PCIE_HOST_INT_STATUS_MASK 0xC3C
	57	#define PCIE_SCRATCH_2_REG 0xC40
	58	#define PCIE_SCRATCH_3_REG 0xC44
428ca8a7 BZ	59	#define PCIE_SCRATCH_4_REG 0xCD0
	60	#define PCIE_SCRATCH_5_REG 0xCD4
	61	#define PCIE_SCRATCH_6_REG 0xCD8
	62	#define PCIE_SCRATCH_7_REG 0xCDC
	63	#define PCIE_SCRATCH_8_REG 0xCE0
	64	#define PCIE_SCRATCH_9_REG 0xCE4
	65	#define PCIE_SCRATCH_10_REG 0xCE8
	66	#define PCIE_SCRATCH_11_REG 0xCEC
	67	#define PCIE_SCRATCH_12_REG 0xCF0
ca8f2112 AP	68	#define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C
ca8f2112 AP	69	#define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C
d930faee AK	70
	71	#define CPU_INTR_DNLD_RDY BIT(0)
	72	#define CPU_INTR_DOOR_BELL BIT(1)
	73	#define CPU_INTR_SLEEP_CFM_DONE BIT(2)
	74	#define CPU_INTR_RESET BIT(3)
2703a668	75	#define CPU_INTR_EVENT_DONE BIT(5)
d930faee AK	76
	77	#define HOST_INTR_DNLD_DONE BIT(0)
	78	#define HOST_INTR_UPLD_RDY BIT(1)
	79	#define HOST_INTR_CMD_DONE BIT(2)
	80	#define HOST_INTR_EVENT_RDY BIT(3)
	81	#define HOST_INTR_MASK (HOST_INTR_DNLD_DONE \| \
	82	HOST_INTR_UPLD_RDY \| \
	83	HOST_INTR_CMD_DONE \| \
	84	HOST_INTR_EVENT_RDY)
	85
	86	#define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
	87	#define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
	88	#define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
ca8f2112 AP	89	#define MWIFIEX_BD_FLAG_SOP BIT(0)
	90	#define MWIFIEX_BD_FLAG_EOP BIT(1)
	91	#define MWIFIEX_BD_FLAG_XS_SOP BIT(2)
	92	#define MWIFIEX_BD_FLAG_XS_EOP BIT(3)
	93	#define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7)
	94	#define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10)
	95	#define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16)
	96	#define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26)
d930faee AK	97
	98	/* Max retry number of command write */
	99	#define MAX_WRITE_IOMEM_RETRY 2
	100	/* Define PCIE block size for firmware download */
	101	#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
	102	/* FW awake cookie after FW ready */
	103	#define FW_AWAKE_COOKIE (0xAA55AA55)
c4bc980f AP	104	#define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF
c4bc980f AP	105	#define MWIFIEX_MAX_DELAY_COUNT 5
d930faee	106
dd04e6ac AP	107	struct mwifiex_pcie_card_reg {
	108	u16 cmd_addr_lo;
	109	u16 cmd_addr_hi;
	110	u16 fw_status;
	111	u16 cmd_size;
	112	u16 cmdrsp_addr_lo;
	113	u16 cmdrsp_addr_hi;
	114	u16 tx_rdptr;
	115	u16 tx_wrptr;
	116	u16 rx_rdptr;
	117	u16 rx_wrptr;
	118	u16 evt_rdptr;
	119	u16 evt_wrptr;
	120	u16 drv_rdy;
	121	u16 tx_start_ptr;
	122	u32 tx_mask;
	123	u32 tx_wrap_mask;
	124	u32 rx_mask;
	125	u32 rx_wrap_mask;
	126	u32 tx_rollover_ind;
	127	u32 rx_rollover_ind;
	128	u32 evt_rollover_ind;
	129	u8 ring_flag_sop;
	130	u8 ring_flag_eop;
	131	u8 ring_flag_xs_sop;
	132	u8 ring_flag_xs_eop;
	133	u32 ring_tx_start_ptr;
	134	u8 pfu_enabled;
52301a81	135	u8 sleep_cookie;
92c2538f AK	136	u16 fw_dump_ctrl;
	137	u16 fw_dump_start;
	138	u16 fw_dump_end;
50632092 XH	139	u8 fw_dump_host_ready;
50632092 XH	140	u8 fw_dump_read_done;
99074fc1	141	u8 msix_support;
dd04e6ac AP	142	};
	143
	144	static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	145	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	146	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	147	.cmd_size = PCIE_SCRATCH_2_REG,
	148	.fw_status = PCIE_SCRATCH_3_REG,
	149	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	150	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	151	.tx_rdptr = PCIE_SCRATCH_6_REG,
	152	.tx_wrptr = PCIE_SCRATCH_7_REG,
	153	.rx_rdptr = PCIE_SCRATCH_8_REG,
	154	.rx_wrptr = PCIE_SCRATCH_9_REG,
	155	.evt_rdptr = PCIE_SCRATCH_10_REG,
	156	.evt_wrptr = PCIE_SCRATCH_11_REG,
	157	.drv_rdy = PCIE_SCRATCH_12_REG,
	158	.tx_start_ptr = 0,
	159	.tx_mask = MWIFIEX_TXBD_MASK,
	160	.tx_wrap_mask = 0,
	161	.rx_mask = MWIFIEX_RXBD_MASK,
	162	.rx_wrap_mask = 0,
	163	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	164	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	165	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	166	.ring_flag_sop = 0,
	167	.ring_flag_eop = 0,
	168	.ring_flag_xs_sop = 0,
	169	.ring_flag_xs_eop = 0,
	170	.ring_tx_start_ptr = 0,
	171	.pfu_enabled = 0,
52301a81	172	.sleep_cookie = 1,
99074fc1	173	.msix_support = 0,
dd04e6ac AP	174	};
dd04e6ac AP	175
ca8f2112 AP	176	static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
	177	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	178	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	179	.cmd_size = PCIE_SCRATCH_2_REG,
	180	.fw_status = PCIE_SCRATCH_3_REG,
	181	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	182	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	183	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
	184	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
	185	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
	186	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
	187	.evt_rdptr = PCIE_SCRATCH_10_REG,
	188	.evt_wrptr = PCIE_SCRATCH_11_REG,
	189	.drv_rdy = PCIE_SCRATCH_12_REG,
	190	.tx_start_ptr = 16,
	191	.tx_mask = 0x03FF0000,
	192	.tx_wrap_mask = 0x07FF0000,
	193	.rx_mask = 0x000003FF,
	194	.rx_wrap_mask = 0x000007FF,
	195	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
	196	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
	197	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	198	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	199	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	200	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	201	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	202	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	203	.pfu_enabled = 1,
52301a81	204	.sleep_cookie = 0,
92c2538f AK	205	.fw_dump_ctrl = 0xcf4,
92c2538f AK	206	.fw_dump_start = 0xcf8,
6d85ef00	207	.fw_dump_end = 0xcff,
50632092 XH	208	.fw_dump_host_ready = 0xee,
50632092 XH	209	.fw_dump_read_done = 0xfe,
99074fc1	210	.msix_support = 0,
6d85ef00 ZL	211	};
	212
	213	static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
	214	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	215	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	216	.cmd_size = PCIE_SCRATCH_2_REG,
	217	.fw_status = PCIE_SCRATCH_3_REG,
	218	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	219	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	220	.tx_rdptr = 0xC1A4,
ce0c58d9 AK	221	.tx_wrptr = 0xC174,
ce0c58d9 AK	222	.rx_rdptr = 0xC174,
6d85ef00 ZL	223	.rx_wrptr = 0xC1A4,
	224	.evt_rdptr = PCIE_SCRATCH_10_REG,
	225	.evt_wrptr = PCIE_SCRATCH_11_REG,
	226	.drv_rdy = PCIE_SCRATCH_12_REG,
	227	.tx_start_ptr = 16,
	228	.tx_mask = 0x0FFF0000,
ce0c58d9	229	.tx_wrap_mask = 0x1FFF0000,
6d85ef00	230	.rx_mask = 0x00000FFF,
ce0c58d9	231	.rx_wrap_mask = 0x00001FFF,
6d85ef00 ZL	232	.tx_rollover_ind = BIT(28),
	233	.rx_rollover_ind = BIT(12),
	234	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	235	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	236	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	237	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	238	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	239	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	240	.pfu_enabled = 1,
	241	.sleep_cookie = 0,
11e70824 XH	242	.fw_dump_ctrl = 0xcf4,
	243	.fw_dump_start = 0xcf8,
	244	.fw_dump_end = 0xcff,
	245	.fw_dump_host_ready = 0xcc,
	246	.fw_dump_read_done = 0xdd,
99074fc1	247	.msix_support = 1,
ca8f2112 AP	248	};
ca8f2112 AP	249
50632092 XH	250	static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
	251	{"ITCM", NULL, 0, 0xF0},
	252	{"DTCM", NULL, 0, 0xF1},
	253	{"SQRAM", NULL, 0, 0xF2},
	254	{"IRAM", NULL, 0, 0xF3},
	255	{"APU", NULL, 0, 0xF4},
	256	{"CIU", NULL, 0, 0xF5},
	257	{"ICU", NULL, 0, 0xF6},
	258	{"MAC", NULL, 0, 0xF7},
	259	};
	260
11e70824 XH	261	static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
	262	{"DUMP", NULL, 0, 0xDD},
	263	};
	264
dd04e6ac AP	265	struct mwifiex_pcie_device {
	266	const char *firmware;
	267	const struct mwifiex_pcie_card_reg *reg;
	268	u16 blksz_fw_dl;
828cf222	269	u16 tx_buf_size;
b4e8aebb	270	bool can_dump_fw;
50632092 XH	271	struct memory_type_mapping *mem_type_mapping_tbl;
50632092 XH	272	u8 num_mem_types;
1fe192d8	273	bool can_ext_scan;
dd04e6ac AP	274	};
	275
	276	static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
	277	.firmware = PCIE8766_DEFAULT_FW_NAME,
	278	.reg = &mwifiex_reg_8766,
	279	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
828cf222	280	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
b4e8aebb	281	.can_dump_fw = false,
1fe192d8	282	.can_ext_scan = true,
dd04e6ac AP	283	};
dd04e6ac AP	284
ca8f2112 AP	285	static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
	286	.firmware = PCIE8897_DEFAULT_FW_NAME,
	287	.reg = &mwifiex_reg_8897,
	288	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
828cf222	289	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
b4e8aebb	290	.can_dump_fw = true,
50632092 XH	291	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
50632092 XH	292	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
1fe192d8	293	.can_ext_scan = true,
ca8f2112 AP	294	};
ca8f2112 AP	295
6d85ef00 ZL	296	static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
	297	.firmware = PCIE8997_DEFAULT_FW_NAME,
	298	.reg = &mwifiex_reg_8997,
	299	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	300	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
11e70824 XH	301	.can_dump_fw = true,
	302	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
	303	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
6d85ef00 ZL	304	.can_ext_scan = true,
	305	};
	306
e05dc3e9 AP	307	struct mwifiex_evt_buf_desc {
	308	u64 paddr;
	309	u16 len;
	310	u16 flags;
	311	} __packed;
	312
d930faee AK	313	struct mwifiex_pcie_buf_desc {
	314	u64 paddr;
	315	u16 len;
	316	u16 flags;
	317	} __packed;
	318
ca8f2112 AP	319	struct mwifiex_pfu_buf_desc {
	320	u16 flags;
	321	u16 offset;
	322	u16 frag_len;
	323	u16 len;
	324	u64 paddr;
	325	u32 reserved;
	326	} __packed;
	327
99074fc1 XH	328	#define MWIFIEX_NUM_MSIX_VECTORS 4
	329
	330	struct mwifiex_msix_context {
	331	struct pci_dev *dev;
	332	u16 msg_id;
	333	};
	334
d930faee AK	335	struct pcie_service_card {
	336	struct pci_dev *dev;
	337	struct mwifiex_adapter *adapter;
dd04e6ac	338	struct mwifiex_pcie_device pcie;
d930faee	339
fbd7e7ac	340	u8 txbd_flush;
d930faee AK	341	u32 txbd_wrptr;
	342	u32 txbd_rdptr;
	343	u32 txbd_ring_size;
	344	u8 *txbd_ring_vbase;
fc331460	345	dma_addr_t txbd_ring_pbase;
e05dc3e9	346	void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
d930faee AK	347	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
	348
	349	u32 rxbd_wrptr;
	350	u32 rxbd_rdptr;
	351	u32 rxbd_ring_size;
	352	u8 *rxbd_ring_vbase;
fc331460	353	dma_addr_t rxbd_ring_pbase;
e05dc3e9	354	void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
d930faee AK	355	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
	356
	357	u32 evtbd_wrptr;
	358	u32 evtbd_rdptr;
	359	u32 evtbd_ring_size;
	360	u8 *evtbd_ring_vbase;
fc331460	361	dma_addr_t evtbd_ring_pbase;
e05dc3e9	362	void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
d930faee AK	363	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
	364
	365	struct sk_buff *cmd_buf;
	366	struct sk_buff *cmdrsp_buf;
fc331460 AP	367	u8 *sleep_cookie_vbase;
fc331460 AP	368	dma_addr_t sleep_cookie_pbase;
d930faee AK	369	void __iomem *pci_mmap;
d930faee AK	370	void __iomem *pci_mmap1;
7be0f5b5	371	int msi_enable;
99074fc1 XH	372	int msix_enable;
	373	#ifdef CONFIG_PCI
	374	struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
	375	#endif
	376	struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
	377	struct mwifiex_msix_context share_irq_ctx;
d930faee AK	378	};
d930faee AK	379
fbd7e7ac AP	380	static inline int
	381	mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
	382	{
dd04e6ac AP	383	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
dd04e6ac AP	384
ca8f2112 AP	385	switch (card->dev->device) {
	386	case PCIE_DEVICE_ID_MARVELL_88W8766P:
	387	if (((card->txbd_wrptr & reg->tx_mask) ==
	388	(rdptr & reg->tx_mask)) &&
	389	((card->txbd_wrptr & reg->tx_rollover_ind) !=
	390	(rdptr & reg->tx_rollover_ind)))
	391	return 1;
	392	break;
	393	case PCIE_DEVICE_ID_MARVELL_88W8897:
f3b35f28	394	case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112 AP	395	if (((card->txbd_wrptr & reg->tx_mask) ==
	396	(rdptr & reg->tx_mask)) &&
	397	((card->txbd_wrptr & reg->tx_rollover_ind) ==
dd04e6ac	398	(rdptr & reg->tx_rollover_ind)))
ca8f2112 AP	399	return 1;
	400	break;
	401	}
fbd7e7ac AP	402
	403	return 0;
	404	}
	405
e7f767a7 AP	406	static inline int
	407	mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
	408	{
dd04e6ac AP	409	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
dd04e6ac AP	410
ca8f2112 AP	411	switch (card->dev->device) {
	412	case PCIE_DEVICE_ID_MARVELL_88W8766P:
	413	if (((card->txbd_wrptr & reg->tx_mask) !=
	414	(card->txbd_rdptr & reg->tx_mask)) \|\|
	415	((card->txbd_wrptr & reg->tx_rollover_ind) !=
	416	(card->txbd_rdptr & reg->tx_rollover_ind)))
	417	return 1;
	418	break;
	419	case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00	420	case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112 AP	421	if (((card->txbd_wrptr & reg->tx_mask) !=
	422	(card->txbd_rdptr & reg->tx_mask)) \|\|
	423	((card->txbd_wrptr & reg->tx_rollover_ind) ==
	424	(card->txbd_rdptr & reg->tx_rollover_ind)))
	425	return 1;
	426	break;
	427	}
e7f767a7 AP	428
	429	return 0;
	430	}
92c2538f	431
d930faee	432	#endif /* _MWIFIEX_PCIE_H */