[deliverable/linux.git] / drivers / net / wireless / marvell / mwifiex / pcie.h

/* @file mwifiex_pcie.h
 *
 * @brief This file contains definitions for PCI-E interface.
 * driver.
 *
 * Copyright (C) 2011-2014, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_PCIE_H
#define	_MWIFIEX_PCIE_H

#include    <linux/pci.h>
#include    <linux/pcieport_if.h>
#include    <linux/interrupt.h>

#include    "decl.h"
#include    "main.h"

#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
#define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin"
#define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin"
#define PCIE8997_FW_NAME_Z "mrvl/pcieusb8997_combo.bin"
#define PCIE8997_FW_NAME_V2 "mrvl/pcieusb8997_combo_v2.bin"

#define PCIE_VENDOR_ID_MARVELL              (0x11ab)
#define PCIE_VENDOR_ID_V2_MARVELL           (0x1b4b)
#define PCIE_DEVICE_ID_MARVELL_88W8766P		(0x2b30)
#define PCIE_DEVICE_ID_MARVELL_88W8897		(0x2b38)
#define PCIE_DEVICE_ID_MARVELL_88W8997		(0x2b42)

#define PCIE8897_A0	0x1100
#define PCIE8897_B0	0x1200
#define PCIE8997_Z	0x0
#define PCIE8997_V2	0x471

/* Constants for Buffer Descriptor (BD) rings */
#define MWIFIEX_MAX_TXRX_BD			0x20
#define MWIFIEX_TXBD_MASK			0x3F
#define MWIFIEX_RXBD_MASK			0x3F

#define MWIFIEX_MAX_EVT_BD			0x08
#define MWIFIEX_EVTBD_MASK			0x0f

/* PCIE INTERNAL REGISTERS */
#define PCIE_SCRATCH_0_REG				0xC10
#define PCIE_SCRATCH_1_REG				0xC14
#define PCIE_CPU_INT_EVENT				0xC18
#define PCIE_CPU_INT_STATUS				0xC1C
#define PCIE_HOST_INT_STATUS				0xC30
#define PCIE_HOST_INT_MASK				0xC34
#define PCIE_HOST_INT_STATUS_MASK			0xC3C
#define PCIE_SCRATCH_2_REG				0xC40
#define PCIE_SCRATCH_3_REG				0xC44
#define PCIE_SCRATCH_4_REG				0xCD0
#define PCIE_SCRATCH_5_REG				0xCD4
#define PCIE_SCRATCH_6_REG				0xCD8
#define PCIE_SCRATCH_7_REG				0xCDC
#define PCIE_SCRATCH_8_REG				0xCE0
#define PCIE_SCRATCH_9_REG				0xCE4
#define PCIE_SCRATCH_10_REG				0xCE8
#define PCIE_SCRATCH_11_REG				0xCEC
#define PCIE_SCRATCH_12_REG				0xCF0
#define PCIE_SCRATCH_13_REG				0xCF8
#define PCIE_SCRATCH_14_REG				0xCFC
#define PCIE_RD_DATA_PTR_Q0_Q1                          0xC08C
#define PCIE_WR_DATA_PTR_Q0_Q1                          0xC05C

#define CPU_INTR_DNLD_RDY				BIT(0)
#define CPU_INTR_DOOR_BELL				BIT(1)
#define CPU_INTR_SLEEP_CFM_DONE			BIT(2)
#define CPU_INTR_RESET					BIT(3)
#define CPU_INTR_EVENT_DONE				BIT(5)

#define HOST_INTR_DNLD_DONE				BIT(0)
#define HOST_INTR_UPLD_RDY				BIT(1)
#define HOST_INTR_CMD_DONE				BIT(2)
#define HOST_INTR_EVENT_RDY				BIT(3)
#define HOST_INTR_MASK					(HOST_INTR_DNLD_DONE | \
							 HOST_INTR_UPLD_RDY  | \
							 HOST_INTR_CMD_DONE  | \
							 HOST_INTR_EVENT_RDY)

#define MWIFIEX_BD_FLAG_ROLLOVER_IND			BIT(7)
#define MWIFIEX_BD_FLAG_FIRST_DESC			BIT(0)
#define MWIFIEX_BD_FLAG_LAST_DESC			BIT(1)
#define MWIFIEX_BD_FLAG_SOP				BIT(0)
#define MWIFIEX_BD_FLAG_EOP				BIT(1)
#define MWIFIEX_BD_FLAG_XS_SOP				BIT(2)
#define MWIFIEX_BD_FLAG_XS_EOP				BIT(3)
#define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND		BIT(7)
#define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND			BIT(10)
#define MWIFIEX_BD_FLAG_TX_START_PTR			BIT(16)
#define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND			BIT(26)

/* Max retry number of command write */
#define MAX_WRITE_IOMEM_RETRY				2
/* Define PCIE block size for firmware download */
#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD		256
/* FW awake cookie after FW ready */
#define FW_AWAKE_COOKIE						(0xAA55AA55)
#define MWIFIEX_DEF_SLEEP_COOKIE			0xBEEFBEEF
#define MWIFIEX_MAX_DELAY_COUNT				5

struct mwifiex_pcie_card_reg {
	u16 cmd_addr_lo;
	u16 cmd_addr_hi;
	u16 fw_status;
	u16 cmd_size;
	u16 cmdrsp_addr_lo;
	u16 cmdrsp_addr_hi;
	u16 tx_rdptr;
	u16 tx_wrptr;
	u16 rx_rdptr;
	u16 rx_wrptr;
	u16 evt_rdptr;
	u16 evt_wrptr;
	u16 drv_rdy;
	u16 tx_start_ptr;
	u32 tx_mask;
	u32 tx_wrap_mask;
	u32 rx_mask;
	u32 rx_wrap_mask;
	u32 tx_rollover_ind;
	u32 rx_rollover_ind;
	u32 evt_rollover_ind;
	u8 ring_flag_sop;
	u8 ring_flag_eop;
	u8 ring_flag_xs_sop;
	u8 ring_flag_xs_eop;
	u32 ring_tx_start_ptr;
	u8 pfu_enabled;
	u8 sleep_cookie;
	u16 fw_dump_ctrl;
	u16 fw_dump_start;
	u16 fw_dump_end;
	u8 fw_dump_host_ready;
	u8 fw_dump_read_done;
	u8 msix_support;
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = PCIE_SCRATCH_6_REG,
	.tx_wrptr = PCIE_SCRATCH_7_REG,
	.rx_rdptr = PCIE_SCRATCH_8_REG,
	.rx_wrptr = PCIE_SCRATCH_9_REG,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 0,
	.tx_mask = MWIFIEX_TXBD_MASK,
	.tx_wrap_mask = 0,
	.rx_mask = MWIFIEX_RXBD_MASK,
	.rx_wrap_mask = 0,
	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.ring_flag_sop = 0,
	.ring_flag_eop = 0,
	.ring_flag_xs_sop = 0,
	.ring_flag_xs_eop = 0,
	.ring_tx_start_ptr = 0,
	.pfu_enabled = 0,
	.sleep_cookie = 1,
	.msix_support = 0,
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 16,
	.tx_mask = 0x03FF0000,
	.tx_wrap_mask = 0x07FF0000,
	.rx_mask = 0x000003FF,
	.rx_wrap_mask = 0x000007FF,
	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	.pfu_enabled = 1,
	.sleep_cookie = 0,
	.fw_dump_ctrl = 0xcf4,
	.fw_dump_start = 0xcf8,
	.fw_dump_end = 0xcff,
	.fw_dump_host_ready = 0xee,
	.fw_dump_read_done = 0xfe,
	.msix_support = 0,
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = 0xC1A4,
	.tx_wrptr = 0xC174,
	.rx_rdptr = 0xC174,
	.rx_wrptr = 0xC1A4,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 16,
	.tx_mask = 0x0FFF0000,
	.tx_wrap_mask = 0x1FFF0000,
	.rx_mask = 0x00000FFF,
	.rx_wrap_mask = 0x00001FFF,
	.tx_rollover_ind = BIT(28),
	.rx_rollover_ind = BIT(12),
	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	.pfu_enabled = 1,
	.sleep_cookie = 0,
	.fw_dump_ctrl = 0xcf4,
	.fw_dump_start = 0xcf8,
	.fw_dump_end = 0xcff,
	.fw_dump_host_ready = 0xcc,
	.fw_dump_read_done = 0xdd,
	.msix_support = 1,
};

static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
	{"ITCM", NULL, 0, 0xF0},
	{"DTCM", NULL, 0, 0xF1},
	{"SQRAM", NULL, 0, 0xF2},
	{"IRAM", NULL, 0, 0xF3},
	{"APU", NULL, 0, 0xF4},
	{"CIU", NULL, 0, 0xF5},
	{"ICU", NULL, 0, 0xF6},
	{"MAC", NULL, 0, 0xF7},
};

static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
	{"DUMP", NULL, 0, 0xDD},
};

struct mwifiex_pcie_device {
	const struct mwifiex_pcie_card_reg *reg;
	u16 blksz_fw_dl;
	u16 tx_buf_size;
	bool can_dump_fw;
	struct memory_type_mapping *mem_type_mapping_tbl;
	u8 num_mem_types;
	bool can_ext_scan;
};

static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
	.reg            = &mwifiex_reg_8766,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.can_dump_fw = false,
	.can_ext_scan = true,
};

static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
	.reg            = &mwifiex_reg_8897,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	.can_dump_fw = true,
	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
	.can_ext_scan = true,
};

static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
	.reg            = &mwifiex_reg_8997,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	.can_dump_fw = true,
	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
	.can_ext_scan = true,
};

struct mwifiex_evt_buf_desc {
	u64 paddr;
	u16 len;
	u16 flags;
} __packed;

struct mwifiex_pcie_buf_desc {
	u64 paddr;
	u16 len;
	u16 flags;
} __packed;

struct mwifiex_pfu_buf_desc {
	u16 flags;
	u16 offset;
	u16 frag_len;
	u16 len;
	u64 paddr;
	u32 reserved;
} __packed;

#define MWIFIEX_NUM_MSIX_VECTORS   4

struct mwifiex_msix_context {
	struct pci_dev *dev;
	u16 msg_id;
};

struct pcie_service_card {
	struct pci_dev *dev;
	struct mwifiex_adapter *adapter;
	struct mwifiex_pcie_device pcie;

	u8 txbd_flush;
	u32 txbd_wrptr;
	u32 txbd_rdptr;
	u32 txbd_ring_size;
	u8 *txbd_ring_vbase;
	dma_addr_t txbd_ring_pbase;
	void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];

	u32 rxbd_wrptr;
	u32 rxbd_rdptr;
	u32 rxbd_ring_size;
	u8 *rxbd_ring_vbase;
	dma_addr_t rxbd_ring_pbase;
	void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];

	u32 evtbd_wrptr;
	u32 evtbd_rdptr;
	u32 evtbd_ring_size;
	u8 *evtbd_ring_vbase;
	dma_addr_t evtbd_ring_pbase;
	void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];

	struct sk_buff *cmd_buf;
	struct sk_buff *cmdrsp_buf;
	u8 *sleep_cookie_vbase;
	dma_addr_t sleep_cookie_pbase;
	void __iomem *pci_mmap;
	void __iomem *pci_mmap1;
	int msi_enable;
	int msix_enable;
#ifdef CONFIG_PCI
	struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
#endif
	struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
	struct mwifiex_msix_context share_irq_ctx;
};

static inline int
mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
{
	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;

	switch (card->dev->device) {
	case PCIE_DEVICE_ID_MARVELL_88W8766P:
		if (((card->txbd_wrptr & reg->tx_mask) ==
		     (rdptr & reg->tx_mask)) &&
		    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
		     (rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	case PCIE_DEVICE_ID_MARVELL_88W8897:
	case PCIE_DEVICE_ID_MARVELL_88W8997:
		if (((card->txbd_wrptr & reg->tx_mask) ==
		     (rdptr & reg->tx_mask)) &&
		    ((card->txbd_wrptr & reg->tx_rollover_ind) ==
			(rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	}

	return 0;
}

static inline int
mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
{
	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;

	switch (card->dev->device) {
	case PCIE_DEVICE_ID_MARVELL_88W8766P:
		if (((card->txbd_wrptr & reg->tx_mask) !=
		     (card->txbd_rdptr & reg->tx_mask)) ||
		    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
		     (card->txbd_rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	case PCIE_DEVICE_ID_MARVELL_88W8897:
	case PCIE_DEVICE_ID_MARVELL_88W8997:
		if (((card->txbd_wrptr & reg->tx_mask) !=
		     (card->txbd_rdptr & reg->tx_mask)) ||
		    ((card->txbd_wrptr & reg->tx_rollover_ind) ==
		     (card->txbd_rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	}

	return 0;
}

#endif /* _MWIFIEX_PCIE_H */
Commit	Line	Data
d930faee AK	1	/* @file mwifiex_pcie.h
	2	*
	3	* @brief This file contains definitions for PCI-E interface.
	4	* driver.
	5	*
65da33f5	6	* Copyright (C) 2011-2014, Marvell International Ltd.
d930faee AK	7	*
	8	* This software file (the "File") is distributed by Marvell International
	9	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	10	* (the "License"). You may use, redistribute and/or modify this File in
	11	* accordance with the terms and conditions of the License, a copy of which
	12	* is available by writing to the Free Software Foundation, Inc.,
	13	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	14	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	15	*
	16	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	17	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	18	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	19	* this warranty disclaimer.
	20	*/
	21
	22	#ifndef _MWIFIEX_PCIE_H
	23	#define _MWIFIEX_PCIE_H
	24
	25	#include <linux/pci.h>
	26	#include <linux/pcieport_if.h>
	27	#include <linux/interrupt.h>
	28
9a862322	29	#include "decl.h"
d930faee AK	30	#include "main.h"
	31
	32	#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
a362e16b SL	33	#define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin"
	34	#define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin"
	35	#define PCIE8997_FW_NAME_Z "mrvl/pcieusb8997_combo.bin"
	36	#define PCIE8997_FW_NAME_V2 "mrvl/pcieusb8997_combo_v2.bin"
ca8f2112 AP	37
ca8f2112 AP	38	#define PCIE_VENDOR_ID_MARVELL (0x11ab)
a362e16b	39	#define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b)
ca8f2112 AP	40	#define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
ca8f2112 AP	41	#define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
6d85ef00	42	#define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42)
d930faee	43
a362e16b SL	44	#define PCIE8897_A0 0x1100
	45	#define PCIE8897_B0 0x1200
	46	#define PCIE8997_Z 0x0
	47	#define PCIE8997_V2 0x471
	48
d930faee AK	49	/* Constants for Buffer Descriptor (BD) rings */
	50	#define MWIFIEX_MAX_TXRX_BD 0x20
	51	#define MWIFIEX_TXBD_MASK 0x3F
	52	#define MWIFIEX_RXBD_MASK 0x3F
	53
2703a668 AP	54	#define MWIFIEX_MAX_EVT_BD 0x08
2703a668 AP	55	#define MWIFIEX_EVTBD_MASK 0x0f
d930faee AK	56
	57	/* PCIE INTERNAL REGISTERS */
	58	#define PCIE_SCRATCH_0_REG 0xC10
	59	#define PCIE_SCRATCH_1_REG 0xC14
	60	#define PCIE_CPU_INT_EVENT 0xC18
	61	#define PCIE_CPU_INT_STATUS 0xC1C
	62	#define PCIE_HOST_INT_STATUS 0xC30
	63	#define PCIE_HOST_INT_MASK 0xC34
	64	#define PCIE_HOST_INT_STATUS_MASK 0xC3C
	65	#define PCIE_SCRATCH_2_REG 0xC40
	66	#define PCIE_SCRATCH_3_REG 0xC44
428ca8a7 BZ	67	#define PCIE_SCRATCH_4_REG 0xCD0
	68	#define PCIE_SCRATCH_5_REG 0xCD4
	69	#define PCIE_SCRATCH_6_REG 0xCD8
	70	#define PCIE_SCRATCH_7_REG 0xCDC
	71	#define PCIE_SCRATCH_8_REG 0xCE0
	72	#define PCIE_SCRATCH_9_REG 0xCE4
	73	#define PCIE_SCRATCH_10_REG 0xCE8
	74	#define PCIE_SCRATCH_11_REG 0xCEC
	75	#define PCIE_SCRATCH_12_REG 0xCF0
4646968b XH	76	#define PCIE_SCRATCH_13_REG 0xCF8
4646968b XH	77	#define PCIE_SCRATCH_14_REG 0xCFC
ca8f2112 AP	78	#define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C
ca8f2112 AP	79	#define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C
d930faee AK	80
	81	#define CPU_INTR_DNLD_RDY BIT(0)
	82	#define CPU_INTR_DOOR_BELL BIT(1)
	83	#define CPU_INTR_SLEEP_CFM_DONE BIT(2)
	84	#define CPU_INTR_RESET BIT(3)
2703a668	85	#define CPU_INTR_EVENT_DONE BIT(5)
d930faee AK	86
	87	#define HOST_INTR_DNLD_DONE BIT(0)
	88	#define HOST_INTR_UPLD_RDY BIT(1)
	89	#define HOST_INTR_CMD_DONE BIT(2)
	90	#define HOST_INTR_EVENT_RDY BIT(3)
	91	#define HOST_INTR_MASK (HOST_INTR_DNLD_DONE \| \
	92	HOST_INTR_UPLD_RDY \| \
	93	HOST_INTR_CMD_DONE \| \
	94	HOST_INTR_EVENT_RDY)
	95
	96	#define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
	97	#define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
	98	#define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
ca8f2112 AP	99	#define MWIFIEX_BD_FLAG_SOP BIT(0)
	100	#define MWIFIEX_BD_FLAG_EOP BIT(1)
	101	#define MWIFIEX_BD_FLAG_XS_SOP BIT(2)
	102	#define MWIFIEX_BD_FLAG_XS_EOP BIT(3)
	103	#define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7)
	104	#define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10)
	105	#define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16)
	106	#define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26)
d930faee AK	107
	108	/* Max retry number of command write */
	109	#define MAX_WRITE_IOMEM_RETRY 2
	110	/* Define PCIE block size for firmware download */
	111	#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
	112	/* FW awake cookie after FW ready */
	113	#define FW_AWAKE_COOKIE (0xAA55AA55)
c4bc980f AP	114	#define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF
c4bc980f AP	115	#define MWIFIEX_MAX_DELAY_COUNT 5
d930faee	116
dd04e6ac AP	117	struct mwifiex_pcie_card_reg {
	118	u16 cmd_addr_lo;
	119	u16 cmd_addr_hi;
	120	u16 fw_status;
	121	u16 cmd_size;
	122	u16 cmdrsp_addr_lo;
	123	u16 cmdrsp_addr_hi;
	124	u16 tx_rdptr;
	125	u16 tx_wrptr;
	126	u16 rx_rdptr;
	127	u16 rx_wrptr;
	128	u16 evt_rdptr;
	129	u16 evt_wrptr;
	130	u16 drv_rdy;
	131	u16 tx_start_ptr;
	132	u32 tx_mask;
	133	u32 tx_wrap_mask;
	134	u32 rx_mask;
	135	u32 rx_wrap_mask;
	136	u32 tx_rollover_ind;
	137	u32 rx_rollover_ind;
	138	u32 evt_rollover_ind;
	139	u8 ring_flag_sop;
	140	u8 ring_flag_eop;
	141	u8 ring_flag_xs_sop;
	142	u8 ring_flag_xs_eop;
	143	u32 ring_tx_start_ptr;
	144	u8 pfu_enabled;
52301a81	145	u8 sleep_cookie;
92c2538f AK	146	u16 fw_dump_ctrl;
	147	u16 fw_dump_start;
	148	u16 fw_dump_end;
50632092 XH	149	u8 fw_dump_host_ready;
50632092 XH	150	u8 fw_dump_read_done;
99074fc1	151	u8 msix_support;
dd04e6ac AP	152	};
	153
	154	static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	155	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	156	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	157	.cmd_size = PCIE_SCRATCH_2_REG,
	158	.fw_status = PCIE_SCRATCH_3_REG,
	159	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	160	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	161	.tx_rdptr = PCIE_SCRATCH_6_REG,
	162	.tx_wrptr = PCIE_SCRATCH_7_REG,
	163	.rx_rdptr = PCIE_SCRATCH_8_REG,
	164	.rx_wrptr = PCIE_SCRATCH_9_REG,
	165	.evt_rdptr = PCIE_SCRATCH_10_REG,
	166	.evt_wrptr = PCIE_SCRATCH_11_REG,
	167	.drv_rdy = PCIE_SCRATCH_12_REG,
	168	.tx_start_ptr = 0,
	169	.tx_mask = MWIFIEX_TXBD_MASK,
	170	.tx_wrap_mask = 0,
	171	.rx_mask = MWIFIEX_RXBD_MASK,
	172	.rx_wrap_mask = 0,
	173	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	174	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	175	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	176	.ring_flag_sop = 0,
	177	.ring_flag_eop = 0,
	178	.ring_flag_xs_sop = 0,
	179	.ring_flag_xs_eop = 0,
	180	.ring_tx_start_ptr = 0,
	181	.pfu_enabled = 0,
52301a81	182	.sleep_cookie = 1,
99074fc1	183	.msix_support = 0,
dd04e6ac AP	184	};
dd04e6ac AP	185
ca8f2112 AP	186	static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
	187	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	188	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	189	.cmd_size = PCIE_SCRATCH_2_REG,
	190	.fw_status = PCIE_SCRATCH_3_REG,
	191	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	192	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	193	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
	194	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
	195	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
	196	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
	197	.evt_rdptr = PCIE_SCRATCH_10_REG,
	198	.evt_wrptr = PCIE_SCRATCH_11_REG,
	199	.drv_rdy = PCIE_SCRATCH_12_REG,
	200	.tx_start_ptr = 16,
	201	.tx_mask = 0x03FF0000,
	202	.tx_wrap_mask = 0x07FF0000,
	203	.rx_mask = 0x000003FF,
	204	.rx_wrap_mask = 0x000007FF,
	205	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
	206	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
	207	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	208	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	209	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	210	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	211	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	212	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	213	.pfu_enabled = 1,
52301a81	214	.sleep_cookie = 0,
92c2538f AK	215	.fw_dump_ctrl = 0xcf4,
92c2538f AK	216	.fw_dump_start = 0xcf8,
6d85ef00	217	.fw_dump_end = 0xcff,
50632092 XH	218	.fw_dump_host_ready = 0xee,
50632092 XH	219	.fw_dump_read_done = 0xfe,
99074fc1	220	.msix_support = 0,
6d85ef00 ZL	221	};
	222
	223	static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
	224	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	225	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	226	.cmd_size = PCIE_SCRATCH_2_REG,
	227	.fw_status = PCIE_SCRATCH_3_REG,
	228	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	229	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	230	.tx_rdptr = 0xC1A4,
ce0c58d9 AK	231	.tx_wrptr = 0xC174,
ce0c58d9 AK	232	.rx_rdptr = 0xC174,
6d85ef00 ZL	233	.rx_wrptr = 0xC1A4,
	234	.evt_rdptr = PCIE_SCRATCH_10_REG,
	235	.evt_wrptr = PCIE_SCRATCH_11_REG,
	236	.drv_rdy = PCIE_SCRATCH_12_REG,
	237	.tx_start_ptr = 16,
	238	.tx_mask = 0x0FFF0000,
ce0c58d9	239	.tx_wrap_mask = 0x1FFF0000,
6d85ef00	240	.rx_mask = 0x00000FFF,
ce0c58d9	241	.rx_wrap_mask = 0x00001FFF,
6d85ef00 ZL	242	.tx_rollover_ind = BIT(28),
	243	.rx_rollover_ind = BIT(12),
	244	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	245	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	246	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	247	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	248	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	249	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	250	.pfu_enabled = 1,
	251	.sleep_cookie = 0,
11e70824 XH	252	.fw_dump_ctrl = 0xcf4,
	253	.fw_dump_start = 0xcf8,
	254	.fw_dump_end = 0xcff,
	255	.fw_dump_host_ready = 0xcc,
	256	.fw_dump_read_done = 0xdd,
99074fc1	257	.msix_support = 1,
ca8f2112 AP	258	};
ca8f2112 AP	259
50632092 XH	260	static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
	261	{"ITCM", NULL, 0, 0xF0},
	262	{"DTCM", NULL, 0, 0xF1},
	263	{"SQRAM", NULL, 0, 0xF2},
	264	{"IRAM", NULL, 0, 0xF3},
	265	{"APU", NULL, 0, 0xF4},
	266	{"CIU", NULL, 0, 0xF5},
	267	{"ICU", NULL, 0, 0xF6},
	268	{"MAC", NULL, 0, 0xF7},
	269	};
	270
11e70824 XH	271	static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
	272	{"DUMP", NULL, 0, 0xDD},
	273	};
	274
dd04e6ac	275	struct mwifiex_pcie_device {
dd04e6ac AP	276	const struct mwifiex_pcie_card_reg *reg;
dd04e6ac AP	277	u16 blksz_fw_dl;
828cf222	278	u16 tx_buf_size;
b4e8aebb	279	bool can_dump_fw;
50632092 XH	280	struct memory_type_mapping *mem_type_mapping_tbl;
50632092 XH	281	u8 num_mem_types;
1fe192d8	282	bool can_ext_scan;
dd04e6ac AP	283	};
	284
	285	static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
dd04e6ac AP	286	.reg = &mwifiex_reg_8766,
dd04e6ac AP	287	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
828cf222	288	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
b4e8aebb	289	.can_dump_fw = false,
1fe192d8	290	.can_ext_scan = true,
dd04e6ac AP	291	};
dd04e6ac AP	292
ca8f2112	293	static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
ca8f2112 AP	294	.reg = &mwifiex_reg_8897,
ca8f2112 AP	295	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
828cf222	296	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
b4e8aebb	297	.can_dump_fw = true,
50632092 XH	298	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
50632092 XH	299	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
1fe192d8	300	.can_ext_scan = true,
ca8f2112 AP	301	};
ca8f2112 AP	302
6d85ef00	303	static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
6d85ef00 ZL	304	.reg = &mwifiex_reg_8997,
	305	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	306	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
11e70824 XH	307	.can_dump_fw = true,
	308	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
	309	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
6d85ef00 ZL	310	.can_ext_scan = true,
	311	};
	312
e05dc3e9 AP	313	struct mwifiex_evt_buf_desc {
	314	u64 paddr;
	315	u16 len;
	316	u16 flags;
	317	} __packed;
	318
d930faee AK	319	struct mwifiex_pcie_buf_desc {
	320	u64 paddr;
	321	u16 len;
	322	u16 flags;
	323	} __packed;
	324
ca8f2112 AP	325	struct mwifiex_pfu_buf_desc {
	326	u16 flags;
	327	u16 offset;
	328	u16 frag_len;
	329	u16 len;
	330	u64 paddr;
	331	u32 reserved;
	332	} __packed;
	333
99074fc1 XH	334	#define MWIFIEX_NUM_MSIX_VECTORS 4
	335
	336	struct mwifiex_msix_context {
	337	struct pci_dev *dev;
	338	u16 msg_id;
	339	};
	340
d930faee AK	341	struct pcie_service_card {
	342	struct pci_dev *dev;
	343	struct mwifiex_adapter *adapter;
dd04e6ac	344	struct mwifiex_pcie_device pcie;
d930faee	345
fbd7e7ac	346	u8 txbd_flush;
d930faee AK	347	u32 txbd_wrptr;
	348	u32 txbd_rdptr;
	349	u32 txbd_ring_size;
	350	u8 *txbd_ring_vbase;
fc331460	351	dma_addr_t txbd_ring_pbase;
e05dc3e9	352	void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
d930faee AK	353	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
	354
	355	u32 rxbd_wrptr;
	356	u32 rxbd_rdptr;
	357	u32 rxbd_ring_size;
	358	u8 *rxbd_ring_vbase;
fc331460	359	dma_addr_t rxbd_ring_pbase;
e05dc3e9	360	void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
d930faee AK	361	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
	362
	363	u32 evtbd_wrptr;
	364	u32 evtbd_rdptr;
	365	u32 evtbd_ring_size;
	366	u8 *evtbd_ring_vbase;
fc331460	367	dma_addr_t evtbd_ring_pbase;
e05dc3e9	368	void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
d930faee AK	369	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
	370
	371	struct sk_buff *cmd_buf;
	372	struct sk_buff *cmdrsp_buf;
fc331460 AP	373	u8 *sleep_cookie_vbase;
fc331460 AP	374	dma_addr_t sleep_cookie_pbase;
d930faee AK	375	void __iomem *pci_mmap;
d930faee AK	376	void __iomem *pci_mmap1;
7be0f5b5	377	int msi_enable;
99074fc1 XH	378	int msix_enable;
	379	#ifdef CONFIG_PCI
	380	struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
	381	#endif
	382	struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
	383	struct mwifiex_msix_context share_irq_ctx;
d930faee AK	384	};
d930faee AK	385
fbd7e7ac AP	386	static inline int
	387	mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
	388	{
dd04e6ac AP	389	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
dd04e6ac AP	390
ca8f2112 AP	391	switch (card->dev->device) {
	392	case PCIE_DEVICE_ID_MARVELL_88W8766P:
	393	if (((card->txbd_wrptr & reg->tx_mask) ==
	394	(rdptr & reg->tx_mask)) &&
	395	((card->txbd_wrptr & reg->tx_rollover_ind) !=
	396	(rdptr & reg->tx_rollover_ind)))
	397	return 1;
	398	break;
	399	case PCIE_DEVICE_ID_MARVELL_88W8897:
f3b35f28	400	case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112 AP	401	if (((card->txbd_wrptr & reg->tx_mask) ==
	402	(rdptr & reg->tx_mask)) &&
	403	((card->txbd_wrptr & reg->tx_rollover_ind) ==
dd04e6ac	404	(rdptr & reg->tx_rollover_ind)))
ca8f2112 AP	405	return 1;
	406	break;
	407	}
fbd7e7ac AP	408
	409	return 0;
	410	}
	411
e7f767a7 AP	412	static inline int
	413	mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
	414	{
dd04e6ac AP	415	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
dd04e6ac AP	416
ca8f2112 AP	417	switch (card->dev->device) {
	418	case PCIE_DEVICE_ID_MARVELL_88W8766P:
	419	if (((card->txbd_wrptr & reg->tx_mask) !=
	420	(card->txbd_rdptr & reg->tx_mask)) \|\|
	421	((card->txbd_wrptr & reg->tx_rollover_ind) !=
	422	(card->txbd_rdptr & reg->tx_rollover_ind)))
	423	return 1;
	424	break;
	425	case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00	426	case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112 AP	427	if (((card->txbd_wrptr & reg->tx_mask) !=
	428	(card->txbd_rdptr & reg->tx_mask)) \|\|
	429	((card->txbd_wrptr & reg->tx_rollover_ind) ==
	430	(card->txbd_rdptr & reg->tx_rollover_ind)))
	431	return 1;
	432	break;
	433	}
e7f767a7 AP	434
	435	return 0;
	436	}
92c2538f	437
d930faee	438	#endif /* _MWIFIEX_PCIE_H */