[deliverable/linux.git] / drivers / net / wireless / marvell / mwifiex / pcie.h

/* @file mwifiex_pcie.h
 *
 * @brief This file contains definitions for PCI-E interface.
 * driver.
 *
 * Copyright (C) 2011-2014, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_PCIE_H
#define	_MWIFIEX_PCIE_H

#include    <linux/pci.h>
#include    <linux/pcieport_if.h>
#include    <linux/interrupt.h>

#include    "decl.h"
#include    "main.h"

#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
#define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin"
#define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin"
#define PCIEUART8997_FW_NAME_Z "mrvl/pcieuart8997_combo.bin"
#define PCIEUART8997_FW_NAME_V2 "mrvl/pcieuart8997_combo_v2.bin"
#define PCIEUSB8997_FW_NAME_Z "mrvl/pcieusb8997_combo.bin"
#define PCIEUSB8997_FW_NAME_V2 "mrvl/pcieusb8997_combo_v2.bin"

#define PCIE_VENDOR_ID_MARVELL              (0x11ab)
#define PCIE_VENDOR_ID_V2_MARVELL           (0x1b4b)
#define PCIE_DEVICE_ID_MARVELL_88W8766P		(0x2b30)
#define PCIE_DEVICE_ID_MARVELL_88W8897		(0x2b38)
#define PCIE_DEVICE_ID_MARVELL_88W8997		(0x2b42)

#define PCIE8897_A0	0x1100
#define PCIE8897_B0	0x1200
#define PCIE8997_Z	0x0
#define PCIE8997_V2	0x471
#define CHIP_VER_PCIEUSB	0x2

/* Constants for Buffer Descriptor (BD) rings */
#define MWIFIEX_MAX_TXRX_BD			0x20
#define MWIFIEX_TXBD_MASK			0x3F
#define MWIFIEX_RXBD_MASK			0x3F

#define MWIFIEX_MAX_EVT_BD			0x08
#define MWIFIEX_EVTBD_MASK			0x0f

/* PCIE INTERNAL REGISTERS */
#define PCIE_SCRATCH_0_REG				0xC10
#define PCIE_SCRATCH_1_REG				0xC14
#define PCIE_CPU_INT_EVENT				0xC18
#define PCIE_CPU_INT_STATUS				0xC1C
#define PCIE_HOST_INT_STATUS				0xC30
#define PCIE_HOST_INT_MASK				0xC34
#define PCIE_HOST_INT_STATUS_MASK			0xC3C
#define PCIE_SCRATCH_2_REG				0xC40
#define PCIE_SCRATCH_3_REG				0xC44
#define PCIE_SCRATCH_4_REG				0xCD0
#define PCIE_SCRATCH_5_REG				0xCD4
#define PCIE_SCRATCH_6_REG				0xCD8
#define PCIE_SCRATCH_7_REG				0xCDC
#define PCIE_SCRATCH_8_REG				0xCE0
#define PCIE_SCRATCH_9_REG				0xCE4
#define PCIE_SCRATCH_10_REG				0xCE8
#define PCIE_SCRATCH_11_REG				0xCEC
#define PCIE_SCRATCH_12_REG				0xCF0
#define PCIE_SCRATCH_13_REG				0xCF8
#define PCIE_SCRATCH_14_REG				0xCFC
#define PCIE_RD_DATA_PTR_Q0_Q1                          0xC08C
#define PCIE_WR_DATA_PTR_Q0_Q1                          0xC05C

#define CPU_INTR_DNLD_RDY				BIT(0)
#define CPU_INTR_DOOR_BELL				BIT(1)
#define CPU_INTR_SLEEP_CFM_DONE			BIT(2)
#define CPU_INTR_RESET					BIT(3)
#define CPU_INTR_EVENT_DONE				BIT(5)

#define HOST_INTR_DNLD_DONE				BIT(0)
#define HOST_INTR_UPLD_RDY				BIT(1)
#define HOST_INTR_CMD_DONE				BIT(2)
#define HOST_INTR_EVENT_RDY				BIT(3)
#define HOST_INTR_MASK					(HOST_INTR_DNLD_DONE | \
							 HOST_INTR_UPLD_RDY  | \
							 HOST_INTR_CMD_DONE  | \
							 HOST_INTR_EVENT_RDY)

#define MWIFIEX_BD_FLAG_ROLLOVER_IND			BIT(7)
#define MWIFIEX_BD_FLAG_FIRST_DESC			BIT(0)
#define MWIFIEX_BD_FLAG_LAST_DESC			BIT(1)
#define MWIFIEX_BD_FLAG_SOP				BIT(0)
#define MWIFIEX_BD_FLAG_EOP				BIT(1)
#define MWIFIEX_BD_FLAG_XS_SOP				BIT(2)
#define MWIFIEX_BD_FLAG_XS_EOP				BIT(3)
#define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND		BIT(7)
#define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND			BIT(10)
#define MWIFIEX_BD_FLAG_TX_START_PTR			BIT(16)
#define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND			BIT(26)

/* Max retry number of command write */
#define MAX_WRITE_IOMEM_RETRY				2
/* Define PCIE block size for firmware download */
#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD		256
/* FW awake cookie after FW ready */
#define FW_AWAKE_COOKIE						(0xAA55AA55)
#define MWIFIEX_DEF_SLEEP_COOKIE			0xBEEFBEEF
#define MWIFIEX_MAX_DELAY_COUNT				5

struct mwifiex_pcie_card_reg {
	u16 cmd_addr_lo;
	u16 cmd_addr_hi;
	u16 fw_status;
	u16 cmd_size;
	u16 cmdrsp_addr_lo;
	u16 cmdrsp_addr_hi;
	u16 tx_rdptr;
	u16 tx_wrptr;
	u16 rx_rdptr;
	u16 rx_wrptr;
	u16 evt_rdptr;
	u16 evt_wrptr;
	u16 drv_rdy;
	u16 tx_start_ptr;
	u32 tx_mask;
	u32 tx_wrap_mask;
	u32 rx_mask;
	u32 rx_wrap_mask;
	u32 tx_rollover_ind;
	u32 rx_rollover_ind;
	u32 evt_rollover_ind;
	u8 ring_flag_sop;
	u8 ring_flag_eop;
	u8 ring_flag_xs_sop;
	u8 ring_flag_xs_eop;
	u32 ring_tx_start_ptr;
	u8 pfu_enabled;
	u8 sleep_cookie;
	u16 fw_dump_ctrl;
	u16 fw_dump_start;
	u16 fw_dump_end;
	u8 fw_dump_host_ready;
	u8 fw_dump_read_done;
	u8 msix_support;
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = PCIE_SCRATCH_6_REG,
	.tx_wrptr = PCIE_SCRATCH_7_REG,
	.rx_rdptr = PCIE_SCRATCH_8_REG,
	.rx_wrptr = PCIE_SCRATCH_9_REG,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 0,
	.tx_mask = MWIFIEX_TXBD_MASK,
	.tx_wrap_mask = 0,
	.rx_mask = MWIFIEX_RXBD_MASK,
	.rx_wrap_mask = 0,
	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.ring_flag_sop = 0,
	.ring_flag_eop = 0,
	.ring_flag_xs_sop = 0,
	.ring_flag_xs_eop = 0,
	.ring_tx_start_ptr = 0,
	.pfu_enabled = 0,
	.sleep_cookie = 1,
	.msix_support = 0,
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 16,
	.tx_mask = 0x03FF0000,
	.tx_wrap_mask = 0x07FF0000,
	.rx_mask = 0x000003FF,
	.rx_wrap_mask = 0x000007FF,
	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	.pfu_enabled = 1,
	.sleep_cookie = 0,
	.fw_dump_ctrl = 0xcf4,
	.fw_dump_start = 0xcf8,
	.fw_dump_end = 0xcff,
	.fw_dump_host_ready = 0xee,
	.fw_dump_read_done = 0xfe,
	.msix_support = 0,
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = 0xC1A4,
	.tx_wrptr = 0xC174,
	.rx_rdptr = 0xC174,
	.rx_wrptr = 0xC1A4,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 16,
	.tx_mask = 0x0FFF0000,
	.tx_wrap_mask = 0x1FFF0000,
	.rx_mask = 0x00000FFF,
	.rx_wrap_mask = 0x00001FFF,
	.tx_rollover_ind = BIT(28),
	.rx_rollover_ind = BIT(12),
	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	.pfu_enabled = 1,
	.sleep_cookie = 0,
	.fw_dump_ctrl = 0xcf4,
	.fw_dump_start = 0xcf8,
	.fw_dump_end = 0xcff,
	.fw_dump_host_ready = 0xcc,
	.fw_dump_read_done = 0xdd,
	.msix_support = 1,
};

static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
	{"ITCM", NULL, 0, 0xF0},
	{"DTCM", NULL, 0, 0xF1},
	{"SQRAM", NULL, 0, 0xF2},
	{"IRAM", NULL, 0, 0xF3},
	{"APU", NULL, 0, 0xF4},
	{"CIU", NULL, 0, 0xF5},
	{"ICU", NULL, 0, 0xF6},
	{"MAC", NULL, 0, 0xF7},
};

static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
	{"DUMP", NULL, 0, 0xDD},
};

struct mwifiex_pcie_device {
	const struct mwifiex_pcie_card_reg *reg;
	u16 blksz_fw_dl;
	u16 tx_buf_size;
	bool can_dump_fw;
	struct memory_type_mapping *mem_type_mapping_tbl;
	u8 num_mem_types;
	bool can_ext_scan;
};

static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
	.reg            = &mwifiex_reg_8766,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.can_dump_fw = false,
	.can_ext_scan = true,
};

static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
	.reg            = &mwifiex_reg_8897,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	.can_dump_fw = true,
	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
	.can_ext_scan = true,
};

static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
	.reg            = &mwifiex_reg_8997,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	.can_dump_fw = true,
	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
	.can_ext_scan = true,
};

struct mwifiex_evt_buf_desc {
	u64 paddr;
	u16 len;
	u16 flags;
} __packed;

struct mwifiex_pcie_buf_desc {
	u64 paddr;
	u16 len;
	u16 flags;
} __packed;

struct mwifiex_pfu_buf_desc {
	u16 flags;
	u16 offset;
	u16 frag_len;
	u16 len;
	u64 paddr;
	u32 reserved;
} __packed;

#define MWIFIEX_NUM_MSIX_VECTORS   4

struct mwifiex_msix_context {
	struct pci_dev *dev;
	u16 msg_id;
};

struct pcie_service_card {
	struct pci_dev *dev;
	struct mwifiex_adapter *adapter;
	struct mwifiex_pcie_device pcie;

	u8 txbd_flush;
	u32 txbd_wrptr;
	u32 txbd_rdptr;
	u32 txbd_ring_size;
	u8 *txbd_ring_vbase;
	dma_addr_t txbd_ring_pbase;
	void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];

	u32 rxbd_wrptr;
	u32 rxbd_rdptr;
	u32 rxbd_ring_size;
	u8 *rxbd_ring_vbase;
	dma_addr_t rxbd_ring_pbase;
	void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];

	u32 evtbd_wrptr;
	u32 evtbd_rdptr;
	u32 evtbd_ring_size;
	u8 *evtbd_ring_vbase;
	dma_addr_t evtbd_ring_pbase;
	void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];

	struct sk_buff *cmd_buf;
	struct sk_buff *cmdrsp_buf;
	u8 *sleep_cookie_vbase;
	dma_addr_t sleep_cookie_pbase;
	void __iomem *pci_mmap;
	void __iomem *pci_mmap1;
	int msi_enable;
	int msix_enable;
#ifdef CONFIG_PCI
	struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
#endif
	struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
	struct mwifiex_msix_context share_irq_ctx;
};

static inline int
mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
{
	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;

	switch (card->dev->device) {
	case PCIE_DEVICE_ID_MARVELL_88W8766P:
		if (((card->txbd_wrptr & reg->tx_mask) ==
		     (rdptr & reg->tx_mask)) &&
		    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
		     (rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	case PCIE_DEVICE_ID_MARVELL_88W8897:
	case PCIE_DEVICE_ID_MARVELL_88W8997:
		if (((card->txbd_wrptr & reg->tx_mask) ==
		     (rdptr & reg->tx_mask)) &&
		    ((card->txbd_wrptr & reg->tx_rollover_ind) ==
			(rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	}

	return 0;
}

static inline int
mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
{
	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;

	switch (card->dev->device) {
	case PCIE_DEVICE_ID_MARVELL_88W8766P:
		if (((card->txbd_wrptr & reg->tx_mask) !=
		     (card->txbd_rdptr & reg->tx_mask)) ||
		    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
		     (card->txbd_rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	case PCIE_DEVICE_ID_MARVELL_88W8897:
	case PCIE_DEVICE_ID_MARVELL_88W8997:
		if (((card->txbd_wrptr & reg->tx_mask) !=
		     (card->txbd_rdptr & reg->tx_mask)) ||
		    ((card->txbd_wrptr & reg->tx_rollover_ind) ==
		     (card->txbd_rdptr & reg->tx_rollover_ind)))
			return 1;
		break;
	}

	return 0;
}

#endif /* _MWIFIEX_PCIE_H */
Commit	Line	Data
d930faee AK	1	/* @file mwifiex_pcie.h
	2	*
	3	* @brief This file contains definitions for PCI-E interface.
	4	* driver.
	5	*
65da33f5	6	* Copyright (C) 2011-2014, Marvell International Ltd.
d930faee AK	7	*
	8	* This software file (the "File") is distributed by Marvell International
	9	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	10	* (the "License"). You may use, redistribute and/or modify this File in
	11	* accordance with the terms and conditions of the License, a copy of which
	12	* is available by writing to the Free Software Foundation, Inc.,
	13	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	14	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	15	*
	16	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	17	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	18	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	19	* this warranty disclaimer.
	20	*/
	21
	22	#ifndef _MWIFIEX_PCIE_H
	23	#define _MWIFIEX_PCIE_H
	24
	25	#include <linux/pci.h>
	26	#include <linux/pcieport_if.h>
	27	#include <linux/interrupt.h>
	28
9a862322	29	#include "decl.h"
d930faee AK	30	#include "main.h"
	31
	32	#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
a362e16b SL	33	#define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin"
a362e16b SL	34	#define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin"
e87650bc SL	35	#define PCIEUART8997_FW_NAME_Z "mrvl/pcieuart8997_combo.bin"
	36	#define PCIEUART8997_FW_NAME_V2 "mrvl/pcieuart8997_combo_v2.bin"
	37	#define PCIEUSB8997_FW_NAME_Z "mrvl/pcieusb8997_combo.bin"
	38	#define PCIEUSB8997_FW_NAME_V2 "mrvl/pcieusb8997_combo_v2.bin"
ca8f2112 AP	39
ca8f2112 AP	40	#define PCIE_VENDOR_ID_MARVELL (0x11ab)
a362e16b	41	#define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b)
ca8f2112 AP	42	#define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
ca8f2112 AP	43	#define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
6d85ef00	44	#define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42)
d930faee	45
a362e16b SL	46	#define PCIE8897_A0 0x1100
	47	#define PCIE8897_B0 0x1200
	48	#define PCIE8997_Z 0x0
	49	#define PCIE8997_V2 0x471
e87650bc	50	#define CHIP_VER_PCIEUSB 0x2
a362e16b	51
d930faee AK	52	/* Constants for Buffer Descriptor (BD) rings */
	53	#define MWIFIEX_MAX_TXRX_BD 0x20
	54	#define MWIFIEX_TXBD_MASK 0x3F
	55	#define MWIFIEX_RXBD_MASK 0x3F
	56
2703a668 AP	57	#define MWIFIEX_MAX_EVT_BD 0x08
2703a668 AP	58	#define MWIFIEX_EVTBD_MASK 0x0f
d930faee AK	59
	60	/* PCIE INTERNAL REGISTERS */
	61	#define PCIE_SCRATCH_0_REG 0xC10
	62	#define PCIE_SCRATCH_1_REG 0xC14
	63	#define PCIE_CPU_INT_EVENT 0xC18
	64	#define PCIE_CPU_INT_STATUS 0xC1C
	65	#define PCIE_HOST_INT_STATUS 0xC30
	66	#define PCIE_HOST_INT_MASK 0xC34
	67	#define PCIE_HOST_INT_STATUS_MASK 0xC3C
	68	#define PCIE_SCRATCH_2_REG 0xC40
	69	#define PCIE_SCRATCH_3_REG 0xC44
428ca8a7 BZ	70	#define PCIE_SCRATCH_4_REG 0xCD0
	71	#define PCIE_SCRATCH_5_REG 0xCD4
	72	#define PCIE_SCRATCH_6_REG 0xCD8
	73	#define PCIE_SCRATCH_7_REG 0xCDC
	74	#define PCIE_SCRATCH_8_REG 0xCE0
	75	#define PCIE_SCRATCH_9_REG 0xCE4
	76	#define PCIE_SCRATCH_10_REG 0xCE8
	77	#define PCIE_SCRATCH_11_REG 0xCEC
	78	#define PCIE_SCRATCH_12_REG 0xCF0
4646968b XH	79	#define PCIE_SCRATCH_13_REG 0xCF8
4646968b XH	80	#define PCIE_SCRATCH_14_REG 0xCFC
ca8f2112 AP	81	#define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C
ca8f2112 AP	82	#define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C
d930faee AK	83
	84	#define CPU_INTR_DNLD_RDY BIT(0)
	85	#define CPU_INTR_DOOR_BELL BIT(1)
	86	#define CPU_INTR_SLEEP_CFM_DONE BIT(2)
	87	#define CPU_INTR_RESET BIT(3)
2703a668	88	#define CPU_INTR_EVENT_DONE BIT(5)
d930faee AK	89
	90	#define HOST_INTR_DNLD_DONE BIT(0)
	91	#define HOST_INTR_UPLD_RDY BIT(1)
	92	#define HOST_INTR_CMD_DONE BIT(2)
	93	#define HOST_INTR_EVENT_RDY BIT(3)
	94	#define HOST_INTR_MASK (HOST_INTR_DNLD_DONE \| \
	95	HOST_INTR_UPLD_RDY \| \
	96	HOST_INTR_CMD_DONE \| \
	97	HOST_INTR_EVENT_RDY)
	98
	99	#define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
	100	#define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
	101	#define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
ca8f2112 AP	102	#define MWIFIEX_BD_FLAG_SOP BIT(0)
	103	#define MWIFIEX_BD_FLAG_EOP BIT(1)
	104	#define MWIFIEX_BD_FLAG_XS_SOP BIT(2)
	105	#define MWIFIEX_BD_FLAG_XS_EOP BIT(3)
	106	#define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7)
	107	#define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10)
	108	#define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16)
	109	#define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26)
d930faee AK	110
	111	/* Max retry number of command write */
	112	#define MAX_WRITE_IOMEM_RETRY 2
	113	/* Define PCIE block size for firmware download */
	114	#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
	115	/* FW awake cookie after FW ready */
	116	#define FW_AWAKE_COOKIE (0xAA55AA55)
c4bc980f AP	117	#define MWIFIEX_DEF_SLEEP_COOKIE 0xBEEFBEEF
c4bc980f AP	118	#define MWIFIEX_MAX_DELAY_COUNT 5
d930faee	119
dd04e6ac AP	120	struct mwifiex_pcie_card_reg {
	121	u16 cmd_addr_lo;
	122	u16 cmd_addr_hi;
	123	u16 fw_status;
	124	u16 cmd_size;
	125	u16 cmdrsp_addr_lo;
	126	u16 cmdrsp_addr_hi;
	127	u16 tx_rdptr;
	128	u16 tx_wrptr;
	129	u16 rx_rdptr;
	130	u16 rx_wrptr;
	131	u16 evt_rdptr;
	132	u16 evt_wrptr;
	133	u16 drv_rdy;
	134	u16 tx_start_ptr;
	135	u32 tx_mask;
	136	u32 tx_wrap_mask;
	137	u32 rx_mask;
	138	u32 rx_wrap_mask;
	139	u32 tx_rollover_ind;
	140	u32 rx_rollover_ind;
	141	u32 evt_rollover_ind;
	142	u8 ring_flag_sop;
	143	u8 ring_flag_eop;
	144	u8 ring_flag_xs_sop;
	145	u8 ring_flag_xs_eop;
	146	u32 ring_tx_start_ptr;
	147	u8 pfu_enabled;
52301a81	148	u8 sleep_cookie;
92c2538f AK	149	u16 fw_dump_ctrl;
	150	u16 fw_dump_start;
	151	u16 fw_dump_end;
50632092 XH	152	u8 fw_dump_host_ready;
50632092 XH	153	u8 fw_dump_read_done;
99074fc1	154	u8 msix_support;
dd04e6ac AP	155	};
	156
	157	static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	158	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	159	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	160	.cmd_size = PCIE_SCRATCH_2_REG,
	161	.fw_status = PCIE_SCRATCH_3_REG,
	162	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	163	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	164	.tx_rdptr = PCIE_SCRATCH_6_REG,
	165	.tx_wrptr = PCIE_SCRATCH_7_REG,
	166	.rx_rdptr = PCIE_SCRATCH_8_REG,
	167	.rx_wrptr = PCIE_SCRATCH_9_REG,
	168	.evt_rdptr = PCIE_SCRATCH_10_REG,
	169	.evt_wrptr = PCIE_SCRATCH_11_REG,
	170	.drv_rdy = PCIE_SCRATCH_12_REG,
	171	.tx_start_ptr = 0,
	172	.tx_mask = MWIFIEX_TXBD_MASK,
	173	.tx_wrap_mask = 0,
	174	.rx_mask = MWIFIEX_RXBD_MASK,
	175	.rx_wrap_mask = 0,
	176	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	177	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	178	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	179	.ring_flag_sop = 0,
	180	.ring_flag_eop = 0,
	181	.ring_flag_xs_sop = 0,
	182	.ring_flag_xs_eop = 0,
	183	.ring_tx_start_ptr = 0,
	184	.pfu_enabled = 0,
52301a81	185	.sleep_cookie = 1,
99074fc1	186	.msix_support = 0,
dd04e6ac AP	187	};
dd04e6ac AP	188
ca8f2112 AP	189	static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
	190	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	191	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	192	.cmd_size = PCIE_SCRATCH_2_REG,
	193	.fw_status = PCIE_SCRATCH_3_REG,
	194	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	195	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	196	.tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1,
	197	.tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1,
	198	.rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1,
	199	.rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1,
	200	.evt_rdptr = PCIE_SCRATCH_10_REG,
	201	.evt_wrptr = PCIE_SCRATCH_11_REG,
	202	.drv_rdy = PCIE_SCRATCH_12_REG,
	203	.tx_start_ptr = 16,
	204	.tx_mask = 0x03FF0000,
	205	.tx_wrap_mask = 0x07FF0000,
	206	.rx_mask = 0x000003FF,
	207	.rx_wrap_mask = 0x000007FF,
	208	.tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND,
	209	.rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND,
	210	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	211	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	212	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	213	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	214	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	215	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	216	.pfu_enabled = 1,
52301a81	217	.sleep_cookie = 0,
92c2538f AK	218	.fw_dump_ctrl = 0xcf4,
92c2538f AK	219	.fw_dump_start = 0xcf8,
6d85ef00	220	.fw_dump_end = 0xcff,
50632092 XH	221	.fw_dump_host_ready = 0xee,
50632092 XH	222	.fw_dump_read_done = 0xfe,
99074fc1	223	.msix_support = 0,
6d85ef00 ZL	224	};
	225
	226	static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
	227	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	228	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	229	.cmd_size = PCIE_SCRATCH_2_REG,
	230	.fw_status = PCIE_SCRATCH_3_REG,
	231	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	232	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	233	.tx_rdptr = 0xC1A4,
ce0c58d9 AK	234	.tx_wrptr = 0xC174,
ce0c58d9 AK	235	.rx_rdptr = 0xC174,
6d85ef00 ZL	236	.rx_wrptr = 0xC1A4,
	237	.evt_rdptr = PCIE_SCRATCH_10_REG,
	238	.evt_wrptr = PCIE_SCRATCH_11_REG,
	239	.drv_rdy = PCIE_SCRATCH_12_REG,
	240	.tx_start_ptr = 16,
	241	.tx_mask = 0x0FFF0000,
ce0c58d9	242	.tx_wrap_mask = 0x1FFF0000,
6d85ef00	243	.rx_mask = 0x00000FFF,
ce0c58d9	244	.rx_wrap_mask = 0x00001FFF,
6d85ef00 ZL	245	.tx_rollover_ind = BIT(28),
	246	.rx_rollover_ind = BIT(12),
	247	.evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND,
	248	.ring_flag_sop = MWIFIEX_BD_FLAG_SOP,
	249	.ring_flag_eop = MWIFIEX_BD_FLAG_EOP,
	250	.ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP,
	251	.ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP,
	252	.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
	253	.pfu_enabled = 1,
	254	.sleep_cookie = 0,
11e70824 XH	255	.fw_dump_ctrl = 0xcf4,
	256	.fw_dump_start = 0xcf8,
	257	.fw_dump_end = 0xcff,
	258	.fw_dump_host_ready = 0xcc,
	259	.fw_dump_read_done = 0xdd,
99074fc1	260	.msix_support = 1,
ca8f2112 AP	261	};
ca8f2112 AP	262
50632092 XH	263	static struct memory_type_mapping mem_type_mapping_tbl_w8897[] = {
	264	{"ITCM", NULL, 0, 0xF0},
	265	{"DTCM", NULL, 0, 0xF1},
	266	{"SQRAM", NULL, 0, 0xF2},
	267	{"IRAM", NULL, 0, 0xF3},
	268	{"APU", NULL, 0, 0xF4},
	269	{"CIU", NULL, 0, 0xF5},
	270	{"ICU", NULL, 0, 0xF6},
	271	{"MAC", NULL, 0, 0xF7},
	272	};
	273
11e70824 XH	274	static struct memory_type_mapping mem_type_mapping_tbl_w8997[] = {
	275	{"DUMP", NULL, 0, 0xDD},
	276	};
	277
dd04e6ac	278	struct mwifiex_pcie_device {
dd04e6ac AP	279	const struct mwifiex_pcie_card_reg *reg;
dd04e6ac AP	280	u16 blksz_fw_dl;
828cf222	281	u16 tx_buf_size;
b4e8aebb	282	bool can_dump_fw;
50632092 XH	283	struct memory_type_mapping *mem_type_mapping_tbl;
50632092 XH	284	u8 num_mem_types;
1fe192d8	285	bool can_ext_scan;
dd04e6ac AP	286	};
	287
	288	static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
dd04e6ac AP	289	.reg = &mwifiex_reg_8766,
dd04e6ac AP	290	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
828cf222	291	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
b4e8aebb	292	.can_dump_fw = false,
1fe192d8	293	.can_ext_scan = true,
dd04e6ac AP	294	};
dd04e6ac AP	295
ca8f2112	296	static const struct mwifiex_pcie_device mwifiex_pcie8897 = {
ca8f2112 AP	297	.reg = &mwifiex_reg_8897,
ca8f2112 AP	298	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
828cf222	299	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
b4e8aebb	300	.can_dump_fw = true,
50632092 XH	301	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8897,
50632092 XH	302	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8897),
1fe192d8	303	.can_ext_scan = true,
ca8f2112 AP	304	};
ca8f2112 AP	305
6d85ef00	306	static const struct mwifiex_pcie_device mwifiex_pcie8997 = {
6d85ef00 ZL	307	.reg = &mwifiex_reg_8997,
	308	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
	309	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
11e70824 XH	310	.can_dump_fw = true,
	311	.mem_type_mapping_tbl = mem_type_mapping_tbl_w8997,
	312	.num_mem_types = ARRAY_SIZE(mem_type_mapping_tbl_w8997),
6d85ef00 ZL	313	.can_ext_scan = true,
	314	};
	315
e05dc3e9 AP	316	struct mwifiex_evt_buf_desc {
	317	u64 paddr;
	318	u16 len;
	319	u16 flags;
	320	} __packed;
	321
d930faee AK	322	struct mwifiex_pcie_buf_desc {
	323	u64 paddr;
	324	u16 len;
	325	u16 flags;
	326	} __packed;
	327
ca8f2112 AP	328	struct mwifiex_pfu_buf_desc {
	329	u16 flags;
	330	u16 offset;
	331	u16 frag_len;
	332	u16 len;
	333	u64 paddr;
	334	u32 reserved;
	335	} __packed;
	336
99074fc1 XH	337	#define MWIFIEX_NUM_MSIX_VECTORS 4
	338
	339	struct mwifiex_msix_context {
	340	struct pci_dev *dev;
	341	u16 msg_id;
	342	};
	343
d930faee AK	344	struct pcie_service_card {
	345	struct pci_dev *dev;
	346	struct mwifiex_adapter *adapter;
dd04e6ac	347	struct mwifiex_pcie_device pcie;
d930faee	348
fbd7e7ac	349	u8 txbd_flush;
d930faee AK	350	u32 txbd_wrptr;
	351	u32 txbd_rdptr;
	352	u32 txbd_ring_size;
	353	u8 *txbd_ring_vbase;
fc331460	354	dma_addr_t txbd_ring_pbase;
e05dc3e9	355	void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
d930faee AK	356	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
	357
	358	u32 rxbd_wrptr;
	359	u32 rxbd_rdptr;
	360	u32 rxbd_ring_size;
	361	u8 *rxbd_ring_vbase;
fc331460	362	dma_addr_t rxbd_ring_pbase;
e05dc3e9	363	void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
d930faee AK	364	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
	365
	366	u32 evtbd_wrptr;
	367	u32 evtbd_rdptr;
	368	u32 evtbd_ring_size;
	369	u8 *evtbd_ring_vbase;
fc331460	370	dma_addr_t evtbd_ring_pbase;
e05dc3e9	371	void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
d930faee AK	372	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
	373
	374	struct sk_buff *cmd_buf;
	375	struct sk_buff *cmdrsp_buf;
fc331460 AP	376	u8 *sleep_cookie_vbase;
fc331460 AP	377	dma_addr_t sleep_cookie_pbase;
d930faee AK	378	void __iomem *pci_mmap;
d930faee AK	379	void __iomem *pci_mmap1;
7be0f5b5	380	int msi_enable;
99074fc1 XH	381	int msix_enable;
	382	#ifdef CONFIG_PCI
	383	struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
	384	#endif
	385	struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
	386	struct mwifiex_msix_context share_irq_ctx;
d930faee AK	387	};
d930faee AK	388
fbd7e7ac AP	389	static inline int
	390	mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
	391	{
dd04e6ac AP	392	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
dd04e6ac AP	393
ca8f2112 AP	394	switch (card->dev->device) {
	395	case PCIE_DEVICE_ID_MARVELL_88W8766P:
	396	if (((card->txbd_wrptr & reg->tx_mask) ==
	397	(rdptr & reg->tx_mask)) &&
	398	((card->txbd_wrptr & reg->tx_rollover_ind) !=
	399	(rdptr & reg->tx_rollover_ind)))
	400	return 1;
	401	break;
	402	case PCIE_DEVICE_ID_MARVELL_88W8897:
f3b35f28	403	case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112 AP	404	if (((card->txbd_wrptr & reg->tx_mask) ==
	405	(rdptr & reg->tx_mask)) &&
	406	((card->txbd_wrptr & reg->tx_rollover_ind) ==
dd04e6ac	407	(rdptr & reg->tx_rollover_ind)))
ca8f2112 AP	408	return 1;
	409	break;
	410	}
fbd7e7ac AP	411
	412	return 0;
	413	}
	414
e7f767a7 AP	415	static inline int
	416	mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
	417	{
dd04e6ac AP	418	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
dd04e6ac AP	419
ca8f2112 AP	420	switch (card->dev->device) {
	421	case PCIE_DEVICE_ID_MARVELL_88W8766P:
	422	if (((card->txbd_wrptr & reg->tx_mask) !=
	423	(card->txbd_rdptr & reg->tx_mask)) \|\|
	424	((card->txbd_wrptr & reg->tx_rollover_ind) !=
	425	(card->txbd_rdptr & reg->tx_rollover_ind)))
	426	return 1;
	427	break;
	428	case PCIE_DEVICE_ID_MARVELL_88W8897:
6d85ef00	429	case PCIE_DEVICE_ID_MARVELL_88W8997:
ca8f2112 AP	430	if (((card->txbd_wrptr & reg->tx_mask) !=
	431	(card->txbd_rdptr & reg->tx_mask)) \|\|
	432	((card->txbd_wrptr & reg->tx_rollover_ind) ==
	433	(card->txbd_rdptr & reg->tx_rollover_ind)))
	434	return 1;
	435	break;
	436	}
e7f767a7 AP	437
	438	return 0;
	439	}
92c2538f	440
d930faee	441	#endif /* _MWIFIEX_PCIE_H */