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mwifiex: add platform specific wakeup interrupt support
[deliverable/linux.git] / drivers / net / wireless / marvell / mwifiex / sdio.h
CommitLineData
5e6e3a92
BZ		 1/*
2 * Marvell Wireless LAN device driver: SDIO specific definitions
3 *
65da33f5 4 * Copyright (C) 2011-2014, Marvell International Ltd.
5e6e3a92
BZ		 5 *
6 * This software file (the "File") is distributed by Marvell International
7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
8 * (the "License"). You may use, redistribute and/or modify this File in
9 * accordance with the terms and conditions of the License, a copy of which
10 * is available by writing to the Free Software Foundation, Inc.,
11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
13 *
14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about
17 * this warranty disclaimer.
18 */
19
20#ifndef _MWIFIEX_SDIO_H
21#define _MWIFIEX_SDIO_H
22
23
24#include <linux/mmc/sdio.h>
25#include <linux/mmc/sdio_ids.h>
26#include <linux/mmc/sdio_func.h>
27#include <linux/mmc/card.h>
d31ab357 28#include <linux/mmc/host.h>
5e6e3a92
BZ		 29
30#include "main.h"
31
98e6b9df 32#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
4a7f5db1 33#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
e3bea1c8 34#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
b60186f8 35#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
030bb75a 36#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin"
52bd3d20 37#define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin"
6d85ef00 38#define SD8997_DEFAULT_FW_NAME "mrvl/sd8997_uapsta.bin"
4a7f5db1 39
5e6e3a92
BZ		 40#define BLOCK_MODE 1
41#define BYTE_MODE 0
42
43#define REG_PORT 0
5e6e3a92
BZ		 44
45#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
46
47#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
48
809c6ea8
XH		 49#define MWIFIEX_MAX_FUNC2_REG_NUM 13
50#define MWIFIEX_SDIO_SCRATCH_SIZE 10
51
248eb4c6 52#define SDIO_MPA_ADDR_BASE 0x1000
5e6e3a92
BZ		 53#define CTRL_PORT 0
54#define CTRL_PORT_MASK 0x0001
5e6e3a92 55
b60186f8
YAP		 56#define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
57#define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
58#define HOST_TERM_CMD53 (0x1U << 2)
59#define REG_PORT 0
60#define MEM_PORT 0x10000
554a0113 61
b60186f8 62#define CMD53_NEW_MODE (0x1U << 0)
b60186f8 63#define CMD_PORT_RD_LEN_EN (0x1U << 2)
b60186f8
YAP		 64#define CMD_PORT_AUTO_EN (0x1U << 0)
65#define CMD_PORT_SLCT 0x8000
66#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
67#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
68
e1aa93a4
AK		 69#define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
70#define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
ea44f4d0
AP		 71/* we leave one block of 256 bytes for DMA alignment*/
72#define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280)
5e6e3a92
BZ		 73
74/* Misc. Config Register : Auto Re-enable interrupts */
75#define AUTO_RE_ENABLE_INT BIT(4)
76
5e6e3a92
BZ		 77/* Host Control Registers : Configuration */
78#define CONFIGURATION_REG 0x00
5e6e3a92
BZ		 79/* Host Control Registers : Host power up */
80#define HOST_POWER_UP (0x1U << 1)
5e6e3a92 81
5e6e3a92
BZ		 82/* Host Control Registers : Upload host interrupt mask */
83#define UP_LD_HOST_INT_MASK (0x1U)
84/* Host Control Registers : Download host interrupt mask */
85#define DN_LD_HOST_INT_MASK (0x2U)
b60186f8 86
5e6e3a92
BZ		 87/* Host Control Registers : Upload host interrupt status */
88#define UP_LD_HOST_INT_STATUS (0x1U)
89/* Host Control Registers : Download host interrupt status */
90#define DN_LD_HOST_INT_STATUS (0x2U)
91
5e6e3a92 92/* Host Control Registers : Host interrupt status */
554a0113 93#define CARD_INT_STATUS_REG 0x28
5e6e3a92 94
5e6e3a92
BZ		 95/* Card Control Registers : Card I/O ready */
96#define CARD_IO_READY (0x1U << 3)
5e6e3a92
BZ		 97/* Card Control Registers : Download card ready */
98#define DN_LD_CARD_RDY (0x1U << 0)
99
5e6e3a92
BZ		 100/* Max retry number of CMD53 write */
101#define MAX_WRITE_IOMEM_RETRY 2
102
103/* SDIO Tx aggregation in progress ? */
104#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
105
106/* SDIO Tx aggregation buffer room for next packet ? */
107#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
108 <= a->mpa_tx.buf_size)
109
110/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
111#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
112 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
113 payload, pkt_len); \
114 a->mpa_tx.buf_len += pkt_len; \
115 if (!a->mpa_tx.pkt_cnt) \
116 a->mpa_tx.start_port = port; \
117 if (a->mpa_tx.start_port <= port) \
118 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \
119 else \
05889f82
AK		 120 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \
121 (a->max_ports - \
5e6e3a92
BZ		 122 a->mp_end_port))); \
123 a->mpa_tx.pkt_cnt++; \
da951c24 124} while (0)
5e6e3a92
BZ		 125
126/* SDIO Tx aggregation limit ? */
127#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
128 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
129
5e6e3a92
BZ		 130/* Reset SDIO Tx aggregation buffer parameters */
131#define MP_TX_AGGR_BUF_RESET(a) do { \
132 a->mpa_tx.pkt_cnt = 0; \
133 a->mpa_tx.buf_len = 0; \
134 a->mpa_tx.ports = 0; \
135 a->mpa_tx.start_port = 0; \
da951c24 136} while (0)
5e6e3a92
BZ		 137
138/* SDIO Rx aggregation limit ? */
139#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
140 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
141
5e6e3a92
BZ		 142/* SDIO Rx aggregation in progress ? */
143#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
144
145/* SDIO Rx aggregation buffer room for next packet ? */
146#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
147 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
148
5e6e3a92
BZ		 149/* Reset SDIO Rx aggregation buffer parameters */
150#define MP_RX_AGGR_BUF_RESET(a) do { \
151 a->mpa_rx.pkt_cnt = 0; \
152 a->mpa_rx.buf_len = 0; \
153 a->mpa_rx.ports = 0; \
154 a->mpa_rx.start_port = 0; \
da951c24 155} while (0)
5e6e3a92 156
ce4f6f0c
XH		 157struct mwifiex_plt_wake_cfg {
158 int irq_wifi;
159 bool wake_by_wifi;
160};
161
5e6e3a92
BZ		 162/* data structure for SDIO MPA TX */
163struct mwifiex_sdio_mpa_tx {
164 /* multiport tx aggregation buffer pointer */
165 u8 *buf;
166 u32 buf_len;
167 u32 pkt_cnt;
5ac253d5 168 u32 ports;
5e6e3a92
BZ		 169 u16 start_port;
170 u8 enabled;
171 u32 buf_size;
172 u32 pkt_aggr_limit;
173};
174
175struct mwifiex_sdio_mpa_rx {
176 u8 *buf;
177 u32 buf_len;
178 u32 pkt_cnt;
5ac253d5 179 u32 ports;
5e6e3a92
BZ		 180 u16 start_port;
181
c23b7c8f
AK		 182 struct sk_buff **skb_arr;
183 u32 *len_arr;
5e6e3a92
BZ		 184
185 u8 enabled;
186 u32 buf_size;
187 u32 pkt_aggr_limit;
188};
189
190int mwifiex_bus_register(void);
191void mwifiex_bus_unregister(void);
192
05889f82
AK		 193struct mwifiex_sdio_card_reg {
194 u8 start_rd_port;
195 u8 start_wr_port;
196 u8 base_0_reg;
197 u8 base_1_reg;
198 u8 poll_reg;
199 u8 host_int_enable;
554a0113
AP		 200 u8 host_int_rsr_reg;
201 u8 host_int_status_reg;
202 u8 host_int_mask_reg;
05889f82
AK		 203 u8 status_reg_0;
204 u8 status_reg_1;
205 u8 sdio_int_mask;
206 u32 data_port_mask;
554a0113
AP		 207 u8 io_port_0_reg;
208 u8 io_port_1_reg;
209 u8 io_port_2_reg;
05889f82
AK		 210 u8 max_mp_regs;
211 u8 rd_bitmap_l;
212 u8 rd_bitmap_u;
b60186f8
YAP		 213 u8 rd_bitmap_1l;
214 u8 rd_bitmap_1u;
05889f82
AK		 215 u8 wr_bitmap_l;
216 u8 wr_bitmap_u;
b60186f8
YAP		 217 u8 wr_bitmap_1l;
218 u8 wr_bitmap_1u;
05889f82
AK		 219 u8 rd_len_p0_l;
220 u8 rd_len_p0_u;
221 u8 card_misc_cfg_reg;
554a0113
AP		 222 u8 card_cfg_2_1_reg;
223 u8 cmd_rd_len_0;
224 u8 cmd_rd_len_1;
225 u8 cmd_rd_len_2;
226 u8 cmd_rd_len_3;
227 u8 cmd_cfg_0;
228 u8 cmd_cfg_1;
229 u8 cmd_cfg_2;
230 u8 cmd_cfg_3;
eee7f196 231 u8 fw_dump_host_ready;
54881c6b
AK		 232 u8 fw_dump_ctrl;
233 u8 fw_dump_start;
234 u8 fw_dump_end;
809c6ea8
XH		 235 u8 func1_dump_reg_start;
236 u8 func1_dump_reg_end;
237 u8 func1_scratch_reg;
238 u8 func1_spec_reg_num;
239 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM];
05889f82
AK		 240};
241
5e6e3a92
BZ		 242struct sdio_mmc_card {
243 struct sdio_func *func;
244 struct mwifiex_adapter *adapter;
ce4f6f0c
XH		 245 struct device_node *plt_of_node;
246 struct mwifiex_plt_wake_cfg *plt_wake_cfg;
5e6e3a92 247
05889f82
AK		 248 const char *firmware;
249 const struct mwifiex_sdio_card_reg *reg;
250 u8 max_ports;
251 u8 mp_agg_pkt_limit;
828cf222 252 u16 tx_buf_size;
e1aa93a4
AK		 253 u32 mp_tx_agg_buf_size;
254 u32 mp_rx_agg_buf_size;
05889f82 255
5ac253d5
AK		 256 u32 mp_rd_bitmap;
257 u32 mp_wr_bitmap;
5e6e3a92
BZ		 258
259 u16 mp_end_port;
5ac253d5 260 u32 mp_data_port_mask;
5e6e3a92
BZ		 261
262 u8 curr_rd_port;
263 u8 curr_wr_port;
264
265 u8 *mp_regs;
b4e8aebb
AP		 266 bool supports_sdio_new_mode;
267 bool has_control_mask;
268 bool can_dump_fw;
eee7f196 269 bool fw_dump_enh;
b4e8aebb 270 bool can_auto_tdls;
1fe192d8 271 bool can_ext_scan;
5e6e3a92
BZ		 272
273 struct mwifiex_sdio_mpa_tx mpa_tx;
274 struct mwifiex_sdio_mpa_rx mpa_rx;
b4336a28
AF		 275
276 /* needed for card reset */
277 const struct sdio_device_id *device_id;
5e6e3a92 278};
d930faee 279
05889f82
AK		 280struct mwifiex_sdio_device {
281 const char *firmware;
282 const struct mwifiex_sdio_card_reg *reg;
283 u8 max_ports;
284 u8 mp_agg_pkt_limit;
828cf222 285 u16 tx_buf_size;
e1aa93a4
AK		 286 u32 mp_tx_agg_buf_size;
287 u32 mp_rx_agg_buf_size;
b4e8aebb
AP		 288 bool supports_sdio_new_mode;
289 bool has_control_mask;
290 bool can_dump_fw;
eee7f196 291 bool fw_dump_enh;
b4e8aebb 292 bool can_auto_tdls;
1fe192d8 293 bool can_ext_scan;
05889f82
AK		 294};
295
296static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
297 .start_rd_port = 1,
298 .start_wr_port = 1,
299 .base_0_reg = 0x0040,
300 .base_1_reg = 0x0041,
301 .poll_reg = 0x30,
302 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
554a0113
AP		 303 .host_int_rsr_reg = 0x1,
304 .host_int_mask_reg = 0x02,
305 .host_int_status_reg = 0x03,
05889f82
AK		 306 .status_reg_0 = 0x60,
307 .status_reg_1 = 0x61,
308 .sdio_int_mask = 0x3f,
309 .data_port_mask = 0x0000fffe,
554a0113
AP		 310 .io_port_0_reg = 0x78,
311 .io_port_1_reg = 0x79,
312 .io_port_2_reg = 0x7A,
05889f82
AK		 313 .max_mp_regs = 64,
314 .rd_bitmap_l = 0x04,
315 .rd_bitmap_u = 0x05,
316 .wr_bitmap_l = 0x06,
317 .wr_bitmap_u = 0x07,
318 .rd_len_p0_l = 0x08,
319 .rd_len_p0_u = 0x09,
320 .card_misc_cfg_reg = 0x6c,
809c6ea8
XH		 321 .func1_dump_reg_start = 0x0,
322 .func1_dump_reg_end = 0x9,
323 .func1_scratch_reg = 0x60,
324 .func1_spec_reg_num = 5,
325 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c},
05889f82
AK		 326};
327
b60186f8
YAP		 328static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
329 .start_rd_port = 0,
330 .start_wr_port = 0,
331 .base_0_reg = 0x60,
332 .base_1_reg = 0x61,
333 .poll_reg = 0x50,
334 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
335 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
554a0113
AP		 336 .host_int_rsr_reg = 0x1,
337 .host_int_status_reg = 0x03,
338 .host_int_mask_reg = 0x02,
b60186f8
YAP		 339 .status_reg_0 = 0xc0,
340 .status_reg_1 = 0xc1,
341 .sdio_int_mask = 0xff,
342 .data_port_mask = 0xffffffff,
554a0113
AP		 343 .io_port_0_reg = 0xD8,
344 .io_port_1_reg = 0xD9,
345 .io_port_2_reg = 0xDA,
b60186f8
YAP		 346 .max_mp_regs = 184,
347 .rd_bitmap_l = 0x04,
348 .rd_bitmap_u = 0x05,
349 .rd_bitmap_1l = 0x06,
350 .rd_bitmap_1u = 0x07,
351 .wr_bitmap_l = 0x08,
352 .wr_bitmap_u = 0x09,
353 .wr_bitmap_1l = 0x0a,
354 .wr_bitmap_1u = 0x0b,
355 .rd_len_p0_l = 0x0c,
356 .rd_len_p0_u = 0x0d,
357 .card_misc_cfg_reg = 0xcc,
554a0113
AP		 358 .card_cfg_2_1_reg = 0xcd,
359 .cmd_rd_len_0 = 0xb4,
360 .cmd_rd_len_1 = 0xb5,
361 .cmd_rd_len_2 = 0xb6,
362 .cmd_rd_len_3 = 0xb7,
363 .cmd_cfg_0 = 0xb8,
364 .cmd_cfg_1 = 0xb9,
365 .cmd_cfg_2 = 0xba,
366 .cmd_cfg_3 = 0xbb,
eee7f196 367 .fw_dump_host_ready = 0xee,
54881c6b
AK		 368 .fw_dump_ctrl = 0xe2,
369 .fw_dump_start = 0xe3,
370 .fw_dump_end = 0xea,
809c6ea8
XH		 371 .func1_dump_reg_start = 0x0,
372 .func1_dump_reg_end = 0xb,
373 .func1_scratch_reg = 0xc0,
374 .func1_spec_reg_num = 8,
375 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58,
376 0x59, 0x5c, 0x5d},
b60186f8
YAP		 377};
378
6d85ef00
ZL		 379static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8997 = {
380 .start_rd_port = 0,
381 .start_wr_port = 0,
382 .base_0_reg = 0xF8,
383 .base_1_reg = 0xF9,
384 .poll_reg = 0x5C,
385 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
386 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
387 .host_int_rsr_reg = 0x4,
388 .host_int_status_reg = 0x0C,
389 .host_int_mask_reg = 0x08,
390 .status_reg_0 = 0xE8,
391 .status_reg_1 = 0xE9,
392 .sdio_int_mask = 0xff,
393 .data_port_mask = 0xffffffff,
394 .io_port_0_reg = 0xE4,
395 .io_port_1_reg = 0xE5,
396 .io_port_2_reg = 0xE6,
397 .max_mp_regs = 196,
398 .rd_bitmap_l = 0x10,
399 .rd_bitmap_u = 0x11,
400 .rd_bitmap_1l = 0x12,
401 .rd_bitmap_1u = 0x13,
402 .wr_bitmap_l = 0x14,
403 .wr_bitmap_u = 0x15,
404 .wr_bitmap_1l = 0x16,
405 .wr_bitmap_1u = 0x17,
406 .rd_len_p0_l = 0x18,
407 .rd_len_p0_u = 0x19,
408 .card_misc_cfg_reg = 0xd8,
409 .card_cfg_2_1_reg = 0xd9,
410 .cmd_rd_len_0 = 0xc0,
411 .cmd_rd_len_1 = 0xc1,
412 .cmd_rd_len_2 = 0xc2,
413 .cmd_rd_len_3 = 0xc3,
414 .cmd_cfg_0 = 0xc4,
415 .cmd_cfg_1 = 0xc5,
416 .cmd_cfg_2 = 0xc6,
417 .cmd_cfg_3 = 0xc7,
eee7f196
ZL		 418 .fw_dump_host_ready = 0xcc,
419 .fw_dump_ctrl = 0xf0,
420 .fw_dump_start = 0xf1,
421 .fw_dump_end = 0xf8,
6d85ef00
ZL		 422 .func1_dump_reg_start = 0x10,
423 .func1_dump_reg_end = 0x17,
424 .func1_scratch_reg = 0xe8,
425 .func1_spec_reg_num = 13,
426 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D,
427 0x60, 0x61, 0x62, 0x64,
428 0x65, 0x66, 0x68, 0x69,
429 0x6a},
430};
431
030bb75a
AP		 432static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = {
433 .start_rd_port = 0,
434 .start_wr_port = 0,
435 .base_0_reg = 0x6C,
436 .base_1_reg = 0x6D,
437 .poll_reg = 0x5C,
438 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
439 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
440 .host_int_rsr_reg = 0x4,
441 .host_int_status_reg = 0x0C,
442 .host_int_mask_reg = 0x08,
443 .status_reg_0 = 0x90,
444 .status_reg_1 = 0x91,
445 .sdio_int_mask = 0xff,
446 .data_port_mask = 0xffffffff,
447 .io_port_0_reg = 0xE4,
448 .io_port_1_reg = 0xE5,
449 .io_port_2_reg = 0xE6,
450 .max_mp_regs = 196,
451 .rd_bitmap_l = 0x10,
452 .rd_bitmap_u = 0x11,
453 .rd_bitmap_1l = 0x12,
454 .rd_bitmap_1u = 0x13,
455 .wr_bitmap_l = 0x14,
456 .wr_bitmap_u = 0x15,
457 .wr_bitmap_1l = 0x16,
458 .wr_bitmap_1u = 0x17,
459 .rd_len_p0_l = 0x18,
460 .rd_len_p0_u = 0x19,
461 .card_misc_cfg_reg = 0xd8,
462 .card_cfg_2_1_reg = 0xd9,
463 .cmd_rd_len_0 = 0xc0,
464 .cmd_rd_len_1 = 0xc1,
465 .cmd_rd_len_2 = 0xc2,
466 .cmd_rd_len_3 = 0xc3,
467 .cmd_cfg_0 = 0xc4,
468 .cmd_cfg_1 = 0xc5,
469 .cmd_cfg_2 = 0xc6,
470 .cmd_cfg_3 = 0xc7,
809c6ea8
XH		 471 .func1_dump_reg_start = 0x10,
472 .func1_dump_reg_end = 0x17,
473 .func1_scratch_reg = 0x90,
474 .func1_spec_reg_num = 13,
475 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60,
476 0x61, 0x62, 0x64, 0x65, 0x66,
477 0x68, 0x69, 0x6a},
030bb75a
AP		 478};
479
05889f82
AK		 480static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
481 .firmware = SD8786_DEFAULT_FW_NAME,
482 .reg = &mwifiex_reg_sd87xx,
483 .max_ports = 16,
484 .mp_agg_pkt_limit = 8,
828cf222 485 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4
AK		 486 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
487 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb
AP		 488 .supports_sdio_new_mode = false,
489 .has_control_mask = true,
490 .can_dump_fw = false,
491 .can_auto_tdls = false,
1fe192d8 492 .can_ext_scan = false,
05889f82
AK		 493};
494
495static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
496 .firmware = SD8787_DEFAULT_FW_NAME,
497 .reg = &mwifiex_reg_sd87xx,
498 .max_ports = 16,
499 .mp_agg_pkt_limit = 8,
828cf222 500 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4
AK		 501 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
502 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb
AP		 503 .supports_sdio_new_mode = false,
504 .has_control_mask = true,
505 .can_dump_fw = false,
506 .can_auto_tdls = false,
1fe192d8 507 .can_ext_scan = true,
05889f82
AK		 508};
509
510static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
511 .firmware = SD8797_DEFAULT_FW_NAME,
512 .reg = &mwifiex_reg_sd87xx,
513 .max_ports = 16,
514 .mp_agg_pkt_limit = 8,
828cf222 515 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4
AK		 516 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
517 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb
AP		 518 .supports_sdio_new_mode = false,
519 .has_control_mask = true,
520 .can_dump_fw = false,
521 .can_auto_tdls = false,
1fe192d8 522 .can_ext_scan = true,
b60186f8
YAP		 523};
524
525static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
526 .firmware = SD8897_DEFAULT_FW_NAME,
527 .reg = &mwifiex_reg_sd8897,
528 .max_ports = 32,
529 .mp_agg_pkt_limit = 16,
828cf222 530 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
ea44f4d0
AP		 531 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
532 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
b4e8aebb
AP		 533 .supports_sdio_new_mode = true,
534 .has_control_mask = false,
535 .can_dump_fw = true,
536 .can_auto_tdls = false,
6d85ef00
ZL		 537 .can_ext_scan = true,
538};
539
540static const struct mwifiex_sdio_device mwifiex_sdio_sd8997 = {
541 .firmware = SD8997_DEFAULT_FW_NAME,
542 .reg = &mwifiex_reg_sd8997,
543 .max_ports = 32,
544 .mp_agg_pkt_limit = 16,
545 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
546 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
547 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX,
548 .supports_sdio_new_mode = true,
549 .has_control_mask = false,
eee7f196
ZL		 550 .can_dump_fw = true,
551 .fw_dump_enh = true,
6d85ef00 552 .can_auto_tdls = false,
1fe192d8 553 .can_ext_scan = true,
05889f82
AK		 554};
555
030bb75a
AP		 556static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = {
557 .firmware = SD8887_DEFAULT_FW_NAME,
558 .reg = &mwifiex_reg_sd8887,
559 .max_ports = 32,
560 .mp_agg_pkt_limit = 16,
1c4c24eb 561 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
030bb75a
AP		 562 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
563 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
b4e8aebb
AP		 564 .supports_sdio_new_mode = true,
565 .has_control_mask = false,
566 .can_dump_fw = false,
567 .can_auto_tdls = true,
1fe192d8 568 .can_ext_scan = true,
030bb75a
AP		 569};
570
52bd3d20
YAP		 571static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = {
572 .firmware = SD8801_DEFAULT_FW_NAME,
573 .reg = &mwifiex_reg_sd87xx,
574 .max_ports = 16,
575 .mp_agg_pkt_limit = 8,
576 .supports_sdio_new_mode = false,
577 .has_control_mask = true,
578 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
579 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
580 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b4e8aebb
AP		 581 .can_dump_fw = false,
582 .can_auto_tdls = false,
1fe192d8 583 .can_ext_scan = true,
52bd3d20
YAP		 584};
585
d930faee
AK		 586/*
587 * .cmdrsp_complete handler
588 */
589static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
590 struct sk_buff *skb)
591{
592 dev_kfree_skb_any(skb);
593 return 0;
594}
595
596/*
597 * .event_complete handler
598 */
599static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
600 struct sk_buff *skb)
601{
602 dev_kfree_skb_any(skb);
603 return 0;
604}
605
c23b7c8f
AK		 606static inline bool
607mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
608{
609 u8 tmp;
610
611 if (card->curr_rd_port < card->mpa_rx.start_port) {
b60186f8
YAP		 612 if (card->supports_sdio_new_mode)
613 tmp = card->mp_end_port >> 1;
614 else
615 tmp = card->mp_agg_pkt_limit;
c23b7c8f
AK		 616
617 if (((card->max_ports - card->mpa_rx.start_port) +
618 card->curr_rd_port) >= tmp)
619 return true;
620 }
621
b60186f8
YAP		 622 if (!card->supports_sdio_new_mode)
623 return false;
624
625 if ((card->curr_rd_port - card->mpa_rx.start_port) >=
626 (card->mp_end_port >> 1))
627 return true;
628
c23b7c8f
AK		 629 return false;
630}
631
632static inline bool
633mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
634{
635 u16 tmp;
636
637 if (card->curr_wr_port < card->mpa_tx.start_port) {
b60186f8
YAP		 638 if (card->supports_sdio_new_mode)
639 tmp = card->mp_end_port >> 1;
640 else
641 tmp = card->mp_agg_pkt_limit;
c23b7c8f
AK		 642
643 if (((card->max_ports - card->mpa_tx.start_port) +
644 card->curr_wr_port) >= tmp)
645 return true;
646 }
647
b60186f8
YAP		 648 if (!card->supports_sdio_new_mode)
649 return false;
650
651 if ((card->curr_wr_port - card->mpa_tx.start_port) >=
652 (card->mp_end_port >> 1))
653 return true;
654
c23b7c8f
AK		 655 return false;
656}
657
658/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
659static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
960d6d08 660 u16 rx_len, u8 port)
c23b7c8f 661{
960d6d08 662 card->mpa_rx.buf_len += rx_len;
c23b7c8f
AK		 663
664 if (!card->mpa_rx.pkt_cnt)
665 card->mpa_rx.start_port = port;
666
b60186f8
YAP		 667 if (card->supports_sdio_new_mode) {
668 card->mpa_rx.ports |= (1 << port);
669 } else {
670 if (card->mpa_rx.start_port <= port)
671 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
672 else
673 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
674 }
960d6d08
ZL		 675 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL;
676 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len;
c23b7c8f
AK		 677 card->mpa_rx.pkt_cnt++;
678}
5e6e3a92 679#endif /* _MWIFIEX_SDIO_H */
Linux kernel - Deliverables
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