[deliverable/linux.git] / drivers / net / wireless / mwifiex / ioctl.h

/*
 * Marvell Wireless LAN device driver: ioctl data structures & APIs
 *
 * Copyright (C) 2011, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef _MWIFIEX_IOCTL_H_
#define _MWIFIEX_IOCTL_H_

#include <net/mac80211.h>

enum {
	MWIFIEX_SCAN_TYPE_UNCHANGED = 0,
	MWIFIEX_SCAN_TYPE_ACTIVE,
	MWIFIEX_SCAN_TYPE_PASSIVE
};

struct mwifiex_user_scan {
	u32 scan_cfg_len;
	u8 scan_cfg_buf[1];
};

#define MWIFIEX_PROMISC_MODE            1
#define MWIFIEX_MULTICAST_MODE		2
#define	MWIFIEX_ALL_MULTI_MODE		4
#define MWIFIEX_MAX_MULTICAST_LIST_SIZE	32

struct mwifiex_multicast_list {
	u32 mode;
	u32 num_multicast_addr;
	u8 mac_list[MWIFIEX_MAX_MULTICAST_LIST_SIZE][ETH_ALEN];
};

struct mwifiex_chan_freq {
	u32 channel;
	u32 freq;
};

struct mwifiex_ssid_bssid {
	struct cfg80211_ssid ssid;
	u8 bssid[ETH_ALEN];
};

enum {
	BAND_B = 1,
	BAND_G = 2,
	BAND_A = 4,
	BAND_GN = 8,
	BAND_AN = 16,
};

enum {
	ADHOC_IDLE,
	ADHOC_STARTED,
	ADHOC_JOINED,
	ADHOC_COALESCED
};

struct mwifiex_ds_get_stats {
	u32 mcast_tx_frame;
	u32 failed;
	u32 retry;
	u32 multi_retry;
	u32 frame_dup;
	u32 rts_success;
	u32 rts_failure;
	u32 ack_failure;
	u32 rx_frag;
	u32 mcast_rx_frame;
	u32 fcs_error;
	u32 tx_frame;
	u32 wep_icv_error[4];
};

#define MWIFIEX_MAX_VER_STR_LEN    128

struct mwifiex_ver_ext {
	u32 version_str_sel;
	char version_str[MWIFIEX_MAX_VER_STR_LEN];
};

struct mwifiex_bss_info {
	u32 bss_mode;
	struct cfg80211_ssid ssid;
	u32 bss_chan;
	u8 country_code[3];
	u32 media_connected;
	u32 max_power_level;
	u32 min_power_level;
	u32 adhoc_state;
	signed int bcn_nf_last;
	u32 wep_status;
	u32 is_hs_configured;
	u32 is_deep_sleep;
	u8 bssid[ETH_ALEN];
};

#define MAX_NUM_TID     8

#define MAX_RX_WINSIZE  64

struct mwifiex_ds_rx_reorder_tbl {
	u16 tid;
	u8 ta[ETH_ALEN];
	u32 start_win;
	u32 win_size;
	u32 buffer[MAX_RX_WINSIZE];
};

struct mwifiex_ds_tx_ba_stream_tbl {
	u16 tid;
	u8 ra[ETH_ALEN];
};

#define DBG_CMD_NUM	5

struct mwifiex_debug_info {
	u32 int_counter;
	u32 packets_out[MAX_NUM_TID];
	u32 max_tx_buf_size;
	u32 tx_buf_size;
	u32 curr_tx_buf_size;
	u32 tx_tbl_num;
	struct mwifiex_ds_tx_ba_stream_tbl
		tx_tbl[MWIFIEX_MAX_TX_BASTREAM_SUPPORTED];
	u32 rx_tbl_num;
	struct mwifiex_ds_rx_reorder_tbl rx_tbl
		[MWIFIEX_MAX_RX_BASTREAM_SUPPORTED];
	u16 ps_mode;
	u32 ps_state;
	u8 is_deep_sleep;
	u8 pm_wakeup_card_req;
	u32 pm_wakeup_fw_try;
	u8 is_hs_configured;
	u8 hs_activated;
	u32 num_cmd_host_to_card_failure;
	u32 num_cmd_sleep_cfm_host_to_card_failure;
	u32 num_tx_host_to_card_failure;
	u32 num_event_deauth;
	u32 num_event_disassoc;
	u32 num_event_link_lost;
	u32 num_cmd_deauth;
	u32 num_cmd_assoc_success;
	u32 num_cmd_assoc_failure;
	u32 num_tx_timeout;
	u32 num_cmd_timeout;
	u16 timeout_cmd_id;
	u16 timeout_cmd_act;
	u16 last_cmd_id[DBG_CMD_NUM];
	u16 last_cmd_act[DBG_CMD_NUM];
	u16 last_cmd_index;
	u16 last_cmd_resp_id[DBG_CMD_NUM];
	u16 last_cmd_resp_index;
	u16 last_event[DBG_CMD_NUM];
	u16 last_event_index;
	u8 data_sent;
	u8 cmd_sent;
	u8 cmd_resp_received;
	u8 event_received;
};

#define MWIFIEX_KEY_INDEX_UNICAST	0x40000000
#define WAPI_RXPN_LEN			16

struct mwifiex_ds_encrypt_key {
	u32 key_disable;
	u32 key_index;
	u32 key_len;
	u8 key_material[WLAN_MAX_KEY_LEN];
	u8 mac_addr[ETH_ALEN];
	u32 is_wapi_key;
	u8 wapi_rxpn[WAPI_RXPN_LEN];
};

struct mwifiex_rate_cfg {
	u32 action;
	u32 is_rate_auto;
	u32 rate;
};

struct mwifiex_power_cfg {
	u32 is_power_auto;
	u32 power_level;
};

struct mwifiex_ds_hs_cfg {
	u32 is_invoke_hostcmd;
	/*  Bit0: non-unicast data
	 *  Bit1: unicast data
	 *  Bit2: mac events
	 *  Bit3: magic packet
	 */
	u32 conditions;
	u32 gpio;
	u32 gap;
};

#define DEEP_SLEEP_ON  1
#define DEEP_SLEEP_OFF 0
#define DEEP_SLEEP_IDLE_TIME	100
#define PS_MODE_AUTO		1

struct mwifiex_ds_auto_ds {
	u16 auto_ds;
	u16 idle_time;
};

struct mwifiex_ds_pm_cfg {
	union {
		u32 ps_mode;
		struct mwifiex_ds_hs_cfg hs_cfg;
		struct mwifiex_ds_auto_ds auto_deep_sleep;
		u32 sleep_period;
	} param;
};

struct mwifiex_ds_11n_tx_cfg {
	u16 tx_htcap;
	u16 tx_htinfo;
};

struct mwifiex_ds_11n_amsdu_aggr_ctrl {
	u16 enable;
	u16 curr_buf_size;
};

#define MWIFIEX_NUM_OF_CMD_BUFFER	20
#define MWIFIEX_SIZE_OF_CMD_BUFFER	2048

enum {
	MWIFIEX_IE_TYPE_GEN_IE = 0,
	MWIFIEX_IE_TYPE_ARP_FILTER,
};

enum {
	MWIFIEX_REG_MAC = 1,
	MWIFIEX_REG_BBP,
	MWIFIEX_REG_RF,
	MWIFIEX_REG_PMIC,
	MWIFIEX_REG_CAU,
};

struct mwifiex_ds_reg_rw {
	__le32 type;
	__le32 offset;
	__le32 value;
};

#define MAX_EEPROM_DATA 256

struct mwifiex_ds_read_eeprom {
	__le16 offset;
	__le16 byte_count;
	u8 value[MAX_EEPROM_DATA];
};

#define IEEE_MAX_IE_SIZE		256

struct mwifiex_ds_misc_gen_ie {
	u32 type;
	u32 len;
	u8 ie_data[IEEE_MAX_IE_SIZE];
};

struct mwifiex_ds_misc_cmd {
	u32 len;
	u8 cmd[MWIFIEX_SIZE_OF_CMD_BUFFER];
};

#define BITMASK_BCN_RSSI_LOW	BIT(0)
#define BITMASK_BCN_RSSI_HIGH	BIT(4)

enum subsc_evt_rssi_state {
	EVENT_HANDLED,
	RSSI_LOW_RECVD,
	RSSI_HIGH_RECVD
};

struct subsc_evt_cfg {
	u8 abs_value;
	u8 evt_freq;
};

struct mwifiex_ds_misc_subsc_evt {
	u16 action;
	u16 events;
	struct subsc_evt_cfg bcn_l_rssi_cfg;
	struct subsc_evt_cfg bcn_h_rssi_cfg;
};

#define MWIFIEX_MAX_VSIE_LEN       (256)
#define MWIFIEX_MAX_VSIE_NUM       (8)
#define MWIFIEX_VSIE_MASK_CLEAR    0x00
#define MWIFIEX_VSIE_MASK_SCAN     0x01
#define MWIFIEX_VSIE_MASK_ASSOC    0x02
#define MWIFIEX_VSIE_MASK_ADHOC    0x04

enum {
	MWIFIEX_FUNC_INIT = 1,
	MWIFIEX_FUNC_SHUTDOWN,
};

#endif /* !_MWIFIEX_IOCTL_H_ */
Commit	Line	Data
5e6e3a92 BZ	1	/*
	2	* Marvell Wireless LAN device driver: ioctl data structures & APIs
	3	*
	4	* Copyright (C) 2011, Marvell International Ltd.
	5	*
	6	* This software file (the "File") is distributed by Marvell International
	7	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	8	* (the "License"). You may use, redistribute and/or modify this File in
	9	* accordance with the terms and conditions of the License, a copy of which
	10	* is available by writing to the Free Software Foundation, Inc.,
	11	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	12	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	13	*
	14	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	15	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	16	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	17	* this warranty disclaimer.
	18	*/
	19
	20	#ifndef _MWIFIEX_IOCTL_H_
	21	#define _MWIFIEX_IOCTL_H_
	22
	23	#include <net/mac80211.h>
	24
5e6e3a92 BZ	25	enum {
	26	MWIFIEX_SCAN_TYPE_UNCHANGED = 0,
	27	MWIFIEX_SCAN_TYPE_ACTIVE,
	28	MWIFIEX_SCAN_TYPE_PASSIVE
	29	};
	30
5e6e3a92 BZ	31	struct mwifiex_user_scan {
	32	u32 scan_cfg_len;
	33	u8 scan_cfg_buf[1];
	34	};
	35
5e6e3a92 BZ	36	#define MWIFIEX_PROMISC_MODE 1
	37	#define MWIFIEX_MULTICAST_MODE 2
	38	#define MWIFIEX_ALL_MULTI_MODE 4
	39	#define MWIFIEX_MAX_MULTICAST_LIST_SIZE 32
	40
	41	struct mwifiex_multicast_list {
	42	u32 mode;
	43	u32 num_multicast_addr;
	44	u8 mac_list[MWIFIEX_MAX_MULTICAST_LIST_SIZE][ETH_ALEN];
	45	};
	46
5e6e3a92 BZ	47	struct mwifiex_chan_freq {
	48	u32 channel;
	49	u32 freq;
	50	};
	51
5e6e3a92	52	struct mwifiex_ssid_bssid {
b9be5f39	53	struct cfg80211_ssid ssid;
5e6e3a92 BZ	54	u8 bssid[ETH_ALEN];
	55	};
	56
	57	enum {
	58	BAND_B = 1,
	59	BAND_G = 2,
	60	BAND_A = 4,
	61	BAND_GN = 8,
	62	BAND_AN = 16,
	63	};
	64
5e6e3a92 BZ	65	enum {
	66	ADHOC_IDLE,
	67	ADHOC_STARTED,
	68	ADHOC_JOINED,
	69	ADHOC_COALESCED
	70	};
	71
	72	struct mwifiex_ds_get_stats {
	73	u32 mcast_tx_frame;
	74	u32 failed;
	75	u32 retry;
	76	u32 multi_retry;
	77	u32 frame_dup;
	78	u32 rts_success;
	79	u32 rts_failure;
	80	u32 ack_failure;
	81	u32 rx_frag;
	82	u32 mcast_rx_frame;
	83	u32 fcs_error;
	84	u32 tx_frame;
	85	u32 wep_icv_error[4];
	86	};
	87
5e6e3a92 BZ	88	#define MWIFIEX_MAX_VER_STR_LEN 128
	89
	90	struct mwifiex_ver_ext {
	91	u32 version_str_sel;
	92	char version_str[MWIFIEX_MAX_VER_STR_LEN];
	93	};
	94
	95	struct mwifiex_bss_info {
	96	u32 bss_mode;
b9be5f39	97	struct cfg80211_ssid ssid;
5e6e3a92	98	u32 bss_chan;
5e218b7a	99	u8 country_code[3];
5e6e3a92	100	u32 media_connected;
5e6e3a92 BZ	101	u32 max_power_level;
	102	u32 min_power_level;
	103	u32 adhoc_state;
	104	signed int bcn_nf_last;
	105	u32 wep_status;
	106	u32 is_hs_configured;
	107	u32 is_deep_sleep;
	108	u8 bssid[ETH_ALEN];
	109	};
	110
	111	#define MAX_NUM_TID 8
	112
	113	#define MAX_RX_WINSIZE 64
	114
	115	struct mwifiex_ds_rx_reorder_tbl {
	116	u16 tid;
	117	u8 ta[ETH_ALEN];
	118	u32 start_win;
	119	u32 win_size;
	120	u32 buffer[MAX_RX_WINSIZE];
	121	};
	122
	123	struct mwifiex_ds_tx_ba_stream_tbl {
	124	u16 tid;
	125	u8 ra[ETH_ALEN];
	126	};
	127
	128	#define DBG_CMD_NUM 5
	129
	130	struct mwifiex_debug_info {
	131	u32 int_counter;
	132	u32 packets_out[MAX_NUM_TID];
	133	u32 max_tx_buf_size;
	134	u32 tx_buf_size;
	135	u32 curr_tx_buf_size;
	136	u32 tx_tbl_num;
	137	struct mwifiex_ds_tx_ba_stream_tbl
	138	tx_tbl[MWIFIEX_MAX_TX_BASTREAM_SUPPORTED];
	139	u32 rx_tbl_num;
	140	struct mwifiex_ds_rx_reorder_tbl rx_tbl
	141	[MWIFIEX_MAX_RX_BASTREAM_SUPPORTED];
	142	u16 ps_mode;
	143	u32 ps_state;
	144	u8 is_deep_sleep;
	145	u8 pm_wakeup_card_req;
	146	u32 pm_wakeup_fw_try;
	147	u8 is_hs_configured;
	148	u8 hs_activated;
	149	u32 num_cmd_host_to_card_failure;
	150	u32 num_cmd_sleep_cfm_host_to_card_failure;
	151	u32 num_tx_host_to_card_failure;
	152	u32 num_event_deauth;
	153	u32 num_event_disassoc;
	154	u32 num_event_link_lost;
	155	u32 num_cmd_deauth;
	156	u32 num_cmd_assoc_success;
	157	u32 num_cmd_assoc_failure;
	158	u32 num_tx_timeout;
	159	u32 num_cmd_timeout;
	160	u16 timeout_cmd_id;
	161	u16 timeout_cmd_act;
	162	u16 last_cmd_id[DBG_CMD_NUM];
	163	u16 last_cmd_act[DBG_CMD_NUM];
	164	u16 last_cmd_index;
165	u16 last_cmd_resp_id[DBG_CMD_NUM];
166	u16 last_cmd_resp_index;
167	u16 last_event[DBG_CMD_NUM];
168	u16 last_event_index;
169	u8 data_sent;
170	u8 cmd_sent;
171	u8 cmd_resp_received;
172	u8 event_received;
173	};
174
5e6e3a92	175	#define MWIFIEX_KEY_INDEX_UNICAST 0x40000000
5e6e3a92 BZ	176	#define WAPI_RXPN_LEN 16
	177
	178	struct mwifiex_ds_encrypt_key {
	179	u32 key_disable;
	180	u32 key_index;
	181	u32 key_len;
a3731658	182	u8 key_material[WLAN_MAX_KEY_LEN];
5e6e3a92 BZ	183	u8 mac_addr[ETH_ALEN];
	184	u32 is_wapi_key;
	185	u8 wapi_rxpn[WAPI_RXPN_LEN];
	186	};
	187
	188	struct mwifiex_rate_cfg {
	189	u32 action;
	190	u32 is_rate_auto;
	191	u32 rate;
	192	};
	193
5e6e3a92 BZ	194	struct mwifiex_power_cfg {
	195	u32 is_power_auto;
	196	u32 power_level;
	197	};
	198
	199	struct mwifiex_ds_hs_cfg {
	200	u32 is_invoke_hostcmd;
	201	/* Bit0: non-unicast data
	202	* Bit1: unicast data
	203	* Bit2: mac events
	204	* Bit3: magic packet
	205	*/
	206	u32 conditions;
	207	u32 gpio;
	208	u32 gap;
	209	};
	210
	211	#define DEEP_SLEEP_ON 1
a0490936	212	#define DEEP_SLEEP_OFF 0
5e6e3a92	213	#define DEEP_SLEEP_IDLE_TIME 100
a8c48565	214	#define PS_MODE_AUTO 1
5e6e3a92 BZ	215
	216	struct mwifiex_ds_auto_ds {
	217	u16 auto_ds;
	218	u16 idle_time;
	219	};
	220
5e6e3a92 BZ	221	struct mwifiex_ds_pm_cfg {
	222	union {
	223	u32 ps_mode;
	224	struct mwifiex_ds_hs_cfg hs_cfg;
	225	struct mwifiex_ds_auto_ds auto_deep_sleep;
	226	u32 sleep_period;
	227	} param;
	228	};
	229
5e6e3a92 BZ	230	struct mwifiex_ds_11n_tx_cfg {
	231	u16 tx_htcap;
	232	u16 tx_htinfo;
	233	};
	234
	235	struct mwifiex_ds_11n_amsdu_aggr_ctrl {
	236	u16 enable;
	237	u16 curr_buf_size;
	238	};
	239
	240	#define MWIFIEX_NUM_OF_CMD_BUFFER 20
	241	#define MWIFIEX_SIZE_OF_CMD_BUFFER 2048
	242
	243	enum {
	244	MWIFIEX_IE_TYPE_GEN_IE = 0,
	245	MWIFIEX_IE_TYPE_ARP_FILTER,
	246	};
	247
	248	enum {
	249	MWIFIEX_REG_MAC = 1,
	250	MWIFIEX_REG_BBP,
	251	MWIFIEX_REG_RF,
	252	MWIFIEX_REG_PMIC,
	253	MWIFIEX_REG_CAU,
	254	};
	255
	256	struct mwifiex_ds_reg_rw {
	257	__le32 type;
	258	__le32 offset;
	259	__le32 value;
	260	};
	261
	262	#define MAX_EEPROM_DATA 256
	263
	264	struct mwifiex_ds_read_eeprom {
	265	__le16 offset;
	266	__le16 byte_count;
	267	u8 value[MAX_EEPROM_DATA];
	268	};
	269
67a50035 BZ	270	#define IEEE_MAX_IE_SIZE 256
67a50035 BZ	271
5e6e3a92 BZ	272	struct mwifiex_ds_misc_gen_ie {
	273	u32 type;
	274	u32 len;
67a50035	275	u8 ie_data[IEEE_MAX_IE_SIZE];
5e6e3a92 BZ	276	};
	277
	278	struct mwifiex_ds_misc_cmd {
	279	u32 len;
	280	u8 cmd[MWIFIEX_SIZE_OF_CMD_BUFFER];
	281	};
	282
fa444bf8 AK	283	#define BITMASK_BCN_RSSI_LOW BIT(0)
	284	#define BITMASK_BCN_RSSI_HIGH BIT(4)
	285
	286	enum subsc_evt_rssi_state {
	287	EVENT_HANDLED,
	288	RSSI_LOW_RECVD,
	289	RSSI_HIGH_RECVD
	290	};
	291
	292	struct subsc_evt_cfg {
	293	u8 abs_value;
	294	u8 evt_freq;
	295	};
	296
	297	struct mwifiex_ds_misc_subsc_evt {
	298	u16 action;
	299	u16 events;
	300	struct subsc_evt_cfg bcn_l_rssi_cfg;
	301	struct subsc_evt_cfg bcn_h_rssi_cfg;
	302	};
	303
5e6e3a92 BZ	304	#define MWIFIEX_MAX_VSIE_LEN (256)
5e6e3a92 BZ	305	#define MWIFIEX_MAX_VSIE_NUM (8)
13d7ba78	306	#define MWIFIEX_VSIE_MASK_CLEAR 0x00
5e6e3a92 BZ	307	#define MWIFIEX_VSIE_MASK_SCAN 0x01
	308	#define MWIFIEX_VSIE_MASK_ASSOC 0x02
	309	#define MWIFIEX_VSIE_MASK_ADHOC 0x04
	310
	311	enum {
	312	MWIFIEX_FUNC_INIT = 1,
	313	MWIFIEX_FUNC_SHUTDOWN,
	314	};
	315
	316	#endif /* !_MWIFIEX_IOCTL_H_ */