Commit | Line | Data |
---|---|---|
d930faee AK |
1 | /* |
2 | * Marvell Wireless LAN device driver: PCIE specific handling | |
3 | * | |
4 | * Copyright (C) 2011, Marvell International Ltd. | |
5 | * | |
6 | * This software file (the "File") is distributed by Marvell International | |
7 | * Ltd. under the terms of the GNU General Public License Version 2, June 1991 | |
8 | * (the "License"). You may use, redistribute and/or modify this File in | |
9 | * accordance with the terms and conditions of the License, a copy of which | |
10 | * is available by writing to the Free Software Foundation, Inc., | |
11 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the | |
12 | * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. | |
13 | * | |
14 | * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE | |
15 | * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE | |
16 | * ARE EXPRESSLY DISCLAIMED. The License provides additional details about | |
17 | * this warranty disclaimer. | |
18 | */ | |
19 | ||
20 | #include <linux/firmware.h> | |
21 | ||
22 | #include "decl.h" | |
23 | #include "ioctl.h" | |
24 | #include "util.h" | |
25 | #include "fw.h" | |
26 | #include "main.h" | |
27 | #include "wmm.h" | |
28 | #include "11n.h" | |
29 | #include "pcie.h" | |
30 | ||
31 | #define PCIE_VERSION "1.0" | |
32 | #define DRV_NAME "Marvell mwifiex PCIe" | |
33 | ||
34 | static u8 user_rmmod; | |
35 | ||
36 | static struct mwifiex_if_ops pcie_ops; | |
37 | ||
38 | static struct semaphore add_remove_card_sem; | |
d930faee | 39 | |
fc331460 AP |
40 | static int |
41 | mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, | |
dbccc92b | 42 | size_t size, int flags) |
d930faee | 43 | { |
fc331460 | 44 | struct pcie_service_card *card = adapter->card; |
dbccc92b | 45 | struct mwifiex_dma_mapping mapping; |
d930faee | 46 | |
dbccc92b AD |
47 | mapping.addr = pci_map_single(card->dev, skb->data, size, flags); |
48 | if (pci_dma_mapping_error(card->dev, mapping.addr)) { | |
fc331460 AP |
49 | dev_err(adapter->dev, "failed to map pci memory!\n"); |
50 | return -1; | |
51 | } | |
dbccc92b | 52 | mapping.len = size; |
bca463e8 | 53 | mwifiex_store_mapping(skb, &mapping); |
fc331460 | 54 | return 0; |
d930faee AK |
55 | } |
56 | ||
dbccc92b AD |
57 | static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter, |
58 | struct sk_buff *skb, int flags) | |
59 | { | |
60 | struct pcie_service_card *card = adapter->card; | |
61 | struct mwifiex_dma_mapping mapping; | |
62 | ||
bca463e8 | 63 | mwifiex_get_mapping(skb, &mapping); |
dbccc92b AD |
64 | pci_unmap_single(card->dev, mapping.addr, mapping.len, flags); |
65 | } | |
66 | ||
d930faee AK |
67 | /* |
68 | * This function reads sleep cookie and checks if FW is ready | |
69 | */ | |
70 | static bool mwifiex_pcie_ok_to_access_hw(struct mwifiex_adapter *adapter) | |
71 | { | |
72 | u32 *cookie_addr; | |
73 | struct pcie_service_card *card = adapter->card; | |
52301a81 AP |
74 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
75 | ||
76 | if (!reg->sleep_cookie) | |
77 | return true; | |
d930faee | 78 | |
fc331460 AP |
79 | if (card->sleep_cookie_vbase) { |
80 | cookie_addr = (u32 *)card->sleep_cookie_vbase; | |
d930faee AK |
81 | dev_dbg(adapter->dev, "info: ACCESS_HW: sleep cookie=0x%x\n", |
82 | *cookie_addr); | |
83 | if (*cookie_addr == FW_AWAKE_COOKIE) | |
84 | return true; | |
85 | } | |
86 | ||
87 | return false; | |
88 | } | |
89 | ||
3266d732 | 90 | #ifdef CONFIG_PM_SLEEP |
fcca8d5a BZ |
91 | /* |
92 | * Kernel needs to suspend all functions separately. Therefore all | |
93 | * registered functions must have drivers with suspend and resume | |
94 | * methods. Failing that the kernel simply removes the whole card. | |
95 | * | |
96 | * If already not suspended, this function allocates and sends a host | |
97 | * sleep activate request to the firmware and turns off the traffic. | |
98 | */ | |
3266d732 | 99 | static int mwifiex_pcie_suspend(struct device *dev) |
fcca8d5a BZ |
100 | { |
101 | struct mwifiex_adapter *adapter; | |
102 | struct pcie_service_card *card; | |
103 | int hs_actived; | |
3266d732 | 104 | struct pci_dev *pdev = to_pci_dev(dev); |
fcca8d5a BZ |
105 | |
106 | if (pdev) { | |
b2a31204 | 107 | card = pci_get_drvdata(pdev); |
fcca8d5a BZ |
108 | if (!card || !card->adapter) { |
109 | pr_err("Card or adapter structure is not valid\n"); | |
110 | return 0; | |
111 | } | |
112 | } else { | |
113 | pr_err("PCIE device is not specified\n"); | |
114 | return 0; | |
115 | } | |
116 | ||
117 | adapter = card->adapter; | |
118 | ||
119 | hs_actived = mwifiex_enable_hs(adapter); | |
120 | ||
121 | /* Indicate device suspended */ | |
122 | adapter->is_suspended = true; | |
c0dbba66 | 123 | adapter->hs_enabling = false; |
fcca8d5a BZ |
124 | |
125 | return 0; | |
126 | } | |
127 | ||
128 | /* | |
129 | * Kernel needs to suspend all functions separately. Therefore all | |
130 | * registered functions must have drivers with suspend and resume | |
131 | * methods. Failing that the kernel simply removes the whole card. | |
132 | * | |
133 | * If already not resumed, this function turns on the traffic and | |
134 | * sends a host sleep cancel request to the firmware. | |
135 | */ | |
3266d732 | 136 | static int mwifiex_pcie_resume(struct device *dev) |
fcca8d5a BZ |
137 | { |
138 | struct mwifiex_adapter *adapter; | |
139 | struct pcie_service_card *card; | |
3266d732 | 140 | struct pci_dev *pdev = to_pci_dev(dev); |
fcca8d5a BZ |
141 | |
142 | if (pdev) { | |
b2a31204 | 143 | card = pci_get_drvdata(pdev); |
fcca8d5a BZ |
144 | if (!card || !card->adapter) { |
145 | pr_err("Card or adapter structure is not valid\n"); | |
146 | return 0; | |
147 | } | |
148 | } else { | |
149 | pr_err("PCIE device is not specified\n"); | |
150 | return 0; | |
151 | } | |
152 | ||
153 | adapter = card->adapter; | |
154 | ||
155 | if (!adapter->is_suspended) { | |
156 | dev_warn(adapter->dev, "Device already resumed\n"); | |
157 | return 0; | |
158 | } | |
159 | ||
160 | adapter->is_suspended = false; | |
161 | ||
162 | mwifiex_cancel_hs(mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_STA), | |
163 | MWIFIEX_ASYNC_CMD); | |
164 | ||
165 | return 0; | |
166 | } | |
8509e820 | 167 | #endif |
fcca8d5a | 168 | |
d930faee AK |
169 | /* |
170 | * This function probes an mwifiex device and registers it. It allocates | |
171 | * the card structure, enables PCIE function number and initiates the | |
172 | * device registration and initialization procedure by adding a logical | |
173 | * interface. | |
174 | */ | |
175 | static int mwifiex_pcie_probe(struct pci_dev *pdev, | |
176 | const struct pci_device_id *ent) | |
177 | { | |
178 | struct pcie_service_card *card; | |
179 | ||
180 | pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", | |
f57c1edc | 181 | pdev->vendor, pdev->device, pdev->revision); |
d930faee AK |
182 | |
183 | card = kzalloc(sizeof(struct pcie_service_card), GFP_KERNEL); | |
e404decb | 184 | if (!card) |
d930faee | 185 | return -ENOMEM; |
d930faee AK |
186 | |
187 | card->dev = pdev; | |
188 | ||
dd04e6ac AP |
189 | if (ent->driver_data) { |
190 | struct mwifiex_pcie_device *data = (void *)ent->driver_data; | |
191 | card->pcie.firmware = data->firmware; | |
192 | card->pcie.reg = data->reg; | |
193 | card->pcie.blksz_fw_dl = data->blksz_fw_dl; | |
828cf222 | 194 | card->pcie.tx_buf_size = data->tx_buf_size; |
dd04e6ac AP |
195 | } |
196 | ||
d930faee AK |
197 | if (mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops, |
198 | MWIFIEX_PCIE)) { | |
199 | pr_err("%s failed\n", __func__); | |
200 | kfree(card); | |
201 | return -1; | |
202 | } | |
203 | ||
204 | return 0; | |
205 | } | |
206 | ||
207 | /* | |
208 | * This function removes the interface and frees up the card structure. | |
209 | */ | |
210 | static void mwifiex_pcie_remove(struct pci_dev *pdev) | |
211 | { | |
212 | struct pcie_service_card *card; | |
213 | struct mwifiex_adapter *adapter; | |
f57c1edc | 214 | struct mwifiex_private *priv; |
d930faee AK |
215 | |
216 | card = pci_get_drvdata(pdev); | |
217 | if (!card) | |
218 | return; | |
219 | ||
220 | adapter = card->adapter; | |
221 | if (!adapter || !adapter->priv_num) | |
222 | return; | |
223 | ||
224 | if (user_rmmod) { | |
3266d732 | 225 | #ifdef CONFIG_PM_SLEEP |
d930faee | 226 | if (adapter->is_suspended) |
3266d732 | 227 | mwifiex_pcie_resume(&pdev->dev); |
d930faee AK |
228 | #endif |
229 | ||
848819f4 | 230 | mwifiex_deauthenticate_all(adapter); |
d930faee | 231 | |
f57c1edc | 232 | priv = mwifiex_get_priv(adapter, MWIFIEX_BSS_ROLE_ANY); |
d930faee | 233 | |
f57c1edc YAP |
234 | mwifiex_disable_auto_ds(priv); |
235 | ||
236 | mwifiex_init_shutdown_fw(priv, MWIFIEX_FUNC_SHUTDOWN); | |
d930faee AK |
237 | } |
238 | ||
239 | mwifiex_remove_card(card->adapter, &add_remove_card_sem); | |
d930faee AK |
240 | } |
241 | ||
43ba6b9f AK |
242 | static void mwifiex_pcie_shutdown(struct pci_dev *pdev) |
243 | { | |
244 | user_rmmod = 1; | |
245 | mwifiex_pcie_remove(pdev); | |
246 | ||
247 | return; | |
248 | } | |
249 | ||
d930faee AK |
250 | static DEFINE_PCI_DEVICE_TABLE(mwifiex_ids) = { |
251 | { | |
252 | PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8766P, | |
253 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
dd04e6ac | 254 | .driver_data = (unsigned long) &mwifiex_pcie8766, |
d930faee | 255 | }, |
ca8f2112 AP |
256 | { |
257 | PCIE_VENDOR_ID_MARVELL, PCIE_DEVICE_ID_MARVELL_88W8897, | |
258 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
259 | .driver_data = (unsigned long) &mwifiex_pcie8897, | |
260 | }, | |
d930faee AK |
261 | {}, |
262 | }; | |
263 | ||
264 | MODULE_DEVICE_TABLE(pci, mwifiex_ids); | |
265 | ||
3266d732 SK |
266 | #ifdef CONFIG_PM_SLEEP |
267 | /* Power Management Hooks */ | |
268 | static SIMPLE_DEV_PM_OPS(mwifiex_pcie_pm_ops, mwifiex_pcie_suspend, | |
269 | mwifiex_pcie_resume); | |
270 | #endif | |
271 | ||
d930faee AK |
272 | /* PCI Device Driver */ |
273 | static struct pci_driver __refdata mwifiex_pcie = { | |
274 | .name = "mwifiex_pcie", | |
275 | .id_table = mwifiex_ids, | |
276 | .probe = mwifiex_pcie_probe, | |
277 | .remove = mwifiex_pcie_remove, | |
3266d732 SK |
278 | #ifdef CONFIG_PM_SLEEP |
279 | .driver = { | |
280 | .pm = &mwifiex_pcie_pm_ops, | |
281 | }, | |
d930faee | 282 | #endif |
43ba6b9f | 283 | .shutdown = mwifiex_pcie_shutdown, |
d930faee AK |
284 | }; |
285 | ||
286 | /* | |
287 | * This function writes data into PCIE card register. | |
288 | */ | |
289 | static int mwifiex_write_reg(struct mwifiex_adapter *adapter, int reg, u32 data) | |
290 | { | |
291 | struct pcie_service_card *card = adapter->card; | |
292 | ||
293 | iowrite32(data, card->pci_mmap1 + reg); | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
298 | /* | |
299 | * This function reads data from PCIE card register. | |
300 | */ | |
301 | static int mwifiex_read_reg(struct mwifiex_adapter *adapter, int reg, u32 *data) | |
302 | { | |
303 | struct pcie_service_card *card = adapter->card; | |
304 | ||
305 | *data = ioread32(card->pci_mmap1 + reg); | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
310 | /* | |
c0880a29 | 311 | * This function adds delay loop to ensure FW is awake before proceeding. |
d930faee | 312 | */ |
c0880a29 | 313 | static void mwifiex_pcie_dev_wakeup_delay(struct mwifiex_adapter *adapter) |
d930faee AK |
314 | { |
315 | int i = 0; | |
316 | ||
c0880a29 | 317 | while (mwifiex_pcie_ok_to_access_hw(adapter)) { |
d930faee | 318 | i++; |
e7891ba2 | 319 | usleep_range(10, 20); |
d930faee | 320 | /* 50ms max wait */ |
3e7a4ff7 | 321 | if (i == 5000) |
d930faee AK |
322 | break; |
323 | } | |
324 | ||
c0880a29 AP |
325 | return; |
326 | } | |
327 | ||
c4bc980f AP |
328 | static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, |
329 | u32 max_delay_loop_cnt) | |
330 | { | |
331 | struct pcie_service_card *card = adapter->card; | |
332 | u8 *buffer; | |
333 | u32 sleep_cookie, count; | |
334 | ||
335 | for (count = 0; count < max_delay_loop_cnt; count++) { | |
336 | buffer = card->cmdrsp_buf->data - INTF_HEADER_LEN; | |
337 | sleep_cookie = *(u32 *)buffer; | |
338 | ||
339 | if (sleep_cookie == MWIFIEX_DEF_SLEEP_COOKIE) { | |
340 | dev_dbg(adapter->dev, | |
341 | "sleep cookie found at count %d\n", count); | |
342 | break; | |
343 | } | |
344 | usleep_range(20, 30); | |
345 | } | |
346 | ||
347 | if (count >= max_delay_loop_cnt) | |
348 | dev_dbg(adapter->dev, | |
349 | "max count reached while accessing sleep cookie\n"); | |
350 | } | |
351 | ||
c0880a29 AP |
352 | /* This function wakes up the card by reading fw_status register. */ |
353 | static int mwifiex_pm_wakeup_card(struct mwifiex_adapter *adapter) | |
354 | { | |
355 | u32 fw_status; | |
356 | struct pcie_service_card *card = adapter->card; | |
357 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; | |
358 | ||
d930faee AK |
359 | dev_dbg(adapter->dev, "event: Wakeup device...\n"); |
360 | ||
c0880a29 AP |
361 | if (reg->sleep_cookie) |
362 | mwifiex_pcie_dev_wakeup_delay(adapter); | |
363 | ||
364 | /* Reading fw_status register will wakeup device */ | |
365 | if (mwifiex_read_reg(adapter, reg->fw_status, &fw_status)) { | |
366 | dev_warn(adapter->dev, "Reading fw_status register failed\n"); | |
d930faee AK |
367 | return -1; |
368 | } | |
369 | ||
c0880a29 AP |
370 | if (reg->sleep_cookie) { |
371 | mwifiex_pcie_dev_wakeup_delay(adapter); | |
372 | dev_dbg(adapter->dev, "PCIE wakeup: Setting PS_STATE_AWAKE\n"); | |
373 | adapter->ps_state = PS_STATE_AWAKE; | |
374 | } | |
d930faee AK |
375 | |
376 | return 0; | |
377 | } | |
378 | ||
379 | /* | |
380 | * This function is called after the card has woken up. | |
381 | * | |
382 | * The card configuration register is reset. | |
383 | */ | |
384 | static int mwifiex_pm_wakeup_card_complete(struct mwifiex_adapter *adapter) | |
385 | { | |
386 | dev_dbg(adapter->dev, "cmd: Wakeup device completed\n"); | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | /* | |
392 | * This function disables the host interrupt. | |
393 | * | |
394 | * The host interrupt mask is read, the disable bit is reset and | |
395 | * written back to the card host interrupt mask register. | |
396 | */ | |
397 | static int mwifiex_pcie_disable_host_int(struct mwifiex_adapter *adapter) | |
398 | { | |
399 | if (mwifiex_pcie_ok_to_access_hw(adapter)) { | |
400 | if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, | |
401 | 0x00000000)) { | |
402 | dev_warn(adapter->dev, "Disable host interrupt failed\n"); | |
403 | return -1; | |
404 | } | |
405 | } | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | /* | |
411 | * This function enables the host interrupt. | |
412 | * | |
413 | * The host interrupt enable mask is written to the card | |
414 | * host interrupt mask register. | |
415 | */ | |
416 | static int mwifiex_pcie_enable_host_int(struct mwifiex_adapter *adapter) | |
417 | { | |
418 | if (mwifiex_pcie_ok_to_access_hw(adapter)) { | |
419 | /* Simply write the mask to the register */ | |
420 | if (mwifiex_write_reg(adapter, PCIE_HOST_INT_MASK, | |
421 | HOST_INTR_MASK)) { | |
422 | dev_warn(adapter->dev, "Enable host interrupt failed\n"); | |
423 | return -1; | |
424 | } | |
425 | } | |
426 | ||
427 | return 0; | |
428 | } | |
429 | ||
430 | /* | |
0732484b AP |
431 | * This function initializes TX buffer ring descriptors |
432 | */ | |
433 | static int mwifiex_init_txq_ring(struct mwifiex_adapter *adapter) | |
434 | { | |
435 | struct pcie_service_card *card = adapter->card; | |
ca8f2112 | 436 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
0732484b | 437 | struct mwifiex_pcie_buf_desc *desc; |
ca8f2112 | 438 | struct mwifiex_pfu_buf_desc *desc2; |
0732484b AP |
439 | int i; |
440 | ||
441 | for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { | |
442 | card->tx_buf_list[i] = NULL; | |
ca8f2112 AP |
443 | if (reg->pfu_enabled) { |
444 | card->txbd_ring[i] = (void *)card->txbd_ring_vbase + | |
445 | (sizeof(*desc2) * i); | |
446 | desc2 = card->txbd_ring[i]; | |
447 | memset(desc2, 0, sizeof(*desc2)); | |
448 | } else { | |
449 | card->txbd_ring[i] = (void *)card->txbd_ring_vbase + | |
450 | (sizeof(*desc) * i); | |
451 | desc = card->txbd_ring[i]; | |
452 | memset(desc, 0, sizeof(*desc)); | |
453 | } | |
0732484b AP |
454 | } |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | /* This function initializes RX buffer ring descriptors. Each SKB is allocated | |
460 | * here and after mapping PCI memory, its physical address is assigned to | |
461 | * PCIE Rx buffer descriptor's physical address. | |
462 | */ | |
463 | static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) | |
464 | { | |
465 | struct pcie_service_card *card = adapter->card; | |
ca8f2112 | 466 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
0732484b AP |
467 | struct sk_buff *skb; |
468 | struct mwifiex_pcie_buf_desc *desc; | |
ca8f2112 | 469 | struct mwifiex_pfu_buf_desc *desc2; |
0732484b AP |
470 | dma_addr_t buf_pa; |
471 | int i; | |
472 | ||
473 | for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { | |
474 | /* Allocate skb here so that firmware can DMA data from it */ | |
475 | skb = dev_alloc_skb(MWIFIEX_RX_DATA_BUF_SIZE); | |
476 | if (!skb) { | |
477 | dev_err(adapter->dev, | |
478 | "Unable to allocate skb for RX ring.\n"); | |
479 | kfree(card->rxbd_ring_vbase); | |
480 | return -ENOMEM; | |
481 | } | |
482 | ||
483 | if (mwifiex_map_pci_memory(adapter, skb, | |
484 | MWIFIEX_RX_DATA_BUF_SIZE, | |
485 | PCI_DMA_FROMDEVICE)) | |
486 | return -1; | |
487 | ||
dbccc92b | 488 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); |
0732484b AP |
489 | |
490 | dev_dbg(adapter->dev, | |
491 | "info: RX ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", | |
492 | skb, skb->len, skb->data, (u32)buf_pa, | |
493 | (u32)((u64)buf_pa >> 32)); | |
494 | ||
495 | card->rx_buf_list[i] = skb; | |
ca8f2112 AP |
496 | if (reg->pfu_enabled) { |
497 | card->rxbd_ring[i] = (void *)card->rxbd_ring_vbase + | |
498 | (sizeof(*desc2) * i); | |
499 | desc2 = card->rxbd_ring[i]; | |
500 | desc2->paddr = buf_pa; | |
501 | desc2->len = (u16)skb->len; | |
502 | desc2->frag_len = (u16)skb->len; | |
503 | desc2->flags = reg->ring_flag_eop | reg->ring_flag_sop; | |
504 | desc2->offset = 0; | |
505 | } else { | |
506 | card->rxbd_ring[i] = (void *)(card->rxbd_ring_vbase + | |
507 | (sizeof(*desc) * i)); | |
508 | desc = card->rxbd_ring[i]; | |
509 | desc->paddr = buf_pa; | |
510 | desc->len = (u16)skb->len; | |
511 | desc->flags = 0; | |
512 | } | |
0732484b AP |
513 | } |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | /* This function initializes event buffer ring descriptors. Each SKB is | |
519 | * allocated here and after mapping PCI memory, its physical address is assigned | |
520 | * to PCIE Rx buffer descriptor's physical address | |
521 | */ | |
522 | static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) | |
523 | { | |
524 | struct pcie_service_card *card = adapter->card; | |
e05dc3e9 | 525 | struct mwifiex_evt_buf_desc *desc; |
0732484b AP |
526 | struct sk_buff *skb; |
527 | dma_addr_t buf_pa; | |
528 | int i; | |
529 | ||
530 | for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { | |
531 | /* Allocate skb here so that firmware can DMA data from it */ | |
532 | skb = dev_alloc_skb(MAX_EVENT_SIZE); | |
533 | if (!skb) { | |
534 | dev_err(adapter->dev, | |
535 | "Unable to allocate skb for EVENT buf.\n"); | |
536 | kfree(card->evtbd_ring_vbase); | |
537 | return -ENOMEM; | |
538 | } | |
539 | skb_put(skb, MAX_EVENT_SIZE); | |
540 | ||
541 | if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, | |
542 | PCI_DMA_FROMDEVICE)) | |
543 | return -1; | |
544 | ||
dbccc92b | 545 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); |
0732484b AP |
546 | |
547 | dev_dbg(adapter->dev, | |
548 | "info: EVT ring: skb=%p len=%d data=%p buf_pa=%#x:%x\n", | |
549 | skb, skb->len, skb->data, (u32)buf_pa, | |
550 | (u32)((u64)buf_pa >> 32)); | |
551 | ||
552 | card->evt_buf_list[i] = skb; | |
553 | card->evtbd_ring[i] = (void *)(card->evtbd_ring_vbase + | |
554 | (sizeof(*desc) * i)); | |
0732484b AP |
555 | desc = card->evtbd_ring[i]; |
556 | desc->paddr = buf_pa; | |
557 | desc->len = (u16)skb->len; | |
558 | desc->flags = 0; | |
559 | } | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
564 | /* This function cleans up TX buffer rings. If any of the buffer list has valid | |
565 | * SKB address, associated SKB is freed. | |
566 | */ | |
567 | static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) | |
568 | { | |
569 | struct pcie_service_card *card = adapter->card; | |
ca8f2112 | 570 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
0732484b AP |
571 | struct sk_buff *skb; |
572 | struct mwifiex_pcie_buf_desc *desc; | |
ca8f2112 | 573 | struct mwifiex_pfu_buf_desc *desc2; |
0732484b AP |
574 | int i; |
575 | ||
576 | for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { | |
ca8f2112 AP |
577 | if (reg->pfu_enabled) { |
578 | desc2 = card->txbd_ring[i]; | |
579 | if (card->tx_buf_list[i]) { | |
580 | skb = card->tx_buf_list[i]; | |
dbccc92b AD |
581 | mwifiex_unmap_pci_memory(adapter, skb, |
582 | PCI_DMA_TODEVICE); | |
ca8f2112 AP |
583 | dev_kfree_skb_any(skb); |
584 | } | |
585 | memset(desc2, 0, sizeof(*desc2)); | |
586 | } else { | |
587 | desc = card->txbd_ring[i]; | |
588 | if (card->tx_buf_list[i]) { | |
589 | skb = card->tx_buf_list[i]; | |
dbccc92b AD |
590 | mwifiex_unmap_pci_memory(adapter, skb, |
591 | PCI_DMA_TODEVICE); | |
ca8f2112 AP |
592 | dev_kfree_skb_any(skb); |
593 | } | |
594 | memset(desc, 0, sizeof(*desc)); | |
0732484b AP |
595 | } |
596 | card->tx_buf_list[i] = NULL; | |
0732484b AP |
597 | } |
598 | ||
599 | return; | |
600 | } | |
601 | ||
602 | /* This function cleans up RX buffer rings. If any of the buffer list has valid | |
603 | * SKB address, associated SKB is freed. | |
604 | */ | |
605 | static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) | |
606 | { | |
607 | struct pcie_service_card *card = adapter->card; | |
ca8f2112 | 608 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
0732484b | 609 | struct mwifiex_pcie_buf_desc *desc; |
ca8f2112 | 610 | struct mwifiex_pfu_buf_desc *desc2; |
0732484b AP |
611 | struct sk_buff *skb; |
612 | int i; | |
613 | ||
614 | for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { | |
ca8f2112 AP |
615 | if (reg->pfu_enabled) { |
616 | desc2 = card->rxbd_ring[i]; | |
617 | if (card->rx_buf_list[i]) { | |
618 | skb = card->rx_buf_list[i]; | |
dbccc92b AD |
619 | mwifiex_unmap_pci_memory(adapter, skb, |
620 | PCI_DMA_FROMDEVICE); | |
ca8f2112 AP |
621 | dev_kfree_skb_any(skb); |
622 | } | |
623 | memset(desc2, 0, sizeof(*desc2)); | |
624 | } else { | |
625 | desc = card->rxbd_ring[i]; | |
626 | if (card->rx_buf_list[i]) { | |
627 | skb = card->rx_buf_list[i]; | |
dbccc92b AD |
628 | mwifiex_unmap_pci_memory(adapter, skb, |
629 | PCI_DMA_FROMDEVICE); | |
ca8f2112 AP |
630 | dev_kfree_skb_any(skb); |
631 | } | |
632 | memset(desc, 0, sizeof(*desc)); | |
0732484b | 633 | } |
ca8f2112 | 634 | card->rx_buf_list[i] = NULL; |
0732484b AP |
635 | } |
636 | ||
637 | return; | |
638 | } | |
639 | ||
640 | /* This function cleans up event buffer rings. If any of the buffer list has | |
641 | * valid SKB address, associated SKB is freed. | |
642 | */ | |
643 | static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter) | |
644 | { | |
645 | struct pcie_service_card *card = adapter->card; | |
e05dc3e9 | 646 | struct mwifiex_evt_buf_desc *desc; |
0732484b AP |
647 | struct sk_buff *skb; |
648 | int i; | |
649 | ||
650 | for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { | |
651 | desc = card->evtbd_ring[i]; | |
652 | if (card->evt_buf_list[i]) { | |
653 | skb = card->evt_buf_list[i]; | |
dbccc92b AD |
654 | mwifiex_unmap_pci_memory(adapter, skb, |
655 | PCI_DMA_FROMDEVICE); | |
0732484b AP |
656 | dev_kfree_skb_any(skb); |
657 | } | |
658 | card->evt_buf_list[i] = NULL; | |
659 | memset(desc, 0, sizeof(*desc)); | |
660 | } | |
661 | ||
662 | return; | |
663 | } | |
664 | ||
665 | /* This function creates buffer descriptor ring for TX | |
d930faee AK |
666 | */ |
667 | static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter) | |
668 | { | |
669 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 670 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
671 | |
672 | /* | |
673 | * driver maintaines the write pointer and firmware maintaines the read | |
674 | * pointer. The write pointer starts at 0 (zero) while the read pointer | |
675 | * starts at zero with rollover bit set | |
676 | */ | |
677 | card->txbd_wrptr = 0; | |
ca8f2112 AP |
678 | |
679 | if (reg->pfu_enabled) | |
680 | card->txbd_rdptr = 0; | |
681 | else | |
682 | card->txbd_rdptr |= reg->tx_rollover_ind; | |
d930faee AK |
683 | |
684 | /* allocate shared memory for the BD ring and divide the same in to | |
685 | several descriptors */ | |
ca8f2112 AP |
686 | if (reg->pfu_enabled) |
687 | card->txbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * | |
688 | MWIFIEX_MAX_TXRX_BD; | |
689 | else | |
690 | card->txbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * | |
691 | MWIFIEX_MAX_TXRX_BD; | |
692 | ||
d930faee | 693 | dev_dbg(adapter->dev, "info: txbd_ring: Allocating %d bytes\n", |
f57c1edc | 694 | card->txbd_ring_size); |
fc331460 AP |
695 | card->txbd_ring_vbase = pci_alloc_consistent(card->dev, |
696 | card->txbd_ring_size, | |
697 | &card->txbd_ring_pbase); | |
d930faee | 698 | if (!card->txbd_ring_vbase) { |
fc331460 AP |
699 | dev_err(adapter->dev, |
700 | "allocate consistent memory (%d bytes) failed!\n", | |
701 | card->txbd_ring_size); | |
8c53e42d | 702 | return -ENOMEM; |
d930faee | 703 | } |
f57c1edc YAP |
704 | dev_dbg(adapter->dev, |
705 | "info: txbd_ring - base: %p, pbase: %#x:%x, len: %x\n", | |
fc331460 | 706 | card->txbd_ring_vbase, (unsigned int)card->txbd_ring_pbase, |
f57c1edc | 707 | (u32)((u64)card->txbd_ring_pbase >> 32), card->txbd_ring_size); |
d930faee | 708 | |
0732484b | 709 | return mwifiex_init_txq_ring(adapter); |
d930faee AK |
710 | } |
711 | ||
712 | static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) | |
713 | { | |
714 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 715 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 716 | |
0732484b | 717 | mwifiex_cleanup_txq_ring(adapter); |
d930faee | 718 | |
fc331460 AP |
719 | if (card->txbd_ring_vbase) |
720 | pci_free_consistent(card->dev, card->txbd_ring_size, | |
721 | card->txbd_ring_vbase, | |
722 | card->txbd_ring_pbase); | |
d930faee AK |
723 | card->txbd_ring_size = 0; |
724 | card->txbd_wrptr = 0; | |
dd04e6ac | 725 | card->txbd_rdptr = 0 | reg->tx_rollover_ind; |
d930faee | 726 | card->txbd_ring_vbase = NULL; |
fc331460 | 727 | card->txbd_ring_pbase = 0; |
d930faee AK |
728 | |
729 | return 0; | |
730 | } | |
731 | ||
732 | /* | |
733 | * This function creates buffer descriptor ring for RX | |
734 | */ | |
735 | static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) | |
736 | { | |
737 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 738 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
739 | |
740 | /* | |
741 | * driver maintaines the read pointer and firmware maintaines the write | |
742 | * pointer. The write pointer starts at 0 (zero) while the read pointer | |
743 | * starts at zero with rollover bit set | |
744 | */ | |
745 | card->rxbd_wrptr = 0; | |
dd04e6ac | 746 | card->rxbd_rdptr = reg->rx_rollover_ind; |
d930faee | 747 | |
ca8f2112 AP |
748 | if (reg->pfu_enabled) |
749 | card->rxbd_ring_size = sizeof(struct mwifiex_pfu_buf_desc) * | |
750 | MWIFIEX_MAX_TXRX_BD; | |
751 | else | |
752 | card->rxbd_ring_size = sizeof(struct mwifiex_pcie_buf_desc) * | |
753 | MWIFIEX_MAX_TXRX_BD; | |
754 | ||
d930faee | 755 | dev_dbg(adapter->dev, "info: rxbd_ring: Allocating %d bytes\n", |
f57c1edc | 756 | card->rxbd_ring_size); |
fc331460 AP |
757 | card->rxbd_ring_vbase = pci_alloc_consistent(card->dev, |
758 | card->rxbd_ring_size, | |
759 | &card->rxbd_ring_pbase); | |
d930faee | 760 | if (!card->rxbd_ring_vbase) { |
fc331460 AP |
761 | dev_err(adapter->dev, |
762 | "allocate consistent memory (%d bytes) failed!\n", | |
763 | card->rxbd_ring_size); | |
8c53e42d | 764 | return -ENOMEM; |
d930faee | 765 | } |
d930faee | 766 | |
f57c1edc YAP |
767 | dev_dbg(adapter->dev, |
768 | "info: rxbd_ring - base: %p, pbase: %#x:%x, len: %#x\n", | |
769 | card->rxbd_ring_vbase, (u32)card->rxbd_ring_pbase, | |
770 | (u32)((u64)card->rxbd_ring_pbase >> 32), | |
771 | card->rxbd_ring_size); | |
d930faee | 772 | |
0732484b | 773 | return mwifiex_init_rxq_ring(adapter); |
d930faee AK |
774 | } |
775 | ||
776 | /* | |
777 | * This function deletes Buffer descriptor ring for RX | |
778 | */ | |
779 | static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) | |
780 | { | |
781 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 782 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 783 | |
0732484b | 784 | mwifiex_cleanup_rxq_ring(adapter); |
d930faee | 785 | |
fc331460 AP |
786 | if (card->rxbd_ring_vbase) |
787 | pci_free_consistent(card->dev, card->rxbd_ring_size, | |
788 | card->rxbd_ring_vbase, | |
789 | card->rxbd_ring_pbase); | |
d930faee AK |
790 | card->rxbd_ring_size = 0; |
791 | card->rxbd_wrptr = 0; | |
dd04e6ac | 792 | card->rxbd_rdptr = 0 | reg->rx_rollover_ind; |
d930faee | 793 | card->rxbd_ring_vbase = NULL; |
fc331460 | 794 | card->rxbd_ring_pbase = 0; |
d930faee AK |
795 | |
796 | return 0; | |
797 | } | |
798 | ||
799 | /* | |
800 | * This function creates buffer descriptor ring for Events | |
801 | */ | |
802 | static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) | |
803 | { | |
804 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 805 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
806 | |
807 | /* | |
808 | * driver maintaines the read pointer and firmware maintaines the write | |
809 | * pointer. The write pointer starts at 0 (zero) while the read pointer | |
810 | * starts at zero with rollover bit set | |
811 | */ | |
812 | card->evtbd_wrptr = 0; | |
dd04e6ac | 813 | card->evtbd_rdptr = reg->evt_rollover_ind; |
d930faee | 814 | |
e05dc3e9 | 815 | card->evtbd_ring_size = sizeof(struct mwifiex_evt_buf_desc) * |
ca8f2112 AP |
816 | MWIFIEX_MAX_EVT_BD; |
817 | ||
d930faee | 818 | dev_dbg(adapter->dev, "info: evtbd_ring: Allocating %d bytes\n", |
f57c1edc | 819 | card->evtbd_ring_size); |
fc331460 AP |
820 | card->evtbd_ring_vbase = pci_alloc_consistent(card->dev, |
821 | card->evtbd_ring_size, | |
822 | &card->evtbd_ring_pbase); | |
d930faee | 823 | if (!card->evtbd_ring_vbase) { |
f57c1edc | 824 | dev_err(adapter->dev, |
fc331460 AP |
825 | "allocate consistent memory (%d bytes) failed!\n", |
826 | card->evtbd_ring_size); | |
8c53e42d | 827 | return -ENOMEM; |
d930faee | 828 | } |
d930faee | 829 | |
f57c1edc YAP |
830 | dev_dbg(adapter->dev, |
831 | "info: CMDRSP/EVT bd_ring - base: %p pbase: %#x:%x len: %#x\n", | |
832 | card->evtbd_ring_vbase, (u32)card->evtbd_ring_pbase, | |
833 | (u32)((u64)card->evtbd_ring_pbase >> 32), | |
834 | card->evtbd_ring_size); | |
d930faee | 835 | |
0732484b | 836 | return mwifiex_pcie_init_evt_ring(adapter); |
d930faee AK |
837 | } |
838 | ||
839 | /* | |
840 | * This function deletes Buffer descriptor ring for Events | |
841 | */ | |
842 | static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter) | |
843 | { | |
844 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 845 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 846 | |
0732484b | 847 | mwifiex_cleanup_evt_ring(adapter); |
d930faee | 848 | |
fc331460 AP |
849 | if (card->evtbd_ring_vbase) |
850 | pci_free_consistent(card->dev, card->evtbd_ring_size, | |
851 | card->evtbd_ring_vbase, | |
852 | card->evtbd_ring_pbase); | |
d930faee | 853 | card->evtbd_wrptr = 0; |
dd04e6ac | 854 | card->evtbd_rdptr = 0 | reg->evt_rollover_ind; |
d930faee AK |
855 | card->evtbd_ring_size = 0; |
856 | card->evtbd_ring_vbase = NULL; | |
fc331460 | 857 | card->evtbd_ring_pbase = 0; |
d930faee AK |
858 | |
859 | return 0; | |
860 | } | |
861 | ||
862 | /* | |
863 | * This function allocates a buffer for CMDRSP | |
864 | */ | |
865 | static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter) | |
866 | { | |
867 | struct pcie_service_card *card = adapter->card; | |
868 | struct sk_buff *skb; | |
869 | ||
870 | /* Allocate memory for receiving command response data */ | |
871 | skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); | |
872 | if (!skb) { | |
f57c1edc YAP |
873 | dev_err(adapter->dev, |
874 | "Unable to allocate skb for command response data.\n"); | |
d930faee AK |
875 | return -ENOMEM; |
876 | } | |
d930faee | 877 | skb_put(skb, MWIFIEX_UPLD_SIZE); |
fc331460 AP |
878 | if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, |
879 | PCI_DMA_FROMDEVICE)) | |
880 | return -1; | |
d930faee | 881 | |
fc331460 | 882 | card->cmdrsp_buf = skb; |
d930faee AK |
883 | |
884 | return 0; | |
885 | } | |
886 | ||
887 | /* | |
888 | * This function deletes a buffer for CMDRSP | |
889 | */ | |
890 | static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter) | |
891 | { | |
892 | struct pcie_service_card *card; | |
893 | ||
894 | if (!adapter) | |
895 | return 0; | |
896 | ||
897 | card = adapter->card; | |
898 | ||
fc331460 | 899 | if (card && card->cmdrsp_buf) { |
dbccc92b AD |
900 | mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf, |
901 | PCI_DMA_FROMDEVICE); | |
d930faee | 902 | dev_kfree_skb_any(card->cmdrsp_buf); |
fc331460 | 903 | } |
d930faee | 904 | |
fc331460 | 905 | if (card && card->cmd_buf) { |
dbccc92b AD |
906 | mwifiex_unmap_pci_memory(adapter, card->cmd_buf, |
907 | PCI_DMA_TODEVICE); | |
fc331460 | 908 | } |
d930faee AK |
909 | return 0; |
910 | } | |
911 | ||
912 | /* | |
913 | * This function allocates a buffer for sleep cookie | |
914 | */ | |
915 | static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter) | |
916 | { | |
d930faee AK |
917 | struct pcie_service_card *card = adapter->card; |
918 | ||
fc331460 AP |
919 | card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32), |
920 | &card->sleep_cookie_pbase); | |
921 | if (!card->sleep_cookie_vbase) { | |
922 | dev_err(adapter->dev, "pci_alloc_consistent failed!\n"); | |
d930faee AK |
923 | return -ENOMEM; |
924 | } | |
d930faee | 925 | /* Init val of Sleep Cookie */ |
fc331460 | 926 | *(u32 *)card->sleep_cookie_vbase = FW_AWAKE_COOKIE; |
d930faee AK |
927 | |
928 | dev_dbg(adapter->dev, "alloc_scook: sleep cookie=0x%x\n", | |
fc331460 | 929 | *((u32 *)card->sleep_cookie_vbase)); |
d930faee AK |
930 | |
931 | return 0; | |
932 | } | |
933 | ||
934 | /* | |
935 | * This function deletes buffer for sleep cookie | |
936 | */ | |
937 | static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter) | |
938 | { | |
939 | struct pcie_service_card *card; | |
940 | ||
941 | if (!adapter) | |
942 | return 0; | |
943 | ||
944 | card = adapter->card; | |
945 | ||
fc331460 AP |
946 | if (card && card->sleep_cookie_vbase) { |
947 | pci_free_consistent(card->dev, sizeof(u32), | |
948 | card->sleep_cookie_vbase, | |
949 | card->sleep_cookie_pbase); | |
950 | card->sleep_cookie_vbase = NULL; | |
d930faee AK |
951 | } |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
fbd7e7ac AP |
956 | /* This function flushes the TX buffer descriptor ring |
957 | * This function defined as handler is also called while cleaning TXRX | |
958 | * during disconnect/ bss stop. | |
959 | */ | |
960 | static int mwifiex_clean_pcie_ring_buf(struct mwifiex_adapter *adapter) | |
961 | { | |
962 | struct pcie_service_card *card = adapter->card; | |
fbd7e7ac | 963 | |
48f4d916 | 964 | if (!mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) { |
fbd7e7ac AP |
965 | card->txbd_flush = 1; |
966 | /* write pointer already set at last send | |
967 | * send dnld-rdy intr again, wait for completion. | |
968 | */ | |
969 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
970 | CPU_INTR_DNLD_RDY)) { | |
971 | dev_err(adapter->dev, | |
972 | "failed to assert dnld-rdy interrupt.\n"); | |
973 | return -1; | |
974 | } | |
975 | } | |
976 | return 0; | |
977 | } | |
978 | ||
d930faee | 979 | /* |
e7f767a7 | 980 | * This function unmaps and frees downloaded data buffer |
d930faee | 981 | */ |
e7f767a7 | 982 | static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter) |
d930faee | 983 | { |
e7f767a7 | 984 | struct sk_buff *skb; |
ca8f2112 | 985 | u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0; |
e05dc3e9 | 986 | struct mwifiex_pcie_buf_desc *desc; |
ca8f2112 | 987 | struct mwifiex_pfu_buf_desc *desc2; |
d930faee | 988 | struct pcie_service_card *card = adapter->card; |
dd04e6ac | 989 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
990 | |
991 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) | |
992 | mwifiex_pm_wakeup_card(adapter); | |
993 | ||
994 | /* Read the TX ring read pointer set by firmware */ | |
dd04e6ac | 995 | if (mwifiex_read_reg(adapter, reg->tx_rdptr, &rdptr)) { |
f57c1edc | 996 | dev_err(adapter->dev, |
dd04e6ac | 997 | "SEND COMP: failed to read reg->tx_rdptr\n"); |
d930faee AK |
998 | return -1; |
999 | } | |
1000 | ||
e7f767a7 AP |
1001 | dev_dbg(adapter->dev, "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n", |
1002 | card->txbd_rdptr, rdptr); | |
d930faee | 1003 | |
ca8f2112 | 1004 | num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; |
e7f767a7 | 1005 | /* free from previous txbd_rdptr to current txbd_rdptr */ |
dd04e6ac AP |
1006 | while (((card->txbd_rdptr & reg->tx_mask) != |
1007 | (rdptr & reg->tx_mask)) || | |
1008 | ((card->txbd_rdptr & reg->tx_rollover_ind) != | |
1009 | (rdptr & reg->tx_rollover_ind))) { | |
ca8f2112 AP |
1010 | wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >> |
1011 | reg->tx_start_ptr; | |
e7f767a7 AP |
1012 | |
1013 | skb = card->tx_buf_list[wrdoneidx]; | |
dbccc92b | 1014 | |
e7f767a7 AP |
1015 | if (skb) { |
1016 | dev_dbg(adapter->dev, | |
1017 | "SEND COMP: Detach skb %p at txbd_rdidx=%d\n", | |
1018 | skb, wrdoneidx); | |
dbccc92b AD |
1019 | mwifiex_unmap_pci_memory(adapter, skb, |
1020 | PCI_DMA_TODEVICE); | |
e7f767a7 AP |
1021 | |
1022 | unmap_count++; | |
1023 | ||
1024 | if (card->txbd_flush) | |
1025 | mwifiex_write_data_complete(adapter, skb, 0, | |
1026 | -1); | |
1027 | else | |
1028 | mwifiex_write_data_complete(adapter, skb, 0, 0); | |
1029 | } | |
1030 | ||
1031 | card->tx_buf_list[wrdoneidx] = NULL; | |
ca8f2112 AP |
1032 | |
1033 | if (reg->pfu_enabled) { | |
45d18c56 | 1034 | desc2 = card->txbd_ring[wrdoneidx]; |
ca8f2112 AP |
1035 | memset(desc2, 0, sizeof(*desc2)); |
1036 | } else { | |
1037 | desc = card->txbd_ring[wrdoneidx]; | |
1038 | memset(desc, 0, sizeof(*desc)); | |
1039 | } | |
1040 | switch (card->dev->device) { | |
1041 | case PCIE_DEVICE_ID_MARVELL_88W8766P: | |
1042 | card->txbd_rdptr++; | |
1043 | break; | |
1044 | case PCIE_DEVICE_ID_MARVELL_88W8897: | |
1045 | card->txbd_rdptr += reg->ring_tx_start_ptr; | |
1046 | break; | |
1047 | } | |
1048 | ||
e7f767a7 | 1049 | |
dd04e6ac | 1050 | if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs) |
e7f767a7 | 1051 | card->txbd_rdptr = ((card->txbd_rdptr & |
dd04e6ac AP |
1052 | reg->tx_rollover_ind) ^ |
1053 | reg->tx_rollover_ind); | |
e7f767a7 AP |
1054 | } |
1055 | ||
1056 | if (unmap_count) | |
1057 | adapter->data_sent = false; | |
1058 | ||
1059 | if (card->txbd_flush) { | |
3d482038 | 1060 | if (mwifiex_pcie_txbd_empty(card, card->txbd_rdptr)) |
e7f767a7 AP |
1061 | card->txbd_flush = 0; |
1062 | else | |
1063 | mwifiex_clean_pcie_ring_buf(adapter); | |
1064 | } | |
1065 | ||
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | /* This function sends data buffer to device. First 4 bytes of payload | |
1070 | * are filled with payload length and payload type. Then this payload | |
1071 | * is mapped to PCI device memory. Tx ring pointers are advanced accordingly. | |
1072 | * Download ready interrupt to FW is deffered if Tx ring is not full and | |
1073 | * additional payload can be accomodated. | |
8d767dcb | 1074 | * Caller must ensure tx_param parameter to this function is not NULL. |
e7f767a7 AP |
1075 | */ |
1076 | static int | |
1077 | mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, | |
1078 | struct mwifiex_tx_param *tx_param) | |
1079 | { | |
1080 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1081 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
ca8f2112 | 1082 | u32 wrindx, num_tx_buffs, rx_val; |
e7f767a7 AP |
1083 | int ret; |
1084 | dma_addr_t buf_pa; | |
9931078e BZ |
1085 | struct mwifiex_pcie_buf_desc *desc = NULL; |
1086 | struct mwifiex_pfu_buf_desc *desc2 = NULL; | |
e7f767a7 AP |
1087 | __le16 *tmp; |
1088 | ||
1089 | if (!(skb->data && skb->len)) { | |
1090 | dev_err(adapter->dev, "%s(): invalid parameter <%p, %#x>\n", | |
1091 | __func__, skb->data, skb->len); | |
1092 | return -1; | |
1093 | } | |
1094 | ||
1095 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) | |
1096 | mwifiex_pm_wakeup_card(adapter); | |
1097 | ||
ca8f2112 | 1098 | num_tx_buffs = MWIFIEX_MAX_TXRX_BD << reg->tx_start_ptr; |
e7f767a7 AP |
1099 | dev_dbg(adapter->dev, "info: SEND DATA: <Rd: %#x, Wr: %#x>\n", |
1100 | card->txbd_rdptr, card->txbd_wrptr); | |
1101 | if (mwifiex_pcie_txbd_not_full(card)) { | |
d930faee AK |
1102 | u8 *payload; |
1103 | ||
1104 | adapter->data_sent = true; | |
e7f767a7 | 1105 | payload = skb->data; |
d930faee AK |
1106 | tmp = (__le16 *)&payload[0]; |
1107 | *tmp = cpu_to_le16((u16)skb->len); | |
1108 | tmp = (__le16 *)&payload[2]; | |
1109 | *tmp = cpu_to_le16(MWIFIEX_TYPE_DATA); | |
e7f767a7 | 1110 | |
dbccc92b | 1111 | if (mwifiex_map_pci_memory(adapter, skb, skb->len, |
e7f767a7 AP |
1112 | PCI_DMA_TODEVICE)) |
1113 | return -1; | |
1114 | ||
ca8f2112 | 1115 | wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; |
dbccc92b | 1116 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); |
e7f767a7 | 1117 | card->tx_buf_list[wrindx] = skb; |
d930faee | 1118 | |
ca8f2112 | 1119 | if (reg->pfu_enabled) { |
45d18c56 | 1120 | desc2 = card->txbd_ring[wrindx]; |
ca8f2112 AP |
1121 | desc2->paddr = buf_pa; |
1122 | desc2->len = (u16)skb->len; | |
1123 | desc2->frag_len = (u16)skb->len; | |
1124 | desc2->offset = 0; | |
1125 | desc2->flags = MWIFIEX_BD_FLAG_FIRST_DESC | | |
1126 | MWIFIEX_BD_FLAG_LAST_DESC; | |
1127 | } else { | |
1128 | desc = card->txbd_ring[wrindx]; | |
1129 | desc->paddr = buf_pa; | |
1130 | desc->len = (u16)skb->len; | |
1131 | desc->flags = MWIFIEX_BD_FLAG_FIRST_DESC | | |
1132 | MWIFIEX_BD_FLAG_LAST_DESC; | |
1133 | } | |
1134 | ||
1135 | switch (card->dev->device) { | |
1136 | case PCIE_DEVICE_ID_MARVELL_88W8766P: | |
1137 | card->txbd_wrptr++; | |
1138 | break; | |
1139 | case PCIE_DEVICE_ID_MARVELL_88W8897: | |
1140 | card->txbd_wrptr += reg->ring_tx_start_ptr; | |
1141 | break; | |
1142 | } | |
1143 | ||
1144 | if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs) | |
d930faee | 1145 | card->txbd_wrptr = ((card->txbd_wrptr & |
dd04e6ac AP |
1146 | reg->tx_rollover_ind) ^ |
1147 | reg->tx_rollover_ind); | |
d930faee | 1148 | |
ca8f2112 | 1149 | rx_val = card->rxbd_rdptr & reg->rx_wrap_mask; |
dd04e6ac AP |
1150 | /* Write the TX ring write pointer in to reg->tx_wrptr */ |
1151 | if (mwifiex_write_reg(adapter, reg->tx_wrptr, | |
ca8f2112 | 1152 | card->txbd_wrptr | rx_val)) { |
f57c1edc | 1153 | dev_err(adapter->dev, |
dd04e6ac | 1154 | "SEND DATA: failed to write reg->tx_wrptr\n"); |
e7f767a7 AP |
1155 | ret = -1; |
1156 | goto done_unmap; | |
d930faee | 1157 | } |
e7f767a7 AP |
1158 | if ((mwifiex_pcie_txbd_not_full(card)) && |
1159 | tx_param->next_pkt_len) { | |
1160 | /* have more packets and TxBD still can hold more */ | |
1161 | dev_dbg(adapter->dev, | |
1162 | "SEND DATA: delay dnld-rdy interrupt.\n"); | |
1163 | adapter->data_sent = false; | |
1164 | } else { | |
1165 | /* Send the TX ready interrupt */ | |
1166 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
1167 | CPU_INTR_DNLD_RDY)) { | |
1168 | dev_err(adapter->dev, | |
1169 | "SEND DATA: failed to assert dnld-rdy interrupt.\n"); | |
1170 | ret = -1; | |
1171 | goto done_unmap; | |
1172 | } | |
d930faee AK |
1173 | } |
1174 | dev_dbg(adapter->dev, "info: SEND DATA: Updated <Rd: %#x, Wr: " | |
f57c1edc | 1175 | "%#x> and sent packet to firmware successfully\n", |
e7f767a7 | 1176 | card->txbd_rdptr, card->txbd_wrptr); |
d930faee | 1177 | } else { |
f57c1edc YAP |
1178 | dev_dbg(adapter->dev, |
1179 | "info: TX Ring full, can't send packets to fw\n"); | |
d930faee AK |
1180 | adapter->data_sent = true; |
1181 | /* Send the TX ready interrupt */ | |
1182 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
1183 | CPU_INTR_DNLD_RDY)) | |
f57c1edc YAP |
1184 | dev_err(adapter->dev, |
1185 | "SEND DATA: failed to assert door-bell intr\n"); | |
d930faee AK |
1186 | return -EBUSY; |
1187 | } | |
1188 | ||
e7f767a7 AP |
1189 | return -EINPROGRESS; |
1190 | done_unmap: | |
dbccc92b | 1191 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
e7f767a7 | 1192 | card->tx_buf_list[wrindx] = NULL; |
ca8f2112 AP |
1193 | if (reg->pfu_enabled) |
1194 | memset(desc2, 0, sizeof(*desc2)); | |
1195 | else | |
1196 | memset(desc, 0, sizeof(*desc)); | |
1197 | ||
e7f767a7 | 1198 | return ret; |
d930faee AK |
1199 | } |
1200 | ||
1201 | /* | |
1202 | * This function handles received buffer ring and | |
1203 | * dispatches packets to upper | |
1204 | */ | |
1205 | static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) | |
1206 | { | |
1207 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1208 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
ca8f2112 | 1209 | u32 wrptr, rd_index, tx_val; |
e7f767a7 | 1210 | dma_addr_t buf_pa; |
d930faee AK |
1211 | int ret = 0; |
1212 | struct sk_buff *skb_tmp = NULL; | |
e05dc3e9 | 1213 | struct mwifiex_pcie_buf_desc *desc; |
ca8f2112 | 1214 | struct mwifiex_pfu_buf_desc *desc2; |
d930faee | 1215 | |
e7f767a7 AP |
1216 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) |
1217 | mwifiex_pm_wakeup_card(adapter); | |
1218 | ||
d930faee | 1219 | /* Read the RX ring Write pointer set by firmware */ |
dd04e6ac | 1220 | if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { |
f57c1edc | 1221 | dev_err(adapter->dev, |
dd04e6ac | 1222 | "RECV DATA: failed to read reg->rx_wrptr\n"); |
d930faee AK |
1223 | ret = -1; |
1224 | goto done; | |
1225 | } | |
e7f767a7 | 1226 | card->rxbd_wrptr = wrptr; |
d930faee | 1227 | |
dd04e6ac AP |
1228 | while (((wrptr & reg->rx_mask) != |
1229 | (card->rxbd_rdptr & reg->rx_mask)) || | |
1230 | ((wrptr & reg->rx_rollover_ind) == | |
1231 | (card->rxbd_rdptr & reg->rx_rollover_ind))) { | |
d930faee AK |
1232 | struct sk_buff *skb_data; |
1233 | u16 rx_len; | |
e7f767a7 | 1234 | __le16 pkt_len; |
d930faee | 1235 | |
dd04e6ac | 1236 | rd_index = card->rxbd_rdptr & reg->rx_mask; |
d930faee AK |
1237 | skb_data = card->rx_buf_list[rd_index]; |
1238 | ||
bb8e6a1e AK |
1239 | /* If skb allocation was failed earlier for Rx packet, |
1240 | * rx_buf_list[rd_index] would have been left with a NULL. | |
1241 | */ | |
1242 | if (!skb_data) | |
1243 | return -ENOMEM; | |
1244 | ||
dbccc92b | 1245 | mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE); |
e7f767a7 AP |
1246 | card->rx_buf_list[rd_index] = NULL; |
1247 | ||
d930faee | 1248 | /* Get data length from interface header - |
e7f767a7 AP |
1249 | * first 2 bytes for len, next 2 bytes is for type |
1250 | */ | |
1251 | pkt_len = *((__le16 *)skb_data->data); | |
1252 | rx_len = le16_to_cpu(pkt_len); | |
1253 | skb_put(skb_data, rx_len); | |
f57c1edc YAP |
1254 | dev_dbg(adapter->dev, |
1255 | "info: RECV DATA: Rd=%#x, Wr=%#x, Len=%d\n", | |
1256 | card->rxbd_rdptr, wrptr, rx_len); | |
e7f767a7 AP |
1257 | skb_pull(skb_data, INTF_HEADER_LEN); |
1258 | mwifiex_handle_rx_packet(adapter, skb_data); | |
1259 | ||
1260 | skb_tmp = dev_alloc_skb(MWIFIEX_RX_DATA_BUF_SIZE); | |
d930faee | 1261 | if (!skb_tmp) { |
e7f767a7 AP |
1262 | dev_err(adapter->dev, |
1263 | "Unable to allocate skb.\n"); | |
1264 | return -ENOMEM; | |
d930faee AK |
1265 | } |
1266 | ||
e7f767a7 AP |
1267 | if (mwifiex_map_pci_memory(adapter, skb_tmp, |
1268 | MWIFIEX_RX_DATA_BUF_SIZE, | |
1269 | PCI_DMA_FROMDEVICE)) | |
1270 | return -1; | |
1271 | ||
dbccc92b | 1272 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp); |
e7f767a7 AP |
1273 | |
1274 | dev_dbg(adapter->dev, | |
1275 | "RECV DATA: Attach new sk_buff %p at rxbd_rdidx=%d\n", | |
1276 | skb_tmp, rd_index); | |
1277 | card->rx_buf_list[rd_index] = skb_tmp; | |
ca8f2112 AP |
1278 | |
1279 | if (reg->pfu_enabled) { | |
45d18c56 | 1280 | desc2 = card->rxbd_ring[rd_index]; |
ca8f2112 AP |
1281 | desc2->paddr = buf_pa; |
1282 | desc2->len = skb_tmp->len; | |
1283 | desc2->frag_len = skb_tmp->len; | |
1284 | desc2->offset = 0; | |
1285 | desc2->flags = reg->ring_flag_sop | reg->ring_flag_eop; | |
1286 | } else { | |
1287 | desc = card->rxbd_ring[rd_index]; | |
1288 | desc->paddr = buf_pa; | |
1289 | desc->len = skb_tmp->len; | |
1290 | desc->flags = 0; | |
1291 | } | |
d930faee | 1292 | |
dd04e6ac | 1293 | if ((++card->rxbd_rdptr & reg->rx_mask) == |
d930faee AK |
1294 | MWIFIEX_MAX_TXRX_BD) { |
1295 | card->rxbd_rdptr = ((card->rxbd_rdptr & | |
dd04e6ac AP |
1296 | reg->rx_rollover_ind) ^ |
1297 | reg->rx_rollover_ind); | |
d930faee AK |
1298 | } |
1299 | dev_dbg(adapter->dev, "info: RECV DATA: <Rd: %#x, Wr: %#x>\n", | |
f57c1edc | 1300 | card->rxbd_rdptr, wrptr); |
d930faee | 1301 | |
ca8f2112 | 1302 | tx_val = card->txbd_wrptr & reg->tx_wrap_mask; |
dd04e6ac AP |
1303 | /* Write the RX ring read pointer in to reg->rx_rdptr */ |
1304 | if (mwifiex_write_reg(adapter, reg->rx_rdptr, | |
ca8f2112 | 1305 | card->rxbd_rdptr | tx_val)) { |
f57c1edc | 1306 | dev_err(adapter->dev, |
dd04e6ac | 1307 | "RECV DATA: failed to write reg->rx_rdptr\n"); |
d930faee AK |
1308 | ret = -1; |
1309 | goto done; | |
1310 | } | |
1311 | ||
1312 | /* Read the RX ring Write pointer set by firmware */ | |
dd04e6ac | 1313 | if (mwifiex_read_reg(adapter, reg->rx_wrptr, &wrptr)) { |
f57c1edc | 1314 | dev_err(adapter->dev, |
dd04e6ac | 1315 | "RECV DATA: failed to read reg->rx_wrptr\n"); |
d930faee AK |
1316 | ret = -1; |
1317 | goto done; | |
1318 | } | |
f57c1edc YAP |
1319 | dev_dbg(adapter->dev, |
1320 | "info: RECV DATA: Rcvd packet from fw successfully\n"); | |
e7f767a7 | 1321 | card->rxbd_wrptr = wrptr; |
d930faee AK |
1322 | } |
1323 | ||
1324 | done: | |
d930faee AK |
1325 | return ret; |
1326 | } | |
1327 | ||
1328 | /* | |
1329 | * This function downloads the boot command to device | |
1330 | */ | |
1331 | static int | |
1332 | mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) | |
1333 | { | |
fc331460 AP |
1334 | dma_addr_t buf_pa; |
1335 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1336 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 1337 | |
fc331460 | 1338 | if (!(skb->data && skb->len)) { |
f57c1edc | 1339 | dev_err(adapter->dev, |
fc331460 AP |
1340 | "Invalid parameter in %s <%p. len %d>\n", |
1341 | __func__, skb->data, skb->len); | |
d930faee AK |
1342 | return -1; |
1343 | } | |
1344 | ||
fc331460 AP |
1345 | if (mwifiex_map_pci_memory(adapter, skb, skb->len , PCI_DMA_TODEVICE)) |
1346 | return -1; | |
1347 | ||
dbccc92b | 1348 | buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); |
fc331460 | 1349 | |
dd04e6ac AP |
1350 | /* Write the lower 32bits of the physical address to low command |
1351 | * address scratch register | |
1352 | */ | |
1353 | if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, (u32)buf_pa)) { | |
f57c1edc YAP |
1354 | dev_err(adapter->dev, |
1355 | "%s: failed to write download command to boot code.\n", | |
1356 | __func__); | |
dbccc92b | 1357 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
d930faee AK |
1358 | return -1; |
1359 | } | |
1360 | ||
dd04e6ac AP |
1361 | /* Write the upper 32bits of the physical address to high command |
1362 | * address scratch register | |
1363 | */ | |
1364 | if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, | |
fc331460 | 1365 | (u32)((u64)buf_pa >> 32))) { |
f57c1edc YAP |
1366 | dev_err(adapter->dev, |
1367 | "%s: failed to write download command to boot code.\n", | |
1368 | __func__); | |
dbccc92b | 1369 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
d930faee AK |
1370 | return -1; |
1371 | } | |
1372 | ||
dd04e6ac AP |
1373 | /* Write the command length to cmd_size scratch register */ |
1374 | if (mwifiex_write_reg(adapter, reg->cmd_size, skb->len)) { | |
f57c1edc | 1375 | dev_err(adapter->dev, |
dd04e6ac | 1376 | "%s: failed to write command len to cmd_size scratch reg\n", |
f57c1edc | 1377 | __func__); |
dbccc92b | 1378 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
d930faee AK |
1379 | return -1; |
1380 | } | |
1381 | ||
1382 | /* Ring the door bell */ | |
1383 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
1384 | CPU_INTR_DOOR_BELL)) { | |
f57c1edc YAP |
1385 | dev_err(adapter->dev, |
1386 | "%s: failed to assert door-bell intr\n", __func__); | |
dbccc92b | 1387 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
d930faee AK |
1388 | return -1; |
1389 | } | |
1390 | ||
1391 | return 0; | |
1392 | } | |
1393 | ||
c6d1d87a AP |
1394 | /* This function init rx port in firmware which in turn enables to receive data |
1395 | * from device before transmitting any packet. | |
1396 | */ | |
1397 | static int mwifiex_pcie_init_fw_port(struct mwifiex_adapter *adapter) | |
1398 | { | |
1399 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1400 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
ca8f2112 | 1401 | int tx_wrap = card->txbd_wrptr & reg->tx_wrap_mask; |
c6d1d87a | 1402 | |
dd04e6ac | 1403 | /* Write the RX ring read pointer in to reg->rx_rdptr */ |
ca8f2112 AP |
1404 | if (mwifiex_write_reg(adapter, reg->rx_rdptr, card->rxbd_rdptr | |
1405 | tx_wrap)) { | |
c6d1d87a | 1406 | dev_err(adapter->dev, |
dd04e6ac | 1407 | "RECV DATA: failed to write reg->rx_rdptr\n"); |
c6d1d87a AP |
1408 | return -1; |
1409 | } | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | /* This function downloads commands to the device | |
d930faee AK |
1414 | */ |
1415 | static int | |
1416 | mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) | |
1417 | { | |
1418 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1419 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 1420 | int ret = 0; |
fc331460 AP |
1421 | dma_addr_t cmd_buf_pa, cmdrsp_buf_pa; |
1422 | u8 *payload = (u8 *)skb->data; | |
d930faee AK |
1423 | |
1424 | if (!(skb->data && skb->len)) { | |
1425 | dev_err(adapter->dev, "Invalid parameter in %s <%p, %#x>\n", | |
f57c1edc | 1426 | __func__, skb->data, skb->len); |
d930faee AK |
1427 | return -1; |
1428 | } | |
1429 | ||
1430 | /* Make sure a command response buffer is available */ | |
1431 | if (!card->cmdrsp_buf) { | |
f57c1edc YAP |
1432 | dev_err(adapter->dev, |
1433 | "No response buffer available, send command failed\n"); | |
d930faee AK |
1434 | return -EBUSY; |
1435 | } | |
1436 | ||
fc331460 AP |
1437 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) |
1438 | mwifiex_pm_wakeup_card(adapter); | |
d930faee AK |
1439 | |
1440 | adapter->cmd_sent = true; | |
fc331460 AP |
1441 | |
1442 | *(__le16 *)&payload[0] = cpu_to_le16((u16)skb->len); | |
1443 | *(__le16 *)&payload[2] = cpu_to_le16(MWIFIEX_TYPE_CMD); | |
1444 | ||
1445 | if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE)) | |
1446 | return -1; | |
1447 | ||
1448 | card->cmd_buf = skb; | |
d930faee AK |
1449 | |
1450 | /* To send a command, the driver will: | |
1451 | 1. Write the 64bit physical address of the data buffer to | |
dd04e6ac | 1452 | cmd response address low + cmd response address high |
d930faee AK |
1453 | 2. Ring the door bell (i.e. set the door bell interrupt) |
1454 | ||
1455 | In response to door bell interrupt, the firmware will perform | |
1456 | the DMA of the command packet (first header to obtain the total | |
1457 | length and then rest of the command). | |
1458 | */ | |
1459 | ||
1460 | if (card->cmdrsp_buf) { | |
dbccc92b | 1461 | cmdrsp_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmdrsp_buf); |
d930faee AK |
1462 | /* Write the lower 32bits of the cmdrsp buffer physical |
1463 | address */ | |
dd04e6ac | 1464 | if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, |
fc331460 | 1465 | (u32)cmdrsp_buf_pa)) { |
f57c1edc YAP |
1466 | dev_err(adapter->dev, |
1467 | "Failed to write download cmd to boot code.\n"); | |
d930faee AK |
1468 | ret = -1; |
1469 | goto done; | |
1470 | } | |
1471 | /* Write the upper 32bits of the cmdrsp buffer physical | |
1472 | address */ | |
dd04e6ac | 1473 | if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, |
fc331460 | 1474 | (u32)((u64)cmdrsp_buf_pa >> 32))) { |
f57c1edc YAP |
1475 | dev_err(adapter->dev, |
1476 | "Failed to write download cmd to boot code.\n"); | |
d930faee AK |
1477 | ret = -1; |
1478 | goto done; | |
1479 | } | |
1480 | } | |
1481 | ||
dbccc92b | 1482 | cmd_buf_pa = MWIFIEX_SKB_DMA_ADDR(card->cmd_buf); |
dd04e6ac AP |
1483 | /* Write the lower 32bits of the physical address to reg->cmd_addr_lo */ |
1484 | if (mwifiex_write_reg(adapter, reg->cmd_addr_lo, | |
1485 | (u32)cmd_buf_pa)) { | |
f57c1edc YAP |
1486 | dev_err(adapter->dev, |
1487 | "Failed to write download cmd to boot code.\n"); | |
d930faee AK |
1488 | ret = -1; |
1489 | goto done; | |
1490 | } | |
dd04e6ac AP |
1491 | /* Write the upper 32bits of the physical address to reg->cmd_addr_hi */ |
1492 | if (mwifiex_write_reg(adapter, reg->cmd_addr_hi, | |
fc331460 | 1493 | (u32)((u64)cmd_buf_pa >> 32))) { |
f57c1edc YAP |
1494 | dev_err(adapter->dev, |
1495 | "Failed to write download cmd to boot code.\n"); | |
d930faee AK |
1496 | ret = -1; |
1497 | goto done; | |
1498 | } | |
1499 | ||
dd04e6ac AP |
1500 | /* Write the command length to reg->cmd_size */ |
1501 | if (mwifiex_write_reg(adapter, reg->cmd_size, | |
1502 | card->cmd_buf->len)) { | |
f57c1edc | 1503 | dev_err(adapter->dev, |
dd04e6ac | 1504 | "Failed to write cmd len to reg->cmd_size\n"); |
d930faee AK |
1505 | ret = -1; |
1506 | goto done; | |
1507 | } | |
1508 | ||
1509 | /* Ring the door bell */ | |
1510 | if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, | |
1511 | CPU_INTR_DOOR_BELL)) { | |
f57c1edc YAP |
1512 | dev_err(adapter->dev, |
1513 | "Failed to assert door-bell intr\n"); | |
d930faee AK |
1514 | ret = -1; |
1515 | goto done; | |
1516 | } | |
1517 | ||
1518 | done: | |
1519 | if (ret) | |
1520 | adapter->cmd_sent = false; | |
1521 | ||
1522 | return 0; | |
1523 | } | |
1524 | ||
1525 | /* | |
1526 | * This function handles command complete interrupt | |
1527 | */ | |
1528 | static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) | |
1529 | { | |
1530 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1531 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
f57c1edc | 1532 | struct sk_buff *skb = card->cmdrsp_buf; |
d930faee | 1533 | int count = 0; |
fc331460 AP |
1534 | u16 rx_len; |
1535 | __le16 pkt_len; | |
d930faee AK |
1536 | |
1537 | dev_dbg(adapter->dev, "info: Rx CMD Response\n"); | |
1538 | ||
dbccc92b | 1539 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE); |
fc331460 | 1540 | |
189b3299 AD |
1541 | /* Unmap the command as a response has been received. */ |
1542 | if (card->cmd_buf) { | |
1543 | mwifiex_unmap_pci_memory(adapter, card->cmd_buf, | |
1544 | PCI_DMA_TODEVICE); | |
1545 | card->cmd_buf = NULL; | |
1546 | } | |
1547 | ||
fc331460 AP |
1548 | pkt_len = *((__le16 *)skb->data); |
1549 | rx_len = le16_to_cpu(pkt_len); | |
1550 | skb_trim(skb, rx_len); | |
1551 | skb_pull(skb, INTF_HEADER_LEN); | |
1552 | ||
d930faee | 1553 | if (!adapter->curr_cmd) { |
d930faee | 1554 | if (adapter->ps_state == PS_STATE_SLEEP_CFM) { |
f57c1edc YAP |
1555 | mwifiex_process_sleep_confirm_resp(adapter, skb->data, |
1556 | skb->len); | |
1c97560f AK |
1557 | mwifiex_pcie_enable_host_int(adapter); |
1558 | if (mwifiex_write_reg(adapter, | |
1559 | PCIE_CPU_INT_EVENT, | |
1560 | CPU_INTR_SLEEP_CFM_DONE)) { | |
1561 | dev_warn(adapter->dev, | |
1562 | "Write register failed\n"); | |
1563 | return -1; | |
1564 | } | |
c4bc980f AP |
1565 | mwifiex_delay_for_sleep_cookie(adapter, |
1566 | MWIFIEX_MAX_DELAY_COUNT); | |
52301a81 AP |
1567 | while (reg->sleep_cookie && (count++ < 10) && |
1568 | mwifiex_pcie_ok_to_access_hw(adapter)) | |
e7891ba2 | 1569 | usleep_range(50, 60); |
d930faee | 1570 | } else { |
f57c1edc YAP |
1571 | dev_err(adapter->dev, |
1572 | "There is no command but got cmdrsp\n"); | |
d930faee | 1573 | } |
f57c1edc YAP |
1574 | memcpy(adapter->upld_buf, skb->data, |
1575 | min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); | |
0f49d64c | 1576 | skb_push(skb, INTF_HEADER_LEN); |
fc331460 AP |
1577 | if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, |
1578 | PCI_DMA_FROMDEVICE)) | |
1579 | return -1; | |
d930faee | 1580 | } else if (mwifiex_pcie_ok_to_access_hw(adapter)) { |
f57c1edc | 1581 | adapter->curr_cmd->resp_skb = skb; |
d930faee AK |
1582 | adapter->cmd_resp_received = true; |
1583 | /* Take the pointer and set it to CMD node and will | |
1584 | return in the response complete callback */ | |
1585 | card->cmdrsp_buf = NULL; | |
1586 | ||
1587 | /* Clear the cmd-rsp buffer address in scratch registers. This | |
1588 | will prevent firmware from writing to the same response | |
1589 | buffer again. */ | |
dd04e6ac | 1590 | if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) { |
f57c1edc YAP |
1591 | dev_err(adapter->dev, |
1592 | "cmd_done: failed to clear cmd_rsp_addr_lo\n"); | |
d930faee AK |
1593 | return -1; |
1594 | } | |
1595 | /* Write the upper 32bits of the cmdrsp buffer physical | |
1596 | address */ | |
dd04e6ac | 1597 | if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) { |
f57c1edc YAP |
1598 | dev_err(adapter->dev, |
1599 | "cmd_done: failed to clear cmd_rsp_addr_hi\n"); | |
d930faee AK |
1600 | return -1; |
1601 | } | |
1602 | } | |
1603 | ||
1604 | return 0; | |
1605 | } | |
1606 | ||
1607 | /* | |
1608 | * Command Response processing complete handler | |
1609 | */ | |
1610 | static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter, | |
1611 | struct sk_buff *skb) | |
1612 | { | |
1613 | struct pcie_service_card *card = adapter->card; | |
1614 | ||
1615 | if (skb) { | |
1616 | card->cmdrsp_buf = skb; | |
1617 | skb_push(card->cmdrsp_buf, INTF_HEADER_LEN); | |
fc331460 AP |
1618 | if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, |
1619 | PCI_DMA_FROMDEVICE)) | |
1620 | return -1; | |
1621 | } | |
1622 | ||
d930faee AK |
1623 | return 0; |
1624 | } | |
1625 | ||
1626 | /* | |
1627 | * This function handles firmware event ready interrupt | |
1628 | */ | |
1629 | static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) | |
1630 | { | |
1631 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1632 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
1633 | u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; |
1634 | u32 wrptr, event; | |
e05dc3e9 | 1635 | struct mwifiex_evt_buf_desc *desc; |
fc331460 AP |
1636 | |
1637 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) | |
1638 | mwifiex_pm_wakeup_card(adapter); | |
d930faee AK |
1639 | |
1640 | if (adapter->event_received) { | |
f57c1edc YAP |
1641 | dev_dbg(adapter->dev, "info: Event being processed, " |
1642 | "do not process this interrupt just yet\n"); | |
d930faee AK |
1643 | return 0; |
1644 | } | |
1645 | ||
1646 | if (rdptr >= MWIFIEX_MAX_EVT_BD) { | |
1647 | dev_dbg(adapter->dev, "info: Invalid read pointer...\n"); | |
1648 | return -1; | |
1649 | } | |
1650 | ||
1651 | /* Read the event ring write pointer set by firmware */ | |
dd04e6ac | 1652 | if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { |
f57c1edc | 1653 | dev_err(adapter->dev, |
dd04e6ac | 1654 | "EventReady: failed to read reg->evt_wrptr\n"); |
d930faee AK |
1655 | return -1; |
1656 | } | |
1657 | ||
1658 | dev_dbg(adapter->dev, "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>", | |
f57c1edc YAP |
1659 | card->evtbd_rdptr, wrptr); |
1660 | if (((wrptr & MWIFIEX_EVTBD_MASK) != (card->evtbd_rdptr | |
1661 | & MWIFIEX_EVTBD_MASK)) || | |
dd04e6ac AP |
1662 | ((wrptr & reg->evt_rollover_ind) == |
1663 | (card->evtbd_rdptr & reg->evt_rollover_ind))) { | |
d930faee AK |
1664 | struct sk_buff *skb_cmd; |
1665 | __le16 data_len = 0; | |
1666 | u16 evt_len; | |
1667 | ||
1668 | dev_dbg(adapter->dev, "info: Read Index: %d\n", rdptr); | |
1669 | skb_cmd = card->evt_buf_list[rdptr]; | |
dbccc92b | 1670 | mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE); |
fc331460 | 1671 | |
d930faee AK |
1672 | /* Take the pointer and set it to event pointer in adapter |
1673 | and will return back after event handling callback */ | |
1674 | card->evt_buf_list[rdptr] = NULL; | |
e05dc3e9 AP |
1675 | desc = card->evtbd_ring[rdptr]; |
1676 | memset(desc, 0, sizeof(*desc)); | |
d930faee AK |
1677 | |
1678 | event = *(u32 *) &skb_cmd->data[INTF_HEADER_LEN]; | |
1679 | adapter->event_cause = event; | |
1680 | /* The first 4bytes will be the event transfer header | |
1681 | len is 2 bytes followed by type which is 2 bytes */ | |
1682 | memcpy(&data_len, skb_cmd->data, sizeof(__le16)); | |
1683 | evt_len = le16_to_cpu(data_len); | |
1684 | ||
1685 | skb_pull(skb_cmd, INTF_HEADER_LEN); | |
1686 | dev_dbg(adapter->dev, "info: Event length: %d\n", evt_len); | |
1687 | ||
1688 | if ((evt_len > 0) && (evt_len < MAX_EVENT_SIZE)) | |
1689 | memcpy(adapter->event_body, skb_cmd->data + | |
1690 | MWIFIEX_EVENT_HEADER_LEN, evt_len - | |
1691 | MWIFIEX_EVENT_HEADER_LEN); | |
1692 | ||
1693 | adapter->event_received = true; | |
1694 | adapter->event_skb = skb_cmd; | |
1695 | ||
1696 | /* Do not update the event read pointer here, wait till the | |
1697 | buffer is released. This is just to make things simpler, | |
1698 | we need to find a better method of managing these buffers. | |
1699 | */ | |
1700 | } | |
1701 | ||
1702 | return 0; | |
1703 | } | |
1704 | ||
1705 | /* | |
1706 | * Event processing complete handler | |
1707 | */ | |
1708 | static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter, | |
1709 | struct sk_buff *skb) | |
1710 | { | |
1711 | struct pcie_service_card *card = adapter->card; | |
dd04e6ac | 1712 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
1713 | int ret = 0; |
1714 | u32 rdptr = card->evtbd_rdptr & MWIFIEX_EVTBD_MASK; | |
1715 | u32 wrptr; | |
e05dc3e9 | 1716 | struct mwifiex_evt_buf_desc *desc; |
d930faee AK |
1717 | |
1718 | if (!skb) | |
1719 | return 0; | |
1720 | ||
1eb54c8a | 1721 | if (rdptr >= MWIFIEX_MAX_EVT_BD) { |
d930faee | 1722 | dev_err(adapter->dev, "event_complete: Invalid rdptr 0x%x\n", |
f57c1edc | 1723 | rdptr); |
8c53e42d | 1724 | return -EINVAL; |
1eb54c8a | 1725 | } |
d930faee AK |
1726 | |
1727 | /* Read the event ring write pointer set by firmware */ | |
dd04e6ac | 1728 | if (mwifiex_read_reg(adapter, reg->evt_wrptr, &wrptr)) { |
f57c1edc | 1729 | dev_err(adapter->dev, |
dd04e6ac | 1730 | "event_complete: failed to read reg->evt_wrptr\n"); |
8c53e42d | 1731 | return -1; |
d930faee AK |
1732 | } |
1733 | ||
1734 | if (!card->evt_buf_list[rdptr]) { | |
1735 | skb_push(skb, INTF_HEADER_LEN); | |
fc331460 AP |
1736 | if (mwifiex_map_pci_memory(adapter, skb, |
1737 | MAX_EVENT_SIZE, | |
1738 | PCI_DMA_FROMDEVICE)) | |
1739 | return -1; | |
d930faee | 1740 | card->evt_buf_list[rdptr] = skb; |
e05dc3e9 | 1741 | desc = card->evtbd_ring[rdptr]; |
dbccc92b | 1742 | desc->paddr = MWIFIEX_SKB_DMA_ADDR(skb); |
e05dc3e9 AP |
1743 | desc->len = (u16)skb->len; |
1744 | desc->flags = 0; | |
d930faee AK |
1745 | skb = NULL; |
1746 | } else { | |
f57c1edc YAP |
1747 | dev_dbg(adapter->dev, |
1748 | "info: ERROR: buf still valid at index %d, <%p, %p>\n", | |
1749 | rdptr, card->evt_buf_list[rdptr], skb); | |
d930faee AK |
1750 | } |
1751 | ||
1752 | if ((++card->evtbd_rdptr & MWIFIEX_EVTBD_MASK) == MWIFIEX_MAX_EVT_BD) { | |
1753 | card->evtbd_rdptr = ((card->evtbd_rdptr & | |
dd04e6ac AP |
1754 | reg->evt_rollover_ind) ^ |
1755 | reg->evt_rollover_ind); | |
d930faee AK |
1756 | } |
1757 | ||
1758 | dev_dbg(adapter->dev, "info: Updated <Rd: 0x%x, Wr: 0x%x>", | |
f57c1edc | 1759 | card->evtbd_rdptr, wrptr); |
d930faee | 1760 | |
dd04e6ac AP |
1761 | /* Write the event ring read pointer in to reg->evt_rdptr */ |
1762 | if (mwifiex_write_reg(adapter, reg->evt_rdptr, | |
1763 | card->evtbd_rdptr)) { | |
f57c1edc | 1764 | dev_err(adapter->dev, |
dd04e6ac | 1765 | "event_complete: failed to read reg->evt_rdptr\n"); |
8c53e42d | 1766 | return -1; |
d930faee AK |
1767 | } |
1768 | ||
d930faee AK |
1769 | dev_dbg(adapter->dev, "info: Check Events Again\n"); |
1770 | ret = mwifiex_pcie_process_event_ready(adapter); | |
1771 | ||
1772 | return ret; | |
1773 | } | |
1774 | ||
1775 | /* | |
1776 | * This function downloads the firmware to the card. | |
1777 | * | |
1778 | * Firmware is downloaded to the card in blocks. Every block download | |
1779 | * is tested for CRC errors, and retried a number of times before | |
1780 | * returning failure. | |
1781 | */ | |
1782 | static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, | |
1783 | struct mwifiex_fw_image *fw) | |
1784 | { | |
1785 | int ret; | |
1786 | u8 *firmware = fw->fw_buf; | |
1787 | u32 firmware_len = fw->fw_len; | |
1788 | u32 offset = 0; | |
1789 | struct sk_buff *skb; | |
1790 | u32 txlen, tx_blocks = 0, tries, len; | |
1791 | u32 block_retry_cnt = 0; | |
fc331460 | 1792 | struct pcie_service_card *card = adapter->card; |
dd04e6ac | 1793 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
1794 | |
1795 | if (!firmware || !firmware_len) { | |
f57c1edc YAP |
1796 | dev_err(adapter->dev, |
1797 | "No firmware image found! Terminating download\n"); | |
d930faee AK |
1798 | return -1; |
1799 | } | |
1800 | ||
1801 | dev_dbg(adapter->dev, "info: Downloading FW image (%d bytes)\n", | |
f57c1edc | 1802 | firmware_len); |
d930faee AK |
1803 | |
1804 | if (mwifiex_pcie_disable_host_int(adapter)) { | |
f57c1edc YAP |
1805 | dev_err(adapter->dev, |
1806 | "%s: Disabling interrupts failed.\n", __func__); | |
d930faee AK |
1807 | return -1; |
1808 | } | |
1809 | ||
1810 | skb = dev_alloc_skb(MWIFIEX_UPLD_SIZE); | |
1811 | if (!skb) { | |
1812 | ret = -ENOMEM; | |
1813 | goto done; | |
1814 | } | |
d930faee AK |
1815 | |
1816 | /* Perform firmware data transfer */ | |
1817 | do { | |
1818 | u32 ireg_intr = 0; | |
1819 | ||
1820 | /* More data? */ | |
1821 | if (offset >= firmware_len) | |
1822 | break; | |
1823 | ||
1824 | for (tries = 0; tries < MAX_POLL_TRIES; tries++) { | |
dd04e6ac | 1825 | ret = mwifiex_read_reg(adapter, reg->cmd_size, |
d930faee AK |
1826 | &len); |
1827 | if (ret) { | |
f57c1edc YAP |
1828 | dev_warn(adapter->dev, |
1829 | "Failed reading len from boot code\n"); | |
d930faee AK |
1830 | goto done; |
1831 | } | |
1832 | if (len) | |
1833 | break; | |
e7891ba2 | 1834 | usleep_range(10, 20); |
d930faee AK |
1835 | } |
1836 | ||
1837 | if (!len) { | |
1838 | break; | |
1839 | } else if (len > MWIFIEX_UPLD_SIZE) { | |
1840 | pr_err("FW download failure @ %d, invalid length %d\n", | |
f57c1edc | 1841 | offset, len); |
d930faee AK |
1842 | ret = -1; |
1843 | goto done; | |
1844 | } | |
1845 | ||
1846 | txlen = len; | |
1847 | ||
1848 | if (len & BIT(0)) { | |
1849 | block_retry_cnt++; | |
1850 | if (block_retry_cnt > MAX_WRITE_IOMEM_RETRY) { | |
1851 | pr_err("FW download failure @ %d, over max " | |
1852 | "retry count\n", offset); | |
1853 | ret = -1; | |
1854 | goto done; | |
1855 | } | |
1856 | dev_err(adapter->dev, "FW CRC error indicated by the " | |
f57c1edc YAP |
1857 | "helper: len = 0x%04X, txlen = %d\n", |
1858 | len, txlen); | |
d930faee AK |
1859 | len &= ~BIT(0); |
1860 | /* Setting this to 0 to resend from same offset */ | |
1861 | txlen = 0; | |
1862 | } else { | |
1863 | block_retry_cnt = 0; | |
1864 | /* Set blocksize to transfer - checking for | |
1865 | last block */ | |
1866 | if (firmware_len - offset < txlen) | |
1867 | txlen = firmware_len - offset; | |
1868 | ||
1869 | dev_dbg(adapter->dev, "."); | |
1870 | ||
dd04e6ac AP |
1871 | tx_blocks = (txlen + card->pcie.blksz_fw_dl - 1) / |
1872 | card->pcie.blksz_fw_dl; | |
d930faee AK |
1873 | |
1874 | /* Copy payload to buffer */ | |
1875 | memmove(skb->data, &firmware[offset], txlen); | |
1876 | } | |
1877 | ||
1878 | skb_put(skb, MWIFIEX_UPLD_SIZE - skb->len); | |
dd04e6ac | 1879 | skb_trim(skb, tx_blocks * card->pcie.blksz_fw_dl); |
d930faee AK |
1880 | |
1881 | /* Send the boot command to device */ | |
1882 | if (mwifiex_pcie_send_boot_cmd(adapter, skb)) { | |
f57c1edc YAP |
1883 | dev_err(adapter->dev, |
1884 | "Failed to send firmware download command\n"); | |
d930faee AK |
1885 | ret = -1; |
1886 | goto done; | |
1887 | } | |
fc331460 | 1888 | |
d930faee AK |
1889 | /* Wait for the command done interrupt */ |
1890 | do { | |
1891 | if (mwifiex_read_reg(adapter, PCIE_CPU_INT_STATUS, | |
1892 | &ireg_intr)) { | |
1893 | dev_err(adapter->dev, "%s: Failed to read " | |
f57c1edc YAP |
1894 | "interrupt status during fw dnld.\n", |
1895 | __func__); | |
dbccc92b AD |
1896 | mwifiex_unmap_pci_memory(adapter, skb, |
1897 | PCI_DMA_TODEVICE); | |
d930faee AK |
1898 | ret = -1; |
1899 | goto done; | |
1900 | } | |
1901 | } while ((ireg_intr & CPU_INTR_DOOR_BELL) == | |
1902 | CPU_INTR_DOOR_BELL); | |
fc331460 | 1903 | |
dbccc92b | 1904 | mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); |
fc331460 | 1905 | |
d930faee AK |
1906 | offset += txlen; |
1907 | } while (true); | |
1908 | ||
1909 | dev_dbg(adapter->dev, "info:\nFW download over, size %d bytes\n", | |
f57c1edc | 1910 | offset); |
d930faee AK |
1911 | |
1912 | ret = 0; | |
1913 | ||
1914 | done: | |
1915 | dev_kfree_skb_any(skb); | |
1916 | return ret; | |
1917 | } | |
1918 | ||
1919 | /* | |
1920 | * This function checks the firmware status in card. | |
1921 | * | |
1922 | * The winner interface is also determined by this function. | |
1923 | */ | |
1924 | static int | |
1925 | mwifiex_check_fw_status(struct mwifiex_adapter *adapter, u32 poll_num) | |
1926 | { | |
1927 | int ret = 0; | |
1928 | u32 firmware_stat, winner_status; | |
dd04e6ac AP |
1929 | struct pcie_service_card *card = adapter->card; |
1930 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; | |
d930faee AK |
1931 | u32 tries; |
1932 | ||
1933 | /* Mask spurios interrupts */ | |
1934 | if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS_MASK, | |
f57c1edc | 1935 | HOST_INTR_MASK)) { |
d930faee AK |
1936 | dev_warn(adapter->dev, "Write register failed\n"); |
1937 | return -1; | |
1938 | } | |
1939 | ||
1940 | dev_dbg(adapter->dev, "Setting driver ready signature\n"); | |
dd04e6ac AP |
1941 | if (mwifiex_write_reg(adapter, reg->drv_rdy, |
1942 | FIRMWARE_READY_PCIE)) { | |
f57c1edc YAP |
1943 | dev_err(adapter->dev, |
1944 | "Failed to write driver ready signature\n"); | |
d930faee AK |
1945 | return -1; |
1946 | } | |
1947 | ||
1948 | /* Wait for firmware initialization event */ | |
1949 | for (tries = 0; tries < poll_num; tries++) { | |
dd04e6ac | 1950 | if (mwifiex_read_reg(adapter, reg->fw_status, |
d930faee AK |
1951 | &firmware_stat)) |
1952 | ret = -1; | |
1953 | else | |
1954 | ret = 0; | |
1955 | if (ret) | |
1956 | continue; | |
1957 | if (firmware_stat == FIRMWARE_READY_PCIE) { | |
1958 | ret = 0; | |
1959 | break; | |
1960 | } else { | |
a76b20e5 | 1961 | msleep(100); |
d930faee AK |
1962 | ret = -1; |
1963 | } | |
1964 | } | |
1965 | ||
1966 | if (ret) { | |
dd04e6ac | 1967 | if (mwifiex_read_reg(adapter, reg->fw_status, |
d930faee AK |
1968 | &winner_status)) |
1969 | ret = -1; | |
1970 | else if (!winner_status) { | |
1971 | dev_err(adapter->dev, "PCI-E is the winner\n"); | |
1972 | adapter->winner = 1; | |
d930faee | 1973 | } else { |
f57c1edc YAP |
1974 | dev_err(adapter->dev, |
1975 | "PCI-E is not the winner <%#x,%d>, exit dnld\n", | |
1976 | ret, adapter->winner); | |
d930faee AK |
1977 | } |
1978 | } | |
1979 | ||
1980 | return ret; | |
1981 | } | |
1982 | ||
1983 | /* | |
1984 | * This function reads the interrupt status from card. | |
1985 | */ | |
1986 | static void mwifiex_interrupt_status(struct mwifiex_adapter *adapter) | |
1987 | { | |
1988 | u32 pcie_ireg; | |
1989 | unsigned long flags; | |
1990 | ||
1991 | if (!mwifiex_pcie_ok_to_access_hw(adapter)) | |
1992 | return; | |
1993 | ||
1994 | if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, &pcie_ireg)) { | |
1995 | dev_warn(adapter->dev, "Read register failed\n"); | |
1996 | return; | |
1997 | } | |
1998 | ||
1999 | if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { | |
2000 | ||
2001 | mwifiex_pcie_disable_host_int(adapter); | |
2002 | ||
2003 | /* Clear the pending interrupts */ | |
2004 | if (mwifiex_write_reg(adapter, PCIE_HOST_INT_STATUS, | |
2005 | ~pcie_ireg)) { | |
2006 | dev_warn(adapter->dev, "Write register failed\n"); | |
2007 | return; | |
2008 | } | |
2009 | spin_lock_irqsave(&adapter->int_lock, flags); | |
2010 | adapter->int_status |= pcie_ireg; | |
2011 | spin_unlock_irqrestore(&adapter->int_lock, flags); | |
2012 | ||
1c97560f AK |
2013 | if (!adapter->pps_uapsd_mode && |
2014 | adapter->ps_state == PS_STATE_SLEEP && | |
2015 | mwifiex_pcie_ok_to_access_hw(adapter)) { | |
d930faee AK |
2016 | /* Potentially for PCIe we could get other |
2017 | * interrupts like shared. Don't change power | |
2018 | * state until cookie is set */ | |
c24d992a AP |
2019 | adapter->ps_state = PS_STATE_AWAKE; |
2020 | adapter->pm_wakeup_fw_try = false; | |
d930faee AK |
2021 | } |
2022 | } | |
2023 | } | |
2024 | ||
2025 | /* | |
2026 | * Interrupt handler for PCIe root port | |
2027 | * | |
2028 | * This function reads the interrupt status from firmware and assigns | |
2029 | * the main process in workqueue which will handle the interrupt. | |
2030 | */ | |
2031 | static irqreturn_t mwifiex_pcie_interrupt(int irq, void *context) | |
2032 | { | |
2033 | struct pci_dev *pdev = (struct pci_dev *)context; | |
2034 | struct pcie_service_card *card; | |
2035 | struct mwifiex_adapter *adapter; | |
2036 | ||
2037 | if (!pdev) { | |
2038 | pr_debug("info: %s: pdev is NULL\n", (u8 *)pdev); | |
2039 | goto exit; | |
2040 | } | |
2041 | ||
b2a31204 | 2042 | card = pci_get_drvdata(pdev); |
d930faee AK |
2043 | if (!card || !card->adapter) { |
2044 | pr_debug("info: %s: card=%p adapter=%p\n", __func__, card, | |
f57c1edc | 2045 | card ? card->adapter : NULL); |
d930faee AK |
2046 | goto exit; |
2047 | } | |
2048 | adapter = card->adapter; | |
2049 | ||
2050 | if (adapter->surprise_removed) | |
2051 | goto exit; | |
2052 | ||
2053 | mwifiex_interrupt_status(adapter); | |
2054 | queue_work(adapter->workqueue, &adapter->main_work); | |
2055 | ||
2056 | exit: | |
2057 | return IRQ_HANDLED; | |
2058 | } | |
2059 | ||
2060 | /* | |
2061 | * This function checks the current interrupt status. | |
2062 | * | |
2063 | * The following interrupts are checked and handled by this function - | |
2064 | * - Data sent | |
2065 | * - Command sent | |
2066 | * - Command received | |
2067 | * - Packets received | |
2068 | * - Events received | |
2069 | * | |
2070 | * In case of Rx packets received, the packets are uploaded from card to | |
2071 | * host and processed accordingly. | |
2072 | */ | |
2073 | static int mwifiex_process_int_status(struct mwifiex_adapter *adapter) | |
2074 | { | |
2075 | int ret; | |
659c4788 | 2076 | u32 pcie_ireg; |
d930faee AK |
2077 | unsigned long flags; |
2078 | ||
2079 | spin_lock_irqsave(&adapter->int_lock, flags); | |
2080 | /* Clear out unused interrupts */ | |
659c4788 AP |
2081 | pcie_ireg = adapter->int_status; |
2082 | adapter->int_status = 0; | |
d930faee AK |
2083 | spin_unlock_irqrestore(&adapter->int_lock, flags); |
2084 | ||
659c4788 AP |
2085 | while (pcie_ireg & HOST_INTR_MASK) { |
2086 | if (pcie_ireg & HOST_INTR_DNLD_DONE) { | |
2087 | pcie_ireg &= ~HOST_INTR_DNLD_DONE; | |
e7f767a7 AP |
2088 | dev_dbg(adapter->dev, "info: TX DNLD Done\n"); |
2089 | ret = mwifiex_pcie_send_data_complete(adapter); | |
2090 | if (ret) | |
2091 | return ret; | |
d930faee | 2092 | } |
659c4788 AP |
2093 | if (pcie_ireg & HOST_INTR_UPLD_RDY) { |
2094 | pcie_ireg &= ~HOST_INTR_UPLD_RDY; | |
d930faee AK |
2095 | dev_dbg(adapter->dev, "info: Rx DATA\n"); |
2096 | ret = mwifiex_pcie_process_recv_data(adapter); | |
2097 | if (ret) | |
2098 | return ret; | |
2099 | } | |
659c4788 AP |
2100 | if (pcie_ireg & HOST_INTR_EVENT_RDY) { |
2101 | pcie_ireg &= ~HOST_INTR_EVENT_RDY; | |
d930faee AK |
2102 | dev_dbg(adapter->dev, "info: Rx EVENT\n"); |
2103 | ret = mwifiex_pcie_process_event_ready(adapter); | |
2104 | if (ret) | |
2105 | return ret; | |
2106 | } | |
2107 | ||
659c4788 AP |
2108 | if (pcie_ireg & HOST_INTR_CMD_DONE) { |
2109 | pcie_ireg &= ~HOST_INTR_CMD_DONE; | |
d930faee | 2110 | if (adapter->cmd_sent) { |
f57c1edc YAP |
2111 | dev_dbg(adapter->dev, |
2112 | "info: CMD sent Interrupt\n"); | |
d930faee AK |
2113 | adapter->cmd_sent = false; |
2114 | } | |
2115 | /* Handle command response */ | |
2116 | ret = mwifiex_pcie_process_cmd_complete(adapter); | |
2117 | if (ret) | |
2118 | return ret; | |
2119 | } | |
2120 | ||
2121 | if (mwifiex_pcie_ok_to_access_hw(adapter)) { | |
2122 | if (mwifiex_read_reg(adapter, PCIE_HOST_INT_STATUS, | |
2123 | &pcie_ireg)) { | |
f57c1edc YAP |
2124 | dev_warn(adapter->dev, |
2125 | "Read register failed\n"); | |
d930faee AK |
2126 | return -1; |
2127 | } | |
2128 | ||
2129 | if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { | |
2130 | if (mwifiex_write_reg(adapter, | |
f57c1edc YAP |
2131 | PCIE_HOST_INT_STATUS, |
2132 | ~pcie_ireg)) { | |
2133 | dev_warn(adapter->dev, | |
2134 | "Write register failed\n"); | |
d930faee AK |
2135 | return -1; |
2136 | } | |
d930faee AK |
2137 | } |
2138 | ||
2139 | } | |
2140 | } | |
2141 | dev_dbg(adapter->dev, "info: cmd_sent=%d data_sent=%d\n", | |
f57c1edc | 2142 | adapter->cmd_sent, adapter->data_sent); |
b2fda1f6 AP |
2143 | if (adapter->ps_state != PS_STATE_SLEEP) |
2144 | mwifiex_pcie_enable_host_int(adapter); | |
d930faee AK |
2145 | |
2146 | return 0; | |
2147 | } | |
2148 | ||
2149 | /* | |
2150 | * This function downloads data from driver to card. | |
2151 | * | |
2152 | * Both commands and data packets are transferred to the card by this | |
2153 | * function. | |
2154 | * | |
2155 | * This function adds the PCIE specific header to the front of the buffer | |
2156 | * before transferring. The header contains the length of the packet and | |
2157 | * the type. The firmware handles the packets based upon this set type. | |
2158 | */ | |
2159 | static int mwifiex_pcie_host_to_card(struct mwifiex_adapter *adapter, u8 type, | |
2160 | struct sk_buff *skb, | |
2161 | struct mwifiex_tx_param *tx_param) | |
2162 | { | |
fa161cb7 DC |
2163 | if (!skb) { |
2164 | dev_err(adapter->dev, "Passed NULL skb to %s\n", __func__); | |
d930faee AK |
2165 | return -1; |
2166 | } | |
2167 | ||
2168 | if (type == MWIFIEX_TYPE_DATA) | |
e7f767a7 | 2169 | return mwifiex_pcie_send_data(adapter, skb, tx_param); |
d930faee AK |
2170 | else if (type == MWIFIEX_TYPE_CMD) |
2171 | return mwifiex_pcie_send_cmd(adapter, skb); | |
2172 | ||
2173 | return 0; | |
2174 | } | |
2175 | ||
2176 | /* | |
2177 | * This function initializes the PCI-E host memory space, WCB rings, etc. | |
2178 | * | |
2179 | * The following initializations steps are followed - | |
2180 | * - Allocate TXBD ring buffers | |
2181 | * - Allocate RXBD ring buffers | |
2182 | * - Allocate event BD ring buffers | |
2183 | * - Allocate command response ring buffer | |
2184 | * - Allocate sleep cookie buffer | |
2185 | */ | |
2186 | static int mwifiex_pcie_init(struct mwifiex_adapter *adapter) | |
2187 | { | |
2188 | struct pcie_service_card *card = adapter->card; | |
2189 | int ret; | |
2190 | struct pci_dev *pdev = card->dev; | |
52301a81 | 2191 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee AK |
2192 | |
2193 | pci_set_drvdata(pdev, card); | |
2194 | ||
2195 | ret = pci_enable_device(pdev); | |
2196 | if (ret) | |
2197 | goto err_enable_dev; | |
2198 | ||
2199 | pci_set_master(pdev); | |
2200 | ||
2201 | dev_dbg(adapter->dev, "try set_consistent_dma_mask(32)\n"); | |
2202 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2203 | if (ret) { | |
2204 | dev_err(adapter->dev, "set_dma_mask(32) failed\n"); | |
2205 | goto err_set_dma_mask; | |
2206 | } | |
2207 | ||
2208 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2209 | if (ret) { | |
2210 | dev_err(adapter->dev, "set_consistent_dma_mask(64) failed\n"); | |
2211 | goto err_set_dma_mask; | |
2212 | } | |
2213 | ||
2214 | ret = pci_request_region(pdev, 0, DRV_NAME); | |
2215 | if (ret) { | |
2216 | dev_err(adapter->dev, "req_reg(0) error\n"); | |
2217 | goto err_req_region0; | |
2218 | } | |
2219 | card->pci_mmap = pci_iomap(pdev, 0, 0); | |
2220 | if (!card->pci_mmap) { | |
2221 | dev_err(adapter->dev, "iomap(0) error\n"); | |
3220712d | 2222 | ret = -EIO; |
d930faee AK |
2223 | goto err_iomap0; |
2224 | } | |
2225 | ret = pci_request_region(pdev, 2, DRV_NAME); | |
2226 | if (ret) { | |
2227 | dev_err(adapter->dev, "req_reg(2) error\n"); | |
2228 | goto err_req_region2; | |
2229 | } | |
2230 | card->pci_mmap1 = pci_iomap(pdev, 2, 0); | |
2231 | if (!card->pci_mmap1) { | |
2232 | dev_err(adapter->dev, "iomap(2) error\n"); | |
3220712d | 2233 | ret = -EIO; |
d930faee AK |
2234 | goto err_iomap2; |
2235 | } | |
2236 | ||
f57c1edc YAP |
2237 | dev_dbg(adapter->dev, |
2238 | "PCI memory map Virt0: %p PCI memory map Virt2: %p\n", | |
2239 | card->pci_mmap, card->pci_mmap1); | |
d930faee AK |
2240 | |
2241 | card->cmdrsp_buf = NULL; | |
2242 | ret = mwifiex_pcie_create_txbd_ring(adapter); | |
2243 | if (ret) | |
2244 | goto err_cre_txbd; | |
2245 | ret = mwifiex_pcie_create_rxbd_ring(adapter); | |
2246 | if (ret) | |
2247 | goto err_cre_rxbd; | |
2248 | ret = mwifiex_pcie_create_evtbd_ring(adapter); | |
2249 | if (ret) | |
2250 | goto err_cre_evtbd; | |
2251 | ret = mwifiex_pcie_alloc_cmdrsp_buf(adapter); | |
2252 | if (ret) | |
2253 | goto err_alloc_cmdbuf; | |
52301a81 AP |
2254 | if (reg->sleep_cookie) { |
2255 | ret = mwifiex_pcie_alloc_sleep_cookie_buf(adapter); | |
2256 | if (ret) | |
2257 | goto err_alloc_cookie; | |
2258 | } else { | |
2259 | card->sleep_cookie_vbase = NULL; | |
2260 | } | |
d930faee AK |
2261 | return ret; |
2262 | ||
2263 | err_alloc_cookie: | |
2264 | mwifiex_pcie_delete_cmdrsp_buf(adapter); | |
2265 | err_alloc_cmdbuf: | |
2266 | mwifiex_pcie_delete_evtbd_ring(adapter); | |
2267 | err_cre_evtbd: | |
2268 | mwifiex_pcie_delete_rxbd_ring(adapter); | |
2269 | err_cre_rxbd: | |
2270 | mwifiex_pcie_delete_txbd_ring(adapter); | |
2271 | err_cre_txbd: | |
2272 | pci_iounmap(pdev, card->pci_mmap1); | |
2273 | err_iomap2: | |
2274 | pci_release_region(pdev, 2); | |
2275 | err_req_region2: | |
2276 | pci_iounmap(pdev, card->pci_mmap); | |
2277 | err_iomap0: | |
2278 | pci_release_region(pdev, 0); | |
2279 | err_req_region0: | |
2280 | err_set_dma_mask: | |
2281 | pci_disable_device(pdev); | |
2282 | err_enable_dev: | |
2283 | pci_set_drvdata(pdev, NULL); | |
2284 | return ret; | |
2285 | } | |
2286 | ||
2287 | /* | |
2288 | * This function cleans up the allocated card buffers. | |
2289 | * | |
2290 | * The following are freed by this function - | |
2291 | * - TXBD ring buffers | |
2292 | * - RXBD ring buffers | |
2293 | * - Event BD ring buffers | |
2294 | * - Command response ring buffer | |
2295 | * - Sleep cookie buffer | |
2296 | */ | |
2297 | static void mwifiex_pcie_cleanup(struct mwifiex_adapter *adapter) | |
2298 | { | |
2299 | struct pcie_service_card *card = adapter->card; | |
2300 | struct pci_dev *pdev = card->dev; | |
dd04e6ac | 2301 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
d930faee | 2302 | |
d930faee | 2303 | if (user_rmmod) { |
fc331460 | 2304 | dev_dbg(adapter->dev, "Clearing driver ready signature\n"); |
dd04e6ac | 2305 | if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) |
f57c1edc YAP |
2306 | dev_err(adapter->dev, |
2307 | "Failed to write driver not-ready signature\n"); | |
d930faee AK |
2308 | } |
2309 | ||
2310 | if (pdev) { | |
2311 | pci_iounmap(pdev, card->pci_mmap); | |
2312 | pci_iounmap(pdev, card->pci_mmap1); | |
5b0d9b21 | 2313 | pci_disable_device(pdev); |
c380aafb YAP |
2314 | pci_release_region(pdev, 2); |
2315 | pci_release_region(pdev, 0); | |
d930faee AK |
2316 | pci_set_drvdata(pdev, NULL); |
2317 | } | |
3c59e328 | 2318 | kfree(card); |
d930faee AK |
2319 | } |
2320 | ||
2321 | /* | |
2322 | * This function registers the PCIE device. | |
2323 | * | |
2324 | * PCIE IRQ is claimed, block size is set and driver data is initialized. | |
2325 | */ | |
2326 | static int mwifiex_register_dev(struct mwifiex_adapter *adapter) | |
2327 | { | |
2328 | int ret; | |
2329 | struct pcie_service_card *card = adapter->card; | |
2330 | struct pci_dev *pdev = card->dev; | |
2331 | ||
2332 | /* save adapter pointer in card */ | |
2333 | card->adapter = adapter; | |
2334 | ||
2335 | ret = request_irq(pdev->irq, mwifiex_pcie_interrupt, IRQF_SHARED, | |
2336 | "MRVL_PCIE", pdev); | |
2337 | if (ret) { | |
2338 | pr_err("request_irq failed: ret=%d\n", ret); | |
2339 | adapter->card = NULL; | |
2340 | return -1; | |
2341 | } | |
2342 | ||
2343 | adapter->dev = &pdev->dev; | |
828cf222 | 2344 | adapter->tx_buf_size = card->pcie.tx_buf_size; |
dd04e6ac | 2345 | strcpy(adapter->fw_name, card->pcie.firmware); |
d930faee AK |
2346 | |
2347 | return 0; | |
2348 | } | |
2349 | ||
2350 | /* | |
2351 | * This function unregisters the PCIE device. | |
2352 | * | |
2353 | * The PCIE IRQ is released, the function is disabled and driver | |
2354 | * data is set to null. | |
2355 | */ | |
2356 | static void mwifiex_unregister_dev(struct mwifiex_adapter *adapter) | |
2357 | { | |
2358 | struct pcie_service_card *card = adapter->card; | |
52301a81 | 2359 | const struct mwifiex_pcie_card_reg *reg; |
d930faee AK |
2360 | |
2361 | if (card) { | |
2362 | dev_dbg(adapter->dev, "%s(): calling free_irq()\n", __func__); | |
2363 | free_irq(card->dev->irq, card->dev); | |
fc331460 | 2364 | |
52301a81 AP |
2365 | reg = card->pcie.reg; |
2366 | if (reg->sleep_cookie) | |
2367 | mwifiex_pcie_delete_sleep_cookie_buf(adapter); | |
2368 | ||
fc331460 AP |
2369 | mwifiex_pcie_delete_cmdrsp_buf(adapter); |
2370 | mwifiex_pcie_delete_evtbd_ring(adapter); | |
2371 | mwifiex_pcie_delete_rxbd_ring(adapter); | |
2372 | mwifiex_pcie_delete_txbd_ring(adapter); | |
2373 | card->cmdrsp_buf = NULL; | |
d930faee AK |
2374 | } |
2375 | } | |
2376 | ||
2377 | static struct mwifiex_if_ops pcie_ops = { | |
2378 | .init_if = mwifiex_pcie_init, | |
2379 | .cleanup_if = mwifiex_pcie_cleanup, | |
2380 | .check_fw_status = mwifiex_check_fw_status, | |
2381 | .prog_fw = mwifiex_prog_fw_w_helper, | |
2382 | .register_dev = mwifiex_register_dev, | |
2383 | .unregister_dev = mwifiex_unregister_dev, | |
2384 | .enable_int = mwifiex_pcie_enable_host_int, | |
2385 | .process_int_status = mwifiex_process_int_status, | |
2386 | .host_to_card = mwifiex_pcie_host_to_card, | |
2387 | .wakeup = mwifiex_pm_wakeup_card, | |
2388 | .wakeup_complete = mwifiex_pm_wakeup_card_complete, | |
2389 | ||
2390 | /* PCIE specific */ | |
2391 | .cmdrsp_complete = mwifiex_pcie_cmdrsp_complete, | |
2392 | .event_complete = mwifiex_pcie_event_complete, | |
2393 | .update_mp_end_port = NULL, | |
2394 | .cleanup_mpa_buf = NULL, | |
c6d1d87a | 2395 | .init_fw_port = mwifiex_pcie_init_fw_port, |
fbd7e7ac | 2396 | .clean_pcie_ring = mwifiex_clean_pcie_ring_buf, |
d930faee AK |
2397 | }; |
2398 | ||
2399 | /* | |
2400 | * This function initializes the PCIE driver module. | |
2401 | * | |
2402 | * This initiates the semaphore and registers the device with | |
2403 | * PCIE bus. | |
2404 | */ | |
2405 | static int mwifiex_pcie_init_module(void) | |
2406 | { | |
2407 | int ret; | |
2408 | ||
ca8f2112 | 2409 | pr_debug("Marvell PCIe Driver\n"); |
d930faee AK |
2410 | |
2411 | sema_init(&add_remove_card_sem, 1); | |
2412 | ||
2413 | /* Clear the flag in case user removes the card. */ | |
2414 | user_rmmod = 0; | |
2415 | ||
2416 | ret = pci_register_driver(&mwifiex_pcie); | |
2417 | if (ret) | |
2418 | pr_err("Driver register failed!\n"); | |
2419 | else | |
2420 | pr_debug("info: Driver registered successfully!\n"); | |
2421 | ||
2422 | return ret; | |
2423 | } | |
2424 | ||
2425 | /* | |
2426 | * This function cleans up the PCIE driver. | |
2427 | * | |
2428 | * The following major steps are followed for cleanup - | |
2429 | * - Resume the device if its suspended | |
2430 | * - Disconnect the device if connected | |
2431 | * - Shutdown the firmware | |
2432 | * - Unregister the device from PCIE bus. | |
2433 | */ | |
2434 | static void mwifiex_pcie_cleanup_module(void) | |
2435 | { | |
2436 | if (!down_interruptible(&add_remove_card_sem)) | |
2437 | up(&add_remove_card_sem); | |
2438 | ||
2439 | /* Set the flag as user is removing this module. */ | |
2440 | user_rmmod = 1; | |
2441 | ||
2442 | pci_unregister_driver(&mwifiex_pcie); | |
2443 | } | |
2444 | ||
2445 | module_init(mwifiex_pcie_init_module); | |
2446 | module_exit(mwifiex_pcie_cleanup_module); | |
2447 | ||
2448 | MODULE_AUTHOR("Marvell International Ltd."); | |
2449 | MODULE_DESCRIPTION("Marvell WiFi-Ex PCI-Express Driver version " PCIE_VERSION); | |
2450 | MODULE_VERSION(PCIE_VERSION); | |
2451 | MODULE_LICENSE("GPL v2"); | |
ca8f2112 AP |
2452 | MODULE_FIRMWARE(PCIE8766_DEFAULT_FW_NAME); |
2453 | MODULE_FIRMWARE(PCIE8897_DEFAULT_FW_NAME); |