[deliverable/linux.git] / drivers / net / wireless / mwifiex / pcie.h

/* @file mwifiex_pcie.h
 *
 * @brief This file contains definitions for PCI-E interface.
 * driver.
 *
 * Copyright (C) 2011, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_PCIE_H
#define	_MWIFIEX_PCIE_H

#include    <linux/pci.h>
#include    <linux/pcieport_if.h>
#include    <linux/interrupt.h>

#include    "main.h"

#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"

/* Constants for Buffer Descriptor (BD) rings */
#define MWIFIEX_MAX_TXRX_BD			0x20
#define MWIFIEX_TXBD_MASK			0x3F
#define MWIFIEX_RXBD_MASK			0x3F

#define MWIFIEX_MAX_EVT_BD			0x04
#define MWIFIEX_EVTBD_MASK			0x07

/* PCIE INTERNAL REGISTERS */
#define PCIE_SCRATCH_0_REG				0xC10
#define PCIE_SCRATCH_1_REG				0xC14
#define PCIE_CPU_INT_EVENT				0xC18
#define PCIE_CPU_INT_STATUS				0xC1C
#define PCIE_HOST_INT_STATUS				0xC30
#define PCIE_HOST_INT_MASK				0xC34
#define PCIE_HOST_INT_STATUS_MASK			0xC3C
#define PCIE_SCRATCH_2_REG				0xC40
#define PCIE_SCRATCH_3_REG				0xC44
#define PCIE_SCRATCH_4_REG				0xCD0
#define PCIE_SCRATCH_5_REG				0xCD4
#define PCIE_SCRATCH_6_REG				0xCD8
#define PCIE_SCRATCH_7_REG				0xCDC
#define PCIE_SCRATCH_8_REG				0xCE0
#define PCIE_SCRATCH_9_REG				0xCE4
#define PCIE_SCRATCH_10_REG				0xCE8
#define PCIE_SCRATCH_11_REG				0xCEC
#define PCIE_SCRATCH_12_REG				0xCF0

#define CPU_INTR_DNLD_RDY				BIT(0)
#define CPU_INTR_DOOR_BELL				BIT(1)
#define CPU_INTR_SLEEP_CFM_DONE			BIT(2)
#define CPU_INTR_RESET					BIT(3)

#define HOST_INTR_DNLD_DONE				BIT(0)
#define HOST_INTR_UPLD_RDY				BIT(1)
#define HOST_INTR_CMD_DONE				BIT(2)
#define HOST_INTR_EVENT_RDY				BIT(3)
#define HOST_INTR_MASK					(HOST_INTR_DNLD_DONE | \
							 HOST_INTR_UPLD_RDY  | \
							 HOST_INTR_CMD_DONE  | \
							 HOST_INTR_EVENT_RDY)

#define MWIFIEX_BD_FLAG_ROLLOVER_IND			BIT(7)
#define MWIFIEX_BD_FLAG_FIRST_DESC			BIT(0)
#define MWIFIEX_BD_FLAG_LAST_DESC			BIT(1)

/* Max retry number of command write */
#define MAX_WRITE_IOMEM_RETRY				2
/* Define PCIE block size for firmware download */
#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD		256
/* FW awake cookie after FW ready */
#define FW_AWAKE_COOKIE						(0xAA55AA55)

struct mwifiex_pcie_card_reg {
	u16 cmd_addr_lo;
	u16 cmd_addr_hi;
	u16 fw_status;
	u16 cmd_size;
	u16 cmdrsp_addr_lo;
	u16 cmdrsp_addr_hi;
	u16 tx_rdptr;
	u16 tx_wrptr;
	u16 rx_rdptr;
	u16 rx_wrptr;
	u16 evt_rdptr;
	u16 evt_wrptr;
	u16 drv_rdy;
	u16 tx_start_ptr;
	u32 tx_mask;
	u32 tx_wrap_mask;
	u32 rx_mask;
	u32 rx_wrap_mask;
	u32 tx_rollover_ind;
	u32 rx_rollover_ind;
	u32 evt_rollover_ind;
	u8 ring_flag_sop;
	u8 ring_flag_eop;
	u8 ring_flag_xs_sop;
	u8 ring_flag_xs_eop;
	u32 ring_tx_start_ptr;
	u8 pfu_enabled;
};

static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	.cmd_size = PCIE_SCRATCH_2_REG,
	.fw_status = PCIE_SCRATCH_3_REG,
	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	.tx_rdptr = PCIE_SCRATCH_6_REG,
	.tx_wrptr = PCIE_SCRATCH_7_REG,
	.rx_rdptr = PCIE_SCRATCH_8_REG,
	.rx_wrptr = PCIE_SCRATCH_9_REG,
	.evt_rdptr = PCIE_SCRATCH_10_REG,
	.evt_wrptr = PCIE_SCRATCH_11_REG,
	.drv_rdy = PCIE_SCRATCH_12_REG,
	.tx_start_ptr = 0,
	.tx_mask = MWIFIEX_TXBD_MASK,
	.tx_wrap_mask = 0,
	.rx_mask = MWIFIEX_RXBD_MASK,
	.rx_wrap_mask = 0,
	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	.ring_flag_sop = 0,
	.ring_flag_eop = 0,
	.ring_flag_xs_sop = 0,
	.ring_flag_xs_eop = 0,
	.ring_tx_start_ptr = 0,
	.pfu_enabled = 0,
};

struct mwifiex_pcie_device {
	const char *firmware;
	const struct mwifiex_pcie_card_reg *reg;
	u16 blksz_fw_dl;
};

static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
	.firmware       = PCIE8766_DEFAULT_FW_NAME,
	.reg            = &mwifiex_reg_8766,
	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
};

struct mwifiex_pcie_buf_desc {
	u64 paddr;
	u16 len;
	u16 flags;
} __packed;

struct pcie_service_card {
	struct pci_dev *dev;
	struct mwifiex_adapter *adapter;
	struct mwifiex_pcie_device pcie;

	u8 txbd_flush;
	u32 txbd_wrptr;
	u32 txbd_rdptr;
	u32 txbd_ring_size;
	u8 *txbd_ring_vbase;
	dma_addr_t txbd_ring_pbase;
	struct mwifiex_pcie_buf_desc *txbd_ring[MWIFIEX_MAX_TXRX_BD];
	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];

	u32 rxbd_wrptr;
	u32 rxbd_rdptr;
	u32 rxbd_ring_size;
	u8 *rxbd_ring_vbase;
	dma_addr_t rxbd_ring_pbase;
	struct mwifiex_pcie_buf_desc *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];

	u32 evtbd_wrptr;
	u32 evtbd_rdptr;
	u32 evtbd_ring_size;
	u8 *evtbd_ring_vbase;
	dma_addr_t evtbd_ring_pbase;
	struct mwifiex_pcie_buf_desc *evtbd_ring[MWIFIEX_MAX_EVT_BD];
	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];

	struct sk_buff *cmd_buf;
	struct sk_buff *cmdrsp_buf;
	u8 *sleep_cookie_vbase;
	dma_addr_t sleep_cookie_pbase;
	void __iomem *pci_mmap;
	void __iomem *pci_mmap1;
};

static inline int
mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
{
	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;

	if (((card->txbd_wrptr & reg->tx_mask) == (rdptr & reg->tx_mask)) &&
	    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
			(rdptr & reg->tx_rollover_ind)))
		return 1;

	return 0;
}

static inline int
mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
{
	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;

	if (((card->txbd_wrptr & reg->tx_mask) !=
	     (card->txbd_rdptr & reg->tx_mask)) ||
	    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
	     (card->txbd_rdptr & reg->tx_rollover_ind)))
		return 1;

	return 0;
}
#endif /* _MWIFIEX_PCIE_H */
Commit	Line	Data
d930faee AK	1	/* @file mwifiex_pcie.h
	2	*
	3	* @brief This file contains definitions for PCI-E interface.
	4	* driver.
	5	*
	6	* Copyright (C) 2011, Marvell International Ltd.
	7	*
	8	* This software file (the "File") is distributed by Marvell International
	9	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	10	* (the "License"). You may use, redistribute and/or modify this File in
	11	* accordance with the terms and conditions of the License, a copy of which
	12	* is available by writing to the Free Software Foundation, Inc.,
	13	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	14	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	15	*
	16	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	17	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	18	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	19	* this warranty disclaimer.
	20	*/
	21
	22	#ifndef _MWIFIEX_PCIE_H
	23	#define _MWIFIEX_PCIE_H
	24
	25	#include <linux/pci.h>
	26	#include <linux/pcieport_if.h>
	27	#include <linux/interrupt.h>
	28
	29	#include "main.h"
	30
	31	#define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
	32
	33	/* Constants for Buffer Descriptor (BD) rings */
	34	#define MWIFIEX_MAX_TXRX_BD 0x20
	35	#define MWIFIEX_TXBD_MASK 0x3F
	36	#define MWIFIEX_RXBD_MASK 0x3F
	37
	38	#define MWIFIEX_MAX_EVT_BD 0x04
	39	#define MWIFIEX_EVTBD_MASK 0x07
	40
	41	/* PCIE INTERNAL REGISTERS */
	42	#define PCIE_SCRATCH_0_REG 0xC10
	43	#define PCIE_SCRATCH_1_REG 0xC14
	44	#define PCIE_CPU_INT_EVENT 0xC18
	45	#define PCIE_CPU_INT_STATUS 0xC1C
	46	#define PCIE_HOST_INT_STATUS 0xC30
	47	#define PCIE_HOST_INT_MASK 0xC34
	48	#define PCIE_HOST_INT_STATUS_MASK 0xC3C
	49	#define PCIE_SCRATCH_2_REG 0xC40
	50	#define PCIE_SCRATCH_3_REG 0xC44
428ca8a7 BZ	51	#define PCIE_SCRATCH_4_REG 0xCD0
	52	#define PCIE_SCRATCH_5_REG 0xCD4
	53	#define PCIE_SCRATCH_6_REG 0xCD8
	54	#define PCIE_SCRATCH_7_REG 0xCDC
	55	#define PCIE_SCRATCH_8_REG 0xCE0
	56	#define PCIE_SCRATCH_9_REG 0xCE4
	57	#define PCIE_SCRATCH_10_REG 0xCE8
	58	#define PCIE_SCRATCH_11_REG 0xCEC
	59	#define PCIE_SCRATCH_12_REG 0xCF0
d930faee AK	60
	61	#define CPU_INTR_DNLD_RDY BIT(0)
	62	#define CPU_INTR_DOOR_BELL BIT(1)
	63	#define CPU_INTR_SLEEP_CFM_DONE BIT(2)
	64	#define CPU_INTR_RESET BIT(3)
	65
	66	#define HOST_INTR_DNLD_DONE BIT(0)
	67	#define HOST_INTR_UPLD_RDY BIT(1)
	68	#define HOST_INTR_CMD_DONE BIT(2)
	69	#define HOST_INTR_EVENT_RDY BIT(3)
	70	#define HOST_INTR_MASK (HOST_INTR_DNLD_DONE \| \
	71	HOST_INTR_UPLD_RDY \| \
	72	HOST_INTR_CMD_DONE \| \
	73	HOST_INTR_EVENT_RDY)
	74
	75	#define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7)
	76	#define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0)
	77	#define MWIFIEX_BD_FLAG_LAST_DESC BIT(1)
d930faee AK	78
	79	/* Max retry number of command write */
	80	#define MAX_WRITE_IOMEM_RETRY 2
	81	/* Define PCIE block size for firmware download */
	82	#define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256
	83	/* FW awake cookie after FW ready */
	84	#define FW_AWAKE_COOKIE (0xAA55AA55)
	85
dd04e6ac AP	86	struct mwifiex_pcie_card_reg {
	87	u16 cmd_addr_lo;
	88	u16 cmd_addr_hi;
	89	u16 fw_status;
	90	u16 cmd_size;
	91	u16 cmdrsp_addr_lo;
	92	u16 cmdrsp_addr_hi;
	93	u16 tx_rdptr;
	94	u16 tx_wrptr;
	95	u16 rx_rdptr;
	96	u16 rx_wrptr;
	97	u16 evt_rdptr;
	98	u16 evt_wrptr;
	99	u16 drv_rdy;
	100	u16 tx_start_ptr;
	101	u32 tx_mask;
	102	u32 tx_wrap_mask;
	103	u32 rx_mask;
	104	u32 rx_wrap_mask;
	105	u32 tx_rollover_ind;
	106	u32 rx_rollover_ind;
	107	u32 evt_rollover_ind;
	108	u8 ring_flag_sop;
	109	u8 ring_flag_eop;
	110	u8 ring_flag_xs_sop;
	111	u8 ring_flag_xs_eop;
	112	u32 ring_tx_start_ptr;
	113	u8 pfu_enabled;
	114	};
	115
	116	static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = {
	117	.cmd_addr_lo = PCIE_SCRATCH_0_REG,
	118	.cmd_addr_hi = PCIE_SCRATCH_1_REG,
	119	.cmd_size = PCIE_SCRATCH_2_REG,
	120	.fw_status = PCIE_SCRATCH_3_REG,
	121	.cmdrsp_addr_lo = PCIE_SCRATCH_4_REG,
	122	.cmdrsp_addr_hi = PCIE_SCRATCH_5_REG,
	123	.tx_rdptr = PCIE_SCRATCH_6_REG,
	124	.tx_wrptr = PCIE_SCRATCH_7_REG,
	125	.rx_rdptr = PCIE_SCRATCH_8_REG,
	126	.rx_wrptr = PCIE_SCRATCH_9_REG,
	127	.evt_rdptr = PCIE_SCRATCH_10_REG,
	128	.evt_wrptr = PCIE_SCRATCH_11_REG,
	129	.drv_rdy = PCIE_SCRATCH_12_REG,
	130	.tx_start_ptr = 0,
	131	.tx_mask = MWIFIEX_TXBD_MASK,
	132	.tx_wrap_mask = 0,
	133	.rx_mask = MWIFIEX_RXBD_MASK,
	134	.rx_wrap_mask = 0,
	135	.tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	136	.rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	137	.evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND,
	138	.ring_flag_sop = 0,
	139	.ring_flag_eop = 0,
	140	.ring_flag_xs_sop = 0,
	141	.ring_flag_xs_eop = 0,
	142	.ring_tx_start_ptr = 0,
	143	.pfu_enabled = 0,
	144	};
	145
	146	struct mwifiex_pcie_device {
	147	const char *firmware;
	148	const struct mwifiex_pcie_card_reg *reg;
	149	u16 blksz_fw_dl;
150	};
151
152	static const struct mwifiex_pcie_device mwifiex_pcie8766 = {
153	.firmware = PCIE8766_DEFAULT_FW_NAME,
154	.reg = &mwifiex_reg_8766,
155	.blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD,
156	};
157
d930faee AK	158	struct mwifiex_pcie_buf_desc {
	159	u64 paddr;
	160	u16 len;
	161	u16 flags;
	162	} __packed;
	163
	164	struct pcie_service_card {
	165	struct pci_dev *dev;
	166	struct mwifiex_adapter *adapter;
dd04e6ac	167	struct mwifiex_pcie_device pcie;
d930faee	168
fbd7e7ac	169	u8 txbd_flush;
d930faee AK	170	u32 txbd_wrptr;
	171	u32 txbd_rdptr;
	172	u32 txbd_ring_size;
	173	u8 *txbd_ring_vbase;
fc331460	174	dma_addr_t txbd_ring_pbase;
d930faee AK	175	struct mwifiex_pcie_buf_desc *txbd_ring[MWIFIEX_MAX_TXRX_BD];
	176	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
	177
	178	u32 rxbd_wrptr;
	179	u32 rxbd_rdptr;
	180	u32 rxbd_ring_size;
	181	u8 *rxbd_ring_vbase;
fc331460	182	dma_addr_t rxbd_ring_pbase;
d930faee AK	183	struct mwifiex_pcie_buf_desc *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
	184	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
	185
	186	u32 evtbd_wrptr;
	187	u32 evtbd_rdptr;
	188	u32 evtbd_ring_size;
	189	u8 *evtbd_ring_vbase;
fc331460	190	dma_addr_t evtbd_ring_pbase;
d930faee AK	191	struct mwifiex_pcie_buf_desc *evtbd_ring[MWIFIEX_MAX_EVT_BD];
	192	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
	193
	194	struct sk_buff *cmd_buf;
	195	struct sk_buff *cmdrsp_buf;
fc331460 AP	196	u8 *sleep_cookie_vbase;
fc331460 AP	197	dma_addr_t sleep_cookie_pbase;
d930faee AK	198	void __iomem *pci_mmap;
	199	void __iomem *pci_mmap1;
	200	};
	201
fbd7e7ac AP	202	static inline int
	203	mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
	204	{
dd04e6ac AP	205	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
	206
	207	if (((card->txbd_wrptr & reg->tx_mask) == (rdptr & reg->tx_mask)) &&
	208	((card->txbd_wrptr & reg->tx_rollover_ind) !=
	209	(rdptr & reg->tx_rollover_ind)))
fbd7e7ac AP	210	return 1;
	211
	212	return 0;
	213	}
	214
e7f767a7 AP	215	static inline int
	216	mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
	217	{
dd04e6ac AP	218	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
	219
	220	if (((card->txbd_wrptr & reg->tx_mask) !=
	221	(card->txbd_rdptr & reg->tx_mask)) \|\|
	222	((card->txbd_wrptr & reg->tx_rollover_ind) !=
	223	(card->txbd_rdptr & reg->tx_rollover_ind)))
e7f767a7 AP	224	return 1;
	225
	226	return 0;
	227	}
d930faee	228	#endif /* _MWIFIEX_PCIE_H */