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d930faee AK |
1 | /* @file mwifiex_pcie.h |
2 | * | |
3 | * @brief This file contains definitions for PCI-E interface. | |
4 | * driver. | |
5 | * | |
6 | * Copyright (C) 2011, Marvell International Ltd. | |
7 | * | |
8 | * This software file (the "File") is distributed by Marvell International | |
9 | * Ltd. under the terms of the GNU General Public License Version 2, June 1991 | |
10 | * (the "License"). You may use, redistribute and/or modify this File in | |
11 | * accordance with the terms and conditions of the License, a copy of which | |
12 | * is available by writing to the Free Software Foundation, Inc., | |
13 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the | |
14 | * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. | |
15 | * | |
16 | * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE | |
17 | * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE | |
18 | * ARE EXPRESSLY DISCLAIMED. The License provides additional details about | |
19 | * this warranty disclaimer. | |
20 | */ | |
21 | ||
22 | #ifndef _MWIFIEX_PCIE_H | |
23 | #define _MWIFIEX_PCIE_H | |
24 | ||
25 | #include <linux/pci.h> | |
26 | #include <linux/pcieport_if.h> | |
27 | #include <linux/interrupt.h> | |
28 | ||
29 | #include "main.h" | |
30 | ||
31 | #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin" | |
ca8f2112 AP |
32 | #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin" |
33 | ||
34 | #define PCIE_VENDOR_ID_MARVELL (0x11ab) | |
35 | #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30) | |
36 | #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38) | |
d930faee AK |
37 | |
38 | /* Constants for Buffer Descriptor (BD) rings */ | |
39 | #define MWIFIEX_MAX_TXRX_BD 0x20 | |
40 | #define MWIFIEX_TXBD_MASK 0x3F | |
41 | #define MWIFIEX_RXBD_MASK 0x3F | |
42 | ||
43 | #define MWIFIEX_MAX_EVT_BD 0x04 | |
44 | #define MWIFIEX_EVTBD_MASK 0x07 | |
45 | ||
46 | /* PCIE INTERNAL REGISTERS */ | |
47 | #define PCIE_SCRATCH_0_REG 0xC10 | |
48 | #define PCIE_SCRATCH_1_REG 0xC14 | |
49 | #define PCIE_CPU_INT_EVENT 0xC18 | |
50 | #define PCIE_CPU_INT_STATUS 0xC1C | |
51 | #define PCIE_HOST_INT_STATUS 0xC30 | |
52 | #define PCIE_HOST_INT_MASK 0xC34 | |
53 | #define PCIE_HOST_INT_STATUS_MASK 0xC3C | |
54 | #define PCIE_SCRATCH_2_REG 0xC40 | |
55 | #define PCIE_SCRATCH_3_REG 0xC44 | |
428ca8a7 BZ |
56 | #define PCIE_SCRATCH_4_REG 0xCD0 |
57 | #define PCIE_SCRATCH_5_REG 0xCD4 | |
58 | #define PCIE_SCRATCH_6_REG 0xCD8 | |
59 | #define PCIE_SCRATCH_7_REG 0xCDC | |
60 | #define PCIE_SCRATCH_8_REG 0xCE0 | |
61 | #define PCIE_SCRATCH_9_REG 0xCE4 | |
62 | #define PCIE_SCRATCH_10_REG 0xCE8 | |
63 | #define PCIE_SCRATCH_11_REG 0xCEC | |
64 | #define PCIE_SCRATCH_12_REG 0xCF0 | |
ca8f2112 AP |
65 | #define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C |
66 | #define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C | |
d930faee AK |
67 | |
68 | #define CPU_INTR_DNLD_RDY BIT(0) | |
69 | #define CPU_INTR_DOOR_BELL BIT(1) | |
70 | #define CPU_INTR_SLEEP_CFM_DONE BIT(2) | |
71 | #define CPU_INTR_RESET BIT(3) | |
72 | ||
73 | #define HOST_INTR_DNLD_DONE BIT(0) | |
74 | #define HOST_INTR_UPLD_RDY BIT(1) | |
75 | #define HOST_INTR_CMD_DONE BIT(2) | |
76 | #define HOST_INTR_EVENT_RDY BIT(3) | |
77 | #define HOST_INTR_MASK (HOST_INTR_DNLD_DONE | \ | |
78 | HOST_INTR_UPLD_RDY | \ | |
79 | HOST_INTR_CMD_DONE | \ | |
80 | HOST_INTR_EVENT_RDY) | |
81 | ||
82 | #define MWIFIEX_BD_FLAG_ROLLOVER_IND BIT(7) | |
83 | #define MWIFIEX_BD_FLAG_FIRST_DESC BIT(0) | |
84 | #define MWIFIEX_BD_FLAG_LAST_DESC BIT(1) | |
ca8f2112 AP |
85 | #define MWIFIEX_BD_FLAG_SOP BIT(0) |
86 | #define MWIFIEX_BD_FLAG_EOP BIT(1) | |
87 | #define MWIFIEX_BD_FLAG_XS_SOP BIT(2) | |
88 | #define MWIFIEX_BD_FLAG_XS_EOP BIT(3) | |
89 | #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND BIT(7) | |
90 | #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND BIT(10) | |
91 | #define MWIFIEX_BD_FLAG_TX_START_PTR BIT(16) | |
92 | #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND BIT(26) | |
d930faee AK |
93 | |
94 | /* Max retry number of command write */ | |
95 | #define MAX_WRITE_IOMEM_RETRY 2 | |
96 | /* Define PCIE block size for firmware download */ | |
97 | #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD 256 | |
98 | /* FW awake cookie after FW ready */ | |
99 | #define FW_AWAKE_COOKIE (0xAA55AA55) | |
100 | ||
dd04e6ac AP |
101 | struct mwifiex_pcie_card_reg { |
102 | u16 cmd_addr_lo; | |
103 | u16 cmd_addr_hi; | |
104 | u16 fw_status; | |
105 | u16 cmd_size; | |
106 | u16 cmdrsp_addr_lo; | |
107 | u16 cmdrsp_addr_hi; | |
108 | u16 tx_rdptr; | |
109 | u16 tx_wrptr; | |
110 | u16 rx_rdptr; | |
111 | u16 rx_wrptr; | |
112 | u16 evt_rdptr; | |
113 | u16 evt_wrptr; | |
114 | u16 drv_rdy; | |
115 | u16 tx_start_ptr; | |
116 | u32 tx_mask; | |
117 | u32 tx_wrap_mask; | |
118 | u32 rx_mask; | |
119 | u32 rx_wrap_mask; | |
120 | u32 tx_rollover_ind; | |
121 | u32 rx_rollover_ind; | |
122 | u32 evt_rollover_ind; | |
123 | u8 ring_flag_sop; | |
124 | u8 ring_flag_eop; | |
125 | u8 ring_flag_xs_sop; | |
126 | u8 ring_flag_xs_eop; | |
127 | u32 ring_tx_start_ptr; | |
128 | u8 pfu_enabled; | |
52301a81 | 129 | u8 sleep_cookie; |
dd04e6ac AP |
130 | }; |
131 | ||
132 | static const struct mwifiex_pcie_card_reg mwifiex_reg_8766 = { | |
133 | .cmd_addr_lo = PCIE_SCRATCH_0_REG, | |
134 | .cmd_addr_hi = PCIE_SCRATCH_1_REG, | |
135 | .cmd_size = PCIE_SCRATCH_2_REG, | |
136 | .fw_status = PCIE_SCRATCH_3_REG, | |
137 | .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, | |
138 | .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, | |
139 | .tx_rdptr = PCIE_SCRATCH_6_REG, | |
140 | .tx_wrptr = PCIE_SCRATCH_7_REG, | |
141 | .rx_rdptr = PCIE_SCRATCH_8_REG, | |
142 | .rx_wrptr = PCIE_SCRATCH_9_REG, | |
143 | .evt_rdptr = PCIE_SCRATCH_10_REG, | |
144 | .evt_wrptr = PCIE_SCRATCH_11_REG, | |
145 | .drv_rdy = PCIE_SCRATCH_12_REG, | |
146 | .tx_start_ptr = 0, | |
147 | .tx_mask = MWIFIEX_TXBD_MASK, | |
148 | .tx_wrap_mask = 0, | |
149 | .rx_mask = MWIFIEX_RXBD_MASK, | |
150 | .rx_wrap_mask = 0, | |
151 | .tx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, | |
152 | .rx_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, | |
153 | .evt_rollover_ind = MWIFIEX_BD_FLAG_ROLLOVER_IND, | |
154 | .ring_flag_sop = 0, | |
155 | .ring_flag_eop = 0, | |
156 | .ring_flag_xs_sop = 0, | |
157 | .ring_flag_xs_eop = 0, | |
158 | .ring_tx_start_ptr = 0, | |
159 | .pfu_enabled = 0, | |
52301a81 | 160 | .sleep_cookie = 1, |
dd04e6ac AP |
161 | }; |
162 | ||
ca8f2112 AP |
163 | static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = { |
164 | .cmd_addr_lo = PCIE_SCRATCH_0_REG, | |
165 | .cmd_addr_hi = PCIE_SCRATCH_1_REG, | |
166 | .cmd_size = PCIE_SCRATCH_2_REG, | |
167 | .fw_status = PCIE_SCRATCH_3_REG, | |
168 | .cmdrsp_addr_lo = PCIE_SCRATCH_4_REG, | |
169 | .cmdrsp_addr_hi = PCIE_SCRATCH_5_REG, | |
170 | .tx_rdptr = PCIE_RD_DATA_PTR_Q0_Q1, | |
171 | .tx_wrptr = PCIE_WR_DATA_PTR_Q0_Q1, | |
172 | .rx_rdptr = PCIE_WR_DATA_PTR_Q0_Q1, | |
173 | .rx_wrptr = PCIE_RD_DATA_PTR_Q0_Q1, | |
174 | .evt_rdptr = PCIE_SCRATCH_10_REG, | |
175 | .evt_wrptr = PCIE_SCRATCH_11_REG, | |
176 | .drv_rdy = PCIE_SCRATCH_12_REG, | |
177 | .tx_start_ptr = 16, | |
178 | .tx_mask = 0x03FF0000, | |
179 | .tx_wrap_mask = 0x07FF0000, | |
180 | .rx_mask = 0x000003FF, | |
181 | .rx_wrap_mask = 0x000007FF, | |
182 | .tx_rollover_ind = MWIFIEX_BD_FLAG_TX_ROLLOVER_IND, | |
183 | .rx_rollover_ind = MWIFIEX_BD_FLAG_RX_ROLLOVER_IND, | |
184 | .evt_rollover_ind = MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND, | |
185 | .ring_flag_sop = MWIFIEX_BD_FLAG_SOP, | |
186 | .ring_flag_eop = MWIFIEX_BD_FLAG_EOP, | |
187 | .ring_flag_xs_sop = MWIFIEX_BD_FLAG_XS_SOP, | |
188 | .ring_flag_xs_eop = MWIFIEX_BD_FLAG_XS_EOP, | |
189 | .ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR, | |
190 | .pfu_enabled = 1, | |
52301a81 | 191 | .sleep_cookie = 0, |
ca8f2112 AP |
192 | }; |
193 | ||
dd04e6ac AP |
194 | struct mwifiex_pcie_device { |
195 | const char *firmware; | |
196 | const struct mwifiex_pcie_card_reg *reg; | |
197 | u16 blksz_fw_dl; | |
198 | }; | |
199 | ||
200 | static const struct mwifiex_pcie_device mwifiex_pcie8766 = { | |
201 | .firmware = PCIE8766_DEFAULT_FW_NAME, | |
202 | .reg = &mwifiex_reg_8766, | |
203 | .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, | |
204 | }; | |
205 | ||
ca8f2112 AP |
206 | static const struct mwifiex_pcie_device mwifiex_pcie8897 = { |
207 | .firmware = PCIE8897_DEFAULT_FW_NAME, | |
208 | .reg = &mwifiex_reg_8897, | |
209 | .blksz_fw_dl = MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD, | |
210 | }; | |
211 | ||
e05dc3e9 AP |
212 | struct mwifiex_evt_buf_desc { |
213 | u64 paddr; | |
214 | u16 len; | |
215 | u16 flags; | |
216 | } __packed; | |
217 | ||
d930faee AK |
218 | struct mwifiex_pcie_buf_desc { |
219 | u64 paddr; | |
220 | u16 len; | |
221 | u16 flags; | |
222 | } __packed; | |
223 | ||
ca8f2112 AP |
224 | struct mwifiex_pfu_buf_desc { |
225 | u16 flags; | |
226 | u16 offset; | |
227 | u16 frag_len; | |
228 | u16 len; | |
229 | u64 paddr; | |
230 | u32 reserved; | |
231 | } __packed; | |
232 | ||
d930faee AK |
233 | struct pcie_service_card { |
234 | struct pci_dev *dev; | |
235 | struct mwifiex_adapter *adapter; | |
dd04e6ac | 236 | struct mwifiex_pcie_device pcie; |
d930faee | 237 | |
fbd7e7ac | 238 | u8 txbd_flush; |
d930faee AK |
239 | u32 txbd_wrptr; |
240 | u32 txbd_rdptr; | |
241 | u32 txbd_ring_size; | |
242 | u8 *txbd_ring_vbase; | |
fc331460 | 243 | dma_addr_t txbd_ring_pbase; |
e05dc3e9 | 244 | void *txbd_ring[MWIFIEX_MAX_TXRX_BD]; |
d930faee AK |
245 | struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD]; |
246 | ||
247 | u32 rxbd_wrptr; | |
248 | u32 rxbd_rdptr; | |
249 | u32 rxbd_ring_size; | |
250 | u8 *rxbd_ring_vbase; | |
fc331460 | 251 | dma_addr_t rxbd_ring_pbase; |
e05dc3e9 | 252 | void *rxbd_ring[MWIFIEX_MAX_TXRX_BD]; |
d930faee AK |
253 | struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD]; |
254 | ||
255 | u32 evtbd_wrptr; | |
256 | u32 evtbd_rdptr; | |
257 | u32 evtbd_ring_size; | |
258 | u8 *evtbd_ring_vbase; | |
fc331460 | 259 | dma_addr_t evtbd_ring_pbase; |
e05dc3e9 | 260 | void *evtbd_ring[MWIFIEX_MAX_EVT_BD]; |
d930faee AK |
261 | struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD]; |
262 | ||
263 | struct sk_buff *cmd_buf; | |
264 | struct sk_buff *cmdrsp_buf; | |
fc331460 AP |
265 | u8 *sleep_cookie_vbase; |
266 | dma_addr_t sleep_cookie_pbase; | |
d930faee AK |
267 | void __iomem *pci_mmap; |
268 | void __iomem *pci_mmap1; | |
269 | }; | |
270 | ||
fbd7e7ac AP |
271 | static inline int |
272 | mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr) | |
273 | { | |
dd04e6ac AP |
274 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
275 | ||
ca8f2112 AP |
276 | switch (card->dev->device) { |
277 | case PCIE_DEVICE_ID_MARVELL_88W8766P: | |
278 | if (((card->txbd_wrptr & reg->tx_mask) == | |
279 | (rdptr & reg->tx_mask)) && | |
280 | ((card->txbd_wrptr & reg->tx_rollover_ind) != | |
281 | (rdptr & reg->tx_rollover_ind))) | |
282 | return 1; | |
283 | break; | |
284 | case PCIE_DEVICE_ID_MARVELL_88W8897: | |
285 | if (((card->txbd_wrptr & reg->tx_mask) == | |
286 | (rdptr & reg->tx_mask)) && | |
287 | ((card->txbd_wrptr & reg->tx_rollover_ind) == | |
dd04e6ac | 288 | (rdptr & reg->tx_rollover_ind))) |
ca8f2112 AP |
289 | return 1; |
290 | break; | |
291 | } | |
fbd7e7ac AP |
292 | |
293 | return 0; | |
294 | } | |
295 | ||
e7f767a7 AP |
296 | static inline int |
297 | mwifiex_pcie_txbd_not_full(struct pcie_service_card *card) | |
298 | { | |
dd04e6ac AP |
299 | const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; |
300 | ||
ca8f2112 AP |
301 | switch (card->dev->device) { |
302 | case PCIE_DEVICE_ID_MARVELL_88W8766P: | |
303 | if (((card->txbd_wrptr & reg->tx_mask) != | |
304 | (card->txbd_rdptr & reg->tx_mask)) || | |
305 | ((card->txbd_wrptr & reg->tx_rollover_ind) != | |
306 | (card->txbd_rdptr & reg->tx_rollover_ind))) | |
307 | return 1; | |
308 | break; | |
309 | case PCIE_DEVICE_ID_MARVELL_88W8897: | |
310 | if (((card->txbd_wrptr & reg->tx_mask) != | |
311 | (card->txbd_rdptr & reg->tx_mask)) || | |
312 | ((card->txbd_wrptr & reg->tx_rollover_ind) == | |
313 | (card->txbd_rdptr & reg->tx_rollover_ind))) | |
314 | return 1; | |
315 | break; | |
316 | } | |
e7f767a7 AP |
317 | |
318 | return 0; | |
319 | } | |
d930faee | 320 | #endif /* _MWIFIEX_PCIE_H */ |