[deliverable/linux.git] / drivers / net / wireless / mwifiex / sdio.h

/*
 * Marvell Wireless LAN device driver: SDIO specific definitions
 *
 * Copyright (C) 2011, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_SDIO_H
#define	_MWIFIEX_SDIO_H


#include <linux/mmc/sdio.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>

#include "main.h"

#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"

#define BLOCK_MODE	1
#define BYTE_MODE	0

#define REG_PORT			0

#define MWIFIEX_SDIO_IO_PORT_MASK		0xfffff

#define MWIFIEX_SDIO_BYTE_MODE_MASK	0x80000000

#define SDIO_MPA_ADDR_BASE		0x1000
#define CTRL_PORT			0
#define CTRL_PORT_MASK			0x0001

#define CMD_PORT_UPLD_INT_MASK		(0x1U<<6)
#define CMD_PORT_DNLD_INT_MASK		(0x1U<<7)
#define HOST_TERM_CMD53			(0x1U << 2)
#define REG_PORT			0
#define MEM_PORT			0x10000
#define CMD_RD_LEN_0			0xB4
#define CMD_RD_LEN_1			0xB5
#define CARD_CONFIG_2_1_REG             0xCD
#define CMD53_NEW_MODE			(0x1U << 0)
#define CMD_CONFIG_0			0xB8
#define CMD_PORT_RD_LEN_EN		(0x1U << 2)
#define CMD_CONFIG_1			0xB9
#define CMD_PORT_AUTO_EN		(0x1U << 0)
#define CMD_PORT_SLCT			0x8000
#define UP_LD_CMD_PORT_HOST_INT_STATUS	(0x40U)
#define DN_LD_CMD_PORT_HOST_INT_STATUS	(0x80U)

#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE        (8192)	/* 8K */

/* Multi port RX aggregation buffer size */
#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE        (16384)	/* 16K */

/* Misc. Config Register : Auto Re-enable interrupts */
#define AUTO_RE_ENABLE_INT              BIT(4)

/* Host Control Registers */
/* Host Control Registers : I/O port 0 */
#define IO_PORT_0_REG			0x78
/* Host Control Registers : I/O port 1 */
#define IO_PORT_1_REG			0x79
/* Host Control Registers : I/O port 2 */
#define IO_PORT_2_REG			0x7A

/* Host Control Registers : Configuration */
#define CONFIGURATION_REG		0x00
/* Host Control Registers : Host power up */
#define HOST_POWER_UP			(0x1U << 1)

/* Host Control Registers : Host interrupt mask */
#define HOST_INT_MASK_REG		0x02
/* Host Control Registers : Upload host interrupt mask */
#define UP_LD_HOST_INT_MASK		(0x1U)
/* Host Control Registers : Download host interrupt mask */
#define DN_LD_HOST_INT_MASK		(0x2U)

/* Host Control Registers : Host interrupt status */
#define HOST_INTSTATUS_REG		0x03
/* Host Control Registers : Upload host interrupt status */
#define UP_LD_HOST_INT_STATUS		(0x1U)
/* Host Control Registers : Download host interrupt status */
#define DN_LD_HOST_INT_STATUS		(0x2U)

/* Host Control Registers : Host interrupt RSR */
#define HOST_INT_RSR_REG		0x01

/* Host Control Registers : Host interrupt status */
#define HOST_INT_STATUS_REG		0x28

/* Card Control Registers : Card I/O ready */
#define CARD_IO_READY                   (0x1U << 3)
/* Card Control Registers : Download card ready */
#define DN_LD_CARD_RDY                  (0x1U << 0)

/* Max retry number of CMD53 write */
#define MAX_WRITE_IOMEM_RETRY		2

/* SDIO Tx aggregation in progress ? */
#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)

/* SDIO Tx aggregation buffer room for next packet ? */
#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)	\
						<= a->mpa_tx.buf_size)

/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {		\
	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],			\
			payload, pkt_len);				\
	a->mpa_tx.buf_len += pkt_len;					\
	if (!a->mpa_tx.pkt_cnt)						\
		a->mpa_tx.start_port = port;				\
	if (a->mpa_tx.start_port <= port)				\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));		\
	else								\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+		\
						(a->max_ports -	\
						a->mp_end_port)));	\
	a->mpa_tx.pkt_cnt++;						\
} while (0)

/* SDIO Tx aggregation limit ? */
#define MP_TX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)

/* Reset SDIO Tx aggregation buffer parameters */
#define MP_TX_AGGR_BUF_RESET(a) do {					\
	a->mpa_tx.pkt_cnt = 0;						\
	a->mpa_tx.buf_len = 0;						\
	a->mpa_tx.ports = 0;						\
	a->mpa_tx.start_port = 0;					\
} while (0)

/* SDIO Rx aggregation limit ? */
#define MP_RX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)

/* SDIO Rx aggregation in progress ? */
#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)

/* SDIO Rx aggregation buffer room for next packet ? */
#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)				\
			((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)

/* Reset SDIO Rx aggregation buffer parameters */
#define MP_RX_AGGR_BUF_RESET(a) do {					\
	a->mpa_rx.pkt_cnt = 0;						\
	a->mpa_rx.buf_len = 0;						\
	a->mpa_rx.ports = 0;						\
	a->mpa_rx.start_port = 0;					\
} while (0)

/* data structure for SDIO MPA TX */
struct mwifiex_sdio_mpa_tx {
	/* multiport tx aggregation buffer pointer */
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;
	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

struct mwifiex_sdio_mpa_rx {
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;

	struct sk_buff **skb_arr;
	u32 *len_arr;

	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

int mwifiex_bus_register(void);
void mwifiex_bus_unregister(void);

struct mwifiex_sdio_card_reg {
	u8 start_rd_port;
	u8 start_wr_port;
	u8 base_0_reg;
	u8 base_1_reg;
	u8 poll_reg;
	u8 host_int_enable;
	u8 status_reg_0;
	u8 status_reg_1;
	u8 sdio_int_mask;
	u32 data_port_mask;
	u8 max_mp_regs;
	u8 rd_bitmap_l;
	u8 rd_bitmap_u;
	u8 rd_bitmap_1l;
	u8 rd_bitmap_1u;
	u8 wr_bitmap_l;
	u8 wr_bitmap_u;
	u8 wr_bitmap_1l;
	u8 wr_bitmap_1u;
	u8 rd_len_p0_l;
	u8 rd_len_p0_u;
	u8 card_misc_cfg_reg;
};

struct sdio_mmc_card {
	struct sdio_func *func;
	struct mwifiex_adapter *adapter;

	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;
	bool supports_sdio_new_mode;
	bool has_control_mask;

	u32 mp_rd_bitmap;
	u32 mp_wr_bitmap;

	u16 mp_end_port;
	u32 mp_data_port_mask;

	u8 curr_rd_port;
	u8 curr_wr_port;

	u8 *mp_regs;

	struct mwifiex_sdio_mpa_tx mpa_tx;
	struct mwifiex_sdio_mpa_rx mpa_rx;
};

struct mwifiex_sdio_device {
	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;
	bool supports_sdio_new_mode;
	bool has_control_mask;
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	.start_rd_port = 1,
	.start_wr_port = 1,
	.base_0_reg = 0x0040,
	.base_1_reg = 0x0041,
	.poll_reg = 0x30,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
	.status_reg_0 = 0x60,
	.status_reg_1 = 0x61,
	.sdio_int_mask = 0x3f,
	.data_port_mask = 0x0000fffe,
	.max_mp_regs = 64,
	.rd_bitmap_l = 0x04,
	.rd_bitmap_u = 0x05,
	.wr_bitmap_l = 0x06,
	.wr_bitmap_u = 0x07,
	.rd_len_p0_l = 0x08,
	.rd_len_p0_u = 0x09,
	.card_misc_cfg_reg = 0x6c,
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
	.start_rd_port = 0,
	.start_wr_port = 0,
	.base_0_reg = 0x60,
	.base_1_reg = 0x61,
	.poll_reg = 0x50,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
			CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
	.status_reg_0 = 0xc0,
	.status_reg_1 = 0xc1,
	.sdio_int_mask = 0xff,
	.data_port_mask = 0xffffffff,
	.max_mp_regs = 184,
	.rd_bitmap_l = 0x04,
	.rd_bitmap_u = 0x05,
	.rd_bitmap_1l = 0x06,
	.rd_bitmap_1u = 0x07,
	.wr_bitmap_l = 0x08,
	.wr_bitmap_u = 0x09,
	.wr_bitmap_1l = 0x0a,
	.wr_bitmap_1u = 0x0b,
	.rd_len_p0_l = 0x0c,
	.rd_len_p0_u = 0x0d,
	.card_misc_cfg_reg = 0xcc,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	.firmware = SD8786_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	.firmware = SD8787_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	.firmware = SD8797_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
	.firmware = SD8897_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd8897,
	.max_ports = 32,
	.mp_agg_pkt_limit = 16,
	.supports_sdio_new_mode = true,
	.has_control_mask = false,
};

/*
 * .cmdrsp_complete handler
 */
static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
					       struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

/*
 * .event_complete handler
 */
static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
					      struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

static inline bool
mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
{
	u8 tmp;

	if (card->curr_rd_port < card->mpa_rx.start_port) {
		if (card->supports_sdio_new_mode)
			tmp = card->mp_end_port >> 1;
		else
			tmp = card->mp_agg_pkt_limit;

		if (((card->max_ports - card->mpa_rx.start_port) +
		    card->curr_rd_port) >= tmp)
			return true;
	}

	if (!card->supports_sdio_new_mode)
		return false;

	if ((card->curr_rd_port - card->mpa_rx.start_port) >=
	    (card->mp_end_port >> 1))
		return true;

	return false;
}

static inline bool
mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
{
	u16 tmp;

	if (card->curr_wr_port < card->mpa_tx.start_port) {
		if (card->supports_sdio_new_mode)
			tmp = card->mp_end_port >> 1;
		else
			tmp = card->mp_agg_pkt_limit;

		if (((card->max_ports - card->mpa_tx.start_port) +
		    card->curr_wr_port) >= tmp)
			return true;
	}

	if (!card->supports_sdio_new_mode)
		return false;

	if ((card->curr_wr_port - card->mpa_tx.start_port) >=
	    (card->mp_end_port >> 1))
		return true;

	return false;
}

/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
				    struct sk_buff *skb, u8 port)
{
	card->mpa_rx.buf_len += skb->len;

	if (!card->mpa_rx.pkt_cnt)
		card->mpa_rx.start_port = port;

	if (card->supports_sdio_new_mode) {
		card->mpa_rx.ports |= (1 << port);
	} else {
		if (card->mpa_rx.start_port <= port)
			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
		else
			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
	}
	card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
	card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
	card->mpa_rx.pkt_cnt++;
}
#endif /* _MWIFIEX_SDIO_H */
Commit	Line	Data
5e6e3a92 BZ	1	/*
	2	* Marvell Wireless LAN device driver: SDIO specific definitions
	3	*
	4	* Copyright (C) 2011, Marvell International Ltd.
	5	*
	6	* This software file (the "File") is distributed by Marvell International
	7	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	8	* (the "License"). You may use, redistribute and/or modify this File in
	9	* accordance with the terms and conditions of the License, a copy of which
	10	* is available by writing to the Free Software Foundation, Inc.,
	11	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	12	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	13	*
	14	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	15	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	16	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	17	* this warranty disclaimer.
	18	*/
	19
	20	#ifndef _MWIFIEX_SDIO_H
	21	#define _MWIFIEX_SDIO_H
	22
	23
	24	#include <linux/mmc/sdio.h>
	25	#include <linux/mmc/sdio_ids.h>
	26	#include <linux/mmc/sdio_func.h>
	27	#include <linux/mmc/card.h>
d31ab357	28	#include <linux/mmc/host.h>
5e6e3a92 BZ	29
	30	#include "main.h"
	31
98e6b9df	32	#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
4a7f5db1	33	#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
e3bea1c8	34	#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
b60186f8	35	#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
4a7f5db1	36
5e6e3a92 BZ	37	#define BLOCK_MODE 1
	38	#define BYTE_MODE 0
	39
	40	#define REG_PORT 0
5e6e3a92 BZ	41
	42	#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
	43
	44	#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
	45
248eb4c6	46	#define SDIO_MPA_ADDR_BASE 0x1000
5e6e3a92 BZ	47	#define CTRL_PORT 0
5e6e3a92 BZ	48	#define CTRL_PORT_MASK 0x0001
5e6e3a92	49
b60186f8 YAP	50	#define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
	51	#define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
	52	#define HOST_TERM_CMD53 (0x1U << 2)
	53	#define REG_PORT 0
	54	#define MEM_PORT 0x10000
	55	#define CMD_RD_LEN_0 0xB4
	56	#define CMD_RD_LEN_1 0xB5
	57	#define CARD_CONFIG_2_1_REG 0xCD
	58	#define CMD53_NEW_MODE (0x1U << 0)
	59	#define CMD_CONFIG_0 0xB8
	60	#define CMD_PORT_RD_LEN_EN (0x1U << 2)
	61	#define CMD_CONFIG_1 0xB9
	62	#define CMD_PORT_AUTO_EN (0x1U << 0)
	63	#define CMD_PORT_SLCT 0x8000
	64	#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
	65	#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
	66
f0c717e6	67	#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
5e6e3a92 BZ	68
5e6e3a92 BZ	69	/* Multi port RX aggregation buffer size */
f0c717e6	70	#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
5e6e3a92 BZ	71
	72	/* Misc. Config Register : Auto Re-enable interrupts */
	73	#define AUTO_RE_ENABLE_INT BIT(4)
	74
	75	/* Host Control Registers */
	76	/* Host Control Registers : I/O port 0 */
	77	#define IO_PORT_0_REG 0x78
	78	/* Host Control Registers : I/O port 1 */
	79	#define IO_PORT_1_REG 0x79
	80	/* Host Control Registers : I/O port 2 */
	81	#define IO_PORT_2_REG 0x7A
	82
	83	/* Host Control Registers : Configuration */
	84	#define CONFIGURATION_REG 0x00
5e6e3a92 BZ	85	/* Host Control Registers : Host power up */
5e6e3a92 BZ	86	#define HOST_POWER_UP (0x1U << 1)
5e6e3a92 BZ	87
	88	/* Host Control Registers : Host interrupt mask */
	89	#define HOST_INT_MASK_REG 0x02
	90	/* Host Control Registers : Upload host interrupt mask */
	91	#define UP_LD_HOST_INT_MASK (0x1U)
	92	/* Host Control Registers : Download host interrupt mask */
	93	#define DN_LD_HOST_INT_MASK (0x2U)
b60186f8	94
5e6e3a92 BZ	95	/* Host Control Registers : Host interrupt status */
	96	#define HOST_INTSTATUS_REG 0x03
	97	/* Host Control Registers : Upload host interrupt status */
	98	#define UP_LD_HOST_INT_STATUS (0x1U)
	99	/* Host Control Registers : Download host interrupt status */
	100	#define DN_LD_HOST_INT_STATUS (0x2U)
	101
	102	/* Host Control Registers : Host interrupt RSR */
	103	#define HOST_INT_RSR_REG 0x01
5e6e3a92 BZ	104
	105	/* Host Control Registers : Host interrupt status */
	106	#define HOST_INT_STATUS_REG 0x28
5e6e3a92	107
5e6e3a92 BZ	108	/* Card Control Registers : Card I/O ready */
5e6e3a92 BZ	109	#define CARD_IO_READY (0x1U << 3)
5e6e3a92 BZ	110	/* Card Control Registers : Download card ready */
	111	#define DN_LD_CARD_RDY (0x1U << 0)
	112
5e6e3a92 BZ	113	/* Max retry number of CMD53 write */
	114	#define MAX_WRITE_IOMEM_RETRY 2
	115
	116	/* SDIO Tx aggregation in progress ? */
	117	#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
	118
	119	/* SDIO Tx aggregation buffer room for next packet ? */
	120	#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
	121	<= a->mpa_tx.buf_size)
	122
	123	/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
	124	#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
	125	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
	126	payload, pkt_len); \
	127	a->mpa_tx.buf_len += pkt_len; \
	128	if (!a->mpa_tx.pkt_cnt) \
	129	a->mpa_tx.start_port = port; \
	130	if (a->mpa_tx.start_port <= port) \
	131	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt)); \
	132	else \
05889f82 AK	133	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt+1+ \
05889f82 AK	134	(a->max_ports - \
5e6e3a92 BZ	135	a->mp_end_port))); \
5e6e3a92 BZ	136	a->mpa_tx.pkt_cnt++; \
da951c24	137	} while (0)
5e6e3a92 BZ	138
	139	/* SDIO Tx aggregation limit ? */
	140	#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
	141	(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
	142
5e6e3a92 BZ	143	/* Reset SDIO Tx aggregation buffer parameters */
	144	#define MP_TX_AGGR_BUF_RESET(a) do { \
	145	a->mpa_tx.pkt_cnt = 0; \
	146	a->mpa_tx.buf_len = 0; \
	147	a->mpa_tx.ports = 0; \
	148	a->mpa_tx.start_port = 0; \
da951c24	149	} while (0)
5e6e3a92 BZ	150
	151	/* SDIO Rx aggregation limit ? */
	152	#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
	153	(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
	154
5e6e3a92 BZ	155	/* SDIO Rx aggregation in progress ? */
	156	#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
	157
	158	/* SDIO Rx aggregation buffer room for next packet ? */
	159	#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
	160	((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
	161
5e6e3a92 BZ	162	/* Reset SDIO Rx aggregation buffer parameters */
	163	#define MP_RX_AGGR_BUF_RESET(a) do { \
	164	a->mpa_rx.pkt_cnt = 0; \
	165	a->mpa_rx.buf_len = 0; \
	166	a->mpa_rx.ports = 0; \
	167	a->mpa_rx.start_port = 0; \
da951c24	168	} while (0)
5e6e3a92	169
5e6e3a92 BZ	170	/* data structure for SDIO MPA TX */
	171	struct mwifiex_sdio_mpa_tx {
	172	/* multiport tx aggregation buffer pointer */
	173	u8 *buf;
	174	u32 buf_len;
	175	u32 pkt_cnt;
5ac253d5	176	u32 ports;
5e6e3a92 BZ	177	u16 start_port;
	178	u8 enabled;
	179	u32 buf_size;
	180	u32 pkt_aggr_limit;
	181	};
	182
	183	struct mwifiex_sdio_mpa_rx {
	184	u8 *buf;
	185	u32 buf_len;
	186	u32 pkt_cnt;
5ac253d5	187	u32 ports;
5e6e3a92 BZ	188	u16 start_port;
5e6e3a92 BZ	189
c23b7c8f AK	190	struct sk_buff **skb_arr;
c23b7c8f AK	191	u32 *len_arr;
5e6e3a92 BZ	192
	193	u8 enabled;
	194	u32 buf_size;
	195	u32 pkt_aggr_limit;
	196	};
	197
	198	int mwifiex_bus_register(void);
	199	void mwifiex_bus_unregister(void);
	200
05889f82 AK	201	struct mwifiex_sdio_card_reg {
	202	u8 start_rd_port;
	203	u8 start_wr_port;
	204	u8 base_0_reg;
	205	u8 base_1_reg;
	206	u8 poll_reg;
	207	u8 host_int_enable;
	208	u8 status_reg_0;
	209	u8 status_reg_1;
	210	u8 sdio_int_mask;
	211	u32 data_port_mask;
	212	u8 max_mp_regs;
	213	u8 rd_bitmap_l;
	214	u8 rd_bitmap_u;
b60186f8 YAP	215	u8 rd_bitmap_1l;
b60186f8 YAP	216	u8 rd_bitmap_1u;
05889f82 AK	217	u8 wr_bitmap_l;
05889f82 AK	218	u8 wr_bitmap_u;
b60186f8 YAP	219	u8 wr_bitmap_1l;
b60186f8 YAP	220	u8 wr_bitmap_1u;
05889f82 AK	221	u8 rd_len_p0_l;
	222	u8 rd_len_p0_u;
	223	u8 card_misc_cfg_reg;
	224	};
	225
5e6e3a92 BZ	226	struct sdio_mmc_card {
	227	struct sdio_func *func;
	228	struct mwifiex_adapter *adapter;
	229
05889f82 AK	230	const char *firmware;
	231	const struct mwifiex_sdio_card_reg *reg;
	232	u8 max_ports;
	233	u8 mp_agg_pkt_limit;
b60186f8 YAP	234	bool supports_sdio_new_mode;
b60186f8 YAP	235	bool has_control_mask;
05889f82	236
5ac253d5 AK	237	u32 mp_rd_bitmap;
5ac253d5 AK	238	u32 mp_wr_bitmap;
5e6e3a92 BZ	239
5e6e3a92 BZ	240	u16 mp_end_port;
5ac253d5	241	u32 mp_data_port_mask;
5e6e3a92 BZ	242
	243	u8 curr_rd_port;
	244	u8 curr_wr_port;
	245
	246	u8 *mp_regs;
	247
	248	struct mwifiex_sdio_mpa_tx mpa_tx;
	249	struct mwifiex_sdio_mpa_rx mpa_rx;
	250	};
d930faee	251
05889f82 AK	252	struct mwifiex_sdio_device {
	253	const char *firmware;
	254	const struct mwifiex_sdio_card_reg *reg;
	255	u8 max_ports;
	256	u8 mp_agg_pkt_limit;
b60186f8 YAP	257	bool supports_sdio_new_mode;
b60186f8 YAP	258	bool has_control_mask;
05889f82 AK	259	};
	260
	261	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	262	.start_rd_port = 1,
	263	.start_wr_port = 1,
	264	.base_0_reg = 0x0040,
	265	.base_1_reg = 0x0041,
	266	.poll_reg = 0x30,
	267	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK,
	268	.status_reg_0 = 0x60,
	269	.status_reg_1 = 0x61,
	270	.sdio_int_mask = 0x3f,
	271	.data_port_mask = 0x0000fffe,
	272	.max_mp_regs = 64,
	273	.rd_bitmap_l = 0x04,
	274	.rd_bitmap_u = 0x05,
	275	.wr_bitmap_l = 0x06,
	276	.wr_bitmap_u = 0x07,
	277	.rd_len_p0_l = 0x08,
	278	.rd_len_p0_u = 0x09,
	279	.card_misc_cfg_reg = 0x6c,
	280	};
	281
b60186f8 YAP	282	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
	283	.start_rd_port = 0,
	284	.start_wr_port = 0,
	285	.base_0_reg = 0x60,
	286	.base_1_reg = 0x61,
	287	.poll_reg = 0x50,
	288	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK \|
	289	CMD_PORT_UPLD_INT_MASK \| CMD_PORT_DNLD_INT_MASK,
	290	.status_reg_0 = 0xc0,
	291	.status_reg_1 = 0xc1,
	292	.sdio_int_mask = 0xff,
	293	.data_port_mask = 0xffffffff,
	294	.max_mp_regs = 184,
	295	.rd_bitmap_l = 0x04,
	296	.rd_bitmap_u = 0x05,
	297	.rd_bitmap_1l = 0x06,
	298	.rd_bitmap_1u = 0x07,
	299	.wr_bitmap_l = 0x08,
	300	.wr_bitmap_u = 0x09,
	301	.wr_bitmap_1l = 0x0a,
	302	.wr_bitmap_1u = 0x0b,
	303	.rd_len_p0_l = 0x0c,
	304	.rd_len_p0_u = 0x0d,
	305	.card_misc_cfg_reg = 0xcc,
	306	};
	307
05889f82 AK	308	static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	309	.firmware = SD8786_DEFAULT_FW_NAME,
	310	.reg = &mwifiex_reg_sd87xx,
	311	.max_ports = 16,
	312	.mp_agg_pkt_limit = 8,
b60186f8 YAP	313	.supports_sdio_new_mode = false,
b60186f8 YAP	314	.has_control_mask = true,
05889f82 AK	315	};
	316
	317	static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	318	.firmware = SD8787_DEFAULT_FW_NAME,
	319	.reg = &mwifiex_reg_sd87xx,
	320	.max_ports = 16,
	321	.mp_agg_pkt_limit = 8,
b60186f8 YAP	322	.supports_sdio_new_mode = false,
b60186f8 YAP	323	.has_control_mask = true,
05889f82 AK	324	};
	325
	326	static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	327	.firmware = SD8797_DEFAULT_FW_NAME,
	328	.reg = &mwifiex_reg_sd87xx,
	329	.max_ports = 16,
	330	.mp_agg_pkt_limit = 8,
b60186f8 YAP	331	.supports_sdio_new_mode = false,
	332	.has_control_mask = true,
	333	};
	334
	335	static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
	336	.firmware = SD8897_DEFAULT_FW_NAME,
	337	.reg = &mwifiex_reg_sd8897,
	338	.max_ports = 32,
	339	.mp_agg_pkt_limit = 16,
	340	.supports_sdio_new_mode = true,
	341	.has_control_mask = false,
05889f82 AK	342	};
05889f82 AK	343
d930faee AK	344	/*
	345	* .cmdrsp_complete handler
	346	*/
	347	static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
	348	struct sk_buff *skb)
	349	{
	350	dev_kfree_skb_any(skb);
	351	return 0;
	352	}
	353
	354	/*
	355	* .event_complete handler
	356	*/
	357	static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
	358	struct sk_buff *skb)
	359	{
	360	dev_kfree_skb_any(skb);
	361	return 0;
	362	}
	363
c23b7c8f AK	364	static inline bool
	365	mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
	366	{
	367	u8 tmp;
	368
	369	if (card->curr_rd_port < card->mpa_rx.start_port) {
b60186f8 YAP	370	if (card->supports_sdio_new_mode)
	371	tmp = card->mp_end_port >> 1;
	372	else
	373	tmp = card->mp_agg_pkt_limit;
c23b7c8f AK	374
	375	if (((card->max_ports - card->mpa_rx.start_port) +
	376	card->curr_rd_port) >= tmp)
	377	return true;
	378	}
	379
b60186f8 YAP	380	if (!card->supports_sdio_new_mode)
	381	return false;
	382
	383	if ((card->curr_rd_port - card->mpa_rx.start_port) >=
	384	(card->mp_end_port >> 1))
	385	return true;
	386
c23b7c8f AK	387	return false;
	388	}
	389
	390	static inline bool
	391	mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
	392	{
	393	u16 tmp;
	394
	395	if (card->curr_wr_port < card->mpa_tx.start_port) {
b60186f8 YAP	396	if (card->supports_sdio_new_mode)
	397	tmp = card->mp_end_port >> 1;
	398	else
	399	tmp = card->mp_agg_pkt_limit;
c23b7c8f AK	400
	401	if (((card->max_ports - card->mpa_tx.start_port) +
	402	card->curr_wr_port) >= tmp)
	403	return true;
	404	}
	405
b60186f8 YAP	406	if (!card->supports_sdio_new_mode)
	407	return false;
	408
	409	if ((card->curr_wr_port - card->mpa_tx.start_port) >=
	410	(card->mp_end_port >> 1))
	411	return true;
	412
c23b7c8f AK	413	return false;
	414	}
	415
	416	/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
	417	static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
	418	struct sk_buff *skb, u8 port)
	419	{
	420	card->mpa_rx.buf_len += skb->len;
	421
	422	if (!card->mpa_rx.pkt_cnt)
	423	card->mpa_rx.start_port = port;
	424
b60186f8 YAP	425	if (card->supports_sdio_new_mode) {
	426	card->mpa_rx.ports \|= (1 << port);
	427	} else {
	428	if (card->mpa_rx.start_port <= port)
	429	card->mpa_rx.ports \|= 1 << (card->mpa_rx.pkt_cnt);
	430	else
	431	card->mpa_rx.ports \|= 1 << (card->mpa_rx.pkt_cnt + 1);
	432	}
c23b7c8f AK	433	card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
	434	card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
	435	card->mpa_rx.pkt_cnt++;
	436	}
5e6e3a92	437	#endif /* _MWIFIEX_SDIO_H */