[deliverable/linux.git] / drivers / net / wireless / mwifiex / sdio.h

/*
 * Marvell Wireless LAN device driver: SDIO specific definitions
 *
 * Copyright (C) 2011, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_SDIO_H
#define	_MWIFIEX_SDIO_H


#include <linux/mmc/sdio.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>

#include "main.h"

#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"

#define BLOCK_MODE	1
#define BYTE_MODE	0

#define REG_PORT			0

#define MWIFIEX_SDIO_IO_PORT_MASK		0xfffff

#define MWIFIEX_SDIO_BYTE_MODE_MASK	0x80000000

#define SDIO_MPA_ADDR_BASE		0x1000
#define CTRL_PORT			0
#define CTRL_PORT_MASK			0x0001

#define CMD_PORT_UPLD_INT_MASK		(0x1U<<6)
#define CMD_PORT_DNLD_INT_MASK		(0x1U<<7)
#define HOST_TERM_CMD53			(0x1U << 2)
#define REG_PORT			0
#define MEM_PORT			0x10000
#define CMD_RD_LEN_0			0xB4
#define CMD_RD_LEN_1			0xB5
#define CARD_CONFIG_2_1_REG             0xCD
#define CMD53_NEW_MODE			(0x1U << 0)
#define CMD_CONFIG_0			0xB8
#define CMD_PORT_RD_LEN_EN		(0x1U << 2)
#define CMD_CONFIG_1			0xB9
#define CMD_PORT_AUTO_EN		(0x1U << 0)
#define CMD_PORT_SLCT			0x8000
#define UP_LD_CMD_PORT_HOST_INT_STATUS	(0x40U)
#define DN_LD_CMD_PORT_HOST_INT_STATUS	(0x80U)

#define MWIFIEX_MP_AGGR_BUF_SIZE_16K	(16384)
#define MWIFIEX_MP_AGGR_BUF_SIZE_32K	(32768)

/* Misc. Config Register : Auto Re-enable interrupts */
#define AUTO_RE_ENABLE_INT              BIT(4)

/* Host Control Registers */
/* Host Control Registers : I/O port 0 */
#define IO_PORT_0_REG			0x78
/* Host Control Registers : I/O port 1 */
#define IO_PORT_1_REG			0x79
/* Host Control Registers : I/O port 2 */
#define IO_PORT_2_REG			0x7A

/* Host Control Registers : Configuration */
#define CONFIGURATION_REG		0x00
/* Host Control Registers : Host power up */
#define HOST_POWER_UP			(0x1U << 1)

/* Host Control Registers : Host interrupt mask */
#define HOST_INT_MASK_REG		0x02
/* Host Control Registers : Upload host interrupt mask */
#define UP_LD_HOST_INT_MASK		(0x1U)
/* Host Control Registers : Download host interrupt mask */
#define DN_LD_HOST_INT_MASK		(0x2U)

/* Host Control Registers : Host interrupt status */
#define HOST_INTSTATUS_REG		0x03
/* Host Control Registers : Upload host interrupt status */
#define UP_LD_HOST_INT_STATUS		(0x1U)
/* Host Control Registers : Download host interrupt status */
#define DN_LD_HOST_INT_STATUS		(0x2U)

/* Host Control Registers : Host interrupt RSR */
#define HOST_INT_RSR_REG		0x01

/* Host Control Registers : Host interrupt status */
#define HOST_INT_STATUS_REG		0x28

/* Card Control Registers : Card I/O ready */
#define CARD_IO_READY                   (0x1U << 3)
/* Card Control Registers : Download card ready */
#define DN_LD_CARD_RDY                  (0x1U << 0)

/* Max retry number of CMD53 write */
#define MAX_WRITE_IOMEM_RETRY		2

/* SDIO Tx aggregation in progress ? */
#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)

/* SDIO Tx aggregation buffer room for next packet ? */
#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)	\
						<= a->mpa_tx.buf_size)

/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {		\
	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],			\
			payload, pkt_len);				\
	a->mpa_tx.buf_len += pkt_len;					\
	if (!a->mpa_tx.pkt_cnt)						\
		a->mpa_tx.start_port = port;				\
	if (a->mpa_tx.start_port <= port)				\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));		\
	else								\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+		\
						(a->max_ports -	\
						a->mp_end_port)));	\
	a->mpa_tx.pkt_cnt++;						\
} while (0)

/* SDIO Tx aggregation limit ? */
#define MP_TX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)

/* Reset SDIO Tx aggregation buffer parameters */
#define MP_TX_AGGR_BUF_RESET(a) do {					\
	a->mpa_tx.pkt_cnt = 0;						\
	a->mpa_tx.buf_len = 0;						\
	a->mpa_tx.ports = 0;						\
	a->mpa_tx.start_port = 0;					\
} while (0)

/* SDIO Rx aggregation limit ? */
#define MP_RX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)

/* SDIO Rx aggregation in progress ? */
#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)

/* SDIO Rx aggregation buffer room for next packet ? */
#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)				\
			((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)

/* Reset SDIO Rx aggregation buffer parameters */
#define MP_RX_AGGR_BUF_RESET(a) do {					\
	a->mpa_rx.pkt_cnt = 0;						\
	a->mpa_rx.buf_len = 0;						\
	a->mpa_rx.ports = 0;						\
	a->mpa_rx.start_port = 0;					\
} while (0)

/* data structure for SDIO MPA TX */
struct mwifiex_sdio_mpa_tx {
	/* multiport tx aggregation buffer pointer */
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;
	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

struct mwifiex_sdio_mpa_rx {
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;

	struct sk_buff **skb_arr;
	u32 *len_arr;

	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

int mwifiex_bus_register(void);
void mwifiex_bus_unregister(void);

struct mwifiex_sdio_card_reg {
	u8 start_rd_port;
	u8 start_wr_port;
	u8 base_0_reg;
	u8 base_1_reg;
	u8 poll_reg;
	u8 host_int_enable;
	u8 status_reg_0;
	u8 status_reg_1;
	u8 sdio_int_mask;
	u32 data_port_mask;
	u8 max_mp_regs;
	u8 rd_bitmap_l;
	u8 rd_bitmap_u;
	u8 rd_bitmap_1l;
	u8 rd_bitmap_1u;
	u8 wr_bitmap_l;
	u8 wr_bitmap_u;
	u8 wr_bitmap_1l;
	u8 wr_bitmap_1u;
	u8 rd_len_p0_l;
	u8 rd_len_p0_u;
	u8 card_misc_cfg_reg;
};

struct sdio_mmc_card {
	struct sdio_func *func;
	struct mwifiex_adapter *adapter;

	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;
	bool supports_sdio_new_mode;
	bool has_control_mask;
	u16 tx_buf_size;
	u32 mp_tx_agg_buf_size;
	u32 mp_rx_agg_buf_size;

	u32 mp_rd_bitmap;
	u32 mp_wr_bitmap;

	u16 mp_end_port;
	u32 mp_data_port_mask;

	u8 curr_rd_port;
	u8 curr_wr_port;

	u8 *mp_regs;

	struct mwifiex_sdio_mpa_tx mpa_tx;
	struct mwifiex_sdio_mpa_rx mpa_rx;
};

struct mwifiex_sdio_device {
	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;
	bool supports_sdio_new_mode;
	bool has_control_mask;
	u16 tx_buf_size;
	u32 mp_tx_agg_buf_size;
	u32 mp_rx_agg_buf_size;
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	.start_rd_port = 1,
	.start_wr_port = 1,
	.base_0_reg = 0x0040,
	.base_1_reg = 0x0041,
	.poll_reg = 0x30,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
	.status_reg_0 = 0x60,
	.status_reg_1 = 0x61,
	.sdio_int_mask = 0x3f,
	.data_port_mask = 0x0000fffe,
	.max_mp_regs = 64,
	.rd_bitmap_l = 0x04,
	.rd_bitmap_u = 0x05,
	.wr_bitmap_l = 0x06,
	.wr_bitmap_u = 0x07,
	.rd_len_p0_l = 0x08,
	.rd_len_p0_u = 0x09,
	.card_misc_cfg_reg = 0x6c,
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
	.start_rd_port = 0,
	.start_wr_port = 0,
	.base_0_reg = 0x60,
	.base_1_reg = 0x61,
	.poll_reg = 0x50,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK |
			CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK,
	.status_reg_0 = 0xc0,
	.status_reg_1 = 0xc1,
	.sdio_int_mask = 0xff,
	.data_port_mask = 0xffffffff,
	.max_mp_regs = 184,
	.rd_bitmap_l = 0x04,
	.rd_bitmap_u = 0x05,
	.rd_bitmap_1l = 0x06,
	.rd_bitmap_1u = 0x07,
	.wr_bitmap_l = 0x08,
	.wr_bitmap_u = 0x09,
	.wr_bitmap_1l = 0x0a,
	.wr_bitmap_1u = 0x0b,
	.rd_len_p0_l = 0x0c,
	.rd_len_p0_u = 0x0d,
	.card_misc_cfg_reg = 0xcc,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	.firmware = SD8786_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	.firmware = SD8787_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	.firmware = SD8797_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
	.supports_sdio_new_mode = false,
	.has_control_mask = true,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
	.firmware = SD8897_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd8897,
	.max_ports = 32,
	.mp_agg_pkt_limit = 16,
	.supports_sdio_new_mode = true,
	.has_control_mask = false,
	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
};

/*
 * .cmdrsp_complete handler
 */
static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
					       struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

/*
 * .event_complete handler
 */
static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
					      struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

static inline bool
mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
{
	u8 tmp;

	if (card->curr_rd_port < card->mpa_rx.start_port) {
		if (card->supports_sdio_new_mode)
			tmp = card->mp_end_port >> 1;
		else
			tmp = card->mp_agg_pkt_limit;

		if (((card->max_ports - card->mpa_rx.start_port) +
		    card->curr_rd_port) >= tmp)
			return true;
	}

	if (!card->supports_sdio_new_mode)
		return false;

	if ((card->curr_rd_port - card->mpa_rx.start_port) >=
	    (card->mp_end_port >> 1))
		return true;

	return false;
}

static inline bool
mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
{
	u16 tmp;

	if (card->curr_wr_port < card->mpa_tx.start_port) {
		if (card->supports_sdio_new_mode)
			tmp = card->mp_end_port >> 1;
		else
			tmp = card->mp_agg_pkt_limit;

		if (((card->max_ports - card->mpa_tx.start_port) +
		    card->curr_wr_port) >= tmp)
			return true;
	}

	if (!card->supports_sdio_new_mode)
		return false;

	if ((card->curr_wr_port - card->mpa_tx.start_port) >=
	    (card->mp_end_port >> 1))
		return true;

	return false;
}

/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
				    struct sk_buff *skb, u8 port)
{
	card->mpa_rx.buf_len += skb->len;

	if (!card->mpa_rx.pkt_cnt)
		card->mpa_rx.start_port = port;

	if (card->supports_sdio_new_mode) {
		card->mpa_rx.ports |= (1 << port);
	} else {
		if (card->mpa_rx.start_port <= port)
			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt);
		else
			card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1);
	}
	card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
	card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
	card->mpa_rx.pkt_cnt++;
}
#endif /* _MWIFIEX_SDIO_H */
Commit	Line	Data
5e6e3a92 BZ	1	/*
	2	* Marvell Wireless LAN device driver: SDIO specific definitions
	3	*
	4	* Copyright (C) 2011, Marvell International Ltd.
	5	*
	6	* This software file (the "File") is distributed by Marvell International
	7	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	8	* (the "License"). You may use, redistribute and/or modify this File in
	9	* accordance with the terms and conditions of the License, a copy of which
	10	* is available by writing to the Free Software Foundation, Inc.,
	11	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	12	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	13	*
	14	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	15	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	16	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	17	* this warranty disclaimer.
	18	*/
	19
	20	#ifndef _MWIFIEX_SDIO_H
	21	#define _MWIFIEX_SDIO_H
	22
	23
	24	#include <linux/mmc/sdio.h>
	25	#include <linux/mmc/sdio_ids.h>
	26	#include <linux/mmc/sdio_func.h>
	27	#include <linux/mmc/card.h>
d31ab357	28	#include <linux/mmc/host.h>
5e6e3a92 BZ	29
	30	#include "main.h"
	31
98e6b9df	32	#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
4a7f5db1	33	#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
e3bea1c8	34	#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
b60186f8	35	#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin"
4a7f5db1	36
5e6e3a92 BZ	37	#define BLOCK_MODE 1
	38	#define BYTE_MODE 0
	39
	40	#define REG_PORT 0
5e6e3a92 BZ	41
	42	#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
	43
	44	#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
	45
248eb4c6	46	#define SDIO_MPA_ADDR_BASE 0x1000
5e6e3a92 BZ	47	#define CTRL_PORT 0
5e6e3a92 BZ	48	#define CTRL_PORT_MASK 0x0001
5e6e3a92	49
b60186f8 YAP	50	#define CMD_PORT_UPLD_INT_MASK (0x1U<<6)
	51	#define CMD_PORT_DNLD_INT_MASK (0x1U<<7)
	52	#define HOST_TERM_CMD53 (0x1U << 2)
	53	#define REG_PORT 0
	54	#define MEM_PORT 0x10000
	55	#define CMD_RD_LEN_0 0xB4
	56	#define CMD_RD_LEN_1 0xB5
	57	#define CARD_CONFIG_2_1_REG 0xCD
	58	#define CMD53_NEW_MODE (0x1U << 0)
	59	#define CMD_CONFIG_0 0xB8
	60	#define CMD_PORT_RD_LEN_EN (0x1U << 2)
	61	#define CMD_CONFIG_1 0xB9
	62	#define CMD_PORT_AUTO_EN (0x1U << 0)
	63	#define CMD_PORT_SLCT 0x8000
	64	#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U)
	65	#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U)
	66
e1aa93a4 AK	67	#define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384)
e1aa93a4 AK	68	#define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768)
5e6e3a92 BZ	69
	70	/* Misc. Config Register : Auto Re-enable interrupts */
	71	#define AUTO_RE_ENABLE_INT BIT(4)
	72
	73	/* Host Control Registers */
	74	/* Host Control Registers : I/O port 0 */
	75	#define IO_PORT_0_REG 0x78
	76	/* Host Control Registers : I/O port 1 */
	77	#define IO_PORT_1_REG 0x79
	78	/* Host Control Registers : I/O port 2 */
	79	#define IO_PORT_2_REG 0x7A
	80
	81	/* Host Control Registers : Configuration */
	82	#define CONFIGURATION_REG 0x00
5e6e3a92 BZ	83	/* Host Control Registers : Host power up */
5e6e3a92 BZ	84	#define HOST_POWER_UP (0x1U << 1)
5e6e3a92 BZ	85
	86	/* Host Control Registers : Host interrupt mask */
	87	#define HOST_INT_MASK_REG 0x02
	88	/* Host Control Registers : Upload host interrupt mask */
	89	#define UP_LD_HOST_INT_MASK (0x1U)
	90	/* Host Control Registers : Download host interrupt mask */
	91	#define DN_LD_HOST_INT_MASK (0x2U)
b60186f8	92
5e6e3a92 BZ	93	/* Host Control Registers : Host interrupt status */
	94	#define HOST_INTSTATUS_REG 0x03
	95	/* Host Control Registers : Upload host interrupt status */
	96	#define UP_LD_HOST_INT_STATUS (0x1U)
	97	/* Host Control Registers : Download host interrupt status */
	98	#define DN_LD_HOST_INT_STATUS (0x2U)
	99
	100	/* Host Control Registers : Host interrupt RSR */
	101	#define HOST_INT_RSR_REG 0x01
5e6e3a92 BZ	102
	103	/* Host Control Registers : Host interrupt status */
	104	#define HOST_INT_STATUS_REG 0x28
5e6e3a92	105
5e6e3a92 BZ	106	/* Card Control Registers : Card I/O ready */
5e6e3a92 BZ	107	#define CARD_IO_READY (0x1U << 3)
5e6e3a92 BZ	108	/* Card Control Registers : Download card ready */
	109	#define DN_LD_CARD_RDY (0x1U << 0)
	110
5e6e3a92 BZ	111	/* Max retry number of CMD53 write */
	112	#define MAX_WRITE_IOMEM_RETRY 2
	113
	114	/* SDIO Tx aggregation in progress ? */
	115	#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
	116
	117	/* SDIO Tx aggregation buffer room for next packet ? */
	118	#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
	119	<= a->mpa_tx.buf_size)
	120
	121	/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
	122	#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
	123	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
	124	payload, pkt_len); \
	125	a->mpa_tx.buf_len += pkt_len; \
	126	if (!a->mpa_tx.pkt_cnt) \
	127	a->mpa_tx.start_port = port; \
	128	if (a->mpa_tx.start_port <= port) \
	129	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt)); \
	130	else \
05889f82 AK	131	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt+1+ \
05889f82 AK	132	(a->max_ports - \
5e6e3a92 BZ	133	a->mp_end_port))); \
5e6e3a92 BZ	134	a->mpa_tx.pkt_cnt++; \
da951c24	135	} while (0)
5e6e3a92 BZ	136
	137	/* SDIO Tx aggregation limit ? */
	138	#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
	139	(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
	140
5e6e3a92 BZ	141	/* Reset SDIO Tx aggregation buffer parameters */
	142	#define MP_TX_AGGR_BUF_RESET(a) do { \
	143	a->mpa_tx.pkt_cnt = 0; \
	144	a->mpa_tx.buf_len = 0; \
	145	a->mpa_tx.ports = 0; \
	146	a->mpa_tx.start_port = 0; \
da951c24	147	} while (0)
5e6e3a92 BZ	148
	149	/* SDIO Rx aggregation limit ? */
	150	#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
	151	(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
	152
5e6e3a92 BZ	153	/* SDIO Rx aggregation in progress ? */
	154	#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
	155
	156	/* SDIO Rx aggregation buffer room for next packet ? */
	157	#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
	158	((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
	159
5e6e3a92 BZ	160	/* Reset SDIO Rx aggregation buffer parameters */
	161	#define MP_RX_AGGR_BUF_RESET(a) do { \
	162	a->mpa_rx.pkt_cnt = 0; \
	163	a->mpa_rx.buf_len = 0; \
	164	a->mpa_rx.ports = 0; \
	165	a->mpa_rx.start_port = 0; \
da951c24	166	} while (0)
5e6e3a92	167
5e6e3a92 BZ	168	/* data structure for SDIO MPA TX */
	169	struct mwifiex_sdio_mpa_tx {
	170	/* multiport tx aggregation buffer pointer */
	171	u8 *buf;
	172	u32 buf_len;
	173	u32 pkt_cnt;
5ac253d5	174	u32 ports;
5e6e3a92 BZ	175	u16 start_port;
	176	u8 enabled;
	177	u32 buf_size;
	178	u32 pkt_aggr_limit;
	179	};
	180
	181	struct mwifiex_sdio_mpa_rx {
	182	u8 *buf;
	183	u32 buf_len;
	184	u32 pkt_cnt;
5ac253d5	185	u32 ports;
5e6e3a92 BZ	186	u16 start_port;
5e6e3a92 BZ	187
c23b7c8f AK	188	struct sk_buff **skb_arr;
c23b7c8f AK	189	u32 *len_arr;
5e6e3a92 BZ	190
	191	u8 enabled;
	192	u32 buf_size;
	193	u32 pkt_aggr_limit;
	194	};
	195
	196	int mwifiex_bus_register(void);
	197	void mwifiex_bus_unregister(void);
	198
05889f82 AK	199	struct mwifiex_sdio_card_reg {
	200	u8 start_rd_port;
	201	u8 start_wr_port;
	202	u8 base_0_reg;
	203	u8 base_1_reg;
	204	u8 poll_reg;
	205	u8 host_int_enable;
	206	u8 status_reg_0;
	207	u8 status_reg_1;
	208	u8 sdio_int_mask;
	209	u32 data_port_mask;
	210	u8 max_mp_regs;
	211	u8 rd_bitmap_l;
	212	u8 rd_bitmap_u;
b60186f8 YAP	213	u8 rd_bitmap_1l;
b60186f8 YAP	214	u8 rd_bitmap_1u;
05889f82 AK	215	u8 wr_bitmap_l;
05889f82 AK	216	u8 wr_bitmap_u;
b60186f8 YAP	217	u8 wr_bitmap_1l;
b60186f8 YAP	218	u8 wr_bitmap_1u;
05889f82 AK	219	u8 rd_len_p0_l;
	220	u8 rd_len_p0_u;
	221	u8 card_misc_cfg_reg;
	222	};
	223
5e6e3a92 BZ	224	struct sdio_mmc_card {
	225	struct sdio_func *func;
	226	struct mwifiex_adapter *adapter;
	227
05889f82 AK	228	const char *firmware;
	229	const struct mwifiex_sdio_card_reg *reg;
	230	u8 max_ports;
	231	u8 mp_agg_pkt_limit;
b60186f8 YAP	232	bool supports_sdio_new_mode;
b60186f8 YAP	233	bool has_control_mask;
828cf222	234	u16 tx_buf_size;
e1aa93a4 AK	235	u32 mp_tx_agg_buf_size;
e1aa93a4 AK	236	u32 mp_rx_agg_buf_size;
05889f82	237
5ac253d5 AK	238	u32 mp_rd_bitmap;
5ac253d5 AK	239	u32 mp_wr_bitmap;
5e6e3a92 BZ	240
5e6e3a92 BZ	241	u16 mp_end_port;
5ac253d5	242	u32 mp_data_port_mask;
5e6e3a92 BZ	243
	244	u8 curr_rd_port;
	245	u8 curr_wr_port;
	246
	247	u8 *mp_regs;
	248
	249	struct mwifiex_sdio_mpa_tx mpa_tx;
	250	struct mwifiex_sdio_mpa_rx mpa_rx;
	251	};
d930faee	252
05889f82 AK	253	struct mwifiex_sdio_device {
	254	const char *firmware;
	255	const struct mwifiex_sdio_card_reg *reg;
	256	u8 max_ports;
	257	u8 mp_agg_pkt_limit;
b60186f8 YAP	258	bool supports_sdio_new_mode;
b60186f8 YAP	259	bool has_control_mask;
828cf222	260	u16 tx_buf_size;
e1aa93a4 AK	261	u32 mp_tx_agg_buf_size;
e1aa93a4 AK	262	u32 mp_rx_agg_buf_size;
05889f82 AK	263	};
	264
	265	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	266	.start_rd_port = 1,
	267	.start_wr_port = 1,
	268	.base_0_reg = 0x0040,
	269	.base_1_reg = 0x0041,
	270	.poll_reg = 0x30,
	271	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK,
	272	.status_reg_0 = 0x60,
	273	.status_reg_1 = 0x61,
	274	.sdio_int_mask = 0x3f,
	275	.data_port_mask = 0x0000fffe,
	276	.max_mp_regs = 64,
	277	.rd_bitmap_l = 0x04,
	278	.rd_bitmap_u = 0x05,
	279	.wr_bitmap_l = 0x06,
	280	.wr_bitmap_u = 0x07,
	281	.rd_len_p0_l = 0x08,
	282	.rd_len_p0_u = 0x09,
	283	.card_misc_cfg_reg = 0x6c,
	284	};
	285
b60186f8 YAP	286	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = {
	287	.start_rd_port = 0,
	288	.start_wr_port = 0,
	289	.base_0_reg = 0x60,
	290	.base_1_reg = 0x61,
	291	.poll_reg = 0x50,
	292	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK \|
	293	CMD_PORT_UPLD_INT_MASK \| CMD_PORT_DNLD_INT_MASK,
	294	.status_reg_0 = 0xc0,
	295	.status_reg_1 = 0xc1,
	296	.sdio_int_mask = 0xff,
	297	.data_port_mask = 0xffffffff,
	298	.max_mp_regs = 184,
	299	.rd_bitmap_l = 0x04,
	300	.rd_bitmap_u = 0x05,
	301	.rd_bitmap_1l = 0x06,
	302	.rd_bitmap_1u = 0x07,
	303	.wr_bitmap_l = 0x08,
	304	.wr_bitmap_u = 0x09,
	305	.wr_bitmap_1l = 0x0a,
	306	.wr_bitmap_1u = 0x0b,
	307	.rd_len_p0_l = 0x0c,
	308	.rd_len_p0_u = 0x0d,
	309	.card_misc_cfg_reg = 0xcc,
	310	};
	311
05889f82 AK	312	static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	313	.firmware = SD8786_DEFAULT_FW_NAME,
	314	.reg = &mwifiex_reg_sd87xx,
	315	.max_ports = 16,
	316	.mp_agg_pkt_limit = 8,
b60186f8 YAP	317	.supports_sdio_new_mode = false,
b60186f8 YAP	318	.has_control_mask = true,
828cf222	319	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4 AK	320	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
e1aa93a4 AK	321	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
05889f82 AK	322	};
	323
	324	static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	325	.firmware = SD8787_DEFAULT_FW_NAME,
	326	.reg = &mwifiex_reg_sd87xx,
	327	.max_ports = 16,
	328	.mp_agg_pkt_limit = 8,
b60186f8 YAP	329	.supports_sdio_new_mode = false,
b60186f8 YAP	330	.has_control_mask = true,
828cf222	331	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4 AK	332	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
e1aa93a4 AK	333	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
05889f82 AK	334	};
	335
	336	static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	337	.firmware = SD8797_DEFAULT_FW_NAME,
	338	.reg = &mwifiex_reg_sd87xx,
	339	.max_ports = 16,
	340	.mp_agg_pkt_limit = 8,
b60186f8 YAP	341	.supports_sdio_new_mode = false,
b60186f8 YAP	342	.has_control_mask = true,
828cf222	343	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K,
e1aa93a4 AK	344	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
e1aa93a4 AK	345	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K,
b60186f8 YAP	346	};
	347
	348	static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = {
	349	.firmware = SD8897_DEFAULT_FW_NAME,
	350	.reg = &mwifiex_reg_sd8897,
	351	.max_ports = 32,
	352	.mp_agg_pkt_limit = 16,
	353	.supports_sdio_new_mode = true,
	354	.has_control_mask = false,
828cf222	355	.tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K,
e1aa93a4 AK	356	.mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
e1aa93a4 AK	357	.mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K,
05889f82 AK	358	};
05889f82 AK	359
d930faee AK	360	/*
	361	* .cmdrsp_complete handler
	362	*/
	363	static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
	364	struct sk_buff *skb)
	365	{
	366	dev_kfree_skb_any(skb);
	367	return 0;
	368	}
	369
	370	/*
	371	* .event_complete handler
	372	*/
	373	static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
	374	struct sk_buff *skb)
	375	{
	376	dev_kfree_skb_any(skb);
	377	return 0;
	378	}
	379
c23b7c8f AK	380	static inline bool
	381	mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card)
	382	{
	383	u8 tmp;
	384
	385	if (card->curr_rd_port < card->mpa_rx.start_port) {
b60186f8 YAP	386	if (card->supports_sdio_new_mode)
	387	tmp = card->mp_end_port >> 1;
	388	else
	389	tmp = card->mp_agg_pkt_limit;
c23b7c8f AK	390
	391	if (((card->max_ports - card->mpa_rx.start_port) +
	392	card->curr_rd_port) >= tmp)
	393	return true;
	394	}
	395
b60186f8 YAP	396	if (!card->supports_sdio_new_mode)
	397	return false;
	398
	399	if ((card->curr_rd_port - card->mpa_rx.start_port) >=
	400	(card->mp_end_port >> 1))
	401	return true;
	402
c23b7c8f AK	403	return false;
	404	}
	405
	406	static inline bool
	407	mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card)
	408	{
	409	u16 tmp;
	410
	411	if (card->curr_wr_port < card->mpa_tx.start_port) {
b60186f8 YAP	412	if (card->supports_sdio_new_mode)
	413	tmp = card->mp_end_port >> 1;
	414	else
	415	tmp = card->mp_agg_pkt_limit;
c23b7c8f AK	416
	417	if (((card->max_ports - card->mpa_tx.start_port) +
	418	card->curr_wr_port) >= tmp)
	419	return true;
	420	}
	421
b60186f8 YAP	422	if (!card->supports_sdio_new_mode)
	423	return false;
	424
	425	if ((card->curr_wr_port - card->mpa_tx.start_port) >=
	426	(card->mp_end_port >> 1))
	427	return true;
	428
c23b7c8f AK	429	return false;
	430	}
	431
	432	/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
	433	static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card,
	434	struct sk_buff *skb, u8 port)
	435	{
	436	card->mpa_rx.buf_len += skb->len;
	437
	438	if (!card->mpa_rx.pkt_cnt)
	439	card->mpa_rx.start_port = port;
	440
b60186f8 YAP	441	if (card->supports_sdio_new_mode) {
	442	card->mpa_rx.ports \|= (1 << port);
	443	} else {
	444	if (card->mpa_rx.start_port <= port)
	445	card->mpa_rx.ports \|= 1 << (card->mpa_rx.pkt_cnt);
	446	else
	447	card->mpa_rx.ports \|= 1 << (card->mpa_rx.pkt_cnt + 1);
	448	}
c23b7c8f AK	449	card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb;
	450	card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len;
	451	card->mpa_rx.pkt_cnt++;
	452	}
5e6e3a92	453	#endif /* _MWIFIEX_SDIO_H */