[deliverable/linux.git] / drivers / net / wireless / mwifiex / sdio.h

/*
 * Marvell Wireless LAN device driver: SDIO specific definitions
 *
 * Copyright (C) 2011, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_SDIO_H
#define	_MWIFIEX_SDIO_H


#include <linux/mmc/sdio.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>

#include "main.h"

#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"

#define BLOCK_MODE	1
#define BYTE_MODE	0

#define REG_PORT			0

#define MWIFIEX_SDIO_IO_PORT_MASK		0xfffff

#define MWIFIEX_SDIO_BYTE_MODE_MASK	0x80000000

#define CTRL_PORT			0
#define CTRL_PORT_MASK			0x0001

#define SDIO_MP_AGGR_DEF_PKT_LIMIT		8

#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE        (8192)	/* 8K */

/* Multi port RX aggregation buffer size */
#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE        (16384)	/* 16K */

/* Misc. Config Register : Auto Re-enable interrupts */
#define AUTO_RE_ENABLE_INT              BIT(4)

/* Host Control Registers */
/* Host Control Registers : I/O port 0 */
#define IO_PORT_0_REG			0x78
/* Host Control Registers : I/O port 1 */
#define IO_PORT_1_REG			0x79
/* Host Control Registers : I/O port 2 */
#define IO_PORT_2_REG			0x7A

/* Host Control Registers : Configuration */
#define CONFIGURATION_REG		0x00
/* Host Control Registers : Host without Command 53 finish host*/
#define HOST_TO_CARD_EVENT       (0x1U << 3)
/* Host Control Registers : Host without Command 53 finish host */
#define HOST_WO_CMD53_FINISH_HOST	(0x1U << 2)
/* Host Control Registers : Host power up */
#define HOST_POWER_UP			(0x1U << 1)
/* Host Control Registers : Host power down */
#define HOST_POWER_DOWN			(0x1U << 0)

/* Host Control Registers : Host interrupt mask */
#define HOST_INT_MASK_REG		0x02
/* Host Control Registers : Upload host interrupt mask */
#define UP_LD_HOST_INT_MASK		(0x1U)
/* Host Control Registers : Download host interrupt mask */
#define DN_LD_HOST_INT_MASK		(0x2U)
/* Disable Host interrupt mask */
#define	HOST_INT_DISABLE		0xff

/* Host Control Registers : Host interrupt status */
#define HOST_INTSTATUS_REG		0x03
/* Host Control Registers : Upload host interrupt status */
#define UP_LD_HOST_INT_STATUS		(0x1U)
/* Host Control Registers : Download host interrupt status */
#define DN_LD_HOST_INT_STATUS		(0x2U)

/* Host Control Registers : Host interrupt RSR */
#define HOST_INT_RSR_REG		0x01
/* Host Control Registers : Upload host interrupt RSR */
#define UP_LD_HOST_INT_RSR		(0x1U)

/* Host Control Registers : Host interrupt status */
#define HOST_INT_STATUS_REG		0x28
/* Host Control Registers : Upload CRC error */
#define UP_LD_CRC_ERR			(0x1U << 2)
/* Host Control Registers : Upload restart */
#define UP_LD_RESTART                   (0x1U << 1)
/* Host Control Registers : Download restart */
#define DN_LD_RESTART                   (0x1U << 0)

/* Card Control Registers : Card I/O ready */
#define CARD_IO_READY                   (0x1U << 3)
/* Card Control Registers : CIS card ready */
#define CIS_CARD_RDY                    (0x1U << 2)
/* Card Control Registers : Upload card ready */
#define UP_LD_CARD_RDY                  (0x1U << 1)
/* Card Control Registers : Download card ready */
#define DN_LD_CARD_RDY                  (0x1U << 0)

/* Card Control Registers : Host interrupt mask register */
#define HOST_INTERRUPT_MASK_REG         0x34
/* Card Control Registers : Host power interrupt mask */
#define HOST_POWER_INT_MASK             (0x1U << 3)
/* Card Control Registers : Abort card interrupt mask */
#define ABORT_CARD_INT_MASK             (0x1U << 2)
/* Card Control Registers : Upload card interrupt mask */
#define UP_LD_CARD_INT_MASK             (0x1U << 1)
/* Card Control Registers : Download card interrupt mask */
#define DN_LD_CARD_INT_MASK             (0x1U << 0)

/* Card Control Registers : Card interrupt status register */
#define CARD_INTERRUPT_STATUS_REG       0x38
/* Card Control Registers : Power up interrupt */
#define POWER_UP_INT                    (0x1U << 4)
/* Card Control Registers : Power down interrupt */
#define POWER_DOWN_INT                  (0x1U << 3)

/* Card Control Registers : Card interrupt RSR register */
#define CARD_INTERRUPT_RSR_REG          0x3c
/* Card Control Registers : Power up RSR */
#define POWER_UP_RSR                    (0x1U << 4)
/* Card Control Registers : Power down RSR */
#define POWER_DOWN_RSR                  (0x1U << 3)

/* Host F1 card ready */
#define HOST_F1_CARD_RDY		0x0020

/* Rx length register */
#define CARD_RX_LEN_REG			0x62
/* Rx unit register */
#define CARD_RX_UNIT_REG		0x63

/* Max retry number of CMD53 write */
#define MAX_WRITE_IOMEM_RETRY		2

/* SDIO Tx aggregation in progress ? */
#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)

/* SDIO Tx aggregation buffer room for next packet ? */
#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)	\
						<= a->mpa_tx.buf_size)

/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {		\
	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],			\
			payload, pkt_len);				\
	a->mpa_tx.buf_len += pkt_len;					\
	if (!a->mpa_tx.pkt_cnt)						\
		a->mpa_tx.start_port = port;				\
	if (a->mpa_tx.start_port <= port)				\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));		\
	else								\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+		\
						(a->max_ports -	\
						a->mp_end_port)));	\
	a->mpa_tx.pkt_cnt++;						\
} while (0)

/* SDIO Tx aggregation limit ? */
#define MP_TX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)

/* SDIO Tx aggregation port limit ? */
#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port <		\
			a->mpa_tx.start_port) && (((a->max_ports -\
			a->mpa_tx.start_port) + a->curr_wr_port) >=	\
				a->mp_agg_pkt_limit))

/* Reset SDIO Tx aggregation buffer parameters */
#define MP_TX_AGGR_BUF_RESET(a) do {					\
	a->mpa_tx.pkt_cnt = 0;						\
	a->mpa_tx.buf_len = 0;						\
	a->mpa_tx.ports = 0;						\
	a->mpa_tx.start_port = 0;					\
} while (0)

/* SDIO Rx aggregation limit ? */
#define MP_RX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)

/* SDIO Tx aggregation port limit ? */
#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port <		\
			a->mpa_rx.start_port) && (((a->max_ports -\
			a->mpa_rx.start_port) + a->curr_rd_port) >=	\
			a->mp_agg_pkt_limit))

/* SDIO Rx aggregation in progress ? */
#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)

/* SDIO Rx aggregation buffer room for next packet ? */
#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)				\
			((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)

/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
#define MP_RX_AGGR_SETUP(a, skb, port) do {				\
	a->mpa_rx.buf_len += skb->len;					\
	if (!a->mpa_rx.pkt_cnt)						\
		a->mpa_rx.start_port = port;				\
	if (a->mpa_rx.start_port <= port)				\
		a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt));		\
	else								\
		a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt+1));		\
	a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb;			\
	a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len;		\
	a->mpa_rx.pkt_cnt++;						\
} while (0)

/* Reset SDIO Rx aggregation buffer parameters */
#define MP_RX_AGGR_BUF_RESET(a) do {					\
	a->mpa_rx.pkt_cnt = 0;						\
	a->mpa_rx.buf_len = 0;						\
	a->mpa_rx.ports = 0;						\
	a->mpa_rx.start_port = 0;					\
} while (0)


/* data structure for SDIO MPA TX */
struct mwifiex_sdio_mpa_tx {
	/* multiport tx aggregation buffer pointer */
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;
	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

struct mwifiex_sdio_mpa_rx {
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;

	struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
	u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];

	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

int mwifiex_bus_register(void);
void mwifiex_bus_unregister(void);

struct mwifiex_sdio_card_reg {
	u8 start_rd_port;
	u8 start_wr_port;
	u8 base_0_reg;
	u8 base_1_reg;
	u8 poll_reg;
	u8 host_int_enable;
	u8 status_reg_0;
	u8 status_reg_1;
	u8 sdio_int_mask;
	u32 data_port_mask;
	u8 max_mp_regs;
	u8 rd_bitmap_l;
	u8 rd_bitmap_u;
	u8 wr_bitmap_l;
	u8 wr_bitmap_u;
	u8 rd_len_p0_l;
	u8 rd_len_p0_u;
	u8 card_misc_cfg_reg;
};

struct sdio_mmc_card {
	struct sdio_func *func;
	struct mwifiex_adapter *adapter;

	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;

	u32 mp_rd_bitmap;
	u32 mp_wr_bitmap;

	u16 mp_end_port;
	u32 mp_data_port_mask;

	u8 curr_rd_port;
	u8 curr_wr_port;

	u8 *mp_regs;

	struct mwifiex_sdio_mpa_tx mpa_tx;
	struct mwifiex_sdio_mpa_rx mpa_rx;
};

struct mwifiex_sdio_device {
	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	.start_rd_port = 1,
	.start_wr_port = 1,
	.base_0_reg = 0x0040,
	.base_1_reg = 0x0041,
	.poll_reg = 0x30,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
	.status_reg_0 = 0x60,
	.status_reg_1 = 0x61,
	.sdio_int_mask = 0x3f,
	.data_port_mask = 0x0000fffe,
	.max_mp_regs = 64,
	.rd_bitmap_l = 0x04,
	.rd_bitmap_u = 0x05,
	.wr_bitmap_l = 0x06,
	.wr_bitmap_u = 0x07,
	.rd_len_p0_l = 0x08,
	.rd_len_p0_u = 0x09,
	.card_misc_cfg_reg = 0x6c,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	.firmware = SD8786_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	.firmware = SD8787_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	.firmware = SD8797_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
};

/*
 * .cmdrsp_complete handler
 */
static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
					       struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

/*
 * .event_complete handler
 */
static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
					      struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

#endif /* _MWIFIEX_SDIO_H */
Commit	Line	Data
5e6e3a92 BZ	1	/*
	2	* Marvell Wireless LAN device driver: SDIO specific definitions
	3	*
	4	* Copyright (C) 2011, Marvell International Ltd.
	5	*
	6	* This software file (the "File") is distributed by Marvell International
	7	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	8	* (the "License"). You may use, redistribute and/or modify this File in
	9	* accordance with the terms and conditions of the License, a copy of which
	10	* is available by writing to the Free Software Foundation, Inc.,
	11	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	12	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	13	*
	14	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	15	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	16	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	17	* this warranty disclaimer.
	18	*/
	19
	20	#ifndef _MWIFIEX_SDIO_H
	21	#define _MWIFIEX_SDIO_H
	22
	23
	24	#include <linux/mmc/sdio.h>
	25	#include <linux/mmc/sdio_ids.h>
	26	#include <linux/mmc/sdio_func.h>
	27	#include <linux/mmc/card.h>
d31ab357	28	#include <linux/mmc/host.h>
5e6e3a92 BZ	29
	30	#include "main.h"
	31
98e6b9df	32	#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
4a7f5db1	33	#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
e3bea1c8	34	#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
4a7f5db1	35
5e6e3a92 BZ	36	#define BLOCK_MODE 1
	37	#define BYTE_MODE 0
	38
	39	#define REG_PORT 0
5e6e3a92 BZ	40
	41	#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
	42
	43	#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
	44
	45	#define CTRL_PORT 0
	46	#define CTRL_PORT_MASK 0x0001
5e6e3a92	47
05889f82	48	#define SDIO_MP_AGGR_DEF_PKT_LIMIT 8
5e6e3a92	49
f0c717e6	50	#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
5e6e3a92 BZ	51
5e6e3a92 BZ	52	/* Multi port RX aggregation buffer size */
f0c717e6	53	#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
5e6e3a92 BZ	54
	55	/* Misc. Config Register : Auto Re-enable interrupts */
	56	#define AUTO_RE_ENABLE_INT BIT(4)
	57
	58	/* Host Control Registers */
	59	/* Host Control Registers : I/O port 0 */
	60	#define IO_PORT_0_REG 0x78
	61	/* Host Control Registers : I/O port 1 */
	62	#define IO_PORT_1_REG 0x79
	63	/* Host Control Registers : I/O port 2 */
	64	#define IO_PORT_2_REG 0x7A
	65
	66	/* Host Control Registers : Configuration */
	67	#define CONFIGURATION_REG 0x00
	68	/* Host Control Registers : Host without Command 53 finish host*/
	69	#define HOST_TO_CARD_EVENT (0x1U << 3)
	70	/* Host Control Registers : Host without Command 53 finish host */
	71	#define HOST_WO_CMD53_FINISH_HOST (0x1U << 2)
	72	/* Host Control Registers : Host power up */
	73	#define HOST_POWER_UP (0x1U << 1)
	74	/* Host Control Registers : Host power down */
	75	#define HOST_POWER_DOWN (0x1U << 0)
	76
	77	/* Host Control Registers : Host interrupt mask */
	78	#define HOST_INT_MASK_REG 0x02
	79	/* Host Control Registers : Upload host interrupt mask */
	80	#define UP_LD_HOST_INT_MASK (0x1U)
	81	/* Host Control Registers : Download host interrupt mask */
	82	#define DN_LD_HOST_INT_MASK (0x2U)
5e6e3a92 BZ	83	/* Disable Host interrupt mask */
	84	#define HOST_INT_DISABLE 0xff
	85
	86	/* Host Control Registers : Host interrupt status */
	87	#define HOST_INTSTATUS_REG 0x03
	88	/* Host Control Registers : Upload host interrupt status */
	89	#define UP_LD_HOST_INT_STATUS (0x1U)
	90	/* Host Control Registers : Download host interrupt status */
	91	#define DN_LD_HOST_INT_STATUS (0x2U)
	92
	93	/* Host Control Registers : Host interrupt RSR */
	94	#define HOST_INT_RSR_REG 0x01
	95	/* Host Control Registers : Upload host interrupt RSR */
	96	#define UP_LD_HOST_INT_RSR (0x1U)
5e6e3a92 BZ	97
	98	/* Host Control Registers : Host interrupt status */
	99	#define HOST_INT_STATUS_REG 0x28
	100	/* Host Control Registers : Upload CRC error */
	101	#define UP_LD_CRC_ERR (0x1U << 2)
	102	/* Host Control Registers : Upload restart */
	103	#define UP_LD_RESTART (0x1U << 1)
	104	/* Host Control Registers : Download restart */
	105	#define DN_LD_RESTART (0x1U << 0)
	106
5e6e3a92 BZ	107	/* Card Control Registers : Card I/O ready */
	108	#define CARD_IO_READY (0x1U << 3)
	109	/* Card Control Registers : CIS card ready */
	110	#define CIS_CARD_RDY (0x1U << 2)
	111	/* Card Control Registers : Upload card ready */
	112	#define UP_LD_CARD_RDY (0x1U << 1)
	113	/* Card Control Registers : Download card ready */
	114	#define DN_LD_CARD_RDY (0x1U << 0)
	115
	116	/* Card Control Registers : Host interrupt mask register */
	117	#define HOST_INTERRUPT_MASK_REG 0x34
	118	/* Card Control Registers : Host power interrupt mask */
	119	#define HOST_POWER_INT_MASK (0x1U << 3)
	120	/* Card Control Registers : Abort card interrupt mask */
	121	#define ABORT_CARD_INT_MASK (0x1U << 2)
	122	/* Card Control Registers : Upload card interrupt mask */
	123	#define UP_LD_CARD_INT_MASK (0x1U << 1)
	124	/* Card Control Registers : Download card interrupt mask */
	125	#define DN_LD_CARD_INT_MASK (0x1U << 0)
	126
	127	/* Card Control Registers : Card interrupt status register */
	128	#define CARD_INTERRUPT_STATUS_REG 0x38
	129	/* Card Control Registers : Power up interrupt */
	130	#define POWER_UP_INT (0x1U << 4)
	131	/* Card Control Registers : Power down interrupt */
	132	#define POWER_DOWN_INT (0x1U << 3)
	133
	134	/* Card Control Registers : Card interrupt RSR register */
	135	#define CARD_INTERRUPT_RSR_REG 0x3c
	136	/* Card Control Registers : Power up RSR */
	137	#define POWER_UP_RSR (0x1U << 4)
	138	/* Card Control Registers : Power down RSR */
	139	#define POWER_DOWN_RSR (0x1U << 3)
	140
5e6e3a92 BZ	141	/* Host F1 card ready */
	142	#define HOST_F1_CARD_RDY 0x0020
	143
5e6e3a92 BZ	144	/* Rx length register */
	145	#define CARD_RX_LEN_REG 0x62
	146	/* Rx unit register */
	147	#define CARD_RX_UNIT_REG 0x63
	148
5e6e3a92 BZ	149	/* Max retry number of CMD53 write */
	150	#define MAX_WRITE_IOMEM_RETRY 2
	151
	152	/* SDIO Tx aggregation in progress ? */
	153	#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
	154
	155	/* SDIO Tx aggregation buffer room for next packet ? */
	156	#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
	157	<= a->mpa_tx.buf_size)
	158
	159	/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
	160	#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
	161	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
	162	payload, pkt_len); \
	163	a->mpa_tx.buf_len += pkt_len; \
	164	if (!a->mpa_tx.pkt_cnt) \
	165	a->mpa_tx.start_port = port; \
	166	if (a->mpa_tx.start_port <= port) \
	167	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt)); \
	168	else \
05889f82 AK	169	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt+1+ \
05889f82 AK	170	(a->max_ports - \
5e6e3a92 BZ	171	a->mp_end_port))); \
5e6e3a92 BZ	172	a->mpa_tx.pkt_cnt++; \
da951c24	173	} while (0)
5e6e3a92 BZ	174
	175	/* SDIO Tx aggregation limit ? */
	176	#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
	177	(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
	178
	179	/* SDIO Tx aggregation port limit ? */
	180	#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port < \
05889f82	181	a->mpa_tx.start_port) && (((a->max_ports -\
5e6e3a92	182	a->mpa_tx.start_port) + a->curr_wr_port) >= \
05889f82	183	a->mp_agg_pkt_limit))
5e6e3a92 BZ	184
	185	/* Reset SDIO Tx aggregation buffer parameters */
	186	#define MP_TX_AGGR_BUF_RESET(a) do { \
	187	a->mpa_tx.pkt_cnt = 0; \
	188	a->mpa_tx.buf_len = 0; \
	189	a->mpa_tx.ports = 0; \
	190	a->mpa_tx.start_port = 0; \
da951c24	191	} while (0)
5e6e3a92 BZ	192
	193	/* SDIO Rx aggregation limit ? */
	194	#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
	195	(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
	196
	197	/* SDIO Tx aggregation port limit ? */
	198	#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port < \
05889f82	199	a->mpa_rx.start_port) && (((a->max_ports -\
5e6e3a92	200	a->mpa_rx.start_port) + a->curr_rd_port) >= \
05889f82	201	a->mp_agg_pkt_limit))
5e6e3a92 BZ	202
	203	/* SDIO Rx aggregation in progress ? */
	204	#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
	205
	206	/* SDIO Rx aggregation buffer room for next packet ? */
	207	#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
	208	((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
	209
	210	/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
	211	#define MP_RX_AGGR_SETUP(a, skb, port) do { \
	212	a->mpa_rx.buf_len += skb->len; \
	213	if (!a->mpa_rx.pkt_cnt) \
	214	a->mpa_rx.start_port = port; \
	215	if (a->mpa_rx.start_port <= port) \
	216	a->mpa_rx.ports \|= (1<<(a->mpa_rx.pkt_cnt)); \
	217	else \
	218	a->mpa_rx.ports \|= (1<<(a->mpa_rx.pkt_cnt+1)); \
	219	a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb; \
	220	a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len; \
	221	a->mpa_rx.pkt_cnt++; \
da951c24	222	} while (0)
5e6e3a92 BZ	223
	224	/* Reset SDIO Rx aggregation buffer parameters */
	225	#define MP_RX_AGGR_BUF_RESET(a) do { \
	226	a->mpa_rx.pkt_cnt = 0; \
	227	a->mpa_rx.buf_len = 0; \
	228	a->mpa_rx.ports = 0; \
	229	a->mpa_rx.start_port = 0; \
da951c24	230	} while (0)
5e6e3a92 BZ	231
	232
	233	/* data structure for SDIO MPA TX */
	234	struct mwifiex_sdio_mpa_tx {
	235	/* multiport tx aggregation buffer pointer */
	236	u8 *buf;
	237	u32 buf_len;
	238	u32 pkt_cnt;
5ac253d5	239	u32 ports;
5e6e3a92 BZ	240	u16 start_port;
	241	u8 enabled;
	242	u32 buf_size;
	243	u32 pkt_aggr_limit;
	244	};
	245
	246	struct mwifiex_sdio_mpa_rx {
	247	u8 *buf;
	248	u32 buf_len;
	249	u32 pkt_cnt;
5ac253d5	250	u32 ports;
5e6e3a92 BZ	251	u16 start_port;
	252
	253	struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
	254	u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
	255
	256	u8 enabled;
	257	u32 buf_size;
	258	u32 pkt_aggr_limit;
	259	};
	260
	261	int mwifiex_bus_register(void);
	262	void mwifiex_bus_unregister(void);
	263
05889f82 AK	264	struct mwifiex_sdio_card_reg {
	265	u8 start_rd_port;
	266	u8 start_wr_port;
	267	u8 base_0_reg;
	268	u8 base_1_reg;
	269	u8 poll_reg;
	270	u8 host_int_enable;
	271	u8 status_reg_0;
	272	u8 status_reg_1;
	273	u8 sdio_int_mask;
	274	u32 data_port_mask;
	275	u8 max_mp_regs;
	276	u8 rd_bitmap_l;
	277	u8 rd_bitmap_u;
	278	u8 wr_bitmap_l;
	279	u8 wr_bitmap_u;
	280	u8 rd_len_p0_l;
	281	u8 rd_len_p0_u;
	282	u8 card_misc_cfg_reg;
	283	};
	284
5e6e3a92 BZ	285	struct sdio_mmc_card {
	286	struct sdio_func *func;
	287	struct mwifiex_adapter *adapter;
	288
05889f82 AK	289	const char *firmware;
	290	const struct mwifiex_sdio_card_reg *reg;
	291	u8 max_ports;
	292	u8 mp_agg_pkt_limit;
	293
5ac253d5 AK	294	u32 mp_rd_bitmap;
5ac253d5 AK	295	u32 mp_wr_bitmap;
5e6e3a92 BZ	296
5e6e3a92 BZ	297	u16 mp_end_port;
5ac253d5	298	u32 mp_data_port_mask;
5e6e3a92 BZ	299
	300	u8 curr_rd_port;
	301	u8 curr_wr_port;
	302
	303	u8 *mp_regs;
	304
	305	struct mwifiex_sdio_mpa_tx mpa_tx;
	306	struct mwifiex_sdio_mpa_rx mpa_rx;
	307	};
d930faee	308
05889f82 AK	309	struct mwifiex_sdio_device {
	310	const char *firmware;
	311	const struct mwifiex_sdio_card_reg *reg;
	312	u8 max_ports;
	313	u8 mp_agg_pkt_limit;
	314	};
	315
	316	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	317	.start_rd_port = 1,
	318	.start_wr_port = 1,
	319	.base_0_reg = 0x0040,
	320	.base_1_reg = 0x0041,
	321	.poll_reg = 0x30,
	322	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK,
	323	.status_reg_0 = 0x60,
	324	.status_reg_1 = 0x61,
	325	.sdio_int_mask = 0x3f,
	326	.data_port_mask = 0x0000fffe,
	327	.max_mp_regs = 64,
	328	.rd_bitmap_l = 0x04,
	329	.rd_bitmap_u = 0x05,
	330	.wr_bitmap_l = 0x06,
	331	.wr_bitmap_u = 0x07,
	332	.rd_len_p0_l = 0x08,
	333	.rd_len_p0_u = 0x09,
	334	.card_misc_cfg_reg = 0x6c,
	335	};
	336
	337	static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	338	.firmware = SD8786_DEFAULT_FW_NAME,
	339	.reg = &mwifiex_reg_sd87xx,
	340	.max_ports = 16,
	341	.mp_agg_pkt_limit = 8,
	342	};
	343
	344	static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	345	.firmware = SD8787_DEFAULT_FW_NAME,
	346	.reg = &mwifiex_reg_sd87xx,
	347	.max_ports = 16,
	348	.mp_agg_pkt_limit = 8,
	349	};
	350
	351	static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	352	.firmware = SD8797_DEFAULT_FW_NAME,
	353	.reg = &mwifiex_reg_sd87xx,
	354	.max_ports = 16,
	355	.mp_agg_pkt_limit = 8,
	356	};
	357
d930faee AK	358	/*
	359	* .cmdrsp_complete handler
	360	*/
	361	static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
	362	struct sk_buff *skb)
	363	{
	364	dev_kfree_skb_any(skb);
	365	return 0;
	366	}
	367
	368	/*
	369	* .event_complete handler
	370	*/
	371	static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
	372	struct sk_buff *skb)
	373	{
	374	dev_kfree_skb_any(skb);
	375	return 0;
	376	}
	377
5e6e3a92	378	#endif /* _MWIFIEX_SDIO_H */