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5e6e3a92 BZ |
1 | /* |
2 | * Marvell Wireless LAN device driver: SDIO specific definitions | |
3 | * | |
4 | * Copyright (C) 2011, Marvell International Ltd. | |
5 | * | |
6 | * This software file (the "File") is distributed by Marvell International | |
7 | * Ltd. under the terms of the GNU General Public License Version 2, June 1991 | |
8 | * (the "License"). You may use, redistribute and/or modify this File in | |
9 | * accordance with the terms and conditions of the License, a copy of which | |
10 | * is available by writing to the Free Software Foundation, Inc., | |
11 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the | |
12 | * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. | |
13 | * | |
14 | * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE | |
15 | * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE | |
16 | * ARE EXPRESSLY DISCLAIMED. The License provides additional details about | |
17 | * this warranty disclaimer. | |
18 | */ | |
19 | ||
20 | #ifndef _MWIFIEX_SDIO_H | |
21 | #define _MWIFIEX_SDIO_H | |
22 | ||
23 | ||
24 | #include <linux/mmc/sdio.h> | |
25 | #include <linux/mmc/sdio_ids.h> | |
26 | #include <linux/mmc/sdio_func.h> | |
27 | #include <linux/mmc/card.h> | |
d31ab357 | 28 | #include <linux/mmc/host.h> |
5e6e3a92 BZ |
29 | |
30 | #include "main.h" | |
31 | ||
98e6b9df | 32 | #define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin" |
4a7f5db1 | 33 | #define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin" |
e3bea1c8 | 34 | #define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin" |
b60186f8 | 35 | #define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin" |
4a7f5db1 | 36 | |
5e6e3a92 BZ |
37 | #define BLOCK_MODE 1 |
38 | #define BYTE_MODE 0 | |
39 | ||
40 | #define REG_PORT 0 | |
5e6e3a92 BZ |
41 | |
42 | #define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff | |
43 | ||
44 | #define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000 | |
45 | ||
248eb4c6 | 46 | #define SDIO_MPA_ADDR_BASE 0x1000 |
5e6e3a92 BZ |
47 | #define CTRL_PORT 0 |
48 | #define CTRL_PORT_MASK 0x0001 | |
5e6e3a92 | 49 | |
b60186f8 YAP |
50 | #define CMD_PORT_UPLD_INT_MASK (0x1U<<6) |
51 | #define CMD_PORT_DNLD_INT_MASK (0x1U<<7) | |
52 | #define HOST_TERM_CMD53 (0x1U << 2) | |
53 | #define REG_PORT 0 | |
54 | #define MEM_PORT 0x10000 | |
55 | #define CMD_RD_LEN_0 0xB4 | |
56 | #define CMD_RD_LEN_1 0xB5 | |
57 | #define CARD_CONFIG_2_1_REG 0xCD | |
58 | #define CMD53_NEW_MODE (0x1U << 0) | |
59 | #define CMD_CONFIG_0 0xB8 | |
60 | #define CMD_PORT_RD_LEN_EN (0x1U << 2) | |
61 | #define CMD_CONFIG_1 0xB9 | |
62 | #define CMD_PORT_AUTO_EN (0x1U << 0) | |
63 | #define CMD_PORT_SLCT 0x8000 | |
64 | #define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) | |
65 | #define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) | |
66 | ||
f0c717e6 | 67 | #define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */ |
5e6e3a92 BZ |
68 | |
69 | /* Multi port RX aggregation buffer size */ | |
f0c717e6 | 70 | #define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */ |
5e6e3a92 BZ |
71 | |
72 | /* Misc. Config Register : Auto Re-enable interrupts */ | |
73 | #define AUTO_RE_ENABLE_INT BIT(4) | |
74 | ||
75 | /* Host Control Registers */ | |
76 | /* Host Control Registers : I/O port 0 */ | |
77 | #define IO_PORT_0_REG 0x78 | |
78 | /* Host Control Registers : I/O port 1 */ | |
79 | #define IO_PORT_1_REG 0x79 | |
80 | /* Host Control Registers : I/O port 2 */ | |
81 | #define IO_PORT_2_REG 0x7A | |
82 | ||
83 | /* Host Control Registers : Configuration */ | |
84 | #define CONFIGURATION_REG 0x00 | |
5e6e3a92 BZ |
85 | /* Host Control Registers : Host power up */ |
86 | #define HOST_POWER_UP (0x1U << 1) | |
5e6e3a92 BZ |
87 | |
88 | /* Host Control Registers : Host interrupt mask */ | |
89 | #define HOST_INT_MASK_REG 0x02 | |
90 | /* Host Control Registers : Upload host interrupt mask */ | |
91 | #define UP_LD_HOST_INT_MASK (0x1U) | |
92 | /* Host Control Registers : Download host interrupt mask */ | |
93 | #define DN_LD_HOST_INT_MASK (0x2U) | |
b60186f8 | 94 | |
5e6e3a92 BZ |
95 | /* Disable Host interrupt mask */ |
96 | #define HOST_INT_DISABLE 0xff | |
97 | ||
98 | /* Host Control Registers : Host interrupt status */ | |
99 | #define HOST_INTSTATUS_REG 0x03 | |
100 | /* Host Control Registers : Upload host interrupt status */ | |
101 | #define UP_LD_HOST_INT_STATUS (0x1U) | |
102 | /* Host Control Registers : Download host interrupt status */ | |
103 | #define DN_LD_HOST_INT_STATUS (0x2U) | |
104 | ||
105 | /* Host Control Registers : Host interrupt RSR */ | |
106 | #define HOST_INT_RSR_REG 0x01 | |
5e6e3a92 BZ |
107 | |
108 | /* Host Control Registers : Host interrupt status */ | |
109 | #define HOST_INT_STATUS_REG 0x28 | |
5e6e3a92 | 110 | |
5e6e3a92 BZ |
111 | /* Card Control Registers : Card I/O ready */ |
112 | #define CARD_IO_READY (0x1U << 3) | |
5e6e3a92 BZ |
113 | /* Card Control Registers : Download card ready */ |
114 | #define DN_LD_CARD_RDY (0x1U << 0) | |
115 | ||
5e6e3a92 BZ |
116 | /* Max retry number of CMD53 write */ |
117 | #define MAX_WRITE_IOMEM_RETRY 2 | |
118 | ||
119 | /* SDIO Tx aggregation in progress ? */ | |
120 | #define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0) | |
121 | ||
122 | /* SDIO Tx aggregation buffer room for next packet ? */ | |
123 | #define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \ | |
124 | <= a->mpa_tx.buf_size) | |
125 | ||
126 | /* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ | |
127 | #define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \ | |
128 | memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \ | |
129 | payload, pkt_len); \ | |
130 | a->mpa_tx.buf_len += pkt_len; \ | |
131 | if (!a->mpa_tx.pkt_cnt) \ | |
132 | a->mpa_tx.start_port = port; \ | |
133 | if (a->mpa_tx.start_port <= port) \ | |
134 | a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \ | |
135 | else \ | |
05889f82 AK |
136 | a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \ |
137 | (a->max_ports - \ | |
5e6e3a92 BZ |
138 | a->mp_end_port))); \ |
139 | a->mpa_tx.pkt_cnt++; \ | |
da951c24 | 140 | } while (0) |
5e6e3a92 BZ |
141 | |
142 | /* SDIO Tx aggregation limit ? */ | |
143 | #define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \ | |
144 | (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit) | |
145 | ||
5e6e3a92 BZ |
146 | /* Reset SDIO Tx aggregation buffer parameters */ |
147 | #define MP_TX_AGGR_BUF_RESET(a) do { \ | |
148 | a->mpa_tx.pkt_cnt = 0; \ | |
149 | a->mpa_tx.buf_len = 0; \ | |
150 | a->mpa_tx.ports = 0; \ | |
151 | a->mpa_tx.start_port = 0; \ | |
da951c24 | 152 | } while (0) |
5e6e3a92 BZ |
153 | |
154 | /* SDIO Rx aggregation limit ? */ | |
155 | #define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \ | |
156 | (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit) | |
157 | ||
5e6e3a92 BZ |
158 | /* SDIO Rx aggregation in progress ? */ |
159 | #define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0) | |
160 | ||
161 | /* SDIO Rx aggregation buffer room for next packet ? */ | |
162 | #define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \ | |
163 | ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size) | |
164 | ||
5e6e3a92 BZ |
165 | /* Reset SDIO Rx aggregation buffer parameters */ |
166 | #define MP_RX_AGGR_BUF_RESET(a) do { \ | |
167 | a->mpa_rx.pkt_cnt = 0; \ | |
168 | a->mpa_rx.buf_len = 0; \ | |
169 | a->mpa_rx.ports = 0; \ | |
170 | a->mpa_rx.start_port = 0; \ | |
da951c24 | 171 | } while (0) |
5e6e3a92 | 172 | |
5e6e3a92 BZ |
173 | /* data structure for SDIO MPA TX */ |
174 | struct mwifiex_sdio_mpa_tx { | |
175 | /* multiport tx aggregation buffer pointer */ | |
176 | u8 *buf; | |
177 | u32 buf_len; | |
178 | u32 pkt_cnt; | |
5ac253d5 | 179 | u32 ports; |
5e6e3a92 BZ |
180 | u16 start_port; |
181 | u8 enabled; | |
182 | u32 buf_size; | |
183 | u32 pkt_aggr_limit; | |
184 | }; | |
185 | ||
186 | struct mwifiex_sdio_mpa_rx { | |
187 | u8 *buf; | |
188 | u32 buf_len; | |
189 | u32 pkt_cnt; | |
5ac253d5 | 190 | u32 ports; |
5e6e3a92 BZ |
191 | u16 start_port; |
192 | ||
c23b7c8f AK |
193 | struct sk_buff **skb_arr; |
194 | u32 *len_arr; | |
5e6e3a92 BZ |
195 | |
196 | u8 enabled; | |
197 | u32 buf_size; | |
198 | u32 pkt_aggr_limit; | |
199 | }; | |
200 | ||
201 | int mwifiex_bus_register(void); | |
202 | void mwifiex_bus_unregister(void); | |
203 | ||
05889f82 AK |
204 | struct mwifiex_sdio_card_reg { |
205 | u8 start_rd_port; | |
206 | u8 start_wr_port; | |
207 | u8 base_0_reg; | |
208 | u8 base_1_reg; | |
209 | u8 poll_reg; | |
210 | u8 host_int_enable; | |
211 | u8 status_reg_0; | |
212 | u8 status_reg_1; | |
213 | u8 sdio_int_mask; | |
214 | u32 data_port_mask; | |
215 | u8 max_mp_regs; | |
216 | u8 rd_bitmap_l; | |
217 | u8 rd_bitmap_u; | |
b60186f8 YAP |
218 | u8 rd_bitmap_1l; |
219 | u8 rd_bitmap_1u; | |
05889f82 AK |
220 | u8 wr_bitmap_l; |
221 | u8 wr_bitmap_u; | |
b60186f8 YAP |
222 | u8 wr_bitmap_1l; |
223 | u8 wr_bitmap_1u; | |
05889f82 AK |
224 | u8 rd_len_p0_l; |
225 | u8 rd_len_p0_u; | |
226 | u8 card_misc_cfg_reg; | |
227 | }; | |
228 | ||
5e6e3a92 BZ |
229 | struct sdio_mmc_card { |
230 | struct sdio_func *func; | |
231 | struct mwifiex_adapter *adapter; | |
232 | ||
05889f82 AK |
233 | const char *firmware; |
234 | const struct mwifiex_sdio_card_reg *reg; | |
235 | u8 max_ports; | |
236 | u8 mp_agg_pkt_limit; | |
b60186f8 YAP |
237 | bool supports_sdio_new_mode; |
238 | bool has_control_mask; | |
05889f82 | 239 | |
5ac253d5 AK |
240 | u32 mp_rd_bitmap; |
241 | u32 mp_wr_bitmap; | |
5e6e3a92 BZ |
242 | |
243 | u16 mp_end_port; | |
5ac253d5 | 244 | u32 mp_data_port_mask; |
5e6e3a92 BZ |
245 | |
246 | u8 curr_rd_port; | |
247 | u8 curr_wr_port; | |
248 | ||
249 | u8 *mp_regs; | |
250 | ||
251 | struct mwifiex_sdio_mpa_tx mpa_tx; | |
252 | struct mwifiex_sdio_mpa_rx mpa_rx; | |
253 | }; | |
d930faee | 254 | |
05889f82 AK |
255 | struct mwifiex_sdio_device { |
256 | const char *firmware; | |
257 | const struct mwifiex_sdio_card_reg *reg; | |
258 | u8 max_ports; | |
259 | u8 mp_agg_pkt_limit; | |
b60186f8 YAP |
260 | bool supports_sdio_new_mode; |
261 | bool has_control_mask; | |
05889f82 AK |
262 | }; |
263 | ||
264 | static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = { | |
265 | .start_rd_port = 1, | |
266 | .start_wr_port = 1, | |
267 | .base_0_reg = 0x0040, | |
268 | .base_1_reg = 0x0041, | |
269 | .poll_reg = 0x30, | |
270 | .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK, | |
271 | .status_reg_0 = 0x60, | |
272 | .status_reg_1 = 0x61, | |
273 | .sdio_int_mask = 0x3f, | |
274 | .data_port_mask = 0x0000fffe, | |
275 | .max_mp_regs = 64, | |
276 | .rd_bitmap_l = 0x04, | |
277 | .rd_bitmap_u = 0x05, | |
278 | .wr_bitmap_l = 0x06, | |
279 | .wr_bitmap_u = 0x07, | |
280 | .rd_len_p0_l = 0x08, | |
281 | .rd_len_p0_u = 0x09, | |
282 | .card_misc_cfg_reg = 0x6c, | |
283 | }; | |
284 | ||
b60186f8 YAP |
285 | static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = { |
286 | .start_rd_port = 0, | |
287 | .start_wr_port = 0, | |
288 | .base_0_reg = 0x60, | |
289 | .base_1_reg = 0x61, | |
290 | .poll_reg = 0x50, | |
291 | .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | | |
292 | CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, | |
293 | .status_reg_0 = 0xc0, | |
294 | .status_reg_1 = 0xc1, | |
295 | .sdio_int_mask = 0xff, | |
296 | .data_port_mask = 0xffffffff, | |
297 | .max_mp_regs = 184, | |
298 | .rd_bitmap_l = 0x04, | |
299 | .rd_bitmap_u = 0x05, | |
300 | .rd_bitmap_1l = 0x06, | |
301 | .rd_bitmap_1u = 0x07, | |
302 | .wr_bitmap_l = 0x08, | |
303 | .wr_bitmap_u = 0x09, | |
304 | .wr_bitmap_1l = 0x0a, | |
305 | .wr_bitmap_1u = 0x0b, | |
306 | .rd_len_p0_l = 0x0c, | |
307 | .rd_len_p0_u = 0x0d, | |
308 | .card_misc_cfg_reg = 0xcc, | |
309 | }; | |
310 | ||
05889f82 AK |
311 | static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = { |
312 | .firmware = SD8786_DEFAULT_FW_NAME, | |
313 | .reg = &mwifiex_reg_sd87xx, | |
314 | .max_ports = 16, | |
315 | .mp_agg_pkt_limit = 8, | |
b60186f8 YAP |
316 | .supports_sdio_new_mode = false, |
317 | .has_control_mask = true, | |
05889f82 AK |
318 | }; |
319 | ||
320 | static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = { | |
321 | .firmware = SD8787_DEFAULT_FW_NAME, | |
322 | .reg = &mwifiex_reg_sd87xx, | |
323 | .max_ports = 16, | |
324 | .mp_agg_pkt_limit = 8, | |
b60186f8 YAP |
325 | .supports_sdio_new_mode = false, |
326 | .has_control_mask = true, | |
05889f82 AK |
327 | }; |
328 | ||
329 | static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = { | |
330 | .firmware = SD8797_DEFAULT_FW_NAME, | |
331 | .reg = &mwifiex_reg_sd87xx, | |
332 | .max_ports = 16, | |
333 | .mp_agg_pkt_limit = 8, | |
b60186f8 YAP |
334 | .supports_sdio_new_mode = false, |
335 | .has_control_mask = true, | |
336 | }; | |
337 | ||
338 | static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = { | |
339 | .firmware = SD8897_DEFAULT_FW_NAME, | |
340 | .reg = &mwifiex_reg_sd8897, | |
341 | .max_ports = 32, | |
342 | .mp_agg_pkt_limit = 16, | |
343 | .supports_sdio_new_mode = true, | |
344 | .has_control_mask = false, | |
05889f82 AK |
345 | }; |
346 | ||
d930faee AK |
347 | /* |
348 | * .cmdrsp_complete handler | |
349 | */ | |
350 | static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter, | |
351 | struct sk_buff *skb) | |
352 | { | |
353 | dev_kfree_skb_any(skb); | |
354 | return 0; | |
355 | } | |
356 | ||
357 | /* | |
358 | * .event_complete handler | |
359 | */ | |
360 | static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter, | |
361 | struct sk_buff *skb) | |
362 | { | |
363 | dev_kfree_skb_any(skb); | |
364 | return 0; | |
365 | } | |
366 | ||
c23b7c8f AK |
367 | static inline bool |
368 | mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card) | |
369 | { | |
370 | u8 tmp; | |
371 | ||
372 | if (card->curr_rd_port < card->mpa_rx.start_port) { | |
b60186f8 YAP |
373 | if (card->supports_sdio_new_mode) |
374 | tmp = card->mp_end_port >> 1; | |
375 | else | |
376 | tmp = card->mp_agg_pkt_limit; | |
c23b7c8f AK |
377 | |
378 | if (((card->max_ports - card->mpa_rx.start_port) + | |
379 | card->curr_rd_port) >= tmp) | |
380 | return true; | |
381 | } | |
382 | ||
b60186f8 YAP |
383 | if (!card->supports_sdio_new_mode) |
384 | return false; | |
385 | ||
386 | if ((card->curr_rd_port - card->mpa_rx.start_port) >= | |
387 | (card->mp_end_port >> 1)) | |
388 | return true; | |
389 | ||
c23b7c8f AK |
390 | return false; |
391 | } | |
392 | ||
393 | static inline bool | |
394 | mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card) | |
395 | { | |
396 | u16 tmp; | |
397 | ||
398 | if (card->curr_wr_port < card->mpa_tx.start_port) { | |
b60186f8 YAP |
399 | if (card->supports_sdio_new_mode) |
400 | tmp = card->mp_end_port >> 1; | |
401 | else | |
402 | tmp = card->mp_agg_pkt_limit; | |
c23b7c8f AK |
403 | |
404 | if (((card->max_ports - card->mpa_tx.start_port) + | |
405 | card->curr_wr_port) >= tmp) | |
406 | return true; | |
407 | } | |
408 | ||
b60186f8 YAP |
409 | if (!card->supports_sdio_new_mode) |
410 | return false; | |
411 | ||
412 | if ((card->curr_wr_port - card->mpa_tx.start_port) >= | |
413 | (card->mp_end_port >> 1)) | |
414 | return true; | |
415 | ||
c23b7c8f AK |
416 | return false; |
417 | } | |
418 | ||
419 | /* Prepare to copy current packet from card to SDIO Rx aggregation buffer */ | |
420 | static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card, | |
421 | struct sk_buff *skb, u8 port) | |
422 | { | |
423 | card->mpa_rx.buf_len += skb->len; | |
424 | ||
425 | if (!card->mpa_rx.pkt_cnt) | |
426 | card->mpa_rx.start_port = port; | |
427 | ||
b60186f8 YAP |
428 | if (card->supports_sdio_new_mode) { |
429 | card->mpa_rx.ports |= (1 << port); | |
430 | } else { | |
431 | if (card->mpa_rx.start_port <= port) | |
432 | card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt); | |
433 | else | |
434 | card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1); | |
435 | } | |
c23b7c8f AK |
436 | card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = skb; |
437 | card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = skb->len; | |
438 | card->mpa_rx.pkt_cnt++; | |
439 | } | |
5e6e3a92 | 440 | #endif /* _MWIFIEX_SDIO_H */ |