[deliverable/linux.git] / drivers / net / wireless / mwifiex / sdio.h

/*
 * Marvell Wireless LAN device driver: SDIO specific definitions
 *
 * Copyright (C) 2011, Marvell International Ltd.
 *
 * This software file (the "File") is distributed by Marvell International
 * Ltd. under the terms of the GNU General Public License Version 2, June 1991
 * (the "License").  You may use, redistribute and/or modify this File in
 * accordance with the terms and conditions of the License, a copy of which
 * is available by writing to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
 *
 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
 * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
 * this warranty disclaimer.
 */

#ifndef	_MWIFIEX_SDIO_H
#define	_MWIFIEX_SDIO_H


#include <linux/mmc/sdio.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>

#include "main.h"

#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"

#define BLOCK_MODE	1
#define BYTE_MODE	0

#define REG_PORT			0

#define MWIFIEX_SDIO_IO_PORT_MASK		0xfffff

#define MWIFIEX_SDIO_BYTE_MODE_MASK	0x80000000

#define SDIO_MPA_ADDR_BASE		0x1000
#define CTRL_PORT			0
#define CTRL_PORT_MASK			0x0001

#define SDIO_MP_AGGR_DEF_PKT_LIMIT		8

#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE        (8192)	/* 8K */

/* Multi port RX aggregation buffer size */
#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE        (16384)	/* 16K */

/* Misc. Config Register : Auto Re-enable interrupts */
#define AUTO_RE_ENABLE_INT              BIT(4)

/* Host Control Registers */
/* Host Control Registers : I/O port 0 */
#define IO_PORT_0_REG			0x78
/* Host Control Registers : I/O port 1 */
#define IO_PORT_1_REG			0x79
/* Host Control Registers : I/O port 2 */
#define IO_PORT_2_REG			0x7A

/* Host Control Registers : Configuration */
#define CONFIGURATION_REG		0x00
/* Host Control Registers : Host power up */
#define HOST_POWER_UP			(0x1U << 1)

/* Host Control Registers : Host interrupt mask */
#define HOST_INT_MASK_REG		0x02
/* Host Control Registers : Upload host interrupt mask */
#define UP_LD_HOST_INT_MASK		(0x1U)
/* Host Control Registers : Download host interrupt mask */
#define DN_LD_HOST_INT_MASK		(0x2U)
/* Disable Host interrupt mask */
#define	HOST_INT_DISABLE		0xff

/* Host Control Registers : Host interrupt status */
#define HOST_INTSTATUS_REG		0x03
/* Host Control Registers : Upload host interrupt status */
#define UP_LD_HOST_INT_STATUS		(0x1U)
/* Host Control Registers : Download host interrupt status */
#define DN_LD_HOST_INT_STATUS		(0x2U)

/* Host Control Registers : Host interrupt RSR */
#define HOST_INT_RSR_REG		0x01

/* Host Control Registers : Host interrupt status */
#define HOST_INT_STATUS_REG		0x28

/* Card Control Registers : Card I/O ready */
#define CARD_IO_READY                   (0x1U << 3)
/* Card Control Registers : Download card ready */
#define DN_LD_CARD_RDY                  (0x1U << 0)

/* Max retry number of CMD53 write */
#define MAX_WRITE_IOMEM_RETRY		2

/* SDIO Tx aggregation in progress ? */
#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)

/* SDIO Tx aggregation buffer room for next packet ? */
#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len)	\
						<= a->mpa_tx.buf_size)

/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do {		\
	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len],			\
			payload, pkt_len);				\
	a->mpa_tx.buf_len += pkt_len;					\
	if (!a->mpa_tx.pkt_cnt)						\
		a->mpa_tx.start_port = port;				\
	if (a->mpa_tx.start_port <= port)				\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt));		\
	else								\
		a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+		\
						(a->max_ports -	\
						a->mp_end_port)));	\
	a->mpa_tx.pkt_cnt++;						\
} while (0)

/* SDIO Tx aggregation limit ? */
#define MP_TX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)

/* SDIO Tx aggregation port limit ? */
#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port <		\
			a->mpa_tx.start_port) && (((a->max_ports -\
			a->mpa_tx.start_port) + a->curr_wr_port) >=	\
				a->mp_agg_pkt_limit))

/* Reset SDIO Tx aggregation buffer parameters */
#define MP_TX_AGGR_BUF_RESET(a) do {					\
	a->mpa_tx.pkt_cnt = 0;						\
	a->mpa_tx.buf_len = 0;						\
	a->mpa_tx.ports = 0;						\
	a->mpa_tx.start_port = 0;					\
} while (0)

/* SDIO Rx aggregation limit ? */
#define MP_RX_AGGR_PKT_LIMIT_REACHED(a)					\
			(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)

/* SDIO Tx aggregation port limit ? */
#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port <		\
			a->mpa_rx.start_port) && (((a->max_ports -\
			a->mpa_rx.start_port) + a->curr_rd_port) >=	\
			a->mp_agg_pkt_limit))

/* SDIO Rx aggregation in progress ? */
#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)

/* SDIO Rx aggregation buffer room for next packet ? */
#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len)				\
			((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)

/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
#define MP_RX_AGGR_SETUP(a, skb, port) do {				\
	a->mpa_rx.buf_len += skb->len;					\
	if (!a->mpa_rx.pkt_cnt)						\
		a->mpa_rx.start_port = port;				\
	if (a->mpa_rx.start_port <= port)				\
		a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt));		\
	else								\
		a->mpa_rx.ports |= (1<<(a->mpa_rx.pkt_cnt+1));		\
	a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb;			\
	a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len;		\
	a->mpa_rx.pkt_cnt++;						\
} while (0)

/* Reset SDIO Rx aggregation buffer parameters */
#define MP_RX_AGGR_BUF_RESET(a) do {					\
	a->mpa_rx.pkt_cnt = 0;						\
	a->mpa_rx.buf_len = 0;						\
	a->mpa_rx.ports = 0;						\
	a->mpa_rx.start_port = 0;					\
} while (0)


/* data structure for SDIO MPA TX */
struct mwifiex_sdio_mpa_tx {
	/* multiport tx aggregation buffer pointer */
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;
	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

struct mwifiex_sdio_mpa_rx {
	u8 *buf;
	u32 buf_len;
	u32 pkt_cnt;
	u32 ports;
	u16 start_port;

	struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
	u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];

	u8 enabled;
	u32 buf_size;
	u32 pkt_aggr_limit;
};

int mwifiex_bus_register(void);
void mwifiex_bus_unregister(void);

struct mwifiex_sdio_card_reg {
	u8 start_rd_port;
	u8 start_wr_port;
	u8 base_0_reg;
	u8 base_1_reg;
	u8 poll_reg;
	u8 host_int_enable;
	u8 status_reg_0;
	u8 status_reg_1;
	u8 sdio_int_mask;
	u32 data_port_mask;
	u8 max_mp_regs;
	u8 rd_bitmap_l;
	u8 rd_bitmap_u;
	u8 wr_bitmap_l;
	u8 wr_bitmap_u;
	u8 rd_len_p0_l;
	u8 rd_len_p0_u;
	u8 card_misc_cfg_reg;
};

struct sdio_mmc_card {
	struct sdio_func *func;
	struct mwifiex_adapter *adapter;

	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;

	u32 mp_rd_bitmap;
	u32 mp_wr_bitmap;

	u16 mp_end_port;
	u32 mp_data_port_mask;

	u8 curr_rd_port;
	u8 curr_wr_port;

	u8 *mp_regs;

	struct mwifiex_sdio_mpa_tx mpa_tx;
	struct mwifiex_sdio_mpa_rx mpa_rx;
};

struct mwifiex_sdio_device {
	const char *firmware;
	const struct mwifiex_sdio_card_reg *reg;
	u8 max_ports;
	u8 mp_agg_pkt_limit;
};

static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	.start_rd_port = 1,
	.start_wr_port = 1,
	.base_0_reg = 0x0040,
	.base_1_reg = 0x0041,
	.poll_reg = 0x30,
	.host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK,
	.status_reg_0 = 0x60,
	.status_reg_1 = 0x61,
	.sdio_int_mask = 0x3f,
	.data_port_mask = 0x0000fffe,
	.max_mp_regs = 64,
	.rd_bitmap_l = 0x04,
	.rd_bitmap_u = 0x05,
	.wr_bitmap_l = 0x06,
	.wr_bitmap_u = 0x07,
	.rd_len_p0_l = 0x08,
	.rd_len_p0_u = 0x09,
	.card_misc_cfg_reg = 0x6c,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	.firmware = SD8786_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	.firmware = SD8787_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
};

static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	.firmware = SD8797_DEFAULT_FW_NAME,
	.reg = &mwifiex_reg_sd87xx,
	.max_ports = 16,
	.mp_agg_pkt_limit = 8,
};

/*
 * .cmdrsp_complete handler
 */
static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
					       struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

/*
 * .event_complete handler
 */
static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
					      struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
	return 0;
}

#endif /* _MWIFIEX_SDIO_H */
Commit	Line	Data
5e6e3a92 BZ	1	/*
	2	* Marvell Wireless LAN device driver: SDIO specific definitions
	3	*
	4	* Copyright (C) 2011, Marvell International Ltd.
	5	*
	6	* This software file (the "File") is distributed by Marvell International
	7	* Ltd. under the terms of the GNU General Public License Version 2, June 1991
	8	* (the "License"). You may use, redistribute and/or modify this File in
	9	* accordance with the terms and conditions of the License, a copy of which
	10	* is available by writing to the Free Software Foundation, Inc.,
	11	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
	12	* worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
	13	*
	14	* THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
	15	* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
	16	* ARE EXPRESSLY DISCLAIMED. The License provides additional details about
	17	* this warranty disclaimer.
	18	*/
	19
	20	#ifndef _MWIFIEX_SDIO_H
	21	#define _MWIFIEX_SDIO_H
	22
	23
	24	#include <linux/mmc/sdio.h>
	25	#include <linux/mmc/sdio_ids.h>
	26	#include <linux/mmc/sdio_func.h>
	27	#include <linux/mmc/card.h>
d31ab357	28	#include <linux/mmc/host.h>
5e6e3a92 BZ	29
	30	#include "main.h"
	31
98e6b9df	32	#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin"
4a7f5db1	33	#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin"
e3bea1c8	34	#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin"
4a7f5db1	35
5e6e3a92 BZ	36	#define BLOCK_MODE 1
	37	#define BYTE_MODE 0
	38
	39	#define REG_PORT 0
5e6e3a92 BZ	40
	41	#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff
	42
	43	#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000
	44
248eb4c6	45	#define SDIO_MPA_ADDR_BASE 0x1000
5e6e3a92 BZ	46	#define CTRL_PORT 0
5e6e3a92 BZ	47	#define CTRL_PORT_MASK 0x0001
5e6e3a92	48
05889f82	49	#define SDIO_MP_AGGR_DEF_PKT_LIMIT 8
5e6e3a92	50
f0c717e6	51	#define SDIO_MP_TX_AGGR_DEF_BUF_SIZE (8192) /* 8K */
5e6e3a92 BZ	52
5e6e3a92 BZ	53	/* Multi port RX aggregation buffer size */
f0c717e6	54	#define SDIO_MP_RX_AGGR_DEF_BUF_SIZE (16384) /* 16K */
5e6e3a92 BZ	55
	56	/* Misc. Config Register : Auto Re-enable interrupts */
	57	#define AUTO_RE_ENABLE_INT BIT(4)
	58
	59	/* Host Control Registers */
	60	/* Host Control Registers : I/O port 0 */
	61	#define IO_PORT_0_REG 0x78
	62	/* Host Control Registers : I/O port 1 */
	63	#define IO_PORT_1_REG 0x79
	64	/* Host Control Registers : I/O port 2 */
	65	#define IO_PORT_2_REG 0x7A
	66
	67	/* Host Control Registers : Configuration */
	68	#define CONFIGURATION_REG 0x00
5e6e3a92 BZ	69	/* Host Control Registers : Host power up */
5e6e3a92 BZ	70	#define HOST_POWER_UP (0x1U << 1)
5e6e3a92 BZ	71
	72	/* Host Control Registers : Host interrupt mask */
	73	#define HOST_INT_MASK_REG 0x02
	74	/* Host Control Registers : Upload host interrupt mask */
	75	#define UP_LD_HOST_INT_MASK (0x1U)
	76	/* Host Control Registers : Download host interrupt mask */
	77	#define DN_LD_HOST_INT_MASK (0x2U)
5e6e3a92 BZ	78	/* Disable Host interrupt mask */
	79	#define HOST_INT_DISABLE 0xff
	80
	81	/* Host Control Registers : Host interrupt status */
	82	#define HOST_INTSTATUS_REG 0x03
	83	/* Host Control Registers : Upload host interrupt status */
	84	#define UP_LD_HOST_INT_STATUS (0x1U)
	85	/* Host Control Registers : Download host interrupt status */
	86	#define DN_LD_HOST_INT_STATUS (0x2U)
	87
	88	/* Host Control Registers : Host interrupt RSR */
	89	#define HOST_INT_RSR_REG 0x01
5e6e3a92 BZ	90
	91	/* Host Control Registers : Host interrupt status */
	92	#define HOST_INT_STATUS_REG 0x28
5e6e3a92	93
5e6e3a92 BZ	94	/* Card Control Registers : Card I/O ready */
5e6e3a92 BZ	95	#define CARD_IO_READY (0x1U << 3)
5e6e3a92 BZ	96	/* Card Control Registers : Download card ready */
	97	#define DN_LD_CARD_RDY (0x1U << 0)
	98
5e6e3a92 BZ	99	/* Max retry number of CMD53 write */
	100	#define MAX_WRITE_IOMEM_RETRY 2
	101
	102	/* SDIO Tx aggregation in progress ? */
	103	#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0)
	104
	105	/* SDIO Tx aggregation buffer room for next packet ? */
	106	#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \
	107	<= a->mpa_tx.buf_size)
	108
	109	/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */
	110	#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \
	111	memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \
	112	payload, pkt_len); \
	113	a->mpa_tx.buf_len += pkt_len; \
	114	if (!a->mpa_tx.pkt_cnt) \
	115	a->mpa_tx.start_port = port; \
	116	if (a->mpa_tx.start_port <= port) \
	117	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt)); \
	118	else \
05889f82 AK	119	a->mpa_tx.ports \|= (1<<(a->mpa_tx.pkt_cnt+1+ \
05889f82 AK	120	(a->max_ports - \
5e6e3a92 BZ	121	a->mp_end_port))); \
5e6e3a92 BZ	122	a->mpa_tx.pkt_cnt++; \
da951c24	123	} while (0)
5e6e3a92 BZ	124
	125	/* SDIO Tx aggregation limit ? */
	126	#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \
	127	(a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit)
	128
	129	/* SDIO Tx aggregation port limit ? */
	130	#define MP_TX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_wr_port < \
05889f82	131	a->mpa_tx.start_port) && (((a->max_ports -\
5e6e3a92	132	a->mpa_tx.start_port) + a->curr_wr_port) >= \
05889f82	133	a->mp_agg_pkt_limit))
5e6e3a92 BZ	134
	135	/* Reset SDIO Tx aggregation buffer parameters */
	136	#define MP_TX_AGGR_BUF_RESET(a) do { \
	137	a->mpa_tx.pkt_cnt = 0; \
	138	a->mpa_tx.buf_len = 0; \
	139	a->mpa_tx.ports = 0; \
	140	a->mpa_tx.start_port = 0; \
da951c24	141	} while (0)
5e6e3a92 BZ	142
	143	/* SDIO Rx aggregation limit ? */
	144	#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \
	145	(a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit)
	146
	147	/* SDIO Tx aggregation port limit ? */
	148	#define MP_RX_AGGR_PORT_LIMIT_REACHED(a) ((a->curr_rd_port < \
05889f82	149	a->mpa_rx.start_port) && (((a->max_ports -\
5e6e3a92	150	a->mpa_rx.start_port) + a->curr_rd_port) >= \
05889f82	151	a->mp_agg_pkt_limit))
5e6e3a92 BZ	152
	153	/* SDIO Rx aggregation in progress ? */
	154	#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0)
	155
	156	/* SDIO Rx aggregation buffer room for next packet ? */
	157	#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \
	158	((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size)
	159
	160	/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */
	161	#define MP_RX_AGGR_SETUP(a, skb, port) do { \
	162	a->mpa_rx.buf_len += skb->len; \
	163	if (!a->mpa_rx.pkt_cnt) \
	164	a->mpa_rx.start_port = port; \
	165	if (a->mpa_rx.start_port <= port) \
	166	a->mpa_rx.ports \|= (1<<(a->mpa_rx.pkt_cnt)); \
	167	else \
	168	a->mpa_rx.ports \|= (1<<(a->mpa_rx.pkt_cnt+1)); \
	169	a->mpa_rx.skb_arr[a->mpa_rx.pkt_cnt] = skb; \
	170	a->mpa_rx.len_arr[a->mpa_rx.pkt_cnt] = skb->len; \
	171	a->mpa_rx.pkt_cnt++; \
da951c24	172	} while (0)
5e6e3a92 BZ	173
	174	/* Reset SDIO Rx aggregation buffer parameters */
	175	#define MP_RX_AGGR_BUF_RESET(a) do { \
	176	a->mpa_rx.pkt_cnt = 0; \
	177	a->mpa_rx.buf_len = 0; \
	178	a->mpa_rx.ports = 0; \
	179	a->mpa_rx.start_port = 0; \
da951c24	180	} while (0)
5e6e3a92 BZ	181
	182
	183	/* data structure for SDIO MPA TX */
	184	struct mwifiex_sdio_mpa_tx {
	185	/* multiport tx aggregation buffer pointer */
	186	u8 *buf;
	187	u32 buf_len;
	188	u32 pkt_cnt;
5ac253d5	189	u32 ports;
5e6e3a92 BZ	190	u16 start_port;
	191	u8 enabled;
	192	u32 buf_size;
	193	u32 pkt_aggr_limit;
	194	};
	195
	196	struct mwifiex_sdio_mpa_rx {
	197	u8 *buf;
	198	u32 buf_len;
	199	u32 pkt_cnt;
5ac253d5	200	u32 ports;
5e6e3a92 BZ	201	u16 start_port;
	202
	203	struct sk_buff *skb_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
	204	u32 len_arr[SDIO_MP_AGGR_DEF_PKT_LIMIT];
	205
	206	u8 enabled;
	207	u32 buf_size;
	208	u32 pkt_aggr_limit;
	209	};
	210
	211	int mwifiex_bus_register(void);
	212	void mwifiex_bus_unregister(void);
	213
05889f82 AK	214	struct mwifiex_sdio_card_reg {
	215	u8 start_rd_port;
	216	u8 start_wr_port;
	217	u8 base_0_reg;
	218	u8 base_1_reg;
	219	u8 poll_reg;
	220	u8 host_int_enable;
	221	u8 status_reg_0;
	222	u8 status_reg_1;
	223	u8 sdio_int_mask;
	224	u32 data_port_mask;
	225	u8 max_mp_regs;
	226	u8 rd_bitmap_l;
	227	u8 rd_bitmap_u;
	228	u8 wr_bitmap_l;
	229	u8 wr_bitmap_u;
	230	u8 rd_len_p0_l;
	231	u8 rd_len_p0_u;
	232	u8 card_misc_cfg_reg;
	233	};
	234
5e6e3a92 BZ	235	struct sdio_mmc_card {
	236	struct sdio_func *func;
	237	struct mwifiex_adapter *adapter;
	238
05889f82 AK	239	const char *firmware;
	240	const struct mwifiex_sdio_card_reg *reg;
	241	u8 max_ports;
	242	u8 mp_agg_pkt_limit;
	243
5ac253d5 AK	244	u32 mp_rd_bitmap;
5ac253d5 AK	245	u32 mp_wr_bitmap;
5e6e3a92 BZ	246
5e6e3a92 BZ	247	u16 mp_end_port;
5ac253d5	248	u32 mp_data_port_mask;
5e6e3a92 BZ	249
	250	u8 curr_rd_port;
	251	u8 curr_wr_port;
	252
	253	u8 *mp_regs;
	254
	255	struct mwifiex_sdio_mpa_tx mpa_tx;
	256	struct mwifiex_sdio_mpa_rx mpa_rx;
	257	};
d930faee	258
05889f82 AK	259	struct mwifiex_sdio_device {
	260	const char *firmware;
	261	const struct mwifiex_sdio_card_reg *reg;
	262	u8 max_ports;
	263	u8 mp_agg_pkt_limit;
	264	};
	265
	266	static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = {
	267	.start_rd_port = 1,
	268	.start_wr_port = 1,
	269	.base_0_reg = 0x0040,
	270	.base_1_reg = 0x0041,
	271	.poll_reg = 0x30,
	272	.host_int_enable = UP_LD_HOST_INT_MASK \| DN_LD_HOST_INT_MASK,
	273	.status_reg_0 = 0x60,
	274	.status_reg_1 = 0x61,
	275	.sdio_int_mask = 0x3f,
	276	.data_port_mask = 0x0000fffe,
	277	.max_mp_regs = 64,
	278	.rd_bitmap_l = 0x04,
	279	.rd_bitmap_u = 0x05,
	280	.wr_bitmap_l = 0x06,
	281	.wr_bitmap_u = 0x07,
	282	.rd_len_p0_l = 0x08,
	283	.rd_len_p0_u = 0x09,
	284	.card_misc_cfg_reg = 0x6c,
	285	};
	286
	287	static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = {
	288	.firmware = SD8786_DEFAULT_FW_NAME,
	289	.reg = &mwifiex_reg_sd87xx,
	290	.max_ports = 16,
	291	.mp_agg_pkt_limit = 8,
	292	};
	293
	294	static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = {
	295	.firmware = SD8787_DEFAULT_FW_NAME,
	296	.reg = &mwifiex_reg_sd87xx,
	297	.max_ports = 16,
	298	.mp_agg_pkt_limit = 8,
	299	};
	300
	301	static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = {
	302	.firmware = SD8797_DEFAULT_FW_NAME,
	303	.reg = &mwifiex_reg_sd87xx,
	304	.max_ports = 16,
	305	.mp_agg_pkt_limit = 8,
	306	};
	307
d930faee AK	308	/*
	309	* .cmdrsp_complete handler
	310	*/
	311	static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter,
	312	struct sk_buff *skb)
	313	{
	314	dev_kfree_skb_any(skb);
	315	return 0;
	316	}
	317
	318	/*
	319	* .event_complete handler
	320	*/
	321	static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter,
	322	struct sk_buff *skb)
	323	{
	324	dev_kfree_skb_any(skb);
	325	return 0;
	326	}
	327
5e6e3a92	328	#endif /* _MWIFIEX_SDIO_H */