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ath10k: embed ar_pci inside ar
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
a6b7a407 12#include <linux/interrupt.h>
a66098da
LB		 13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
5a0e3ad6 22#include <linux/slab.h>
a66098da
LB		 23#include <net/mac80211.h>
24#include <linux/moduleparam.h>
25#include <linux/firmware.h>
26#include <linux/workqueue.h>
27
28#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29#define MWL8K_NAME KBUILD_MODNAME
00e8e692 30#define MWL8K_VERSION "0.13"
a66098da 31
0863ade8 32/* Module parameters */
eb939922 33static bool ap_mode_default;
0863ade8
BC		 34module_param(ap_mode_default, bool, 0);
35MODULE_PARM_DESC(ap_mode_default,
36 "Set to 1 to make ap mode the default instead of sta mode");
37
a66098da
LB		 38/* Register definitions */
39#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 40#define MWL8K_MODE_STA 0x0000005a
41#define MWL8K_MODE_AP 0x000000a5
a66098da 42#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 43#define MWL8K_FWSTA_READY 0xf0f1f2f4
44#define MWL8K_FWAP_READY 0xf1f2f4a5
45#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 46#define MWL8K_HIU_SCRATCH 0x00000c40
47
48/* Host->device communications */
49#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 54#define MWL8K_H2A_INT_DUMMY (1 << 20)
55#define MWL8K_H2A_INT_RESET (1 << 15)
56#define MWL8K_H2A_INT_DOORBELL (1 << 1)
57#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 58
59/* Device->host communications */
60#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b 65#define MWL8K_A2H_INT_DUMMY (1 << 20)
3aefc37e 66#define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
ce9e2e1b
LB		 67#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
68#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
69#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
70#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
71#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
72#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
73#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
74#define MWL8K_A2H_INT_RX_READY (1 << 1)
75#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da 76
566875db
PN		 77/* HW micro second timer register
78 * located at offset 0xA600. This
79 * will be used to timestamp tx
80 * packets.
81 */
82
83#define MWL8K_HW_TIMER_REGISTER 0x0000a600
4c924f42
YAP		 84#define BBU_RXRDY_CNT_REG 0x0000a860
85#define NOK_CCA_CNT_REG 0x0000a6a0
86#define BBU_AVG_NOISE_VAL 0x67
566875db 87
a66098da
LB		 88#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
89 MWL8K_A2H_INT_CHNL_SWITCHED | \
90 MWL8K_A2H_INT_QUEUE_EMPTY | \
91 MWL8K_A2H_INT_RADAR_DETECT | \
92 MWL8K_A2H_INT_RADIO_ON | \
93 MWL8K_A2H_INT_RADIO_OFF | \
94 MWL8K_A2H_INT_MAC_EVENT | \
95 MWL8K_A2H_INT_OPC_DONE | \
96 MWL8K_A2H_INT_RX_READY | \
3aefc37e
NS		 97 MWL8K_A2H_INT_TX_DONE | \
98 MWL8K_A2H_INT_BA_WATCHDOG)
a66098da 99
a66098da 100#define MWL8K_RX_QUEUES 1
e600707b 101#define MWL8K_TX_WMM_QUEUES 4
8a7a578c 102#define MWL8K_MAX_AMPDU_QUEUES 8
e600707b
BC		 103#define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
104#define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
a66098da 105
7fb978b7
YAP		 106/* txpriorities are mapped with hw queues.
107 * Each hw queue has a txpriority.
108 */
109#define TOTAL_HW_TX_QUEUES 8
110
111/* Each HW queue can have one AMPDU stream.
112 * But, because one of the hw queue is reserved,
113 * maximum AMPDU queues that can be created are
114 * one short of total tx queues.
115 */
116#define MWL8K_NUM_AMPDU_STREAMS (TOTAL_HW_TX_QUEUES - 1)
117
031eb464
YAP		 118#define MWL8K_NUM_CHANS 18
119
54bc3a0d
LB		 120struct rxd_ops {
121 int rxd_size;
122 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
123 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 124 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 125 __le16 *qos, s8 *noise);
54bc3a0d
LB		 126};
127
45a390dd 128struct mwl8k_device_info {
a74b295e
LB		 129 char *part_name;
130 char *helper_image;
0863ade8
BC		 131 char *fw_image_sta;
132 char *fw_image_ap;
89a91f4f 133 struct rxd_ops *ap_rxd_ops;
952a0e96 134 u32 fw_api_ap;
45a390dd
LB		 135};
136
a66098da 137struct mwl8k_rx_queue {
45eb400d 138 int rxd_count;
a66098da
LB		 139
140 /* hw receives here */
45eb400d 141 int head;
a66098da
LB		 142
143 /* refill descs here */
45eb400d 144 int tail;
a66098da 145
54bc3a0d 146 void *rxd;
45eb400d 147 dma_addr_t rxd_dma;
788838eb
LB		 148 struct {
149 struct sk_buff *skb;
53b1b3e1 150 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 151 } *buf;
a66098da
LB		 152};
153
a66098da
LB		 154struct mwl8k_tx_queue {
155 /* hw transmits here */
45eb400d 156 int head;
a66098da
LB		 157
158 /* sw appends here */
45eb400d 159 int tail;
a66098da 160
8ccbc3b8 161 unsigned int len;
45eb400d
LB		 162 struct mwl8k_tx_desc *txd;
163 dma_addr_t txd_dma;
164 struct sk_buff **skb;
a66098da
LB		 165};
166
ac109fd0
BC		 167enum {
168 AMPDU_NO_STREAM,
169 AMPDU_STREAM_NEW,
170 AMPDU_STREAM_IN_PROGRESS,
171 AMPDU_STREAM_ACTIVE,
172};
173
5faa1aff
NS		 174struct mwl8k_ampdu_stream {
175 struct ieee80211_sta *sta;
176 u8 tid;
177 u8 state;
178 u8 idx;
5faa1aff
NS		 179};
180
a66098da 181struct mwl8k_priv {
a66098da 182 struct ieee80211_hw *hw;
a66098da 183 struct pci_dev *pdev;
bf3ca7f7 184 int irq;
a66098da 185
45a390dd
LB		 186 struct mwl8k_device_info *device_info;
187
be695fc4
LB		 188 void __iomem *sram;
189 void __iomem *regs;
190
191 /* firmware */
d1f9e41d
BC		 192 const struct firmware *fw_helper;
193 const struct firmware *fw_ucode;
a66098da 194
be695fc4
LB		 195 /* hardware/firmware parameters */
196 bool ap_fw;
197 struct rxd_ops *rxd_ops;
777ad375
LB		 198 struct ieee80211_supported_band band_24;
199 struct ieee80211_channel channels_24[14];
3f524559 200 struct ieee80211_rate rates_24[13];
4eae9edd
LB		 201 struct ieee80211_supported_band band_50;
202 struct ieee80211_channel channels_50[4];
3f524559 203 struct ieee80211_rate rates_50[8];
ee0ddf18
LB		 204 u32 ap_macids_supported;
205 u32 sta_macids_supported;
be695fc4 206
8a7a578c
BC		 207 /* Ampdu stream information */
208 u8 num_ampdu_queues;
ac109fd0
BC		 209 spinlock_t stream_lock;
210 struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
3aefc37e 211 struct work_struct watchdog_ba_handle;
8a7a578c 212
618952a7
LB		 213 /* firmware access */
214 struct mutex fw_mutex;
215 struct task_struct *fw_mutex_owner;
6b6accc3 216 struct task_struct *hw_restart_owner;
618952a7 217 int fw_mutex_depth;
618952a7
LB		 218 struct completion *hostcmd_wait;
219
c27a54d3
YAP		 220 atomic_t watchdog_event_pending;
221
a66098da
LB		 222 /* lock held over TX and TX reap */
223 spinlock_t tx_lock;
a66098da 224
88de754a
LB		 225 /* TX quiesce completion, protected by fw_mutex and tx_lock */
226 struct completion *tx_wait;
227
f5bb87cf 228 /* List of interfaces. */
ee0ddf18 229 u32 macids_used;
f5bb87cf 230 struct list_head vif_list;
a66098da 231
a66098da
LB		 232 /* power management status cookie from firmware */
233 u32 *cookie;
234 dma_addr_t cookie_dma;
235
236 u16 num_mcaddrs;
a66098da 237 u8 hw_rev;
2aa7b01f 238 u32 fw_rev;
c3f251a3 239 u32 caps;
a66098da
LB		 240
241 /*
242 * Running count of TX packets in flight, to avoid
243 * iterating over the transmit rings each time.
244 */
245 int pending_tx_pkts;
246
247 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
e600707b
BC		 248 struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
249 u32 txq_offset[MWL8K_MAX_TX_QUEUES];
a66098da 250
c46563b7 251 bool radio_on;
68ce3884 252 bool radio_short_preamble;
a43c49a8 253 bool sniffer_enabled;
0439b1f5 254 bool wmm_enabled;
a66098da 255
a66098da
LB		 256 /* XXX need to convert this to handle multiple interfaces */
257 bool capture_beacon;
d89173f2 258 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 259 struct sk_buff *beacon_skb;
260
261 /*
262 * This FJ worker has to be global as it is scheduled from the
263 * RX handler. At this point we don't know which interface it
264 * belongs to until the list of bssids waiting to complete join
265 * is checked.
266 */
267 struct work_struct finalize_join_worker;
268
1e9f9de3
LB		 269 /* Tasklet to perform TX reclaim. */
270 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 271
272 /* Tasklet to perform RX. */
273 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 274
275 /* Most recently reported noise in dBm */
276 s8 noise;
0863ade8
BC		 277
278 /*
279 * preserve the queue configurations so they can be restored if/when
280 * the firmware image is swapped.
281 */
e600707b 282 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
99020471 283
6b6accc3
YAP		 284 /* To perform the task of reloading the firmware */
285 struct work_struct fw_reload;
286 bool hw_restart_in_progress;
287
99020471
BC		 288 /* async firmware loading state */
289 unsigned fw_state;
290 char *fw_pref;
291 char *fw_alt;
98929824 292 bool is_8764;
99020471 293 struct completion firmware_loading_complete;
e882efc9
YAP		 294
295 /* bitmap of running BSSes */
296 u32 running_bsses;
4c924f42
YAP		 297
298 /* ACS related */
299 bool sw_scan_start;
031eb464
YAP		 300 struct ieee80211_channel *acs_chan;
301 unsigned long channel_time;
302 struct survey_info survey[MWL8K_NUM_CHANS];
a66098da
LB		 303};
304
e53d9b96
NS		 305#define MAX_WEP_KEY_LEN 13
306#define NUM_WEP_KEYS 4
307
a66098da
LB		 308/* Per interface specific private data */
309struct mwl8k_vif {
f5bb87cf
LB		 310 struct list_head list;
311 struct ieee80211_vif *vif;
312
f57ca9c1
LB		 313 /* Firmware macid for this vif. */
314 int macid;
315
c2c2b12a 316 /* Non AMPDU sequence number assigned by driver. */
a680400e 317 u16 seqno;
e53d9b96
NS		 318
319 /* Saved WEP keys */
320 struct {
321 u8 enabled;
322 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
323 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS		 324
325 /* BSSID */
326 u8 bssid[ETH_ALEN];
327
328 /* A flag to indicate is HW crypto is enabled for this bssid */
329 bool is_hw_crypto_enabled;
a66098da 330};
a94cc97e 331#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
fcdc403c 332#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
a66098da 333
d0805c1c
BC		 334struct tx_traffic_info {
335 u32 start_time;
336 u32 pkts;
337};
338
339#define MWL8K_MAX_TID 8
a680400e
LB		 340struct mwl8k_sta {
341 /* Index into station database. Returned by UPDATE_STADB. */
342 u8 peer_id;
17033543 343 u8 is_ampdu_allowed;
d0805c1c 344 struct tx_traffic_info tx_stats[MWL8K_MAX_TID];
a680400e
LB		 345};
346#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
347
777ad375 348static const struct ieee80211_channel mwl8k_channels_24[] = {
d786f67e
JG		 349 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412, .hw_value = 1, },
350 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417, .hw_value = 2, },
351 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422, .hw_value = 3, },
352 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427, .hw_value = 4, },
353 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432, .hw_value = 5, },
354 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437, .hw_value = 6, },
355 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442, .hw_value = 7, },
356 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447, .hw_value = 8, },
357 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452, .hw_value = 9, },
358 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457, .hw_value = 10, },
359 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462, .hw_value = 11, },
360 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467, .hw_value = 12, },
361 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472, .hw_value = 13, },
362 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 363};
364
777ad375 365static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 366 { .bitrate = 10, .hw_value = 2, },
367 { .bitrate = 20, .hw_value = 4, },
368 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 369 { .bitrate = 110, .hw_value = 22, },
370 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 371 { .bitrate = 60, .hw_value = 12, },
372 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 373 { .bitrate = 120, .hw_value = 24, },
374 { .bitrate = 180, .hw_value = 36, },
375 { .bitrate = 240, .hw_value = 48, },
376 { .bitrate = 360, .hw_value = 72, },
377 { .bitrate = 480, .hw_value = 96, },
378 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 379};
380
4eae9edd 381static const struct ieee80211_channel mwl8k_channels_50[] = {
d786f67e
JG		 382 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5180, .hw_value = 36, },
383 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5200, .hw_value = 40, },
384 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5220, .hw_value = 44, },
385 { .band = IEEE80211_BAND_5GHZ, .center_freq = 5240, .hw_value = 48, },
4eae9edd
LB		 386};
387
388static const struct ieee80211_rate mwl8k_rates_50[] = {
389 { .bitrate = 60, .hw_value = 12, },
390 { .bitrate = 90, .hw_value = 18, },
391 { .bitrate = 120, .hw_value = 24, },
392 { .bitrate = 180, .hw_value = 36, },
393 { .bitrate = 240, .hw_value = 48, },
394 { .bitrate = 360, .hw_value = 72, },
395 { .bitrate = 480, .hw_value = 96, },
396 { .bitrate = 540, .hw_value = 108, },
4eae9edd
LB		 397};
398
a66098da 399/* Set or get info from Firmware */
a66098da 400#define MWL8K_CMD_GET 0x0000
41fdf097
NS		 401#define MWL8K_CMD_SET 0x0001
402#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB		 403
404/* Firmware command codes */
405#define MWL8K_CMD_CODE_DNLD 0x0001
406#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 407#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 408#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
409#define MWL8K_CMD_GET_STAT 0x0014
c3015313 410#define MWL8K_CMD_BBP_REG_ACCESS 0x001a
ff45fc60
LB		 411#define MWL8K_CMD_RADIO_CONTROL 0x001c
412#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 413#define MWL8K_CMD_TX_POWER 0x001f
08b06347 414#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 415#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 416#define MWL8K_CMD_SET_PRE_SCAN 0x0107
417#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 418#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
419#define MWL8K_CMD_SET_AID 0x010d
420#define MWL8K_CMD_SET_RATE 0x0110
421#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
422#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 423#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 424#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
425#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 426#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 427#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 428#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 429#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 430#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
3aefc37e 431#define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
197a4e4e 432#define MWL8K_CMD_DEL_MAC_ADDR 0x0206 /* per-vif */
aa21d0f6
LB		 433#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
434#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
fcdc403c 435#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
ff45fc60 436#define MWL8K_CMD_UPDATE_STADB 0x1123
5faa1aff 437#define MWL8K_CMD_BASTREAM 0x1125
a66098da 438
b603742f 439static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 440{
b603742f
JL		 441 u16 command = le16_to_cpu(cmd);
442
a66098da
LB		 443#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
444 snprintf(buf, bufsize, "%s", #x);\
445 return buf;\
446 } while (0)
b603742f 447 switch (command & ~0x8000) {
a66098da
LB		 448 MWL8K_CMDNAME(CODE_DNLD);
449 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 450 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 451 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
452 MWL8K_CMDNAME(GET_STAT);
453 MWL8K_CMDNAME(RADIO_CONTROL);
454 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 455 MWL8K_CMDNAME(TX_POWER);
08b06347 456 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 457 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 458 MWL8K_CMDNAME(SET_PRE_SCAN);
459 MWL8K_CMDNAME(SET_POST_SCAN);
460 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 461 MWL8K_CMDNAME(SET_AID);
462 MWL8K_CMDNAME(SET_RATE);
463 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
464 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 465 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 466 MWL8K_CMDNAME(SET_EDCA_PARAMS);
467 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 468 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 469 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 470 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 471 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 472 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 473 MWL8K_CMDNAME(BSS_START);
3f5610ff 474 MWL8K_CMDNAME(SET_NEW_STN);
fcdc403c 475 MWL8K_CMDNAME(UPDATE_ENCRYPTION);
ff45fc60 476 MWL8K_CMDNAME(UPDATE_STADB);
5faa1aff 477 MWL8K_CMDNAME(BASTREAM);
3aefc37e 478 MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
a66098da
LB		 479 default:
480 snprintf(buf, bufsize, "0x%x", cmd);
481 }
482#undef MWL8K_CMDNAME
483
484 return buf;
485}
486
487/* Hardware and firmware reset */
488static void mwl8k_hw_reset(struct mwl8k_priv *priv)
489{
490 iowrite32(MWL8K_H2A_INT_RESET,
491 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
492 iowrite32(MWL8K_H2A_INT_RESET,
493 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
494 msleep(20);
495}
496
497/* Release fw image */
d1f9e41d 498static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB		 499{
500 if (*fw == NULL)
501 return;
502 release_firmware(*fw);
503 *fw = NULL;
504}
505
506static void mwl8k_release_firmware(struct mwl8k_priv *priv)
507{
22be40d9
LB		 508 mwl8k_release_fw(&priv->fw_ucode);
509 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 510}
511
99020471
BC		 512/* states for asynchronous f/w loading */
513static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
514enum {
515 FW_STATE_INIT = 0,
516 FW_STATE_LOADING_PREF,
517 FW_STATE_LOADING_ALT,
518 FW_STATE_ERROR,
519};
520
a66098da
LB		 521/* Request fw image */
522static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 523 const char *fname, const struct firmware **fw,
99020471 524 bool nowait)
a66098da
LB		 525{
526 /* release current image */
527 if (*fw != NULL)
528 mwl8k_release_fw(fw);
529
99020471
BC		 530 if (nowait)
531 return request_firmware_nowait(THIS_MODULE, 1, fname,
532 &priv->pdev->dev, GFP_KERNEL,
533 priv, mwl8k_fw_state_machine);
534 else
d1f9e41d 535 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB		 536}
537
99020471
BC		 538static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
539 bool nowait)
a66098da 540{
a74b295e 541 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 542 int rc;
543
a74b295e 544 if (di->helper_image != NULL) {
99020471
BC		 545 if (nowait)
546 rc = mwl8k_request_fw(priv, di->helper_image,
547 &priv->fw_helper, true);
548 else
549 rc = mwl8k_request_fw(priv, di->helper_image,
550 &priv->fw_helper, false);
551 if (rc)
552 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
553 pci_name(priv->pdev), di->helper_image);
554
555 if (rc || nowait)
a74b295e 556 return rc;
a66098da
LB		 557 }
558
99020471
BC		 559 if (nowait) {
560 /*
561 * if we get here, no helper image is needed. Skip the
562 * FW_STATE_INIT state.
563 */
564 priv->fw_state = FW_STATE_LOADING_PREF;
565 rc = mwl8k_request_fw(priv, fw_image,
566 &priv->fw_ucode,
567 true);
568 } else
569 rc = mwl8k_request_fw(priv, fw_image,
570 &priv->fw_ucode, false);
a66098da 571 if (rc) {
c2c357ce 572 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 573 pci_name(priv->pdev), fw_image);
22be40d9 574 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 575 return rc;
576 }
577
578 return 0;
579}
580
581struct mwl8k_cmd_pkt {
582 __le16 code;
583 __le16 length;
f57ca9c1
LB		 584 __u8 seq_num;
585 __u8 macid;
a66098da
LB		 586 __le16 result;
587 char payload[0];
ba2d3587 588} __packed;
a66098da
LB		 589
590/*
591 * Firmware loading.
592 */
593static int
594mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
595{
596 void __iomem *regs = priv->regs;
597 dma_addr_t dma_addr;
a66098da
LB		 598 int loops;
599
600 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
601 if (pci_dma_mapping_error(priv->pdev, dma_addr))
602 return -ENOMEM;
603
604 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
605 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
606 iowrite32(MWL8K_H2A_INT_DOORBELL,
607 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
608 iowrite32(MWL8K_H2A_INT_DUMMY,
609 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
610
a66098da
LB		 611 loops = 1000;
612 do {
613 u32 int_code;
98929824
NS		 614 if (priv->is_8764) {
615 int_code = ioread32(regs +
616 MWL8K_HIU_H2A_INTERRUPT_STATUS);
617 if (int_code == 0)
618 break;
619 } else {
620 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
621 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
622 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
623 break;
624 }
a66098da 625 }
3d76e82c 626 cond_resched();
a66098da
LB		 627 udelay(1);
628 } while (--loops);
629
630 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
631
d4b70570 632 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 633}
634
635static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
636 const u8 *data, size_t length)
637{
638 struct mwl8k_cmd_pkt *cmd;
639 int done;
640 int rc = 0;
641
642 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
643 if (cmd == NULL)
644 return -ENOMEM;
645
646 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
647 cmd->seq_num = 0;
f57ca9c1 648 cmd->macid = 0;
a66098da
LB		 649 cmd->result = 0;
650
651 done = 0;
652 while (length) {
653 int block_size = length > 256 ? 256 : length;
654
655 memcpy(cmd->payload, data + done, block_size);
656 cmd->length = cpu_to_le16(block_size);
657
658 rc = mwl8k_send_fw_load_cmd(priv, cmd,
659 sizeof(*cmd) + block_size);
660 if (rc)
661 break;
662
663 done += block_size;
664 length -= block_size;
665 }
666
667 if (!rc) {
668 cmd->length = 0;
669 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
670 }
671
672 kfree(cmd);
673
674 return rc;
675}
676
677static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
678 const u8 *data, size_t length)
679{
680 unsigned char *buffer;
681 int may_continue, rc = 0;
682 u32 done, prev_block_size;
683
684 buffer = kmalloc(1024, GFP_KERNEL);
685 if (buffer == NULL)
686 return -ENOMEM;
687
688 done = 0;
689 prev_block_size = 0;
690 may_continue = 1000;
691 while (may_continue > 0) {
692 u32 block_size;
693
694 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
695 if (block_size & 1) {
696 block_size &= ~1;
697 may_continue--;
698 } else {
699 done += prev_block_size;
700 length -= prev_block_size;
701 }
702
703 if (block_size > 1024 || block_size > length) {
704 rc = -EOVERFLOW;
705 break;
706 }
707
708 if (length == 0) {
709 rc = 0;
710 break;
711 }
712
713 if (block_size == 0) {
714 rc = -EPROTO;
715 may_continue--;
716 udelay(1);
717 continue;
718 }
719
720 prev_block_size = block_size;
721 memcpy(buffer, data + done, block_size);
722
723 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
724 if (rc)
725 break;
726 }
727
728 if (!rc && length != 0)
729 rc = -EREMOTEIO;
730
731 kfree(buffer);
732
733 return rc;
734}
735
c2c357ce 736static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 737{
c2c357ce 738 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 739 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 740 int rc;
741 int loops;
742
98929824 743 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4) && !priv->is_8764) {
d1f9e41d 744 const struct firmware *helper = priv->fw_helper;
a66098da 745
c2c357ce
LB		 746 if (helper == NULL) {
747 printk(KERN_ERR "%s: helper image needed but none "
748 "given\n", pci_name(priv->pdev));
749 return -EINVAL;
750 }
a66098da 751
c2c357ce 752 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 753 if (rc) {
754 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 755 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 756 return rc;
757 }
ba30c4a5 758 msleep(20);
a66098da 759
c2c357ce 760 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 761 } else {
98929824
NS		 762 if (priv->is_8764)
763 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
764 else
765 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 766 }
767
768 if (rc) {
c2c357ce
LB		 769 printk(KERN_ERR "%s: unable to load firmware image\n",
770 pci_name(priv->pdev));
a66098da
LB		 771 return rc;
772 }
773
89a91f4f 774 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 775
89b872e2 776 loops = 500000;
a66098da 777 do {
eae74e65
LB		 778 u32 ready_code;
779
780 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
781 if (ready_code == MWL8K_FWAP_READY) {
3db1cd5c 782 priv->ap_fw = true;
eae74e65
LB		 783 break;
784 } else if (ready_code == MWL8K_FWSTA_READY) {
3db1cd5c 785 priv->ap_fw = false;
a66098da 786 break;
eae74e65
LB		 787 }
788
789 cond_resched();
a66098da
LB		 790 udelay(1);
791 } while (--loops);
792
793 return loops ? 0 : -ETIMEDOUT;
794}
795
796
a66098da
LB		 797/* DMA header used by firmware and hardware. */
798struct mwl8k_dma_data {
799 __le16 fwlen;
800 struct ieee80211_hdr wh;
20f09c3d 801 char data[0];
ba2d3587 802} __packed;
a66098da
LB		 803
804/* Routines to add/remove DMA header from skb. */
20f09c3d 805static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 806{
20f09c3d
LB		 807 struct mwl8k_dma_data *tr;
808 int hdrlen;
809
810 tr = (struct mwl8k_dma_data *)skb->data;
811 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
812
813 if (hdrlen != sizeof(tr->wh)) {
814 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
815 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
816 *((__le16 *)(tr->data - 2)) = qos;
817 } else {
818 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
819 }
a66098da 820 }
20f09c3d
LB		 821
822 if (hdrlen != sizeof(*tr))
823 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 824}
825
ff776cec
YAP		 826#define REDUCED_TX_HEADROOM 8
827
252486a1 828static void
e4eefec7
YAP		 829mwl8k_add_dma_header(struct mwl8k_priv *priv, struct sk_buff *skb,
830 int head_pad, int tail_pad)
a66098da
LB		 831{
832 struct ieee80211_hdr *wh;
ca009301 833 int hdrlen;
252486a1 834 int reqd_hdrlen;
a66098da
LB		 835 struct mwl8k_dma_data *tr;
836
ca009301
LB		 837 /*
838 * Add a firmware DMA header; the firmware requires that we
839 * present a 2-byte payload length followed by a 4-address
840 * header (without QoS field), followed (optionally) by any
841 * WEP/ExtIV header (but only filled in for CCMP).
842 */
a66098da 843 wh = (struct ieee80211_hdr *)skb->data;
ca009301 844
a66098da 845 hdrlen = ieee80211_hdrlen(wh->frame_control);
ff776cec
YAP		 846
847 /*
848 * Check if skb_resize is required because of
849 * tx_headroom adjustment.
850 */
851 if (priv->ap_fw && (hdrlen < (sizeof(struct ieee80211_cts)
852 + REDUCED_TX_HEADROOM))) {
853 if (pskb_expand_head(skb, REDUCED_TX_HEADROOM, 0, GFP_ATOMIC)) {
854
855 wiphy_err(priv->hw->wiphy,
856 "Failed to reallocate TX buffer\n");
857 return;
858 }
859 skb->truesize += REDUCED_TX_HEADROOM;
860 }
861
e4eefec7 862 reqd_hdrlen = sizeof(*tr) + head_pad;
252486a1
NS		 863
864 if (hdrlen != reqd_hdrlen)
865 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 866
ca009301 867 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 868 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB		 869
870 tr = (struct mwl8k_dma_data *)skb->data;
871 if (wh != &tr->wh)
872 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 873 if (hdrlen != sizeof(tr->wh))
874 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 875
876 /*
877 * Firmware length is the length of the fully formed "802.11
878 * payload". That is, everything except for the 802.11 header.
879 * This includes all crypto material including the MIC.
880 */
252486a1 881 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB		 882}
883
ff776cec
YAP		 884static void mwl8k_encapsulate_tx_frame(struct mwl8k_priv *priv,
885 struct sk_buff *skb)
e53d9b96
NS		 886{
887 struct ieee80211_hdr *wh;
888 struct ieee80211_tx_info *tx_info;
889 struct ieee80211_key_conf *key_conf;
890 int data_pad;
e4eefec7 891 int head_pad = 0;
e53d9b96
NS		 892
893 wh = (struct ieee80211_hdr *)skb->data;
894
895 tx_info = IEEE80211_SKB_CB(skb);
896
897 key_conf = NULL;
898 if (ieee80211_is_data(wh->frame_control))
899 key_conf = tx_info->control.hw_key;
900
901 /*
902 * Make sure the packet header is in the DMA header format (4-address
e4eefec7 903 * without QoS), and add head & tail padding when HW crypto is enabled.
e53d9b96
NS		 904 *
905 * We have the following trailer padding requirements:
906 * - WEP: 4 trailer bytes (ICV)
907 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
908 * - CCMP: 8 trailer bytes (MIC)
909 */
910 data_pad = 0;
911 if (key_conf != NULL) {
e4eefec7 912 head_pad = key_conf->iv_len;
e53d9b96
NS		 913 switch (key_conf->cipher) {
914 case WLAN_CIPHER_SUITE_WEP40:
915 case WLAN_CIPHER_SUITE_WEP104:
916 data_pad = 4;
917 break;
918 case WLAN_CIPHER_SUITE_TKIP:
919 data_pad = 12;
920 break;
921 case WLAN_CIPHER_SUITE_CCMP:
922 data_pad = 8;
923 break;
924 }
925 }
e4eefec7 926 mwl8k_add_dma_header(priv, skb, head_pad, data_pad);
e53d9b96 927}
a66098da
LB		 928
929/*
d926dc7d 930 * Packet reception for 88w8366/88w8764 AP firmware.
6f6d1e9a 931 */
d926dc7d 932struct mwl8k_rxd_ap {
6f6d1e9a
LB		 933 __le16 pkt_len;
934 __u8 sq2;
935 __u8 rate;
936 __le32 pkt_phys_addr;
937 __le32 next_rxd_phys_addr;
938 __le16 qos_control;
939 __le16 htsig2;
940 __le32 hw_rssi_info;
941 __le32 hw_noise_floor_info;
942 __u8 noise_floor;
943 __u8 pad0[3];
944 __u8 rssi;
945 __u8 rx_status;
946 __u8 channel;
947 __u8 rx_ctrl;
ba2d3587 948} __packed;
6f6d1e9a 949
d926dc7d
NS		 950#define MWL8K_AP_RATE_INFO_MCS_FORMAT 0x80
951#define MWL8K_AP_RATE_INFO_40MHZ 0x40
952#define MWL8K_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 953
d926dc7d 954#define MWL8K_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 955
d926dc7d
NS		 956/* 8366/8764 AP rx_status bits */
957#define MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
958#define MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
959#define MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
960#define MWL8K_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
961#define MWL8K_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
d9a07d49 962
d926dc7d 963static void mwl8k_rxd_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 964{
d926dc7d 965 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a
LB		 966
967 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
d926dc7d 968 rxd->rx_ctrl = MWL8K_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 969}
970
d926dc7d 971static void mwl8k_rxd_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 972{
d926dc7d 973 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a
LB		 974
975 rxd->pkt_len = cpu_to_le16(len);
976 rxd->pkt_phys_addr = cpu_to_le32(addr);
977 wmb();
978 rxd->rx_ctrl = 0;
979}
980
981static int
d926dc7d
NS		 982mwl8k_rxd_ap_process(void *_rxd, struct ieee80211_rx_status *status,
983 __le16 *qos, s8 *noise)
6f6d1e9a 984{
d926dc7d 985 struct mwl8k_rxd_ap *rxd = _rxd;
6f6d1e9a 986
d926dc7d 987 if (!(rxd->rx_ctrl & MWL8K_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 988 return -1;
989 rmb();
990
991 memset(status, 0, sizeof(*status));
992
993 status->signal = -rxd->rssi;
0d462bbb 994 *noise = -rxd->noise_floor;
6f6d1e9a 995
d926dc7d 996 if (rxd->rate & MWL8K_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 997 status->flag |= RX_FLAG_HT;
d926dc7d 998 if (rxd->rate & MWL8K_AP_RATE_INFO_40MHZ)
8e9f33f0 999 status->flag |= RX_FLAG_40MHZ;
d926dc7d 1000 status->rate_idx = MWL8K_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 1001 } else {
1002 int i;
1003
777ad375
LB		 1004 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
1005 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 1006 status->rate_idx = i;
1007 break;
1008 }
1009 }
1010 }
1011
85478344
LB		 1012 if (rxd->channel > 14) {
1013 status->band = IEEE80211_BAND_5GHZ;
1014 if (!(status->flag & RX_FLAG_HT))
1015 status->rate_idx -= 5;
1016 } else {
1017 status->band = IEEE80211_BAND_2GHZ;
1018 }
59eb21a6
BR		 1019 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1020 status->band);
6f6d1e9a 1021
20f09c3d
LB		 1022 *qos = rxd->qos_control;
1023
d926dc7d
NS		 1024 if ((rxd->rx_status != MWL8K_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
1025 (rxd->rx_status & MWL8K_AP_RXSTAT_DECRYPT_ERR_MASK) &&
1026 (rxd->rx_status & MWL8K_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
d9a07d49
NS		 1027 status->flag |= RX_FLAG_MMIC_ERROR;
1028
6f6d1e9a
LB		 1029 return le16_to_cpu(rxd->pkt_len);
1030}
1031
d926dc7d
NS		 1032static struct rxd_ops rxd_ap_ops = {
1033 .rxd_size = sizeof(struct mwl8k_rxd_ap),
1034 .rxd_init = mwl8k_rxd_ap_init,
1035 .rxd_refill = mwl8k_rxd_ap_refill,
1036 .rxd_process = mwl8k_rxd_ap_process,
6f6d1e9a
LB		 1037};
1038
1039/*
89a91f4f 1040 * Packet reception for STA firmware.
a66098da 1041 */
89a91f4f 1042struct mwl8k_rxd_sta {
a66098da
LB		 1043 __le16 pkt_len;
1044 __u8 link_quality;
1045 __u8 noise_level;
1046 __le32 pkt_phys_addr;
45eb400d 1047 __le32 next_rxd_phys_addr;
a66098da
LB		 1048 __le16 qos_control;
1049 __le16 rate_info;
1050 __le32 pad0[4];
1051 __u8 rssi;
1052 __u8 channel;
1053 __le16 pad1;
1054 __u8 rx_ctrl;
1055 __u8 rx_status;
1056 __u8 pad2[2];
ba2d3587 1057} __packed;
a66098da 1058
89a91f4f
LB		 1059#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
1060#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
1061#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
1062#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
1063#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
1064#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 1065
89a91f4f 1066#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS		 1067#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
1068/* ICV=0 or MIC=1 */
1069#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
1070/* Key is uploaded only in failure case */
1071#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 1072
89a91f4f 1073static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 1074{
89a91f4f 1075 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1076
1077 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 1078 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 1079}
1080
89a91f4f 1081static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 1082{
89a91f4f 1083 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1084
1085 rxd->pkt_len = cpu_to_le16(len);
1086 rxd->pkt_phys_addr = cpu_to_le32(addr);
1087 wmb();
1088 rxd->rx_ctrl = 0;
1089}
1090
1091static int
89a91f4f 1092mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 1093 __le16 *qos, s8 *noise)
54bc3a0d 1094{
89a91f4f 1095 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1096 u16 rate_info;
1097
89a91f4f 1098 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 1099 return -1;
1100 rmb();
1101
1102 rate_info = le16_to_cpu(rxd->rate_info);
1103
1104 memset(status, 0, sizeof(*status));
1105
1106 status->signal = -rxd->rssi;
0d462bbb 1107 *noise = -rxd->noise_level;
89a91f4f
LB		 1108 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
1109 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 1110
89a91f4f 1111 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 1112 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 1113 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1114 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1115 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1116 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1117 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 1118 status->flag |= RX_FLAG_HT;
1119
85478344
LB		 1120 if (rxd->channel > 14) {
1121 status->band = IEEE80211_BAND_5GHZ;
1122 if (!(status->flag & RX_FLAG_HT))
1123 status->rate_idx -= 5;
1124 } else {
1125 status->band = IEEE80211_BAND_2GHZ;
1126 }
59eb21a6
BR		 1127 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1128 status->band);
54bc3a0d 1129
20f09c3d 1130 *qos = rxd->qos_control;
d9a07d49
NS		 1131 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1132 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1133 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1134
54bc3a0d
LB		 1135 return le16_to_cpu(rxd->pkt_len);
1136}
1137
89a91f4f
LB		 1138static struct rxd_ops rxd_sta_ops = {
1139 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1140 .rxd_init = mwl8k_rxd_sta_init,
1141 .rxd_refill = mwl8k_rxd_sta_refill,
1142 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 1143};
1144
1145
a66098da
LB		 1146#define MWL8K_RX_DESCS 256
1147#define MWL8K_RX_MAXSZ 3800
1148
1149static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1150{
1151 struct mwl8k_priv *priv = hw->priv;
1152 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1153 int size;
1154 int i;
1155
45eb400d
LB		 1156 rxq->rxd_count = 0;
1157 rxq->head = 0;
1158 rxq->tail = 0;
a66098da 1159
54bc3a0d 1160 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1161
45eb400d
LB		 1162 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1163 if (rxq->rxd == NULL) {
5db55844 1164 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 1165 return -ENOMEM;
1166 }
45eb400d 1167 memset(rxq->rxd, 0, size);
a66098da 1168
b9ede5f1 1169 rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
788838eb 1170 if (rxq->buf == NULL) {
45eb400d 1171 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 1172 return -ENOMEM;
1173 }
a66098da
LB		 1174
1175 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 1176 int desc_size;
1177 void *rxd;
a66098da 1178 int nexti;
54bc3a0d
LB		 1179 dma_addr_t next_dma_addr;
1180
1181 desc_size = priv->rxd_ops->rxd_size;
1182 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1183
54bc3a0d
LB		 1184 nexti = i + 1;
1185 if (nexti == MWL8K_RX_DESCS)
1186 nexti = 0;
1187 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1188
54bc3a0d 1189 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 1190 }
1191
1192 return 0;
1193}
1194
1195static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1196{
1197 struct mwl8k_priv *priv = hw->priv;
1198 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1199 int refilled;
1200
1201 refilled = 0;
45eb400d 1202 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1203 struct sk_buff *skb;
788838eb 1204 dma_addr_t addr;
a66098da 1205 int rx;
54bc3a0d 1206 void *rxd;
a66098da
LB		 1207
1208 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1209 if (skb == NULL)
1210 break;
1211
788838eb
LB		 1212 addr = pci_map_single(priv->pdev, skb->data,
1213 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1214
54bc3a0d
LB		 1215 rxq->rxd_count++;
1216 rx = rxq->tail++;
1217 if (rxq->tail == MWL8K_RX_DESCS)
1218 rxq->tail = 0;
788838eb 1219 rxq->buf[rx].skb = skb;
53b1b3e1 1220 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1221
1222 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1223 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1224
1225 refilled++;
1226 }
1227
1228 return refilled;
1229}
1230
1231/* Must be called only when the card's reception is completely halted */
1232static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1233{
1234 struct mwl8k_priv *priv = hw->priv;
1235 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1236 int i;
1237
73b46320
BC		 1238 if (rxq->rxd == NULL)
1239 return;
1240
a66098da 1241 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1242 if (rxq->buf[i].skb != NULL) {
1243 pci_unmap_single(priv->pdev,
53b1b3e1 1244 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1245 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1246 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 1247
1248 kfree_skb(rxq->buf[i].skb);
1249 rxq->buf[i].skb = NULL;
a66098da
LB		 1250 }
1251 }
1252
788838eb
LB		 1253 kfree(rxq->buf);
1254 rxq->buf = NULL;
a66098da
LB		 1255
1256 pci_free_consistent(priv->pdev,
54bc3a0d 1257 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1258 rxq->rxd, rxq->rxd_dma);
1259 rxq->rxd = NULL;
a66098da
LB		 1260}
1261
1262
1263/*
1264 * Scan a list of BSSIDs to process for finalize join.
1265 * Allows for extension to process multiple BSSIDs.
1266 */
1267static inline int
1268mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1269{
1270 return priv->capture_beacon &&
1271 ieee80211_is_beacon(wh->frame_control) &&
3f9a79b5 1272 ether_addr_equal_64bits(wh->addr3, priv->capture_bssid);
a66098da
LB		 1273}
1274
3779752d
LB		 1275static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1276 struct sk_buff *skb)
a66098da 1277{
3779752d
LB		 1278 struct mwl8k_priv *priv = hw->priv;
1279
a66098da 1280 priv->capture_beacon = false;
d89173f2 1281 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1282
1283 /*
1284 * Use GFP_ATOMIC as rxq_process is called from
1285 * the primary interrupt handler, memory allocation call
1286 * must not sleep.
1287 */
1288 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1289 if (priv->beacon_skb != NULL)
3779752d 1290 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1291}
1292
d9a07d49
NS		 1293static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1294 u8 *bssid)
1295{
1296 struct mwl8k_vif *mwl8k_vif;
1297
1298 list_for_each_entry(mwl8k_vif,
1299 vif_list, list) {
1300 if (memcmp(bssid, mwl8k_vif->bssid,
1301 ETH_ALEN) == 0)
1302 return mwl8k_vif;
1303 }
1304
1305 return NULL;
1306}
1307
a66098da
LB		 1308static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1309{
1310 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1311 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB		 1312 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1313 int processed;
1314
1315 processed = 0;
45eb400d 1316 while (rxq->rxd_count && limit--) {
a66098da 1317 struct sk_buff *skb;
54bc3a0d
LB		 1318 void *rxd;
1319 int pkt_len;
a66098da 1320 struct ieee80211_rx_status status;
d9a07d49 1321 struct ieee80211_hdr *wh;
20f09c3d 1322 __le16 qos;
a66098da 1323
788838eb 1324 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1325 if (skb == NULL)
1326 break;
54bc3a0d
LB		 1327
1328 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1329
0d462bbb
JL		 1330 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1331 &priv->noise);
54bc3a0d
LB		 1332 if (pkt_len < 0)
1333 break;
1334
788838eb
LB		 1335 rxq->buf[rxq->head].skb = NULL;
1336
1337 pci_unmap_single(priv->pdev,
53b1b3e1 1338 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1339 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1340 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1341
54bc3a0d
LB		 1342 rxq->head++;
1343 if (rxq->head == MWL8K_RX_DESCS)
1344 rxq->head = 0;
1345
45eb400d 1346 rxq->rxd_count--;
a66098da 1347
d9a07d49 1348 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1349
a66098da 1350 /*
c2c357ce
LB		 1351 * Check for a pending join operation. Save a
1352 * copy of the beacon and schedule a tasklet to
1353 * send a FINALIZE_JOIN command to the firmware.
a66098da 1354 */
54bc3a0d 1355 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1356 mwl8k_save_beacon(hw, skb);
a66098da 1357
d9a07d49
NS		 1358 if (ieee80211_has_protected(wh->frame_control)) {
1359
1360 /* Check if hw crypto has been enabled for
1361 * this bss. If yes, set the status flags
1362 * accordingly
1363 */
1364 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1365 wh->addr1);
1366
1367 if (mwl8k_vif != NULL &&
23677ce3 1368 mwl8k_vif->is_hw_crypto_enabled) {
d9a07d49
NS		 1369 /*
1370 * When MMIC ERROR is encountered
1371 * by the firmware, payload is
1372 * dropped and only 32 bytes of
1373 * mwl8k Firmware header is sent
1374 * to the host.
1375 *
1376 * We need to add four bytes of
1377 * key information. In it
1378 * MAC80211 expects keyidx set to
1379 * 0 for triggering Counter
1380 * Measure of MMIC failure.
1381 */
1382 if (status.flag & RX_FLAG_MMIC_ERROR) {
1383 struct mwl8k_dma_data *tr;
1384 tr = (struct mwl8k_dma_data *)skb->data;
1385 memset((void *)&(tr->data), 0, 4);
1386 pkt_len += 4;
1387 }
1388
1389 if (!ieee80211_is_auth(wh->frame_control))
1390 status.flag |= RX_FLAG_IV_STRIPPED |
1391 RX_FLAG_DECRYPTED |
1392 RX_FLAG_MMIC_STRIPPED;
1393 }
1394 }
1395
1396 skb_put(skb, pkt_len);
1397 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB		 1398 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1399 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1400
1401 processed++;
1402 }
1403
1404 return processed;
1405}
1406
1407
1408/*
1409 * Packet transmission.
1410 */
1411
a66098da
LB		 1412#define MWL8K_TXD_STATUS_OK 0x00000001
1413#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1414#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1415#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1416#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1417
e0493a8d
LB		 1418#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1419#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1420#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1421#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1422#define MWL8K_QOS_EOSP 0x0010
1423
a66098da
LB		 1424struct mwl8k_tx_desc {
1425 __le32 status;
1426 __u8 data_rate;
1427 __u8 tx_priority;
1428 __le16 qos_control;
1429 __le32 pkt_phys_addr;
1430 __le16 pkt_len;
d89173f2 1431 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1432 __le32 next_txd_phys_addr;
8a7a578c 1433 __le32 timestamp;
a66098da
LB		 1434 __le16 rate_info;
1435 __u8 peer_id;
a1fe24b0 1436 __u8 tx_frag_cnt;
ba2d3587 1437} __packed;
a66098da
LB		 1438
1439#define MWL8K_TX_DESCS 128
1440
1441static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1442{
1443 struct mwl8k_priv *priv = hw->priv;
1444 struct mwl8k_tx_queue *txq = priv->txq + index;
1445 int size;
1446 int i;
1447
8ccbc3b8 1448 txq->len = 0;
45eb400d
LB		 1449 txq->head = 0;
1450 txq->tail = 0;
a66098da
LB		 1451
1452 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1453
45eb400d
LB		 1454 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1455 if (txq->txd == NULL) {
5db55844 1456 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1457 return -ENOMEM;
1458 }
45eb400d 1459 memset(txq->txd, 0, size);
a66098da 1460
b9ede5f1 1461 txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
45eb400d 1462 if (txq->skb == NULL) {
45eb400d 1463 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1464 return -ENOMEM;
1465 }
a66098da
LB		 1466
1467 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1468 struct mwl8k_tx_desc *tx_desc;
1469 int nexti;
1470
45eb400d 1471 tx_desc = txq->txd + i;
a66098da
LB		 1472 nexti = (i + 1) % MWL8K_TX_DESCS;
1473
1474 tx_desc->status = 0;
45eb400d
LB		 1475 tx_desc->next_txd_phys_addr =
1476 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1477 }
1478
1479 return 0;
1480}
1481
1482static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1483{
1484 iowrite32(MWL8K_H2A_INT_PPA_READY,
1485 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1486 iowrite32(MWL8K_H2A_INT_DUMMY,
1487 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1488 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1489}
1490
7e1112d3 1491static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1492{
7e1112d3
LB		 1493 struct mwl8k_priv *priv = hw->priv;
1494 int i;
1495
e600707b 1496 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
7e1112d3
LB		 1497 struct mwl8k_tx_queue *txq = priv->txq + i;
1498 int fw_owned = 0;
1499 int drv_owned = 0;
1500 int unused = 0;
1501 int desc;
1502
a66098da 1503 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1504 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1505 u32 status;
a66098da 1506
7e1112d3 1507 status = le32_to_cpu(tx_desc->status);
a66098da 1508 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1509 fw_owned++;
a66098da 1510 else
7e1112d3 1511 drv_owned++;
a66098da
LB		 1512
1513 if (tx_desc->pkt_len == 0)
7e1112d3 1514 unused++;
a66098da 1515 }
a66098da 1516
c96c31e4
JP		 1517 wiphy_err(hw->wiphy,
1518 "txq[%d] len=%d head=%d tail=%d "
1519 "fw_owned=%d drv_owned=%d unused=%d\n",
1520 i,
1521 txq->len, txq->head, txq->tail,
1522 fw_owned, drv_owned, unused);
7e1112d3 1523 }
a66098da
LB		 1524}
1525
618952a7 1526/*
88de754a 1527 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1528 */
62abd3cf 1529#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1530
950d5b01 1531static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1532{
a66098da 1533 struct mwl8k_priv *priv = hw->priv;
88de754a 1534 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1535 int retry;
1536 int rc;
a66098da
LB		 1537
1538 might_sleep();
1539
6b6accc3
YAP		 1540 /* Since fw restart is in progress, allow only the firmware
1541 * commands from the restart code and block the other
1542 * commands since they are going to fail in any case since
1543 * the firmware has crashed
1544 */
1545 if (priv->hw_restart_in_progress) {
1546 if (priv->hw_restart_owner == current)
1547 return 0;
1548 else
1549 return -EBUSY;
1550 }
1551
c27a54d3
YAP		 1552 if (atomic_read(&priv->watchdog_event_pending))
1553 return 0;
1554
7e1112d3
LB		 1555 /*
1556 * The TX queues are stopped at this point, so this test
1557 * doesn't need to take ->tx_lock.
1558 */
1559 if (!priv->pending_tx_pkts)
1560 return 0;
1561
bbf71a8f 1562 retry = 1;
7e1112d3
LB		 1563 rc = 0;
1564
a66098da 1565 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1566 priv->tx_wait = &tx_wait;
1567 while (!rc) {
1568 int oldcount;
1569 unsigned long timeout;
a66098da 1570
7e1112d3 1571 oldcount = priv->pending_tx_pkts;
a66098da 1572
7e1112d3 1573 spin_unlock_bh(&priv->tx_lock);
88de754a 1574 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1575 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
c27a54d3
YAP		 1576
1577 if (atomic_read(&priv->watchdog_event_pending)) {
1578 spin_lock_bh(&priv->tx_lock);
1579 priv->tx_wait = NULL;
1580 spin_unlock_bh(&priv->tx_lock);
1581 return 0;
1582 }
1583
a66098da 1584 spin_lock_bh(&priv->tx_lock);
7e1112d3 1585
bbf71a8f 1586 if (timeout || !priv->pending_tx_pkts) {
7e1112d3 1587 WARN_ON(priv->pending_tx_pkts);
ba30c4a5 1588 if (retry)
c96c31e4 1589 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1590 break;
1591 }
1592
bbf71a8f
NS		 1593 if (retry) {
1594 mwl8k_tx_start(priv);
1595 retry = 0;
1596 continue;
1597 }
1598
7e1112d3 1599 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1600 wiphy_notice(hw->wiphy,
1601 "waiting for tx rings to drain (%d -> %d pkts)\n",
1602 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1603 retry = 1;
1604 continue;
1605 }
1606
a66098da 1607 priv->tx_wait = NULL;
a66098da 1608
c96c31e4
JP		 1609 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1610 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3 1611 mwl8k_dump_tx_rings(hw);
6b6accc3
YAP		 1612 priv->hw_restart_in_progress = true;
1613 ieee80211_queue_work(hw, &priv->fw_reload);
7e1112d3
LB		 1614
1615 rc = -ETIMEDOUT;
a66098da 1616 }
9b0b11fb 1617 priv->tx_wait = NULL;
7e1112d3 1618 spin_unlock_bh(&priv->tx_lock);
a66098da 1619
7e1112d3 1620 return rc;
a66098da
LB		 1621}
1622
c23b5a69
LB		 1623#define MWL8K_TXD_SUCCESS(status) \
1624 ((status) & (MWL8K_TXD_STATUS_OK | \
1625 MWL8K_TXD_STATUS_OK_RETRY | \
1626 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1627
a0e7c6cf
NS		 1628static int mwl8k_tid_queue_mapping(u8 tid)
1629{
1630 BUG_ON(tid > 7);
1631
1632 switch (tid) {
1633 case 0:
1634 case 3:
1635 return IEEE80211_AC_BE;
1636 break;
1637 case 1:
1638 case 2:
1639 return IEEE80211_AC_BK;
1640 break;
1641 case 4:
1642 case 5:
1643 return IEEE80211_AC_VI;
1644 break;
1645 case 6:
1646 case 7:
1647 return IEEE80211_AC_VO;
1648 break;
1649 default:
1650 return -1;
1651 break;
1652 }
1653}
1654
17033543
NS		 1655/* The firmware will fill in the rate information
1656 * for each packet that gets queued in the hardware
49adc5ce 1657 * and these macros will interpret that info.
17033543
NS		 1658 */
1659
49adc5ce
JL		 1660#define RI_FORMAT(a) (a & 0x0001)
1661#define RI_RATE_ID_MCS(a) ((a & 0x01f8) >> 3)
17033543 1662
efb7c49a
LB		 1663static int
1664mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1665{
1666 struct mwl8k_priv *priv = hw->priv;
1667 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1668 int processed;
a66098da 1669
efb7c49a 1670 processed = 0;
8ccbc3b8 1671 while (txq->len > 0 && limit--) {
a66098da 1672 int tx;
a66098da
LB		 1673 struct mwl8k_tx_desc *tx_desc;
1674 unsigned long addr;
ce9e2e1b 1675 int size;
a66098da
LB		 1676 struct sk_buff *skb;
1677 struct ieee80211_tx_info *info;
1678 u32 status;
17033543
NS		 1679 struct ieee80211_sta *sta;
1680 struct mwl8k_sta *sta_info = NULL;
1681 u16 rate_info;
17033543 1682 struct ieee80211_hdr *wh;
a66098da 1683
45eb400d
LB		 1684 tx = txq->head;
1685 tx_desc = txq->txd + tx;
a66098da
LB		 1686
1687 status = le32_to_cpu(tx_desc->status);
1688
1689 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1690 if (!force)
1691 break;
1692 tx_desc->status &=
1693 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1694 }
1695
45eb400d 1696 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1697 BUG_ON(txq->len == 0);
1698 txq->len--;
a66098da
LB		 1699 priv->pending_tx_pkts--;
1700
1701 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1702 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1703 skb = txq->skb[tx];
1704 txq->skb[tx] = NULL;
a66098da
LB		 1705
1706 BUG_ON(skb == NULL);
1707 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1708
20f09c3d 1709 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da 1710
17033543
NS		 1711 wh = (struct ieee80211_hdr *) skb->data;
1712
a66098da
LB		 1713 /* Mark descriptor as unused */
1714 tx_desc->pkt_phys_addr = 0;
1715 tx_desc->pkt_len = 0;
1716
a66098da 1717 info = IEEE80211_SKB_CB(skb);
17033543 1718 if (ieee80211_is_data(wh->frame_control)) {
89e11801
TH		 1719 rcu_read_lock();
1720 sta = ieee80211_find_sta_by_ifaddr(hw, wh->addr1,
1721 wh->addr2);
17033543
NS		 1722 if (sta) {
1723 sta_info = MWL8K_STA(sta);
1724 BUG_ON(sta_info == NULL);
1725 rate_info = le16_to_cpu(tx_desc->rate_info);
17033543
NS		 1726 /* If rate is < 6.5 Mpbs for an ht station
1727 * do not form an ampdu. If the station is a
1728 * legacy station (format = 0), do not form an
1729 * ampdu
1730 */
49adc5ce
JL		 1731 if (RI_RATE_ID_MCS(rate_info) < 1 ||
1732 RI_FORMAT(rate_info) == 0) {
17033543
NS		 1733 sta_info->is_ampdu_allowed = false;
1734 } else {
1735 sta_info->is_ampdu_allowed = true;
1736 }
1737 }
89e11801 1738 rcu_read_unlock();
17033543
NS		 1739 }
1740
a66098da 1741 ieee80211_tx_info_clear_status(info);
0bf22c37
NS		 1742
1743 /* Rate control is happening in the firmware.
1744 * Ensure no tx rate is being reported.
1745 */
ba30c4a5
YAP		 1746 info->status.rates[0].idx = -1;
1747 info->status.rates[0].count = 1;
0bf22c37 1748
ce9e2e1b 1749 if (MWL8K_TXD_SUCCESS(status))
a66098da 1750 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1751
1752 ieee80211_tx_status_irqsafe(hw, skb);
1753
efb7c49a 1754 processed++;
a66098da
LB		 1755 }
1756
efb7c49a 1757 return processed;
a66098da
LB		 1758}
1759
1760/* must be called only when the card's transmit is completely halted */
1761static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1762{
1763 struct mwl8k_priv *priv = hw->priv;
1764 struct mwl8k_tx_queue *txq = priv->txq + index;
1765
73b46320
BC		 1766 if (txq->txd == NULL)
1767 return;
1768
efb7c49a 1769 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1770
45eb400d
LB		 1771 kfree(txq->skb);
1772 txq->skb = NULL;
a66098da
LB		 1773
1774 pci_free_consistent(priv->pdev,
1775 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1776 txq->txd, txq->txd_dma);
1777 txq->txd = NULL;
a66098da
LB		 1778}
1779
ac109fd0 1780/* caller must hold priv->stream_lock when calling the stream functions */
ba30c4a5 1781static struct mwl8k_ampdu_stream *
ac109fd0
BC		 1782mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
1783{
1784 struct mwl8k_ampdu_stream *stream;
1785 struct mwl8k_priv *priv = hw->priv;
1786 int i;
1787
7fb978b7 1788 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
ac109fd0
BC		 1789 stream = &priv->ampdu[i];
1790 if (stream->state == AMPDU_NO_STREAM) {
1791 stream->sta = sta;
1792 stream->state = AMPDU_STREAM_NEW;
1793 stream->tid = tid;
1794 stream->idx = i;
ac109fd0
BC		 1795 wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
1796 sta->addr, tid);
1797 return stream;
1798 }
1799 }
1800 return NULL;
1801}
1802
1803static int
1804mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1805{
1806 int ret;
1807
1808 /* if the stream has already been started, don't start it again */
1809 if (stream->state != AMPDU_STREAM_NEW)
1810 return 0;
1811 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
1812 if (ret)
1813 wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
1814 "%d\n", stream->sta->addr, stream->tid, ret);
1815 else
1816 wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
1817 stream->sta->addr, stream->tid);
1818 return ret;
1819}
1820
1821static void
1822mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1823{
1824 wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
1825 stream->tid);
1826 memset(stream, 0, sizeof(*stream));
1827}
1828
1829static struct mwl8k_ampdu_stream *
1830mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
1831{
1832 struct mwl8k_priv *priv = hw->priv;
1833 int i;
1834
7fb978b7 1835 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
ac109fd0
BC		 1836 struct mwl8k_ampdu_stream *stream;
1837 stream = &priv->ampdu[i];
1838 if (stream->state == AMPDU_NO_STREAM)
1839 continue;
1840 if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
1841 stream->tid == tid)
1842 return stream;
1843 }
1844 return NULL;
1845}
1846
d0805c1c
BC		 1847#define MWL8K_AMPDU_PACKET_THRESHOLD 64
1848static inline bool mwl8k_ampdu_allowed(struct ieee80211_sta *sta, u8 tid)
1849{
1850 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1851 struct tx_traffic_info *tx_stats;
1852
1853 BUG_ON(tid >= MWL8K_MAX_TID);
1854 tx_stats = &sta_info->tx_stats[tid];
1855
1856 return sta_info->is_ampdu_allowed &&
1857 tx_stats->pkts > MWL8K_AMPDU_PACKET_THRESHOLD;
1858}
1859
1860static inline void mwl8k_tx_count_packet(struct ieee80211_sta *sta, u8 tid)
1861{
1862 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1863 struct tx_traffic_info *tx_stats;
1864
1865 BUG_ON(tid >= MWL8K_MAX_TID);
1866 tx_stats = &sta_info->tx_stats[tid];
1867
1868 if (tx_stats->start_time == 0)
1869 tx_stats->start_time = jiffies;
1870
1871 /* reset the packet count after each second elapses. If the number of
1872 * packets ever exceeds the ampdu_min_traffic threshold, we will allow
1873 * an ampdu stream to be started.
1874 */
1875 if (jiffies - tx_stats->start_time > HZ) {
1876 tx_stats->pkts = 0;
1877 tx_stats->start_time = 0;
1878 } else
1879 tx_stats->pkts++;
1880}
1881
7fb978b7
YAP		 1882/* The hardware ampdu queues start from 5.
1883 * txpriorities for ampdu queues are
1884 * 5 6 7 0 1 2 3 4 ie., queue 5 is highest
1885 * and queue 3 is lowest (queue 4 is reserved)
1886 */
1887#define BA_QUEUE 5
1888
7bb45683 1889static void
36323f81
TH		 1890mwl8k_txq_xmit(struct ieee80211_hw *hw,
1891 int index,
1892 struct ieee80211_sta *sta,
1893 struct sk_buff *skb)
a66098da
LB		 1894{
1895 struct mwl8k_priv *priv = hw->priv;
1896 struct ieee80211_tx_info *tx_info;
23b33906 1897 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1898 struct ieee80211_hdr *wh;
1899 struct mwl8k_tx_queue *txq;
1900 struct mwl8k_tx_desc *tx;
a66098da 1901 dma_addr_t dma;
23b33906
LB		 1902 u32 txstatus;
1903 u8 txdatarate;
1904 u16 qos;
65f3ddcd
NS		 1905 int txpriority;
1906 u8 tid = 0;
1907 struct mwl8k_ampdu_stream *stream = NULL;
1908 bool start_ba_session = false;
3a769888 1909 bool mgmtframe = false;
a0e7c6cf 1910 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
e1f4d69b 1911 bool eapol_frame = false;
a66098da 1912
23b33906
LB		 1913 wh = (struct ieee80211_hdr *)skb->data;
1914 if (ieee80211_is_data_qos(wh->frame_control))
1915 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1916 else
1917 qos = 0;
a66098da 1918
e1f4d69b
NS		 1919 if (skb->protocol == cpu_to_be16(ETH_P_PAE))
1920 eapol_frame = true;
1921
3a769888
NS		 1922 if (ieee80211_is_mgmt(wh->frame_control))
1923 mgmtframe = true;
1924
d9a07d49 1925 if (priv->ap_fw)
ff776cec 1926 mwl8k_encapsulate_tx_frame(priv, skb);
d9a07d49 1927 else
e4eefec7 1928 mwl8k_add_dma_header(priv, skb, 0, 0);
d9a07d49 1929
23b33906 1930 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1931
1932 tx_info = IEEE80211_SKB_CB(skb);
1933 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1934
1935 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1936 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1937 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1938 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1939 }
1940
23b33906
LB		 1941 /* Setup firmware control bit fields for each frame type. */
1942 txstatus = 0;
1943 txdatarate = 0;
1944 if (ieee80211_is_mgmt(wh->frame_control) ||
1945 ieee80211_is_ctl(wh->frame_control)) {
1946 txdatarate = 0;
e0493a8d 1947 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1948 } else if (ieee80211_is_data(wh->frame_control)) {
1949 txdatarate = 1;
1950 if (is_multicast_ether_addr(wh->addr1))
1951 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1952
e0493a8d 1953 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1954 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1955 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1956 else
e0493a8d 1957 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1958 }
a66098da 1959
a0e7c6cf
NS		 1960 /* Queue ADDBA request in the respective data queue. While setting up
1961 * the ampdu stream, mac80211 queues further packets for that
1962 * particular ra/tid pair. However, packets piled up in the hardware
1963 * for that ra/tid pair will still go out. ADDBA request and the
1964 * related data packets going out from different queues asynchronously
1965 * will cause a shift in the receiver window which might result in
1966 * ampdu packets getting dropped at the receiver after the stream has
1967 * been setup.
1968 */
1969 if (unlikely(ieee80211_is_action(wh->frame_control) &&
1970 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
1971 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ &&
1972 priv->ap_fw)) {
1973 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
1974 tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
1975 index = mwl8k_tid_queue_mapping(tid);
1976 }
1977
65f3ddcd
NS		 1978 txpriority = index;
1979
e1f4d69b
NS		 1980 if (priv->ap_fw && sta && sta->ht_cap.ht_supported && !eapol_frame &&
1981 ieee80211_is_data_qos(wh->frame_control)) {
65f3ddcd 1982 tid = qos & 0xf;
d0805c1c 1983 mwl8k_tx_count_packet(sta, tid);
65f3ddcd
NS		 1984 spin_lock(&priv->stream_lock);
1985 stream = mwl8k_lookup_stream(hw, sta->addr, tid);
1986 if (stream != NULL) {
1987 if (stream->state == AMPDU_STREAM_ACTIVE) {
5f2a1494 1988 WARN_ON(!(qos & MWL8K_QOS_ACK_POLICY_BLOCKACK));
7fb978b7
YAP		 1989 txpriority = (BA_QUEUE + stream->idx) %
1990 TOTAL_HW_TX_QUEUES;
1991 if (stream->idx <= 1)
1992 index = stream->idx +
1993 MWL8K_TX_WMM_QUEUES;
1994
65f3ddcd
NS		 1995 } else if (stream->state == AMPDU_STREAM_NEW) {
1996 /* We get here if the driver sends us packets
1997 * after we've initiated a stream, but before
1998 * our ampdu_action routine has been called
1999 * with IEEE80211_AMPDU_TX_START to get the SSN
2000 * for the ADDBA request. So this packet can
2001 * go out with no risk of sequence number
2002 * mismatch. No special handling is required.
2003 */
2004 } else {
2005 /* Drop packets that would go out after the
2006 * ADDBA request was sent but before the ADDBA
2007 * response is received. If we don't do this,
2008 * the recipient would probably receive it
2009 * after the ADDBA request with SSN 0. This
2010 * will cause the recipient's BA receive window
2011 * to shift, which would cause the subsequent
2012 * packets in the BA stream to be discarded.
2013 * mac80211 queues our packets for us in this
2014 * case, so this is really just a safety check.
2015 */
2016 wiphy_warn(hw->wiphy,
2017 "Cannot send packet while ADDBA "
2018 "dialog is underway.\n");
2019 spin_unlock(&priv->stream_lock);
2020 dev_kfree_skb(skb);
2021 return;
2022 }
2023 } else {
2024 /* Defer calling mwl8k_start_stream so that the current
2025 * skb can go out before the ADDBA request. This
2026 * prevents sequence number mismatch at the recepient
2027 * as described above.
2028 */
d0805c1c 2029 if (mwl8k_ampdu_allowed(sta, tid)) {
17033543
NS		 2030 stream = mwl8k_add_stream(hw, sta, tid);
2031 if (stream != NULL)
2032 start_ba_session = true;
2033 }
65f3ddcd
NS		 2034 }
2035 spin_unlock(&priv->stream_lock);
5f2a1494
YAP		 2036 } else {
2037 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
2038 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
65f3ddcd
NS		 2039 }
2040
a66098da
LB		 2041 dma = pci_map_single(priv->pdev, skb->data,
2042 skb->len, PCI_DMA_TODEVICE);
2043
2044 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 2045 wiphy_debug(hw->wiphy,
2046 "failed to dma map skb, dropping TX frame.\n");
65f3ddcd
NS		 2047 if (start_ba_session) {
2048 spin_lock(&priv->stream_lock);
2049 mwl8k_remove_stream(hw, stream);
2050 spin_unlock(&priv->stream_lock);
2051 }
23b33906 2052 dev_kfree_skb(skb);
7bb45683 2053 return;
a66098da
LB		 2054 }
2055
23b33906 2056 spin_lock_bh(&priv->tx_lock);
a66098da 2057
23b33906 2058 txq = priv->txq + index;
a66098da 2059
3a769888
NS		 2060 /* Mgmt frames that go out frequently are probe
2061 * responses. Other mgmt frames got out relatively
2062 * infrequently. Hence reserve 2 buffers so that
2063 * other mgmt frames do not get dropped due to an
2064 * already queued probe response in one of the
2065 * reserved buffers.
2066 */
2067
2068 if (txq->len >= MWL8K_TX_DESCS - 2) {
23677ce3 2069 if (!mgmtframe || txq->len == MWL8K_TX_DESCS) {
3a769888
NS		 2070 if (start_ba_session) {
2071 spin_lock(&priv->stream_lock);
2072 mwl8k_remove_stream(hw, stream);
2073 spin_unlock(&priv->stream_lock);
2074 }
bbf71a8f 2075 mwl8k_tx_start(priv);
3a769888 2076 spin_unlock_bh(&priv->tx_lock);
ff7aa96f
NS		 2077 pci_unmap_single(priv->pdev, dma, skb->len,
2078 PCI_DMA_TODEVICE);
3a769888
NS		 2079 dev_kfree_skb(skb);
2080 return;
3a7dbc3b 2081 }
65f3ddcd
NS		 2082 }
2083
45eb400d
LB		 2084 BUG_ON(txq->skb[txq->tail] != NULL);
2085 txq->skb[txq->tail] = skb;
a66098da 2086
45eb400d 2087 tx = txq->txd + txq->tail;
23b33906 2088 tx->data_rate = txdatarate;
65f3ddcd 2089 tx->tx_priority = txpriority;
a66098da 2090 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 2091 tx->pkt_phys_addr = cpu_to_le32(dma);
2092 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 2093 tx->rate_info = 0;
36323f81
TH		 2094 if (!priv->ap_fw && sta != NULL)
2095 tx->peer_id = MWL8K_STA(sta)->peer_id;
a680400e
LB		 2096 else
2097 tx->peer_id = 0;
566875db 2098
e1f4d69b 2099 if (priv->ap_fw && ieee80211_is_data(wh->frame_control) && !eapol_frame)
566875db
PN		 2100 tx->timestamp = cpu_to_le32(ioread32(priv->regs +
2101 MWL8K_HW_TIMER_REGISTER));
b8d9e572
NS		 2102 else
2103 tx->timestamp = 0;
566875db 2104
a66098da 2105 wmb();
23b33906
LB		 2106 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
2107
8ccbc3b8 2108 txq->len++;
a66098da 2109 priv->pending_tx_pkts++;
a66098da 2110
45eb400d
LB		 2111 txq->tail++;
2112 if (txq->tail == MWL8K_TX_DESCS)
2113 txq->tail = 0;
23b33906 2114
23b33906 2115 mwl8k_tx_start(priv);
a66098da
LB		 2116
2117 spin_unlock_bh(&priv->tx_lock);
65f3ddcd
NS		 2118
2119 /* Initiate the ampdu session here */
2120 if (start_ba_session) {
2121 spin_lock(&priv->stream_lock);
2122 if (mwl8k_start_stream(hw, stream))
2123 mwl8k_remove_stream(hw, stream);
2124 spin_unlock(&priv->stream_lock);
2125 }
a66098da
LB		 2126}
2127
2128
618952a7
LB		 2129/*
2130 * Firmware access.
2131 *
2132 * We have the following requirements for issuing firmware commands:
2133 * - Some commands require that the packet transmit path is idle when
2134 * the command is issued. (For simplicity, we'll just quiesce the
2135 * transmit path for every command.)
2136 * - There are certain sequences of commands that need to be issued to
2137 * the hardware sequentially, with no other intervening commands.
2138 *
2139 * This leads to an implementation of a "firmware lock" as a mutex that
2140 * can be taken recursively, and which is taken by both the low-level
2141 * command submission function (mwl8k_post_cmd) as well as any users of
2142 * that function that require issuing of an atomic sequence of commands,
2143 * and quiesces the transmit path whenever it's taken.
2144 */
2145static int mwl8k_fw_lock(struct ieee80211_hw *hw)
2146{
2147 struct mwl8k_priv *priv = hw->priv;
2148
2149 if (priv->fw_mutex_owner != current) {
2150 int rc;
2151
2152 mutex_lock(&priv->fw_mutex);
2153 ieee80211_stop_queues(hw);
2154
2155 rc = mwl8k_tx_wait_empty(hw);
2156 if (rc) {
6b6accc3
YAP		 2157 if (!priv->hw_restart_in_progress)
2158 ieee80211_wake_queues(hw);
2159
618952a7
LB		 2160 mutex_unlock(&priv->fw_mutex);
2161
2162 return rc;
2163 }
2164
2165 priv->fw_mutex_owner = current;
2166 }
2167
2168 priv->fw_mutex_depth++;
2169
2170 return 0;
2171}
2172
2173static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
2174{
2175 struct mwl8k_priv *priv = hw->priv;
2176
2177 if (!--priv->fw_mutex_depth) {
6b6accc3
YAP		 2178 if (!priv->hw_restart_in_progress)
2179 ieee80211_wake_queues(hw);
2180
618952a7
LB		 2181 priv->fw_mutex_owner = NULL;
2182 mutex_unlock(&priv->fw_mutex);
2183 }
2184}
2185
e882efc9
YAP		 2186static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable,
2187 u32 bitmap);
618952a7 2188
a66098da
LB		 2189/*
2190 * Command processing.
2191 */
2192
0c9cc640
LB		 2193/* Timeout firmware commands after 10s */
2194#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 2195
2196static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
2197{
2198 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2199 struct mwl8k_priv *priv = hw->priv;
2200 void __iomem *regs = priv->regs;
2201 dma_addr_t dma_addr;
2202 unsigned int dma_size;
2203 int rc;
a66098da
LB		 2204 unsigned long timeout = 0;
2205 u8 buf[32];
e882efc9
YAP		 2206 u32 bitmap = 0;
2207
2208 wiphy_dbg(hw->wiphy, "Posting %s [%d]\n",
2209 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), cmd->macid);
2210
2211 /* Before posting firmware commands that could change the hardware
2212 * characteristics, make sure that all BSSes are stopped temporary.
2213 * Enable these stopped BSSes after completion of the commands
2214 */
2215
2216 rc = mwl8k_fw_lock(hw);
2217 if (rc)
2218 return rc;
2219
2220 if (priv->ap_fw && priv->running_bsses) {
2221 switch (le16_to_cpu(cmd->code)) {
2222 case MWL8K_CMD_SET_RF_CHANNEL:
2223 case MWL8K_CMD_RADIO_CONTROL:
2224 case MWL8K_CMD_RF_TX_POWER:
2225 case MWL8K_CMD_TX_POWER:
2226 case MWL8K_CMD_RF_ANTENNA:
2227 case MWL8K_CMD_RTS_THRESHOLD:
2228 case MWL8K_CMD_MIMO_CONFIG:
2229 bitmap = priv->running_bsses;
2230 mwl8k_enable_bsses(hw, false, bitmap);
2231 break;
2232 }
2233 }
a66098da 2234
b603742f 2235 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 2236 dma_size = le16_to_cpu(cmd->length);
2237 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
2238 PCI_DMA_BIDIRECTIONAL);
2239 if (pci_dma_mapping_error(priv->pdev, dma_addr))
2240 return -ENOMEM;
2241
a66098da
LB		 2242 priv->hostcmd_wait = &cmd_wait;
2243 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
2244 iowrite32(MWL8K_H2A_INT_DOORBELL,
2245 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2246 iowrite32(MWL8K_H2A_INT_DUMMY,
2247 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 2248
2249 timeout = wait_for_completion_timeout(&cmd_wait,
2250 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
2251
618952a7
LB		 2252 priv->hostcmd_wait = NULL;
2253
618952a7 2254
37055bd4
LB		 2255 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2256 PCI_DMA_BIDIRECTIONAL);
2257
a66098da 2258 if (!timeout) {
5db55844 2259 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 2260 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2261 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 2262 rc = -ETIMEDOUT;
2263 } else {
0c9cc640
LB		 2264 int ms;
2265
2266 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
2267
ce9e2e1b 2268 rc = cmd->result ? -EINVAL : 0;
a66098da 2269 if (rc)
5db55844 2270 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 2271 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2272 le16_to_cpu(cmd->result));
0c9cc640 2273 else if (ms > 2000)
5db55844 2274 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 2275 mwl8k_cmd_name(cmd->code,
2276 buf, sizeof(buf)),
2277 ms);
a66098da
LB		 2278 }
2279
e882efc9
YAP		 2280 if (bitmap)
2281 mwl8k_enable_bsses(hw, true, bitmap);
2282
2283 mwl8k_fw_unlock(hw);
2284
a66098da
LB		 2285 return rc;
2286}
2287
f57ca9c1
LB		 2288static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
2289 struct ieee80211_vif *vif,
2290 struct mwl8k_cmd_pkt *cmd)
2291{
2292 if (vif != NULL)
2293 cmd->macid = MWL8K_VIF(vif)->macid;
2294 return mwl8k_post_cmd(hw, cmd);
2295}
2296
1349ad2f
LB		 2297/*
2298 * Setup code shared between STA and AP firmware images.
2299 */
2300static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
2301{
2302 struct mwl8k_priv *priv = hw->priv;
2303
2304 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
2305 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
2306
2307 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
2308 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
2309
2310 priv->band_24.band = IEEE80211_BAND_2GHZ;
2311 priv->band_24.channels = priv->channels_24;
2312 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
2313 priv->band_24.bitrates = priv->rates_24;
2314 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
2315
2316 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
2317}
2318
4eae9edd
LB		 2319static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
2320{
2321 struct mwl8k_priv *priv = hw->priv;
2322
2323 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
2324 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
2325
2326 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
2327 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
2328
2329 priv->band_50.band = IEEE80211_BAND_5GHZ;
2330 priv->band_50.channels = priv->channels_50;
2331 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
2332 priv->band_50.bitrates = priv->rates_50;
2333 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
2334
2335 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
2336}
2337
a66098da 2338/*
04b147b1 2339 * CMD_GET_HW_SPEC (STA version).
a66098da 2340 */
04b147b1 2341struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 2342 struct mwl8k_cmd_pkt header;
2343 __u8 hw_rev;
2344 __u8 host_interface;
2345 __le16 num_mcaddrs;
d89173f2 2346 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 2347 __le16 region_code;
2348 __le32 fw_rev;
2349 __le32 ps_cookie;
2350 __le32 caps;
2351 __u8 mcs_bitmap[16];
2352 __le32 rx_queue_ptr;
2353 __le32 num_tx_queues;
e600707b 2354 __le32 tx_queue_ptrs[MWL8K_TX_WMM_QUEUES];
a66098da
LB		 2355 __le32 caps2;
2356 __le32 num_tx_desc_per_queue;
45eb400d 2357 __le32 total_rxd;
ba2d3587 2358} __packed;
a66098da 2359
341c9791
LB		 2360#define MWL8K_CAP_MAX_AMSDU 0x20000000
2361#define MWL8K_CAP_GREENFIELD 0x08000000
2362#define MWL8K_CAP_AMPDU 0x04000000
2363#define MWL8K_CAP_RX_STBC 0x01000000
2364#define MWL8K_CAP_TX_STBC 0x00800000
2365#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2366#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2367#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2368#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2369#define MWL8K_CAP_DELAY_BA 0x00003000
2370#define MWL8K_CAP_MIMO 0x00000200
2371#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 2372#define MWL8K_CAP_BAND_MASK 0x00000007
2373#define MWL8K_CAP_5GHZ 0x00000004
2374#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 2375
06953235
LB		 2376static void
2377mwl8k_set_ht_caps(struct ieee80211_hw *hw,
2378 struct ieee80211_supported_band *band, u32 cap)
341c9791 2379{
341c9791
LB		 2380 int rx_streams;
2381 int tx_streams;
2382
777ad375 2383 band->ht_cap.ht_supported = 1;
341c9791
LB		 2384
2385 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 2386 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 2387 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 2388 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 2389 if (cap & MWL8K_CAP_AMPDU) {
2390 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 2391 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2392 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 2393 }
2394 if (cap & MWL8K_CAP_RX_STBC)
777ad375 2395 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 2396 if (cap & MWL8K_CAP_TX_STBC)
777ad375 2397 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 2398 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 2399 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 2400 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 2401 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 2402 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 2403 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 2404 if (cap & MWL8K_CAP_40MHZ)
777ad375 2405 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 2406
2407 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
2408 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
2409
777ad375 2410 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 2411 if (rx_streams >= 2)
777ad375 2412 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 2413 if (rx_streams >= 3)
777ad375
LB		 2414 band->ht_cap.mcs.rx_mask[2] = 0xff;
2415 band->ht_cap.mcs.rx_mask[4] = 0x01;
2416 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 2417
2418 if (rx_streams != tx_streams) {
777ad375
LB		 2419 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
2420 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 2421 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2422 }
2423}
2424
06953235
LB		 2425static void
2426mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
2427{
2428 struct mwl8k_priv *priv = hw->priv;
2429
c3f251a3
JG		 2430 if (priv->caps)
2431 return;
2432
06953235
LB		 2433 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
2434 mwl8k_setup_2ghz_band(hw);
2435 if (caps & MWL8K_CAP_MIMO)
2436 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
2437 }
2438
2439 if (caps & MWL8K_CAP_5GHZ) {
2440 mwl8k_setup_5ghz_band(hw);
2441 if (caps & MWL8K_CAP_MIMO)
2442 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
2443 }
c3f251a3
JG		 2444
2445 priv->caps = caps;
06953235
LB		 2446}
2447
04b147b1 2448static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 2449{
2450 struct mwl8k_priv *priv = hw->priv;
04b147b1 2451 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 2452 int rc;
2453 int i;
2454
2455 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2456 if (cmd == NULL)
2457 return -ENOMEM;
2458
2459 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2460 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2461
2462 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2463 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 2464 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b
BC		 2465 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2466 for (i = 0; i < mwl8k_tx_queues(priv); i++)
45eb400d 2467 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 2468 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 2469 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 2470
2471 rc = mwl8k_post_cmd(hw, &cmd->header);
2472
2473 if (!rc) {
2474 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2475 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 2476 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 2477 priv->hw_rev = cmd->hw_rev;
06953235 2478 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 2479 priv->ap_macids_supported = 0x00000000;
2480 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 2481 }
2482
2483 kfree(cmd);
2484 return rc;
2485}
2486
42fba21d
LB		 2487/*
2488 * CMD_GET_HW_SPEC (AP version).
2489 */
2490struct mwl8k_cmd_get_hw_spec_ap {
2491 struct mwl8k_cmd_pkt header;
2492 __u8 hw_rev;
2493 __u8 host_interface;
2494 __le16 num_wcb;
2495 __le16 num_mcaddrs;
2496 __u8 perm_addr[ETH_ALEN];
2497 __le16 region_code;
2498 __le16 num_antenna;
2499 __le32 fw_rev;
2500 __le32 wcbbase0;
2501 __le32 rxwrptr;
2502 __le32 rxrdptr;
2503 __le32 ps_cookie;
2504 __le32 wcbbase1;
2505 __le32 wcbbase2;
2506 __le32 wcbbase3;
952a0e96 2507 __le32 fw_api_version;
8a7a578c
BC		 2508 __le32 caps;
2509 __le32 num_of_ampdu_queues;
2510 __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES];
ba2d3587 2511} __packed;
42fba21d
LB		 2512
2513static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2514{
2515 struct mwl8k_priv *priv = hw->priv;
2516 struct mwl8k_cmd_get_hw_spec_ap *cmd;
8a7a578c 2517 int rc, i;
952a0e96 2518 u32 api_version;
42fba21d
LB		 2519
2520 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2521 if (cmd == NULL)
2522 return -ENOMEM;
2523
2524 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2525 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2526
2527 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2528 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2529
2530 rc = mwl8k_post_cmd(hw, &cmd->header);
2531
2532 if (!rc) {
2533 int off;
2534
952a0e96
BC		 2535 api_version = le32_to_cpu(cmd->fw_api_version);
2536 if (priv->device_info->fw_api_ap != api_version) {
2537 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2538 " Expected %d got %d.\n", MWL8K_NAME,
2539 priv->device_info->part_name,
2540 priv->device_info->fw_api_ap,
2541 api_version);
2542 rc = -EINVAL;
2543 goto done;
2544 }
42fba21d
LB		 2545 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2546 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2547 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2548 priv->hw_rev = cmd->hw_rev;
8a7a578c 2549 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18 2550 priv->ap_macids_supported = 0x000000ff;
d59c1cfd 2551 priv->sta_macids_supported = 0x00000100;
8a7a578c
BC		 2552 priv->num_ampdu_queues = le32_to_cpu(cmd->num_of_ampdu_queues);
2553 if (priv->num_ampdu_queues > MWL8K_MAX_AMPDU_QUEUES) {
2554 wiphy_warn(hw->wiphy, "fw reported %d ampdu queues"
2555 " but we only support %d.\n",
2556 priv->num_ampdu_queues,
2557 MWL8K_MAX_AMPDU_QUEUES);
2558 priv->num_ampdu_queues = MWL8K_MAX_AMPDU_QUEUES;
2559 }
42fba21d 2560 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2561 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2562
2563 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2564 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d 2565
73b46320
BC		 2566 priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff;
2567 priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff;
2568 priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff;
2569 priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff;
8a7a578c
BC		 2570
2571 for (i = 0; i < priv->num_ampdu_queues; i++)
e600707b 2572 priv->txq_offset[i + MWL8K_TX_WMM_QUEUES] =
8a7a578c 2573 le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff;
42fba21d
LB		 2574 }
2575
952a0e96 2576done:
42fba21d
LB		 2577 kfree(cmd);
2578 return rc;
2579}
2580
2581/*
2582 * CMD_SET_HW_SPEC.
2583 */
2584struct mwl8k_cmd_set_hw_spec {
2585 struct mwl8k_cmd_pkt header;
2586 __u8 hw_rev;
2587 __u8 host_interface;
2588 __le16 num_mcaddrs;
2589 __u8 perm_addr[ETH_ALEN];
2590 __le16 region_code;
2591 __le32 fw_rev;
2592 __le32 ps_cookie;
2593 __le32 caps;
2594 __le32 rx_queue_ptr;
2595 __le32 num_tx_queues;
e600707b 2596 __le32 tx_queue_ptrs[MWL8K_MAX_TX_QUEUES];
42fba21d
LB		 2597 __le32 flags;
2598 __le32 num_tx_desc_per_queue;
2599 __le32 total_rxd;
ba2d3587 2600} __packed;
42fba21d 2601
8a7a578c
BC		 2602/* If enabled, MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY will cause
2603 * packets to expire 500 ms after the timestamp in the tx descriptor. That is,
2604 * the packets that are queued for more than 500ms, will be dropped in the
2605 * hardware. This helps minimizing the issues caused due to head-of-line
2606 * blocking where a slow client can hog the bandwidth and affect traffic to a
2607 * faster client.
2608 */
2609#define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
3373b28e 2610#define MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR 0x00000200
b64fe619
LB		 2611#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2612#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2613#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 2614
2615static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2616{
2617 struct mwl8k_priv *priv = hw->priv;
2618 struct mwl8k_cmd_set_hw_spec *cmd;
2619 int rc;
2620 int i;
2621
2622 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2623 if (cmd == NULL)
2624 return -ENOMEM;
2625
2626 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2627 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2628
2629 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2630 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b 2631 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
85c9205c
NS		 2632
2633 /*
2634 * Mac80211 stack has Q0 as highest priority and Q3 as lowest in
2635 * that order. Firmware has Q3 as highest priority and Q0 as lowest
2636 * in that order. Map Q3 of mac80211 to Q0 of firmware so that the
2637 * priority is interpreted the right way in firmware.
2638 */
e600707b
BC		 2639 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
2640 int j = mwl8k_tx_queues(priv) - 1 - i;
85c9205c
NS		 2641 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[j].txd_dma);
2642 }
2643
b64fe619
LB		 2644 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2645 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
31d291a7 2646 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON |
3373b28e
NS		 2647 MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY |
2648 MWL8K_SET_HW_SPEC_FLAG_GENERATE_CCMP_HDR);
42fba21d
LB		 2649 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2650 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2651
2652 rc = mwl8k_post_cmd(hw, &cmd->header);
2653 kfree(cmd);
2654
2655 return rc;
2656}
2657
a66098da
LB		 2658/*
2659 * CMD_MAC_MULTICAST_ADR.
2660 */
2661struct mwl8k_cmd_mac_multicast_adr {
2662 struct mwl8k_cmd_pkt header;
2663 __le16 action;
2664 __le16 numaddr;
ce9e2e1b 2665 __u8 addr[0][ETH_ALEN];
a66098da
LB		 2666};
2667
d5e30845
LB		 2668#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2669#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2670#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2671#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2672
e81cd2d6 2673static struct mwl8k_cmd_pkt *
447ced07 2674__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2675 struct netdev_hw_addr_list *mc_list)
a66098da 2676{
e81cd2d6 2677 struct mwl8k_priv *priv = hw->priv;
a66098da 2678 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2679 int size;
22bedad3
JP		 2680 int mc_count = 0;
2681
2682 if (mc_list)
2683 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2684
447ced07 2685 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 2686 allmulti = 1;
2687 mc_count = 0;
2688 }
e81cd2d6
LB		 2689
2690 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2691
e81cd2d6 2692 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2693 if (cmd == NULL)
e81cd2d6 2694 return NULL;
a66098da
LB		 2695
2696 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2697 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 2698 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2699 MWL8K_ENABLE_RX_BROADCAST);
2700
2701 if (allmulti) {
2702 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2703 } else if (mc_count) {
22bedad3
JP		 2704 struct netdev_hw_addr *ha;
2705 int i = 0;
d5e30845
LB		 2706
2707 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2708 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 2709 netdev_hw_addr_list_for_each(ha, mc_list) {
2710 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2711 }
a66098da
LB		 2712 }
2713
e81cd2d6 2714 return &cmd->header;
a66098da
LB		 2715}
2716
2717/*
55489b6e 2718 * CMD_GET_STAT.
a66098da 2719 */
55489b6e 2720struct mwl8k_cmd_get_stat {
a66098da 2721 struct mwl8k_cmd_pkt header;
a66098da 2722 __le32 stats[64];
ba2d3587 2723} __packed;
a66098da
LB		 2724
2725#define MWL8K_STAT_ACK_FAILURE 9
2726#define MWL8K_STAT_RTS_FAILURE 12
2727#define MWL8K_STAT_FCS_ERROR 24
2728#define MWL8K_STAT_RTS_SUCCESS 11
2729
55489b6e
LB		 2730static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2731 struct ieee80211_low_level_stats *stats)
a66098da 2732{
55489b6e 2733 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2734 int rc;
2735
2736 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2737 if (cmd == NULL)
2738 return -ENOMEM;
2739
2740 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2741 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2742
2743 rc = mwl8k_post_cmd(hw, &cmd->header);
2744 if (!rc) {
2745 stats->dot11ACKFailureCount =
2746 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2747 stats->dot11RTSFailureCount =
2748 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2749 stats->dot11FCSErrorCount =
2750 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2751 stats->dot11RTSSuccessCount =
2752 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2753 }
2754 kfree(cmd);
2755
2756 return rc;
2757}
2758
2759/*
55489b6e 2760 * CMD_RADIO_CONTROL.
a66098da 2761 */
55489b6e 2762struct mwl8k_cmd_radio_control {
a66098da
LB		 2763 struct mwl8k_cmd_pkt header;
2764 __le16 action;
2765 __le16 control;
2766 __le16 radio_on;
ba2d3587 2767} __packed;
a66098da 2768
c46563b7 2769static int
55489b6e 2770mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2771{
2772 struct mwl8k_priv *priv = hw->priv;
55489b6e 2773 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2774 int rc;
2775
c46563b7 2776 if (enable == priv->radio_on && !force)
a66098da
LB		 2777 return 0;
2778
a66098da
LB		 2779 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2780 if (cmd == NULL)
2781 return -ENOMEM;
2782
2783 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2784 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2785 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2786 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2787 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2788
2789 rc = mwl8k_post_cmd(hw, &cmd->header);
2790 kfree(cmd);
2791
2792 if (!rc)
c46563b7 2793 priv->radio_on = enable;
a66098da
LB		 2794
2795 return rc;
2796}
2797
55489b6e 2798static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2799{
55489b6e 2800 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2801}
2802
55489b6e 2803static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2804{
55489b6e 2805 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2806}
2807
a66098da
LB		 2808static int
2809mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2810{
99200a99 2811 struct mwl8k_priv *priv = hw->priv;
a66098da 2812
68ce3884 2813 priv->radio_short_preamble = short_preamble;
a66098da 2814
55489b6e 2815 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2816}
2817
2818/*
55489b6e 2819 * CMD_RF_TX_POWER.
a66098da 2820 */
41fdf097 2821#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2822
55489b6e 2823struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2824 struct mwl8k_cmd_pkt header;
2825 __le16 action;
2826 __le16 support_level;
2827 __le16 current_level;
2828 __le16 reserved;
41fdf097 2829 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2830} __packed;
a66098da 2831
55489b6e 2832static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2833{
55489b6e 2834 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2835 int rc;
2836
2837 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2838 if (cmd == NULL)
2839 return -ENOMEM;
2840
2841 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2842 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2843 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2844 cmd->support_level = cpu_to_le16(dBm);
2845
2846 rc = mwl8k_post_cmd(hw, &cmd->header);
2847 kfree(cmd);
2848
2849 return rc;
2850}
2851
41fdf097
NS		 2852/*
2853 * CMD_TX_POWER.
2854 */
2855#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2856
2857struct mwl8k_cmd_tx_power {
2858 struct mwl8k_cmd_pkt header;
2859 __le16 action;
2860 __le16 band;
2861 __le16 channel;
2862 __le16 bw;
2863 __le16 sub_ch;
2864 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
ba30c4a5 2865} __packed;
41fdf097
NS		 2866
2867static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2868 struct ieee80211_conf *conf,
2869 unsigned short pwr)
2870{
675a0b04
KB		 2871 struct ieee80211_channel *channel = conf->chandef.chan;
2872 enum nl80211_channel_type channel_type =
2873 cfg80211_get_chandef_type(&conf->chandef);
41fdf097
NS		 2874 struct mwl8k_cmd_tx_power *cmd;
2875 int rc;
2876 int i;
2877
2878 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2879 if (cmd == NULL)
2880 return -ENOMEM;
2881
2882 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2883 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2884 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2885
2886 if (channel->band == IEEE80211_BAND_2GHZ)
2887 cmd->band = cpu_to_le16(0x1);
2888 else if (channel->band == IEEE80211_BAND_5GHZ)
2889 cmd->band = cpu_to_le16(0x4);
2890
604c4ef1 2891 cmd->channel = cpu_to_le16(channel->hw_value);
41fdf097 2892
675a0b04
KB		 2893 if (channel_type == NL80211_CHAN_NO_HT ||
2894 channel_type == NL80211_CHAN_HT20) {
41fdf097
NS		 2895 cmd->bw = cpu_to_le16(0x2);
2896 } else {
2897 cmd->bw = cpu_to_le16(0x4);
675a0b04 2898 if (channel_type == NL80211_CHAN_HT40MINUS)
41fdf097 2899 cmd->sub_ch = cpu_to_le16(0x3);
675a0b04 2900 else if (channel_type == NL80211_CHAN_HT40PLUS)
41fdf097
NS		 2901 cmd->sub_ch = cpu_to_le16(0x1);
2902 }
2903
2904 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2905 cmd->power_level_list[i] = cpu_to_le16(pwr);
2906
2907 rc = mwl8k_post_cmd(hw, &cmd->header);
2908 kfree(cmd);
2909
2910 return rc;
2911}
2912
08b06347
LB		 2913/*
2914 * CMD_RF_ANTENNA.
2915 */
2916struct mwl8k_cmd_rf_antenna {
2917 struct mwl8k_cmd_pkt header;
2918 __le16 antenna;
2919 __le16 mode;
ba2d3587 2920} __packed;
08b06347
LB		 2921
2922#define MWL8K_RF_ANTENNA_RX 1
2923#define MWL8K_RF_ANTENNA_TX 2
2924
2925static int
2926mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2927{
2928 struct mwl8k_cmd_rf_antenna *cmd;
2929 int rc;
2930
2931 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2932 if (cmd == NULL)
2933 return -ENOMEM;
2934
2935 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2936 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2937 cmd->antenna = cpu_to_le16(antenna);
2938 cmd->mode = cpu_to_le16(mask);
2939
2940 rc = mwl8k_post_cmd(hw, &cmd->header);
2941 kfree(cmd);
2942
2943 return rc;
2944}
2945
b64fe619
LB		 2946/*
2947 * CMD_SET_BEACON.
2948 */
2949struct mwl8k_cmd_set_beacon {
2950 struct mwl8k_cmd_pkt header;
2951 __le16 beacon_len;
2952 __u8 beacon[0];
2953};
2954
aa21d0f6
LB		 2955static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2956 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2957{
2958 struct mwl8k_cmd_set_beacon *cmd;
2959 int rc;
2960
2961 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2962 if (cmd == NULL)
2963 return -ENOMEM;
2964
2965 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2966 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2967 cmd->beacon_len = cpu_to_le16(len);
2968 memcpy(cmd->beacon, beacon, len);
2969
aa21d0f6 2970 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2971 kfree(cmd);
2972
2973 return rc;
2974}
2975
a66098da
LB		 2976/*
2977 * CMD_SET_PRE_SCAN.
2978 */
2979struct mwl8k_cmd_set_pre_scan {
2980 struct mwl8k_cmd_pkt header;
ba2d3587 2981} __packed;
a66098da
LB		 2982
2983static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2984{
2985 struct mwl8k_cmd_set_pre_scan *cmd;
2986 int rc;
2987
2988 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2989 if (cmd == NULL)
2990 return -ENOMEM;
2991
2992 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2993 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2994
2995 rc = mwl8k_post_cmd(hw, &cmd->header);
2996 kfree(cmd);
2997
2998 return rc;
2999}
3000
c3015313
YAP		 3001/*
3002 * CMD_BBP_REG_ACCESS.
3003 */
3004struct mwl8k_cmd_bbp_reg_access {
3005 struct mwl8k_cmd_pkt header;
3006 __le16 action;
3007 __le16 offset;
3008 u8 value;
3009 u8 rsrv[3];
3010} __packed;
3011
3012static int
3013mwl8k_cmd_bbp_reg_access(struct ieee80211_hw *hw,
3014 u16 action,
3015 u16 offset,
3016 u8 *value)
3017{
3018 struct mwl8k_cmd_bbp_reg_access *cmd;
3019 int rc;
3020
3021 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3022 if (cmd == NULL)
3023 return -ENOMEM;
3024
3025 cmd->header.code = cpu_to_le16(MWL8K_CMD_BBP_REG_ACCESS);
3026 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3027 cmd->action = cpu_to_le16(action);
3028 cmd->offset = cpu_to_le16(offset);
3029
3030 rc = mwl8k_post_cmd(hw, &cmd->header);
3031
3032 if (!rc)
3033 *value = cmd->value;
3034 else
3035 *value = 0;
3036
3037 kfree(cmd);
3038
3039 return rc;
3040}
3041
a66098da
LB		 3042/*
3043 * CMD_SET_POST_SCAN.
3044 */
3045struct mwl8k_cmd_set_post_scan {
3046 struct mwl8k_cmd_pkt header;
3047 __le32 isibss;
d89173f2 3048 __u8 bssid[ETH_ALEN];
ba2d3587 3049} __packed;
a66098da
LB		 3050
3051static int
0a11dfc3 3052mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 3053{
3054 struct mwl8k_cmd_set_post_scan *cmd;
3055 int rc;
3056
3057 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3058 if (cmd == NULL)
3059 return -ENOMEM;
3060
3061 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
3062 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3063 cmd->isibss = 0;
d89173f2 3064 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 3065
3066 rc = mwl8k_post_cmd(hw, &cmd->header);
3067 kfree(cmd);
3068
3069 return rc;
3070}
3071
031eb464
YAP		 3072static int freq_to_idx(struct mwl8k_priv *priv, int freq)
3073{
3074 struct ieee80211_supported_band *sband;
3075 int band, ch, idx = 0;
3076
3077 for (band = IEEE80211_BAND_2GHZ; band < IEEE80211_NUM_BANDS; band++) {
3078 sband = priv->hw->wiphy->bands[band];
3079 if (!sband)
3080 continue;
3081
3082 for (ch = 0; ch < sband->n_channels; ch++, idx++)
3083 if (sband->channels[ch].center_freq == freq)
3084 goto exit;
3085 }
3086
3087exit:
3088 return idx;
3089}
3090
c7c361ef
YAP		 3091static void mwl8k_update_survey(struct mwl8k_priv *priv,
3092 struct ieee80211_channel *channel)
031eb464
YAP		 3093{
3094 u32 cca_cnt, rx_rdy;
3095 s8 nf = 0, idx;
3096 struct survey_info *survey;
3097
3098 idx = freq_to_idx(priv, priv->acs_chan->center_freq);
3099 if (idx >= MWL8K_NUM_CHANS) {
3100 wiphy_err(priv->hw->wiphy, "Failed to update survey\n");
3101 return;
3102 }
3103
3104 survey = &priv->survey[idx];
3105
aa0bee1f 3106 cca_cnt = ioread32(priv->regs + NOK_CCA_CNT_REG);
031eb464
YAP		 3107 cca_cnt /= 1000; /* uSecs to mSecs */
3108 survey->channel_time_busy = (u64) cca_cnt;
3109
aa0bee1f 3110 rx_rdy = ioread32(priv->regs + BBU_RXRDY_CNT_REG);
031eb464
YAP		 3111 rx_rdy /= 1000; /* uSecs to mSecs */
3112 survey->channel_time_rx = (u64) rx_rdy;
3113
3114 priv->channel_time = jiffies - priv->channel_time;
3115 survey->channel_time = jiffies_to_msecs(priv->channel_time);
3116
3117 survey->channel = channel;
3118
3119 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &nf);
3120
3121 /* Make sure sign is negative else ACS at hostapd fails */
3122 survey->noise = nf * -1;
3123
3124 survey->filled = SURVEY_INFO_NOISE_DBM |
3125 SURVEY_INFO_CHANNEL_TIME |
3126 SURVEY_INFO_CHANNEL_TIME_BUSY |
3127 SURVEY_INFO_CHANNEL_TIME_RX;
3128}
3129
a66098da
LB		 3130/*
3131 * CMD_SET_RF_CHANNEL.
3132 */
3133struct mwl8k_cmd_set_rf_channel {
3134 struct mwl8k_cmd_pkt header;
3135 __le16 action;
3136 __u8 current_channel;
3137 __le32 channel_flags;
ba2d3587 3138} __packed;
a66098da
LB		 3139
3140static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 3141 struct ieee80211_conf *conf)
a66098da 3142{
675a0b04
KB		 3143 struct ieee80211_channel *channel = conf->chandef.chan;
3144 enum nl80211_channel_type channel_type =
3145 cfg80211_get_chandef_type(&conf->chandef);
a66098da 3146 struct mwl8k_cmd_set_rf_channel *cmd;
031eb464 3147 struct mwl8k_priv *priv = hw->priv;
a66098da
LB		 3148 int rc;
3149
3150 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3151 if (cmd == NULL)
3152 return -ENOMEM;
3153
3154 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
3155 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3156 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3157 cmd->current_channel = channel->hw_value;
610677d2 3158
a66098da 3159 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 3160 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 3161 else if (channel->band == IEEE80211_BAND_5GHZ)
3162 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2 3163
031eb464
YAP		 3164 if (!priv->sw_scan_start) {
3165 if (channel_type == NL80211_CHAN_NO_HT ||
3166 channel_type == NL80211_CHAN_HT20)
3167 cmd->channel_flags |= cpu_to_le32(0x00000080);
3168 else if (channel_type == NL80211_CHAN_HT40MINUS)
3169 cmd->channel_flags |= cpu_to_le32(0x000001900);
3170 else if (channel_type == NL80211_CHAN_HT40PLUS)
3171 cmd->channel_flags |= cpu_to_le32(0x000000900);
3172 } else {
610677d2 3173 cmd->channel_flags |= cpu_to_le32(0x00000080);
031eb464
YAP		 3174 }
3175
3176 if (priv->sw_scan_start) {
3177 /* Store current channel stats
3178 * before switching to newer one.
3179 * This will be processed only for AP fw.
3180 */
3181 if (priv->channel_time != 0)
3182 mwl8k_update_survey(priv, priv->acs_chan);
3183
3184 priv->channel_time = jiffies;
3185 priv->acs_chan = channel;
3186 }
a66098da
LB		 3187
3188 rc = mwl8k_post_cmd(hw, &cmd->header);
3189 kfree(cmd);
3190
3191 return rc;
3192}
3193
3194/*
55489b6e 3195 * CMD_SET_AID.
a66098da 3196 */
55489b6e
LB		 3197#define MWL8K_FRAME_PROT_DISABLED 0x00
3198#define MWL8K_FRAME_PROT_11G 0x07
3199#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
3200#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 3201
55489b6e
LB		 3202struct mwl8k_cmd_update_set_aid {
3203 struct mwl8k_cmd_pkt header;
3204 __le16 aid;
a66098da 3205
55489b6e
LB		 3206 /* AP's MAC address (BSSID) */
3207 __u8 bssid[ETH_ALEN];
3208 __le16 protection_mode;
3209 __u8 supp_rates[14];
ba2d3587 3210} __packed;
a66098da 3211
c6e96010
LB		 3212static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
3213{
3214 int i;
3215 int j;
3216
3217 /*
3f524559 3218 * Clear nonstandard rate 4.
c6e96010
LB		 3219 */
3220 mask &= 0x1fef;
3221
3f524559 3222 for (i = 0, j = 0; i < 13; i++) {
c6e96010 3223 if (mask & (1 << i))
777ad375 3224 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 3225 }
3226}
3227
55489b6e 3228static int
c6e96010
LB		 3229mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
3230 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 3231{
55489b6e
LB		 3232 struct mwl8k_cmd_update_set_aid *cmd;
3233 u16 prot_mode;
a66098da
LB		 3234 int rc;
3235
3236 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3237 if (cmd == NULL)
3238 return -ENOMEM;
3239
55489b6e 3240 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 3241 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 3242 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 3243 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3244
7dc6a7a7 3245 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 3246 prot_mode = MWL8K_FRAME_PROT_11G;
3247 } else {
7dc6a7a7 3248 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 3249 IEEE80211_HT_OP_MODE_PROTECTION) {
3250 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
3251 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
3252 break;
3253 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
3254 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
3255 break;
3256 default:
3257 prot_mode = MWL8K_FRAME_PROT_DISABLED;
3258 break;
3259 }
3260 }
3261 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 3262
c6e96010 3263 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 3264
3265 rc = mwl8k_post_cmd(hw, &cmd->header);
3266 kfree(cmd);
3267
3268 return rc;
3269}
3270
32060e1b 3271/*
55489b6e 3272 * CMD_SET_RATE.
32060e1b 3273 */
55489b6e
LB		 3274struct mwl8k_cmd_set_rate {
3275 struct mwl8k_cmd_pkt header;
3276 __u8 legacy_rates[14];
3277
3278 /* Bitmap for supported MCS codes. */
3279 __u8 mcs_set[16];
3280 __u8 reserved[16];
ba2d3587 3281} __packed;
32060e1b 3282
55489b6e 3283static int
c6e96010 3284mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 3285 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 3286{
55489b6e 3287 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 3288 int rc;
3289
3290 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3291 if (cmd == NULL)
3292 return -ENOMEM;
3293
55489b6e 3294 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 3295 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 3296 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 3297 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 3298
3299 rc = mwl8k_post_cmd(hw, &cmd->header);
3300 kfree(cmd);
3301
3302 return rc;
3303}
3304
a66098da 3305/*
55489b6e 3306 * CMD_FINALIZE_JOIN.
a66098da 3307 */
55489b6e
LB		 3308#define MWL8K_FJ_BEACON_MAXLEN 128
3309
3310struct mwl8k_cmd_finalize_join {
a66098da 3311 struct mwl8k_cmd_pkt header;
55489b6e
LB		 3312 __le32 sleep_interval; /* Number of beacon periods to sleep */
3313 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 3314} __packed;
a66098da 3315
55489b6e
LB		 3316static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
3317 int framelen, int dtim)
a66098da 3318{
55489b6e
LB		 3319 struct mwl8k_cmd_finalize_join *cmd;
3320 struct ieee80211_mgmt *payload = frame;
3321 int payload_len;
a66098da
LB		 3322 int rc;
3323
3324 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3325 if (cmd == NULL)
3326 return -ENOMEM;
3327
55489b6e 3328 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 3329 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3330 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
3331
3332 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
3333 if (payload_len < 0)
3334 payload_len = 0;
3335 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
3336 payload_len = MWL8K_FJ_BEACON_MAXLEN;
3337
3338 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 3339
3340 rc = mwl8k_post_cmd(hw, &cmd->header);
3341 kfree(cmd);
3342
3343 return rc;
3344}
3345
3346/*
55489b6e 3347 * CMD_SET_RTS_THRESHOLD.
a66098da 3348 */
55489b6e 3349struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 3350 struct mwl8k_cmd_pkt header;
3351 __le16 action;
55489b6e 3352 __le16 threshold;
ba2d3587 3353} __packed;
a66098da 3354
c2c2b12a
LB		 3355static int
3356mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 3357{
55489b6e 3358 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 3359 int rc;
3360
3361 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3362 if (cmd == NULL)
3363 return -ENOMEM;
3364
55489b6e 3365 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 3366 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 3367 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3368 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 3369
3370 rc = mwl8k_post_cmd(hw, &cmd->header);
3371 kfree(cmd);
3372
a66098da
LB		 3373 return rc;
3374}
3375
3376/*
55489b6e 3377 * CMD_SET_SLOT.
a66098da 3378 */
55489b6e 3379struct mwl8k_cmd_set_slot {
a66098da
LB		 3380 struct mwl8k_cmd_pkt header;
3381 __le16 action;
55489b6e 3382 __u8 short_slot;
ba2d3587 3383} __packed;
a66098da 3384
55489b6e 3385static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 3386{
55489b6e 3387 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 3388 int rc;
3389
3390 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3391 if (cmd == NULL)
3392 return -ENOMEM;
3393
55489b6e 3394 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 3395 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3396 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3397 cmd->short_slot = short_slot_time;
a66098da
LB		 3398
3399 rc = mwl8k_post_cmd(hw, &cmd->header);
3400 kfree(cmd);
3401
3402 return rc;
3403}
3404
3405/*
3406 * CMD_SET_EDCA_PARAMS.
3407 */
3408struct mwl8k_cmd_set_edca_params {
3409 struct mwl8k_cmd_pkt header;
3410
3411 /* See MWL8K_SET_EDCA_XXX below */
3412 __le16 action;
3413
3414 /* TX opportunity in units of 32 us */
3415 __le16 txop;
3416
2e484c89
LB		 3417 union {
3418 struct {
3419 /* Log exponent of max contention period: 0...15 */
3420 __le32 log_cw_max;
3421
3422 /* Log exponent of min contention period: 0...15 */
3423 __le32 log_cw_min;
3424
3425 /* Adaptive interframe spacing in units of 32us */
3426 __u8 aifs;
3427
3428 /* TX queue to configure */
3429 __u8 txq;
3430 } ap;
3431 struct {
3432 /* Log exponent of max contention period: 0...15 */
3433 __u8 log_cw_max;
a66098da 3434
2e484c89
LB		 3435 /* Log exponent of min contention period: 0...15 */
3436 __u8 log_cw_min;
a66098da 3437
2e484c89
LB		 3438 /* Adaptive interframe spacing in units of 32us */
3439 __u8 aifs;
a66098da 3440
2e484c89
LB		 3441 /* TX queue to configure */
3442 __u8 txq;
3443 } sta;
3444 };
ba2d3587 3445} __packed;
a66098da 3446
a66098da
LB		 3447#define MWL8K_SET_EDCA_CW 0x01
3448#define MWL8K_SET_EDCA_TXOP 0x02
3449#define MWL8K_SET_EDCA_AIFS 0x04
3450
3451#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
3452 MWL8K_SET_EDCA_TXOP | \
3453 MWL8K_SET_EDCA_AIFS)
3454
3455static int
55489b6e
LB		 3456mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
3457 __u16 cw_min, __u16 cw_max,
3458 __u8 aifs, __u16 txop)
a66098da 3459{
2e484c89 3460 struct mwl8k_priv *priv = hw->priv;
a66098da 3461 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 3462 int rc;
3463
3464 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3465 if (cmd == NULL)
3466 return -ENOMEM;
3467
a66098da
LB		 3468 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
3469 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 3470 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
3471 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 3472 if (priv->ap_fw) {
3473 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
3474 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
3475 cmd->ap.aifs = aifs;
3476 cmd->ap.txq = qnum;
3477 } else {
3478 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
3479 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
3480 cmd->sta.aifs = aifs;
3481 cmd->sta.txq = qnum;
3482 }
a66098da
LB		 3483
3484 rc = mwl8k_post_cmd(hw, &cmd->header);
3485 kfree(cmd);
3486
3487 return rc;
3488}
3489
3490/*
55489b6e 3491 * CMD_SET_WMM_MODE.
a66098da 3492 */
55489b6e 3493struct mwl8k_cmd_set_wmm_mode {
a66098da 3494 struct mwl8k_cmd_pkt header;
55489b6e 3495 __le16 action;
ba2d3587 3496} __packed;
a66098da 3497
55489b6e 3498static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 3499{
55489b6e
LB		 3500 struct mwl8k_priv *priv = hw->priv;
3501 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 3502 int rc;
3503
a66098da
LB		 3504 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3505 if (cmd == NULL)
3506 return -ENOMEM;
3507
55489b6e 3508 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 3509 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 3510 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 3511
3512 rc = mwl8k_post_cmd(hw, &cmd->header);
3513 kfree(cmd);
16cec43d 3514
55489b6e
LB		 3515 if (!rc)
3516 priv->wmm_enabled = enable;
a66098da
LB		 3517
3518 return rc;
3519}
3520
3521/*
55489b6e 3522 * CMD_MIMO_CONFIG.
a66098da 3523 */
55489b6e
LB		 3524struct mwl8k_cmd_mimo_config {
3525 struct mwl8k_cmd_pkt header;
3526 __le32 action;
3527 __u8 rx_antenna_map;
3528 __u8 tx_antenna_map;
ba2d3587 3529} __packed;
a66098da 3530
55489b6e 3531static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 3532{
55489b6e 3533 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 3534 int rc;
3535
3536 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3537 if (cmd == NULL)
3538 return -ENOMEM;
3539
55489b6e 3540 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 3541 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3542 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
3543 cmd->rx_antenna_map = rx;
3544 cmd->tx_antenna_map = tx;
a66098da
LB		 3545
3546 rc = mwl8k_post_cmd(hw, &cmd->header);
3547 kfree(cmd);
3548
3549 return rc;
3550}
3551
3552/*
b71ed2c6 3553 * CMD_USE_FIXED_RATE (STA version).
a66098da 3554 */
b71ed2c6
LB		 3555struct mwl8k_cmd_use_fixed_rate_sta {
3556 struct mwl8k_cmd_pkt header;
3557 __le32 action;
3558 __le32 allow_rate_drop;
3559 __le32 num_rates;
3560 struct {
3561 __le32 is_ht_rate;
3562 __le32 enable_retry;
3563 __le32 rate;
3564 __le32 retry_count;
3565 } rate_entry[8];
3566 __le32 rate_type;
3567 __le32 reserved1;
3568 __le32 reserved2;
ba2d3587 3569} __packed;
a66098da 3570
b71ed2c6
LB		 3571#define MWL8K_USE_AUTO_RATE 0x0002
3572#define MWL8K_UCAST_RATE 0
a66098da 3573
b71ed2c6 3574static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 3575{
b71ed2c6 3576 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 3577 int rc;
3578
3579 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3580 if (cmd == NULL)
3581 return -ENOMEM;
3582
3583 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3584 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 3585 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3586 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 3587
3588 rc = mwl8k_post_cmd(hw, &cmd->header);
3589 kfree(cmd);
3590
3591 return rc;
3592}
3593
088aab8b
LB		 3594/*
3595 * CMD_USE_FIXED_RATE (AP version).
3596 */
3597struct mwl8k_cmd_use_fixed_rate_ap {
3598 struct mwl8k_cmd_pkt header;
3599 __le32 action;
3600 __le32 allow_rate_drop;
3601 __le32 num_rates;
3602 struct mwl8k_rate_entry_ap {
3603 __le32 is_ht_rate;
3604 __le32 enable_retry;
3605 __le32 rate;
3606 __le32 retry_count;
3607 } rate_entry[4];
3608 u8 multicast_rate;
3609 u8 multicast_rate_type;
3610 u8 management_rate;
ba2d3587 3611} __packed;
088aab8b
LB		 3612
3613static int
3614mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
3615{
3616 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
3617 int rc;
3618
3619 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3620 if (cmd == NULL)
3621 return -ENOMEM;
3622
3623 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3624 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3625 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3626 cmd->multicast_rate = mcast;
3627 cmd->management_rate = mgmt;
3628
3629 rc = mwl8k_post_cmd(hw, &cmd->header);
3630 kfree(cmd);
3631
3632 return rc;
3633}
3634
55489b6e
LB		 3635/*
3636 * CMD_ENABLE_SNIFFER.
3637 */
3638struct mwl8k_cmd_enable_sniffer {
3639 struct mwl8k_cmd_pkt header;
3640 __le32 action;
ba2d3587 3641} __packed;
55489b6e
LB		 3642
3643static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3644{
3645 struct mwl8k_cmd_enable_sniffer *cmd;
3646 int rc;
3647
3648 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3649 if (cmd == NULL)
3650 return -ENOMEM;
3651
3652 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3653 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3654 cmd->action = cpu_to_le32(!!enable);
3655
3656 rc = mwl8k_post_cmd(hw, &cmd->header);
3657 kfree(cmd);
3658
3659 return rc;
3660}
3661
197a4e4e 3662struct mwl8k_cmd_update_mac_addr {
55489b6e
LB		 3663 struct mwl8k_cmd_pkt header;
3664 union {
3665 struct {
3666 __le16 mac_type;
3667 __u8 mac_addr[ETH_ALEN];
3668 } mbss;
3669 __u8 mac_addr[ETH_ALEN];
3670 };
ba2d3587 3671} __packed;
55489b6e 3672
ee0ddf18
LB		 3673#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3674#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3675#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3676#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3677
197a4e4e
YAP		 3678static int mwl8k_cmd_update_mac_addr(struct ieee80211_hw *hw,
3679 struct ieee80211_vif *vif, u8 *mac, bool set)
55489b6e
LB		 3680{
3681 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3682 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
197a4e4e 3683 struct mwl8k_cmd_update_mac_addr *cmd;
ee0ddf18 3684 int mac_type;
55489b6e
LB		 3685 int rc;
3686
ee0ddf18
LB		 3687 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3688 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3689 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
af458831
YAP		 3690 if (priv->ap_fw)
3691 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3692 else
3693 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
ee0ddf18
LB		 3694 else
3695 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3696 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3697 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3698 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3699 else
3700 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3701 }
3702
55489b6e
LB		 3703 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3704 if (cmd == NULL)
3705 return -ENOMEM;
3706
197a4e4e
YAP		 3707 if (set)
3708 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3709 else
3710 cmd->header.code = cpu_to_le16(MWL8K_CMD_DEL_MAC_ADDR);
3711
55489b6e
LB		 3712 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3713 if (priv->ap_fw) {
ee0ddf18 3714 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 3715 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3716 } else {
3717 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3718 }
3719
aa21d0f6 3720 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 3721 kfree(cmd);
3722
3723 return rc;
3724}
3725
197a4e4e
YAP		 3726/*
3727 * MWL8K_CMD_SET_MAC_ADDR.
3728 */
3729static inline int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3730 struct ieee80211_vif *vif, u8 *mac)
3731{
3732 return mwl8k_cmd_update_mac_addr(hw, vif, mac, true);
3733}
3734
3735/*
3736 * MWL8K_CMD_DEL_MAC_ADDR.
3737 */
3738static inline int mwl8k_cmd_del_mac_addr(struct ieee80211_hw *hw,
3739 struct ieee80211_vif *vif, u8 *mac)
3740{
3741 return mwl8k_cmd_update_mac_addr(hw, vif, mac, false);
3742}
3743
55489b6e
LB		 3744/*
3745 * CMD_SET_RATEADAPT_MODE.
3746 */
3747struct mwl8k_cmd_set_rate_adapt_mode {
3748 struct mwl8k_cmd_pkt header;
3749 __le16 action;
3750 __le16 mode;
ba2d3587 3751} __packed;
55489b6e
LB		 3752
3753static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3754{
3755 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3756 int rc;
3757
3758 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3759 if (cmd == NULL)
3760 return -ENOMEM;
3761
3762 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3763 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3764 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3765 cmd->mode = cpu_to_le16(mode);
3766
3767 rc = mwl8k_post_cmd(hw, &cmd->header);
3768 kfree(cmd);
3769
3770 return rc;
3771}
3772
3aefc37e
NS		 3773/*
3774 * CMD_GET_WATCHDOG_BITMAP.
3775 */
3776struct mwl8k_cmd_get_watchdog_bitmap {
3777 struct mwl8k_cmd_pkt header;
3778 u8 bitmap;
3779} __packed;
3780
3781static int mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw *hw, u8 *bitmap)
3782{
3783 struct mwl8k_cmd_get_watchdog_bitmap *cmd;
3784 int rc;
3785
3786 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3787 if (cmd == NULL)
3788 return -ENOMEM;
3789
3790 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_WATCHDOG_BITMAP);
3791 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3792
3793 rc = mwl8k_post_cmd(hw, &cmd->header);
3794 if (!rc)
3795 *bitmap = cmd->bitmap;
3796
3797 kfree(cmd);
3798
3799 return rc;
3800}
3801
cfacba12
YAP		 3802#define MWL8K_WMM_QUEUE_NUMBER 3
3803
3804static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
3805 u8 idx);
3806
3aefc37e
NS		 3807static void mwl8k_watchdog_ba_events(struct work_struct *work)
3808{
3809 int rc;
3810 u8 bitmap = 0, stream_index;
3811 struct mwl8k_ampdu_stream *streams;
3812 struct mwl8k_priv *priv =
3813 container_of(work, struct mwl8k_priv, watchdog_ba_handle);
cfacba12
YAP		 3814 struct ieee80211_hw *hw = priv->hw;
3815 int i;
3816 u32 status = 0;
3817
3818 mwl8k_fw_lock(hw);
3aefc37e
NS		 3819
3820 rc = mwl8k_cmd_get_watchdog_bitmap(priv->hw, &bitmap);
3821 if (rc)
cfacba12 3822 goto done;
3aefc37e 3823
cfacba12 3824 spin_lock(&priv->stream_lock);
3aefc37e
NS		 3825
3826 /* the bitmap is the hw queue number. Map it to the ampdu queue. */
cfacba12
YAP		 3827 for (i = 0; i < TOTAL_HW_TX_QUEUES; i++) {
3828 if (bitmap & (1 << i)) {
3829 stream_index = (i + MWL8K_WMM_QUEUE_NUMBER) %
3830 TOTAL_HW_TX_QUEUES;
3831 streams = &priv->ampdu[stream_index];
3832 if (streams->state == AMPDU_STREAM_ACTIVE) {
3833 ieee80211_stop_tx_ba_session(streams->sta,
3834 streams->tid);
3835 spin_unlock(&priv->stream_lock);
3836 mwl8k_destroy_ba(hw, stream_index);
3837 spin_lock(&priv->stream_lock);
3838 }
3839 }
3840 }
3aefc37e 3841
cfacba12
YAP		 3842 spin_unlock(&priv->stream_lock);
3843done:
c27a54d3 3844 atomic_dec(&priv->watchdog_event_pending);
cfacba12
YAP		 3845 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3846 iowrite32((status | MWL8K_A2H_INT_BA_WATCHDOG),
3847 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3848 mwl8k_fw_unlock(hw);
3aefc37e
NS		 3849 return;
3850}
3851
3852
b64fe619
LB		 3853/*
3854 * CMD_BSS_START.
3855 */
3856struct mwl8k_cmd_bss_start {
3857 struct mwl8k_cmd_pkt header;
3858 __le32 enable;
ba2d3587 3859} __packed;
b64fe619 3860
aa21d0f6
LB		 3861static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3862 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 3863{
3864 struct mwl8k_cmd_bss_start *cmd;
e882efc9
YAP		 3865 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3866 struct mwl8k_priv *priv = hw->priv;
b64fe619
LB		 3867 int rc;
3868
e882efc9
YAP		 3869 if (enable && (priv->running_bsses & (1 << mwl8k_vif->macid)))
3870 return 0;
3871
3872 if (!enable && !(priv->running_bsses & (1 << mwl8k_vif->macid)))
3873 return 0;
3874
b64fe619
LB		 3875 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3876 if (cmd == NULL)
3877 return -ENOMEM;
3878
3879 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3880 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3881 cmd->enable = cpu_to_le32(enable);
3882
aa21d0f6 3883 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3884 kfree(cmd);
3885
e882efc9
YAP		 3886 if (!rc) {
3887 if (enable)
3888 priv->running_bsses |= (1 << mwl8k_vif->macid);
3889 else
3890 priv->running_bsses &= ~(1 << mwl8k_vif->macid);
3891 }
b64fe619
LB		 3892 return rc;
3893}
3894
e882efc9
YAP		 3895static void mwl8k_enable_bsses(struct ieee80211_hw *hw, bool enable, u32 bitmap)
3896{
3897 struct mwl8k_priv *priv = hw->priv;
3898 struct mwl8k_vif *mwl8k_vif, *tmp_vif;
3899 struct ieee80211_vif *vif;
3900
3901 list_for_each_entry_safe(mwl8k_vif, tmp_vif, &priv->vif_list, list) {
3902 vif = mwl8k_vif->vif;
3903
3904 if (!(bitmap & (1 << mwl8k_vif->macid)))
3905 continue;
3906
3907 if (vif->type == NL80211_IFTYPE_AP)
3908 mwl8k_cmd_bss_start(hw, vif, enable);
3909 }
3910}
5faa1aff
NS		 3911/*
3912 * CMD_BASTREAM.
3913 */
3914
3915/*
3916 * UPSTREAM is tx direction
3917 */
3918#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3919#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3920
ba30c4a5 3921enum ba_stream_action_type {
5faa1aff
NS		 3922 MWL8K_BA_CREATE,
3923 MWL8K_BA_UPDATE,
3924 MWL8K_BA_DESTROY,
3925 MWL8K_BA_FLUSH,
3926 MWL8K_BA_CHECK,
ba30c4a5 3927};
5faa1aff
NS		 3928
3929
3930struct mwl8k_create_ba_stream {
3931 __le32 flags;
3932 __le32 idle_thrs;
3933 __le32 bar_thrs;
3934 __le32 window_size;
3935 u8 peer_mac_addr[6];
3936 u8 dialog_token;
3937 u8 tid;
3938 u8 queue_id;
3939 u8 param_info;
3940 __le32 ba_context;
3941 u8 reset_seq_no_flag;
3942 __le16 curr_seq_no;
3943 u8 sta_src_mac_addr[6];
3944} __packed;
3945
3946struct mwl8k_destroy_ba_stream {
3947 __le32 flags;
3948 __le32 ba_context;
3949} __packed;
3950
3951struct mwl8k_cmd_bastream {
3952 struct mwl8k_cmd_pkt header;
3953 __le32 action;
3954 union {
3955 struct mwl8k_create_ba_stream create_params;
3956 struct mwl8k_destroy_ba_stream destroy_params;
3957 };
3958} __packed;
3959
3960static int
f95275c4
YAP		 3961mwl8k_check_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
3962 struct ieee80211_vif *vif)
5faa1aff
NS		 3963{
3964 struct mwl8k_cmd_bastream *cmd;
3965 int rc;
3966
3967 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3968 if (cmd == NULL)
3969 return -ENOMEM;
3970
3971 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3972 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3973
3974 cmd->action = cpu_to_le32(MWL8K_BA_CHECK);
3975
3976 cmd->create_params.queue_id = stream->idx;
3977 memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr,
3978 ETH_ALEN);
3979 cmd->create_params.tid = stream->tid;
3980
3981 cmd->create_params.flags =
3982 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE) |
3983 cpu_to_le32(BASTREAM_FLAG_DIRECTION_UPSTREAM);
3984
f95275c4 3985 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
5faa1aff
NS		 3986
3987 kfree(cmd);
3988
3989 return rc;
3990}
3991
3992static int
3993mwl8k_create_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
f95275c4 3994 u8 buf_size, struct ieee80211_vif *vif)
5faa1aff
NS		 3995{
3996 struct mwl8k_cmd_bastream *cmd;
3997 int rc;
3998
3999 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4000 if (cmd == NULL)
4001 return -ENOMEM;
4002
4003
4004 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
4005 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4006
4007 cmd->action = cpu_to_le32(MWL8K_BA_CREATE);
4008
4009 cmd->create_params.bar_thrs = cpu_to_le32((u32)buf_size);
4010 cmd->create_params.window_size = cpu_to_le32((u32)buf_size);
4011 cmd->create_params.queue_id = stream->idx;
4012
4013 memcpy(cmd->create_params.peer_mac_addr, stream->sta->addr, ETH_ALEN);
4014 cmd->create_params.tid = stream->tid;
4015 cmd->create_params.curr_seq_no = cpu_to_le16(0);
4016 cmd->create_params.reset_seq_no_flag = 1;
4017
4018 cmd->create_params.param_info =
4019 (stream->sta->ht_cap.ampdu_factor &
4020 IEEE80211_HT_AMPDU_PARM_FACTOR) |
4021 ((stream->sta->ht_cap.ampdu_density << 2) &
4022 IEEE80211_HT_AMPDU_PARM_DENSITY);
4023
4024 cmd->create_params.flags =
4025 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE |
4026 BASTREAM_FLAG_DIRECTION_UPSTREAM);
4027
f95275c4 4028 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
5faa1aff
NS		 4029
4030 wiphy_debug(hw->wiphy, "Created a BA stream for %pM : tid %d\n",
4031 stream->sta->addr, stream->tid);
4032 kfree(cmd);
4033
4034 return rc;
4035}
4036
4037static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
07f6dda1 4038 u8 idx)
5faa1aff
NS		 4039{
4040 struct mwl8k_cmd_bastream *cmd;
4041
4042 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4043 if (cmd == NULL)
4044 return;
4045
4046 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
4047 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4048 cmd->action = cpu_to_le32(MWL8K_BA_DESTROY);
4049
07f6dda1 4050 cmd->destroy_params.ba_context = cpu_to_le32(idx);
5faa1aff
NS		 4051 mwl8k_post_cmd(hw, &cmd->header);
4052
07f6dda1 4053 wiphy_debug(hw->wiphy, "Deleted BA stream index %d\n", idx);
5faa1aff
NS		 4054
4055 kfree(cmd);
4056}
4057
3f5610ff
LB		 4058/*
4059 * CMD_SET_NEW_STN.
4060 */
4061struct mwl8k_cmd_set_new_stn {
4062 struct mwl8k_cmd_pkt header;
4063 __le16 aid;
4064 __u8 mac_addr[6];
4065 __le16 stn_id;
4066 __le16 action;
4067 __le16 rsvd;
4068 __le32 legacy_rates;
4069 __u8 ht_rates[4];
4070 __le16 cap_info;
4071 __le16 ht_capabilities_info;
4072 __u8 mac_ht_param_info;
4073 __u8 rev;
4074 __u8 control_channel;
4075 __u8 add_channel;
4076 __le16 op_mode;
4077 __le16 stbc;
4078 __u8 add_qos_info;
4079 __u8 is_qos_sta;
4080 __le32 fw_sta_ptr;
ba2d3587 4081} __packed;
3f5610ff
LB		 4082
4083#define MWL8K_STA_ACTION_ADD 0
4084#define MWL8K_STA_ACTION_REMOVE 2
4085
4086static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
4087 struct ieee80211_vif *vif,
4088 struct ieee80211_sta *sta)
4089{
4090 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 4091 u32 rates;
3f5610ff
LB		 4092 int rc;
4093
4094 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4095 if (cmd == NULL)
4096 return -ENOMEM;
4097
4098 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4099 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4100 cmd->aid = cpu_to_le16(sta->aid);
4101 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
4102 cmd->stn_id = cpu_to_le16(sta->aid);
4103 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
675a0b04 4104 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ)
8707d026
LB		 4105 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4106 else
4107 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4108 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 4109 if (sta->ht_cap.ht_supported) {
4110 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
4111 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
4112 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
4113 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
4114 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
4115 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
4116 ((sta->ht_cap.ampdu_density & 7) << 2);
4117 cmd->is_qos_sta = 1;
4118 }
4119
aa21d0f6 4120 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 4121 kfree(cmd);
4122
4123 return rc;
4124}
4125
b64fe619
LB		 4126static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
4127 struct ieee80211_vif *vif)
4128{
4129 struct mwl8k_cmd_set_new_stn *cmd;
4130 int rc;
4131
4132 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4133 if (cmd == NULL)
4134 return -ENOMEM;
4135
4136 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4137 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4138 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
4139
aa21d0f6 4140 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 4141 kfree(cmd);
4142
4143 return rc;
4144}
4145
3f5610ff
LB		 4146static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
4147 struct ieee80211_vif *vif, u8 *addr)
4148{
4149 struct mwl8k_cmd_set_new_stn *cmd;
0dd13a48
YAP		 4150 struct mwl8k_priv *priv = hw->priv;
4151 int rc, i;
4152 u8 idx;
4153
4154 spin_lock(&priv->stream_lock);
4155 /* Destroy any active ampdu streams for this sta */
4156 for (i = 0; i < MWL8K_NUM_AMPDU_STREAMS; i++) {
4157 struct mwl8k_ampdu_stream *s;
4158 s = &priv->ampdu[i];
4159 if (s->state != AMPDU_NO_STREAM) {
4160 if (memcmp(s->sta->addr, addr, ETH_ALEN) == 0) {
4161 if (s->state == AMPDU_STREAM_ACTIVE) {
4162 idx = s->idx;
4163 spin_unlock(&priv->stream_lock);
4164 mwl8k_destroy_ba(hw, idx);
4165 spin_lock(&priv->stream_lock);
4166 } else if (s->state == AMPDU_STREAM_NEW) {
4167 mwl8k_remove_stream(hw, s);
4168 }
4169 }
4170 }
4171 }
4172
4173 spin_unlock(&priv->stream_lock);
3f5610ff
LB		 4174
4175 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4176 if (cmd == NULL)
4177 return -ENOMEM;
4178
4179 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
4180 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4181 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4182 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
4183
aa21d0f6 4184 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 4185 kfree(cmd);
4186
4187 return rc;
4188}
4189
fcdc403c
NS		 4190/*
4191 * CMD_UPDATE_ENCRYPTION.
4192 */
4193
4194#define MAX_ENCR_KEY_LENGTH 16
4195#define MIC_KEY_LENGTH 8
4196
4197struct mwl8k_cmd_update_encryption {
4198 struct mwl8k_cmd_pkt header;
4199
4200 __le32 action;
4201 __le32 reserved;
4202 __u8 mac_addr[6];
4203 __u8 encr_type;
4204
ba30c4a5 4205} __packed;
fcdc403c
NS		 4206
4207struct mwl8k_cmd_set_key {
4208 struct mwl8k_cmd_pkt header;
4209
4210 __le32 action;
4211 __le32 reserved;
4212 __le16 length;
4213 __le16 key_type_id;
4214 __le32 key_info;
4215 __le32 key_id;
4216 __le16 key_len;
4217 __u8 key_material[MAX_ENCR_KEY_LENGTH];
4218 __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
4219 __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
4220 __le16 tkip_rsc_low;
4221 __le32 tkip_rsc_high;
4222 __le16 tkip_tsc_low;
4223 __le32 tkip_tsc_high;
4224 __u8 mac_addr[6];
ba30c4a5 4225} __packed;
fcdc403c
NS		 4226
4227enum {
4228 MWL8K_ENCR_ENABLE,
4229 MWL8K_ENCR_SET_KEY,
4230 MWL8K_ENCR_REMOVE_KEY,
4231 MWL8K_ENCR_SET_GROUP_KEY,
4232};
4233
4234#define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
4235#define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
4236#define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
4237#define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
4238#define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
4239
4240enum {
4241 MWL8K_ALG_WEP,
4242 MWL8K_ALG_TKIP,
4243 MWL8K_ALG_CCMP,
4244};
4245
4246#define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
4247#define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
4248#define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
4249#define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
4250#define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
4251
4252static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
4253 struct ieee80211_vif *vif,
4254 u8 *addr,
4255 u8 encr_type)
4256{
4257 struct mwl8k_cmd_update_encryption *cmd;
4258 int rc;
4259
4260 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4261 if (cmd == NULL)
4262 return -ENOMEM;
4263
4264 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4265 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4266 cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
4267 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4268 cmd->encr_type = encr_type;
4269
4270 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4271 kfree(cmd);
4272
4273 return rc;
4274}
4275
4276static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
4277 u8 *addr,
4278 struct ieee80211_key_conf *key)
4279{
4280 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
4281 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4282 cmd->length = cpu_to_le16(sizeof(*cmd) -
4283 offsetof(struct mwl8k_cmd_set_key, length));
4284 cmd->key_id = cpu_to_le32(key->keyidx);
4285 cmd->key_len = cpu_to_le16(key->keylen);
4286 memcpy(cmd->mac_addr, addr, ETH_ALEN);
4287
4288 switch (key->cipher) {
4289 case WLAN_CIPHER_SUITE_WEP40:
4290 case WLAN_CIPHER_SUITE_WEP104:
4291 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
4292 if (key->keyidx == 0)
4293 cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
4294
4295 break;
4296 case WLAN_CIPHER_SUITE_TKIP:
4297 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
4298 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4299 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4300 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4301 cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
4302 | MWL8K_KEY_FLAG_TSC_VALID);
4303 break;
4304 case WLAN_CIPHER_SUITE_CCMP:
4305 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
4306 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4307 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
4308 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
4309 break;
4310 default:
4311 return -ENOTSUPP;
4312 }
4313
4314 return 0;
4315}
4316
4317static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
4318 struct ieee80211_vif *vif,
4319 u8 *addr,
4320 struct ieee80211_key_conf *key)
4321{
4322 struct mwl8k_cmd_set_key *cmd;
4323 int rc;
4324 int keymlen;
4325 u32 action;
4326 u8 idx;
4327 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4328
4329 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4330 if (cmd == NULL)
4331 return -ENOMEM;
4332
4333 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4334 if (rc < 0)
4335 goto done;
4336
4337 idx = key->keyidx;
4338
4339 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
4340 action = MWL8K_ENCR_SET_KEY;
4341 else
4342 action = MWL8K_ENCR_SET_GROUP_KEY;
4343
4344 switch (key->cipher) {
4345 case WLAN_CIPHER_SUITE_WEP40:
4346 case WLAN_CIPHER_SUITE_WEP104:
4347 if (!mwl8k_vif->wep_key_conf[idx].enabled) {
4348 memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
4349 sizeof(*key) + key->keylen);
4350 mwl8k_vif->wep_key_conf[idx].enabled = 1;
4351 }
4352
9b571e24 4353 keymlen = key->keylen;
fcdc403c
NS		 4354 action = MWL8K_ENCR_SET_KEY;
4355 break;
4356 case WLAN_CIPHER_SUITE_TKIP:
4357 keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
4358 break;
4359 case WLAN_CIPHER_SUITE_CCMP:
4360 keymlen = key->keylen;
4361 break;
4362 default:
4363 rc = -ENOTSUPP;
4364 goto done;
4365 }
4366
4367 memcpy(cmd->key_material, key->key, keymlen);
4368 cmd->action = cpu_to_le32(action);
4369
4370 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4371done:
4372 kfree(cmd);
4373
4374 return rc;
4375}
4376
4377static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
4378 struct ieee80211_vif *vif,
4379 u8 *addr,
4380 struct ieee80211_key_conf *key)
4381{
4382 struct mwl8k_cmd_set_key *cmd;
4383 int rc;
4384 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4385
4386 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4387 if (cmd == NULL)
4388 return -ENOMEM;
4389
4390 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4391 if (rc < 0)
4392 goto done;
4393
4394 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
d981e059 4395 key->cipher == WLAN_CIPHER_SUITE_WEP104)
fcdc403c
NS		 4396 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
4397
4398 cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
4399
4400 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4401done:
4402 kfree(cmd);
4403
4404 return rc;
4405}
4406
4407static int mwl8k_set_key(struct ieee80211_hw *hw,
4408 enum set_key_cmd cmd_param,
4409 struct ieee80211_vif *vif,
4410 struct ieee80211_sta *sta,
4411 struct ieee80211_key_conf *key)
4412{
4413 int rc = 0;
4414 u8 encr_type;
4415 u8 *addr;
4416 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
751930cb 4417 struct mwl8k_priv *priv = hw->priv;
fcdc403c 4418
751930cb 4419 if (vif->type == NL80211_IFTYPE_STATION && !priv->ap_fw)
fcdc403c
NS		 4420 return -EOPNOTSUPP;
4421
4422 if (sta == NULL)
ff7e9f99 4423 addr = vif->addr;
fcdc403c
NS		 4424 else
4425 addr = sta->addr;
4426
4427 if (cmd_param == SET_KEY) {
fcdc403c
NS		 4428 rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
4429 if (rc)
4430 goto out;
4431
4432 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
4433 || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
4434 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
4435 else
4436 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
4437
4438 rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
4439 encr_type);
4440 if (rc)
4441 goto out;
4442
4443 mwl8k_vif->is_hw_crypto_enabled = true;
4444
4445 } else {
4446 rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
4447
4448 if (rc)
4449 goto out;
fcdc403c
NS		 4450 }
4451out:
4452 return rc;
4453}
4454
55489b6e
LB		 4455/*
4456 * CMD_UPDATE_STADB.
4457 */
25d81b1e
LB		 4458struct ewc_ht_info {
4459 __le16 control1;
4460 __le16 control2;
4461 __le16 control3;
ba2d3587 4462} __packed;
25d81b1e
LB		 4463
4464struct peer_capability_info {
4465 /* Peer type - AP vs. STA. */
4466 __u8 peer_type;
4467
4468 /* Basic 802.11 capabilities from assoc resp. */
4469 __le16 basic_caps;
4470
4471 /* Set if peer supports 802.11n high throughput (HT). */
4472 __u8 ht_support;
4473
4474 /* Valid if HT is supported. */
4475 __le16 ht_caps;
4476 __u8 extended_ht_caps;
4477 struct ewc_ht_info ewc_info;
4478
4479 /* Legacy rate table. Intersection of our rates and peer rates. */
4480 __u8 legacy_rates[12];
4481
4482 /* HT rate table. Intersection of our rates and peer rates. */
4483 __u8 ht_rates[16];
4484 __u8 pad[16];
4485
4486 /* If set, interoperability mode, no proprietary extensions. */
4487 __u8 interop;
4488 __u8 pad2;
4489 __u8 station_id;
4490 __le16 amsdu_enabled;
ba2d3587 4491} __packed;
25d81b1e 4492
55489b6e
LB		 4493struct mwl8k_cmd_update_stadb {
4494 struct mwl8k_cmd_pkt header;
4495
4496 /* See STADB_ACTION_TYPE */
4497 __le32 action;
4498
4499 /* Peer MAC address */
4500 __u8 peer_addr[ETH_ALEN];
4501
4502 __le32 reserved;
4503
4504 /* Peer info - valid during add/update. */
4505 struct peer_capability_info peer_info;
ba2d3587 4506} __packed;
55489b6e 4507
a680400e
LB		 4508#define MWL8K_STA_DB_MODIFY_ENTRY 1
4509#define MWL8K_STA_DB_DEL_ENTRY 2
4510
4511/* Peer Entry flags - used to define the type of the peer node */
4512#define MWL8K_PEER_TYPE_ACCESSPOINT 2
4513
4514static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 4515 struct ieee80211_vif *vif,
13935e2c 4516 struct ieee80211_sta *sta)
55489b6e 4517{
55489b6e 4518 struct mwl8k_cmd_update_stadb *cmd;
a680400e 4519 struct peer_capability_info *p;
8707d026 4520 u32 rates;
55489b6e
LB		 4521 int rc;
4522
4523 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4524 if (cmd == NULL)
4525 return -ENOMEM;
4526
4527 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4528 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 4529 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 4530 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 4531
a680400e
LB		 4532 p = &cmd->peer_info;
4533 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
4534 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 4535 p->ht_support = sta->ht_cap.ht_supported;
b603742f 4536 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 4537 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
4538 ((sta->ht_cap.ampdu_density & 7) << 2);
675a0b04 4539 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ)
8707d026
LB		 4540 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4541 else
4542 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4543 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 4544 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 4545 p->interop = 1;
4546 p->amsdu_enabled = 0;
4547
4548 rc = mwl8k_post_cmd(hw, &cmd->header);
c4f74d35
NZ		 4549 if (!rc)
4550 rc = p->station_id;
a680400e
LB		 4551 kfree(cmd);
4552
c4f74d35 4553 return rc;
a680400e
LB		 4554}
4555
4556static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
4557 struct ieee80211_vif *vif, u8 *addr)
4558{
4559 struct mwl8k_cmd_update_stadb *cmd;
4560 int rc;
4561
4562 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4563 if (cmd == NULL)
4564 return -ENOMEM;
4565
4566 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4567 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4568 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 4569 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 4570
a680400e 4571 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 4572 kfree(cmd);
4573
4574 return rc;
4575}
4576
a66098da
LB		 4577
4578/*
4579 * Interrupt handling.
4580 */
4581static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
4582{
4583 struct ieee80211_hw *hw = dev_id;
4584 struct mwl8k_priv *priv = hw->priv;
4585 u32 status;
4586
4587 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 4588 if (!status)
4589 return IRQ_NONE;
4590
1e9f9de3
LB		 4591 if (status & MWL8K_A2H_INT_TX_DONE) {
4592 status &= ~MWL8K_A2H_INT_TX_DONE;
4593 tasklet_schedule(&priv->poll_tx_task);
4594 }
4595
a66098da 4596 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 4597 status &= ~MWL8K_A2H_INT_RX_READY;
4598 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 4599 }
4600
3aefc37e 4601 if (status & MWL8K_A2H_INT_BA_WATCHDOG) {
c27a54d3
YAP		 4602 iowrite32(~MWL8K_A2H_INT_BA_WATCHDOG,
4603 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4604
4605 atomic_inc(&priv->watchdog_event_pending);
3aefc37e
NS		 4606 status &= ~MWL8K_A2H_INT_BA_WATCHDOG;
4607 ieee80211_queue_work(hw, &priv->watchdog_ba_handle);
4608 }
4609
67e2eb27
LB		 4610 if (status)
4611 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4612
a66098da 4613 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 4614 if (priv->hostcmd_wait != NULL)
a66098da 4615 complete(priv->hostcmd_wait);
a66098da
LB		 4616 }
4617
4618 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 4619 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 4620 priv->radio_on && priv->pending_tx_pkts)
618952a7 4621 mwl8k_tx_start(priv);
a66098da
LB		 4622 }
4623
4624 return IRQ_HANDLED;
4625}
4626
1e9f9de3
LB		 4627static void mwl8k_tx_poll(unsigned long data)
4628{
4629 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4630 struct mwl8k_priv *priv = hw->priv;
4631 int limit;
4632 int i;
4633
4634 limit = 32;
4635
4636 spin_lock_bh(&priv->tx_lock);
4637
e600707b 4638 for (i = 0; i < mwl8k_tx_queues(priv); i++)
1e9f9de3
LB		 4639 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
4640
4641 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
4642 complete(priv->tx_wait);
4643 priv->tx_wait = NULL;
4644 }
4645
4646 spin_unlock_bh(&priv->tx_lock);
4647
4648 if (limit) {
4649 writel(~MWL8K_A2H_INT_TX_DONE,
4650 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4651 } else {
4652 tasklet_schedule(&priv->poll_tx_task);
4653 }
4654}
4655
67e2eb27
LB		 4656static void mwl8k_rx_poll(unsigned long data)
4657{
4658 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4659 struct mwl8k_priv *priv = hw->priv;
4660 int limit;
4661
4662 limit = 32;
4663 limit -= rxq_process(hw, 0, limit);
4664 limit -= rxq_refill(hw, 0, limit);
4665
4666 if (limit) {
4667 writel(~MWL8K_A2H_INT_RX_READY,
4668 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4669 } else {
4670 tasklet_schedule(&priv->poll_rx_task);
4671 }
4672}
4673
a66098da
LB		 4674
4675/*
4676 * Core driver operations.
4677 */
36323f81
TH		 4678static void mwl8k_tx(struct ieee80211_hw *hw,
4679 struct ieee80211_tx_control *control,
4680 struct sk_buff *skb)
a66098da
LB		 4681{
4682 struct mwl8k_priv *priv = hw->priv;
4683 int index = skb_get_queue_mapping(skb);
a66098da 4684
9189c100 4685 if (!priv->radio_on) {
c96c31e4
JP		 4686 wiphy_debug(hw->wiphy,
4687 "dropped TX frame since radio disabled\n");
a66098da 4688 dev_kfree_skb(skb);
7bb45683 4689 return;
a66098da
LB		 4690 }
4691
36323f81 4692 mwl8k_txq_xmit(hw, index, control->sta, skb);
a66098da
LB		 4693}
4694
a66098da
LB		 4695static int mwl8k_start(struct ieee80211_hw *hw)
4696{
a66098da
LB		 4697 struct mwl8k_priv *priv = hw->priv;
4698 int rc;
4699
a0607fd3 4700 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4701 IRQF_SHARED, MWL8K_NAME, hw);
4702 if (rc) {
bf3ca7f7 4703 priv->irq = -1;
5db55844 4704 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 4705 return -EIO;
a66098da 4706 }
bf3ca7f7 4707 priv->irq = priv->pdev->irq;
a66098da 4708
67e2eb27 4709 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 4710 tasklet_enable(&priv->poll_tx_task);
67e2eb27 4711 tasklet_enable(&priv->poll_rx_task);
2ec610cb 4712
a66098da 4713 /* Enable interrupts */
c23b5a69 4714 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
12488e01
NS		 4715 iowrite32(MWL8K_A2H_EVENTS,
4716 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 4717
2ec610cb
LB		 4718 rc = mwl8k_fw_lock(hw);
4719 if (!rc) {
55489b6e 4720 rc = mwl8k_cmd_radio_enable(hw);
a66098da 4721
5e4cf166
LB		 4722 if (!priv->ap_fw) {
4723 if (!rc)
55489b6e 4724 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 4725
5e4cf166
LB		 4726 if (!rc)
4727 rc = mwl8k_cmd_set_pre_scan(hw);
4728
4729 if (!rc)
4730 rc = mwl8k_cmd_set_post_scan(hw,
4731 "\x00\x00\x00\x00\x00\x00");
4732 }
2ec610cb
LB		 4733
4734 if (!rc)
55489b6e 4735 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 4736
2ec610cb 4737 if (!rc)
55489b6e 4738 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 4739
2ec610cb
LB		 4740 mwl8k_fw_unlock(hw);
4741 }
4742
4743 if (rc) {
4744 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4745 free_irq(priv->pdev->irq, hw);
bf3ca7f7 4746 priv->irq = -1;
1e9f9de3 4747 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4748 tasklet_disable(&priv->poll_rx_task);
4850b6d3
NS		 4749 } else {
4750 ieee80211_wake_queues(hw);
2ec610cb 4751 }
a66098da
LB		 4752
4753 return rc;
4754}
4755
a66098da
LB		 4756static void mwl8k_stop(struct ieee80211_hw *hw)
4757{
a66098da
LB		 4758 struct mwl8k_priv *priv = hw->priv;
4759 int i;
4760
6b6accc3
YAP		 4761 if (!priv->hw_restart_in_progress)
4762 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 4763
4764 ieee80211_stop_queues(hw);
4765
a66098da 4766 /* Disable interrupts */
a66098da 4767 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
bf3ca7f7
BC		 4768 if (priv->irq != -1) {
4769 free_irq(priv->pdev->irq, hw);
4770 priv->irq = -1;
4771 }
a66098da
LB		 4772
4773 /* Stop finalize join worker */
4774 cancel_work_sync(&priv->finalize_join_worker);
3aefc37e 4775 cancel_work_sync(&priv->watchdog_ba_handle);
a66098da
LB		 4776 if (priv->beacon_skb != NULL)
4777 dev_kfree_skb(priv->beacon_skb);
4778
67e2eb27 4779 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 4780 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4781 tasklet_disable(&priv->poll_rx_task);
a66098da 4782
a66098da 4783 /* Return all skbs to mac80211 */
e600707b 4784 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 4785 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 4786}
4787
0863ade8
BC		 4788static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
4789
a66098da 4790static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 4791 struct ieee80211_vif *vif)
a66098da
LB		 4792{
4793 struct mwl8k_priv *priv = hw->priv;
4794 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 4795 u32 macids_supported;
0863ade8
BC		 4796 int macid, rc;
4797 struct mwl8k_device_info *di;
a66098da 4798
a43c49a8
LB		 4799 /*
4800 * Reject interface creation if sniffer mode is active, as
4801 * STA operation is mutually exclusive with hardware sniffer
b64fe619 4802 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 4803 */
4804 if (priv->sniffer_enabled) {
c96c31e4
JP		 4805 wiphy_info(hw->wiphy,
4806 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 4807 return -EINVAL;
4808 }
4809
0863ade8 4810 di = priv->device_info;
ee0ddf18
LB		 4811 switch (vif->type) {
4812 case NL80211_IFTYPE_AP:
0863ade8
BC		 4813 if (!priv->ap_fw && di->fw_image_ap) {
4814 /* we must load the ap fw to meet this request */
4815 if (!list_empty(&priv->vif_list))
4816 return -EBUSY;
4817 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4818 if (rc)
4819 return rc;
4820 }
ee0ddf18
LB		 4821 macids_supported = priv->ap_macids_supported;
4822 break;
4823 case NL80211_IFTYPE_STATION:
0863ade8 4824 if (priv->ap_fw && di->fw_image_sta) {
d59c1cfd
YAP		 4825 if (!list_empty(&priv->vif_list)) {
4826 wiphy_warn(hw->wiphy, "AP interface is running.\n"
4827 "Adding STA interface for WDS");
4828 } else {
4829 /* we must load the sta fw to
4830 * meet this request.
4831 */
4832 rc = mwl8k_reload_firmware(hw,
4833 di->fw_image_sta);
4834 if (rc)
4835 return rc;
4836 }
0863ade8 4837 }
ee0ddf18
LB		 4838 macids_supported = priv->sta_macids_supported;
4839 break;
4840 default:
4841 return -EINVAL;
4842 }
4843
4844 macid = ffs(macids_supported & ~priv->macids_used);
4845 if (!macid--)
4846 return -EBUSY;
4847
f5bb87cf 4848 /* Setup driver private area. */
1ed32e4f 4849 mwl8k_vif = MWL8K_VIF(vif);
a66098da 4850 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 4851 mwl8k_vif->vif = vif;
ee0ddf18 4852 mwl8k_vif->macid = macid;
a66098da 4853 mwl8k_vif->seqno = 0;
d9a07d49
NS		 4854 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
4855 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 4856
aa21d0f6
LB		 4857 /* Set the mac address. */
4858 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
4859
d994a1c8 4860 if (vif->type == NL80211_IFTYPE_AP)
aa21d0f6
LB		 4861 mwl8k_cmd_set_new_stn_add_self(hw, vif);
4862
ee0ddf18 4863 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 4864 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 4865
4866 return 0;
4867}
4868
6b6accc3
YAP		 4869static void mwl8k_remove_vif(struct mwl8k_priv *priv, struct mwl8k_vif *vif)
4870{
4871 /* Has ieee80211_restart_hw re-added the removed interfaces? */
4872 if (!priv->macids_used)
4873 return;
4874
4875 priv->macids_used &= ~(1 << vif->macid);
4876 list_del(&vif->list);
4877}
4878
a66098da 4879static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4880 struct ieee80211_vif *vif)
a66098da
LB		 4881{
4882 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 4883 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 4884
d994a1c8 4885 if (vif->type == NL80211_IFTYPE_AP)
b64fe619
LB		 4886 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
4887
197a4e4e 4888 mwl8k_cmd_del_mac_addr(hw, vif, vif->addr);
32060e1b 4889
6b6accc3
YAP		 4890 mwl8k_remove_vif(priv, mwl8k_vif);
4891}
4892
4893static void mwl8k_hw_restart_work(struct work_struct *work)
4894{
4895 struct mwl8k_priv *priv =
4896 container_of(work, struct mwl8k_priv, fw_reload);
4897 struct ieee80211_hw *hw = priv->hw;
4898 struct mwl8k_device_info *di;
4899 int rc;
4900
4901 /* If some command is waiting for a response, clear it */
4902 if (priv->hostcmd_wait != NULL) {
4903 complete(priv->hostcmd_wait);
4904 priv->hostcmd_wait = NULL;
4905 }
4906
4907 priv->hw_restart_owner = current;
4908 di = priv->device_info;
4909 mwl8k_fw_lock(hw);
4910
4911 if (priv->ap_fw)
4912 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4913 else
4914 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
4915
4916 if (rc)
4917 goto fail;
4918
4919 priv->hw_restart_owner = NULL;
4920 priv->hw_restart_in_progress = false;
4921
4922 /*
4923 * This unlock will wake up the queues and
4924 * also opens the command path for other
4925 * commands
4926 */
4927 mwl8k_fw_unlock(hw);
4928
4929 ieee80211_restart_hw(hw);
4930
4931 wiphy_err(hw->wiphy, "Firmware restarted successfully\n");
4932
4933 return;
4934fail:
4935 mwl8k_fw_unlock(hw);
4936
4937 wiphy_err(hw->wiphy, "Firmware restart failed\n");
a66098da
LB		 4938}
4939
ee03a932 4940static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 4941{
a66098da
LB		 4942 struct ieee80211_conf *conf = &hw->conf;
4943 struct mwl8k_priv *priv = hw->priv;
ee03a932 4944 int rc;
a66098da 4945
ee03a932
LB		 4946 rc = mwl8k_fw_lock(hw);
4947 if (rc)
4948 return rc;
a66098da 4949
fe21bb02
JG		 4950 if (conf->flags & IEEE80211_CONF_IDLE)
4951 rc = mwl8k_cmd_radio_disable(hw);
4952 else
4953 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 4954 if (rc)
4955 goto out;
a66098da 4956
0f4316b9
YAP		 4957 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
4958 rc = mwl8k_cmd_set_rf_channel(hw, conf);
4959 if (rc)
4960 goto out;
4961 }
ee03a932 4962
a66098da
LB		 4963 if (conf->power_level > 18)
4964 conf->power_level = 18;
a66098da 4965
08b06347 4966 if (priv->ap_fw) {
03217087
NS		 4967
4968 if (conf->flags & IEEE80211_CONF_CHANGE_POWER) {
4969 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
4970 if (rc)
4971 goto out;
4972 }
41fdf097 4973
da62b761 4974
08b06347 4975 } else {
41fdf097
NS		 4976 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
4977 if (rc)
4978 goto out;
08b06347
LB		 4979 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
4980 }
a66098da 4981
ee03a932
LB		 4982out:
4983 mwl8k_fw_unlock(hw);
a66098da 4984
ee03a932 4985 return rc;
a66098da
LB		 4986}
4987
b64fe619
LB		 4988static void
4989mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4990 struct ieee80211_bss_conf *info, u32 changed)
a66098da 4991{
a66098da 4992 struct mwl8k_priv *priv = hw->priv;
ba30c4a5 4993 u32 ap_legacy_rates = 0;
13935e2c 4994 u8 ap_mcs_rates[16];
3a980d0a
LB		 4995 int rc;
4996
c3cbbe8a 4997 if (mwl8k_fw_lock(hw))
3a980d0a 4998 return;
a66098da 4999
c3cbbe8a
LB		 5000 /*
5001 * No need to capture a beacon if we're no longer associated.
5002 */
5003 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
5004 priv->capture_beacon = false;
3a980d0a 5005
c3cbbe8a 5006 /*
13935e2c 5007 * Get the AP's legacy and MCS rates.
c3cbbe8a 5008 */
7dc6a7a7 5009 if (vif->bss_conf.assoc) {
c6e96010 5010 struct ieee80211_sta *ap;
c97470dd 5011
c6e96010 5012 rcu_read_lock();
c6e96010 5013
c3cbbe8a
LB		 5014 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
5015 if (ap == NULL) {
5016 rcu_read_unlock();
c6e96010 5017 goto out;
c3cbbe8a
LB		 5018 }
5019
675a0b04 5020 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ) {
8707d026
LB		 5021 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
5022 } else {
5023 ap_legacy_rates =
5024 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
5025 }
13935e2c 5026 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 5027
5028 rcu_read_unlock();
5029 }
c6e96010 5030
dcee7438
YAP		 5031 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc &&
5032 !priv->ap_fw) {
13935e2c 5033 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 5034 if (rc)
5035 goto out;
a66098da 5036
b71ed2c6 5037 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 5038 if (rc)
5039 goto out;
dcee7438
YAP		 5040 } else {
5041 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc &&
5042 priv->ap_fw) {
5043 int idx;
5044 int rate;
5045
5046 /* Use AP firmware specific rate command.
5047 */
5048 idx = ffs(vif->bss_conf.basic_rates);
5049 if (idx)
5050 idx--;
5051
675a0b04 5052 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ)
dcee7438
YAP		 5053 rate = mwl8k_rates_24[idx].hw_value;
5054 else
5055 rate = mwl8k_rates_50[idx].hw_value;
5056
5057 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
5058 }
c3cbbe8a 5059 }
a66098da 5060
c3cbbe8a 5061 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 5062 rc = mwl8k_set_radio_preamble(hw,
5063 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 5064 if (rc)
5065 goto out;
c3cbbe8a 5066 }
a66098da 5067
dcee7438 5068 if ((changed & BSS_CHANGED_ERP_SLOT) && !priv->ap_fw) {
7dc6a7a7 5069 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 5070 if (rc)
5071 goto out;
c3cbbe8a 5072 }
a66098da 5073
dcee7438 5074 if (vif->bss_conf.assoc && !priv->ap_fw &&
c97470dd
LB		 5075 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
5076 BSS_CHANGED_HT))) {
c3cbbe8a 5077 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 5078 if (rc)
5079 goto out;
c3cbbe8a 5080 }
a66098da 5081
c3cbbe8a
LB		 5082 if (vif->bss_conf.assoc &&
5083 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 5084 /*
5085 * Finalize the join. Tell rx handler to process
5086 * next beacon from our BSSID.
5087 */
0a11dfc3 5088 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 5089 priv->capture_beacon = true;
a66098da
LB		 5090 }
5091
3a980d0a
LB		 5092out:
5093 mwl8k_fw_unlock(hw);
a66098da
LB		 5094}
5095
b64fe619
LB		 5096static void
5097mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5098 struct ieee80211_bss_conf *info, u32 changed)
5099{
5100 int rc;
5101
5102 if (mwl8k_fw_lock(hw))
5103 return;
5104
5105 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5106 rc = mwl8k_set_radio_preamble(hw,
5107 vif->bss_conf.use_short_preamble);
5108 if (rc)
5109 goto out;
5110 }
5111
5112 if (changed & BSS_CHANGED_BASIC_RATES) {
5113 int idx;
5114 int rate;
5115
5116 /*
5117 * Use lowest supported basic rate for multicasts
5118 * and management frames (such as probe responses --
5119 * beacons will always go out at 1 Mb/s).
5120 */
5121 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 5122 if (idx)
5123 idx--;
5124
675a0b04 5125 if (hw->conf.chandef.chan->band == IEEE80211_BAND_2GHZ)
8707d026
LB		 5126 rate = mwl8k_rates_24[idx].hw_value;
5127 else
5128 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 5129
5130 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
5131 }
5132
5133 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
5134 struct sk_buff *skb;
5135
5136 skb = ieee80211_beacon_get(hw, vif);
5137 if (skb != NULL) {
aa21d0f6 5138 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 5139 kfree_skb(skb);
5140 }
5141 }
5142
5143 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 5144 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 5145
5146out:
5147 mwl8k_fw_unlock(hw);
5148}
5149
5150static void
5151mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5152 struct ieee80211_bss_conf *info, u32 changed)
5153{
41bf9119 5154 if (vif->type == NL80211_IFTYPE_STATION)
b64fe619 5155 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
41bf9119 5156 if (vif->type == NL80211_IFTYPE_AP)
b64fe619
LB		 5157 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
5158}
5159
e81cd2d6 5160static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 5161 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 5162{
5163 struct mwl8k_cmd_pkt *cmd;
5164
447ced07
LB		 5165 /*
5166 * Synthesize and return a command packet that programs the
5167 * hardware multicast address filter. At this point we don't
5168 * know whether FIF_ALLMULTI is being requested, but if it is,
5169 * we'll end up throwing this packet away and creating a new
5170 * one in mwl8k_configure_filter().
5171 */
22bedad3 5172 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 5173
5174 return (unsigned long)cmd;
5175}
5176
a43c49a8
LB		 5177static int
5178mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
5179 unsigned int changed_flags,
5180 unsigned int *total_flags)
5181{
5182 struct mwl8k_priv *priv = hw->priv;
5183
5184 /*
5185 * Hardware sniffer mode is mutually exclusive with STA
5186 * operation, so refuse to enable sniffer mode if a STA
5187 * interface is active.
5188 */
f5bb87cf 5189 if (!list_empty(&priv->vif_list)) {
a43c49a8 5190 if (net_ratelimit())
c96c31e4
JP		 5191 wiphy_info(hw->wiphy,
5192 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 5193 return 0;
5194 }
5195
5196 if (!priv->sniffer_enabled) {
55489b6e 5197 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 5198 return 0;
5199 priv->sniffer_enabled = true;
5200 }
5201
5202 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
5203 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
5204 FIF_OTHER_BSS;
5205
5206 return 1;
5207}
5208
f5bb87cf
LB		 5209static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
5210{
5211 if (!list_empty(&priv->vif_list))
5212 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
5213
5214 return NULL;
5215}
5216
e6935ea1
LB		 5217static void mwl8k_configure_filter(struct ieee80211_hw *hw,
5218 unsigned int changed_flags,
5219 unsigned int *total_flags,
5220 u64 multicast)
5221{
5222 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 5223 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
5224
c0adae2c
LB		 5225 /*
5226 * AP firmware doesn't allow fine-grained control over
5227 * the receive filter.
5228 */
5229 if (priv->ap_fw) {
5230 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
5231 kfree(cmd);
5232 return;
5233 }
5234
a43c49a8
LB		 5235 /*
5236 * Enable hardware sniffer mode if FIF_CONTROL or
5237 * FIF_OTHER_BSS is requested.
5238 */
5239 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
5240 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
5241 kfree(cmd);
5242 return;
5243 }
a66098da 5244
e6935ea1 5245 /* Clear unsupported feature flags */
447ced07 5246 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 5247
90852f7a
LB		 5248 if (mwl8k_fw_lock(hw)) {
5249 kfree(cmd);
e6935ea1 5250 return;
90852f7a 5251 }
a66098da 5252
a43c49a8 5253 if (priv->sniffer_enabled) {
55489b6e 5254 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 5255 priv->sniffer_enabled = false;
5256 }
5257
e6935ea1 5258 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 5259 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
5260 /*
5261 * Disable the BSS filter.
5262 */
e6935ea1 5263 mwl8k_cmd_set_pre_scan(hw);
77165d88 5264 } else {
f5bb87cf 5265 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 5266 const u8 *bssid;
a94cc97e 5267
77165d88
LB		 5268 /*
5269 * Enable the BSS filter.
5270 *
5271 * If there is an active STA interface, use that
5272 * interface's BSSID, otherwise use a dummy one
5273 * (where the OUI part needs to be nonzero for
5274 * the BSSID to be accepted by POST_SCAN).
5275 */
f5bb87cf
LB		 5276 mwl8k_vif = mwl8k_first_vif(priv);
5277 if (mwl8k_vif != NULL)
5278 bssid = mwl8k_vif->vif->bss_conf.bssid;
5279 else
5280 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 5281
e6935ea1 5282 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 5283 }
5284 }
5285
447ced07
LB		 5286 /*
5287 * If FIF_ALLMULTI is being requested, throw away the command
5288 * packet that ->prepare_multicast() built and replace it with
5289 * a command packet that enables reception of all multicast
5290 * packets.
5291 */
5292 if (*total_flags & FIF_ALLMULTI) {
5293 kfree(cmd);
22bedad3 5294 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 5295 }
5296
5297 if (cmd != NULL) {
5298 mwl8k_post_cmd(hw, cmd);
5299 kfree(cmd);
e6935ea1 5300 }
a66098da 5301
e6935ea1 5302 mwl8k_fw_unlock(hw);
a66098da
LB		 5303}
5304
a66098da
LB		 5305static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
5306{
c2c2b12a 5307 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 5308}
5309
4a6967b8
JB		 5310static int mwl8k_sta_remove(struct ieee80211_hw *hw,
5311 struct ieee80211_vif *vif,
5312 struct ieee80211_sta *sta)
3f5610ff
LB		 5313{
5314 struct mwl8k_priv *priv = hw->priv;
5315
4a6967b8
JB		 5316 if (priv->ap_fw)
5317 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
5318 else
5319 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 5320}
5321
4a6967b8
JB		 5322static int mwl8k_sta_add(struct ieee80211_hw *hw,
5323 struct ieee80211_vif *vif,
5324 struct ieee80211_sta *sta)
bbfd9128
LB		 5325{
5326 struct mwl8k_priv *priv = hw->priv;
4a6967b8 5327 int ret;
fcdc403c
NS		 5328 int i;
5329 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
5330 struct ieee80211_key_conf *key;
bbfd9128 5331
4a6967b8
JB		 5332 if (!priv->ap_fw) {
5333 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
5334 if (ret >= 0) {
5335 MWL8K_STA(sta)->peer_id = ret;
17033543
NS		 5336 if (sta->ht_cap.ht_supported)
5337 MWL8K_STA(sta)->is_ampdu_allowed = true;
fcdc403c 5338 ret = 0;
4a6967b8 5339 }
bbfd9128 5340
d9a07d49
NS		 5341 } else {
5342 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128 5343 }
4a6967b8 5344
d9a07d49
NS		 5345 for (i = 0; i < NUM_WEP_KEYS; i++) {
5346 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
5347 if (mwl8k_vif->wep_key_conf[i].enabled)
5348 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
5349 }
fcdc403c 5350 return ret;
bbfd9128
LB		 5351}
5352
8a3a3c85
EP		 5353static int mwl8k_conf_tx(struct ieee80211_hw *hw,
5354 struct ieee80211_vif *vif, u16 queue,
a66098da
LB		 5355 const struct ieee80211_tx_queue_params *params)
5356{
3e4f542c 5357 struct mwl8k_priv *priv = hw->priv;
a66098da 5358 int rc;
a66098da 5359
3e4f542c
LB		 5360 rc = mwl8k_fw_lock(hw);
5361 if (!rc) {
e600707b 5362 BUG_ON(queue > MWL8K_TX_WMM_QUEUES - 1);
0863ade8
BC		 5363 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
5364
3e4f542c 5365 if (!priv->wmm_enabled)
55489b6e 5366 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 5367
85c9205c 5368 if (!rc) {
e600707b 5369 int q = MWL8K_TX_WMM_QUEUES - 1 - queue;
85c9205c 5370 rc = mwl8k_cmd_set_edca_params(hw, q,
55489b6e
LB		 5371 params->cw_min,
5372 params->cw_max,
5373 params->aifs,
5374 params->txop);
85c9205c 5375 }
3e4f542c
LB		 5376
5377 mwl8k_fw_unlock(hw);
a66098da 5378 }
3e4f542c 5379
a66098da
LB		 5380 return rc;
5381}
5382
a66098da
LB		 5383static int mwl8k_get_stats(struct ieee80211_hw *hw,
5384 struct ieee80211_low_level_stats *stats)
5385{
55489b6e 5386 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 5387}
5388
0d462bbb
JL		 5389static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
5390 struct survey_info *survey)
5391{
5392 struct mwl8k_priv *priv = hw->priv;
5393 struct ieee80211_conf *conf = &hw->conf;
031eb464
YAP		 5394 struct ieee80211_supported_band *sband;
5395
5396 if (priv->ap_fw) {
5397 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
5398
5399 if (sband && idx >= sband->n_channels) {
5400 idx -= sband->n_channels;
5401 sband = NULL;
5402 }
5403
5404 if (!sband)
5405 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
5406
5407 if (!sband || idx >= sband->n_channels)
5408 return -ENOENT;
5409
5410 memcpy(survey, &priv->survey[idx], sizeof(*survey));
5411 survey->channel = &sband->channels[idx];
5412
5413 return 0;
5414 }
0d462bbb
JL		 5415
5416 if (idx != 0)
5417 return -ENOENT;
5418
675a0b04 5419 survey->channel = conf->chandef.chan;
0d462bbb
JL		 5420 survey->filled = SURVEY_INFO_NOISE_DBM;
5421 survey->noise = priv->noise;
5422
5423 return 0;
5424}
5425
65f3ddcd
NS		 5426#define MAX_AMPDU_ATTEMPTS 5
5427
a2292d83
LB		 5428static int
5429mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5430 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 5431 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5432 u8 buf_size)
a2292d83 5433{
65f3ddcd
NS		 5434
5435 int i, rc = 0;
5436 struct mwl8k_priv *priv = hw->priv;
5437 struct mwl8k_ampdu_stream *stream;
07f6dda1 5438 u8 *addr = sta->addr, idx;
fd712f5f 5439 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
65f3ddcd
NS		 5440
5441 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
5442 return -ENOTSUPP;
5443
5444 spin_lock(&priv->stream_lock);
5445 stream = mwl8k_lookup_stream(hw, addr, tid);
5446
a2292d83
LB		 5447 switch (action) {
5448 case IEEE80211_AMPDU_RX_START:
5449 case IEEE80211_AMPDU_RX_STOP:
65f3ddcd
NS		 5450 break;
5451 case IEEE80211_AMPDU_TX_START:
5452 /* By the time we get here the hw queues may contain outgoing
5453 * packets for this RA/TID that are not part of this BA
5454 * session. The hw will assign sequence numbers to these
5455 * packets as they go out. So if we query the hw for its next
5456 * sequence number and use that for the SSN here, it may end up
5457 * being wrong, which will lead to sequence number mismatch at
5458 * the recipient. To avoid this, we reset the sequence number
5459 * to O for the first MPDU in this BA stream.
5460 */
5461 *ssn = 0;
5462 if (stream == NULL) {
5463 /* This means that somebody outside this driver called
5464 * ieee80211_start_tx_ba_session. This is unexpected
5465 * because we do our own rate control. Just warn and
5466 * move on.
5467 */
5468 wiphy_warn(hw->wiphy, "Unexpected call to %s. "
5469 "Proceeding anyway.\n", __func__);
5470 stream = mwl8k_add_stream(hw, sta, tid);
5471 }
5472 if (stream == NULL) {
5473 wiphy_debug(hw->wiphy, "no free AMPDU streams\n");
5474 rc = -EBUSY;
5475 break;
5476 }
5477 stream->state = AMPDU_STREAM_IN_PROGRESS;
5478
5479 /* Release the lock before we do the time consuming stuff */
5480 spin_unlock(&priv->stream_lock);
5481 for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) {
fd712f5f
YAP		 5482
5483 /* Check if link is still valid */
5484 if (!sta_info->is_ampdu_allowed) {
5485 spin_lock(&priv->stream_lock);
5486 mwl8k_remove_stream(hw, stream);
5487 spin_unlock(&priv->stream_lock);
5488 return -EBUSY;
5489 }
5490
f95275c4 5491 rc = mwl8k_check_ba(hw, stream, vif);
65f3ddcd 5492
6b6accc3
YAP		 5493 /* If HW restart is in progress mwl8k_post_cmd will
5494 * return -EBUSY. Avoid retrying mwl8k_check_ba in
5495 * such cases
5496 */
5497 if (!rc || rc == -EBUSY)
65f3ddcd
NS		 5498 break;
5499 /*
5500 * HW queues take time to be flushed, give them
5501 * sufficient time
5502 */
5503
5504 msleep(1000);
5505 }
5506 spin_lock(&priv->stream_lock);
5507 if (rc) {
5508 wiphy_err(hw->wiphy, "Stream for tid %d busy after %d"
5509 " attempts\n", tid, MAX_AMPDU_ATTEMPTS);
5510 mwl8k_remove_stream(hw, stream);
5511 rc = -EBUSY;
5512 break;
5513 }
5514 ieee80211_start_tx_ba_cb_irqsafe(vif, addr, tid);
5515 break;
18b559d5
JB		 5516 case IEEE80211_AMPDU_TX_STOP_CONT:
5517 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5518 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
eca107ff
YAP		 5519 if (stream) {
5520 if (stream->state == AMPDU_STREAM_ACTIVE) {
07f6dda1 5521 idx = stream->idx;
eca107ff 5522 spin_unlock(&priv->stream_lock);
07f6dda1 5523 mwl8k_destroy_ba(hw, idx);
eca107ff
YAP		 5524 spin_lock(&priv->stream_lock);
5525 }
5526 mwl8k_remove_stream(hw, stream);
65f3ddcd 5527 }
65f3ddcd
NS		 5528 ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
5529 break;
5530 case IEEE80211_AMPDU_TX_OPERATIONAL:
5531 BUG_ON(stream == NULL);
5532 BUG_ON(stream->state != AMPDU_STREAM_IN_PROGRESS);
5533 spin_unlock(&priv->stream_lock);
f95275c4 5534 rc = mwl8k_create_ba(hw, stream, buf_size, vif);
65f3ddcd
NS		 5535 spin_lock(&priv->stream_lock);
5536 if (!rc)
5537 stream->state = AMPDU_STREAM_ACTIVE;
5538 else {
07f6dda1 5539 idx = stream->idx;
65f3ddcd 5540 spin_unlock(&priv->stream_lock);
07f6dda1 5541 mwl8k_destroy_ba(hw, idx);
65f3ddcd
NS		 5542 spin_lock(&priv->stream_lock);
5543 wiphy_debug(hw->wiphy,
5544 "Failed adding stream for sta %pM tid %d\n",
5545 addr, tid);
5546 mwl8k_remove_stream(hw, stream);
5547 }
5548 break;
5549
a2292d83 5550 default:
65f3ddcd 5551 rc = -ENOTSUPP;
a2292d83 5552 }
65f3ddcd
NS		 5553
5554 spin_unlock(&priv->stream_lock);
5555 return rc;
a2292d83
LB		 5556}
5557
4c924f42
YAP		 5558static void mwl8k_sw_scan_start(struct ieee80211_hw *hw)
5559{
5560 struct mwl8k_priv *priv = hw->priv;
5561 u8 tmp;
5562
5563 if (!priv->ap_fw)
5564 return;
5565
5566 /* clear all stats */
031eb464 5567 priv->channel_time = 0;
4c924f42
YAP		 5568 ioread32(priv->regs + BBU_RXRDY_CNT_REG);
5569 ioread32(priv->regs + NOK_CCA_CNT_REG);
5570 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &tmp);
5571
5572 priv->sw_scan_start = true;
5573}
5574
5575static void mwl8k_sw_scan_complete(struct ieee80211_hw *hw)
5576{
5577 struct mwl8k_priv *priv = hw->priv;
5578 u8 tmp;
5579
5580 if (!priv->ap_fw)
5581 return;
5582
5583 priv->sw_scan_start = false;
5584
5585 /* clear all stats */
031eb464 5586 priv->channel_time = 0;
4c924f42
YAP		 5587 ioread32(priv->regs + BBU_RXRDY_CNT_REG);
5588 ioread32(priv->regs + NOK_CCA_CNT_REG);
5589 mwl8k_cmd_bbp_reg_access(priv->hw, 0, BBU_AVG_NOISE_VAL, &tmp);
5590}
5591
a66098da
LB		 5592static const struct ieee80211_ops mwl8k_ops = {
5593 .tx = mwl8k_tx,
5594 .start = mwl8k_start,
5595 .stop = mwl8k_stop,
5596 .add_interface = mwl8k_add_interface,
5597 .remove_interface = mwl8k_remove_interface,
5598 .config = mwl8k_config,
a66098da 5599 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 5600 .prepare_multicast = mwl8k_prepare_multicast,
a66098da 5601 .configure_filter = mwl8k_configure_filter,
fcdc403c 5602 .set_key = mwl8k_set_key,
a66098da 5603 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 5604 .sta_add = mwl8k_sta_add,
5605 .sta_remove = mwl8k_sta_remove,
a66098da 5606 .conf_tx = mwl8k_conf_tx,
a66098da 5607 .get_stats = mwl8k_get_stats,
0d462bbb 5608 .get_survey = mwl8k_get_survey,
a2292d83 5609 .ampdu_action = mwl8k_ampdu_action,
4c924f42
YAP		 5610 .sw_scan_start = mwl8k_sw_scan_start,
5611 .sw_scan_complete = mwl8k_sw_scan_complete,
a66098da
LB		 5612};
5613
a66098da
LB		 5614static void mwl8k_finalize_join_worker(struct work_struct *work)
5615{
5616 struct mwl8k_priv *priv =
5617 container_of(work, struct mwl8k_priv, finalize_join_worker);
5618 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 5619 struct ieee80211_mgmt *mgmt = (void *)skb->data;
5620 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
5621 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
5622 mgmt->u.beacon.variable, len);
5623 int dtim_period = 1;
5624
5625 if (tim && tim[1] >= 2)
5626 dtim_period = tim[3];
a66098da 5627
56007a02 5628 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 5629
f5bb87cf 5630 dev_kfree_skb(skb);
a66098da
LB		 5631 priv->beacon_skb = NULL;
5632}
5633
bcb628d5 5634enum {
9e1b17ea
LB		 5635 MWL8363 = 0,
5636 MWL8687,
bcb628d5 5637 MWL8366,
d926dc7d 5638 MWL8764,
6f6d1e9a
LB		 5639};
5640
c2f2e202 5641#define MWL8K_8366_AP_FW_API 3
952a0e96
BC		 5642#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
5643#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
5644
d926dc7d
NS		 5645#define MWL8K_8764_AP_FW_API 1
5646#define _MWL8K_8764_AP_FW(api) "mwl8k/fmimage_8764_ap-" #api ".fw"
5647#define MWL8K_8764_AP_FW(api) _MWL8K_8764_AP_FW(api)
5648
8dee5eef 5649static struct mwl8k_device_info mwl8k_info_tbl[] = {
9e1b17ea
LB		 5650 [MWL8363] = {
5651 .part_name = "88w8363",
5652 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 5653 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 5654 },
49eb691c 5655 [MWL8687] = {
bcb628d5
JL		 5656 .part_name = "88w8687",
5657 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 5658 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 5659 },
49eb691c 5660 [MWL8366] = {
bcb628d5
JL		 5661 .part_name = "88w8366",
5662 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 5663 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC		 5664 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
5665 .fw_api_ap = MWL8K_8366_AP_FW_API,
d926dc7d
NS		 5666 .ap_rxd_ops = &rxd_ap_ops,
5667 },
5668 [MWL8764] = {
5669 .part_name = "88w8764",
5670 .fw_image_ap = MWL8K_8764_AP_FW(MWL8K_8764_AP_FW_API),
5671 .fw_api_ap = MWL8K_8764_AP_FW_API,
5672 .ap_rxd_ops = &rxd_ap_ops,
bcb628d5 5673 },
45a390dd
LB		 5674};
5675
c92d4ede
LB		 5676MODULE_FIRMWARE("mwl8k/helper_8363.fw");
5677MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
5678MODULE_FIRMWARE("mwl8k/helper_8687.fw");
5679MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
5680MODULE_FIRMWARE("mwl8k/helper_8366.fw");
5681MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 5682MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 5683
45a390dd 5684static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 5685 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 5686 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5687 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 5688 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5689 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5690 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
fc5bc165
JG		 5691 { PCI_VDEVICE(MARVELL, 0x2a41), .driver_data = MWL8366, },
5692 { PCI_VDEVICE(MARVELL, 0x2a42), .driver_data = MWL8366, },
ca66527c 5693 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
d926dc7d 5694 { PCI_VDEVICE(MARVELL, 0x2b36), .driver_data = MWL8764, },
bcb628d5 5695 { },
45a390dd
LB		 5696};
5697MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
5698
99020471
BC		 5699static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
5700{
5701 int rc;
5702 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
5703 "Trying alternative firmware %s\n", pci_name(priv->pdev),
5704 priv->fw_pref, priv->fw_alt);
5705 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
5706 if (rc) {
5707 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5708 pci_name(priv->pdev), priv->fw_alt);
5709 return rc;
5710 }
5711 return 0;
5712}
5713
5714static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
5715static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
5716{
5717 struct mwl8k_priv *priv = context;
5718 struct mwl8k_device_info *di = priv->device_info;
5719 int rc;
5720
5721 switch (priv->fw_state) {
5722 case FW_STATE_INIT:
5723 if (!fw) {
5724 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
5725 pci_name(priv->pdev), di->helper_image);
5726 goto fail;
5727 }
5728 priv->fw_helper = fw;
5729 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
5730 true);
5731 if (rc && priv->fw_alt) {
5732 rc = mwl8k_request_alt_fw(priv);
5733 if (rc)
5734 goto fail;
5735 priv->fw_state = FW_STATE_LOADING_ALT;
5736 } else if (rc)
5737 goto fail;
5738 else
5739 priv->fw_state = FW_STATE_LOADING_PREF;
5740 break;
5741
5742 case FW_STATE_LOADING_PREF:
5743 if (!fw) {
5744 if (priv->fw_alt) {
5745 rc = mwl8k_request_alt_fw(priv);
5746 if (rc)
5747 goto fail;
5748 priv->fw_state = FW_STATE_LOADING_ALT;
5749 } else
5750 goto fail;
5751 } else {
5752 priv->fw_ucode = fw;
5753 rc = mwl8k_firmware_load_success(priv);
5754 if (rc)
5755 goto fail;
5756 else
5757 complete(&priv->firmware_loading_complete);
5758 }
5759 break;
5760
5761 case FW_STATE_LOADING_ALT:
5762 if (!fw) {
5763 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5764 pci_name(priv->pdev), di->helper_image);
5765 goto fail;
5766 }
5767 priv->fw_ucode = fw;
5768 rc = mwl8k_firmware_load_success(priv);
5769 if (rc)
5770 goto fail;
5771 else
5772 complete(&priv->firmware_loading_complete);
5773 break;
5774
5775 default:
5776 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
5777 MWL8K_NAME, priv->fw_state);
5778 BUG_ON(1);
5779 }
5780
5781 return;
5782
5783fail:
5784 priv->fw_state = FW_STATE_ERROR;
5785 complete(&priv->firmware_loading_complete);
5786 device_release_driver(&priv->pdev->dev);
5787 mwl8k_release_firmware(priv);
5788}
5789
6b6accc3 5790#define MAX_RESTART_ATTEMPTS 1
99020471
BC		 5791static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
5792 bool nowait)
a66098da 5793{
3cc7772c 5794 struct mwl8k_priv *priv = hw->priv;
a66098da 5795 int rc;
6b6accc3 5796 int count = MAX_RESTART_ATTEMPTS;
be695fc4 5797
6b6accc3 5798retry:
be695fc4
LB		 5799 /* Reset firmware and hardware */
5800 mwl8k_hw_reset(priv);
5801
5802 /* Ask userland hotplug daemon for the device firmware */
99020471 5803 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 5804 if (rc) {
5db55844 5805 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 5806 return rc;
be695fc4
LB		 5807 }
5808
99020471
BC		 5809 if (nowait)
5810 return rc;
5811
be695fc4
LB		 5812 /* Load firmware into hardware */
5813 rc = mwl8k_load_firmware(hw);
3cc7772c 5814 if (rc)
5db55844 5815 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 5816
5817 /* Reclaim memory once firmware is successfully loaded */
5818 mwl8k_release_firmware(priv);
5819
6b6accc3
YAP		 5820 if (rc && count) {
5821 /* FW did not start successfully;
5822 * lets try one more time
5823 */
5824 count--;
5825 wiphy_err(hw->wiphy, "Trying to reload the firmware again\n");
5826 msleep(20);
5827 goto retry;
5828 }
5829
3cc7772c
BC		 5830 return rc;
5831}
5832
73b46320
BC		 5833static int mwl8k_init_txqs(struct ieee80211_hw *hw)
5834{
5835 struct mwl8k_priv *priv = hw->priv;
5836 int rc = 0;
5837 int i;
5838
e600707b 5839 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
73b46320
BC		 5840 rc = mwl8k_txq_init(hw, i);
5841 if (rc)
5842 break;
5843 if (priv->ap_fw)
5844 iowrite32(priv->txq[i].txd_dma,
5845 priv->sram + priv->txq_offset[i]);
5846 }
5847 return rc;
5848}
5849
3cc7772c
BC		 5850/* initialize hw after successfully loading a firmware image */
5851static int mwl8k_probe_hw(struct ieee80211_hw *hw)
5852{
5853 struct mwl8k_priv *priv = hw->priv;
5854 int rc = 0;
5855 int i;
be695fc4 5856
91942230 5857 if (priv->ap_fw) {
89a91f4f 5858 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 5859 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 5860 wiphy_err(hw->wiphy,
5861 "Driver does not have AP firmware image support for this hardware\n");
a2ca8ecb 5862 rc = -ENOENT;
91942230
LB		 5863 goto err_stop_firmware;
5864 }
5865 } else {
89a91f4f 5866 priv->rxd_ops = &rxd_sta_ops;
91942230 5867 }
be695fc4
LB		 5868
5869 priv->sniffer_enabled = false;
5870 priv->wmm_enabled = false;
5871 priv->pending_tx_pkts = 0;
c27a54d3 5872 atomic_set(&priv->watchdog_event_pending, 0);
be695fc4 5873
a66098da
LB		 5874 rc = mwl8k_rxq_init(hw, 0);
5875 if (rc)
3cc7772c 5876 goto err_stop_firmware;
a66098da
LB		 5877 rxq_refill(hw, 0, INT_MAX);
5878
73b46320
BC		 5879 /* For the sta firmware, we need to know the dma addresses of tx queues
5880 * before sending MWL8K_CMD_GET_HW_SPEC. So we must initialize them
5881 * prior to issuing this command. But for the AP case, we learn the
5882 * total number of queues from the result CMD_GET_HW_SPEC, so for this
5883 * case we must initialize the tx queues after.
5884 */
8a7a578c 5885 priv->num_ampdu_queues = 0;
73b46320
BC		 5886 if (!priv->ap_fw) {
5887 rc = mwl8k_init_txqs(hw);
a66098da
LB		 5888 if (rc)
5889 goto err_free_queues;
5890 }
5891
5892 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 5893 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3aefc37e
NS		 5894 iowrite32(MWL8K_A2H_INT_TX_DONE|MWL8K_A2H_INT_RX_READY|
5895 MWL8K_A2H_INT_BA_WATCHDOG,
1e9f9de3 5896 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
12488e01
NS		 5897 iowrite32(MWL8K_A2H_INT_OPC_DONE,
5898 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 5899
a0607fd3 5900 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 5901 IRQF_SHARED, MWL8K_NAME, hw);
5902 if (rc) {
5db55844 5903 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 5904 goto err_free_queues;
5905 }
5906
6b6accc3
YAP		 5907 /*
5908 * When hw restart is requested,
5909 * mac80211 will take care of clearing
5910 * the ampdu streams, so do not clear
5911 * the ampdu state here
5912 */
5913 if (!priv->hw_restart_in_progress)
5914 memset(priv->ampdu, 0, sizeof(priv->ampdu));
ac109fd0 5915
a66098da
LB		 5916 /*
5917 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 5918 * commands use interrupts and avoid polling. Disable
a66098da
LB		 5919 * interrupts when done.
5920 */
c23b5a69 5921 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5922
5923 /* Get config data, mac addrs etc */
42fba21d
LB		 5924 if (priv->ap_fw) {
5925 rc = mwl8k_cmd_get_hw_spec_ap(hw);
73b46320
BC		 5926 if (!rc)
5927 rc = mwl8k_init_txqs(hw);
42fba21d
LB		 5928 if (!rc)
5929 rc = mwl8k_cmd_set_hw_spec(hw);
5930 } else {
5931 rc = mwl8k_cmd_get_hw_spec_sta(hw);
5932 }
a66098da 5933 if (rc) {
5db55844 5934 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 5935 goto err_free_irq;
a66098da
LB		 5936 }
5937
5938 /* Turn radio off */
55489b6e 5939 rc = mwl8k_cmd_radio_disable(hw);
a66098da 5940 if (rc) {
5db55844 5941 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 5942 goto err_free_irq;
a66098da
LB		 5943 }
5944
32060e1b 5945 /* Clear MAC address */
aa21d0f6 5946 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 5947 if (rc) {
5db55844 5948 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 5949 goto err_free_irq;
32060e1b
LB		 5950 }
5951
a246ac38
YAP		 5952 /* Configure Antennas */
5953 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3);
5954 if (rc)
5955 wiphy_warn(hw->wiphy, "failed to set # of RX antennas");
5956 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
5957 if (rc)
5958 wiphy_warn(hw->wiphy, "failed to set # of TX antennas");
5959
5960
a66098da 5961 /* Disable interrupts */
a66098da 5962 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5963 free_irq(priv->pdev->irq, hw);
5964
c96c31e4
JP		 5965 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
5966 priv->device_info->part_name,
5967 priv->hw_rev, hw->wiphy->perm_addr,
5968 priv->ap_fw ? "AP" : "STA",
5969 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
5970 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 5971
5972 return 0;
5973
a66098da 5974err_free_irq:
a66098da 5975 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5976 free_irq(priv->pdev->irq, hw);
5977
5978err_free_queues:
e600707b 5979 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 5980 mwl8k_txq_deinit(hw, i);
5981 mwl8k_rxq_deinit(hw, 0);
5982
3cc7772c
BC		 5983err_stop_firmware:
5984 mwl8k_hw_reset(priv);
5985
5986 return rc;
5987}
5988
5989/*
5990 * invoke mwl8k_reload_firmware to change the firmware image after the device
5991 * has already been registered
5992 */
5993static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
5994{
5995 int i, rc = 0;
5996 struct mwl8k_priv *priv = hw->priv;
6b6accc3 5997 struct mwl8k_vif *vif, *tmp_vif;
3cc7772c
BC		 5998
5999 mwl8k_stop(hw);
6000 mwl8k_rxq_deinit(hw, 0);
6001
6b6accc3
YAP		 6002 /*
6003 * All the existing interfaces are re-added by the ieee80211_reconfig;
6004 * which means driver should remove existing interfaces before calling
6005 * ieee80211_restart_hw
6006 */
6007 if (priv->hw_restart_in_progress)
6008 list_for_each_entry_safe(vif, tmp_vif, &priv->vif_list, list)
6009 mwl8k_remove_vif(priv, vif);
6010
e600707b 6011 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 6012 mwl8k_txq_deinit(hw, i);
6013
99020471 6014 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC		 6015 if (rc)
6016 goto fail;
6017
6018 rc = mwl8k_probe_hw(hw);
6019 if (rc)
6020 goto fail;
6021
6b6accc3
YAP		 6022 if (priv->hw_restart_in_progress)
6023 return rc;
6024
3cc7772c
BC		 6025 rc = mwl8k_start(hw);
6026 if (rc)
6027 goto fail;
6028
6029 rc = mwl8k_config(hw, ~0);
6030 if (rc)
6031 goto fail;
6032
e600707b 6033 for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) {
8a3a3c85 6034 rc = mwl8k_conf_tx(hw, NULL, i, &priv->wmm_params[i]);
3cc7772c
BC		 6035 if (rc)
6036 goto fail;
6037 }
6038
6039 return rc;
6040
6041fail:
6042 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
6043 return rc;
6044}
6045
5d377fca
YAP		 6046static const struct ieee80211_iface_limit ap_if_limits[] = {
6047 { .max = 8, .types = BIT(NL80211_IFTYPE_AP) },
2acdaa7a 6048 { .max = 1, .types = BIT(NL80211_IFTYPE_STATION) },
5d377fca
YAP		 6049};
6050
6051static const struct ieee80211_iface_combination ap_if_comb = {
6052 .limits = ap_if_limits,
6053 .n_limits = ARRAY_SIZE(ap_if_limits),
6054 .max_interfaces = 8,
6055 .num_different_channels = 1,
6056};
6057
6058
3cc7772c
BC		 6059static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
6060{
6061 struct ieee80211_hw *hw = priv->hw;
6062 int i, rc;
6063
99020471
BC		 6064 rc = mwl8k_load_firmware(hw);
6065 mwl8k_release_firmware(priv);
6066 if (rc) {
6067 wiphy_err(hw->wiphy, "Cannot start firmware\n");
6068 return rc;
6069 }
6070
3cc7772c
BC		 6071 /*
6072 * Extra headroom is the size of the required DMA header
6073 * minus the size of the smallest 802.11 frame (CTS frame).
6074 */
6075 hw->extra_tx_headroom =
6076 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
6077
ff776cec
YAP		 6078 hw->extra_tx_headroom -= priv->ap_fw ? REDUCED_TX_HEADROOM : 0;
6079
e600707b 6080 hw->queues = MWL8K_TX_WMM_QUEUES;
3cc7772c
BC		 6081
6082 /* Set rssi values to dBm */
0bf22c37 6083 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL;
2a36a0ec
YAP		 6084
6085 /*
6086 * Ask mac80211 to not to trigger PS mode
6087 * based on PM bit of incoming frames.
6088 */
6089 if (priv->ap_fw)
6090 hw->flags |= IEEE80211_HW_AP_LINK_PS;
6091
3cc7772c
BC		 6092 hw->vif_data_size = sizeof(struct mwl8k_vif);
6093 hw->sta_data_size = sizeof(struct mwl8k_sta);
6094
6095 priv->macids_used = 0;
6096 INIT_LIST_HEAD(&priv->vif_list);
6097
6098 /* Set default radio state and preamble */
3db1cd5c
RR		 6099 priv->radio_on = false;
6100 priv->radio_short_preamble = false;
3cc7772c
BC		 6101
6102 /* Finalize join worker */
6103 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3aefc37e
NS		 6104 /* Handle watchdog ba events */
6105 INIT_WORK(&priv->watchdog_ba_handle, mwl8k_watchdog_ba_events);
6b6accc3
YAP		 6106 /* To reload the firmware if it crashes */
6107 INIT_WORK(&priv->fw_reload, mwl8k_hw_restart_work);
3cc7772c
BC		 6108
6109 /* TX reclaim and RX tasklets. */
6110 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
6111 tasklet_disable(&priv->poll_tx_task);
6112 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
6113 tasklet_disable(&priv->poll_rx_task);
6114
6115 /* Power management cookie */
6116 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
6117 if (priv->cookie == NULL)
6118 return -ENOMEM;
6119
6120 mutex_init(&priv->fw_mutex);
6121 priv->fw_mutex_owner = NULL;
6122 priv->fw_mutex_depth = 0;
6123 priv->hostcmd_wait = NULL;
6124
6125 spin_lock_init(&priv->tx_lock);
6126
ac109fd0
BC		 6127 spin_lock_init(&priv->stream_lock);
6128
3cc7772c
BC		 6129 priv->tx_wait = NULL;
6130
6131 rc = mwl8k_probe_hw(hw);
6132 if (rc)
6133 goto err_free_cookie;
6134
6135 hw->wiphy->interface_modes = 0;
5d377fca
YAP		 6136
6137 if (priv->ap_macids_supported || priv->device_info->fw_image_ap) {
3cc7772c 6138 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
2acdaa7a 6139 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5d377fca
YAP		 6140 hw->wiphy->iface_combinations = &ap_if_comb;
6141 hw->wiphy->n_iface_combinations = 1;
6142 }
6143
3cc7772c
BC		 6144 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
6145 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
6146
6147 rc = ieee80211_register_hw(hw);
6148 if (rc) {
6149 wiphy_err(hw->wiphy, "Cannot register device\n");
6150 goto err_unprobe_hw;
6151 }
6152
6153 return 0;
6154
6155err_unprobe_hw:
e600707b 6156 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 6157 mwl8k_txq_deinit(hw, i);
6158 mwl8k_rxq_deinit(hw, 0);
6159
be695fc4 6160err_free_cookie:
a66098da
LB		 6161 if (priv->cookie != NULL)
6162 pci_free_consistent(priv->pdev, 4,
6163 priv->cookie, priv->cookie_dma);
6164
3cc7772c
BC		 6165 return rc;
6166}
8dee5eef 6167static int mwl8k_probe(struct pci_dev *pdev,
3cc7772c
BC		 6168 const struct pci_device_id *id)
6169{
6170 static int printed_version;
6171 struct ieee80211_hw *hw;
6172 struct mwl8k_priv *priv;
0863ade8 6173 struct mwl8k_device_info *di;
3cc7772c
BC		 6174 int rc;
6175
6176 if (!printed_version) {
6177 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
6178 printed_version = 1;
6179 }
6180
6181
6182 rc = pci_enable_device(pdev);
6183 if (rc) {
6184 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
6185 MWL8K_NAME);
6186 return rc;
6187 }
6188
6189 rc = pci_request_regions(pdev, MWL8K_NAME);
6190 if (rc) {
6191 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
6192 MWL8K_NAME);
6193 goto err_disable_device;
6194 }
6195
6196 pci_set_master(pdev);
6197
6198
6199 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
6200 if (hw == NULL) {
6201 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
6202 rc = -ENOMEM;
6203 goto err_free_reg;
6204 }
6205
6206 SET_IEEE80211_DEV(hw, &pdev->dev);
6207 pci_set_drvdata(pdev, hw);
6208
6209 priv = hw->priv;
6210 priv->hw = hw;
6211 priv->pdev = pdev;
6212 priv->device_info = &mwl8k_info_tbl[id->driver_data];
6213
98929824
NS		 6214 if (id->driver_data == MWL8764)
6215 priv->is_8764 = true;
3cc7772c
BC		 6216
6217 priv->sram = pci_iomap(pdev, 0, 0x10000);
6218 if (priv->sram == NULL) {
6219 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
a2ca8ecb 6220 rc = -EIO;
3cc7772c
BC		 6221 goto err_iounmap;
6222 }
6223
6224 /*
6225 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
6226 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
6227 */
6228 priv->regs = pci_iomap(pdev, 1, 0x10000);
6229 if (priv->regs == NULL) {
6230 priv->regs = pci_iomap(pdev, 2, 0x10000);
6231 if (priv->regs == NULL) {
6232 wiphy_err(hw->wiphy, "Cannot map device registers\n");
a2ca8ecb 6233 rc = -EIO;
3cc7772c
BC		 6234 goto err_iounmap;
6235 }
6236 }
6237
0863ade8 6238 /*
99020471
BC		 6239 * Choose the initial fw image depending on user input. If a second
6240 * image is available, make it the alternative image that will be
6241 * loaded if the first one fails.
0863ade8 6242 */
99020471 6243 init_completion(&priv->firmware_loading_complete);
0863ade8 6244 di = priv->device_info;
99020471
BC		 6245 if (ap_mode_default && di->fw_image_ap) {
6246 priv->fw_pref = di->fw_image_ap;
6247 priv->fw_alt = di->fw_image_sta;
6248 } else if (!ap_mode_default && di->fw_image_sta) {
6249 priv->fw_pref = di->fw_image_sta;
6250 priv->fw_alt = di->fw_image_ap;
6251 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 6252 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 6253 priv->fw_pref = di->fw_image_sta;
0863ade8
BC		 6254 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
6255 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC		 6256 priv->fw_pref = di->fw_image_ap;
6257 }
6258 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC		 6259 if (rc)
6260 goto err_stop_firmware;
6b6accc3
YAP		 6261
6262 priv->hw_restart_in_progress = false;
6263
e882efc9
YAP		 6264 priv->running_bsses = 0;
6265
99020471 6266 return rc;
3cc7772c 6267
be695fc4
LB		 6268err_stop_firmware:
6269 mwl8k_hw_reset(priv);
be695fc4
LB		 6270
6271err_iounmap:
a66098da
LB		 6272 if (priv->regs != NULL)
6273 pci_iounmap(pdev, priv->regs);
6274
5b9482dd
LB		 6275 if (priv->sram != NULL)
6276 pci_iounmap(pdev, priv->sram);
6277
a66098da
LB		 6278 ieee80211_free_hw(hw);
6279
6280err_free_reg:
6281 pci_release_regions(pdev);
3db95e50
LB		 6282
6283err_disable_device:
a66098da
LB		 6284 pci_disable_device(pdev);
6285
6286 return rc;
6287}
6288
8dee5eef 6289static void mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 6290{
6291 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
6292 struct mwl8k_priv *priv;
6293 int i;
6294
6295 if (hw == NULL)
6296 return;
6297 priv = hw->priv;
6298
99020471
BC		 6299 wait_for_completion(&priv->firmware_loading_complete);
6300
6301 if (priv->fw_state == FW_STATE_ERROR) {
6302 mwl8k_hw_reset(priv);
6303 goto unmap;
6304 }
6305
a66098da
LB		 6306 ieee80211_stop_queues(hw);
6307
60aa569f
LB		 6308 ieee80211_unregister_hw(hw);
6309
67e2eb27 6310 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 6311 tasklet_kill(&priv->poll_tx_task);
67e2eb27 6312 tasklet_kill(&priv->poll_rx_task);
a66098da 6313
a66098da
LB		 6314 /* Stop hardware */
6315 mwl8k_hw_reset(priv);
6316
6317 /* Return all skbs to mac80211 */
e600707b 6318 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 6319 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 6320
e600707b 6321 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 6322 mwl8k_txq_deinit(hw, i);
6323
6324 mwl8k_rxq_deinit(hw, 0);
6325
c2c357ce 6326 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 6327
99020471 6328unmap:
a66098da 6329 pci_iounmap(pdev, priv->regs);
5b9482dd 6330 pci_iounmap(pdev, priv->sram);
a66098da
LB		 6331 ieee80211_free_hw(hw);
6332 pci_release_regions(pdev);
6333 pci_disable_device(pdev);
6334}
6335
6336static struct pci_driver mwl8k_driver = {
6337 .name = MWL8K_NAME,
45a390dd 6338 .id_table = mwl8k_pci_id_table,
a66098da 6339 .probe = mwl8k_probe,
8dee5eef 6340 .remove = mwl8k_remove,
a66098da
LB		 6341};
6342
5b0a3b7e 6343module_pci_driver(mwl8k_driver);
c2c357ce
LB		 6344
6345MODULE_DESCRIPTION(MWL8K_DESC);
6346MODULE_VERSION(MWL8K_VERSION);
6347MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
6348MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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