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mwl8k: remove MWL8K_WMM_* defines
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da
LB		 4 *
5 * Copyright (C) 2008 Marvell Semiconductor Inc.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/spinlock.h>
16#include <linux/list.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/completion.h>
20#include <linux/etherdevice.h>
21#include <net/mac80211.h>
22#include <linux/moduleparam.h>
23#include <linux/firmware.h>
24#include <linux/workqueue.h>
25
26#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
27#define MWL8K_NAME KBUILD_MODNAME
28#define MWL8K_VERSION "0.9.1"
29
30MODULE_DESCRIPTION(MWL8K_DESC);
31MODULE_VERSION(MWL8K_VERSION);
32MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
33MODULE_LICENSE("GPL");
34
35static DEFINE_PCI_DEVICE_TABLE(mwl8k_table) = {
36 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = 8687, },
37 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = 8687, },
38 { }
39};
40MODULE_DEVICE_TABLE(pci, mwl8k_table);
41
a66098da
LB		 42/* Register definitions */
43#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 44#define MWL8K_MODE_STA 0x0000005a
45#define MWL8K_MODE_AP 0x000000a5
a66098da 46#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 47#define MWL8K_FWSTA_READY 0xf0f1f2f4
48#define MWL8K_FWAP_READY 0xf1f2f4a5
49#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 50#define MWL8K_HIU_SCRATCH 0x00000c40
51
52/* Host->device communications */
53#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
54#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
55#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
56#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
57#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 58#define MWL8K_H2A_INT_DUMMY (1 << 20)
59#define MWL8K_H2A_INT_RESET (1 << 15)
60#define MWL8K_H2A_INT_DOORBELL (1 << 1)
61#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 62
63/* Device->host communications */
64#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
65#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
66#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
67#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
68#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 69#define MWL8K_A2H_INT_DUMMY (1 << 20)
70#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
71#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
72#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
73#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
74#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
75#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
76#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
77#define MWL8K_A2H_INT_RX_READY (1 << 1)
78#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 79
80#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
81 MWL8K_A2H_INT_CHNL_SWITCHED | \
82 MWL8K_A2H_INT_QUEUE_EMPTY | \
83 MWL8K_A2H_INT_RADAR_DETECT | \
84 MWL8K_A2H_INT_RADIO_ON | \
85 MWL8K_A2H_INT_RADIO_OFF | \
86 MWL8K_A2H_INT_MAC_EVENT | \
87 MWL8K_A2H_INT_OPC_DONE | \
88 MWL8K_A2H_INT_RX_READY | \
89 MWL8K_A2H_INT_TX_DONE)
90
91/* WME stream classes */
92#define WME_AC_BE 0 /* best effort */
93#define WME_AC_BK 1 /* background */
94#define WME_AC_VI 2 /* video */
95#define WME_AC_VO 3 /* voice */
96
97#define MWL8K_RX_QUEUES 1
98#define MWL8K_TX_QUEUES 4
99
100struct mwl8k_rx_queue {
101 int rx_desc_count;
102
103 /* hw receives here */
104 int rx_head;
105
106 /* refill descs here */
107 int rx_tail;
108
109 struct mwl8k_rx_desc *rx_desc_area;
110 dma_addr_t rx_desc_dma;
111 struct sk_buff **rx_skb;
112};
113
114struct mwl8k_skb {
115 /*
116 * The DMA engine requires a modification to the payload.
117 * If the skbuff is shared/cloned, it needs to be unshared.
118 * This method is used to ensure the stack always gets back
119 * the skbuff it sent for transmission.
120 */
121 struct sk_buff *clone;
122 struct sk_buff *skb;
123};
124
125struct mwl8k_tx_queue {
126 /* hw transmits here */
127 int tx_head;
128
129 /* sw appends here */
130 int tx_tail;
131
132 struct ieee80211_tx_queue_stats tx_stats;
133 struct mwl8k_tx_desc *tx_desc_area;
134 dma_addr_t tx_desc_dma;
135 struct mwl8k_skb *tx_skb;
136};
137
138/* Pointers to the firmware data and meta information about it. */
139struct mwl8k_firmware {
140 /* Microcode */
141 struct firmware *ucode;
142
143 /* Boot helper code */
144 struct firmware *helper;
145};
146
147struct mwl8k_priv {
148 void __iomem *regs;
149 struct ieee80211_hw *hw;
150
151 struct pci_dev *pdev;
152 u8 name[16];
153 /* firmware access lock */
154 spinlock_t fw_lock;
155
156 /* firmware files and meta data */
157 struct mwl8k_firmware fw;
158 u32 part_num;
159
160 /* lock held over TX and TX reap */
161 spinlock_t tx_lock;
a66098da
LB		 162
163 struct ieee80211_vif *vif;
a66098da
LB		 164
165 struct ieee80211_channel *current_channel;
166
167 /* power management status cookie from firmware */
168 u32 *cookie;
169 dma_addr_t cookie_dma;
170
171 u16 num_mcaddrs;
a66098da
LB		 172 u8 hw_rev;
173 __le32 fw_rev;
a66098da
LB		 174
175 /*
176 * Running count of TX packets in flight, to avoid
177 * iterating over the transmit rings each time.
178 */
179 int pending_tx_pkts;
180
181 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
182 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
183
184 /* PHY parameters */
185 struct ieee80211_supported_band band;
186 struct ieee80211_channel channels[14];
187 struct ieee80211_rate rates[12];
188
c46563b7 189 bool radio_on;
68ce3884 190 bool radio_short_preamble;
0439b1f5 191 bool wmm_enabled;
a66098da
LB		 192
193 /* Set if PHY config is in progress */
194 bool inconfig;
195
196 /* XXX need to convert this to handle multiple interfaces */
197 bool capture_beacon;
d89173f2 198 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 199 struct sk_buff *beacon_skb;
200
201 /*
202 * This FJ worker has to be global as it is scheduled from the
203 * RX handler. At this point we don't know which interface it
204 * belongs to until the list of bssids waiting to complete join
205 * is checked.
206 */
207 struct work_struct finalize_join_worker;
208
209 /* Tasklet to reclaim TX descriptors and buffers after tx */
210 struct tasklet_struct tx_reclaim_task;
211
212 /* Work thread to serialize configuration requests */
213 struct workqueue_struct *config_wq;
214 struct completion *hostcmd_wait;
215 struct completion *tx_wait;
216};
217
218/* Per interface specific private data */
219struct mwl8k_vif {
a66098da
LB		 220 /* backpointer to parent config block */
221 struct mwl8k_priv *priv;
222
223 /* BSS config of AP or IBSS from mac80211*/
224 struct ieee80211_bss_conf bss_info;
225
226 /* BSSID of AP or IBSS */
d89173f2
LB		 227 u8 bssid[ETH_ALEN];
228 u8 mac_addr[ETH_ALEN];
a66098da
LB		 229
230 /*
231 * Subset of supported legacy rates.
232 * Intersection of AP and STA supported rates.
233 */
234 struct ieee80211_rate legacy_rates[12];
235
236 /* number of supported legacy rates */
237 u8 legacy_nrates;
238
a66098da
LB		 239 /* Index into station database.Returned by update_sta_db call */
240 u8 peer_id;
241
242 /* Non AMPDU sequence number assigned by driver */
243 u16 seqno;
a66098da
LB		 244};
245
a94cc97e 246#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 247
248static const struct ieee80211_channel mwl8k_channels[] = {
249 { .center_freq = 2412, .hw_value = 1, },
250 { .center_freq = 2417, .hw_value = 2, },
251 { .center_freq = 2422, .hw_value = 3, },
252 { .center_freq = 2427, .hw_value = 4, },
253 { .center_freq = 2432, .hw_value = 5, },
254 { .center_freq = 2437, .hw_value = 6, },
255 { .center_freq = 2442, .hw_value = 7, },
256 { .center_freq = 2447, .hw_value = 8, },
257 { .center_freq = 2452, .hw_value = 9, },
258 { .center_freq = 2457, .hw_value = 10, },
259 { .center_freq = 2462, .hw_value = 11, },
260};
261
262static const struct ieee80211_rate mwl8k_rates[] = {
263 { .bitrate = 10, .hw_value = 2, },
264 { .bitrate = 20, .hw_value = 4, },
265 { .bitrate = 55, .hw_value = 11, },
266 { .bitrate = 60, .hw_value = 12, },
267 { .bitrate = 90, .hw_value = 18, },
268 { .bitrate = 110, .hw_value = 22, },
269 { .bitrate = 120, .hw_value = 24, },
270 { .bitrate = 180, .hw_value = 36, },
271 { .bitrate = 240, .hw_value = 48, },
272 { .bitrate = 360, .hw_value = 72, },
273 { .bitrate = 480, .hw_value = 96, },
274 { .bitrate = 540, .hw_value = 108, },
275};
276
a66098da
LB		 277/* Slot time */
278
279/* Short Slot: 9us slot time */
280#define MWL8K_SHORT_SLOTTIME 1
281
282/* Long slot: 20us slot time */
283#define MWL8K_LONG_SLOTTIME 0
284
285/* Set or get info from Firmware */
286#define MWL8K_CMD_SET 0x0001
287#define MWL8K_CMD_GET 0x0000
288
289/* Firmware command codes */
290#define MWL8K_CMD_CODE_DNLD 0x0001
291#define MWL8K_CMD_GET_HW_SPEC 0x0003
292#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
293#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 294#define MWL8K_CMD_RADIO_CONTROL 0x001c
295#define MWL8K_CMD_RF_TX_POWER 0x001e
a66098da
LB		 296#define MWL8K_CMD_SET_PRE_SCAN 0x0107
297#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 298#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
299#define MWL8K_CMD_SET_AID 0x010d
300#define MWL8K_CMD_SET_RATE 0x0110
301#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
302#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 303#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 304#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
305#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 306#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 307#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 308#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
a66098da 309#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 310#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 311
312static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
313{
314#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
315 snprintf(buf, bufsize, "%s", #x);\
316 return buf;\
317 } while (0)
ce9e2e1b 318 switch (cmd & ~0x8000) {
a66098da
LB		 319 MWL8K_CMDNAME(CODE_DNLD);
320 MWL8K_CMDNAME(GET_HW_SPEC);
321 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
322 MWL8K_CMDNAME(GET_STAT);
323 MWL8K_CMDNAME(RADIO_CONTROL);
324 MWL8K_CMDNAME(RF_TX_POWER);
325 MWL8K_CMDNAME(SET_PRE_SCAN);
326 MWL8K_CMDNAME(SET_POST_SCAN);
327 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 328 MWL8K_CMDNAME(SET_AID);
329 MWL8K_CMDNAME(SET_RATE);
330 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
331 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 332 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 333 MWL8K_CMDNAME(SET_EDCA_PARAMS);
334 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 335 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 336 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 337 MWL8K_CMDNAME(ENABLE_SNIFFER);
a66098da 338 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 339 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 340 default:
341 snprintf(buf, bufsize, "0x%x", cmd);
342 }
343#undef MWL8K_CMDNAME
344
345 return buf;
346}
347
348/* Hardware and firmware reset */
349static void mwl8k_hw_reset(struct mwl8k_priv *priv)
350{
351 iowrite32(MWL8K_H2A_INT_RESET,
352 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
353 iowrite32(MWL8K_H2A_INT_RESET,
354 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
355 msleep(20);
356}
357
358/* Release fw image */
359static void mwl8k_release_fw(struct firmware **fw)
360{
361 if (*fw == NULL)
362 return;
363 release_firmware(*fw);
364 *fw = NULL;
365}
366
367static void mwl8k_release_firmware(struct mwl8k_priv *priv)
368{
369 mwl8k_release_fw(&priv->fw.ucode);
370 mwl8k_release_fw(&priv->fw.helper);
371}
372
373/* Request fw image */
374static int mwl8k_request_fw(struct mwl8k_priv *priv,
375 const char *fname, struct firmware **fw)
376{
377 /* release current image */
378 if (*fw != NULL)
379 mwl8k_release_fw(fw);
380
381 return request_firmware((const struct firmware **)fw,
382 fname, &priv->pdev->dev);
383}
384
385static int mwl8k_request_firmware(struct mwl8k_priv *priv, u32 part_num)
386{
387 u8 filename[64];
388 int rc;
389
390 priv->part_num = part_num;
391
392 snprintf(filename, sizeof(filename),
393 "mwl8k/helper_%u.fw", priv->part_num);
394
395 rc = mwl8k_request_fw(priv, filename, &priv->fw.helper);
396 if (rc) {
397 printk(KERN_ERR
398 "%s Error requesting helper firmware file %s\n",
399 pci_name(priv->pdev), filename);
400 return rc;
401 }
402
403 snprintf(filename, sizeof(filename),
404 "mwl8k/fmimage_%u.fw", priv->part_num);
405
406 rc = mwl8k_request_fw(priv, filename, &priv->fw.ucode);
407 if (rc) {
408 printk(KERN_ERR "%s Error requesting firmware file %s\n",
409 pci_name(priv->pdev), filename);
410 mwl8k_release_fw(&priv->fw.helper);
411 return rc;
412 }
413
414 return 0;
415}
416
417struct mwl8k_cmd_pkt {
418 __le16 code;
419 __le16 length;
420 __le16 seq_num;
421 __le16 result;
422 char payload[0];
423} __attribute__((packed));
424
425/*
426 * Firmware loading.
427 */
428static int
429mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
430{
431 void __iomem *regs = priv->regs;
432 dma_addr_t dma_addr;
433 int rc;
434 int loops;
435
436 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
437 if (pci_dma_mapping_error(priv->pdev, dma_addr))
438 return -ENOMEM;
439
440 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
441 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
442 iowrite32(MWL8K_H2A_INT_DOORBELL,
443 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
444 iowrite32(MWL8K_H2A_INT_DUMMY,
445 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
446
447 rc = -ETIMEDOUT;
448 loops = 1000;
449 do {
450 u32 int_code;
451
452 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
453 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
454 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
455 rc = 0;
456 break;
457 }
458
459 udelay(1);
460 } while (--loops);
461
462 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
463
464 /*
465 * Clear 'command done' interrupt bit.
466 */
467 loops = 1000;
468 do {
469 u32 status;
470
471 status = ioread32(priv->regs +
472 MWL8K_HIU_A2H_INTERRUPT_STATUS);
473 if (status & MWL8K_A2H_INT_OPC_DONE) {
474 iowrite32(~MWL8K_A2H_INT_OPC_DONE,
475 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
476 ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
477 break;
478 }
479
480 udelay(1);
481 } while (--loops);
482
483 return rc;
484}
485
486static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
487 const u8 *data, size_t length)
488{
489 struct mwl8k_cmd_pkt *cmd;
490 int done;
491 int rc = 0;
492
493 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
494 if (cmd == NULL)
495 return -ENOMEM;
496
497 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
498 cmd->seq_num = 0;
499 cmd->result = 0;
500
501 done = 0;
502 while (length) {
503 int block_size = length > 256 ? 256 : length;
504
505 memcpy(cmd->payload, data + done, block_size);
506 cmd->length = cpu_to_le16(block_size);
507
508 rc = mwl8k_send_fw_load_cmd(priv, cmd,
509 sizeof(*cmd) + block_size);
510 if (rc)
511 break;
512
513 done += block_size;
514 length -= block_size;
515 }
516
517 if (!rc) {
518 cmd->length = 0;
519 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
520 }
521
522 kfree(cmd);
523
524 return rc;
525}
526
527static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
528 const u8 *data, size_t length)
529{
530 unsigned char *buffer;
531 int may_continue, rc = 0;
532 u32 done, prev_block_size;
533
534 buffer = kmalloc(1024, GFP_KERNEL);
535 if (buffer == NULL)
536 return -ENOMEM;
537
538 done = 0;
539 prev_block_size = 0;
540 may_continue = 1000;
541 while (may_continue > 0) {
542 u32 block_size;
543
544 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
545 if (block_size & 1) {
546 block_size &= ~1;
547 may_continue--;
548 } else {
549 done += prev_block_size;
550 length -= prev_block_size;
551 }
552
553 if (block_size > 1024 || block_size > length) {
554 rc = -EOVERFLOW;
555 break;
556 }
557
558 if (length == 0) {
559 rc = 0;
560 break;
561 }
562
563 if (block_size == 0) {
564 rc = -EPROTO;
565 may_continue--;
566 udelay(1);
567 continue;
568 }
569
570 prev_block_size = block_size;
571 memcpy(buffer, data + done, block_size);
572
573 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
574 if (rc)
575 break;
576 }
577
578 if (!rc && length != 0)
579 rc = -EREMOTEIO;
580
581 kfree(buffer);
582
583 return rc;
584}
585
586static int mwl8k_load_firmware(struct mwl8k_priv *priv)
587{
588 int loops, rc;
589
590 const u8 *ucode = priv->fw.ucode->data;
591 size_t ucode_len = priv->fw.ucode->size;
592 const u8 *helper = priv->fw.helper->data;
593 size_t helper_len = priv->fw.helper->size;
594
595 if (!memcmp(ucode, "\x01\x00\x00\x00", 4)) {
596 rc = mwl8k_load_fw_image(priv, helper, helper_len);
597 if (rc) {
598 printk(KERN_ERR "%s: unable to load firmware "
599 "helper image\n", pci_name(priv->pdev));
600 return rc;
601 }
602 msleep(1);
603
604 rc = mwl8k_feed_fw_image(priv, ucode, ucode_len);
605 } else {
606 rc = mwl8k_load_fw_image(priv, ucode, ucode_len);
607 }
608
609 if (rc) {
610 printk(KERN_ERR "%s: unable to load firmware data\n",
611 pci_name(priv->pdev));
612 return rc;
613 }
614
615 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
616 msleep(1);
617
618 loops = 200000;
619 do {
620 if (ioread32(priv->regs + MWL8K_HIU_INT_CODE)
621 == MWL8K_FWSTA_READY)
622 break;
623 udelay(1);
624 } while (--loops);
625
626 return loops ? 0 : -ETIMEDOUT;
627}
628
629
630/*
631 * Defines shared between transmission and reception.
632 */
633/* HT control fields for firmware */
634struct ewc_ht_info {
635 __le16 control1;
636 __le16 control2;
637 __le16 control3;
638} __attribute__((packed));
639
640/* Firmware Station database operations */
641#define MWL8K_STA_DB_ADD_ENTRY 0
642#define MWL8K_STA_DB_MODIFY_ENTRY 1
643#define MWL8K_STA_DB_DEL_ENTRY 2
644#define MWL8K_STA_DB_FLUSH 3
645
646/* Peer Entry flags - used to define the type of the peer node */
647#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da
LB		 648
649#define MWL8K_IEEE_LEGACY_DATA_RATES 12
650#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 651
652struct peer_capability_info {
653 /* Peer type - AP vs. STA. */
654 __u8 peer_type;
655
656 /* Basic 802.11 capabilities from assoc resp. */
657 __le16 basic_caps;
658
659 /* Set if peer supports 802.11n high throughput (HT). */
660 __u8 ht_support;
661
662 /* Valid if HT is supported. */
663 __le16 ht_caps;
664 __u8 extended_ht_caps;
665 struct ewc_ht_info ewc_info;
666
667 /* Legacy rate table. Intersection of our rates and peer rates. */
668 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
669
670 /* HT rate table. Intersection of our rates and peer rates. */
671 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 672 __u8 pad[16];
a66098da
LB		 673
674 /* If set, interoperability mode, no proprietary extensions. */
675 __u8 interop;
676 __u8 pad2;
677 __u8 station_id;
678 __le16 amsdu_enabled;
679} __attribute__((packed));
680
681/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 682static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
683{
684 u16 val_mask = 1 << 4;
685
686 /* End of Service Period Bit 4 */
687 return qos | val_mask;
688}
689
690static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
691{
692 u16 val_mask = 0x3;
693 u8 shift = 5;
694 u16 qos_mask = ~(val_mask << shift);
695
696 /* Ack Policy Bit 5-6 */
697 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
698}
699
700static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
701{
702 u16 val_mask = 1 << 7;
703
704 /* AMSDU present Bit 7 */
705 return qos | val_mask;
706}
707
708static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
709{
710 u16 val_mask = 0xff;
711 u8 shift = 8;
712 u16 qos_mask = ~(val_mask << shift);
713
714 /* Queue Length Bits 8-15 */
715 return (qos & qos_mask) | ((len & val_mask) << shift);
716}
717
718/* DMA header used by firmware and hardware. */
719struct mwl8k_dma_data {
720 __le16 fwlen;
721 struct ieee80211_hdr wh;
722} __attribute__((packed));
723
724/* Routines to add/remove DMA header from skb. */
725static inline int mwl8k_remove_dma_header(struct sk_buff *skb)
726{
727 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)(skb->data);
728 void *dst, *src = &tr->wh;
729 __le16 fc = tr->wh.frame_control;
730 int hdrlen = ieee80211_hdrlen(fc);
731 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
732
733 dst = (void *)tr + space;
734 if (dst != src) {
735 memmove(dst, src, hdrlen);
736 skb_pull(skb, space);
737 }
738
739 return 0;
740}
741
742static inline struct sk_buff *mwl8k_add_dma_header(struct sk_buff *skb)
743{
744 struct ieee80211_hdr *wh;
745 u32 hdrlen, pktlen;
746 struct mwl8k_dma_data *tr;
747
748 wh = (struct ieee80211_hdr *)skb->data;
749 hdrlen = ieee80211_hdrlen(wh->frame_control);
750 pktlen = skb->len;
751
752 /*
753 * Copy up/down the 802.11 header; the firmware requires
754 * we present a 2-byte payload length followed by a
755 * 4-address header (w/o QoS), followed (optionally) by
756 * any WEP/ExtIV header (but only filled in for CCMP).
757 */
758 if (hdrlen != sizeof(struct mwl8k_dma_data))
759 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
760
761 tr = (struct mwl8k_dma_data *)skb->data;
762 if (wh != &tr->wh)
763 memmove(&tr->wh, wh, hdrlen);
764
765 /* Clear addr4 */
d89173f2 766 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 767
768 /*
769 * Firmware length is the length of the fully formed "802.11
770 * payload". That is, everything except for the 802.11 header.
771 * This includes all crypto material including the MIC.
772 */
773 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
774
775 return skb;
776}
777
778
779/*
780 * Packet reception.
781 */
a66098da 782#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
a66098da
LB		 783
784struct mwl8k_rx_desc {
785 __le16 pkt_len;
786 __u8 link_quality;
787 __u8 noise_level;
788 __le32 pkt_phys_addr;
789 __le32 next_rx_desc_phys_addr;
790 __le16 qos_control;
791 __le16 rate_info;
792 __le32 pad0[4];
793 __u8 rssi;
794 __u8 channel;
795 __le16 pad1;
796 __u8 rx_ctrl;
797 __u8 rx_status;
798 __u8 pad2[2];
799} __attribute__((packed));
800
801#define MWL8K_RX_DESCS 256
802#define MWL8K_RX_MAXSZ 3800
803
804static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
805{
806 struct mwl8k_priv *priv = hw->priv;
807 struct mwl8k_rx_queue *rxq = priv->rxq + index;
808 int size;
809 int i;
810
811 rxq->rx_desc_count = 0;
812 rxq->rx_head = 0;
813 rxq->rx_tail = 0;
814
815 size = MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc);
816
817 rxq->rx_desc_area =
818 pci_alloc_consistent(priv->pdev, size, &rxq->rx_desc_dma);
819 if (rxq->rx_desc_area == NULL) {
820 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
821 priv->name);
822 return -ENOMEM;
823 }
824 memset(rxq->rx_desc_area, 0, size);
825
826 rxq->rx_skb = kmalloc(MWL8K_RX_DESCS *
827 sizeof(*rxq->rx_skb), GFP_KERNEL);
828 if (rxq->rx_skb == NULL) {
829 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
830 priv->name);
831 pci_free_consistent(priv->pdev, size,
832 rxq->rx_desc_area, rxq->rx_desc_dma);
833 return -ENOMEM;
834 }
835 memset(rxq->rx_skb, 0, MWL8K_RX_DESCS * sizeof(*rxq->rx_skb));
836
837 for (i = 0; i < MWL8K_RX_DESCS; i++) {
838 struct mwl8k_rx_desc *rx_desc;
839 int nexti;
840
841 rx_desc = rxq->rx_desc_area + i;
842 nexti = (i + 1) % MWL8K_RX_DESCS;
843
844 rx_desc->next_rx_desc_phys_addr =
845 cpu_to_le32(rxq->rx_desc_dma
846 + nexti * sizeof(*rx_desc));
c491bf12 847 rx_desc->rx_ctrl = MWL8K_RX_CTRL_OWNED_BY_HOST;
a66098da
LB		 848 }
849
850 return 0;
851}
852
853static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
854{
855 struct mwl8k_priv *priv = hw->priv;
856 struct mwl8k_rx_queue *rxq = priv->rxq + index;
857 int refilled;
858
859 refilled = 0;
860 while (rxq->rx_desc_count < MWL8K_RX_DESCS && limit--) {
861 struct sk_buff *skb;
862 int rx;
863
864 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
865 if (skb == NULL)
866 break;
867
868 rxq->rx_desc_count++;
869
870 rx = rxq->rx_tail;
871 rxq->rx_tail = (rx + 1) % MWL8K_RX_DESCS;
872
873 rxq->rx_desc_area[rx].pkt_phys_addr =
874 cpu_to_le32(pci_map_single(priv->pdev, skb->data,
875 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE));
876
877 rxq->rx_desc_area[rx].pkt_len = cpu_to_le16(MWL8K_RX_MAXSZ);
878 rxq->rx_skb[rx] = skb;
879 wmb();
880 rxq->rx_desc_area[rx].rx_ctrl = 0;
881
882 refilled++;
883 }
884
885 return refilled;
886}
887
888/* Must be called only when the card's reception is completely halted */
889static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
890{
891 struct mwl8k_priv *priv = hw->priv;
892 struct mwl8k_rx_queue *rxq = priv->rxq + index;
893 int i;
894
895 for (i = 0; i < MWL8K_RX_DESCS; i++) {
896 if (rxq->rx_skb[i] != NULL) {
897 unsigned long addr;
898
899 addr = le32_to_cpu(rxq->rx_desc_area[i].pkt_phys_addr);
900 pci_unmap_single(priv->pdev, addr, MWL8K_RX_MAXSZ,
901 PCI_DMA_FROMDEVICE);
902 kfree_skb(rxq->rx_skb[i]);
903 rxq->rx_skb[i] = NULL;
904 }
905 }
906
907 kfree(rxq->rx_skb);
908 rxq->rx_skb = NULL;
909
910 pci_free_consistent(priv->pdev,
911 MWL8K_RX_DESCS * sizeof(struct mwl8k_rx_desc),
912 rxq->rx_desc_area, rxq->rx_desc_dma);
913 rxq->rx_desc_area = NULL;
914}
915
916
917/*
918 * Scan a list of BSSIDs to process for finalize join.
919 * Allows for extension to process multiple BSSIDs.
920 */
921static inline int
922mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
923{
924 return priv->capture_beacon &&
925 ieee80211_is_beacon(wh->frame_control) &&
926 !compare_ether_addr(wh->addr3, priv->capture_bssid);
927}
928
929static inline void mwl8k_save_beacon(struct mwl8k_priv *priv,
930 struct sk_buff *skb)
931{
932 priv->capture_beacon = false;
d89173f2 933 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 934
935 /*
936 * Use GFP_ATOMIC as rxq_process is called from
937 * the primary interrupt handler, memory allocation call
938 * must not sleep.
939 */
940 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
941 if (priv->beacon_skb != NULL)
942 queue_work(priv->config_wq,
943 &priv->finalize_join_worker);
944}
945
946static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
947{
948 struct mwl8k_priv *priv = hw->priv;
949 struct mwl8k_rx_queue *rxq = priv->rxq + index;
950 int processed;
951
952 processed = 0;
953 while (rxq->rx_desc_count && limit--) {
954 struct mwl8k_rx_desc *rx_desc;
955 struct sk_buff *skb;
956 struct ieee80211_rx_status status;
957 unsigned long addr;
958 struct ieee80211_hdr *wh;
959
960 rx_desc = rxq->rx_desc_area + rxq->rx_head;
961 if (!(rx_desc->rx_ctrl & MWL8K_RX_CTRL_OWNED_BY_HOST))
962 break;
963 rmb();
964
965 skb = rxq->rx_skb[rxq->rx_head];
d25f9f13
LB		 966 if (skb == NULL)
967 break;
a66098da
LB		 968 rxq->rx_skb[rxq->rx_head] = NULL;
969
970 rxq->rx_head = (rxq->rx_head + 1) % MWL8K_RX_DESCS;
971 rxq->rx_desc_count--;
972
973 addr = le32_to_cpu(rx_desc->pkt_phys_addr);
974 pci_unmap_single(priv->pdev, addr,
975 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
976
977 skb_put(skb, le16_to_cpu(rx_desc->pkt_len));
978 if (mwl8k_remove_dma_header(skb)) {
979 dev_kfree_skb(skb);
980 continue;
981 }
982
983 wh = (struct ieee80211_hdr *)skb->data;
984
985 /*
986 * Check for pending join operation. save a copy of
987 * the beacon and schedule a tasklet to send finalize
988 * join command to the firmware.
989 */
990 if (mwl8k_capture_bssid(priv, wh))
991 mwl8k_save_beacon(priv, skb);
992
993 memset(&status, 0, sizeof(status));
994 status.mactime = 0;
995 status.signal = -rx_desc->rssi;
996 status.noise = -rx_desc->noise_level;
997 status.qual = rx_desc->link_quality;
998 status.antenna = 1;
999 status.rate_idx = 1;
1000 status.flag = 0;
1001 status.band = IEEE80211_BAND_2GHZ;
1002 status.freq = ieee80211_channel_to_frequency(rx_desc->channel);
f1d58c25
JB		 1003 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1004 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1005
1006 processed++;
1007 }
1008
1009 return processed;
1010}
1011
1012
1013/*
1014 * Packet transmission.
1015 */
1016
1017/* Transmit queue assignment. */
1018enum {
1019 MWL8K_WME_AC_BK = 0, /* background access */
1020 MWL8K_WME_AC_BE = 1, /* best effort access */
1021 MWL8K_WME_AC_VI = 2, /* video access */
1022 MWL8K_WME_AC_VO = 3, /* voice access */
1023};
1024
1025/* Transmit packet ACK policy */
1026#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1027#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1028
1029#define GET_TXQ(_ac) (\
1030 ((_ac) == WME_AC_VO) ? MWL8K_WME_AC_VO : \
1031 ((_ac) == WME_AC_VI) ? MWL8K_WME_AC_VI : \
1032 ((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
1033 MWL8K_WME_AC_BE)
1034
a66098da
LB		 1035#define MWL8K_TXD_STATUS_OK 0x00000001
1036#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1037#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1038#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1039#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1040
1041struct mwl8k_tx_desc {
1042 __le32 status;
1043 __u8 data_rate;
1044 __u8 tx_priority;
1045 __le16 qos_control;
1046 __le32 pkt_phys_addr;
1047 __le16 pkt_len;
d89173f2 1048 __u8 dest_MAC_addr[ETH_ALEN];
a66098da
LB		 1049 __le32 next_tx_desc_phys_addr;
1050 __le32 reserved;
1051 __le16 rate_info;
1052 __u8 peer_id;
1053 __u8 tx_frag_cnt;
1054} __attribute__((packed));
1055
1056#define MWL8K_TX_DESCS 128
1057
1058static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1059{
1060 struct mwl8k_priv *priv = hw->priv;
1061 struct mwl8k_tx_queue *txq = priv->txq + index;
1062 int size;
1063 int i;
1064
ce9e2e1b 1065 memset(&txq->tx_stats, 0, sizeof(struct ieee80211_tx_queue_stats));
a66098da
LB		 1066 txq->tx_stats.limit = MWL8K_TX_DESCS;
1067 txq->tx_head = 0;
1068 txq->tx_tail = 0;
1069
1070 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1071
1072 txq->tx_desc_area =
1073 pci_alloc_consistent(priv->pdev, size, &txq->tx_desc_dma);
1074 if (txq->tx_desc_area == NULL) {
1075 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
1076 priv->name);
1077 return -ENOMEM;
1078 }
1079 memset(txq->tx_desc_area, 0, size);
1080
1081 txq->tx_skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->tx_skb),
1082 GFP_KERNEL);
1083 if (txq->tx_skb == NULL) {
1084 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
1085 priv->name);
1086 pci_free_consistent(priv->pdev, size,
1087 txq->tx_desc_area, txq->tx_desc_dma);
1088 return -ENOMEM;
1089 }
1090 memset(txq->tx_skb, 0, MWL8K_TX_DESCS * sizeof(*txq->tx_skb));
1091
1092 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1093 struct mwl8k_tx_desc *tx_desc;
1094 int nexti;
1095
1096 tx_desc = txq->tx_desc_area + i;
1097 nexti = (i + 1) % MWL8K_TX_DESCS;
1098
1099 tx_desc->status = 0;
1100 tx_desc->next_tx_desc_phys_addr =
1101 cpu_to_le32(txq->tx_desc_dma +
1102 nexti * sizeof(*tx_desc));
1103 }
1104
1105 return 0;
1106}
1107
1108static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1109{
1110 iowrite32(MWL8K_H2A_INT_PPA_READY,
1111 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1112 iowrite32(MWL8K_H2A_INT_DUMMY,
1113 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1114 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1115}
1116
1117static inline int mwl8k_txq_busy(struct mwl8k_priv *priv)
1118{
1119 return priv->pending_tx_pkts;
1120}
1121
1122struct mwl8k_txq_info {
1123 u32 fw_owned;
1124 u32 drv_owned;
1125 u32 unused;
1126 u32 len;
1127 u32 head;
1128 u32 tail;
1129};
1130
1131static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
1132 struct mwl8k_txq_info txinfo[],
1133 u32 num_queues)
1134{
1135 int count, desc, status;
1136 struct mwl8k_tx_queue *txq;
1137 struct mwl8k_tx_desc *tx_desc;
1138 int ndescs = 0;
1139
1140 memset(txinfo, 0, num_queues * sizeof(struct mwl8k_txq_info));
1141 spin_lock_bh(&priv->tx_lock);
1142 for (count = 0; count < num_queues; count++) {
1143 txq = priv->txq + count;
1144 txinfo[count].len = txq->tx_stats.len;
1145 txinfo[count].head = txq->tx_head;
1146 txinfo[count].tail = txq->tx_tail;
1147 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
1148 tx_desc = txq->tx_desc_area + desc;
1149 status = le32_to_cpu(tx_desc->status);
1150
1151 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1152 txinfo[count].fw_owned++;
1153 else
1154 txinfo[count].drv_owned++;
1155
1156 if (tx_desc->pkt_len == 0)
1157 txinfo[count].unused++;
1158 }
1159 }
1160 spin_unlock_bh(&priv->tx_lock);
1161
1162 return ndescs;
1163}
1164
1165static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw, u32 delay_ms)
1166{
a66098da
LB		 1167 struct mwl8k_priv *priv = hw->priv;
1168 DECLARE_COMPLETION_ONSTACK(cmd_wait);
ce9e2e1b
LB		 1169 u32 count;
1170 unsigned long timeout;
a66098da
LB		 1171
1172 might_sleep();
1173
1174 if (priv->tx_wait != NULL)
1175 printk(KERN_ERR "WARNING Previous TXWaitEmpty instance\n");
1176
1177 spin_lock_bh(&priv->tx_lock);
1178 count = mwl8k_txq_busy(priv);
1179 if (count) {
1180 priv->tx_wait = &cmd_wait;
c46563b7 1181 if (priv->radio_on)
a66098da
LB		 1182 mwl8k_tx_start(priv);
1183 }
1184 spin_unlock_bh(&priv->tx_lock);
1185
1186 if (count) {
1187 struct mwl8k_txq_info txinfo[4];
1188 int index;
1189 int newcount;
1190
1191 timeout = wait_for_completion_timeout(&cmd_wait,
1192 msecs_to_jiffies(delay_ms));
1193 if (timeout)
1194 return 0;
1195
1196 spin_lock_bh(&priv->tx_lock);
1197 priv->tx_wait = NULL;
1198 newcount = mwl8k_txq_busy(priv);
1199 spin_unlock_bh(&priv->tx_lock);
1200
1201 printk(KERN_ERR "%s(%u) TIMEDOUT:%ums Pend:%u-->%u\n",
1202 __func__, __LINE__, delay_ms, count, newcount);
1203
1204 mwl8k_scan_tx_ring(priv, txinfo, 4);
ce9e2e1b 1205 for (index = 0; index < 4; index++)
a66098da
LB		 1206 printk(KERN_ERR
1207 "TXQ:%u L:%u H:%u T:%u FW:%u DRV:%u U:%u\n",
1208 index,
1209 txinfo[index].len,
1210 txinfo[index].head,
1211 txinfo[index].tail,
1212 txinfo[index].fw_owned,
1213 txinfo[index].drv_owned,
1214 txinfo[index].unused);
ce9e2e1b 1215
a66098da
LB		 1216 return -ETIMEDOUT;
1217 }
1218
1219 return 0;
1220}
1221
c23b5a69
LB		 1222#define MWL8K_TXD_SUCCESS(status) \
1223 ((status) & (MWL8K_TXD_STATUS_OK | \
1224 MWL8K_TXD_STATUS_OK_RETRY | \
1225 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1226
1227static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1228{
1229 struct mwl8k_priv *priv = hw->priv;
1230 struct mwl8k_tx_queue *txq = priv->txq + index;
1231 int wake = 0;
1232
1233 while (txq->tx_stats.len > 0) {
1234 int tx;
1235 int rc;
1236 struct mwl8k_tx_desc *tx_desc;
1237 unsigned long addr;
ce9e2e1b 1238 int size;
a66098da
LB		 1239 struct sk_buff *skb;
1240 struct ieee80211_tx_info *info;
1241 u32 status;
1242
1243 rc = 0;
1244 tx = txq->tx_head;
1245 tx_desc = txq->tx_desc_area + tx;
1246
1247 status = le32_to_cpu(tx_desc->status);
1248
1249 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1250 if (!force)
1251 break;
1252 tx_desc->status &=
1253 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1254 }
1255
1256 txq->tx_head = (tx + 1) % MWL8K_TX_DESCS;
1257 BUG_ON(txq->tx_stats.len == 0);
1258 txq->tx_stats.len--;
1259 priv->pending_tx_pkts--;
1260
1261 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1262 size = le16_to_cpu(tx_desc->pkt_len);
a66098da
LB		 1263 skb = txq->tx_skb[tx].skb;
1264 txq->tx_skb[tx].skb = NULL;
1265
1266 BUG_ON(skb == NULL);
1267 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1268
1269 rc = mwl8k_remove_dma_header(skb);
1270
1271 /* Mark descriptor as unused */
1272 tx_desc->pkt_phys_addr = 0;
1273 tx_desc->pkt_len = 0;
1274
1275 if (txq->tx_skb[tx].clone) {
1276 /* Replace with original skb
1277 * before returning to stack
1278 * as buffer has been cloned
1279 */
1280 dev_kfree_skb(skb);
1281 skb = txq->tx_skb[tx].clone;
1282 txq->tx_skb[tx].clone = NULL;
1283 }
1284
1285 if (rc) {
1286 /* Something has gone wrong here.
1287 * Failed to remove DMA header.
1288 * Print error message and drop packet.
1289 */
1290 printk(KERN_ERR "%s: Error removing DMA header from "
1291 "tx skb 0x%p.\n", priv->name, skb);
1292
1293 dev_kfree_skb(skb);
1294 continue;
1295 }
1296
1297 info = IEEE80211_SKB_CB(skb);
1298 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1299 if (MWL8K_TXD_SUCCESS(status))
a66098da 1300 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1301
1302 ieee80211_tx_status_irqsafe(hw, skb);
1303
c46563b7 1304 wake = !priv->inconfig && priv->radio_on;
a66098da
LB		 1305 }
1306
1307 if (wake)
1308 ieee80211_wake_queue(hw, index);
1309}
1310
1311/* must be called only when the card's transmit is completely halted */
1312static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1313{
1314 struct mwl8k_priv *priv = hw->priv;
1315 struct mwl8k_tx_queue *txq = priv->txq + index;
1316
1317 mwl8k_txq_reclaim(hw, index, 1);
1318
1319 kfree(txq->tx_skb);
1320 txq->tx_skb = NULL;
1321
1322 pci_free_consistent(priv->pdev,
1323 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
1324 txq->tx_desc_area, txq->tx_desc_dma);
1325 txq->tx_desc_area = NULL;
1326}
1327
1328static int
1329mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1330{
1331 struct mwl8k_priv *priv = hw->priv;
1332 struct ieee80211_tx_info *tx_info;
1333 struct ieee80211_hdr *wh;
1334 struct mwl8k_tx_queue *txq;
1335 struct mwl8k_tx_desc *tx;
1336 struct mwl8k_dma_data *tr;
1337 struct mwl8k_vif *mwl8k_vif;
1338 struct sk_buff *org_skb = skb;
1339 dma_addr_t dma;
1340 u16 qos = 0;
1341 bool qosframe = false, ampduframe = false;
1342 bool mcframe = false, eapolframe = false;
1343 bool amsduframe = false;
1344 __le16 fc;
1345
1346 txq = priv->txq + index;
1347 tx = txq->tx_desc_area + txq->tx_tail;
1348
1349 BUG_ON(txq->tx_skb[txq->tx_tail].skb != NULL);
1350
1351 /*
1352 * Append HW DMA header to start of packet. Drop packet if
1353 * there is not enough space or a failure to unshare/unclone
1354 * the skb.
1355 */
1356 skb = mwl8k_add_dma_header(skb);
1357
1358 if (skb == NULL) {
1359 printk(KERN_DEBUG "%s: failed to prepend HW DMA "
1360 "header, dropping TX frame.\n", priv->name);
1361 dev_kfree_skb(org_skb);
1362 return NETDEV_TX_OK;
1363 }
1364
1365 tx_info = IEEE80211_SKB_CB(skb);
1366 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
1367 tr = (struct mwl8k_dma_data *)skb->data;
1368 wh = &tr->wh;
1369 fc = wh->frame_control;
1370 qosframe = ieee80211_is_data_qos(fc);
1371 mcframe = is_multicast_ether_addr(wh->addr1);
1372 ampduframe = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1373
1374 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1375 u16 seqno = mwl8k_vif->seqno;
1376 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1377 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1378 mwl8k_vif->seqno = seqno++ % 4096;
1379 }
1380
1381 if (qosframe)
1382 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1383
1384 dma = pci_map_single(priv->pdev, skb->data,
1385 skb->len, PCI_DMA_TODEVICE);
1386
1387 if (pci_dma_mapping_error(priv->pdev, dma)) {
1388 printk(KERN_DEBUG "%s: failed to dma map skb, "
1389 "dropping TX frame.\n", priv->name);
1390
1391 if (org_skb != NULL)
1392 dev_kfree_skb(org_skb);
1393 if (skb != NULL)
1394 dev_kfree_skb(skb);
1395 return NETDEV_TX_OK;
1396 }
1397
1398 /* Set desc header, cpu bit order. */
1399 tx->status = 0;
1400 tx->data_rate = 0;
1401 tx->tx_priority = index;
1402 tx->qos_control = 0;
1403 tx->rate_info = 0;
1404 tx->peer_id = mwl8k_vif->peer_id;
1405
1406 amsduframe = !!(qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT);
1407
1408 /* Setup firmware control bit fields for each frame type. */
1409 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
1410 tx->data_rate = 0;
1411 qos = mwl8k_qos_setbit_eosp(qos);
1412 /* Set Queue size to unspecified */
1413 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1414 } else if (ieee80211_is_data(fc)) {
1415 tx->data_rate = 1;
1416 if (mcframe)
1417 tx->status |= MWL8K_TXD_STATUS_MULTICAST_TX;
1418
1419 /*
1420 * Tell firmware to not send EAPOL pkts in an
1421 * aggregate. Verify against mac80211 tx path. If
1422 * stack turns off AMPDU for an EAPOL frame this
1423 * check will be removed.
1424 */
1425 if (eapolframe) {
1426 qos = mwl8k_qos_setbit_ack(qos,
1427 MWL8K_TXD_ACK_POLICY_NORMAL);
1428 } else {
1429 /* Send pkt in an aggregate if AMPDU frame. */
1430 if (ampduframe)
1431 qos = mwl8k_qos_setbit_ack(qos,
1432 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1433 else
1434 qos = mwl8k_qos_setbit_ack(qos,
1435 MWL8K_TXD_ACK_POLICY_NORMAL);
1436
1437 if (amsduframe)
1438 qos = mwl8k_qos_setbit_amsdu(qos);
1439 }
1440 }
1441
1442 /* Convert to little endian */
1443 tx->qos_control = cpu_to_le16(qos);
1444 tx->status = cpu_to_le32(tx->status);
1445 tx->pkt_phys_addr = cpu_to_le32(dma);
1446 tx->pkt_len = cpu_to_le16(skb->len);
1447
1448 txq->tx_skb[txq->tx_tail].skb = skb;
1449 txq->tx_skb[txq->tx_tail].clone =
1450 skb == org_skb ? NULL : org_skb;
1451
1452 spin_lock_bh(&priv->tx_lock);
1453
1454 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_OK |
1455 MWL8K_TXD_STATUS_FW_OWNED);
1456 wmb();
1457 txq->tx_stats.len++;
1458 priv->pending_tx_pkts++;
1459 txq->tx_stats.count++;
1460 txq->tx_tail++;
1461
1462 if (txq->tx_tail == MWL8K_TX_DESCS)
1463 txq->tx_tail = 0;
1464 if (txq->tx_head == txq->tx_tail)
1465 ieee80211_stop_queue(hw, index);
1466
1467 if (priv->inconfig) {
1468 /*
1469 * Silently queue packet when we are in the middle of
1470 * a config cycle. Notify firmware only if we are
1471 * waiting for TXQs to empty. If a packet is sent
1472 * before .config() is complete, perhaps it is better
1473 * to drop the packet, as the channel is being changed
1474 * and the packet will end up on the wrong channel.
1475 */
1476 printk(KERN_ERR "%s(): WARNING TX activity while "
1477 "in config\n", __func__);
1478
1479 if (priv->tx_wait != NULL)
1480 mwl8k_tx_start(priv);
1481 } else
1482 mwl8k_tx_start(priv);
1483
1484 spin_unlock_bh(&priv->tx_lock);
1485
1486 return NETDEV_TX_OK;
1487}
1488
1489
1490/*
1491 * Command processing.
1492 */
1493
1494/* Timeout firmware commands after 2000ms */
1495#define MWL8K_CMD_TIMEOUT_MS 2000
1496
1497static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1498{
1499 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1500 struct mwl8k_priv *priv = hw->priv;
1501 void __iomem *regs = priv->regs;
1502 dma_addr_t dma_addr;
1503 unsigned int dma_size;
1504 int rc;
a66098da
LB		 1505 unsigned long timeout = 0;
1506 u8 buf[32];
1507
1508 cmd->result = 0xFFFF;
1509 dma_size = le16_to_cpu(cmd->length);
1510 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1511 PCI_DMA_BIDIRECTIONAL);
1512 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1513 return -ENOMEM;
1514
1515 if (priv->hostcmd_wait != NULL)
1516 printk(KERN_ERR "WARNING host command in progress\n");
1517
1518 spin_lock_irq(&priv->fw_lock);
1519 priv->hostcmd_wait = &cmd_wait;
1520 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1521 iowrite32(MWL8K_H2A_INT_DOORBELL,
1522 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1523 iowrite32(MWL8K_H2A_INT_DUMMY,
1524 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1525 spin_unlock_irq(&priv->fw_lock);
1526
1527 timeout = wait_for_completion_timeout(&cmd_wait,
1528 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1529
37055bd4
LB		 1530 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1531 PCI_DMA_BIDIRECTIONAL);
1532
a66098da
LB		 1533 if (!timeout) {
1534 spin_lock_irq(&priv->fw_lock);
1535 priv->hostcmd_wait = NULL;
1536 spin_unlock_irq(&priv->fw_lock);
1537 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
1538 priv->name,
1539 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1540 MWL8K_CMD_TIMEOUT_MS);
1541 rc = -ETIMEDOUT;
1542 } else {
ce9e2e1b 1543 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1544 if (rc)
1545 printk(KERN_ERR "%s: Command %s error 0x%x\n",
1546 priv->name,
1547 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
ce9e2e1b 1548 cmd->result);
a66098da
LB		 1549 }
1550
a66098da
LB		 1551 return rc;
1552}
1553
1554/*
1555 * GET_HW_SPEC.
1556 */
1557struct mwl8k_cmd_get_hw_spec {
1558 struct mwl8k_cmd_pkt header;
1559 __u8 hw_rev;
1560 __u8 host_interface;
1561 __le16 num_mcaddrs;
d89173f2 1562 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1563 __le16 region_code;
1564 __le32 fw_rev;
1565 __le32 ps_cookie;
1566 __le32 caps;
1567 __u8 mcs_bitmap[16];
1568 __le32 rx_queue_ptr;
1569 __le32 num_tx_queues;
1570 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1571 __le32 caps2;
1572 __le32 num_tx_desc_per_queue;
1573 __le32 total_rx_desc;
1574} __attribute__((packed));
1575
1576static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1577{
1578 struct mwl8k_priv *priv = hw->priv;
1579 struct mwl8k_cmd_get_hw_spec *cmd;
1580 int rc;
1581 int i;
1582
1583 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1584 if (cmd == NULL)
1585 return -ENOMEM;
1586
1587 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1588 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1589
1590 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1591 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1592 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rx_desc_dma);
4ff6432e 1593 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da
LB		 1594 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1595 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].tx_desc_dma);
4ff6432e
LB		 1596 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1597 cmd->total_rx_desc = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1598
1599 rc = mwl8k_post_cmd(hw, &cmd->header);
1600
1601 if (!rc) {
1602 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1603 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1604 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1605 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1606 }
1607
1608 kfree(cmd);
1609 return rc;
1610}
1611
1612/*
1613 * CMD_MAC_MULTICAST_ADR.
1614 */
1615struct mwl8k_cmd_mac_multicast_adr {
1616 struct mwl8k_cmd_pkt header;
1617 __le16 action;
1618 __le16 numaddr;
ce9e2e1b 1619 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1620};
1621
1622#define MWL8K_ENABLE_RX_MULTICAST 0x000F
ce9e2e1b 1623
a66098da
LB		 1624static int mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw,
1625 int mc_count,
1626 struct dev_addr_list *mclist)
1627{
1628 struct mwl8k_cmd_mac_multicast_adr *cmd;
1629 int index = 0;
1630 int rc;
ce9e2e1b
LB		 1631 int size = sizeof(*cmd) + mc_count * ETH_ALEN;
1632
a66098da
LB		 1633 cmd = kzalloc(size, GFP_KERNEL);
1634 if (cmd == NULL)
1635 return -ENOMEM;
1636
1637 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1638 cmd->header.length = cpu_to_le16(size);
1639 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1640 cmd->numaddr = cpu_to_le16(mc_count);
ce9e2e1b
LB		 1641
1642 while (index < mc_count && mclist) {
d89173f2 1643 if (mclist->da_addrlen != ETH_ALEN) {
a66098da
LB		 1644 rc = -EINVAL;
1645 goto mwl8k_cmd_mac_multicast_adr_exit;
1646 }
ce9e2e1b 1647 memcpy(cmd->addr[index++], mclist->da_addr, ETH_ALEN);
a66098da
LB		 1648 mclist = mclist->next;
1649 }
1650
1651 rc = mwl8k_post_cmd(hw, &cmd->header);
1652
1653mwl8k_cmd_mac_multicast_adr_exit:
1654 kfree(cmd);
1655 return rc;
1656}
1657
1658/*
1659 * CMD_802_11_GET_STAT.
1660 */
1661struct mwl8k_cmd_802_11_get_stat {
1662 struct mwl8k_cmd_pkt header;
1663 __le16 action;
1664 __le32 stats[64];
1665} __attribute__((packed));
1666
1667#define MWL8K_STAT_ACK_FAILURE 9
1668#define MWL8K_STAT_RTS_FAILURE 12
1669#define MWL8K_STAT_FCS_ERROR 24
1670#define MWL8K_STAT_RTS_SUCCESS 11
1671
1672static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1673 struct ieee80211_low_level_stats *stats)
1674{
1675 struct mwl8k_cmd_802_11_get_stat *cmd;
1676 int rc;
1677
1678 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1679 if (cmd == NULL)
1680 return -ENOMEM;
1681
1682 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1683 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1684 cmd->action = cpu_to_le16(MWL8K_CMD_GET);
1685
1686 rc = mwl8k_post_cmd(hw, &cmd->header);
1687 if (!rc) {
1688 stats->dot11ACKFailureCount =
1689 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1690 stats->dot11RTSFailureCount =
1691 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1692 stats->dot11FCSErrorCount =
1693 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1694 stats->dot11RTSSuccessCount =
1695 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1696 }
1697 kfree(cmd);
1698
1699 return rc;
1700}
1701
1702/*
1703 * CMD_802_11_RADIO_CONTROL.
1704 */
1705struct mwl8k_cmd_802_11_radio_control {
1706 struct mwl8k_cmd_pkt header;
1707 __le16 action;
1708 __le16 control;
1709 __le16 radio_on;
1710} __attribute__((packed));
1711
c46563b7
LB		 1712static int
1713mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1714{
1715 struct mwl8k_priv *priv = hw->priv;
1716 struct mwl8k_cmd_802_11_radio_control *cmd;
1717 int rc;
1718
c46563b7 1719 if (enable == priv->radio_on && !force)
a66098da
LB		 1720 return 0;
1721
a66098da
LB		 1722 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1723 if (cmd == NULL)
1724 return -ENOMEM;
1725
1726 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1727 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1728 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1729 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1730 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1731
1732 rc = mwl8k_post_cmd(hw, &cmd->header);
1733 kfree(cmd);
1734
1735 if (!rc)
c46563b7 1736 priv->radio_on = enable;
a66098da
LB		 1737
1738 return rc;
1739}
1740
c46563b7
LB		 1741static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1742{
1743 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1744}
1745
1746static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1747{
1748 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1749}
1750
a66098da
LB		 1751static int
1752mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1753{
1754 struct mwl8k_priv *priv;
1755
1756 if (hw == NULL || hw->priv == NULL)
1757 return -EINVAL;
1758 priv = hw->priv;
1759
68ce3884 1760 priv->radio_short_preamble = short_preamble;
a66098da 1761
c46563b7 1762 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1763}
1764
1765/*
1766 * CMD_802_11_RF_TX_POWER.
1767 */
1768#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1769
1770struct mwl8k_cmd_802_11_rf_tx_power {
1771 struct mwl8k_cmd_pkt header;
1772 __le16 action;
1773 __le16 support_level;
1774 __le16 current_level;
1775 __le16 reserved;
1776 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1777} __attribute__((packed));
1778
1779static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1780{
1781 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1782 int rc;
1783
1784 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1785 if (cmd == NULL)
1786 return -ENOMEM;
1787
1788 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1789 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1790 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1791 cmd->support_level = cpu_to_le16(dBm);
1792
1793 rc = mwl8k_post_cmd(hw, &cmd->header);
1794 kfree(cmd);
1795
1796 return rc;
1797}
1798
1799/*
1800 * CMD_SET_PRE_SCAN.
1801 */
1802struct mwl8k_cmd_set_pre_scan {
1803 struct mwl8k_cmd_pkt header;
1804} __attribute__((packed));
1805
1806static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1807{
1808 struct mwl8k_cmd_set_pre_scan *cmd;
1809 int rc;
1810
1811 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1812 if (cmd == NULL)
1813 return -ENOMEM;
1814
1815 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1816 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1817
1818 rc = mwl8k_post_cmd(hw, &cmd->header);
1819 kfree(cmd);
1820
1821 return rc;
1822}
1823
1824/*
1825 * CMD_SET_POST_SCAN.
1826 */
1827struct mwl8k_cmd_set_post_scan {
1828 struct mwl8k_cmd_pkt header;
1829 __le32 isibss;
d89173f2 1830 __u8 bssid[ETH_ALEN];
a66098da
LB		 1831} __attribute__((packed));
1832
1833static int
ce9e2e1b 1834mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 1835{
1836 struct mwl8k_cmd_set_post_scan *cmd;
1837 int rc;
1838
1839 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1840 if (cmd == NULL)
1841 return -ENOMEM;
1842
1843 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1844 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1845 cmd->isibss = 0;
d89173f2 1846 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 1847
1848 rc = mwl8k_post_cmd(hw, &cmd->header);
1849 kfree(cmd);
1850
1851 return rc;
1852}
1853
1854/*
1855 * CMD_SET_RF_CHANNEL.
1856 */
1857struct mwl8k_cmd_set_rf_channel {
1858 struct mwl8k_cmd_pkt header;
1859 __le16 action;
1860 __u8 current_channel;
1861 __le32 channel_flags;
1862} __attribute__((packed));
1863
1864static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1865 struct ieee80211_channel *channel)
1866{
1867 struct mwl8k_cmd_set_rf_channel *cmd;
1868 int rc;
1869
1870 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1871 if (cmd == NULL)
1872 return -ENOMEM;
1873
1874 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1875 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1876 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1877 cmd->current_channel = channel->hw_value;
1878 if (channel->band == IEEE80211_BAND_2GHZ)
1879 cmd->channel_flags = cpu_to_le32(0x00000081);
1880 else
1881 cmd->channel_flags = cpu_to_le32(0x00000000);
1882
1883 rc = mwl8k_post_cmd(hw, &cmd->header);
1884 kfree(cmd);
1885
1886 return rc;
1887}
1888
1889/*
1890 * CMD_SET_SLOT.
1891 */
1892struct mwl8k_cmd_set_slot {
1893 struct mwl8k_cmd_pkt header;
1894 __le16 action;
1895 __u8 short_slot;
1896} __attribute__((packed));
1897
1898static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, int slot_time)
1899{
1900 struct mwl8k_cmd_set_slot *cmd;
1901 int rc;
1902
1903 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1904 if (cmd == NULL)
1905 return -ENOMEM;
1906
1907 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1908 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1909 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1910 cmd->short_slot = slot_time == MWL8K_SHORT_SLOTTIME ? 1 : 0;
1911
1912 rc = mwl8k_post_cmd(hw, &cmd->header);
1913 kfree(cmd);
1914
1915 return rc;
1916}
1917
1918/*
1919 * CMD_MIMO_CONFIG.
1920 */
1921struct mwl8k_cmd_mimo_config {
1922 struct mwl8k_cmd_pkt header;
1923 __le32 action;
1924 __u8 rx_antenna_map;
1925 __u8 tx_antenna_map;
1926} __attribute__((packed));
1927
1928static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1929{
1930 struct mwl8k_cmd_mimo_config *cmd;
1931 int rc;
1932
1933 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1934 if (cmd == NULL)
1935 return -ENOMEM;
1936
1937 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1938 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1939 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1940 cmd->rx_antenna_map = rx;
1941 cmd->tx_antenna_map = tx;
1942
1943 rc = mwl8k_post_cmd(hw, &cmd->header);
1944 kfree(cmd);
1945
1946 return rc;
1947}
1948
1949/*
1950 * CMD_ENABLE_SNIFFER.
1951 */
1952struct mwl8k_cmd_enable_sniffer {
1953 struct mwl8k_cmd_pkt header;
1954 __le32 action;
1955} __attribute__((packed));
1956
1957static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1958{
1959 struct mwl8k_cmd_enable_sniffer *cmd;
1960 int rc;
1961
1962 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1963 if (cmd == NULL)
1964 return -ENOMEM;
1965
1966 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1967 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 1968 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 1969
1970 rc = mwl8k_post_cmd(hw, &cmd->header);
1971 kfree(cmd);
1972
1973 return rc;
1974}
1975
1976/*
ce9e2e1b 1977 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 1978 */
1979struct mwl8k_cmd_set_rate_adapt_mode {
1980 struct mwl8k_cmd_pkt header;
1981 __le16 action;
1982 __le16 mode;
1983} __attribute__((packed));
1984
1985static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
1986{
1987 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
1988 int rc;
1989
1990 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1991 if (cmd == NULL)
1992 return -ENOMEM;
1993
1994 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
1995 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1996 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1997 cmd->mode = cpu_to_le16(mode);
1998
1999 rc = mwl8k_post_cmd(hw, &cmd->header);
2000 kfree(cmd);
2001
2002 return rc;
2003}
2004
2005/*
2006 * CMD_SET_WMM_MODE.
2007 */
2008struct mwl8k_cmd_set_wmm {
2009 struct mwl8k_cmd_pkt header;
2010 __le16 action;
2011} __attribute__((packed));
2012
2013static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2014{
2015 struct mwl8k_priv *priv = hw->priv;
2016 struct mwl8k_cmd_set_wmm *cmd;
2017 int rc;
2018
2019 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2020 if (cmd == NULL)
2021 return -ENOMEM;
2022
2023 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2024 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2025 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2026
2027 rc = mwl8k_post_cmd(hw, &cmd->header);
2028 kfree(cmd);
2029
2030 if (!rc)
0439b1f5 2031 priv->wmm_enabled = enable;
a66098da
LB		 2032
2033 return rc;
2034}
2035
2036/*
2037 * CMD_SET_RTS_THRESHOLD.
2038 */
2039struct mwl8k_cmd_rts_threshold {
2040 struct mwl8k_cmd_pkt header;
2041 __le16 action;
2042 __le16 threshold;
2043} __attribute__((packed));
2044
2045static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
2046 u16 action, u16 *threshold)
2047{
2048 struct mwl8k_cmd_rts_threshold *cmd;
2049 int rc;
2050
2051 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2052 if (cmd == NULL)
2053 return -ENOMEM;
2054
2055 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2056 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2057 cmd->action = cpu_to_le16(action);
2058 cmd->threshold = cpu_to_le16(*threshold);
2059
2060 rc = mwl8k_post_cmd(hw, &cmd->header);
2061 kfree(cmd);
2062
2063 return rc;
2064}
2065
2066/*
2067 * CMD_SET_EDCA_PARAMS.
2068 */
2069struct mwl8k_cmd_set_edca_params {
2070 struct mwl8k_cmd_pkt header;
2071
2072 /* See MWL8K_SET_EDCA_XXX below */
2073 __le16 action;
2074
2075 /* TX opportunity in units of 32 us */
2076 __le16 txop;
2077
2078 /* Log exponent of max contention period: 0...15*/
2079 __u8 log_cw_max;
2080
2081 /* Log exponent of min contention period: 0...15 */
2082 __u8 log_cw_min;
2083
2084 /* Adaptive interframe spacing in units of 32us */
2085 __u8 aifs;
2086
2087 /* TX queue to configure */
2088 __u8 txq;
2089} __attribute__((packed));
2090
a66098da
LB		 2091#define MWL8K_SET_EDCA_CW 0x01
2092#define MWL8K_SET_EDCA_TXOP 0x02
2093#define MWL8K_SET_EDCA_AIFS 0x04
2094
2095#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2096 MWL8K_SET_EDCA_TXOP | \
2097 MWL8K_SET_EDCA_AIFS)
2098
2099static int
2100mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2101 __u16 cw_min, __u16 cw_max,
2102 __u8 aifs, __u16 txop)
2103{
2104 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2105 int rc;
2106
2107 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2108 if (cmd == NULL)
2109 return -ENOMEM;
2110
a66098da
LB		 2111 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2112 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2113 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2114 cmd->txop = cpu_to_le16(txop);
ce9e2e1b
LB		 2115 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2116 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
a66098da
LB		 2117 cmd->aifs = aifs;
2118 cmd->txq = qnum;
2119
2120 rc = mwl8k_post_cmd(hw, &cmd->header);
2121 kfree(cmd);
2122
2123 return rc;
2124}
2125
2126/*
2127 * CMD_FINALIZE_JOIN.
2128 */
2129
2130/* FJ beacon buffer size is compiled into the firmware. */
2131#define MWL8K_FJ_BEACON_MAXLEN 128
2132
2133struct mwl8k_cmd_finalize_join {
2134 struct mwl8k_cmd_pkt header;
2135 __le32 sleep_interval; /* Number of beacon periods to sleep */
2136 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2137} __attribute__((packed));
2138
2139static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2140 __u16 framelen, __u16 dtim)
2141{
2142 struct mwl8k_cmd_finalize_join *cmd;
2143 struct ieee80211_mgmt *payload = frame;
2144 u16 hdrlen;
2145 u32 payload_len;
2146 int rc;
2147
2148 if (frame == NULL)
2149 return -EINVAL;
2150
2151 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2152 if (cmd == NULL)
2153 return -ENOMEM;
2154
2155 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2156 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2157 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2158
2159 hdrlen = ieee80211_hdrlen(payload->frame_control);
2160
2161 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2162
2163 /* XXX TBD Might just have to abort and return an error */
2164 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2165 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
2166 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2167 payload_len, MWL8K_FJ_BEACON_MAXLEN);
2168
ce9e2e1b
LB		 2169 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2170 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2171
2172 if (payload && payload_len)
2173 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2174
2175 rc = mwl8k_post_cmd(hw, &cmd->header);
2176 kfree(cmd);
2177 return rc;
2178}
2179
2180/*
2181 * CMD_UPDATE_STADB.
2182 */
2183struct mwl8k_cmd_update_sta_db {
2184 struct mwl8k_cmd_pkt header;
2185
2186 /* See STADB_ACTION_TYPE */
2187 __le32 action;
2188
2189 /* Peer MAC address */
d89173f2 2190 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2191
2192 __le32 reserved;
2193
2194 /* Peer info - valid during add/update. */
2195 struct peer_capability_info peer_info;
2196} __attribute__((packed));
2197
2198static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2199 struct ieee80211_vif *vif, __u32 action)
2200{
2201 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2202 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2203 struct mwl8k_cmd_update_sta_db *cmd;
2204 struct peer_capability_info *peer_info;
2205 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2206 int rc;
2207 __u8 count, *rates;
2208
2209 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2210 if (cmd == NULL)
2211 return -ENOMEM;
2212
2213 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2214 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2215
2216 cmd->action = cpu_to_le32(action);
2217 peer_info = &cmd->peer_info;
d89173f2 2218 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2219
2220 switch (action) {
2221 case MWL8K_STA_DB_ADD_ENTRY:
2222 case MWL8K_STA_DB_MODIFY_ENTRY:
2223 /* Build peer_info block */
2224 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2225 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2226 peer_info->interop = 1;
2227 peer_info->amsdu_enabled = 0;
2228
2229 rates = peer_info->legacy_rates;
ce9e2e1b 2230 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2231 rates[count] = bitrates[count].hw_value;
2232
2233 rc = mwl8k_post_cmd(hw, &cmd->header);
2234 if (rc == 0)
2235 mv_vif->peer_id = peer_info->station_id;
2236
2237 break;
2238
2239 case MWL8K_STA_DB_DEL_ENTRY:
2240 case MWL8K_STA_DB_FLUSH:
2241 default:
2242 rc = mwl8k_post_cmd(hw, &cmd->header);
2243 if (rc == 0)
2244 mv_vif->peer_id = 0;
2245 break;
2246 }
2247 kfree(cmd);
2248
2249 return rc;
2250}
2251
2252/*
2253 * CMD_SET_AID.
2254 */
a66098da
LB		 2255#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2256
2257#define MWL8K_FRAME_PROT_DISABLED 0x00
2258#define MWL8K_FRAME_PROT_11G 0x07
2259#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2260#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2261
2262struct mwl8k_cmd_update_set_aid {
2263 struct mwl8k_cmd_pkt header;
2264 __le16 aid;
2265
2266 /* AP's MAC address (BSSID) */
d89173f2 2267 __u8 bssid[ETH_ALEN];
a66098da
LB		 2268 __le16 protection_mode;
2269 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2270} __attribute__((packed));
2271
2272static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2273 struct ieee80211_vif *vif)
2274{
2275 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2276 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2277 struct mwl8k_cmd_update_set_aid *cmd;
2278 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2279 int count;
2280 u16 prot_mode;
2281 int rc;
2282
2283 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2284 if (cmd == NULL)
2285 return -ENOMEM;
2286
2287 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2288 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2289 cmd->aid = cpu_to_le16(info->aid);
2290
d89173f2 2291 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2292
a66098da
LB		 2293 if (info->use_cts_prot) {
2294 prot_mode = MWL8K_FRAME_PROT_11G;
2295 } else {
9ed6bcce 2296 switch (info->ht_operation_mode &
a66098da
LB		 2297 IEEE80211_HT_OP_MODE_PROTECTION) {
2298 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2299 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2300 break;
2301 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2302 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2303 break;
2304 default:
2305 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2306 break;
2307 }
2308 }
a66098da
LB		 2309 cmd->protection_mode = cpu_to_le16(prot_mode);
2310
2311 for (count = 0; count < mv_vif->legacy_nrates; count++)
2312 cmd->supp_rates[count] = bitrates[count].hw_value;
2313
2314 rc = mwl8k_post_cmd(hw, &cmd->header);
2315 kfree(cmd);
2316
2317 return rc;
2318}
2319
2320/*
2321 * CMD_SET_RATE.
2322 */
2323struct mwl8k_cmd_update_rateset {
2324 struct mwl8k_cmd_pkt header;
2325 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2326
2327 /* Bitmap for supported MCS codes. */
2328 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2329 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2330} __attribute__((packed));
2331
2332static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2333 struct ieee80211_vif *vif)
2334{
2335 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2336 struct mwl8k_cmd_update_rateset *cmd;
2337 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2338 int count;
2339 int rc;
2340
2341 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2342 if (cmd == NULL)
2343 return -ENOMEM;
2344
2345 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2346 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2347
2348 for (count = 0; count < mv_vif->legacy_nrates; count++)
2349 cmd->legacy_rates[count] = bitrates[count].hw_value;
2350
2351 rc = mwl8k_post_cmd(hw, &cmd->header);
2352 kfree(cmd);
2353
2354 return rc;
2355}
2356
2357/*
2358 * CMD_USE_FIXED_RATE.
2359 */
2360#define MWL8K_RATE_TABLE_SIZE 8
2361#define MWL8K_UCAST_RATE 0
a66098da
LB		 2362#define MWL8K_USE_AUTO_RATE 0x0002
2363
2364struct mwl8k_rate_entry {
2365 /* Set to 1 if HT rate, 0 if legacy. */
2366 __le32 is_ht_rate;
2367
2368 /* Set to 1 to use retry_count field. */
2369 __le32 enable_retry;
2370
2371 /* Specified legacy rate or MCS. */
2372 __le32 rate;
2373
2374 /* Number of allowed retries. */
2375 __le32 retry_count;
2376} __attribute__((packed));
2377
2378struct mwl8k_rate_table {
2379 /* 1 to allow specified rate and below */
2380 __le32 allow_rate_drop;
2381 __le32 num_rates;
2382 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2383} __attribute__((packed));
2384
2385struct mwl8k_cmd_use_fixed_rate {
2386 struct mwl8k_cmd_pkt header;
2387 __le32 action;
2388 struct mwl8k_rate_table rate_table;
2389
2390 /* Unicast, Broadcast or Multicast */
2391 __le32 rate_type;
2392 __le32 reserved1;
2393 __le32 reserved2;
2394} __attribute__((packed));
2395
2396static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2397 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2398{
2399 struct mwl8k_cmd_use_fixed_rate *cmd;
2400 int count;
2401 int rc;
2402
2403 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2404 if (cmd == NULL)
2405 return -ENOMEM;
2406
2407 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2408 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2409
2410 cmd->action = cpu_to_le32(action);
2411 cmd->rate_type = cpu_to_le32(rate_type);
2412
2413 if (rate_table != NULL) {
2414 /* Copy over each field manually so
2415 * that bitflipping can be done
2416 */
2417 cmd->rate_table.allow_rate_drop =
2418 cpu_to_le32(rate_table->allow_rate_drop);
2419 cmd->rate_table.num_rates =
2420 cpu_to_le32(rate_table->num_rates);
2421
2422 for (count = 0; count < rate_table->num_rates; count++) {
2423 struct mwl8k_rate_entry *dst =
2424 &cmd->rate_table.rate_entry[count];
2425 struct mwl8k_rate_entry *src =
2426 &rate_table->rate_entry[count];
2427
2428 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2429 dst->enable_retry = cpu_to_le32(src->enable_retry);
2430 dst->rate = cpu_to_le32(src->rate);
2431 dst->retry_count = cpu_to_le32(src->retry_count);
2432 }
2433 }
2434
2435 rc = mwl8k_post_cmd(hw, &cmd->header);
2436 kfree(cmd);
2437
2438 return rc;
2439}
2440
2441
2442/*
2443 * Interrupt handling.
2444 */
2445static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2446{
2447 struct ieee80211_hw *hw = dev_id;
2448 struct mwl8k_priv *priv = hw->priv;
2449 u32 status;
2450
2451 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2452 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2453
a66098da
LB		 2454 if (!status)
2455 return IRQ_NONE;
2456
2457 if (status & MWL8K_A2H_INT_TX_DONE)
2458 tasklet_schedule(&priv->tx_reclaim_task);
2459
2460 if (status & MWL8K_A2H_INT_RX_READY) {
2461 while (rxq_process(hw, 0, 1))
2462 rxq_refill(hw, 0, 1);
2463 }
2464
2465 if (status & MWL8K_A2H_INT_OPC_DONE) {
2466 if (priv->hostcmd_wait != NULL) {
2467 complete(priv->hostcmd_wait);
2468 priv->hostcmd_wait = NULL;
2469 }
2470 }
2471
2472 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
2473 if (!priv->inconfig &&
c46563b7 2474 priv->radio_on &&
a66098da
LB		 2475 mwl8k_txq_busy(priv))
2476 mwl8k_tx_start(priv);
2477 }
2478
2479 return IRQ_HANDLED;
2480}
2481
2482
2483/*
2484 * Core driver operations.
2485 */
2486static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2487{
2488 struct mwl8k_priv *priv = hw->priv;
2489 int index = skb_get_queue_mapping(skb);
2490 int rc;
2491
2492 if (priv->current_channel == NULL) {
2493 printk(KERN_DEBUG "%s: dropped TX frame since radio "
2494 "disabled\n", priv->name);
2495 dev_kfree_skb(skb);
2496 return NETDEV_TX_OK;
2497 }
2498
2499 rc = mwl8k_txq_xmit(hw, index, skb);
2500
2501 return rc;
2502}
2503
2504struct mwl8k_work_struct {
2505 /* Initialized by mwl8k_queue_work(). */
2506 struct work_struct wt;
2507
2508 /* Required field passed in to mwl8k_queue_work(). */
2509 struct ieee80211_hw *hw;
2510
2511 /* Required field passed in to mwl8k_queue_work(). */
2512 int (*wfunc)(struct work_struct *w);
2513
2514 /* Initialized by mwl8k_queue_work(). */
2515 struct completion *cmd_wait;
2516
2517 /* Result code. */
2518 int rc;
2519
2520 /*
2521 * Optional field. Refer to explanation of MWL8K_WQ_XXX_XXX
2522 * flags for explanation. Defaults to MWL8K_WQ_DEFAULT_OPTIONS.
2523 */
2524 u32 options;
2525
2526 /* Optional field. Defaults to MWL8K_CONFIG_TIMEOUT_MS. */
2527 unsigned long timeout_ms;
2528
2529 /* Optional field. Defaults to MWL8K_WQ_TXWAIT_ATTEMPTS. */
2530 u32 txwait_attempts;
2531
2532 /* Optional field. Defaults to MWL8K_TXWAIT_MS. */
2533 u32 tx_timeout_ms;
2534 u32 step;
2535};
2536
2537/* Flags controlling behavior of config queue requests */
2538
2539/* Caller spins while waiting for completion. */
2540#define MWL8K_WQ_SPIN 0x00000001
2541
2542/* Wait for TX queues to empty before proceeding with configuration. */
2543#define MWL8K_WQ_TX_WAIT_EMPTY 0x00000002
2544
2545/* Queue request and return immediately. */
2546#define MWL8K_WQ_POST_REQUEST 0x00000004
2547
2548/*
2549 * Caller sleeps and waits for task complete notification.
2550 * Do not use in atomic context.
2551 */
2552#define MWL8K_WQ_SLEEP 0x00000008
2553
2554/* Free work struct when task is done. */
2555#define MWL8K_WQ_FREE_WORKSTRUCT 0x00000010
2556
2557/*
2558 * Config request is queued and returns to caller imediately. Use
2559 * this in atomic context. Work struct is freed by mwl8k_queue_work()
2560 * when this flag is set.
2561 */
2562#define MWL8K_WQ_QUEUE_ONLY (MWL8K_WQ_POST_REQUEST | \
2563 MWL8K_WQ_FREE_WORKSTRUCT)
2564
2565/* Default work queue behavior is to sleep and wait for tx completion. */
2566#define MWL8K_WQ_DEFAULT_OPTIONS (MWL8K_WQ_SLEEP | MWL8K_WQ_TX_WAIT_EMPTY)
2567
2568/*
2569 * Default config request timeout. Add adjustments to make sure the
2570 * config thread waits long enough for both tx wait and cmd wait before
2571 * timing out.
2572 */
2573
2574/* Time to wait for all TXQs to drain. TX Doorbell is pressed each time. */
2575#define MWL8K_TXWAIT_TIMEOUT_MS 1000
2576
2577/* Default number of TX wait attempts. */
2578#define MWL8K_WQ_TXWAIT_ATTEMPTS 4
2579
2580/* Total time to wait for TXQ to drain. */
2581#define MWL8K_TXWAIT_MS (MWL8K_TXWAIT_TIMEOUT_MS * \
2582 MWL8K_WQ_TXWAIT_ATTEMPTS)
2583
2584/* Scheduling slop. */
2585#define MWL8K_OS_SCHEDULE_OVERHEAD_MS 200
2586
2587#define MWL8K_CONFIG_TIMEOUT_MS (MWL8K_CMD_TIMEOUT_MS + \
2588 MWL8K_TXWAIT_MS + \
2589 MWL8K_OS_SCHEDULE_OVERHEAD_MS)
2590
2591static void mwl8k_config_thread(struct work_struct *wt)
2592{
2593 struct mwl8k_work_struct *worker = (struct mwl8k_work_struct *)wt;
2594 struct ieee80211_hw *hw = worker->hw;
2595 struct mwl8k_priv *priv = hw->priv;
2596 int rc = 0;
2597
2598 spin_lock_irq(&priv->tx_lock);
2599 priv->inconfig = true;
2600 spin_unlock_irq(&priv->tx_lock);
2601
2602 ieee80211_stop_queues(hw);
2603
2604 /*
2605 * Wait for host queues to drain before doing PHY
2606 * reconfiguration. This avoids interrupting any in-flight
2607 * DMA transfers to the hardware.
2608 */
2609 if (worker->options & MWL8K_WQ_TX_WAIT_EMPTY) {
2610 u32 timeout;
2611 u32 time_remaining;
2612 u32 iter;
2613 u32 tx_wait_attempts = worker->txwait_attempts;
2614
2615 time_remaining = worker->tx_timeout_ms;
2616 if (!tx_wait_attempts)
2617 tx_wait_attempts = 1;
2618
2619 timeout = worker->tx_timeout_ms/tx_wait_attempts;
2620 if (!timeout)
2621 timeout = 1;
2622
2623 iter = tx_wait_attempts;
2624 do {
2625 int wait_time;
2626
2627 if (time_remaining > timeout) {
2628 time_remaining -= timeout;
2629 wait_time = timeout;
2630 } else
2631 wait_time = time_remaining;
2632
2633 if (!wait_time)
2634 wait_time = 1;
2635
2636 rc = mwl8k_tx_wait_empty(hw, wait_time);
2637 if (rc)
2638 printk(KERN_ERR "%s() txwait timeout=%ums "
2639 "Retry:%u/%u\n", __func__, timeout,
2640 tx_wait_attempts - iter + 1,
2641 tx_wait_attempts);
2642
2643 } while (rc && --iter);
2644
2645 rc = iter ? 0 : -ETIMEDOUT;
2646 }
2647 if (!rc)
2648 rc = worker->wfunc(wt);
2649
2650 spin_lock_irq(&priv->tx_lock);
2651 priv->inconfig = false;
c46563b7 2652 if (priv->pending_tx_pkts && priv->radio_on)
a66098da
LB		 2653 mwl8k_tx_start(priv);
2654 spin_unlock_irq(&priv->tx_lock);
2655 ieee80211_wake_queues(hw);
2656
2657 worker->rc = rc;
2658 if (worker->options & MWL8K_WQ_SLEEP)
2659 complete(worker->cmd_wait);
2660
2661 if (worker->options & MWL8K_WQ_FREE_WORKSTRUCT)
2662 kfree(wt);
2663}
2664
2665static int mwl8k_queue_work(struct ieee80211_hw *hw,
2666 struct mwl8k_work_struct *worker,
2667 struct workqueue_struct *wqueue,
2668 int (*wfunc)(struct work_struct *w))
2669{
2670 unsigned long timeout = 0;
2671 int rc = 0;
2672
2673 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2674
2675 if (!worker->timeout_ms)
2676 worker->timeout_ms = MWL8K_CONFIG_TIMEOUT_MS;
2677
2678 if (!worker->options)
2679 worker->options = MWL8K_WQ_DEFAULT_OPTIONS;
2680
2681 if (!worker->txwait_attempts)
2682 worker->txwait_attempts = MWL8K_WQ_TXWAIT_ATTEMPTS;
2683
2684 if (!worker->tx_timeout_ms)
2685 worker->tx_timeout_ms = MWL8K_TXWAIT_MS;
2686
2687 worker->hw = hw;
2688 worker->cmd_wait = &cmd_wait;
2689 worker->rc = 1;
2690 worker->wfunc = wfunc;
2691
2692 INIT_WORK(&worker->wt, mwl8k_config_thread);
2693 queue_work(wqueue, &worker->wt);
2694
2695 if (worker->options & MWL8K_WQ_POST_REQUEST) {
2696 rc = 0;
2697 } else {
2698 if (worker->options & MWL8K_WQ_SPIN) {
2699 timeout = worker->timeout_ms;
2700 while (timeout && (worker->rc > 0)) {
2701 mdelay(1);
2702 timeout--;
2703 }
2704 } else if (worker->options & MWL8K_WQ_SLEEP)
2705 timeout = wait_for_completion_timeout(&cmd_wait,
2706 msecs_to_jiffies(worker->timeout_ms));
2707
2708 if (timeout)
2709 rc = worker->rc;
2710 else {
2711 cancel_work_sync(&worker->wt);
2712 rc = -ETIMEDOUT;
2713 }
2714 }
2715
2716 return rc;
2717}
2718
2719struct mwl8k_start_worker {
2720 struct mwl8k_work_struct header;
2721};
2722
2723static int mwl8k_start_wt(struct work_struct *wt)
2724{
2725 struct mwl8k_start_worker *worker = (struct mwl8k_start_worker *)wt;
2726 struct ieee80211_hw *hw = worker->header.hw;
2727 struct mwl8k_priv *priv = hw->priv;
2728 int rc = 0;
2729
2730 if (priv->vif != NULL) {
2731 rc = -EIO;
2732 goto mwl8k_start_exit;
2733 }
2734
2735 /* Turn on radio */
c46563b7 2736 if (mwl8k_cmd_802_11_radio_enable(hw)) {
a66098da
LB		 2737 rc = -EIO;
2738 goto mwl8k_start_exit;
2739 }
2740
2741 /* Purge TX/RX HW queues */
2742 if (mwl8k_cmd_set_pre_scan(hw)) {
2743 rc = -EIO;
2744 goto mwl8k_start_exit;
2745 }
2746
2747 if (mwl8k_cmd_set_post_scan(hw, "\x00\x00\x00\x00\x00\x00")) {
2748 rc = -EIO;
2749 goto mwl8k_start_exit;
2750 }
2751
2752 /* Enable firmware rate adaptation */
2753 if (mwl8k_cmd_setrateadaptmode(hw, 0)) {
2754 rc = -EIO;
2755 goto mwl8k_start_exit;
2756 }
2757
2758 /* Disable WMM. WMM gets enabled when stack sends WMM parms */
0439b1f5 2759 if (mwl8k_set_wmm(hw, 0)) {
a66098da
LB		 2760 rc = -EIO;
2761 goto mwl8k_start_exit;
2762 }
2763
2764 /* Disable sniffer mode */
2765 if (mwl8k_enable_sniffer(hw, 0))
2766 rc = -EIO;
2767
2768mwl8k_start_exit:
2769 return rc;
2770}
2771
2772static int mwl8k_start(struct ieee80211_hw *hw)
2773{
2774 struct mwl8k_start_worker *worker;
2775 struct mwl8k_priv *priv = hw->priv;
2776 int rc;
2777
2778 /* Enable tx reclaim tasklet */
2779 tasklet_enable(&priv->tx_reclaim_task);
2780
2781 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2782 IRQF_SHARED, MWL8K_NAME, hw);
2783 if (rc) {
2784 printk(KERN_ERR "%s: failed to register IRQ handler\n",
2785 priv->name);
2786 rc = -EIO;
2787 goto mwl8k_start_disable_tasklet;
2788 }
2789
2790 /* Enable interrupts */
c23b5a69 2791 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2792
2793 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2794 if (worker == NULL) {
2795 rc = -ENOMEM;
2796 goto mwl8k_start_disable_irq;
2797 }
2798
2799 rc = mwl8k_queue_work(hw, &worker->header,
2800 priv->config_wq, mwl8k_start_wt);
2801 kfree(worker);
2802 if (!rc)
2803 return rc;
2804
2805 if (rc == -ETIMEDOUT)
2806 printk(KERN_ERR "%s() timed out\n", __func__);
2807
2808 rc = -EIO;
2809
2810mwl8k_start_disable_irq:
2811 spin_lock_irq(&priv->tx_lock);
2812 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2813 spin_unlock_irq(&priv->tx_lock);
2814 free_irq(priv->pdev->irq, hw);
2815
2816mwl8k_start_disable_tasklet:
2817 tasklet_disable(&priv->tx_reclaim_task);
2818
2819 return rc;
2820}
2821
2822struct mwl8k_stop_worker {
2823 struct mwl8k_work_struct header;
2824};
2825
2826static int mwl8k_stop_wt(struct work_struct *wt)
2827{
2828 struct mwl8k_stop_worker *worker = (struct mwl8k_stop_worker *)wt;
2829 struct ieee80211_hw *hw = worker->header.hw;
a66098da 2830
c46563b7 2831 return mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2832}
2833
2834static void mwl8k_stop(struct ieee80211_hw *hw)
2835{
2836 int rc;
2837 struct mwl8k_stop_worker *worker;
2838 struct mwl8k_priv *priv = hw->priv;
2839 int i;
2840
2841 if (priv->vif != NULL)
2842 return;
2843
2844 ieee80211_stop_queues(hw);
2845
2846 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2847 if (worker == NULL)
2848 return;
2849
2850 rc = mwl8k_queue_work(hw, &worker->header,
2851 priv->config_wq, mwl8k_stop_wt);
2852 kfree(worker);
2853 if (rc == -ETIMEDOUT)
2854 printk(KERN_ERR "%s() timed out\n", __func__);
2855
2856 /* Disable interrupts */
2857 spin_lock_irq(&priv->tx_lock);
2858 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2859 spin_unlock_irq(&priv->tx_lock);
2860 free_irq(priv->pdev->irq, hw);
2861
2862 /* Stop finalize join worker */
2863 cancel_work_sync(&priv->finalize_join_worker);
2864 if (priv->beacon_skb != NULL)
2865 dev_kfree_skb(priv->beacon_skb);
2866
2867 /* Stop tx reclaim tasklet */
2868 tasklet_disable(&priv->tx_reclaim_task);
2869
2870 /* Stop config thread */
2871 flush_workqueue(priv->config_wq);
2872
2873 /* Return all skbs to mac80211 */
2874 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2875 mwl8k_txq_reclaim(hw, i, 1);
2876}
2877
2878static int mwl8k_add_interface(struct ieee80211_hw *hw,
2879 struct ieee80211_if_init_conf *conf)
2880{
2881 struct mwl8k_priv *priv = hw->priv;
2882 struct mwl8k_vif *mwl8k_vif;
2883
2884 /*
2885 * We only support one active interface at a time.
2886 */
2887 if (priv->vif != NULL)
2888 return -EBUSY;
2889
2890 /*
2891 * We only support managed interfaces for now.
2892 */
2893 if (conf->type != NL80211_IFTYPE_STATION &&
2894 conf->type != NL80211_IFTYPE_MONITOR)
2895 return -EINVAL;
2896
2897 /* Clean out driver private area */
2898 mwl8k_vif = MWL8K_VIF(conf->vif);
2899 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2900
2901 /* Save the mac address */
d89173f2 2902 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2903
2904 /* Back pointer to parent config block */
2905 mwl8k_vif->priv = priv;
2906
2907 /* Setup initial PHY parameters */
ce9e2e1b 2908 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2909 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2910 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2911
2912 /* Set Initial sequence number to zero */
2913 mwl8k_vif->seqno = 0;
2914
2915 priv->vif = conf->vif;
2916 priv->current_channel = NULL;
2917
2918 return 0;
2919}
2920
2921static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2922 struct ieee80211_if_init_conf *conf)
2923{
2924 struct mwl8k_priv *priv = hw->priv;
2925
2926 if (priv->vif == NULL)
2927 return;
2928
2929 priv->vif = NULL;
2930}
2931
2932struct mwl8k_config_worker {
2933 struct mwl8k_work_struct header;
2934 u32 changed;
2935};
2936
2937static int mwl8k_config_wt(struct work_struct *wt)
2938{
2939 struct mwl8k_config_worker *worker =
2940 (struct mwl8k_config_worker *)wt;
2941 struct ieee80211_hw *hw = worker->header.hw;
2942 struct ieee80211_conf *conf = &hw->conf;
2943 struct mwl8k_priv *priv = hw->priv;
2944 int rc = 0;
2945
c46563b7 2946 if (mwl8k_cmd_802_11_radio_enable(hw)) {
a66098da
LB		 2947 rc = -EINVAL;
2948 goto mwl8k_config_exit;
2949 }
2950
2951 priv->current_channel = conf->channel;
2952
2953 if (mwl8k_cmd_set_rf_channel(hw, conf->channel)) {
2954 rc = -EINVAL;
2955 goto mwl8k_config_exit;
2956 }
2957
2958 if (conf->power_level > 18)
2959 conf->power_level = 18;
2960 if (mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level)) {
2961 rc = -EINVAL;
2962 goto mwl8k_config_exit;
2963 }
2964
2965 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2966 rc = -EINVAL;
2967
2968mwl8k_config_exit:
2969 return rc;
2970}
2971
2972static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
2973{
2974 int rc = 0;
2975 struct mwl8k_config_worker *worker;
2976 struct mwl8k_priv *priv = hw->priv;
2977
2978 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
2979 if (worker == NULL)
2980 return -ENOMEM;
2981
2982 worker->changed = changed;
2983 rc = mwl8k_queue_work(hw, &worker->header,
2984 priv->config_wq, mwl8k_config_wt);
2985 if (rc == -ETIMEDOUT) {
2986 printk(KERN_ERR "%s() timed out.\n", __func__);
2987 rc = -EINVAL;
2988 }
2989
2990 kfree(worker);
2991
2992 /*
2993 * mac80211 will crash on anything other than -EINVAL on
2994 * error. Looks like wireless extensions which calls mac80211
2995 * may be the actual culprit...
2996 */
2997 return rc ? -EINVAL : 0;
2998}
2999
a66098da
LB		 3000struct mwl8k_bss_info_changed_worker {
3001 struct mwl8k_work_struct header;
3002 struct ieee80211_vif *vif;
3003 struct ieee80211_bss_conf *info;
3004 u32 changed;
3005};
3006
3007static int mwl8k_bss_info_changed_wt(struct work_struct *wt)
3008{
3009 struct mwl8k_bss_info_changed_worker *worker =
3010 (struct mwl8k_bss_info_changed_worker *)wt;
3011 struct ieee80211_hw *hw = worker->header.hw;
3012 struct ieee80211_vif *vif = worker->vif;
3013 struct ieee80211_bss_conf *info = worker->info;
3014 u32 changed;
3015 int rc;
3016
3017 struct mwl8k_priv *priv = hw->priv;
3018 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3019
3020 changed = worker->changed;
3021 priv->capture_beacon = false;
3022
3023 if (info->assoc) {
3024 memcpy(&mwl8k_vif->bss_info, info,
3025 sizeof(struct ieee80211_bss_conf));
3026
3027 /* Install rates */
3028 if (mwl8k_update_rateset(hw, vif))
3029 goto mwl8k_bss_info_changed_exit;
3030
3031 /* Turn on rate adaptation */
3032 if (mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3033 MWL8K_UCAST_RATE, NULL))
3034 goto mwl8k_bss_info_changed_exit;
3035
3036 /* Set radio preamble */
68ce3884 3037 if (mwl8k_set_radio_preamble(hw, info->use_short_preamble))
a66098da
LB		 3038 goto mwl8k_bss_info_changed_exit;
3039
3040 /* Set slot time */
3041 if (mwl8k_cmd_set_slot(hw, info->use_short_slot ?
3042 MWL8K_SHORT_SLOTTIME : MWL8K_LONG_SLOTTIME))
3043 goto mwl8k_bss_info_changed_exit;
3044
3045 /* Update peer rate info */
3046 if (mwl8k_cmd_update_sta_db(hw, vif,
3047 MWL8K_STA_DB_MODIFY_ENTRY))
3048 goto mwl8k_bss_info_changed_exit;
3049
3050 /* Set AID */
3051 if (mwl8k_cmd_set_aid(hw, vif))
3052 goto mwl8k_bss_info_changed_exit;
3053
3054 /*
3055 * Finalize the join. Tell rx handler to process
3056 * next beacon from our BSSID.
3057 */
d89173f2 3058 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 3059 priv->capture_beacon = true;
3060 } else {
3061 mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
3062 memset(&mwl8k_vif->bss_info, 0,
3063 sizeof(struct ieee80211_bss_conf));
d89173f2 3064 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 3065 }
3066
3067mwl8k_bss_info_changed_exit:
3068 rc = 0;
3069 return rc;
3070}
3071
3072static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3073 struct ieee80211_vif *vif,
3074 struct ieee80211_bss_conf *info,
3075 u32 changed)
3076{
3077 struct mwl8k_bss_info_changed_worker *worker;
3078 struct mwl8k_priv *priv = hw->priv;
2d0ddec5 3079 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
a66098da
LB		 3080 int rc;
3081
2d0ddec5 3082 if (changed & BSS_CHANGED_BSSID)
d89173f2 3083 memcpy(mv_vif->bssid, info->bssid, ETH_ALEN);
2d0ddec5 3084
a66098da
LB		 3085 if ((changed & BSS_CHANGED_ASSOC) == 0)
3086 return;
3087
3088 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3089 if (worker == NULL)
3090 return;
3091
3092 worker->vif = vif;
3093 worker->info = info;
3094 worker->changed = changed;
3095 rc = mwl8k_queue_work(hw, &worker->header,
3096 priv->config_wq,
3097 mwl8k_bss_info_changed_wt);
3098 kfree(worker);
3099 if (rc == -ETIMEDOUT)
3100 printk(KERN_ERR "%s() timed out\n", __func__);
3101}
3102
3103struct mwl8k_configure_filter_worker {
3104 struct mwl8k_work_struct header;
3105 unsigned int changed_flags;
3106 unsigned int *total_flags;
3107 int mc_count;
3108 struct dev_addr_list *mclist;
3109};
3110
3111#define MWL8K_SUPPORTED_IF_FLAGS FIF_BCN_PRBRESP_PROMISC
3112
3113static int mwl8k_configure_filter_wt(struct work_struct *wt)
3114{
3115 struct mwl8k_configure_filter_worker *worker =
3116 (struct mwl8k_configure_filter_worker *)wt;
3117
3118 struct ieee80211_hw *hw = worker->header.hw;
3119 unsigned int changed_flags = worker->changed_flags;
3120 unsigned int *total_flags = worker->total_flags;
3121 int mc_count = worker->mc_count;
3122 struct dev_addr_list *mclist = worker->mclist;
3123
3124 struct mwl8k_priv *priv = hw->priv;
a66098da
LB		 3125 int rc = 0;
3126
3127 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
3128 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
3129 rc = mwl8k_cmd_set_pre_scan(hw);
3130 else {
a94cc97e
LB		 3131 u8 *bssid;
3132
3133 bssid = "\x00\x00\x00\x00\x00\x00";
3134 if (priv->vif != NULL)
3135 bssid = MWL8K_VIF(priv->vif)->bssid;
3136
3137 rc = mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3138 }
3139 }
3140
3141 if (rc)
3142 goto mwl8k_configure_filter_exit;
3143 if (mc_count) {
ce9e2e1b
LB		 3144 if (mc_count > priv->num_mcaddrs)
3145 mc_count = priv->num_mcaddrs;
3146
a66098da
LB		 3147 rc = mwl8k_cmd_mac_multicast_adr(hw, mc_count, mclist);
3148 if (rc)
3149 printk(KERN_ERR
3150 "%s()Error setting multicast addresses\n",
3151 __func__);
3152 }
3153
3154mwl8k_configure_filter_exit:
3155 return rc;
3156}
3157
3ac64bee
JB		 3158static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3159 int mc_count, struct dev_addr_list *mclist)
3160{
3161 struct mwl8k_configure_filter_worker *worker;
3162
3163 worker = kzalloc(sizeof(*worker), GFP_ATOMIC);
3164
3165 if (!worker)
3166 return 0;
3167
3168 /*
3169 * XXX: This is _HORRIBLY_ broken!!
3170 *
3171 * No locking, the mclist pointer might be invalid as soon as this
3172 * function returns, something in the list might be invalidated
3173 * once we get to the worker, etc...
3174 */
3175 worker->mc_count = mc_count;
3176 worker->mclist = mclist;
3177
3178 return (u64)worker;
3179}
3180
a66098da
LB		 3181static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3182 unsigned int changed_flags,
3183 unsigned int *total_flags,
3ac64bee 3184 u64 multicast)
a66098da
LB		 3185{
3186
3ac64bee 3187 struct mwl8k_configure_filter_worker *worker = (void *)multicast;
a66098da
LB		 3188 struct mwl8k_priv *priv = hw->priv;
3189
3190 /* Clear unsupported feature flags */
3191 *total_flags &= MWL8K_SUPPORTED_IF_FLAGS;
3192
3ac64bee 3193 if (!(changed_flags & MWL8K_SUPPORTED_IF_FLAGS))
a66098da
LB		 3194 return;
3195
a66098da
LB		 3196 if (worker == NULL)
3197 return;
3198
3199 worker->header.options = MWL8K_WQ_QUEUE_ONLY | MWL8K_WQ_TX_WAIT_EMPTY;
3200 worker->changed_flags = changed_flags;
3201 worker->total_flags = total_flags;
a66098da
LB		 3202
3203 mwl8k_queue_work(hw, &worker->header, priv->config_wq,
3204 mwl8k_configure_filter_wt);
3205}
3206
3207struct mwl8k_set_rts_threshold_worker {
3208 struct mwl8k_work_struct header;
3209 u32 value;
3210};
3211
3212static int mwl8k_set_rts_threshold_wt(struct work_struct *wt)
3213{
3214 struct mwl8k_set_rts_threshold_worker *worker =
3215 (struct mwl8k_set_rts_threshold_worker *)wt;
3216
3217 struct ieee80211_hw *hw = worker->header.hw;
3218 u16 threshold = (u16)(worker->value);
3219 int rc;
3220
3221 rc = mwl8k_rts_threshold(hw, MWL8K_CMD_SET, &threshold);
3222
3223 return rc;
3224}
3225
3226static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3227{
3228 int rc;
3229 struct mwl8k_set_rts_threshold_worker *worker;
3230 struct mwl8k_priv *priv = hw->priv;
3231
3232 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3233 if (worker == NULL)
3234 return -ENOMEM;
3235
3236 worker->value = value;
3237
3238 rc = mwl8k_queue_work(hw, &worker->header,
3239 priv->config_wq,
3240 mwl8k_set_rts_threshold_wt);
3241 kfree(worker);
3242
3243 if (rc == -ETIMEDOUT) {
3244 printk(KERN_ERR "%s() timed out\n", __func__);
3245 rc = -EINVAL;
3246 }
3247
3248 return rc;
3249}
3250
3251struct mwl8k_conf_tx_worker {
3252 struct mwl8k_work_struct header;
3253 u16 queue;
3254 const struct ieee80211_tx_queue_params *params;
3255};
3256
3257static int mwl8k_conf_tx_wt(struct work_struct *wt)
3258{
3259 struct mwl8k_conf_tx_worker *worker =
3260 (struct mwl8k_conf_tx_worker *)wt;
3261
3262 struct ieee80211_hw *hw = worker->header.hw;
3263 u16 queue = worker->queue;
3264 const struct ieee80211_tx_queue_params *params = worker->params;
3265
3266 struct mwl8k_priv *priv = hw->priv;
3267 int rc = 0;
3268
0439b1f5
LB		 3269 if (!priv->wmm_enabled) {
3270 if (mwl8k_set_wmm(hw, 1)) {
a66098da
LB		 3271 rc = -EINVAL;
3272 goto mwl8k_conf_tx_exit;
0439b1f5 3273 }
a66098da
LB		 3274 }
3275
3276 if (mwl8k_set_edca_params(hw, GET_TXQ(queue), params->cw_min,
3277 params->cw_max, params->aifs, params->txop))
3278 rc = -EINVAL;
3279mwl8k_conf_tx_exit:
3280 return rc;
3281}
3282
3283static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3284 const struct ieee80211_tx_queue_params *params)
3285{
3286 int rc;
3287 struct mwl8k_conf_tx_worker *worker;
3288 struct mwl8k_priv *priv = hw->priv;
3289
3290 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3291 if (worker == NULL)
3292 return -ENOMEM;
3293
3294 worker->queue = queue;
3295 worker->params = params;
3296 rc = mwl8k_queue_work(hw, &worker->header,
3297 priv->config_wq, mwl8k_conf_tx_wt);
3298 kfree(worker);
3299 if (rc == -ETIMEDOUT) {
3300 printk(KERN_ERR "%s() timed out\n", __func__);
3301 rc = -EINVAL;
3302 }
3303 return rc;
3304}
3305
3306static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3307 struct ieee80211_tx_queue_stats *stats)
3308{
3309 struct mwl8k_priv *priv = hw->priv;
3310 struct mwl8k_tx_queue *txq;
3311 int index;
3312
3313 spin_lock_bh(&priv->tx_lock);
3314 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3315 txq = priv->txq + index;
3316 memcpy(&stats[index], &txq->tx_stats,
3317 sizeof(struct ieee80211_tx_queue_stats));
3318 }
3319 spin_unlock_bh(&priv->tx_lock);
3320 return 0;
3321}
3322
3323struct mwl8k_get_stats_worker {
3324 struct mwl8k_work_struct header;
3325 struct ieee80211_low_level_stats *stats;
3326};
3327
3328static int mwl8k_get_stats_wt(struct work_struct *wt)
3329{
3330 struct mwl8k_get_stats_worker *worker =
3331 (struct mwl8k_get_stats_worker *)wt;
3332
3333 return mwl8k_cmd_802_11_get_stat(worker->header.hw, worker->stats);
3334}
3335
3336static int mwl8k_get_stats(struct ieee80211_hw *hw,
3337 struct ieee80211_low_level_stats *stats)
3338{
3339 int rc;
3340 struct mwl8k_get_stats_worker *worker;
3341 struct mwl8k_priv *priv = hw->priv;
3342
3343 worker = kzalloc(sizeof(*worker), GFP_KERNEL);
3344 if (worker == NULL)
3345 return -ENOMEM;
3346
3347 worker->stats = stats;
3348 rc = mwl8k_queue_work(hw, &worker->header,
3349 priv->config_wq, mwl8k_get_stats_wt);
3350
3351 kfree(worker);
3352 if (rc == -ETIMEDOUT) {
3353 printk(KERN_ERR "%s() timed out\n", __func__);
3354 rc = -EINVAL;
3355 }
3356
3357 return rc;
3358}
3359
3360static const struct ieee80211_ops mwl8k_ops = {
3361 .tx = mwl8k_tx,
3362 .start = mwl8k_start,
3363 .stop = mwl8k_stop,
3364 .add_interface = mwl8k_add_interface,
3365 .remove_interface = mwl8k_remove_interface,
3366 .config = mwl8k_config,
a66098da 3367 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3368 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3369 .configure_filter = mwl8k_configure_filter,
3370 .set_rts_threshold = mwl8k_set_rts_threshold,
3371 .conf_tx = mwl8k_conf_tx,
3372 .get_tx_stats = mwl8k_get_tx_stats,
3373 .get_stats = mwl8k_get_stats,
3374};
3375
3376static void mwl8k_tx_reclaim_handler(unsigned long data)
3377{
3378 int i;
3379 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3380 struct mwl8k_priv *priv = hw->priv;
3381
3382 spin_lock_bh(&priv->tx_lock);
3383 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3384 mwl8k_txq_reclaim(hw, i, 0);
3385
ce9e2e1b
LB		 3386 if (priv->tx_wait != NULL && mwl8k_txq_busy(priv) == 0) {
3387 complete(priv->tx_wait);
3388 priv->tx_wait = NULL;
a66098da
LB		 3389 }
3390 spin_unlock_bh(&priv->tx_lock);
3391}
3392
3393static void mwl8k_finalize_join_worker(struct work_struct *work)
3394{
3395 struct mwl8k_priv *priv =
3396 container_of(work, struct mwl8k_priv, finalize_join_worker);
3397 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3398 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3399
3400 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3401 dev_kfree_skb(skb);
3402
3403 priv->beacon_skb = NULL;
3404}
3405
3406static int __devinit mwl8k_probe(struct pci_dev *pdev,
3407 const struct pci_device_id *id)
3408{
3409 struct ieee80211_hw *hw;
3410 struct mwl8k_priv *priv;
a66098da
LB		 3411 int rc;
3412 int i;
3413 u8 *fw;
3414
3415 rc = pci_enable_device(pdev);
3416 if (rc) {
3417 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3418 MWL8K_NAME);
3419 return rc;
3420 }
3421
3422 rc = pci_request_regions(pdev, MWL8K_NAME);
3423 if (rc) {
3424 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3425 MWL8K_NAME);
3426 return rc;
3427 }
3428
3429 pci_set_master(pdev);
3430
3431 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3432 if (hw == NULL) {
3433 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3434 rc = -ENOMEM;
3435 goto err_free_reg;
3436 }
3437
3438 priv = hw->priv;
3439 priv->hw = hw;
3440 priv->pdev = pdev;
3441 priv->hostcmd_wait = NULL;
3442 priv->tx_wait = NULL;
3443 priv->inconfig = false;
0439b1f5 3444 priv->wmm_enabled = false;
a66098da
LB		 3445 priv->pending_tx_pkts = 0;
3446 strncpy(priv->name, MWL8K_NAME, sizeof(priv->name));
3447
3448 spin_lock_init(&priv->fw_lock);
3449
3450 SET_IEEE80211_DEV(hw, &pdev->dev);
3451 pci_set_drvdata(pdev, hw);
3452
3453 priv->regs = pci_iomap(pdev, 1, 0x10000);
3454 if (priv->regs == NULL) {
3455 printk(KERN_ERR "%s: Cannot map device memory\n", priv->name);
3456 goto err_iounmap;
3457 }
3458
3459 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3460 priv->band.band = IEEE80211_BAND_2GHZ;
3461 priv->band.channels = priv->channels;
3462 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3463 priv->band.bitrates = priv->rates;
3464 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3465 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3466
3467 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3468 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3469
3470 /*
3471 * Extra headroom is the size of the required DMA header
3472 * minus the size of the smallest 802.11 frame (CTS frame).
3473 */
3474 hw->extra_tx_headroom =
3475 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3476
3477 hw->channel_change_time = 10;
3478
3479 hw->queues = MWL8K_TX_QUEUES;
3480
3481 hw->wiphy->interface_modes =
3482 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_MONITOR);
3483
3484 /* Set rssi and noise values to dBm */
ce9e2e1b 3485 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3486 hw->vif_data_size = sizeof(struct mwl8k_vif);
3487 priv->vif = NULL;
3488
3489 /* Set default radio state and preamble */
c46563b7 3490 priv->radio_on = 0;
68ce3884 3491 priv->radio_short_preamble = 0;
a66098da
LB		 3492
3493 /* Finalize join worker */
3494 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3495
3496 /* TX reclaim tasklet */
3497 tasklet_init(&priv->tx_reclaim_task,
3498 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3499 tasklet_disable(&priv->tx_reclaim_task);
3500
3501 /* Config workthread */
3502 priv->config_wq = create_singlethread_workqueue("mwl8k_config");
3503 if (priv->config_wq == NULL)
3504 goto err_iounmap;
3505
3506 /* Power management cookie */
3507 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3508 if (priv->cookie == NULL)
3509 goto err_iounmap;
3510
3511 rc = mwl8k_rxq_init(hw, 0);
3512 if (rc)
3513 goto err_iounmap;
3514 rxq_refill(hw, 0, INT_MAX);
3515
3516 spin_lock_init(&priv->tx_lock);
3517
3518 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3519 rc = mwl8k_txq_init(hw, i);
3520 if (rc)
3521 goto err_free_queues;
3522 }
3523
3524 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3525 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3526 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3527 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3528
3529 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3530 IRQF_SHARED, MWL8K_NAME, hw);
3531 if (rc) {
3532 printk(KERN_ERR "%s: failed to register IRQ handler\n",
3533 priv->name);
3534 goto err_free_queues;
3535 }
3536
3537 /* Reset firmware and hardware */
3538 mwl8k_hw_reset(priv);
3539
3540 /* Ask userland hotplug daemon for the device firmware */
3541 rc = mwl8k_request_firmware(priv, (u32)id->driver_data);
3542 if (rc) {
3543 printk(KERN_ERR "%s: Firmware files not found\n", priv->name);
3544 goto err_free_irq;
3545 }
3546
3547 /* Load firmware into hardware */
3548 rc = mwl8k_load_firmware(priv);
3549 if (rc) {
3550 printk(KERN_ERR "%s: Cannot start firmware\n", priv->name);
3551 goto err_stop_firmware;
3552 }
3553
3554 /* Reclaim memory once firmware is successfully loaded */
3555 mwl8k_release_firmware(priv);
3556
3557 /*
3558 * Temporarily enable interrupts. Initial firmware host
3559 * commands use interrupts and avoids polling. Disable
3560 * interrupts when done.
3561 */
c23b5a69 3562 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3563
3564 /* Get config data, mac addrs etc */
3565 rc = mwl8k_cmd_get_hw_spec(hw);
3566 if (rc) {
3567 printk(KERN_ERR "%s: Cannot initialise firmware\n", priv->name);
3568 goto err_stop_firmware;
3569 }
3570
3571 /* Turn radio off */
c46563b7 3572 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 3573 if (rc) {
3574 printk(KERN_ERR "%s: Cannot disable\n", priv->name);
3575 goto err_stop_firmware;
3576 }
3577
3578 /* Disable interrupts */
3579 spin_lock_irq(&priv->tx_lock);
3580 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3581 spin_unlock_irq(&priv->tx_lock);
3582 free_irq(priv->pdev->irq, hw);
3583
3584 rc = ieee80211_register_hw(hw);
3585 if (rc) {
3586 printk(KERN_ERR "%s: Cannot register device\n", priv->name);
3587 goto err_stop_firmware;
3588 }
3589
3590 fw = (u8 *)&priv->fw_rev;
3591 printk(KERN_INFO "%s: 88W%u %s\n", priv->name, priv->part_num,
3592 MWL8K_DESC);
3593 printk(KERN_INFO "%s: Driver Ver:%s Firmware Ver:%u.%u.%u.%u\n",
3594 priv->name, MWL8K_VERSION, fw[3], fw[2], fw[1], fw[0]);
e91d8334
JB		 3595 printk(KERN_INFO "%s: MAC Address: %pM\n", priv->name,
3596 hw->wiphy->perm_addr);
a66098da
LB		 3597
3598 return 0;
3599
3600err_stop_firmware:
3601 mwl8k_hw_reset(priv);
3602 mwl8k_release_firmware(priv);
3603
3604err_free_irq:
3605 spin_lock_irq(&priv->tx_lock);
3606 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3607 spin_unlock_irq(&priv->tx_lock);
3608 free_irq(priv->pdev->irq, hw);
3609
3610err_free_queues:
3611 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3612 mwl8k_txq_deinit(hw, i);
3613 mwl8k_rxq_deinit(hw, 0);
3614
3615err_iounmap:
3616 if (priv->cookie != NULL)
3617 pci_free_consistent(priv->pdev, 4,
3618 priv->cookie, priv->cookie_dma);
3619
3620 if (priv->regs != NULL)
3621 pci_iounmap(pdev, priv->regs);
3622
3623 if (priv->config_wq != NULL)
3624 destroy_workqueue(priv->config_wq);
3625
3626 pci_set_drvdata(pdev, NULL);
3627 ieee80211_free_hw(hw);
3628
3629err_free_reg:
3630 pci_release_regions(pdev);
3631 pci_disable_device(pdev);
3632
3633 return rc;
3634}
3635
230f7af0 3636static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3637{
3638 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3639}
3640
230f7af0 3641static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3642{
3643 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3644 struct mwl8k_priv *priv;
3645 int i;
3646
3647 if (hw == NULL)
3648 return;
3649 priv = hw->priv;
3650
3651 ieee80211_stop_queues(hw);
3652
60aa569f
LB		 3653 ieee80211_unregister_hw(hw);
3654
a66098da
LB		 3655 /* Remove tx reclaim tasklet */
3656 tasklet_kill(&priv->tx_reclaim_task);
3657
3658 /* Stop config thread */
3659 destroy_workqueue(priv->config_wq);
3660
3661 /* Stop hardware */
3662 mwl8k_hw_reset(priv);
3663
3664 /* Return all skbs to mac80211 */
3665 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3666 mwl8k_txq_reclaim(hw, i, 1);
3667
a66098da
LB		 3668 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3669 mwl8k_txq_deinit(hw, i);
3670
3671 mwl8k_rxq_deinit(hw, 0);
3672
3673 pci_free_consistent(priv->pdev, 4,
3674 priv->cookie, priv->cookie_dma);
3675
3676 pci_iounmap(pdev, priv->regs);
3677 pci_set_drvdata(pdev, NULL);
3678 ieee80211_free_hw(hw);
3679 pci_release_regions(pdev);
3680 pci_disable_device(pdev);
3681}
3682
3683static struct pci_driver mwl8k_driver = {
3684 .name = MWL8K_NAME,
3685 .id_table = mwl8k_table,
3686 .probe = mwl8k_probe,
3687 .remove = __devexit_p(mwl8k_remove),
3688 .shutdown = __devexit_p(mwl8k_shutdown),
3689};
3690
3691static int __init mwl8k_init(void)
3692{
3693 return pci_register_driver(&mwl8k_driver);
3694}
3695
3696static void __exit mwl8k_exit(void)
3697{
3698 pci_unregister_driver(&mwl8k_driver);
3699}
3700
3701module_init(mwl8k_init);
3702module_exit(mwl8k_exit);
Linux kernel - Deliverables
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