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mwl8k: fix MCS bitmap size in SET_RATE command
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status);
88};
89
45a390dd 90struct mwl8k_device_info {
a74b295e
LB		 91 char *part_name;
92 char *helper_image;
93 char *fw_image;
54bc3a0d 94 struct rxd_ops *rxd_ops;
547810e3 95 u16 modes;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
128/* Pointers to the firmware data and meta information about it. */
129struct mwl8k_firmware {
a66098da
LB		 130 /* Boot helper code */
131 struct firmware *helper;
a74b295e
LB		 132
133 /* Microcode */
134 struct firmware *ucode;
a66098da
LB		 135};
136
137struct mwl8k_priv {
5b9482dd 138 void __iomem *sram;
a66098da
LB		 139 void __iomem *regs;
140 struct ieee80211_hw *hw;
141
142 struct pci_dev *pdev;
a66098da 143
45a390dd 144 struct mwl8k_device_info *device_info;
eae74e65 145 bool ap_fw;
54bc3a0d 146 struct rxd_ops *rxd_ops;
45a390dd 147
a66098da
LB		 148 /* firmware files and meta data */
149 struct mwl8k_firmware fw;
a66098da 150
618952a7
LB		 151 /* firmware access */
152 struct mutex fw_mutex;
153 struct task_struct *fw_mutex_owner;
154 int fw_mutex_depth;
618952a7
LB		 155 struct completion *hostcmd_wait;
156
a66098da
LB		 157 /* lock held over TX and TX reap */
158 spinlock_t tx_lock;
a66098da 159
88de754a
LB		 160 /* TX quiesce completion, protected by fw_mutex and tx_lock */
161 struct completion *tx_wait;
162
a66098da 163 struct ieee80211_vif *vif;
a66098da
LB		 164
165 struct ieee80211_channel *current_channel;
166
167 /* power management status cookie from firmware */
168 u32 *cookie;
169 dma_addr_t cookie_dma;
170
171 u16 num_mcaddrs;
a66098da 172 u8 hw_rev;
2aa7b01f 173 u32 fw_rev;
a66098da
LB		 174
175 /*
176 * Running count of TX packets in flight, to avoid
177 * iterating over the transmit rings each time.
178 */
179 int pending_tx_pkts;
180
181 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
182 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
183
184 /* PHY parameters */
185 struct ieee80211_supported_band band;
186 struct ieee80211_channel channels[14];
5dfd3e2c 187 struct ieee80211_rate rates[13];
a66098da 188
c46563b7 189 bool radio_on;
68ce3884 190 bool radio_short_preamble;
a43c49a8 191 bool sniffer_enabled;
0439b1f5 192 bool wmm_enabled;
a66098da 193
a66098da
LB		 194 /* XXX need to convert this to handle multiple interfaces */
195 bool capture_beacon;
d89173f2 196 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 197 struct sk_buff *beacon_skb;
198
199 /*
200 * This FJ worker has to be global as it is scheduled from the
201 * RX handler. At this point we don't know which interface it
202 * belongs to until the list of bssids waiting to complete join
203 * is checked.
204 */
205 struct work_struct finalize_join_worker;
206
207 /* Tasklet to reclaim TX descriptors and buffers after tx */
208 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 209};
210
211/* Per interface specific private data */
212struct mwl8k_vif {
a66098da
LB		 213 /* backpointer to parent config block */
214 struct mwl8k_priv *priv;
215
216 /* BSS config of AP or IBSS from mac80211*/
217 struct ieee80211_bss_conf bss_info;
218
219 /* BSSID of AP or IBSS */
d89173f2
LB		 220 u8 bssid[ETH_ALEN];
221 u8 mac_addr[ETH_ALEN];
a66098da
LB		 222
223 /*
224 * Subset of supported legacy rates.
225 * Intersection of AP and STA supported rates.
226 */
5dfd3e2c 227 struct ieee80211_rate legacy_rates[13];
a66098da
LB		 228
229 /* number of supported legacy rates */
230 u8 legacy_nrates;
231
a66098da
LB		 232 /* Index into station database.Returned by update_sta_db call */
233 u8 peer_id;
234
235 /* Non AMPDU sequence number assigned by driver */
236 u16 seqno;
a66098da
LB		 237};
238
a94cc97e 239#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 240
241static const struct ieee80211_channel mwl8k_channels[] = {
242 { .center_freq = 2412, .hw_value = 1, },
243 { .center_freq = 2417, .hw_value = 2, },
244 { .center_freq = 2422, .hw_value = 3, },
245 { .center_freq = 2427, .hw_value = 4, },
246 { .center_freq = 2432, .hw_value = 5, },
247 { .center_freq = 2437, .hw_value = 6, },
248 { .center_freq = 2442, .hw_value = 7, },
249 { .center_freq = 2447, .hw_value = 8, },
250 { .center_freq = 2452, .hw_value = 9, },
251 { .center_freq = 2457, .hw_value = 10, },
252 { .center_freq = 2462, .hw_value = 11, },
253};
254
255static const struct ieee80211_rate mwl8k_rates[] = {
256 { .bitrate = 10, .hw_value = 2, },
257 { .bitrate = 20, .hw_value = 4, },
258 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 259 { .bitrate = 110, .hw_value = 22, },
260 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 261 { .bitrate = 60, .hw_value = 12, },
262 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 263 { .bitrate = 120, .hw_value = 24, },
264 { .bitrate = 180, .hw_value = 36, },
265 { .bitrate = 240, .hw_value = 48, },
266 { .bitrate = 360, .hw_value = 72, },
267 { .bitrate = 480, .hw_value = 96, },
268 { .bitrate = 540, .hw_value = 108, },
269};
270
a66098da
LB		 271/* Set or get info from Firmware */
272#define MWL8K_CMD_SET 0x0001
273#define MWL8K_CMD_GET 0x0000
274
275/* Firmware command codes */
276#define MWL8K_CMD_CODE_DNLD 0x0001
277#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 278#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 279#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
280#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 281#define MWL8K_CMD_RADIO_CONTROL 0x001c
282#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 283#define MWL8K_CMD_RF_ANTENNA 0x0020
a66098da
LB		 284#define MWL8K_CMD_SET_PRE_SCAN 0x0107
285#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 286#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
287#define MWL8K_CMD_SET_AID 0x010d
288#define MWL8K_CMD_SET_RATE 0x0110
289#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
290#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 291#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 292#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
293#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 294#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 295#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 296#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 297#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 298#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 299#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 300
301static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
302{
303#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
304 snprintf(buf, bufsize, "%s", #x);\
305 return buf;\
306 } while (0)
ce9e2e1b 307 switch (cmd & ~0x8000) {
a66098da
LB		 308 MWL8K_CMDNAME(CODE_DNLD);
309 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 310 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 311 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
312 MWL8K_CMDNAME(GET_STAT);
313 MWL8K_CMDNAME(RADIO_CONTROL);
314 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 315 MWL8K_CMDNAME(RF_ANTENNA);
a66098da
LB		 316 MWL8K_CMDNAME(SET_PRE_SCAN);
317 MWL8K_CMDNAME(SET_POST_SCAN);
318 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 319 MWL8K_CMDNAME(SET_AID);
320 MWL8K_CMDNAME(SET_RATE);
321 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
322 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 323 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 324 MWL8K_CMDNAME(SET_EDCA_PARAMS);
325 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 326 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 327 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 328 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 329 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 330 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 331 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 332 default:
333 snprintf(buf, bufsize, "0x%x", cmd);
334 }
335#undef MWL8K_CMDNAME
336
337 return buf;
338}
339
340/* Hardware and firmware reset */
341static void mwl8k_hw_reset(struct mwl8k_priv *priv)
342{
343 iowrite32(MWL8K_H2A_INT_RESET,
344 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
345 iowrite32(MWL8K_H2A_INT_RESET,
346 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
347 msleep(20);
348}
349
350/* Release fw image */
351static void mwl8k_release_fw(struct firmware **fw)
352{
353 if (*fw == NULL)
354 return;
355 release_firmware(*fw);
356 *fw = NULL;
357}
358
359static void mwl8k_release_firmware(struct mwl8k_priv *priv)
360{
361 mwl8k_release_fw(&priv->fw.ucode);
362 mwl8k_release_fw(&priv->fw.helper);
363}
364
365/* Request fw image */
366static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 367 const char *fname, struct firmware **fw)
a66098da
LB		 368{
369 /* release current image */
370 if (*fw != NULL)
371 mwl8k_release_fw(fw);
372
373 return request_firmware((const struct firmware **)fw,
c2c357ce 374 fname, &priv->pdev->dev);
a66098da
LB		 375}
376
45a390dd 377static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 378{
a74b295e 379 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 380 int rc;
381
a74b295e
LB		 382 if (di->helper_image != NULL) {
383 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
384 if (rc) {
385 printk(KERN_ERR "%s: Error requesting helper "
386 "firmware file %s\n", pci_name(priv->pdev),
387 di->helper_image);
388 return rc;
389 }
a66098da
LB		 390 }
391
a74b295e 392 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 393 if (rc) {
c2c357ce 394 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 395 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 396 mwl8k_release_fw(&priv->fw.helper);
397 return rc;
398 }
399
400 return 0;
401}
402
7e75b942
BH		 403MODULE_FIRMWARE("mwl8k/helper_8687.fw");
404MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
405
a66098da
LB		 406struct mwl8k_cmd_pkt {
407 __le16 code;
408 __le16 length;
409 __le16 seq_num;
410 __le16 result;
411 char payload[0];
412} __attribute__((packed));
413
414/*
415 * Firmware loading.
416 */
417static int
418mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
419{
420 void __iomem *regs = priv->regs;
421 dma_addr_t dma_addr;
a66098da
LB		 422 int loops;
423
424 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
425 if (pci_dma_mapping_error(priv->pdev, dma_addr))
426 return -ENOMEM;
427
428 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
429 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
430 iowrite32(MWL8K_H2A_INT_DOORBELL,
431 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
432 iowrite32(MWL8K_H2A_INT_DUMMY,
433 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
434
a66098da
LB		 435 loops = 1000;
436 do {
437 u32 int_code;
438
439 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
440 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
441 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 442 break;
443 }
444
3d76e82c 445 cond_resched();
a66098da
LB		 446 udelay(1);
447 } while (--loops);
448
449 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
450
d4b70570 451 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 452}
453
454static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
455 const u8 *data, size_t length)
456{
457 struct mwl8k_cmd_pkt *cmd;
458 int done;
459 int rc = 0;
460
461 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
462 if (cmd == NULL)
463 return -ENOMEM;
464
465 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
466 cmd->seq_num = 0;
467 cmd->result = 0;
468
469 done = 0;
470 while (length) {
471 int block_size = length > 256 ? 256 : length;
472
473 memcpy(cmd->payload, data + done, block_size);
474 cmd->length = cpu_to_le16(block_size);
475
476 rc = mwl8k_send_fw_load_cmd(priv, cmd,
477 sizeof(*cmd) + block_size);
478 if (rc)
479 break;
480
481 done += block_size;
482 length -= block_size;
483 }
484
485 if (!rc) {
486 cmd->length = 0;
487 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
488 }
489
490 kfree(cmd);
491
492 return rc;
493}
494
495static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
496 const u8 *data, size_t length)
497{
498 unsigned char *buffer;
499 int may_continue, rc = 0;
500 u32 done, prev_block_size;
501
502 buffer = kmalloc(1024, GFP_KERNEL);
503 if (buffer == NULL)
504 return -ENOMEM;
505
506 done = 0;
507 prev_block_size = 0;
508 may_continue = 1000;
509 while (may_continue > 0) {
510 u32 block_size;
511
512 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
513 if (block_size & 1) {
514 block_size &= ~1;
515 may_continue--;
516 } else {
517 done += prev_block_size;
518 length -= prev_block_size;
519 }
520
521 if (block_size > 1024 || block_size > length) {
522 rc = -EOVERFLOW;
523 break;
524 }
525
526 if (length == 0) {
527 rc = 0;
528 break;
529 }
530
531 if (block_size == 0) {
532 rc = -EPROTO;
533 may_continue--;
534 udelay(1);
535 continue;
536 }
537
538 prev_block_size = block_size;
539 memcpy(buffer, data + done, block_size);
540
541 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
542 if (rc)
543 break;
544 }
545
546 if (!rc && length != 0)
547 rc = -EREMOTEIO;
548
549 kfree(buffer);
550
551 return rc;
552}
553
c2c357ce 554static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 555{
c2c357ce
LB		 556 struct mwl8k_priv *priv = hw->priv;
557 struct firmware *fw = priv->fw.ucode;
eae74e65 558 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 559 int rc;
560 int loops;
561
562 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
563 struct firmware *helper = priv->fw.helper;
a66098da 564
c2c357ce
LB		 565 if (helper == NULL) {
566 printk(KERN_ERR "%s: helper image needed but none "
567 "given\n", pci_name(priv->pdev));
568 return -EINVAL;
569 }
a66098da 570
c2c357ce 571 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 572 if (rc) {
573 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 574 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 575 return rc;
576 }
577 msleep(1);
578
c2c357ce 579 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 580 } else {
c2c357ce 581 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 582 }
583
584 if (rc) {
c2c357ce
LB		 585 printk(KERN_ERR "%s: unable to load firmware image\n",
586 pci_name(priv->pdev));
a66098da
LB		 587 return rc;
588 }
589
eae74e65
LB		 590 if (di->modes & BIT(NL80211_IFTYPE_AP))
591 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
592 else
593 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da
LB		 594 msleep(1);
595
596 loops = 200000;
597 do {
eae74e65
LB		 598 u32 ready_code;
599
600 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
601 if (ready_code == MWL8K_FWAP_READY) {
602 priv->ap_fw = 1;
603 break;
604 } else if (ready_code == MWL8K_FWSTA_READY) {
605 priv->ap_fw = 0;
a66098da 606 break;
eae74e65
LB		 607 }
608
609 cond_resched();
a66098da
LB		 610 udelay(1);
611 } while (--loops);
612
613 return loops ? 0 : -ETIMEDOUT;
614}
615
616
617/*
618 * Defines shared between transmission and reception.
619 */
620/* HT control fields for firmware */
621struct ewc_ht_info {
622 __le16 control1;
623 __le16 control2;
624 __le16 control3;
625} __attribute__((packed));
626
627/* Firmware Station database operations */
628#define MWL8K_STA_DB_ADD_ENTRY 0
629#define MWL8K_STA_DB_MODIFY_ENTRY 1
630#define MWL8K_STA_DB_DEL_ENTRY 2
631#define MWL8K_STA_DB_FLUSH 3
632
633/* Peer Entry flags - used to define the type of the peer node */
634#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 635
5dfd3e2c 636#define MWL8K_IEEE_LEGACY_DATA_RATES 13
a66098da
LB		 637
638struct peer_capability_info {
639 /* Peer type - AP vs. STA. */
640 __u8 peer_type;
641
642 /* Basic 802.11 capabilities from assoc resp. */
643 __le16 basic_caps;
644
645 /* Set if peer supports 802.11n high throughput (HT). */
646 __u8 ht_support;
647
648 /* Valid if HT is supported. */
649 __le16 ht_caps;
650 __u8 extended_ht_caps;
651 struct ewc_ht_info ewc_info;
652
653 /* Legacy rate table. Intersection of our rates and peer rates. */
654 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
655
656 /* HT rate table. Intersection of our rates and peer rates. */
0b5351a8 657 __u8 ht_rates[16];
c23b5a69 658 __u8 pad[16];
a66098da
LB		 659
660 /* If set, interoperability mode, no proprietary extensions. */
661 __u8 interop;
662 __u8 pad2;
663 __u8 station_id;
664 __le16 amsdu_enabled;
665} __attribute__((packed));
666
667/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 668static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
669{
670 u16 val_mask = 1 << 4;
671
672 /* End of Service Period Bit 4 */
673 return qos | val_mask;
674}
675
676static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
677{
678 u16 val_mask = 0x3;
679 u8 shift = 5;
680 u16 qos_mask = ~(val_mask << shift);
681
682 /* Ack Policy Bit 5-6 */
683 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
684}
685
686static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
687{
688 u16 val_mask = 1 << 7;
689
690 /* AMSDU present Bit 7 */
691 return qos | val_mask;
692}
693
694static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
695{
696 u16 val_mask = 0xff;
697 u8 shift = 8;
698 u16 qos_mask = ~(val_mask << shift);
699
700 /* Queue Length Bits 8-15 */
701 return (qos & qos_mask) | ((len & val_mask) << shift);
702}
703
704/* DMA header used by firmware and hardware. */
705struct mwl8k_dma_data {
706 __le16 fwlen;
707 struct ieee80211_hdr wh;
708} __attribute__((packed));
709
710/* Routines to add/remove DMA header from skb. */
76266b2a 711static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
a66098da 712{
76266b2a 713 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
a66098da 714 void *dst, *src = &tr->wh;
76266b2a 715 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
a66098da
LB		 716 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
717
718 dst = (void *)tr + space;
719 if (dst != src) {
720 memmove(dst, src, hdrlen);
721 skb_pull(skb, space);
722 }
a66098da
LB		 723}
724
76266b2a 725static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 726{
727 struct ieee80211_hdr *wh;
728 u32 hdrlen, pktlen;
729 struct mwl8k_dma_data *tr;
730
731 wh = (struct ieee80211_hdr *)skb->data;
732 hdrlen = ieee80211_hdrlen(wh->frame_control);
733 pktlen = skb->len;
734
735 /*
736 * Copy up/down the 802.11 header; the firmware requires
737 * we present a 2-byte payload length followed by a
738 * 4-address header (w/o QoS), followed (optionally) by
739 * any WEP/ExtIV header (but only filled in for CCMP).
740 */
741 if (hdrlen != sizeof(struct mwl8k_dma_data))
742 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
743
744 tr = (struct mwl8k_dma_data *)skb->data;
745 if (wh != &tr->wh)
746 memmove(&tr->wh, wh, hdrlen);
747
748 /* Clear addr4 */
d89173f2 749 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 750
751 /*
752 * Firmware length is the length of the fully formed "802.11
753 * payload". That is, everything except for the 802.11 header.
754 * This includes all crypto material including the MIC.
755 */
756 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 757}
758
759
760/*
6f6d1e9a
LB		 761 * Packet reception for 88w8366.
762 */
763struct mwl8k_rxd_8366 {
764 __le16 pkt_len;
765 __u8 sq2;
766 __u8 rate;
767 __le32 pkt_phys_addr;
768 __le32 next_rxd_phys_addr;
769 __le16 qos_control;
770 __le16 htsig2;
771 __le32 hw_rssi_info;
772 __le32 hw_noise_floor_info;
773 __u8 noise_floor;
774 __u8 pad0[3];
775 __u8 rssi;
776 __u8 rx_status;
777 __u8 channel;
778 __u8 rx_ctrl;
779} __attribute__((packed));
780
781#define MWL8K_8366_RX_CTRL_OWNED_BY_HOST 0x80
782
783static void mwl8k_rxd_8366_init(void *_rxd, dma_addr_t next_dma_addr)
784{
785 struct mwl8k_rxd_8366 *rxd = _rxd;
786
787 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
788 rxd->rx_ctrl = MWL8K_8366_RX_CTRL_OWNED_BY_HOST;
789}
790
791static void mwl8k_rxd_8366_refill(void *_rxd, dma_addr_t addr, int len)
792{
793 struct mwl8k_rxd_8366 *rxd = _rxd;
794
795 rxd->pkt_len = cpu_to_le16(len);
796 rxd->pkt_phys_addr = cpu_to_le32(addr);
797 wmb();
798 rxd->rx_ctrl = 0;
799}
800
801static int
802mwl8k_rxd_8366_process(void *_rxd, struct ieee80211_rx_status *status)
803{
804 struct mwl8k_rxd_8366 *rxd = _rxd;
805
806 if (!(rxd->rx_ctrl & MWL8K_8366_RX_CTRL_OWNED_BY_HOST))
807 return -1;
808 rmb();
809
810 memset(status, 0, sizeof(*status));
811
812 status->signal = -rxd->rssi;
813 status->noise = -rxd->noise_floor;
814
815 if (rxd->rate & 0x80) {
816 status->flag |= RX_FLAG_HT;
817 status->rate_idx = rxd->rate & 0x7f;
818 } else {
819 int i;
820
821 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
822 if (mwl8k_rates[i].hw_value == rxd->rate) {
823 status->rate_idx = i;
824 break;
825 }
826 }
827 }
828
829 status->band = IEEE80211_BAND_2GHZ;
830 status->freq = ieee80211_channel_to_frequency(rxd->channel);
831
832 return le16_to_cpu(rxd->pkt_len);
833}
834
835static struct rxd_ops rxd_8366_ops = {
836 .rxd_size = sizeof(struct mwl8k_rxd_8366),
837 .rxd_init = mwl8k_rxd_8366_init,
838 .rxd_refill = mwl8k_rxd_8366_refill,
839 .rxd_process = mwl8k_rxd_8366_process,
840};
841
842/*
843 * Packet reception for 88w8687.
a66098da 844 */
54bc3a0d 845struct mwl8k_rxd_8687 {
a66098da
LB		 846 __le16 pkt_len;
847 __u8 link_quality;
848 __u8 noise_level;
849 __le32 pkt_phys_addr;
45eb400d 850 __le32 next_rxd_phys_addr;
a66098da
LB		 851 __le16 qos_control;
852 __le16 rate_info;
853 __le32 pad0[4];
854 __u8 rssi;
855 __u8 channel;
856 __le16 pad1;
857 __u8 rx_ctrl;
858 __u8 rx_status;
859 __u8 pad2[2];
860} __attribute__((packed));
861
54bc3a0d
LB		 862#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
863#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
864#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
865#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
866#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
867#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
868
869#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
870
871static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
872{
873 struct mwl8k_rxd_8687 *rxd = _rxd;
874
875 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
876 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
877}
878
879static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
880{
881 struct mwl8k_rxd_8687 *rxd = _rxd;
882
883 rxd->pkt_len = cpu_to_le16(len);
884 rxd->pkt_phys_addr = cpu_to_le32(addr);
885 wmb();
886 rxd->rx_ctrl = 0;
887}
888
889static int
890mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status)
891{
892 struct mwl8k_rxd_8687 *rxd = _rxd;
893 u16 rate_info;
894
895 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
896 return -1;
897 rmb();
898
899 rate_info = le16_to_cpu(rxd->rate_info);
900
901 memset(status, 0, sizeof(*status));
902
903 status->signal = -rxd->rssi;
904 status->noise = -rxd->noise_level;
905 status->qual = rxd->link_quality;
906 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
907 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
908
909 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
910 status->flag |= RX_FLAG_SHORTPRE;
911 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
912 status->flag |= RX_FLAG_40MHZ;
913 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
914 status->flag |= RX_FLAG_SHORT_GI;
915 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
916 status->flag |= RX_FLAG_HT;
917
918 status->band = IEEE80211_BAND_2GHZ;
919 status->freq = ieee80211_channel_to_frequency(rxd->channel);
920
921 return le16_to_cpu(rxd->pkt_len);
922}
923
924static struct rxd_ops rxd_8687_ops = {
925 .rxd_size = sizeof(struct mwl8k_rxd_8687),
926 .rxd_init = mwl8k_rxd_8687_init,
927 .rxd_refill = mwl8k_rxd_8687_refill,
928 .rxd_process = mwl8k_rxd_8687_process,
929};
930
931
a66098da
LB		 932#define MWL8K_RX_DESCS 256
933#define MWL8K_RX_MAXSZ 3800
934
935static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
936{
937 struct mwl8k_priv *priv = hw->priv;
938 struct mwl8k_rx_queue *rxq = priv->rxq + index;
939 int size;
940 int i;
941
45eb400d
LB		 942 rxq->rxd_count = 0;
943 rxq->head = 0;
944 rxq->tail = 0;
a66098da 945
54bc3a0d 946 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 947
45eb400d
LB		 948 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
949 if (rxq->rxd == NULL) {
a66098da 950 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 951 wiphy_name(hw->wiphy));
a66098da
LB		 952 return -ENOMEM;
953 }
45eb400d 954 memset(rxq->rxd, 0, size);
a66098da 955
788838eb
LB		 956 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
957 if (rxq->buf == NULL) {
a66098da 958 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 959 wiphy_name(hw->wiphy));
45eb400d 960 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 961 return -ENOMEM;
962 }
788838eb 963 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 964
965 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 966 int desc_size;
967 void *rxd;
a66098da 968 int nexti;
54bc3a0d
LB		 969 dma_addr_t next_dma_addr;
970
971 desc_size = priv->rxd_ops->rxd_size;
972 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 973
54bc3a0d
LB		 974 nexti = i + 1;
975 if (nexti == MWL8K_RX_DESCS)
976 nexti = 0;
977 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 978
54bc3a0d 979 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 980 }
981
982 return 0;
983}
984
985static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
986{
987 struct mwl8k_priv *priv = hw->priv;
988 struct mwl8k_rx_queue *rxq = priv->rxq + index;
989 int refilled;
990
991 refilled = 0;
45eb400d 992 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 993 struct sk_buff *skb;
788838eb 994 dma_addr_t addr;
a66098da 995 int rx;
54bc3a0d 996 void *rxd;
a66098da
LB		 997
998 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
999 if (skb == NULL)
1000 break;
1001
788838eb
LB		 1002 addr = pci_map_single(priv->pdev, skb->data,
1003 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1004
54bc3a0d
LB		 1005 rxq->rxd_count++;
1006 rx = rxq->tail++;
1007 if (rxq->tail == MWL8K_RX_DESCS)
1008 rxq->tail = 0;
788838eb
LB		 1009 rxq->buf[rx].skb = skb;
1010 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1011
1012 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1013 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1014
1015 refilled++;
1016 }
1017
1018 return refilled;
1019}
1020
1021/* Must be called only when the card's reception is completely halted */
1022static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1023{
1024 struct mwl8k_priv *priv = hw->priv;
1025 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1026 int i;
1027
1028 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1029 if (rxq->buf[i].skb != NULL) {
1030 pci_unmap_single(priv->pdev,
1031 pci_unmap_addr(&rxq->buf[i], dma),
1032 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1033 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
1034
1035 kfree_skb(rxq->buf[i].skb);
1036 rxq->buf[i].skb = NULL;
a66098da
LB		 1037 }
1038 }
1039
788838eb
LB		 1040 kfree(rxq->buf);
1041 rxq->buf = NULL;
a66098da
LB		 1042
1043 pci_free_consistent(priv->pdev,
54bc3a0d 1044 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1045 rxq->rxd, rxq->rxd_dma);
1046 rxq->rxd = NULL;
a66098da
LB		 1047}
1048
1049
1050/*
1051 * Scan a list of BSSIDs to process for finalize join.
1052 * Allows for extension to process multiple BSSIDs.
1053 */
1054static inline int
1055mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1056{
1057 return priv->capture_beacon &&
1058 ieee80211_is_beacon(wh->frame_control) &&
1059 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1060}
1061
3779752d
LB		 1062static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1063 struct sk_buff *skb)
a66098da 1064{
3779752d
LB		 1065 struct mwl8k_priv *priv = hw->priv;
1066
a66098da 1067 priv->capture_beacon = false;
d89173f2 1068 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1069
1070 /*
1071 * Use GFP_ATOMIC as rxq_process is called from
1072 * the primary interrupt handler, memory allocation call
1073 * must not sleep.
1074 */
1075 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1076 if (priv->beacon_skb != NULL)
3779752d 1077 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1078}
1079
1080static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1081{
1082 struct mwl8k_priv *priv = hw->priv;
1083 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1084 int processed;
1085
1086 processed = 0;
45eb400d 1087 while (rxq->rxd_count && limit--) {
a66098da 1088 struct sk_buff *skb;
54bc3a0d
LB		 1089 void *rxd;
1090 int pkt_len;
a66098da 1091 struct ieee80211_rx_status status;
a66098da 1092
788838eb 1093 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1094 if (skb == NULL)
1095 break;
54bc3a0d
LB		 1096
1097 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1098
1099 pkt_len = priv->rxd_ops->rxd_process(rxd, &status);
1100 if (pkt_len < 0)
1101 break;
1102
788838eb
LB		 1103 rxq->buf[rxq->head].skb = NULL;
1104
1105 pci_unmap_single(priv->pdev,
1106 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1107 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1108 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1109
54bc3a0d
LB		 1110 rxq->head++;
1111 if (rxq->head == MWL8K_RX_DESCS)
1112 rxq->head = 0;
1113
45eb400d 1114 rxq->rxd_count--;
a66098da 1115
54bc3a0d 1116 skb_put(skb, pkt_len);
76266b2a 1117 mwl8k_remove_dma_header(skb);
a66098da 1118
a66098da 1119 /*
c2c357ce
LB		 1120 * Check for a pending join operation. Save a
1121 * copy of the beacon and schedule a tasklet to
1122 * send a FINALIZE_JOIN command to the firmware.
a66098da 1123 */
54bc3a0d 1124 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1125 mwl8k_save_beacon(hw, skb);
a66098da 1126
f1d58c25
JB		 1127 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1128 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1129
1130 processed++;
1131 }
1132
1133 return processed;
1134}
1135
1136
1137/*
1138 * Packet transmission.
1139 */
1140
a66098da
LB		 1141/* Transmit packet ACK policy */
1142#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1143#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1144
a66098da
LB		 1145#define MWL8K_TXD_STATUS_OK 0x00000001
1146#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1147#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1148#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1149#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1150
1151struct mwl8k_tx_desc {
1152 __le32 status;
1153 __u8 data_rate;
1154 __u8 tx_priority;
1155 __le16 qos_control;
1156 __le32 pkt_phys_addr;
1157 __le16 pkt_len;
d89173f2 1158 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1159 __le32 next_txd_phys_addr;
a66098da
LB		 1160 __le32 reserved;
1161 __le16 rate_info;
1162 __u8 peer_id;
1163 __u8 tx_frag_cnt;
1164} __attribute__((packed));
1165
1166#define MWL8K_TX_DESCS 128
1167
1168static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1169{
1170 struct mwl8k_priv *priv = hw->priv;
1171 struct mwl8k_tx_queue *txq = priv->txq + index;
1172 int size;
1173 int i;
1174
45eb400d
LB		 1175 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1176 txq->stats.limit = MWL8K_TX_DESCS;
1177 txq->head = 0;
1178 txq->tail = 0;
a66098da
LB		 1179
1180 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1181
45eb400d
LB		 1182 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1183 if (txq->txd == NULL) {
a66098da 1184 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1185 wiphy_name(hw->wiphy));
a66098da
LB		 1186 return -ENOMEM;
1187 }
45eb400d 1188 memset(txq->txd, 0, size);
a66098da 1189
45eb400d
LB		 1190 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1191 if (txq->skb == NULL) {
a66098da 1192 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1193 wiphy_name(hw->wiphy));
45eb400d 1194 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1195 return -ENOMEM;
1196 }
45eb400d 1197 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1198
1199 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1200 struct mwl8k_tx_desc *tx_desc;
1201 int nexti;
1202
45eb400d 1203 tx_desc = txq->txd + i;
a66098da
LB		 1204 nexti = (i + 1) % MWL8K_TX_DESCS;
1205
1206 tx_desc->status = 0;
45eb400d
LB		 1207 tx_desc->next_txd_phys_addr =
1208 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1209 }
1210
1211 return 0;
1212}
1213
1214static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1215{
1216 iowrite32(MWL8K_H2A_INT_PPA_READY,
1217 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1218 iowrite32(MWL8K_H2A_INT_DUMMY,
1219 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1220 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1221}
1222
a66098da
LB		 1223struct mwl8k_txq_info {
1224 u32 fw_owned;
1225 u32 drv_owned;
1226 u32 unused;
1227 u32 len;
1228 u32 head;
1229 u32 tail;
1230};
1231
1232static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1233 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1234{
1235 int count, desc, status;
1236 struct mwl8k_tx_queue *txq;
1237 struct mwl8k_tx_desc *tx_desc;
1238 int ndescs = 0;
1239
c3f967d3
LB		 1240 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1241
c3f967d3 1242 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da 1243 txq = priv->txq + count;
45eb400d
LB		 1244 txinfo[count].len = txq->stats.len;
1245 txinfo[count].head = txq->head;
1246 txinfo[count].tail = txq->tail;
a66098da 1247 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
45eb400d 1248 tx_desc = txq->txd + desc;
a66098da
LB		 1249 status = le32_to_cpu(tx_desc->status);
1250
1251 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1252 txinfo[count].fw_owned++;
1253 else
1254 txinfo[count].drv_owned++;
1255
1256 if (tx_desc->pkt_len == 0)
1257 txinfo[count].unused++;
1258 }
1259 }
a66098da
LB		 1260
1261 return ndescs;
1262}
1263
618952a7 1264/*
88de754a 1265 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1266 */
950d5b01 1267static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1268{
a66098da 1269 struct mwl8k_priv *priv = hw->priv;
88de754a 1270 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1271 u32 count;
1272 unsigned long timeout;
a66098da
LB		 1273
1274 might_sleep();
1275
a66098da 1276 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1277 count = priv->pending_tx_pkts;
1278 if (count)
1279 priv->tx_wait = &tx_wait;
a66098da
LB		 1280 spin_unlock_bh(&priv->tx_lock);
1281
1282 if (count) {
c3f967d3 1283 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1284 int index;
1285 int newcount;
1286
88de754a 1287 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1288 msecs_to_jiffies(5000));
a66098da
LB		 1289 if (timeout)
1290 return 0;
1291
1292 spin_lock_bh(&priv->tx_lock);
1293 priv->tx_wait = NULL;
88de754a
LB		 1294 newcount = priv->pending_tx_pkts;
1295 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1296 spin_unlock_bh(&priv->tx_lock);
1297
618952a7 1298 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1299 __func__, __LINE__, count, newcount);
a66098da 1300
c3f967d3 1301 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1302 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1303 "DRV:%u U:%u\n",
a66098da
LB		 1304 index,
1305 txinfo[index].len,
1306 txinfo[index].head,
1307 txinfo[index].tail,
1308 txinfo[index].fw_owned,
1309 txinfo[index].drv_owned,
1310 txinfo[index].unused);
ce9e2e1b 1311
a66098da
LB		 1312 return -ETIMEDOUT;
1313 }
1314
1315 return 0;
1316}
1317
c23b5a69
LB		 1318#define MWL8K_TXD_SUCCESS(status) \
1319 ((status) & (MWL8K_TXD_STATUS_OK | \
1320 MWL8K_TXD_STATUS_OK_RETRY | \
1321 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1322
1323static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1324{
1325 struct mwl8k_priv *priv = hw->priv;
1326 struct mwl8k_tx_queue *txq = priv->txq + index;
1327 int wake = 0;
1328
45eb400d 1329 while (txq->stats.len > 0) {
a66098da 1330 int tx;
a66098da
LB		 1331 struct mwl8k_tx_desc *tx_desc;
1332 unsigned long addr;
ce9e2e1b 1333 int size;
a66098da
LB		 1334 struct sk_buff *skb;
1335 struct ieee80211_tx_info *info;
1336 u32 status;
1337
45eb400d
LB		 1338 tx = txq->head;
1339 tx_desc = txq->txd + tx;
a66098da
LB		 1340
1341 status = le32_to_cpu(tx_desc->status);
1342
1343 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1344 if (!force)
1345 break;
1346 tx_desc->status &=
1347 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1348 }
1349
45eb400d
LB		 1350 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1351 BUG_ON(txq->stats.len == 0);
1352 txq->stats.len--;
a66098da
LB		 1353 priv->pending_tx_pkts--;
1354
1355 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1356 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1357 skb = txq->skb[tx];
1358 txq->skb[tx] = NULL;
a66098da
LB		 1359
1360 BUG_ON(skb == NULL);
1361 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1362
76266b2a 1363 mwl8k_remove_dma_header(skb);
a66098da
LB		 1364
1365 /* Mark descriptor as unused */
1366 tx_desc->pkt_phys_addr = 0;
1367 tx_desc->pkt_len = 0;
1368
a66098da
LB		 1369 info = IEEE80211_SKB_CB(skb);
1370 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1371 if (MWL8K_TXD_SUCCESS(status))
a66098da 1372 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1373
1374 ieee80211_tx_status_irqsafe(hw, skb);
1375
618952a7 1376 wake = 1;
a66098da
LB		 1377 }
1378
618952a7 1379 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1380 ieee80211_wake_queue(hw, index);
1381}
1382
1383/* must be called only when the card's transmit is completely halted */
1384static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1385{
1386 struct mwl8k_priv *priv = hw->priv;
1387 struct mwl8k_tx_queue *txq = priv->txq + index;
1388
1389 mwl8k_txq_reclaim(hw, index, 1);
1390
45eb400d
LB		 1391 kfree(txq->skb);
1392 txq->skb = NULL;
a66098da
LB		 1393
1394 pci_free_consistent(priv->pdev,
1395 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1396 txq->txd, txq->txd_dma);
1397 txq->txd = NULL;
a66098da
LB		 1398}
1399
1400static int
1401mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1402{
1403 struct mwl8k_priv *priv = hw->priv;
1404 struct ieee80211_tx_info *tx_info;
23b33906 1405 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1406 struct ieee80211_hdr *wh;
1407 struct mwl8k_tx_queue *txq;
1408 struct mwl8k_tx_desc *tx;
a66098da 1409 dma_addr_t dma;
23b33906
LB		 1410 u32 txstatus;
1411 u8 txdatarate;
1412 u16 qos;
a66098da 1413
23b33906
LB		 1414 wh = (struct ieee80211_hdr *)skb->data;
1415 if (ieee80211_is_data_qos(wh->frame_control))
1416 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1417 else
1418 qos = 0;
a66098da 1419
76266b2a 1420 mwl8k_add_dma_header(skb);
23b33906 1421 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1422
1423 tx_info = IEEE80211_SKB_CB(skb);
1424 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1425
1426 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1427 u16 seqno = mwl8k_vif->seqno;
23b33906 1428
a66098da
LB		 1429 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1430 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1431 mwl8k_vif->seqno = seqno++ % 4096;
1432 }
1433
23b33906
LB		 1434 /* Setup firmware control bit fields for each frame type. */
1435 txstatus = 0;
1436 txdatarate = 0;
1437 if (ieee80211_is_mgmt(wh->frame_control) ||
1438 ieee80211_is_ctl(wh->frame_control)) {
1439 txdatarate = 0;
1440 qos = mwl8k_qos_setbit_eosp(qos);
1441 /* Set Queue size to unspecified */
1442 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1443 } else if (ieee80211_is_data(wh->frame_control)) {
1444 txdatarate = 1;
1445 if (is_multicast_ether_addr(wh->addr1))
1446 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1447
1448 /* Send pkt in an aggregate if AMPDU frame. */
1449 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1450 qos = mwl8k_qos_setbit_ack(qos,
1451 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1452 else
1453 qos = mwl8k_qos_setbit_ack(qos,
1454 MWL8K_TXD_ACK_POLICY_NORMAL);
1455
1456 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1457 qos = mwl8k_qos_setbit_amsdu(qos);
1458 }
a66098da
LB		 1459
1460 dma = pci_map_single(priv->pdev, skb->data,
1461 skb->len, PCI_DMA_TODEVICE);
1462
1463 if (pci_dma_mapping_error(priv->pdev, dma)) {
1464 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1465 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1466 dev_kfree_skb(skb);
a66098da
LB		 1467 return NETDEV_TX_OK;
1468 }
1469
23b33906 1470 spin_lock_bh(&priv->tx_lock);
a66098da 1471
23b33906 1472 txq = priv->txq + index;
a66098da 1473
45eb400d
LB		 1474 BUG_ON(txq->skb[txq->tail] != NULL);
1475 txq->skb[txq->tail] = skb;
a66098da 1476
45eb400d 1477 tx = txq->txd + txq->tail;
23b33906
LB		 1478 tx->data_rate = txdatarate;
1479 tx->tx_priority = index;
a66098da 1480 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1481 tx->pkt_phys_addr = cpu_to_le32(dma);
1482 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1483 tx->rate_info = 0;
1484 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1485 wmb();
23b33906
LB		 1486 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1487
45eb400d
LB		 1488 txq->stats.count++;
1489 txq->stats.len++;
a66098da 1490 priv->pending_tx_pkts++;
a66098da 1491
45eb400d
LB		 1492 txq->tail++;
1493 if (txq->tail == MWL8K_TX_DESCS)
1494 txq->tail = 0;
23b33906 1495
45eb400d 1496 if (txq->head == txq->tail)
a66098da
LB		 1497 ieee80211_stop_queue(hw, index);
1498
23b33906 1499 mwl8k_tx_start(priv);
a66098da
LB		 1500
1501 spin_unlock_bh(&priv->tx_lock);
1502
1503 return NETDEV_TX_OK;
1504}
1505
1506
618952a7
LB		 1507/*
1508 * Firmware access.
1509 *
1510 * We have the following requirements for issuing firmware commands:
1511 * - Some commands require that the packet transmit path is idle when
1512 * the command is issued. (For simplicity, we'll just quiesce the
1513 * transmit path for every command.)
1514 * - There are certain sequences of commands that need to be issued to
1515 * the hardware sequentially, with no other intervening commands.
1516 *
1517 * This leads to an implementation of a "firmware lock" as a mutex that
1518 * can be taken recursively, and which is taken by both the low-level
1519 * command submission function (mwl8k_post_cmd) as well as any users of
1520 * that function that require issuing of an atomic sequence of commands,
1521 * and quiesces the transmit path whenever it's taken.
1522 */
1523static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1524{
1525 struct mwl8k_priv *priv = hw->priv;
1526
1527 if (priv->fw_mutex_owner != current) {
1528 int rc;
1529
1530 mutex_lock(&priv->fw_mutex);
1531 ieee80211_stop_queues(hw);
1532
1533 rc = mwl8k_tx_wait_empty(hw);
1534 if (rc) {
1535 ieee80211_wake_queues(hw);
1536 mutex_unlock(&priv->fw_mutex);
1537
1538 return rc;
1539 }
1540
1541 priv->fw_mutex_owner = current;
1542 }
1543
1544 priv->fw_mutex_depth++;
1545
1546 return 0;
1547}
1548
1549static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1550{
1551 struct mwl8k_priv *priv = hw->priv;
1552
1553 if (!--priv->fw_mutex_depth) {
1554 ieee80211_wake_queues(hw);
1555 priv->fw_mutex_owner = NULL;
1556 mutex_unlock(&priv->fw_mutex);
1557 }
1558}
1559
1560
a66098da
LB		 1561/*
1562 * Command processing.
1563 */
1564
1565/* Timeout firmware commands after 2000ms */
1566#define MWL8K_CMD_TIMEOUT_MS 2000
1567
1568static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1569{
1570 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1571 struct mwl8k_priv *priv = hw->priv;
1572 void __iomem *regs = priv->regs;
1573 dma_addr_t dma_addr;
1574 unsigned int dma_size;
1575 int rc;
a66098da
LB		 1576 unsigned long timeout = 0;
1577 u8 buf[32];
1578
c2c357ce 1579 cmd->result = 0xffff;
a66098da
LB		 1580 dma_size = le16_to_cpu(cmd->length);
1581 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1582 PCI_DMA_BIDIRECTIONAL);
1583 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1584 return -ENOMEM;
1585
618952a7 1586 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1587 if (rc) {
1588 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1589 PCI_DMA_BIDIRECTIONAL);
618952a7 1590 return rc;
39a1e42e 1591 }
a66098da 1592
a66098da
LB		 1593 priv->hostcmd_wait = &cmd_wait;
1594 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1595 iowrite32(MWL8K_H2A_INT_DOORBELL,
1596 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1597 iowrite32(MWL8K_H2A_INT_DUMMY,
1598 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1599
1600 timeout = wait_for_completion_timeout(&cmd_wait,
1601 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1602
618952a7
LB		 1603 priv->hostcmd_wait = NULL;
1604
1605 mwl8k_fw_unlock(hw);
1606
37055bd4
LB		 1607 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1608 PCI_DMA_BIDIRECTIONAL);
1609
a66098da 1610 if (!timeout) {
a66098da 1611 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1612 wiphy_name(hw->wiphy),
a66098da
LB		 1613 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1614 MWL8K_CMD_TIMEOUT_MS);
1615 rc = -ETIMEDOUT;
1616 } else {
ce9e2e1b 1617 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1618 if (rc)
1619 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1620 wiphy_name(hw->wiphy),
a66098da 1621 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1622 le16_to_cpu(cmd->result));
a66098da
LB		 1623 }
1624
a66098da
LB		 1625 return rc;
1626}
1627
1628/*
04b147b1 1629 * CMD_GET_HW_SPEC (STA version).
a66098da 1630 */
04b147b1 1631struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1632 struct mwl8k_cmd_pkt header;
1633 __u8 hw_rev;
1634 __u8 host_interface;
1635 __le16 num_mcaddrs;
d89173f2 1636 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1637 __le16 region_code;
1638 __le32 fw_rev;
1639 __le32 ps_cookie;
1640 __le32 caps;
1641 __u8 mcs_bitmap[16];
1642 __le32 rx_queue_ptr;
1643 __le32 num_tx_queues;
1644 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1645 __le32 caps2;
1646 __le32 num_tx_desc_per_queue;
45eb400d 1647 __le32 total_rxd;
a66098da
LB		 1648} __attribute__((packed));
1649
04b147b1 1650static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1651{
1652 struct mwl8k_priv *priv = hw->priv;
04b147b1 1653 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1654 int rc;
1655 int i;
1656
1657 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1658 if (cmd == NULL)
1659 return -ENOMEM;
1660
1661 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1662 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1663
1664 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1665 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1666 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1667 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1668 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1669 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1670 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1671 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1672
1673 rc = mwl8k_post_cmd(hw, &cmd->header);
1674
1675 if (!rc) {
1676 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1677 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1678 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1679 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1680 }
1681
1682 kfree(cmd);
1683 return rc;
1684}
1685
42fba21d
LB		 1686/*
1687 * CMD_GET_HW_SPEC (AP version).
1688 */
1689struct mwl8k_cmd_get_hw_spec_ap {
1690 struct mwl8k_cmd_pkt header;
1691 __u8 hw_rev;
1692 __u8 host_interface;
1693 __le16 num_wcb;
1694 __le16 num_mcaddrs;
1695 __u8 perm_addr[ETH_ALEN];
1696 __le16 region_code;
1697 __le16 num_antenna;
1698 __le32 fw_rev;
1699 __le32 wcbbase0;
1700 __le32 rxwrptr;
1701 __le32 rxrdptr;
1702 __le32 ps_cookie;
1703 __le32 wcbbase1;
1704 __le32 wcbbase2;
1705 __le32 wcbbase3;
1706} __attribute__((packed));
1707
1708static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1709{
1710 struct mwl8k_priv *priv = hw->priv;
1711 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1712 int rc;
1713
1714 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1715 if (cmd == NULL)
1716 return -ENOMEM;
1717
1718 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1719 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1720
1721 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1722 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1723
1724 rc = mwl8k_post_cmd(hw, &cmd->header);
1725
1726 if (!rc) {
1727 int off;
1728
1729 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1730 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1731 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1732 priv->hw_rev = cmd->hw_rev;
1733
1734 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1735 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1736
1737 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1738 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1739
1740 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1741 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1742
1743 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1744 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1745
1746 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1747 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1748
1749 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1750 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1751 }
1752
1753 kfree(cmd);
1754 return rc;
1755}
1756
1757/*
1758 * CMD_SET_HW_SPEC.
1759 */
1760struct mwl8k_cmd_set_hw_spec {
1761 struct mwl8k_cmd_pkt header;
1762 __u8 hw_rev;
1763 __u8 host_interface;
1764 __le16 num_mcaddrs;
1765 __u8 perm_addr[ETH_ALEN];
1766 __le16 region_code;
1767 __le32 fw_rev;
1768 __le32 ps_cookie;
1769 __le32 caps;
1770 __le32 rx_queue_ptr;
1771 __le32 num_tx_queues;
1772 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1773 __le32 flags;
1774 __le32 num_tx_desc_per_queue;
1775 __le32 total_rxd;
1776} __attribute__((packed));
1777
1778#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1779
1780static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1781{
1782 struct mwl8k_priv *priv = hw->priv;
1783 struct mwl8k_cmd_set_hw_spec *cmd;
1784 int rc;
1785 int i;
1786
1787 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1788 if (cmd == NULL)
1789 return -ENOMEM;
1790
1791 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1792 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1793
1794 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1795 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1796 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1797 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1798 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
1799 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT);
1800 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1801 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1802
1803 rc = mwl8k_post_cmd(hw, &cmd->header);
1804 kfree(cmd);
1805
1806 return rc;
1807}
1808
a66098da
LB		 1809/*
1810 * CMD_MAC_MULTICAST_ADR.
1811 */
1812struct mwl8k_cmd_mac_multicast_adr {
1813 struct mwl8k_cmd_pkt header;
1814 __le16 action;
1815 __le16 numaddr;
ce9e2e1b 1816 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1817};
1818
d5e30845
LB		 1819#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1820#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1821#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1822#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1823
e81cd2d6 1824static struct mwl8k_cmd_pkt *
447ced07 1825__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1826 int mc_count, struct dev_addr_list *mclist)
a66098da 1827{
e81cd2d6 1828 struct mwl8k_priv *priv = hw->priv;
a66098da 1829 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1830 int size;
e81cd2d6 1831
447ced07 1832 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1833 allmulti = 1;
1834 mc_count = 0;
1835 }
e81cd2d6
LB		 1836
1837 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1838
e81cd2d6 1839 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1840 if (cmd == NULL)
e81cd2d6 1841 return NULL;
a66098da
LB		 1842
1843 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1844 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1845 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1846 MWL8K_ENABLE_RX_BROADCAST);
1847
1848 if (allmulti) {
1849 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1850 } else if (mc_count) {
1851 int i;
1852
1853 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1854 cmd->numaddr = cpu_to_le16(mc_count);
1855 for (i = 0; i < mc_count && mclist; i++) {
1856 if (mclist->da_addrlen != ETH_ALEN) {
1857 kfree(cmd);
1858 return NULL;
1859 }
1860 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1861 mclist = mclist->next;
a66098da 1862 }
a66098da
LB		 1863 }
1864
e81cd2d6 1865 return &cmd->header;
a66098da
LB		 1866}
1867
1868/*
1869 * CMD_802_11_GET_STAT.
1870 */
1871struct mwl8k_cmd_802_11_get_stat {
1872 struct mwl8k_cmd_pkt header;
a66098da
LB		 1873 __le32 stats[64];
1874} __attribute__((packed));
1875
1876#define MWL8K_STAT_ACK_FAILURE 9
1877#define MWL8K_STAT_RTS_FAILURE 12
1878#define MWL8K_STAT_FCS_ERROR 24
1879#define MWL8K_STAT_RTS_SUCCESS 11
1880
1881static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1882 struct ieee80211_low_level_stats *stats)
1883{
1884 struct mwl8k_cmd_802_11_get_stat *cmd;
1885 int rc;
1886
1887 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1888 if (cmd == NULL)
1889 return -ENOMEM;
1890
1891 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1892 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1893
1894 rc = mwl8k_post_cmd(hw, &cmd->header);
1895 if (!rc) {
1896 stats->dot11ACKFailureCount =
1897 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1898 stats->dot11RTSFailureCount =
1899 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1900 stats->dot11FCSErrorCount =
1901 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1902 stats->dot11RTSSuccessCount =
1903 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1904 }
1905 kfree(cmd);
1906
1907 return rc;
1908}
1909
1910/*
1911 * CMD_802_11_RADIO_CONTROL.
1912 */
1913struct mwl8k_cmd_802_11_radio_control {
1914 struct mwl8k_cmd_pkt header;
1915 __le16 action;
1916 __le16 control;
1917 __le16 radio_on;
1918} __attribute__((packed));
1919
c46563b7
LB		 1920static int
1921mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1922{
1923 struct mwl8k_priv *priv = hw->priv;
1924 struct mwl8k_cmd_802_11_radio_control *cmd;
1925 int rc;
1926
c46563b7 1927 if (enable == priv->radio_on && !force)
a66098da
LB		 1928 return 0;
1929
a66098da
LB		 1930 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1931 if (cmd == NULL)
1932 return -ENOMEM;
1933
1934 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1935 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1936 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1937 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1938 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1939
1940 rc = mwl8k_post_cmd(hw, &cmd->header);
1941 kfree(cmd);
1942
1943 if (!rc)
c46563b7 1944 priv->radio_on = enable;
a66098da
LB		 1945
1946 return rc;
1947}
1948
c46563b7
LB		 1949static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1950{
1951 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1952}
1953
1954static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1955{
1956 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1957}
1958
a66098da
LB		 1959static int
1960mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1961{
1962 struct mwl8k_priv *priv;
1963
1964 if (hw == NULL || hw->priv == NULL)
1965 return -EINVAL;
1966 priv = hw->priv;
1967
68ce3884 1968 priv->radio_short_preamble = short_preamble;
a66098da 1969
c46563b7 1970 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1971}
1972
1973/*
1974 * CMD_802_11_RF_TX_POWER.
1975 */
1976#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1977
1978struct mwl8k_cmd_802_11_rf_tx_power {
1979 struct mwl8k_cmd_pkt header;
1980 __le16 action;
1981 __le16 support_level;
1982 __le16 current_level;
1983 __le16 reserved;
1984 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1985} __attribute__((packed));
1986
1987static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1988{
1989 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1990 int rc;
1991
1992 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1993 if (cmd == NULL)
1994 return -ENOMEM;
1995
1996 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1997 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1998 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1999 cmd->support_level = cpu_to_le16(dBm);
2000
2001 rc = mwl8k_post_cmd(hw, &cmd->header);
2002 kfree(cmd);
2003
2004 return rc;
2005}
2006
08b06347
LB		 2007/*
2008 * CMD_RF_ANTENNA.
2009 */
2010struct mwl8k_cmd_rf_antenna {
2011 struct mwl8k_cmd_pkt header;
2012 __le16 antenna;
2013 __le16 mode;
2014} __attribute__((packed));
2015
2016#define MWL8K_RF_ANTENNA_RX 1
2017#define MWL8K_RF_ANTENNA_TX 2
2018
2019static int
2020mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2021{
2022 struct mwl8k_cmd_rf_antenna *cmd;
2023 int rc;
2024
2025 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2026 if (cmd == NULL)
2027 return -ENOMEM;
2028
2029 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2030 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2031 cmd->antenna = cpu_to_le16(antenna);
2032 cmd->mode = cpu_to_le16(mask);
2033
2034 rc = mwl8k_post_cmd(hw, &cmd->header);
2035 kfree(cmd);
2036
2037 return rc;
2038}
2039
a66098da
LB		 2040/*
2041 * CMD_SET_PRE_SCAN.
2042 */
2043struct mwl8k_cmd_set_pre_scan {
2044 struct mwl8k_cmd_pkt header;
2045} __attribute__((packed));
2046
2047static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2048{
2049 struct mwl8k_cmd_set_pre_scan *cmd;
2050 int rc;
2051
2052 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2053 if (cmd == NULL)
2054 return -ENOMEM;
2055
2056 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2057 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2058
2059 rc = mwl8k_post_cmd(hw, &cmd->header);
2060 kfree(cmd);
2061
2062 return rc;
2063}
2064
2065/*
2066 * CMD_SET_POST_SCAN.
2067 */
2068struct mwl8k_cmd_set_post_scan {
2069 struct mwl8k_cmd_pkt header;
2070 __le32 isibss;
d89173f2 2071 __u8 bssid[ETH_ALEN];
a66098da
LB		 2072} __attribute__((packed));
2073
2074static int
ce9e2e1b 2075mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 2076{
2077 struct mwl8k_cmd_set_post_scan *cmd;
2078 int rc;
2079
2080 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2081 if (cmd == NULL)
2082 return -ENOMEM;
2083
2084 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2085 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2086 cmd->isibss = 0;
d89173f2 2087 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2088
2089 rc = mwl8k_post_cmd(hw, &cmd->header);
2090 kfree(cmd);
2091
2092 return rc;
2093}
2094
2095/*
2096 * CMD_SET_RF_CHANNEL.
2097 */
2098struct mwl8k_cmd_set_rf_channel {
2099 struct mwl8k_cmd_pkt header;
2100 __le16 action;
2101 __u8 current_channel;
2102 __le32 channel_flags;
2103} __attribute__((packed));
2104
2105static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
2106 struct ieee80211_channel *channel)
2107{
2108 struct mwl8k_cmd_set_rf_channel *cmd;
2109 int rc;
2110
2111 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2112 if (cmd == NULL)
2113 return -ENOMEM;
2114
2115 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2116 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2117 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2118 cmd->current_channel = channel->hw_value;
2119 if (channel->band == IEEE80211_BAND_2GHZ)
2120 cmd->channel_flags = cpu_to_le32(0x00000081);
2121 else
2122 cmd->channel_flags = cpu_to_le32(0x00000000);
2123
2124 rc = mwl8k_post_cmd(hw, &cmd->header);
2125 kfree(cmd);
2126
2127 return rc;
2128}
2129
2130/*
2131 * CMD_SET_SLOT.
2132 */
2133struct mwl8k_cmd_set_slot {
2134 struct mwl8k_cmd_pkt header;
2135 __le16 action;
2136 __u8 short_slot;
2137} __attribute__((packed));
2138
5539bb51 2139static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 2140{
2141 struct mwl8k_cmd_set_slot *cmd;
2142 int rc;
2143
2144 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2145 if (cmd == NULL)
2146 return -ENOMEM;
2147
2148 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
2149 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2150 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 2151 cmd->short_slot = short_slot_time;
a66098da
LB		 2152
2153 rc = mwl8k_post_cmd(hw, &cmd->header);
2154 kfree(cmd);
2155
2156 return rc;
2157}
2158
2159/*
2160 * CMD_MIMO_CONFIG.
2161 */
2162struct mwl8k_cmd_mimo_config {
2163 struct mwl8k_cmd_pkt header;
2164 __le32 action;
2165 __u8 rx_antenna_map;
2166 __u8 tx_antenna_map;
2167} __attribute__((packed));
2168
2169static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
2170{
2171 struct mwl8k_cmd_mimo_config *cmd;
2172 int rc;
2173
2174 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2175 if (cmd == NULL)
2176 return -ENOMEM;
2177
2178 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
2179 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2180 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2181 cmd->rx_antenna_map = rx;
2182 cmd->tx_antenna_map = tx;
2183
2184 rc = mwl8k_post_cmd(hw, &cmd->header);
2185 kfree(cmd);
2186
2187 return rc;
2188}
2189
2190/*
2191 * CMD_ENABLE_SNIFFER.
2192 */
2193struct mwl8k_cmd_enable_sniffer {
2194 struct mwl8k_cmd_pkt header;
2195 __le32 action;
2196} __attribute__((packed));
2197
2198static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2199{
2200 struct mwl8k_cmd_enable_sniffer *cmd;
2201 int rc;
2202
2203 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2204 if (cmd == NULL)
2205 return -ENOMEM;
2206
2207 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2208 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2209 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 2210
2211 rc = mwl8k_post_cmd(hw, &cmd->header);
2212 kfree(cmd);
2213
2214 return rc;
2215}
2216
32060e1b
LB		 2217/*
2218 * CMD_SET_MAC_ADDR.
2219 */
2220struct mwl8k_cmd_set_mac_addr {
2221 struct mwl8k_cmd_pkt header;
259a8e7d
LB		 2222 union {
2223 struct {
2224 __le16 mac_type;
2225 __u8 mac_addr[ETH_ALEN];
2226 } mbss;
2227 __u8 mac_addr[ETH_ALEN];
2228 };
32060e1b
LB		 2229} __attribute__((packed));
2230
2231static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2232{
259a8e7d 2233 struct mwl8k_priv *priv = hw->priv;
32060e1b
LB		 2234 struct mwl8k_cmd_set_mac_addr *cmd;
2235 int rc;
2236
2237 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2238 if (cmd == NULL)
2239 return -ENOMEM;
2240
2241 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2242 cmd->header.length = cpu_to_le16(sizeof(*cmd));
259a8e7d
LB		 2243 if (priv->ap_fw) {
2244 cmd->mbss.mac_type = 0;
2245 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2246 } else {
2247 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2248 }
32060e1b
LB		 2249
2250 rc = mwl8k_post_cmd(hw, &cmd->header);
2251 kfree(cmd);
2252
2253 return rc;
2254}
2255
2256
a66098da 2257/*
ce9e2e1b 2258 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2259 */
2260struct mwl8k_cmd_set_rate_adapt_mode {
2261 struct mwl8k_cmd_pkt header;
2262 __le16 action;
2263 __le16 mode;
2264} __attribute__((packed));
2265
2266static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2267{
2268 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2269 int rc;
2270
2271 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2272 if (cmd == NULL)
2273 return -ENOMEM;
2274
2275 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2276 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2277 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2278 cmd->mode = cpu_to_le16(mode);
2279
2280 rc = mwl8k_post_cmd(hw, &cmd->header);
2281 kfree(cmd);
2282
2283 return rc;
2284}
2285
2286/*
2287 * CMD_SET_WMM_MODE.
2288 */
2289struct mwl8k_cmd_set_wmm {
2290 struct mwl8k_cmd_pkt header;
2291 __le16 action;
2292} __attribute__((packed));
2293
2294static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2295{
2296 struct mwl8k_priv *priv = hw->priv;
2297 struct mwl8k_cmd_set_wmm *cmd;
2298 int rc;
2299
2300 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2301 if (cmd == NULL)
2302 return -ENOMEM;
2303
2304 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2305 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2306 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2307
2308 rc = mwl8k_post_cmd(hw, &cmd->header);
2309 kfree(cmd);
2310
2311 if (!rc)
0439b1f5 2312 priv->wmm_enabled = enable;
a66098da
LB		 2313
2314 return rc;
2315}
2316
2317/*
2318 * CMD_SET_RTS_THRESHOLD.
2319 */
2320struct mwl8k_cmd_rts_threshold {
2321 struct mwl8k_cmd_pkt header;
2322 __le16 action;
2323 __le16 threshold;
2324} __attribute__((packed));
2325
2326static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2327 u16 action, u16 threshold)
a66098da
LB		 2328{
2329 struct mwl8k_cmd_rts_threshold *cmd;
2330 int rc;
2331
2332 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2333 if (cmd == NULL)
2334 return -ENOMEM;
2335
2336 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2337 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2338 cmd->action = cpu_to_le16(action);
733d3067 2339 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2340
2341 rc = mwl8k_post_cmd(hw, &cmd->header);
2342 kfree(cmd);
2343
2344 return rc;
2345}
2346
2347/*
2348 * CMD_SET_EDCA_PARAMS.
2349 */
2350struct mwl8k_cmd_set_edca_params {
2351 struct mwl8k_cmd_pkt header;
2352
2353 /* See MWL8K_SET_EDCA_XXX below */
2354 __le16 action;
2355
2356 /* TX opportunity in units of 32 us */
2357 __le16 txop;
2358
2e484c89
LB		 2359 union {
2360 struct {
2361 /* Log exponent of max contention period: 0...15 */
2362 __le32 log_cw_max;
2363
2364 /* Log exponent of min contention period: 0...15 */
2365 __le32 log_cw_min;
2366
2367 /* Adaptive interframe spacing in units of 32us */
2368 __u8 aifs;
2369
2370 /* TX queue to configure */
2371 __u8 txq;
2372 } ap;
2373 struct {
2374 /* Log exponent of max contention period: 0...15 */
2375 __u8 log_cw_max;
a66098da 2376
2e484c89
LB		 2377 /* Log exponent of min contention period: 0...15 */
2378 __u8 log_cw_min;
a66098da 2379
2e484c89
LB		 2380 /* Adaptive interframe spacing in units of 32us */
2381 __u8 aifs;
a66098da 2382
2e484c89
LB		 2383 /* TX queue to configure */
2384 __u8 txq;
2385 } sta;
2386 };
a66098da
LB		 2387} __attribute__((packed));
2388
a66098da
LB		 2389#define MWL8K_SET_EDCA_CW 0x01
2390#define MWL8K_SET_EDCA_TXOP 0x02
2391#define MWL8K_SET_EDCA_AIFS 0x04
2392
2393#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2394 MWL8K_SET_EDCA_TXOP | \
2395 MWL8K_SET_EDCA_AIFS)
2396
2397static int
2398mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2399 __u16 cw_min, __u16 cw_max,
2400 __u8 aifs, __u16 txop)
2401{
2e484c89 2402 struct mwl8k_priv *priv = hw->priv;
a66098da 2403 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2404 int rc;
2405
2406 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2407 if (cmd == NULL)
2408 return -ENOMEM;
2409
22995b24
LB		 2410 /*
2411 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2412 * this call.
2413 */
2414 qnum ^= !(qnum >> 1);
2415
a66098da
LB		 2416 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2417 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2418 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2419 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2420 if (priv->ap_fw) {
2421 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2422 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2423 cmd->ap.aifs = aifs;
2424 cmd->ap.txq = qnum;
2425 } else {
2426 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2427 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2428 cmd->sta.aifs = aifs;
2429 cmd->sta.txq = qnum;
2430 }
a66098da
LB		 2431
2432 rc = mwl8k_post_cmd(hw, &cmd->header);
2433 kfree(cmd);
2434
2435 return rc;
2436}
2437
2438/*
2439 * CMD_FINALIZE_JOIN.
2440 */
2441
2442/* FJ beacon buffer size is compiled into the firmware. */
2443#define MWL8K_FJ_BEACON_MAXLEN 128
2444
2445struct mwl8k_cmd_finalize_join {
2446 struct mwl8k_cmd_pkt header;
2447 __le32 sleep_interval; /* Number of beacon periods to sleep */
2448 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2449} __attribute__((packed));
2450
2451static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2452 __u16 framelen, __u16 dtim)
2453{
2454 struct mwl8k_cmd_finalize_join *cmd;
2455 struct ieee80211_mgmt *payload = frame;
2456 u16 hdrlen;
2457 u32 payload_len;
2458 int rc;
2459
2460 if (frame == NULL)
2461 return -EINVAL;
2462
2463 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2464 if (cmd == NULL)
2465 return -ENOMEM;
2466
2467 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2468 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2469 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2470
2471 hdrlen = ieee80211_hdrlen(payload->frame_control);
2472
2473 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2474
2475 /* XXX TBD Might just have to abort and return an error */
2476 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2477 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2478 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2479 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2480
ce9e2e1b
LB		 2481 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2482 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2483
2484 if (payload && payload_len)
2485 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2486
2487 rc = mwl8k_post_cmd(hw, &cmd->header);
2488 kfree(cmd);
2489 return rc;
2490}
2491
2492/*
2493 * CMD_UPDATE_STADB.
2494 */
2495struct mwl8k_cmd_update_sta_db {
2496 struct mwl8k_cmd_pkt header;
2497
2498 /* See STADB_ACTION_TYPE */
2499 __le32 action;
2500
2501 /* Peer MAC address */
d89173f2 2502 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2503
2504 __le32 reserved;
2505
2506 /* Peer info - valid during add/update. */
2507 struct peer_capability_info peer_info;
2508} __attribute__((packed));
2509
2510static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2511 struct ieee80211_vif *vif, __u32 action)
2512{
2513 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2514 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2515 struct mwl8k_cmd_update_sta_db *cmd;
2516 struct peer_capability_info *peer_info;
2517 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2518 int rc;
2519 __u8 count, *rates;
2520
2521 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2522 if (cmd == NULL)
2523 return -ENOMEM;
2524
2525 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2526 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2527
2528 cmd->action = cpu_to_le32(action);
2529 peer_info = &cmd->peer_info;
d89173f2 2530 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2531
2532 switch (action) {
2533 case MWL8K_STA_DB_ADD_ENTRY:
2534 case MWL8K_STA_DB_MODIFY_ENTRY:
2535 /* Build peer_info block */
2536 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2537 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2538 peer_info->interop = 1;
2539 peer_info->amsdu_enabled = 0;
2540
2541 rates = peer_info->legacy_rates;
ce9e2e1b 2542 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2543 rates[count] = bitrates[count].hw_value;
2544
2545 rc = mwl8k_post_cmd(hw, &cmd->header);
2546 if (rc == 0)
2547 mv_vif->peer_id = peer_info->station_id;
2548
2549 break;
2550
2551 case MWL8K_STA_DB_DEL_ENTRY:
2552 case MWL8K_STA_DB_FLUSH:
2553 default:
2554 rc = mwl8k_post_cmd(hw, &cmd->header);
2555 if (rc == 0)
2556 mv_vif->peer_id = 0;
2557 break;
2558 }
2559 kfree(cmd);
2560
2561 return rc;
2562}
2563
2564/*
2565 * CMD_SET_AID.
2566 */
a66098da
LB		 2567#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2568
2569#define MWL8K_FRAME_PROT_DISABLED 0x00
2570#define MWL8K_FRAME_PROT_11G 0x07
2571#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2572#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2573
2574struct mwl8k_cmd_update_set_aid {
2575 struct mwl8k_cmd_pkt header;
2576 __le16 aid;
2577
2578 /* AP's MAC address (BSSID) */
d89173f2 2579 __u8 bssid[ETH_ALEN];
a66098da
LB		 2580 __le16 protection_mode;
2581 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2582} __attribute__((packed));
2583
2584static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2585 struct ieee80211_vif *vif)
2586{
2587 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2588 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2589 struct mwl8k_cmd_update_set_aid *cmd;
2590 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2591 int count;
2592 u16 prot_mode;
2593 int rc;
2594
2595 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2596 if (cmd == NULL)
2597 return -ENOMEM;
2598
2599 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2600 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2601 cmd->aid = cpu_to_le16(info->aid);
2602
d89173f2 2603 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2604
a66098da
LB		 2605 if (info->use_cts_prot) {
2606 prot_mode = MWL8K_FRAME_PROT_11G;
2607 } else {
9ed6bcce 2608 switch (info->ht_operation_mode &
a66098da
LB		 2609 IEEE80211_HT_OP_MODE_PROTECTION) {
2610 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2611 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2612 break;
2613 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2614 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2615 break;
2616 default:
2617 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2618 break;
2619 }
2620 }
a66098da
LB		 2621 cmd->protection_mode = cpu_to_le16(prot_mode);
2622
2623 for (count = 0; count < mv_vif->legacy_nrates; count++)
2624 cmd->supp_rates[count] = bitrates[count].hw_value;
2625
2626 rc = mwl8k_post_cmd(hw, &cmd->header);
2627 kfree(cmd);
2628
2629 return rc;
2630}
2631
2632/*
2633 * CMD_SET_RATE.
2634 */
2635struct mwl8k_cmd_update_rateset {
2636 struct mwl8k_cmd_pkt header;
2637 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2638
2639 /* Bitmap for supported MCS codes. */
0b5351a8
LB		 2640 __u8 mcs_set[16];
2641 __u8 reserved[16];
a66098da
LB		 2642} __attribute__((packed));
2643
2644static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2645 struct ieee80211_vif *vif)
2646{
2647 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2648 struct mwl8k_cmd_update_rateset *cmd;
2649 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2650 int count;
2651 int rc;
2652
2653 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2654 if (cmd == NULL)
2655 return -ENOMEM;
2656
2657 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2658 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2659
2660 for (count = 0; count < mv_vif->legacy_nrates; count++)
2661 cmd->legacy_rates[count] = bitrates[count].hw_value;
2662
2663 rc = mwl8k_post_cmd(hw, &cmd->header);
2664 kfree(cmd);
2665
2666 return rc;
2667}
2668
2669/*
2670 * CMD_USE_FIXED_RATE.
2671 */
2672#define MWL8K_RATE_TABLE_SIZE 8
2673#define MWL8K_UCAST_RATE 0
a66098da
LB		 2674#define MWL8K_USE_AUTO_RATE 0x0002
2675
2676struct mwl8k_rate_entry {
2677 /* Set to 1 if HT rate, 0 if legacy. */
2678 __le32 is_ht_rate;
2679
2680 /* Set to 1 to use retry_count field. */
2681 __le32 enable_retry;
2682
2683 /* Specified legacy rate or MCS. */
2684 __le32 rate;
2685
2686 /* Number of allowed retries. */
2687 __le32 retry_count;
2688} __attribute__((packed));
2689
2690struct mwl8k_rate_table {
2691 /* 1 to allow specified rate and below */
2692 __le32 allow_rate_drop;
2693 __le32 num_rates;
2694 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2695} __attribute__((packed));
2696
2697struct mwl8k_cmd_use_fixed_rate {
2698 struct mwl8k_cmd_pkt header;
2699 __le32 action;
2700 struct mwl8k_rate_table rate_table;
2701
2702 /* Unicast, Broadcast or Multicast */
2703 __le32 rate_type;
2704 __le32 reserved1;
2705 __le32 reserved2;
2706} __attribute__((packed));
2707
2708static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2709 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2710{
2711 struct mwl8k_cmd_use_fixed_rate *cmd;
2712 int count;
2713 int rc;
2714
2715 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2716 if (cmd == NULL)
2717 return -ENOMEM;
2718
2719 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2720 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2721
2722 cmd->action = cpu_to_le32(action);
2723 cmd->rate_type = cpu_to_le32(rate_type);
2724
2725 if (rate_table != NULL) {
c2c357ce
LB		 2726 /*
2727 * Copy over each field manually so that endian
2728 * conversion can be done.
2729 */
a66098da
LB		 2730 cmd->rate_table.allow_rate_drop =
2731 cpu_to_le32(rate_table->allow_rate_drop);
2732 cmd->rate_table.num_rates =
2733 cpu_to_le32(rate_table->num_rates);
2734
2735 for (count = 0; count < rate_table->num_rates; count++) {
2736 struct mwl8k_rate_entry *dst =
2737 &cmd->rate_table.rate_entry[count];
2738 struct mwl8k_rate_entry *src =
2739 &rate_table->rate_entry[count];
2740
2741 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2742 dst->enable_retry = cpu_to_le32(src->enable_retry);
2743 dst->rate = cpu_to_le32(src->rate);
2744 dst->retry_count = cpu_to_le32(src->retry_count);
2745 }
2746 }
2747
2748 rc = mwl8k_post_cmd(hw, &cmd->header);
2749 kfree(cmd);
2750
2751 return rc;
2752}
2753
2754
2755/*
2756 * Interrupt handling.
2757 */
2758static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2759{
2760 struct ieee80211_hw *hw = dev_id;
2761 struct mwl8k_priv *priv = hw->priv;
2762 u32 status;
2763
2764 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2765 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2766
a66098da
LB		 2767 if (!status)
2768 return IRQ_NONE;
2769
2770 if (status & MWL8K_A2H_INT_TX_DONE)
2771 tasklet_schedule(&priv->tx_reclaim_task);
2772
2773 if (status & MWL8K_A2H_INT_RX_READY) {
2774 while (rxq_process(hw, 0, 1))
2775 rxq_refill(hw, 0, 1);
2776 }
2777
2778 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2779 if (priv->hostcmd_wait != NULL)
a66098da 2780 complete(priv->hostcmd_wait);
a66098da
LB		 2781 }
2782
2783 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2784 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2785 priv->radio_on && priv->pending_tx_pkts)
618952a7 2786 mwl8k_tx_start(priv);
a66098da
LB		 2787 }
2788
2789 return IRQ_HANDLED;
2790}
2791
2792
2793/*
2794 * Core driver operations.
2795 */
2796static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2797{
2798 struct mwl8k_priv *priv = hw->priv;
2799 int index = skb_get_queue_mapping(skb);
2800 int rc;
2801
2802 if (priv->current_channel == NULL) {
2803 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2804 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2805 dev_kfree_skb(skb);
2806 return NETDEV_TX_OK;
2807 }
2808
2809 rc = mwl8k_txq_xmit(hw, index, skb);
2810
2811 return rc;
2812}
2813
a66098da
LB		 2814static int mwl8k_start(struct ieee80211_hw *hw)
2815{
a66098da
LB		 2816 struct mwl8k_priv *priv = hw->priv;
2817 int rc;
2818
a0607fd3 2819 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 2820 IRQF_SHARED, MWL8K_NAME, hw);
2821 if (rc) {
2822 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2823 wiphy_name(hw->wiphy));
2ec610cb 2824 return -EIO;
a66098da
LB		 2825 }
2826
2ec610cb
LB		 2827 /* Enable tx reclaim tasklet */
2828 tasklet_enable(&priv->tx_reclaim_task);
2829
a66098da 2830 /* Enable interrupts */
c23b5a69 2831 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2832
2ec610cb
LB		 2833 rc = mwl8k_fw_lock(hw);
2834 if (!rc) {
2835 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2836
5e4cf166
LB		 2837 if (!priv->ap_fw) {
2838 if (!rc)
2839 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2840
5e4cf166
LB		 2841 if (!rc)
2842 rc = mwl8k_cmd_set_pre_scan(hw);
2843
2844 if (!rc)
2845 rc = mwl8k_cmd_set_post_scan(hw,
2846 "\x00\x00\x00\x00\x00\x00");
2847 }
2ec610cb
LB		 2848
2849 if (!rc)
2850 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2851
2ec610cb
LB		 2852 if (!rc)
2853 rc = mwl8k_set_wmm(hw, 0);
a66098da 2854
2ec610cb
LB		 2855 mwl8k_fw_unlock(hw);
2856 }
2857
2858 if (rc) {
2859 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2860 free_irq(priv->pdev->irq, hw);
2861 tasklet_disable(&priv->tx_reclaim_task);
2862 }
a66098da
LB		 2863
2864 return rc;
2865}
2866
a66098da
LB		 2867static void mwl8k_stop(struct ieee80211_hw *hw)
2868{
a66098da
LB		 2869 struct mwl8k_priv *priv = hw->priv;
2870 int i;
2871
d3cea0b8 2872 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2873
2874 ieee80211_stop_queues(hw);
2875
a66098da 2876 /* Disable interrupts */
a66098da 2877 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2878 free_irq(priv->pdev->irq, hw);
2879
2880 /* Stop finalize join worker */
2881 cancel_work_sync(&priv->finalize_join_worker);
2882 if (priv->beacon_skb != NULL)
2883 dev_kfree_skb(priv->beacon_skb);
2884
2885 /* Stop tx reclaim tasklet */
2886 tasklet_disable(&priv->tx_reclaim_task);
2887
a66098da
LB		 2888 /* Return all skbs to mac80211 */
2889 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2890 mwl8k_txq_reclaim(hw, i, 1);
2891}
2892
2893static int mwl8k_add_interface(struct ieee80211_hw *hw,
2894 struct ieee80211_if_init_conf *conf)
2895{
2896 struct mwl8k_priv *priv = hw->priv;
2897 struct mwl8k_vif *mwl8k_vif;
2898
2899 /*
2900 * We only support one active interface at a time.
2901 */
2902 if (priv->vif != NULL)
2903 return -EBUSY;
2904
2905 /*
2906 * We only support managed interfaces for now.
2907 */
240e86ef 2908 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2909 return -EINVAL;
2910
a43c49a8
LB		 2911 /*
2912 * Reject interface creation if sniffer mode is active, as
2913 * STA operation is mutually exclusive with hardware sniffer
2914 * mode.
2915 */
2916 if (priv->sniffer_enabled) {
2917 printk(KERN_INFO "%s: unable to create STA "
2918 "interface due to sniffer mode being enabled\n",
2919 wiphy_name(hw->wiphy));
2920 return -EINVAL;
2921 }
2922
a66098da
LB		 2923 /* Clean out driver private area */
2924 mwl8k_vif = MWL8K_VIF(conf->vif);
2925 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2926
32060e1b
LB		 2927 /* Set and save the mac address */
2928 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2929 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2930
2931 /* Back pointer to parent config block */
2932 mwl8k_vif->priv = priv;
2933
2934 /* Setup initial PHY parameters */
ce9e2e1b 2935 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2936 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2937 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2938
2939 /* Set Initial sequence number to zero */
2940 mwl8k_vif->seqno = 0;
2941
2942 priv->vif = conf->vif;
2943 priv->current_channel = NULL;
2944
2945 return 0;
2946}
2947
2948static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2949 struct ieee80211_if_init_conf *conf)
2950{
2951 struct mwl8k_priv *priv = hw->priv;
2952
2953 if (priv->vif == NULL)
2954 return;
2955
32060e1b
LB		 2956 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2957
a66098da
LB		 2958 priv->vif = NULL;
2959}
2960
ee03a932 2961static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2962{
a66098da
LB		 2963 struct ieee80211_conf *conf = &hw->conf;
2964 struct mwl8k_priv *priv = hw->priv;
ee03a932 2965 int rc;
a66098da 2966
7595d67a
LB		 2967 if (conf->flags & IEEE80211_CONF_IDLE) {
2968 mwl8k_cmd_802_11_radio_disable(hw);
2969 priv->current_channel = NULL;
ee03a932 2970 return 0;
7595d67a
LB		 2971 }
2972
ee03a932
LB		 2973 rc = mwl8k_fw_lock(hw);
2974 if (rc)
2975 return rc;
a66098da 2976
ee03a932
LB		 2977 rc = mwl8k_cmd_802_11_radio_enable(hw);
2978 if (rc)
2979 goto out;
a66098da 2980
ee03a932
LB		 2981 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2982 if (rc)
2983 goto out;
2984
2985 priv->current_channel = conf->channel;
a66098da
LB		 2986
2987 if (conf->power_level > 18)
2988 conf->power_level = 18;
ee03a932
LB		 2989 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2990 if (rc)
2991 goto out;
a66098da 2992
08b06347
LB		 2993 if (priv->ap_fw) {
2994 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
2995 if (!rc)
2996 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
2997 } else {
2998 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
2999 }
a66098da 3000
ee03a932
LB		 3001out:
3002 mwl8k_fw_unlock(hw);
a66098da 3003
ee03a932 3004 return rc;
a66098da
LB		 3005}
3006
3a980d0a
LB		 3007static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
3008 struct ieee80211_vif *vif,
3009 struct ieee80211_bss_conf *info,
3010 u32 changed)
a66098da 3011{
a66098da
LB		 3012 struct mwl8k_priv *priv = hw->priv;
3013 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 3014 int rc;
3015
3016 if (changed & BSS_CHANGED_BSSID)
3017 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
3018
3019 if ((changed & BSS_CHANGED_ASSOC) == 0)
3020 return;
a66098da 3021
a66098da
LB		 3022 priv->capture_beacon = false;
3023
3a980d0a 3024 rc = mwl8k_fw_lock(hw);
942457d6 3025 if (rc)
3a980d0a
LB		 3026 return;
3027
a66098da
LB		 3028 if (info->assoc) {
3029 memcpy(&mwl8k_vif->bss_info, info,
3030 sizeof(struct ieee80211_bss_conf));
3031
3032 /* Install rates */
3a980d0a
LB		 3033 rc = mwl8k_update_rateset(hw, vif);
3034 if (rc)
3035 goto out;
a66098da
LB		 3036
3037 /* Turn on rate adaptation */
3a980d0a
LB		 3038 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
3039 MWL8K_UCAST_RATE, NULL);
3040 if (rc)
3041 goto out;
a66098da
LB		 3042
3043 /* Set radio preamble */
3a980d0a
LB		 3044 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
3045 if (rc)
3046 goto out;
a66098da
LB		 3047
3048 /* Set slot time */
3a980d0a
LB		 3049 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
3050 if (rc)
3051 goto out;
a66098da
LB		 3052
3053 /* Update peer rate info */
3a980d0a
LB		 3054 rc = mwl8k_cmd_update_sta_db(hw, vif,
3055 MWL8K_STA_DB_MODIFY_ENTRY);
3056 if (rc)
3057 goto out;
a66098da
LB		 3058
3059 /* Set AID */
3a980d0a
LB		 3060 rc = mwl8k_cmd_set_aid(hw, vif);
3061 if (rc)
3062 goto out;
a66098da
LB		 3063
3064 /*
3065 * Finalize the join. Tell rx handler to process
3066 * next beacon from our BSSID.
3067 */
d89173f2 3068 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 3069 priv->capture_beacon = true;
3070 } else {
3a980d0a 3071 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 3072 memset(&mwl8k_vif->bss_info, 0,
3073 sizeof(struct ieee80211_bss_conf));
d89173f2 3074 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 3075 }
3076
3a980d0a
LB		 3077out:
3078 mwl8k_fw_unlock(hw);
a66098da
LB		 3079}
3080
e81cd2d6
LB		 3081static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3082 int mc_count, struct dev_addr_list *mclist)
3083{
3084 struct mwl8k_cmd_pkt *cmd;
3085
447ced07
LB		 3086 /*
3087 * Synthesize and return a command packet that programs the
3088 * hardware multicast address filter. At this point we don't
3089 * know whether FIF_ALLMULTI is being requested, but if it is,
3090 * we'll end up throwing this packet away and creating a new
3091 * one in mwl8k_configure_filter().
3092 */
3093 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3094
3095 return (unsigned long)cmd;
3096}
3097
a43c49a8
LB		 3098static int
3099mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3100 unsigned int changed_flags,
3101 unsigned int *total_flags)
3102{
3103 struct mwl8k_priv *priv = hw->priv;
3104
3105 /*
3106 * Hardware sniffer mode is mutually exclusive with STA
3107 * operation, so refuse to enable sniffer mode if a STA
3108 * interface is active.
3109 */
3110 if (priv->vif != NULL) {
3111 if (net_ratelimit())
3112 printk(KERN_INFO "%s: not enabling sniffer "
3113 "mode because STA interface is active\n",
3114 wiphy_name(hw->wiphy));
3115 return 0;
3116 }
3117
3118 if (!priv->sniffer_enabled) {
3119 if (mwl8k_enable_sniffer(hw, 1))
3120 return 0;
3121 priv->sniffer_enabled = true;
3122 }
3123
3124 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3125 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3126 FIF_OTHER_BSS;
3127
3128 return 1;
3129}
3130
e6935ea1
LB		 3131static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3132 unsigned int changed_flags,
3133 unsigned int *total_flags,
3134 u64 multicast)
3135{
3136 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3137 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3138
c0adae2c
LB		 3139 /*
3140 * AP firmware doesn't allow fine-grained control over
3141 * the receive filter.
3142 */
3143 if (priv->ap_fw) {
3144 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3145 kfree(cmd);
3146 return;
3147 }
3148
a43c49a8
LB		 3149 /*
3150 * Enable hardware sniffer mode if FIF_CONTROL or
3151 * FIF_OTHER_BSS is requested.
3152 */
3153 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3154 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3155 kfree(cmd);
3156 return;
3157 }
a66098da 3158
e6935ea1 3159 /* Clear unsupported feature flags */
447ced07 3160 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3161
e6935ea1
LB		 3162 if (mwl8k_fw_lock(hw))
3163 return;
a66098da 3164
a43c49a8
LB		 3165 if (priv->sniffer_enabled) {
3166 mwl8k_enable_sniffer(hw, 0);
3167 priv->sniffer_enabled = false;
3168 }
3169
e6935ea1 3170 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3171 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3172 /*
3173 * Disable the BSS filter.
3174 */
e6935ea1 3175 mwl8k_cmd_set_pre_scan(hw);
77165d88 3176 } else {
a94cc97e
LB		 3177 u8 *bssid;
3178
77165d88
LB		 3179 /*
3180 * Enable the BSS filter.
3181 *
3182 * If there is an active STA interface, use that
3183 * interface's BSSID, otherwise use a dummy one
3184 * (where the OUI part needs to be nonzero for
3185 * the BSSID to be accepted by POST_SCAN).
3186 */
3187 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 3188 if (priv->vif != NULL)
3189 bssid = MWL8K_VIF(priv->vif)->bssid;
3190
e6935ea1 3191 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3192 }
3193 }
3194
447ced07
LB		 3195 /*
3196 * If FIF_ALLMULTI is being requested, throw away the command
3197 * packet that ->prepare_multicast() built and replace it with
3198 * a command packet that enables reception of all multicast
3199 * packets.
3200 */
3201 if (*total_flags & FIF_ALLMULTI) {
3202 kfree(cmd);
3203 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3204 }
3205
3206 if (cmd != NULL) {
3207 mwl8k_post_cmd(hw, cmd);
3208 kfree(cmd);
e6935ea1 3209 }
a66098da 3210
e6935ea1 3211 mwl8k_fw_unlock(hw);
a66098da
LB		 3212}
3213
a66098da
LB		 3214static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3215{
733d3067 3216 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 3217}
3218
a66098da
LB		 3219static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3220 const struct ieee80211_tx_queue_params *params)
3221{
3e4f542c 3222 struct mwl8k_priv *priv = hw->priv;
a66098da 3223 int rc;
a66098da 3224
3e4f542c
LB		 3225 rc = mwl8k_fw_lock(hw);
3226 if (!rc) {
3227 if (!priv->wmm_enabled)
3228 rc = mwl8k_set_wmm(hw, 1);
a66098da 3229
3e4f542c
LB		 3230 if (!rc)
3231 rc = mwl8k_set_edca_params(hw, queue,
3232 params->cw_min,
3233 params->cw_max,
3234 params->aifs,
3235 params->txop);
3236
3237 mwl8k_fw_unlock(hw);
a66098da 3238 }
3e4f542c 3239
a66098da
LB		 3240 return rc;
3241}
3242
3243static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3244 struct ieee80211_tx_queue_stats *stats)
3245{
3246 struct mwl8k_priv *priv = hw->priv;
3247 struct mwl8k_tx_queue *txq;
3248 int index;
3249
3250 spin_lock_bh(&priv->tx_lock);
3251 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3252 txq = priv->txq + index;
45eb400d 3253 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3254 sizeof(struct ieee80211_tx_queue_stats));
3255 }
3256 spin_unlock_bh(&priv->tx_lock);
a66098da 3257
954ef509 3258 return 0;
a66098da
LB		 3259}
3260
3261static int mwl8k_get_stats(struct ieee80211_hw *hw,
3262 struct ieee80211_low_level_stats *stats)
3263{
954ef509 3264 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 3265}
3266
3267static const struct ieee80211_ops mwl8k_ops = {
3268 .tx = mwl8k_tx,
3269 .start = mwl8k_start,
3270 .stop = mwl8k_stop,
3271 .add_interface = mwl8k_add_interface,
3272 .remove_interface = mwl8k_remove_interface,
3273 .config = mwl8k_config,
a66098da 3274 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3275 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3276 .configure_filter = mwl8k_configure_filter,
3277 .set_rts_threshold = mwl8k_set_rts_threshold,
3278 .conf_tx = mwl8k_conf_tx,
3279 .get_tx_stats = mwl8k_get_tx_stats,
3280 .get_stats = mwl8k_get_stats,
3281};
3282
3283static void mwl8k_tx_reclaim_handler(unsigned long data)
3284{
3285 int i;
3286 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
3287 struct mwl8k_priv *priv = hw->priv;
3288
3289 spin_lock_bh(&priv->tx_lock);
3290 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3291 mwl8k_txq_reclaim(hw, i, 0);
3292
88de754a 3293 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 3294 complete(priv->tx_wait);
3295 priv->tx_wait = NULL;
a66098da
LB		 3296 }
3297 spin_unlock_bh(&priv->tx_lock);
3298}
3299
3300static void mwl8k_finalize_join_worker(struct work_struct *work)
3301{
3302 struct mwl8k_priv *priv =
3303 container_of(work, struct mwl8k_priv, finalize_join_worker);
3304 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3305 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3306
3307 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3308 dev_kfree_skb(skb);
3309
3310 priv->beacon_skb = NULL;
3311}
3312
bcb628d5
JL		 3313enum {
3314 MWL8687 = 0,
3315 MWL8366,
6f6d1e9a
LB		 3316};
3317
bcb628d5
JL		 3318static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
3319 {
3320 .part_name = "88w8687",
3321 .helper_image = "mwl8k/helper_8687.fw",
3322 .fw_image = "mwl8k/fmimage_8687.fw",
3323 .rxd_ops = &rxd_8687_ops,
3324 .modes = BIT(NL80211_IFTYPE_STATION),
3325 },
3326 {
3327 .part_name = "88w8366",
3328 .helper_image = "mwl8k/helper_8366.fw",
3329 .fw_image = "mwl8k/fmimage_8366.fw",
3330 .rxd_ops = &rxd_8366_ops,
3331 .modes = 0,
3332 },
45a390dd
LB		 3333};
3334
3335static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
bcb628d5
JL		 3336 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3337 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3338 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3339 { },
45a390dd
LB		 3340};
3341MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3342
a66098da
LB		 3343static int __devinit mwl8k_probe(struct pci_dev *pdev,
3344 const struct pci_device_id *id)
3345{
2aa7b01f 3346 static int printed_version = 0;
a66098da
LB		 3347 struct ieee80211_hw *hw;
3348 struct mwl8k_priv *priv;
a66098da
LB		 3349 int rc;
3350 int i;
2aa7b01f
LB		 3351
3352 if (!printed_version) {
3353 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3354 printed_version = 1;
3355 }
a66098da
LB		 3356
3357 rc = pci_enable_device(pdev);
3358 if (rc) {
3359 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3360 MWL8K_NAME);
3361 return rc;
3362 }
3363
3364 rc = pci_request_regions(pdev, MWL8K_NAME);
3365 if (rc) {
3366 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3367 MWL8K_NAME);
3368 return rc;
3369 }
3370
3371 pci_set_master(pdev);
3372
3373 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3374 if (hw == NULL) {
3375 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3376 rc = -ENOMEM;
3377 goto err_free_reg;
3378 }
3379
3380 priv = hw->priv;
3381 priv->hw = hw;
3382 priv->pdev = pdev;
bcb628d5 3383 priv->device_info = &mwl8k_info_tbl[id->driver_data];
54bc3a0d 3384 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3385 priv->sniffer_enabled = false;
0439b1f5 3386 priv->wmm_enabled = false;
a66098da 3387 priv->pending_tx_pkts = 0;
a66098da 3388
a66098da
LB		 3389 SET_IEEE80211_DEV(hw, &pdev->dev);
3390 pci_set_drvdata(pdev, hw);
3391
5b9482dd
LB		 3392 priv->sram = pci_iomap(pdev, 0, 0x10000);
3393 if (priv->sram == NULL) {
3394 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3395 wiphy_name(hw->wiphy));
a66098da
LB		 3396 goto err_iounmap;
3397 }
3398
5b9482dd
LB		 3399 /*
3400 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3401 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3402 */
3403 priv->regs = pci_iomap(pdev, 1, 0x10000);
3404 if (priv->regs == NULL) {
3405 priv->regs = pci_iomap(pdev, 2, 0x10000);
3406 if (priv->regs == NULL) {
3407 printk(KERN_ERR "%s: Cannot map device registers\n",
3408 wiphy_name(hw->wiphy));
3409 goto err_iounmap;
3410 }
3411 }
3412
a66098da
LB		 3413 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3414 priv->band.band = IEEE80211_BAND_2GHZ;
3415 priv->band.channels = priv->channels;
3416 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3417 priv->band.bitrates = priv->rates;
3418 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3419 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3420
3421 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3422 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3423
3424 /*
3425 * Extra headroom is the size of the required DMA header
3426 * minus the size of the smallest 802.11 frame (CTS frame).
3427 */
3428 hw->extra_tx_headroom =
3429 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3430
3431 hw->channel_change_time = 10;
3432
3433 hw->queues = MWL8K_TX_QUEUES;
3434
547810e3 3435 hw->wiphy->interface_modes = priv->device_info->modes;
a66098da
LB		 3436
3437 /* Set rssi and noise values to dBm */
ce9e2e1b 3438 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3439 hw->vif_data_size = sizeof(struct mwl8k_vif);
3440 priv->vif = NULL;
3441
3442 /* Set default radio state and preamble */
c46563b7 3443 priv->radio_on = 0;
68ce3884 3444 priv->radio_short_preamble = 0;
a66098da
LB		 3445
3446 /* Finalize join worker */
3447 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3448
3449 /* TX reclaim tasklet */
3450 tasklet_init(&priv->tx_reclaim_task,
3451 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3452 tasklet_disable(&priv->tx_reclaim_task);
3453
a66098da
LB		 3454 /* Power management cookie */
3455 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3456 if (priv->cookie == NULL)
3457 goto err_iounmap;
3458
3459 rc = mwl8k_rxq_init(hw, 0);
3460 if (rc)
3461 goto err_iounmap;
3462 rxq_refill(hw, 0, INT_MAX);
3463
618952a7
LB		 3464 mutex_init(&priv->fw_mutex);
3465 priv->fw_mutex_owner = NULL;
3466 priv->fw_mutex_depth = 0;
618952a7
LB		 3467 priv->hostcmd_wait = NULL;
3468
a66098da
LB		 3469 spin_lock_init(&priv->tx_lock);
3470
88de754a
LB		 3471 priv->tx_wait = NULL;
3472
a66098da
LB		 3473 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3474 rc = mwl8k_txq_init(hw, i);
3475 if (rc)
3476 goto err_free_queues;
3477 }
3478
3479 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3480 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3481 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3482 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3483
a0607fd3 3484 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3485 IRQF_SHARED, MWL8K_NAME, hw);
3486 if (rc) {
3487 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3488 wiphy_name(hw->wiphy));
a66098da
LB		 3489 goto err_free_queues;
3490 }
3491
3492 /* Reset firmware and hardware */
3493 mwl8k_hw_reset(priv);
3494
3495 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3496 rc = mwl8k_request_firmware(priv);
a66098da 3497 if (rc) {
c2c357ce
LB		 3498 printk(KERN_ERR "%s: Firmware files not found\n",
3499 wiphy_name(hw->wiphy));
a66098da
LB		 3500 goto err_free_irq;
3501 }
3502
3503 /* Load firmware into hardware */
c2c357ce 3504 rc = mwl8k_load_firmware(hw);
a66098da 3505 if (rc) {
c2c357ce
LB		 3506 printk(KERN_ERR "%s: Cannot start firmware\n",
3507 wiphy_name(hw->wiphy));
a66098da
LB		 3508 goto err_stop_firmware;
3509 }
3510
3511 /* Reclaim memory once firmware is successfully loaded */
3512 mwl8k_release_firmware(priv);
3513
3514 /*
3515 * Temporarily enable interrupts. Initial firmware host
3516 * commands use interrupts and avoids polling. Disable
3517 * interrupts when done.
3518 */
c23b5a69 3519 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3520
3521 /* Get config data, mac addrs etc */
42fba21d
LB		 3522 if (priv->ap_fw) {
3523 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3524 if (!rc)
3525 rc = mwl8k_cmd_set_hw_spec(hw);
3526 } else {
3527 rc = mwl8k_cmd_get_hw_spec_sta(hw);
3528 }
a66098da 3529 if (rc) {
c2c357ce
LB		 3530 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3531 wiphy_name(hw->wiphy));
a66098da
LB		 3532 goto err_stop_firmware;
3533 }
3534
3535 /* Turn radio off */
c46563b7 3536 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3537 if (rc) {
c2c357ce 3538 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3539 goto err_stop_firmware;
3540 }
3541
32060e1b
LB		 3542 /* Clear MAC address */
3543 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3544 if (rc) {
3545 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3546 wiphy_name(hw->wiphy));
3547 goto err_stop_firmware;
3548 }
3549
a66098da 3550 /* Disable interrupts */
a66098da 3551 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3552 free_irq(priv->pdev->irq, hw);
3553
3554 rc = ieee80211_register_hw(hw);
3555 if (rc) {
c2c357ce
LB		 3556 printk(KERN_ERR "%s: Cannot register device\n",
3557 wiphy_name(hw->wiphy));
a66098da
LB		 3558 goto err_stop_firmware;
3559 }
3560
eae74e65 3561 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3562 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3563 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3564 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3565 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3566 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3567
3568 return 0;
3569
3570err_stop_firmware:
3571 mwl8k_hw_reset(priv);
3572 mwl8k_release_firmware(priv);
3573
3574err_free_irq:
a66098da 3575 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3576 free_irq(priv->pdev->irq, hw);
3577
3578err_free_queues:
3579 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3580 mwl8k_txq_deinit(hw, i);
3581 mwl8k_rxq_deinit(hw, 0);
3582
3583err_iounmap:
3584 if (priv->cookie != NULL)
3585 pci_free_consistent(priv->pdev, 4,
3586 priv->cookie, priv->cookie_dma);
3587
3588 if (priv->regs != NULL)
3589 pci_iounmap(pdev, priv->regs);
3590
5b9482dd
LB		 3591 if (priv->sram != NULL)
3592 pci_iounmap(pdev, priv->sram);
3593
a66098da
LB		 3594 pci_set_drvdata(pdev, NULL);
3595 ieee80211_free_hw(hw);
3596
3597err_free_reg:
3598 pci_release_regions(pdev);
3599 pci_disable_device(pdev);
3600
3601 return rc;
3602}
3603
230f7af0 3604static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3605{
3606 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3607}
3608
230f7af0 3609static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3610{
3611 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3612 struct mwl8k_priv *priv;
3613 int i;
3614
3615 if (hw == NULL)
3616 return;
3617 priv = hw->priv;
3618
3619 ieee80211_stop_queues(hw);
3620
60aa569f
LB		 3621 ieee80211_unregister_hw(hw);
3622
a66098da
LB		 3623 /* Remove tx reclaim tasklet */
3624 tasklet_kill(&priv->tx_reclaim_task);
3625
a66098da
LB		 3626 /* Stop hardware */
3627 mwl8k_hw_reset(priv);
3628
3629 /* Return all skbs to mac80211 */
3630 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3631 mwl8k_txq_reclaim(hw, i, 1);
3632
a66098da
LB		 3633 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3634 mwl8k_txq_deinit(hw, i);
3635
3636 mwl8k_rxq_deinit(hw, 0);
3637
c2c357ce 3638 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3639
3640 pci_iounmap(pdev, priv->regs);
5b9482dd 3641 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3642 pci_set_drvdata(pdev, NULL);
3643 ieee80211_free_hw(hw);
3644 pci_release_regions(pdev);
3645 pci_disable_device(pdev);
3646}
3647
3648static struct pci_driver mwl8k_driver = {
3649 .name = MWL8K_NAME,
45a390dd 3650 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3651 .probe = mwl8k_probe,
3652 .remove = __devexit_p(mwl8k_remove),
3653 .shutdown = __devexit_p(mwl8k_shutdown),
3654};
3655
3656static int __init mwl8k_init(void)
3657{
3658 return pci_register_driver(&mwl8k_driver);
3659}
3660
3661static void __exit mwl8k_exit(void)
3662{
3663 pci_unregister_driver(&mwl8k_driver);
3664}
3665
3666module_init(mwl8k_init);
3667module_exit(mwl8k_exit);
c2c357ce
LB		 3668
3669MODULE_DESCRIPTION(MWL8K_DESC);
3670MODULE_VERSION(MWL8K_VERSION);
3671MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3672MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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