mwl8k: Check outgoing rate for a station to decide if ampdu can be created
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB
2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB
16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
5a0e3ad6 22#include <linux/slab.h>
a66098da
LB
23#include <net/mac80211.h>
24#include <linux/moduleparam.h>
25#include <linux/firmware.h>
26#include <linux/workqueue.h>
27
28#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29#define MWL8K_NAME KBUILD_MODNAME
a5fb297d 30#define MWL8K_VERSION "0.12"
a66098da 31
0863ade8
BC
32/* Module parameters */
33static unsigned ap_mode_default;
34module_param(ap_mode_default, bool, 0);
35MODULE_PARM_DESC(ap_mode_default,
36 "Set to 1 to make ap mode the default instead of sta mode");
37
a66098da
LB
38/* Register definitions */
39#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB
40#define MWL8K_MODE_STA 0x0000005a
41#define MWL8K_MODE_AP 0x000000a5
a66098da 42#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB
43#define MWL8K_FWSTA_READY 0xf0f1f2f4
44#define MWL8K_FWAP_READY 0xf1f2f4a5
45#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB
46#define MWL8K_HIU_SCRATCH 0x00000c40
47
48/* Host->device communications */
49#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB
54#define MWL8K_H2A_INT_DUMMY (1 << 20)
55#define MWL8K_H2A_INT_RESET (1 << 15)
56#define MWL8K_H2A_INT_DOORBELL (1 << 1)
57#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB
58
59/* Device->host communications */
60#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b 65#define MWL8K_A2H_INT_DUMMY (1 << 20)
3aefc37e 66#define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
ce9e2e1b
LB
67#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
68#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
69#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
70#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
71#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
72#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
73#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
74#define MWL8K_A2H_INT_RX_READY (1 << 1)
75#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB
76
77#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
78 MWL8K_A2H_INT_CHNL_SWITCHED | \
79 MWL8K_A2H_INT_QUEUE_EMPTY | \
80 MWL8K_A2H_INT_RADAR_DETECT | \
81 MWL8K_A2H_INT_RADIO_ON | \
82 MWL8K_A2H_INT_RADIO_OFF | \
83 MWL8K_A2H_INT_MAC_EVENT | \
84 MWL8K_A2H_INT_OPC_DONE | \
85 MWL8K_A2H_INT_RX_READY | \
3aefc37e
NS
86 MWL8K_A2H_INT_TX_DONE | \
87 MWL8K_A2H_INT_BA_WATCHDOG)
a66098da 88
a66098da 89#define MWL8K_RX_QUEUES 1
e600707b 90#define MWL8K_TX_WMM_QUEUES 4
8a7a578c 91#define MWL8K_MAX_AMPDU_QUEUES 8
e600707b
BC
92#define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
93#define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
a66098da 94
54bc3a0d
LB
95struct rxd_ops {
96 int rxd_size;
97 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
98 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 99 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 100 __le16 *qos, s8 *noise);
54bc3a0d
LB
101};
102
45a390dd 103struct mwl8k_device_info {
a74b295e
LB
104 char *part_name;
105 char *helper_image;
0863ade8
BC
106 char *fw_image_sta;
107 char *fw_image_ap;
89a91f4f 108 struct rxd_ops *ap_rxd_ops;
952a0e96 109 u32 fw_api_ap;
45a390dd
LB
110};
111
a66098da 112struct mwl8k_rx_queue {
45eb400d 113 int rxd_count;
a66098da
LB
114
115 /* hw receives here */
45eb400d 116 int head;
a66098da
LB
117
118 /* refill descs here */
45eb400d 119 int tail;
a66098da 120
54bc3a0d 121 void *rxd;
45eb400d 122 dma_addr_t rxd_dma;
788838eb
LB
123 struct {
124 struct sk_buff *skb;
53b1b3e1 125 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 126 } *buf;
a66098da
LB
127};
128
a66098da
LB
129struct mwl8k_tx_queue {
130 /* hw transmits here */
45eb400d 131 int head;
a66098da
LB
132
133 /* sw appends here */
45eb400d 134 int tail;
a66098da 135
8ccbc3b8 136 unsigned int len;
45eb400d
LB
137 struct mwl8k_tx_desc *txd;
138 dma_addr_t txd_dma;
139 struct sk_buff **skb;
a66098da
LB
140};
141
ac109fd0
BC
142enum {
143 AMPDU_NO_STREAM,
144 AMPDU_STREAM_NEW,
145 AMPDU_STREAM_IN_PROGRESS,
146 AMPDU_STREAM_ACTIVE,
147};
148
5faa1aff
NS
149struct mwl8k_ampdu_stream {
150 struct ieee80211_sta *sta;
151 u8 tid;
152 u8 state;
153 u8 idx;
154 u8 txq_idx; /* index of this stream in priv->txq */
155};
156
a66098da 157struct mwl8k_priv {
a66098da 158 struct ieee80211_hw *hw;
a66098da 159 struct pci_dev *pdev;
a66098da 160
45a390dd
LB
161 struct mwl8k_device_info *device_info;
162
be695fc4
LB
163 void __iomem *sram;
164 void __iomem *regs;
165
166 /* firmware */
d1f9e41d
BC
167 const struct firmware *fw_helper;
168 const struct firmware *fw_ucode;
a66098da 169
be695fc4
LB
170 /* hardware/firmware parameters */
171 bool ap_fw;
172 struct rxd_ops *rxd_ops;
777ad375
LB
173 struct ieee80211_supported_band band_24;
174 struct ieee80211_channel channels_24[14];
175 struct ieee80211_rate rates_24[14];
4eae9edd
LB
176 struct ieee80211_supported_band band_50;
177 struct ieee80211_channel channels_50[4];
178 struct ieee80211_rate rates_50[9];
ee0ddf18
LB
179 u32 ap_macids_supported;
180 u32 sta_macids_supported;
be695fc4 181
8a7a578c
BC
182 /* Ampdu stream information */
183 u8 num_ampdu_queues;
ac109fd0
BC
184 spinlock_t stream_lock;
185 struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
3aefc37e 186 struct work_struct watchdog_ba_handle;
8a7a578c 187
618952a7
LB
188 /* firmware access */
189 struct mutex fw_mutex;
190 struct task_struct *fw_mutex_owner;
191 int fw_mutex_depth;
618952a7
LB
192 struct completion *hostcmd_wait;
193
a66098da
LB
194 /* lock held over TX and TX reap */
195 spinlock_t tx_lock;
a66098da 196
88de754a
LB
197 /* TX quiesce completion, protected by fw_mutex and tx_lock */
198 struct completion *tx_wait;
199
f5bb87cf 200 /* List of interfaces. */
ee0ddf18 201 u32 macids_used;
f5bb87cf 202 struct list_head vif_list;
a66098da 203
a66098da
LB
204 /* power management status cookie from firmware */
205 u32 *cookie;
206 dma_addr_t cookie_dma;
207
208 u16 num_mcaddrs;
a66098da 209 u8 hw_rev;
2aa7b01f 210 u32 fw_rev;
a66098da
LB
211
212 /*
213 * Running count of TX packets in flight, to avoid
214 * iterating over the transmit rings each time.
215 */
216 int pending_tx_pkts;
217
218 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
e600707b
BC
219 struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
220 u32 txq_offset[MWL8K_MAX_TX_QUEUES];
a66098da 221
c46563b7 222 bool radio_on;
68ce3884 223 bool radio_short_preamble;
a43c49a8 224 bool sniffer_enabled;
0439b1f5 225 bool wmm_enabled;
a66098da 226
a66098da
LB
227 /* XXX need to convert this to handle multiple interfaces */
228 bool capture_beacon;
d89173f2 229 u8 capture_bssid[ETH_ALEN];
a66098da
LB
230 struct sk_buff *beacon_skb;
231
232 /*
233 * This FJ worker has to be global as it is scheduled from the
234 * RX handler. At this point we don't know which interface it
235 * belongs to until the list of bssids waiting to complete join
236 * is checked.
237 */
238 struct work_struct finalize_join_worker;
239
1e9f9de3
LB
240 /* Tasklet to perform TX reclaim. */
241 struct tasklet_struct poll_tx_task;
67e2eb27
LB
242
243 /* Tasklet to perform RX. */
244 struct tasklet_struct poll_rx_task;
0d462bbb
JL
245
246 /* Most recently reported noise in dBm */
247 s8 noise;
0863ade8
BC
248
249 /*
250 * preserve the queue configurations so they can be restored if/when
251 * the firmware image is swapped.
252 */
e600707b 253 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
99020471
BC
254
255 /* async firmware loading state */
256 unsigned fw_state;
257 char *fw_pref;
258 char *fw_alt;
259 struct completion firmware_loading_complete;
a66098da
LB
260};
261
e53d9b96
NS
262#define MAX_WEP_KEY_LEN 13
263#define NUM_WEP_KEYS 4
264
a66098da
LB
265/* Per interface specific private data */
266struct mwl8k_vif {
f5bb87cf
LB
267 struct list_head list;
268 struct ieee80211_vif *vif;
269
f57ca9c1
LB
270 /* Firmware macid for this vif. */
271 int macid;
272
c2c2b12a 273 /* Non AMPDU sequence number assigned by driver. */
a680400e 274 u16 seqno;
e53d9b96
NS
275
276 /* Saved WEP keys */
277 struct {
278 u8 enabled;
279 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
280 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS
281
282 /* BSSID */
283 u8 bssid[ETH_ALEN];
284
285 /* A flag to indicate is HW crypto is enabled for this bssid */
286 bool is_hw_crypto_enabled;
a66098da 287};
a94cc97e 288#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
fcdc403c 289#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
a66098da 290
a680400e
LB
291struct mwl8k_sta {
292 /* Index into station database. Returned by UPDATE_STADB. */
293 u8 peer_id;
17033543 294 u8 is_ampdu_allowed;
a680400e
LB
295};
296#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
297
777ad375 298static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB
299 { .center_freq = 2412, .hw_value = 1, },
300 { .center_freq = 2417, .hw_value = 2, },
301 { .center_freq = 2422, .hw_value = 3, },
302 { .center_freq = 2427, .hw_value = 4, },
303 { .center_freq = 2432, .hw_value = 5, },
304 { .center_freq = 2437, .hw_value = 6, },
305 { .center_freq = 2442, .hw_value = 7, },
306 { .center_freq = 2447, .hw_value = 8, },
307 { .center_freq = 2452, .hw_value = 9, },
308 { .center_freq = 2457, .hw_value = 10, },
309 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB
310 { .center_freq = 2467, .hw_value = 12, },
311 { .center_freq = 2472, .hw_value = 13, },
312 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB
313};
314
777ad375 315static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB
316 { .bitrate = 10, .hw_value = 2, },
317 { .bitrate = 20, .hw_value = 4, },
318 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB
319 { .bitrate = 110, .hw_value = 22, },
320 { .bitrate = 220, .hw_value = 44, },
a66098da
LB
321 { .bitrate = 60, .hw_value = 12, },
322 { .bitrate = 90, .hw_value = 18, },
a66098da
LB
323 { .bitrate = 120, .hw_value = 24, },
324 { .bitrate = 180, .hw_value = 36, },
325 { .bitrate = 240, .hw_value = 48, },
326 { .bitrate = 360, .hw_value = 72, },
327 { .bitrate = 480, .hw_value = 96, },
328 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB
329 { .bitrate = 720, .hw_value = 144, },
330};
331
4eae9edd
LB
332static const struct ieee80211_channel mwl8k_channels_50[] = {
333 { .center_freq = 5180, .hw_value = 36, },
334 { .center_freq = 5200, .hw_value = 40, },
335 { .center_freq = 5220, .hw_value = 44, },
336 { .center_freq = 5240, .hw_value = 48, },
337};
338
339static const struct ieee80211_rate mwl8k_rates_50[] = {
340 { .bitrate = 60, .hw_value = 12, },
341 { .bitrate = 90, .hw_value = 18, },
342 { .bitrate = 120, .hw_value = 24, },
343 { .bitrate = 180, .hw_value = 36, },
344 { .bitrate = 240, .hw_value = 48, },
345 { .bitrate = 360, .hw_value = 72, },
346 { .bitrate = 480, .hw_value = 96, },
347 { .bitrate = 540, .hw_value = 108, },
348 { .bitrate = 720, .hw_value = 144, },
349};
350
a66098da 351/* Set or get info from Firmware */
a66098da 352#define MWL8K_CMD_GET 0x0000
41fdf097
NS
353#define MWL8K_CMD_SET 0x0001
354#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB
355
356/* Firmware command codes */
357#define MWL8K_CMD_CODE_DNLD 0x0001
358#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 359#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB
360#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
361#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB
362#define MWL8K_CMD_RADIO_CONTROL 0x001c
363#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 364#define MWL8K_CMD_TX_POWER 0x001f
08b06347 365#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 366#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB
367#define MWL8K_CMD_SET_PRE_SCAN 0x0107
368#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB
369#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
370#define MWL8K_CMD_SET_AID 0x010d
371#define MWL8K_CMD_SET_RATE 0x0110
372#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
373#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 374#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB
375#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
376#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 377#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 378#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 379#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 380#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 381#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
3aefc37e 382#define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
aa21d0f6
LB
383#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
384#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
fcdc403c 385#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
ff45fc60 386#define MWL8K_CMD_UPDATE_STADB 0x1123
5faa1aff 387#define MWL8K_CMD_BASTREAM 0x1125
a66098da 388
b603742f 389static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 390{
b603742f
JL
391 u16 command = le16_to_cpu(cmd);
392
a66098da
LB
393#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
394 snprintf(buf, bufsize, "%s", #x);\
395 return buf;\
396 } while (0)
b603742f 397 switch (command & ~0x8000) {
a66098da
LB
398 MWL8K_CMDNAME(CODE_DNLD);
399 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 400 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB
401 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
402 MWL8K_CMDNAME(GET_STAT);
403 MWL8K_CMDNAME(RADIO_CONTROL);
404 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 405 MWL8K_CMDNAME(TX_POWER);
08b06347 406 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 407 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB
408 MWL8K_CMDNAME(SET_PRE_SCAN);
409 MWL8K_CMDNAME(SET_POST_SCAN);
410 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB
411 MWL8K_CMDNAME(SET_AID);
412 MWL8K_CMDNAME(SET_RATE);
413 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
414 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 415 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB
416 MWL8K_CMDNAME(SET_EDCA_PARAMS);
417 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 418 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 419 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 420 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 421 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 422 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 423 MWL8K_CMDNAME(BSS_START);
3f5610ff 424 MWL8K_CMDNAME(SET_NEW_STN);
fcdc403c 425 MWL8K_CMDNAME(UPDATE_ENCRYPTION);
ff45fc60 426 MWL8K_CMDNAME(UPDATE_STADB);
5faa1aff 427 MWL8K_CMDNAME(BASTREAM);
3aefc37e 428 MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
a66098da
LB
429 default:
430 snprintf(buf, bufsize, "0x%x", cmd);
431 }
432#undef MWL8K_CMDNAME
433
434 return buf;
435}
436
437/* Hardware and firmware reset */
438static void mwl8k_hw_reset(struct mwl8k_priv *priv)
439{
440 iowrite32(MWL8K_H2A_INT_RESET,
441 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
442 iowrite32(MWL8K_H2A_INT_RESET,
443 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
444 msleep(20);
445}
446
447/* Release fw image */
d1f9e41d 448static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB
449{
450 if (*fw == NULL)
451 return;
452 release_firmware(*fw);
453 *fw = NULL;
454}
455
456static void mwl8k_release_firmware(struct mwl8k_priv *priv)
457{
22be40d9
LB
458 mwl8k_release_fw(&priv->fw_ucode);
459 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB
460}
461
99020471
BC
462/* states for asynchronous f/w loading */
463static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
464enum {
465 FW_STATE_INIT = 0,
466 FW_STATE_LOADING_PREF,
467 FW_STATE_LOADING_ALT,
468 FW_STATE_ERROR,
469};
470
a66098da
LB
471/* Request fw image */
472static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 473 const char *fname, const struct firmware **fw,
99020471 474 bool nowait)
a66098da
LB
475{
476 /* release current image */
477 if (*fw != NULL)
478 mwl8k_release_fw(fw);
479
99020471
BC
480 if (nowait)
481 return request_firmware_nowait(THIS_MODULE, 1, fname,
482 &priv->pdev->dev, GFP_KERNEL,
483 priv, mwl8k_fw_state_machine);
484 else
d1f9e41d 485 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB
486}
487
99020471
BC
488static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
489 bool nowait)
a66098da 490{
a74b295e 491 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB
492 int rc;
493
a74b295e 494 if (di->helper_image != NULL) {
99020471
BC
495 if (nowait)
496 rc = mwl8k_request_fw(priv, di->helper_image,
497 &priv->fw_helper, true);
498 else
499 rc = mwl8k_request_fw(priv, di->helper_image,
500 &priv->fw_helper, false);
501 if (rc)
502 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
503 pci_name(priv->pdev), di->helper_image);
504
505 if (rc || nowait)
a74b295e 506 return rc;
a66098da
LB
507 }
508
99020471
BC
509 if (nowait) {
510 /*
511 * if we get here, no helper image is needed. Skip the
512 * FW_STATE_INIT state.
513 */
514 priv->fw_state = FW_STATE_LOADING_PREF;
515 rc = mwl8k_request_fw(priv, fw_image,
516 &priv->fw_ucode,
517 true);
518 } else
519 rc = mwl8k_request_fw(priv, fw_image,
520 &priv->fw_ucode, false);
a66098da 521 if (rc) {
c2c357ce 522 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 523 pci_name(priv->pdev), fw_image);
22be40d9 524 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB
525 return rc;
526 }
527
528 return 0;
529}
530
531struct mwl8k_cmd_pkt {
532 __le16 code;
533 __le16 length;
f57ca9c1
LB
534 __u8 seq_num;
535 __u8 macid;
a66098da
LB
536 __le16 result;
537 char payload[0];
ba2d3587 538} __packed;
a66098da
LB
539
540/*
541 * Firmware loading.
542 */
543static int
544mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
545{
546 void __iomem *regs = priv->regs;
547 dma_addr_t dma_addr;
a66098da
LB
548 int loops;
549
550 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
551 if (pci_dma_mapping_error(priv->pdev, dma_addr))
552 return -ENOMEM;
553
554 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
555 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
556 iowrite32(MWL8K_H2A_INT_DOORBELL,
557 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
558 iowrite32(MWL8K_H2A_INT_DUMMY,
559 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
560
a66098da
LB
561 loops = 1000;
562 do {
563 u32 int_code;
564
565 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
566 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
567 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB
568 break;
569 }
570
3d76e82c 571 cond_resched();
a66098da
LB
572 udelay(1);
573 } while (--loops);
574
575 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
576
d4b70570 577 return loops ? 0 : -ETIMEDOUT;
a66098da
LB
578}
579
580static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
581 const u8 *data, size_t length)
582{
583 struct mwl8k_cmd_pkt *cmd;
584 int done;
585 int rc = 0;
586
587 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
588 if (cmd == NULL)
589 return -ENOMEM;
590
591 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
592 cmd->seq_num = 0;
f57ca9c1 593 cmd->macid = 0;
a66098da
LB
594 cmd->result = 0;
595
596 done = 0;
597 while (length) {
598 int block_size = length > 256 ? 256 : length;
599
600 memcpy(cmd->payload, data + done, block_size);
601 cmd->length = cpu_to_le16(block_size);
602
603 rc = mwl8k_send_fw_load_cmd(priv, cmd,
604 sizeof(*cmd) + block_size);
605 if (rc)
606 break;
607
608 done += block_size;
609 length -= block_size;
610 }
611
612 if (!rc) {
613 cmd->length = 0;
614 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
615 }
616
617 kfree(cmd);
618
619 return rc;
620}
621
622static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
623 const u8 *data, size_t length)
624{
625 unsigned char *buffer;
626 int may_continue, rc = 0;
627 u32 done, prev_block_size;
628
629 buffer = kmalloc(1024, GFP_KERNEL);
630 if (buffer == NULL)
631 return -ENOMEM;
632
633 done = 0;
634 prev_block_size = 0;
635 may_continue = 1000;
636 while (may_continue > 0) {
637 u32 block_size;
638
639 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
640 if (block_size & 1) {
641 block_size &= ~1;
642 may_continue--;
643 } else {
644 done += prev_block_size;
645 length -= prev_block_size;
646 }
647
648 if (block_size > 1024 || block_size > length) {
649 rc = -EOVERFLOW;
650 break;
651 }
652
653 if (length == 0) {
654 rc = 0;
655 break;
656 }
657
658 if (block_size == 0) {
659 rc = -EPROTO;
660 may_continue--;
661 udelay(1);
662 continue;
663 }
664
665 prev_block_size = block_size;
666 memcpy(buffer, data + done, block_size);
667
668 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
669 if (rc)
670 break;
671 }
672
673 if (!rc && length != 0)
674 rc = -EREMOTEIO;
675
676 kfree(buffer);
677
678 return rc;
679}
680
c2c357ce 681static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 682{
c2c357ce 683 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 684 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB
685 int rc;
686 int loops;
687
688 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
d1f9e41d 689 const struct firmware *helper = priv->fw_helper;
a66098da 690
c2c357ce
LB
691 if (helper == NULL) {
692 printk(KERN_ERR "%s: helper image needed but none "
693 "given\n", pci_name(priv->pdev));
694 return -EINVAL;
695 }
a66098da 696
c2c357ce 697 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB
698 if (rc) {
699 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 700 "helper image\n", pci_name(priv->pdev));
a66098da
LB
701 return rc;
702 }
89b872e2 703 msleep(5);
a66098da 704
c2c357ce 705 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 706 } else {
c2c357ce 707 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB
708 }
709
710 if (rc) {
c2c357ce
LB
711 printk(KERN_ERR "%s: unable to load firmware image\n",
712 pci_name(priv->pdev));
a66098da
LB
713 return rc;
714 }
715
89a91f4f 716 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 717
89b872e2 718 loops = 500000;
a66098da 719 do {
eae74e65
LB
720 u32 ready_code;
721
722 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
723 if (ready_code == MWL8K_FWAP_READY) {
724 priv->ap_fw = 1;
725 break;
726 } else if (ready_code == MWL8K_FWSTA_READY) {
727 priv->ap_fw = 0;
a66098da 728 break;
eae74e65
LB
729 }
730
731 cond_resched();
a66098da
LB
732 udelay(1);
733 } while (--loops);
734
735 return loops ? 0 : -ETIMEDOUT;
736}
737
738
a66098da
LB
739/* DMA header used by firmware and hardware. */
740struct mwl8k_dma_data {
741 __le16 fwlen;
742 struct ieee80211_hdr wh;
20f09c3d 743 char data[0];
ba2d3587 744} __packed;
a66098da
LB
745
746/* Routines to add/remove DMA header from skb. */
20f09c3d 747static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 748{
20f09c3d
LB
749 struct mwl8k_dma_data *tr;
750 int hdrlen;
751
752 tr = (struct mwl8k_dma_data *)skb->data;
753 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
754
755 if (hdrlen != sizeof(tr->wh)) {
756 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
757 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
758 *((__le16 *)(tr->data - 2)) = qos;
759 } else {
760 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
761 }
a66098da 762 }
20f09c3d
LB
763
764 if (hdrlen != sizeof(*tr))
765 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB
766}
767
252486a1
NS
768static void
769mwl8k_add_dma_header(struct sk_buff *skb, int tail_pad)
a66098da
LB
770{
771 struct ieee80211_hdr *wh;
ca009301 772 int hdrlen;
252486a1 773 int reqd_hdrlen;
a66098da
LB
774 struct mwl8k_dma_data *tr;
775
ca009301
LB
776 /*
777 * Add a firmware DMA header; the firmware requires that we
778 * present a 2-byte payload length followed by a 4-address
779 * header (without QoS field), followed (optionally) by any
780 * WEP/ExtIV header (but only filled in for CCMP).
781 */
a66098da 782 wh = (struct ieee80211_hdr *)skb->data;
ca009301 783
a66098da 784 hdrlen = ieee80211_hdrlen(wh->frame_control);
252486a1
NS
785 reqd_hdrlen = sizeof(*tr);
786
787 if (hdrlen != reqd_hdrlen)
788 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 789
ca009301 790 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 791 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB
792
793 tr = (struct mwl8k_dma_data *)skb->data;
794 if (wh != &tr->wh)
795 memmove(&tr->wh, wh, hdrlen);
ca009301
LB
796 if (hdrlen != sizeof(tr->wh))
797 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB
798
799 /*
800 * Firmware length is the length of the fully formed "802.11
801 * payload". That is, everything except for the 802.11 header.
802 * This includes all crypto material including the MIC.
803 */
252486a1 804 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB
805}
806
e53d9b96
NS
807static void mwl8k_encapsulate_tx_frame(struct sk_buff *skb)
808{
809 struct ieee80211_hdr *wh;
810 struct ieee80211_tx_info *tx_info;
811 struct ieee80211_key_conf *key_conf;
812 int data_pad;
813
814 wh = (struct ieee80211_hdr *)skb->data;
815
816 tx_info = IEEE80211_SKB_CB(skb);
817
818 key_conf = NULL;
819 if (ieee80211_is_data(wh->frame_control))
820 key_conf = tx_info->control.hw_key;
821
822 /*
823 * Make sure the packet header is in the DMA header format (4-address
824 * without QoS), the necessary crypto padding between the header and the
825 * payload has already been provided by mac80211, but it doesn't add tail
826 * padding when HW crypto is enabled.
827 *
828 * We have the following trailer padding requirements:
829 * - WEP: 4 trailer bytes (ICV)
830 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
831 * - CCMP: 8 trailer bytes (MIC)
832 */
833 data_pad = 0;
834 if (key_conf != NULL) {
835 switch (key_conf->cipher) {
836 case WLAN_CIPHER_SUITE_WEP40:
837 case WLAN_CIPHER_SUITE_WEP104:
838 data_pad = 4;
839 break;
840 case WLAN_CIPHER_SUITE_TKIP:
841 data_pad = 12;
842 break;
843 case WLAN_CIPHER_SUITE_CCMP:
844 data_pad = 8;
845 break;
846 }
847 }
848 mwl8k_add_dma_header(skb, data_pad);
849}
a66098da
LB
850
851/*
89a91f4f 852 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 853 */
89a91f4f 854struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB
855 __le16 pkt_len;
856 __u8 sq2;
857 __u8 rate;
858 __le32 pkt_phys_addr;
859 __le32 next_rxd_phys_addr;
860 __le16 qos_control;
861 __le16 htsig2;
862 __le32 hw_rssi_info;
863 __le32 hw_noise_floor_info;
864 __u8 noise_floor;
865 __u8 pad0[3];
866 __u8 rssi;
867 __u8 rx_status;
868 __u8 channel;
869 __u8 rx_ctrl;
ba2d3587 870} __packed;
6f6d1e9a 871
89a91f4f
LB
872#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
873#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
874#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 875
89a91f4f 876#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 877
d9a07d49
NS
878/* 8366 AP rx_status bits */
879#define MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
880#define MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
881#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
882#define MWL8K_8366_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
883#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
884
89a91f4f 885static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 886{
89a91f4f 887 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB
888
889 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 890 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB
891}
892
89a91f4f 893static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 894{
89a91f4f 895 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB
896
897 rxd->pkt_len = cpu_to_le16(len);
898 rxd->pkt_phys_addr = cpu_to_le32(addr);
899 wmb();
900 rxd->rx_ctrl = 0;
901}
902
903static int
89a91f4f 904mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 905 __le16 *qos, s8 *noise)
6f6d1e9a 906{
89a91f4f 907 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 908
89a91f4f 909 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB
910 return -1;
911 rmb();
912
913 memset(status, 0, sizeof(*status));
914
915 status->signal = -rxd->rssi;
0d462bbb 916 *noise = -rxd->noise_floor;
6f6d1e9a 917
89a91f4f 918 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 919 status->flag |= RX_FLAG_HT;
89a91f4f 920 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 921 status->flag |= RX_FLAG_40MHZ;
89a91f4f 922 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB
923 } else {
924 int i;
925
777ad375
LB
926 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
927 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB
928 status->rate_idx = i;
929 break;
930 }
931 }
932 }
933
85478344
LB
934 if (rxd->channel > 14) {
935 status->band = IEEE80211_BAND_5GHZ;
936 if (!(status->flag & RX_FLAG_HT))
937 status->rate_idx -= 5;
938 } else {
939 status->band = IEEE80211_BAND_2GHZ;
940 }
59eb21a6
BR
941 status->freq = ieee80211_channel_to_frequency(rxd->channel,
942 status->band);
6f6d1e9a 943
20f09c3d
LB
944 *qos = rxd->qos_control;
945
d9a07d49
NS
946 if ((rxd->rx_status != MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
947 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK) &&
948 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
949 status->flag |= RX_FLAG_MMIC_ERROR;
950
6f6d1e9a
LB
951 return le16_to_cpu(rxd->pkt_len);
952}
953
89a91f4f
LB
954static struct rxd_ops rxd_8366_ap_ops = {
955 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
956 .rxd_init = mwl8k_rxd_8366_ap_init,
957 .rxd_refill = mwl8k_rxd_8366_ap_refill,
958 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB
959};
960
961/*
89a91f4f 962 * Packet reception for STA firmware.
a66098da 963 */
89a91f4f 964struct mwl8k_rxd_sta {
a66098da
LB
965 __le16 pkt_len;
966 __u8 link_quality;
967 __u8 noise_level;
968 __le32 pkt_phys_addr;
45eb400d 969 __le32 next_rxd_phys_addr;
a66098da
LB
970 __le16 qos_control;
971 __le16 rate_info;
972 __le32 pad0[4];
973 __u8 rssi;
974 __u8 channel;
975 __le16 pad1;
976 __u8 rx_ctrl;
977 __u8 rx_status;
978 __u8 pad2[2];
ba2d3587 979} __packed;
a66098da 980
89a91f4f
LB
981#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
982#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
983#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
984#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
985#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
986#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 987
89a91f4f 988#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS
989#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
990/* ICV=0 or MIC=1 */
991#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
992/* Key is uploaded only in failure case */
993#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 994
89a91f4f 995static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 996{
89a91f4f 997 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
998
999 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 1000 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB
1001}
1002
89a91f4f 1003static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 1004{
89a91f4f 1005 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
1006
1007 rxd->pkt_len = cpu_to_le16(len);
1008 rxd->pkt_phys_addr = cpu_to_le32(addr);
1009 wmb();
1010 rxd->rx_ctrl = 0;
1011}
1012
1013static int
89a91f4f 1014mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 1015 __le16 *qos, s8 *noise)
54bc3a0d 1016{
89a91f4f 1017 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
1018 u16 rate_info;
1019
89a91f4f 1020 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB
1021 return -1;
1022 rmb();
1023
1024 rate_info = le16_to_cpu(rxd->rate_info);
1025
1026 memset(status, 0, sizeof(*status));
1027
1028 status->signal = -rxd->rssi;
0d462bbb 1029 *noise = -rxd->noise_level;
89a91f4f
LB
1030 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
1031 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 1032
89a91f4f 1033 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 1034 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 1035 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1036 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1037 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1038 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1039 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB
1040 status->flag |= RX_FLAG_HT;
1041
85478344
LB
1042 if (rxd->channel > 14) {
1043 status->band = IEEE80211_BAND_5GHZ;
1044 if (!(status->flag & RX_FLAG_HT))
1045 status->rate_idx -= 5;
1046 } else {
1047 status->band = IEEE80211_BAND_2GHZ;
1048 }
59eb21a6
BR
1049 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1050 status->band);
54bc3a0d 1051
20f09c3d 1052 *qos = rxd->qos_control;
d9a07d49
NS
1053 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1054 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1055 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1056
54bc3a0d
LB
1057 return le16_to_cpu(rxd->pkt_len);
1058}
1059
89a91f4f
LB
1060static struct rxd_ops rxd_sta_ops = {
1061 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1062 .rxd_init = mwl8k_rxd_sta_init,
1063 .rxd_refill = mwl8k_rxd_sta_refill,
1064 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB
1065};
1066
1067
a66098da
LB
1068#define MWL8K_RX_DESCS 256
1069#define MWL8K_RX_MAXSZ 3800
1070
1071static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1072{
1073 struct mwl8k_priv *priv = hw->priv;
1074 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1075 int size;
1076 int i;
1077
45eb400d
LB
1078 rxq->rxd_count = 0;
1079 rxq->head = 0;
1080 rxq->tail = 0;
a66098da 1081
54bc3a0d 1082 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1083
45eb400d
LB
1084 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1085 if (rxq->rxd == NULL) {
5db55844 1086 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB
1087 return -ENOMEM;
1088 }
45eb400d 1089 memset(rxq->rxd, 0, size);
a66098da 1090
b9ede5f1 1091 rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
788838eb 1092 if (rxq->buf == NULL) {
5db55844 1093 wiphy_err(hw->wiphy, "failed to alloc RX skbuff list\n");
45eb400d 1094 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB
1095 return -ENOMEM;
1096 }
a66098da
LB
1097
1098 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB
1099 int desc_size;
1100 void *rxd;
a66098da 1101 int nexti;
54bc3a0d
LB
1102 dma_addr_t next_dma_addr;
1103
1104 desc_size = priv->rxd_ops->rxd_size;
1105 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1106
54bc3a0d
LB
1107 nexti = i + 1;
1108 if (nexti == MWL8K_RX_DESCS)
1109 nexti = 0;
1110 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1111
54bc3a0d 1112 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB
1113 }
1114
1115 return 0;
1116}
1117
1118static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1119{
1120 struct mwl8k_priv *priv = hw->priv;
1121 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1122 int refilled;
1123
1124 refilled = 0;
45eb400d 1125 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1126 struct sk_buff *skb;
788838eb 1127 dma_addr_t addr;
a66098da 1128 int rx;
54bc3a0d 1129 void *rxd;
a66098da
LB
1130
1131 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1132 if (skb == NULL)
1133 break;
1134
788838eb
LB
1135 addr = pci_map_single(priv->pdev, skb->data,
1136 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1137
54bc3a0d
LB
1138 rxq->rxd_count++;
1139 rx = rxq->tail++;
1140 if (rxq->tail == MWL8K_RX_DESCS)
1141 rxq->tail = 0;
788838eb 1142 rxq->buf[rx].skb = skb;
53b1b3e1 1143 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB
1144
1145 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1146 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB
1147
1148 refilled++;
1149 }
1150
1151 return refilled;
1152}
1153
1154/* Must be called only when the card's reception is completely halted */
1155static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1156{
1157 struct mwl8k_priv *priv = hw->priv;
1158 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1159 int i;
1160
73b46320
BC
1161 if (rxq->rxd == NULL)
1162 return;
1163
a66098da 1164 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB
1165 if (rxq->buf[i].skb != NULL) {
1166 pci_unmap_single(priv->pdev,
53b1b3e1 1167 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1168 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1169 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB
1170
1171 kfree_skb(rxq->buf[i].skb);
1172 rxq->buf[i].skb = NULL;
a66098da
LB
1173 }
1174 }
1175
788838eb
LB
1176 kfree(rxq->buf);
1177 rxq->buf = NULL;
a66098da
LB
1178
1179 pci_free_consistent(priv->pdev,
54bc3a0d 1180 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB
1181 rxq->rxd, rxq->rxd_dma);
1182 rxq->rxd = NULL;
a66098da
LB
1183}
1184
1185
1186/*
1187 * Scan a list of BSSIDs to process for finalize join.
1188 * Allows for extension to process multiple BSSIDs.
1189 */
1190static inline int
1191mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1192{
1193 return priv->capture_beacon &&
1194 ieee80211_is_beacon(wh->frame_control) &&
1195 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1196}
1197
3779752d
LB
1198static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1199 struct sk_buff *skb)
a66098da 1200{
3779752d
LB
1201 struct mwl8k_priv *priv = hw->priv;
1202
a66098da 1203 priv->capture_beacon = false;
d89173f2 1204 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB
1205
1206 /*
1207 * Use GFP_ATOMIC as rxq_process is called from
1208 * the primary interrupt handler, memory allocation call
1209 * must not sleep.
1210 */
1211 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1212 if (priv->beacon_skb != NULL)
3779752d 1213 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB
1214}
1215
d9a07d49
NS
1216static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1217 u8 *bssid)
1218{
1219 struct mwl8k_vif *mwl8k_vif;
1220
1221 list_for_each_entry(mwl8k_vif,
1222 vif_list, list) {
1223 if (memcmp(bssid, mwl8k_vif->bssid,
1224 ETH_ALEN) == 0)
1225 return mwl8k_vif;
1226 }
1227
1228 return NULL;
1229}
1230
a66098da
LB
1231static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1232{
1233 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1234 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB
1235 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1236 int processed;
1237
1238 processed = 0;
45eb400d 1239 while (rxq->rxd_count && limit--) {
a66098da 1240 struct sk_buff *skb;
54bc3a0d
LB
1241 void *rxd;
1242 int pkt_len;
a66098da 1243 struct ieee80211_rx_status status;
d9a07d49 1244 struct ieee80211_hdr *wh;
20f09c3d 1245 __le16 qos;
a66098da 1246
788838eb 1247 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB
1248 if (skb == NULL)
1249 break;
54bc3a0d
LB
1250
1251 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1252
0d462bbb
JL
1253 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1254 &priv->noise);
54bc3a0d
LB
1255 if (pkt_len < 0)
1256 break;
1257
788838eb
LB
1258 rxq->buf[rxq->head].skb = NULL;
1259
1260 pci_unmap_single(priv->pdev,
53b1b3e1 1261 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1262 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1263 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1264
54bc3a0d
LB
1265 rxq->head++;
1266 if (rxq->head == MWL8K_RX_DESCS)
1267 rxq->head = 0;
1268
45eb400d 1269 rxq->rxd_count--;
a66098da 1270
d9a07d49 1271 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1272
a66098da 1273 /*
c2c357ce
LB
1274 * Check for a pending join operation. Save a
1275 * copy of the beacon and schedule a tasklet to
1276 * send a FINALIZE_JOIN command to the firmware.
a66098da 1277 */
54bc3a0d 1278 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1279 mwl8k_save_beacon(hw, skb);
a66098da 1280
d9a07d49
NS
1281 if (ieee80211_has_protected(wh->frame_control)) {
1282
1283 /* Check if hw crypto has been enabled for
1284 * this bss. If yes, set the status flags
1285 * accordingly
1286 */
1287 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1288 wh->addr1);
1289
1290 if (mwl8k_vif != NULL &&
1291 mwl8k_vif->is_hw_crypto_enabled == true) {
1292 /*
1293 * When MMIC ERROR is encountered
1294 * by the firmware, payload is
1295 * dropped and only 32 bytes of
1296 * mwl8k Firmware header is sent
1297 * to the host.
1298 *
1299 * We need to add four bytes of
1300 * key information. In it
1301 * MAC80211 expects keyidx set to
1302 * 0 for triggering Counter
1303 * Measure of MMIC failure.
1304 */
1305 if (status.flag & RX_FLAG_MMIC_ERROR) {
1306 struct mwl8k_dma_data *tr;
1307 tr = (struct mwl8k_dma_data *)skb->data;
1308 memset((void *)&(tr->data), 0, 4);
1309 pkt_len += 4;
1310 }
1311
1312 if (!ieee80211_is_auth(wh->frame_control))
1313 status.flag |= RX_FLAG_IV_STRIPPED |
1314 RX_FLAG_DECRYPTED |
1315 RX_FLAG_MMIC_STRIPPED;
1316 }
1317 }
1318
1319 skb_put(skb, pkt_len);
1320 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB
1321 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1322 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB
1323
1324 processed++;
1325 }
1326
1327 return processed;
1328}
1329
1330
1331/*
1332 * Packet transmission.
1333 */
1334
a66098da
LB
1335#define MWL8K_TXD_STATUS_OK 0x00000001
1336#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1337#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1338#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1339#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1340
e0493a8d
LB
1341#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1342#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1343#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1344#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1345#define MWL8K_QOS_EOSP 0x0010
1346
a66098da
LB
1347struct mwl8k_tx_desc {
1348 __le32 status;
1349 __u8 data_rate;
1350 __u8 tx_priority;
1351 __le16 qos_control;
1352 __le32 pkt_phys_addr;
1353 __le16 pkt_len;
d89173f2 1354 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1355 __le32 next_txd_phys_addr;
8a7a578c 1356 __le32 timestamp;
a66098da
LB
1357 __le16 rate_info;
1358 __u8 peer_id;
a1fe24b0 1359 __u8 tx_frag_cnt;
ba2d3587 1360} __packed;
a66098da
LB
1361
1362#define MWL8K_TX_DESCS 128
1363
1364static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1365{
1366 struct mwl8k_priv *priv = hw->priv;
1367 struct mwl8k_tx_queue *txq = priv->txq + index;
1368 int size;
1369 int i;
1370
8ccbc3b8 1371 txq->len = 0;
45eb400d
LB
1372 txq->head = 0;
1373 txq->tail = 0;
a66098da
LB
1374
1375 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1376
45eb400d
LB
1377 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1378 if (txq->txd == NULL) {
5db55844 1379 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB
1380 return -ENOMEM;
1381 }
45eb400d 1382 memset(txq->txd, 0, size);
a66098da 1383
b9ede5f1 1384 txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
45eb400d 1385 if (txq->skb == NULL) {
5db55844 1386 wiphy_err(hw->wiphy, "failed to alloc TX skbuff list\n");
45eb400d 1387 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB
1388 return -ENOMEM;
1389 }
a66098da
LB
1390
1391 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1392 struct mwl8k_tx_desc *tx_desc;
1393 int nexti;
1394
45eb400d 1395 tx_desc = txq->txd + i;
a66098da
LB
1396 nexti = (i + 1) % MWL8K_TX_DESCS;
1397
1398 tx_desc->status = 0;
45eb400d
LB
1399 tx_desc->next_txd_phys_addr =
1400 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB
1401 }
1402
1403 return 0;
1404}
1405
1406static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1407{
1408 iowrite32(MWL8K_H2A_INT_PPA_READY,
1409 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1410 iowrite32(MWL8K_H2A_INT_DUMMY,
1411 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1412 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1413}
1414
7e1112d3 1415static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1416{
7e1112d3
LB
1417 struct mwl8k_priv *priv = hw->priv;
1418 int i;
1419
e600707b 1420 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
7e1112d3
LB
1421 struct mwl8k_tx_queue *txq = priv->txq + i;
1422 int fw_owned = 0;
1423 int drv_owned = 0;
1424 int unused = 0;
1425 int desc;
1426
a66098da 1427 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB
1428 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1429 u32 status;
a66098da 1430
7e1112d3 1431 status = le32_to_cpu(tx_desc->status);
a66098da 1432 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1433 fw_owned++;
a66098da 1434 else
7e1112d3 1435 drv_owned++;
a66098da
LB
1436
1437 if (tx_desc->pkt_len == 0)
7e1112d3 1438 unused++;
a66098da 1439 }
a66098da 1440
c96c31e4
JP
1441 wiphy_err(hw->wiphy,
1442 "txq[%d] len=%d head=%d tail=%d "
1443 "fw_owned=%d drv_owned=%d unused=%d\n",
1444 i,
1445 txq->len, txq->head, txq->tail,
1446 fw_owned, drv_owned, unused);
7e1112d3 1447 }
a66098da
LB
1448}
1449
618952a7 1450/*
88de754a 1451 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1452 */
62abd3cf 1453#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1454
950d5b01 1455static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1456{
a66098da 1457 struct mwl8k_priv *priv = hw->priv;
88de754a 1458 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB
1459 int retry;
1460 int rc;
a66098da
LB
1461
1462 might_sleep();
1463
7e1112d3
LB
1464 /*
1465 * The TX queues are stopped at this point, so this test
1466 * doesn't need to take ->tx_lock.
1467 */
1468 if (!priv->pending_tx_pkts)
1469 return 0;
1470
1471 retry = 0;
1472 rc = 0;
1473
a66098da 1474 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB
1475 priv->tx_wait = &tx_wait;
1476 while (!rc) {
1477 int oldcount;
1478 unsigned long timeout;
a66098da 1479
7e1112d3 1480 oldcount = priv->pending_tx_pkts;
a66098da 1481
7e1112d3 1482 spin_unlock_bh(&priv->tx_lock);
88de754a 1483 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1484 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1485 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB
1486
1487 if (timeout) {
1488 WARN_ON(priv->pending_tx_pkts);
1489 if (retry) {
c96c31e4 1490 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB
1491 }
1492 break;
1493 }
1494
1495 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP
1496 wiphy_notice(hw->wiphy,
1497 "waiting for tx rings to drain (%d -> %d pkts)\n",
1498 oldcount, priv->pending_tx_pkts);
7e1112d3
LB
1499 retry = 1;
1500 continue;
1501 }
1502
a66098da 1503 priv->tx_wait = NULL;
a66098da 1504
c96c31e4
JP
1505 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1506 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3
LB
1507 mwl8k_dump_tx_rings(hw);
1508
1509 rc = -ETIMEDOUT;
a66098da 1510 }
7e1112d3 1511 spin_unlock_bh(&priv->tx_lock);
a66098da 1512
7e1112d3 1513 return rc;
a66098da
LB
1514}
1515
c23b5a69
LB
1516#define MWL8K_TXD_SUCCESS(status) \
1517 ((status) & (MWL8K_TXD_STATUS_OK | \
1518 MWL8K_TXD_STATUS_OK_RETRY | \
1519 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1520
17033543
NS
1521/* The firmware will fill in the rate information
1522 * for each packet that gets queued in the hardware
1523 * in this structure
1524 */
1525
1526struct rateinfo {
1527 __le16 format:1;
1528 __le16 short_gi:1;
1529 __le16 band_width:1;
1530 __le16 rate_id_mcs:6;
1531 __le16 adv_coding:2;
1532 __le16 antenna:2;
1533 __le16 act_sub_chan:2;
1534 __le16 preamble_type:1;
1535 __le16 power_id:4;
1536 __le16 antenna2:1;
1537 __le16 reserved:1;
1538 __le16 tx_bf_frame:1;
1539 __le16 green_field:1;
1540} __packed;
1541
efb7c49a
LB
1542static int
1543mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB
1544{
1545 struct mwl8k_priv *priv = hw->priv;
1546 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1547 int processed;
a66098da 1548
efb7c49a 1549 processed = 0;
8ccbc3b8 1550 while (txq->len > 0 && limit--) {
a66098da 1551 int tx;
a66098da
LB
1552 struct mwl8k_tx_desc *tx_desc;
1553 unsigned long addr;
ce9e2e1b 1554 int size;
a66098da
LB
1555 struct sk_buff *skb;
1556 struct ieee80211_tx_info *info;
1557 u32 status;
17033543
NS
1558 struct ieee80211_sta *sta;
1559 struct mwl8k_sta *sta_info = NULL;
1560 u16 rate_info;
1561 struct rateinfo *rate;
1562 struct ieee80211_hdr *wh;
a66098da 1563
45eb400d
LB
1564 tx = txq->head;
1565 tx_desc = txq->txd + tx;
a66098da
LB
1566
1567 status = le32_to_cpu(tx_desc->status);
1568
1569 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1570 if (!force)
1571 break;
1572 tx_desc->status &=
1573 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1574 }
1575
45eb400d 1576 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV
1577 BUG_ON(txq->len == 0);
1578 txq->len--;
a66098da
LB
1579 priv->pending_tx_pkts--;
1580
1581 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1582 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB
1583 skb = txq->skb[tx];
1584 txq->skb[tx] = NULL;
a66098da
LB
1585
1586 BUG_ON(skb == NULL);
1587 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1588
20f09c3d 1589 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da 1590
17033543
NS
1591 wh = (struct ieee80211_hdr *) skb->data;
1592
a66098da
LB
1593 /* Mark descriptor as unused */
1594 tx_desc->pkt_phys_addr = 0;
1595 tx_desc->pkt_len = 0;
1596
a66098da 1597 info = IEEE80211_SKB_CB(skb);
17033543
NS
1598 if (ieee80211_is_data(wh->frame_control)) {
1599 sta = info->control.sta;
1600 if (sta) {
1601 sta_info = MWL8K_STA(sta);
1602 BUG_ON(sta_info == NULL);
1603 rate_info = le16_to_cpu(tx_desc->rate_info);
1604 rate = (struct rateinfo *)&rate_info;
1605 /* If rate is < 6.5 Mpbs for an ht station
1606 * do not form an ampdu. If the station is a
1607 * legacy station (format = 0), do not form an
1608 * ampdu
1609 */
1610 if (rate->rate_id_mcs < 1 ||
1611 rate->format == 0) {
1612 sta_info->is_ampdu_allowed = false;
1613 } else {
1614 sta_info->is_ampdu_allowed = true;
1615 }
1616 }
1617 }
1618
a66098da 1619 ieee80211_tx_info_clear_status(info);
0bf22c37
NS
1620
1621 /* Rate control is happening in the firmware.
1622 * Ensure no tx rate is being reported.
1623 */
1624 info->status.rates[0].idx = -1;
1625 info->status.rates[0].count = 1;
1626
ce9e2e1b 1627 if (MWL8K_TXD_SUCCESS(status))
a66098da 1628 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB
1629
1630 ieee80211_tx_status_irqsafe(hw, skb);
1631
efb7c49a 1632 processed++;
a66098da
LB
1633 }
1634
65f3ddcd
NS
1635 if (index < MWL8K_TX_WMM_QUEUES && processed && priv->radio_on &&
1636 !mutex_is_locked(&priv->fw_mutex))
a66098da 1637 ieee80211_wake_queue(hw, index);
efb7c49a
LB
1638
1639 return processed;
a66098da
LB
1640}
1641
1642/* must be called only when the card's transmit is completely halted */
1643static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1644{
1645 struct mwl8k_priv *priv = hw->priv;
1646 struct mwl8k_tx_queue *txq = priv->txq + index;
1647
73b46320
BC
1648 if (txq->txd == NULL)
1649 return;
1650
efb7c49a 1651 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1652
45eb400d
LB
1653 kfree(txq->skb);
1654 txq->skb = NULL;
a66098da
LB
1655
1656 pci_free_consistent(priv->pdev,
1657 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB
1658 txq->txd, txq->txd_dma);
1659 txq->txd = NULL;
a66098da
LB
1660}
1661
ac109fd0
BC
1662/* caller must hold priv->stream_lock when calling the stream functions */
1663struct mwl8k_ampdu_stream *
1664mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
1665{
1666 struct mwl8k_ampdu_stream *stream;
1667 struct mwl8k_priv *priv = hw->priv;
1668 int i;
1669
1670 for (i = 0; i < priv->num_ampdu_queues; i++) {
1671 stream = &priv->ampdu[i];
1672 if (stream->state == AMPDU_NO_STREAM) {
1673 stream->sta = sta;
1674 stream->state = AMPDU_STREAM_NEW;
1675 stream->tid = tid;
1676 stream->idx = i;
1677 stream->txq_idx = MWL8K_TX_WMM_QUEUES + i;
1678 wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
1679 sta->addr, tid);
1680 return stream;
1681 }
1682 }
1683 return NULL;
1684}
1685
1686static int
1687mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1688{
1689 int ret;
1690
1691 /* if the stream has already been started, don't start it again */
1692 if (stream->state != AMPDU_STREAM_NEW)
1693 return 0;
1694 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
1695 if (ret)
1696 wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
1697 "%d\n", stream->sta->addr, stream->tid, ret);
1698 else
1699 wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
1700 stream->sta->addr, stream->tid);
1701 return ret;
1702}
1703
1704static void
1705mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1706{
1707 wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
1708 stream->tid);
1709 memset(stream, 0, sizeof(*stream));
1710}
1711
1712static struct mwl8k_ampdu_stream *
1713mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
1714{
1715 struct mwl8k_priv *priv = hw->priv;
1716 int i;
1717
1718 for (i = 0 ; i < priv->num_ampdu_queues; i++) {
1719 struct mwl8k_ampdu_stream *stream;
1720 stream = &priv->ampdu[i];
1721 if (stream->state == AMPDU_NO_STREAM)
1722 continue;
1723 if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
1724 stream->tid == tid)
1725 return stream;
1726 }
1727 return NULL;
1728}
1729
7bb45683 1730static void
a66098da
LB
1731mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1732{
1733 struct mwl8k_priv *priv = hw->priv;
1734 struct ieee80211_tx_info *tx_info;
23b33906 1735 struct mwl8k_vif *mwl8k_vif;
65f3ddcd 1736 struct ieee80211_sta *sta;
a66098da
LB
1737 struct ieee80211_hdr *wh;
1738 struct mwl8k_tx_queue *txq;
1739 struct mwl8k_tx_desc *tx;
a66098da 1740 dma_addr_t dma;
23b33906
LB
1741 u32 txstatus;
1742 u8 txdatarate;
1743 u16 qos;
65f3ddcd
NS
1744 int txpriority;
1745 u8 tid = 0;
1746 struct mwl8k_ampdu_stream *stream = NULL;
1747 bool start_ba_session = false;
a66098da 1748
23b33906
LB
1749 wh = (struct ieee80211_hdr *)skb->data;
1750 if (ieee80211_is_data_qos(wh->frame_control))
1751 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1752 else
1753 qos = 0;
a66098da 1754
d9a07d49
NS
1755 if (priv->ap_fw)
1756 mwl8k_encapsulate_tx_frame(skb);
1757 else
1758 mwl8k_add_dma_header(skb, 0);
1759
23b33906 1760 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB
1761
1762 tx_info = IEEE80211_SKB_CB(skb);
65f3ddcd 1763 sta = tx_info->control.sta;
a66098da 1764 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB
1765
1766 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1767 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB
1768 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1769 mwl8k_vif->seqno += 0x10;
a66098da
LB
1770 }
1771
23b33906
LB
1772 /* Setup firmware control bit fields for each frame type. */
1773 txstatus = 0;
1774 txdatarate = 0;
1775 if (ieee80211_is_mgmt(wh->frame_control) ||
1776 ieee80211_is_ctl(wh->frame_control)) {
1777 txdatarate = 0;
e0493a8d 1778 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB
1779 } else if (ieee80211_is_data(wh->frame_control)) {
1780 txdatarate = 1;
1781 if (is_multicast_ether_addr(wh->addr1))
1782 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1783
e0493a8d 1784 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1785 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1786 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1787 else
e0493a8d 1788 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1789 }
a66098da 1790
65f3ddcd
NS
1791 txpriority = index;
1792
1793 if (ieee80211_is_data_qos(wh->frame_control) &&
1794 skb->protocol != cpu_to_be16(ETH_P_PAE) &&
1795 sta->ht_cap.ht_supported && priv->ap_fw) {
1796 tid = qos & 0xf;
1797 spin_lock(&priv->stream_lock);
1798 stream = mwl8k_lookup_stream(hw, sta->addr, tid);
1799 if (stream != NULL) {
1800 if (stream->state == AMPDU_STREAM_ACTIVE) {
1801 txpriority = stream->txq_idx;
1802 index = stream->txq_idx;
1803 } else if (stream->state == AMPDU_STREAM_NEW) {
1804 /* We get here if the driver sends us packets
1805 * after we've initiated a stream, but before
1806 * our ampdu_action routine has been called
1807 * with IEEE80211_AMPDU_TX_START to get the SSN
1808 * for the ADDBA request. So this packet can
1809 * go out with no risk of sequence number
1810 * mismatch. No special handling is required.
1811 */
1812 } else {
1813 /* Drop packets that would go out after the
1814 * ADDBA request was sent but before the ADDBA
1815 * response is received. If we don't do this,
1816 * the recipient would probably receive it
1817 * after the ADDBA request with SSN 0. This
1818 * will cause the recipient's BA receive window
1819 * to shift, which would cause the subsequent
1820 * packets in the BA stream to be discarded.
1821 * mac80211 queues our packets for us in this
1822 * case, so this is really just a safety check.
1823 */
1824 wiphy_warn(hw->wiphy,
1825 "Cannot send packet while ADDBA "
1826 "dialog is underway.\n");
1827 spin_unlock(&priv->stream_lock);
1828 dev_kfree_skb(skb);
1829 return;
1830 }
1831 } else {
1832 /* Defer calling mwl8k_start_stream so that the current
1833 * skb can go out before the ADDBA request. This
1834 * prevents sequence number mismatch at the recepient
1835 * as described above.
1836 */
17033543
NS
1837 if (MWL8K_STA(sta)->is_ampdu_allowed) {
1838 stream = mwl8k_add_stream(hw, sta, tid);
1839 if (stream != NULL)
1840 start_ba_session = true;
1841 }
65f3ddcd
NS
1842 }
1843 spin_unlock(&priv->stream_lock);
1844 }
1845
a66098da
LB
1846 dma = pci_map_single(priv->pdev, skb->data,
1847 skb->len, PCI_DMA_TODEVICE);
1848
1849 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP
1850 wiphy_debug(hw->wiphy,
1851 "failed to dma map skb, dropping TX frame.\n");
65f3ddcd
NS
1852 if (start_ba_session) {
1853 spin_lock(&priv->stream_lock);
1854 mwl8k_remove_stream(hw, stream);
1855 spin_unlock(&priv->stream_lock);
1856 }
23b33906 1857 dev_kfree_skb(skb);
7bb45683 1858 return;
a66098da
LB
1859 }
1860
23b33906 1861 spin_lock_bh(&priv->tx_lock);
a66098da 1862
23b33906 1863 txq = priv->txq + index;
a66098da 1864
65f3ddcd
NS
1865 if (index >= MWL8K_TX_WMM_QUEUES && txq->len >= MWL8K_TX_DESCS) {
1866 /* This is the case in which the tx packet is destined for an
1867 * AMPDU queue and that AMPDU queue is full. Because we don't
1868 * start and stop the AMPDU queues, we must drop these packets.
1869 */
1870 dev_kfree_skb(skb);
1871 spin_unlock_bh(&priv->tx_lock);
1872 return;
1873 }
1874
45eb400d
LB
1875 BUG_ON(txq->skb[txq->tail] != NULL);
1876 txq->skb[txq->tail] = skb;
a66098da 1877
45eb400d 1878 tx = txq->txd + txq->tail;
23b33906 1879 tx->data_rate = txdatarate;
65f3ddcd 1880 tx->tx_priority = txpriority;
a66098da 1881 tx->qos_control = cpu_to_le16(qos);
a66098da
LB
1882 tx->pkt_phys_addr = cpu_to_le32(dma);
1883 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1884 tx->rate_info = 0;
a680400e
LB
1885 if (!priv->ap_fw && tx_info->control.sta != NULL)
1886 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1887 else
1888 tx->peer_id = 0;
a66098da 1889 wmb();
23b33906
LB
1890 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1891
8ccbc3b8 1892 txq->len++;
a66098da 1893 priv->pending_tx_pkts++;
a66098da 1894
45eb400d
LB
1895 txq->tail++;
1896 if (txq->tail == MWL8K_TX_DESCS)
1897 txq->tail = 0;
23b33906 1898
65f3ddcd 1899 if (txq->head == txq->tail && index < MWL8K_TX_WMM_QUEUES)
a66098da
LB
1900 ieee80211_stop_queue(hw, index);
1901
23b33906 1902 mwl8k_tx_start(priv);
a66098da
LB
1903
1904 spin_unlock_bh(&priv->tx_lock);
65f3ddcd
NS
1905
1906 /* Initiate the ampdu session here */
1907 if (start_ba_session) {
1908 spin_lock(&priv->stream_lock);
1909 if (mwl8k_start_stream(hw, stream))
1910 mwl8k_remove_stream(hw, stream);
1911 spin_unlock(&priv->stream_lock);
1912 }
a66098da
LB
1913}
1914
1915
618952a7
LB
1916/*
1917 * Firmware access.
1918 *
1919 * We have the following requirements for issuing firmware commands:
1920 * - Some commands require that the packet transmit path is idle when
1921 * the command is issued. (For simplicity, we'll just quiesce the
1922 * transmit path for every command.)
1923 * - There are certain sequences of commands that need to be issued to
1924 * the hardware sequentially, with no other intervening commands.
1925 *
1926 * This leads to an implementation of a "firmware lock" as a mutex that
1927 * can be taken recursively, and which is taken by both the low-level
1928 * command submission function (mwl8k_post_cmd) as well as any users of
1929 * that function that require issuing of an atomic sequence of commands,
1930 * and quiesces the transmit path whenever it's taken.
1931 */
1932static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1933{
1934 struct mwl8k_priv *priv = hw->priv;
1935
1936 if (priv->fw_mutex_owner != current) {
1937 int rc;
1938
1939 mutex_lock(&priv->fw_mutex);
1940 ieee80211_stop_queues(hw);
1941
1942 rc = mwl8k_tx_wait_empty(hw);
1943 if (rc) {
1944 ieee80211_wake_queues(hw);
1945 mutex_unlock(&priv->fw_mutex);
1946
1947 return rc;
1948 }
1949
1950 priv->fw_mutex_owner = current;
1951 }
1952
1953 priv->fw_mutex_depth++;
1954
1955 return 0;
1956}
1957
1958static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1959{
1960 struct mwl8k_priv *priv = hw->priv;
1961
1962 if (!--priv->fw_mutex_depth) {
1963 ieee80211_wake_queues(hw);
1964 priv->fw_mutex_owner = NULL;
1965 mutex_unlock(&priv->fw_mutex);
1966 }
1967}
1968
1969
a66098da
LB
1970/*
1971 * Command processing.
1972 */
1973
0c9cc640
LB
1974/* Timeout firmware commands after 10s */
1975#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB
1976
1977static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1978{
1979 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1980 struct mwl8k_priv *priv = hw->priv;
1981 void __iomem *regs = priv->regs;
1982 dma_addr_t dma_addr;
1983 unsigned int dma_size;
1984 int rc;
a66098da
LB
1985 unsigned long timeout = 0;
1986 u8 buf[32];
1987
b603742f 1988 cmd->result = (__force __le16) 0xffff;
a66098da
LB
1989 dma_size = le16_to_cpu(cmd->length);
1990 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1991 PCI_DMA_BIDIRECTIONAL);
1992 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1993 return -ENOMEM;
1994
618952a7 1995 rc = mwl8k_fw_lock(hw);
39a1e42e
LB
1996 if (rc) {
1997 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1998 PCI_DMA_BIDIRECTIONAL);
618952a7 1999 return rc;
39a1e42e 2000 }
a66098da 2001
a66098da
LB
2002 priv->hostcmd_wait = &cmd_wait;
2003 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
2004 iowrite32(MWL8K_H2A_INT_DOORBELL,
2005 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2006 iowrite32(MWL8K_H2A_INT_DUMMY,
2007 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB
2008
2009 timeout = wait_for_completion_timeout(&cmd_wait,
2010 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
2011
618952a7
LB
2012 priv->hostcmd_wait = NULL;
2013
2014 mwl8k_fw_unlock(hw);
2015
37055bd4
LB
2016 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2017 PCI_DMA_BIDIRECTIONAL);
2018
a66098da 2019 if (!timeout) {
5db55844 2020 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP
2021 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2022 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB
2023 rc = -ETIMEDOUT;
2024 } else {
0c9cc640
LB
2025 int ms;
2026
2027 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
2028
ce9e2e1b 2029 rc = cmd->result ? -EINVAL : 0;
a66098da 2030 if (rc)
5db55844 2031 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP
2032 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2033 le16_to_cpu(cmd->result));
0c9cc640 2034 else if (ms > 2000)
5db55844 2035 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP
2036 mwl8k_cmd_name(cmd->code,
2037 buf, sizeof(buf)),
2038 ms);
a66098da
LB
2039 }
2040
a66098da
LB
2041 return rc;
2042}
2043
f57ca9c1
LB
2044static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
2045 struct ieee80211_vif *vif,
2046 struct mwl8k_cmd_pkt *cmd)
2047{
2048 if (vif != NULL)
2049 cmd->macid = MWL8K_VIF(vif)->macid;
2050 return mwl8k_post_cmd(hw, cmd);
2051}
2052
1349ad2f
LB
2053/*
2054 * Setup code shared between STA and AP firmware images.
2055 */
2056static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
2057{
2058 struct mwl8k_priv *priv = hw->priv;
2059
2060 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
2061 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
2062
2063 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
2064 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
2065
2066 priv->band_24.band = IEEE80211_BAND_2GHZ;
2067 priv->band_24.channels = priv->channels_24;
2068 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
2069 priv->band_24.bitrates = priv->rates_24;
2070 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
2071
2072 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
2073}
2074
4eae9edd
LB
2075static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
2076{
2077 struct mwl8k_priv *priv = hw->priv;
2078
2079 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
2080 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
2081
2082 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
2083 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
2084
2085 priv->band_50.band = IEEE80211_BAND_5GHZ;
2086 priv->band_50.channels = priv->channels_50;
2087 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
2088 priv->band_50.bitrates = priv->rates_50;
2089 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
2090
2091 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
2092}
2093
a66098da 2094/*
04b147b1 2095 * CMD_GET_HW_SPEC (STA version).
a66098da 2096 */
04b147b1 2097struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB
2098 struct mwl8k_cmd_pkt header;
2099 __u8 hw_rev;
2100 __u8 host_interface;
2101 __le16 num_mcaddrs;
d89173f2 2102 __u8 perm_addr[ETH_ALEN];
a66098da
LB
2103 __le16 region_code;
2104 __le32 fw_rev;
2105 __le32 ps_cookie;
2106 __le32 caps;
2107 __u8 mcs_bitmap[16];
2108 __le32 rx_queue_ptr;
2109 __le32 num_tx_queues;
e600707b 2110 __le32 tx_queue_ptrs[MWL8K_TX_WMM_QUEUES];
a66098da
LB
2111 __le32 caps2;
2112 __le32 num_tx_desc_per_queue;
45eb400d 2113 __le32 total_rxd;
ba2d3587 2114} __packed;
a66098da 2115
341c9791
LB
2116#define MWL8K_CAP_MAX_AMSDU 0x20000000
2117#define MWL8K_CAP_GREENFIELD 0x08000000
2118#define MWL8K_CAP_AMPDU 0x04000000
2119#define MWL8K_CAP_RX_STBC 0x01000000
2120#define MWL8K_CAP_TX_STBC 0x00800000
2121#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2122#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2123#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2124#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2125#define MWL8K_CAP_DELAY_BA 0x00003000
2126#define MWL8K_CAP_MIMO 0x00000200
2127#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB
2128#define MWL8K_CAP_BAND_MASK 0x00000007
2129#define MWL8K_CAP_5GHZ 0x00000004
2130#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 2131
06953235
LB
2132static void
2133mwl8k_set_ht_caps(struct ieee80211_hw *hw,
2134 struct ieee80211_supported_band *band, u32 cap)
341c9791 2135{
341c9791
LB
2136 int rx_streams;
2137 int tx_streams;
2138
777ad375 2139 band->ht_cap.ht_supported = 1;
341c9791
LB
2140
2141 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 2142 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 2143 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 2144 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB
2145 if (cap & MWL8K_CAP_AMPDU) {
2146 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB
2147 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2148 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB
2149 }
2150 if (cap & MWL8K_CAP_RX_STBC)
777ad375 2151 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 2152 if (cap & MWL8K_CAP_TX_STBC)
777ad375 2153 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 2154 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 2155 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 2156 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 2157 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 2158 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 2159 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 2160 if (cap & MWL8K_CAP_40MHZ)
777ad375 2161 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB
2162
2163 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
2164 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
2165
777ad375 2166 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 2167 if (rx_streams >= 2)
777ad375 2168 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 2169 if (rx_streams >= 3)
777ad375
LB
2170 band->ht_cap.mcs.rx_mask[2] = 0xff;
2171 band->ht_cap.mcs.rx_mask[4] = 0x01;
2172 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB
2173
2174 if (rx_streams != tx_streams) {
777ad375
LB
2175 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
2176 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB
2177 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2178 }
2179}
2180
06953235
LB
2181static void
2182mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
2183{
2184 struct mwl8k_priv *priv = hw->priv;
2185
2186 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
2187 mwl8k_setup_2ghz_band(hw);
2188 if (caps & MWL8K_CAP_MIMO)
2189 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
2190 }
2191
2192 if (caps & MWL8K_CAP_5GHZ) {
2193 mwl8k_setup_5ghz_band(hw);
2194 if (caps & MWL8K_CAP_MIMO)
2195 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
2196 }
2197}
2198
04b147b1 2199static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB
2200{
2201 struct mwl8k_priv *priv = hw->priv;
04b147b1 2202 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB
2203 int rc;
2204 int i;
2205
2206 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2207 if (cmd == NULL)
2208 return -ENOMEM;
2209
2210 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2211 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2212
2213 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2214 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 2215 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b
BC
2216 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2217 for (i = 0; i < mwl8k_tx_queues(priv); i++)
45eb400d 2218 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 2219 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 2220 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB
2221
2222 rc = mwl8k_post_cmd(hw, &cmd->header);
2223
2224 if (!rc) {
2225 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2226 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 2227 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 2228 priv->hw_rev = cmd->hw_rev;
06953235 2229 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB
2230 priv->ap_macids_supported = 0x00000000;
2231 priv->sta_macids_supported = 0x00000001;
a66098da
LB
2232 }
2233
2234 kfree(cmd);
2235 return rc;
2236}
2237
42fba21d
LB
2238/*
2239 * CMD_GET_HW_SPEC (AP version).
2240 */
2241struct mwl8k_cmd_get_hw_spec_ap {
2242 struct mwl8k_cmd_pkt header;
2243 __u8 hw_rev;
2244 __u8 host_interface;
2245 __le16 num_wcb;
2246 __le16 num_mcaddrs;
2247 __u8 perm_addr[ETH_ALEN];
2248 __le16 region_code;
2249 __le16 num_antenna;
2250 __le32 fw_rev;
2251 __le32 wcbbase0;
2252 __le32 rxwrptr;
2253 __le32 rxrdptr;
2254 __le32 ps_cookie;
2255 __le32 wcbbase1;
2256 __le32 wcbbase2;
2257 __le32 wcbbase3;
952a0e96 2258 __le32 fw_api_version;
8a7a578c
BC
2259 __le32 caps;
2260 __le32 num_of_ampdu_queues;
2261 __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES];
ba2d3587 2262} __packed;
42fba21d
LB
2263
2264static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2265{
2266 struct mwl8k_priv *priv = hw->priv;
2267 struct mwl8k_cmd_get_hw_spec_ap *cmd;
8a7a578c 2268 int rc, i;
952a0e96 2269 u32 api_version;
42fba21d
LB
2270
2271 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2272 if (cmd == NULL)
2273 return -ENOMEM;
2274
2275 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2276 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2277
2278 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2279 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2280
2281 rc = mwl8k_post_cmd(hw, &cmd->header);
2282
2283 if (!rc) {
2284 int off;
2285
952a0e96
BC
2286 api_version = le32_to_cpu(cmd->fw_api_version);
2287 if (priv->device_info->fw_api_ap != api_version) {
2288 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2289 " Expected %d got %d.\n", MWL8K_NAME,
2290 priv->device_info->part_name,
2291 priv->device_info->fw_api_ap,
2292 api_version);
2293 rc = -EINVAL;
2294 goto done;
2295 }
42fba21d
LB
2296 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2297 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2298 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2299 priv->hw_rev = cmd->hw_rev;
8a7a578c 2300 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB
2301 priv->ap_macids_supported = 0x000000ff;
2302 priv->sta_macids_supported = 0x00000000;
8a7a578c
BC
2303 priv->num_ampdu_queues = le32_to_cpu(cmd->num_of_ampdu_queues);
2304 if (priv->num_ampdu_queues > MWL8K_MAX_AMPDU_QUEUES) {
2305 wiphy_warn(hw->wiphy, "fw reported %d ampdu queues"
2306 " but we only support %d.\n",
2307 priv->num_ampdu_queues,
2308 MWL8K_MAX_AMPDU_QUEUES);
2309 priv->num_ampdu_queues = MWL8K_MAX_AMPDU_QUEUES;
2310 }
42fba21d 2311 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2312 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB
2313
2314 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2315 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d 2316
73b46320
BC
2317 priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff;
2318 priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff;
2319 priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff;
2320 priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff;
8a7a578c
BC
2321
2322 for (i = 0; i < priv->num_ampdu_queues; i++)
e600707b 2323 priv->txq_offset[i + MWL8K_TX_WMM_QUEUES] =
8a7a578c 2324 le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff;
42fba21d
LB
2325 }
2326
952a0e96 2327done:
42fba21d
LB
2328 kfree(cmd);
2329 return rc;
2330}
2331
2332/*
2333 * CMD_SET_HW_SPEC.
2334 */
2335struct mwl8k_cmd_set_hw_spec {
2336 struct mwl8k_cmd_pkt header;
2337 __u8 hw_rev;
2338 __u8 host_interface;
2339 __le16 num_mcaddrs;
2340 __u8 perm_addr[ETH_ALEN];
2341 __le16 region_code;
2342 __le32 fw_rev;
2343 __le32 ps_cookie;
2344 __le32 caps;
2345 __le32 rx_queue_ptr;
2346 __le32 num_tx_queues;
e600707b 2347 __le32 tx_queue_ptrs[MWL8K_MAX_TX_QUEUES];
42fba21d
LB
2348 __le32 flags;
2349 __le32 num_tx_desc_per_queue;
2350 __le32 total_rxd;
ba2d3587 2351} __packed;
42fba21d 2352
8a7a578c
BC
2353/* If enabled, MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY will cause
2354 * packets to expire 500 ms after the timestamp in the tx descriptor. That is,
2355 * the packets that are queued for more than 500ms, will be dropped in the
2356 * hardware. This helps minimizing the issues caused due to head-of-line
2357 * blocking where a slow client can hog the bandwidth and affect traffic to a
2358 * faster client.
2359 */
2360#define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
b64fe619
LB
2361#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2362#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2363#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB
2364
2365static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2366{
2367 struct mwl8k_priv *priv = hw->priv;
2368 struct mwl8k_cmd_set_hw_spec *cmd;
2369 int rc;
2370 int i;
2371
2372 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2373 if (cmd == NULL)
2374 return -ENOMEM;
2375
2376 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2377 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2378
2379 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2380 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b 2381 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
85c9205c
NS
2382
2383 /*
2384 * Mac80211 stack has Q0 as highest priority and Q3 as lowest in
2385 * that order. Firmware has Q3 as highest priority and Q0 as lowest
2386 * in that order. Map Q3 of mac80211 to Q0 of firmware so that the
2387 * priority is interpreted the right way in firmware.
2388 */
e600707b
BC
2389 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
2390 int j = mwl8k_tx_queues(priv) - 1 - i;
85c9205c
NS
2391 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[j].txd_dma);
2392 }
2393
b64fe619
LB
2394 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2395 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
2396 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB
2397 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2398 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2399
2400 rc = mwl8k_post_cmd(hw, &cmd->header);
2401 kfree(cmd);
2402
2403 return rc;
2404}
2405
a66098da
LB
2406/*
2407 * CMD_MAC_MULTICAST_ADR.
2408 */
2409struct mwl8k_cmd_mac_multicast_adr {
2410 struct mwl8k_cmd_pkt header;
2411 __le16 action;
2412 __le16 numaddr;
ce9e2e1b 2413 __u8 addr[0][ETH_ALEN];
a66098da
LB
2414};
2415
d5e30845
LB
2416#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2417#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2418#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2419#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2420
e81cd2d6 2421static struct mwl8k_cmd_pkt *
447ced07 2422__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2423 struct netdev_hw_addr_list *mc_list)
a66098da 2424{
e81cd2d6 2425 struct mwl8k_priv *priv = hw->priv;
a66098da 2426 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2427 int size;
22bedad3
JP
2428 int mc_count = 0;
2429
2430 if (mc_list)
2431 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2432
447ced07 2433 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB
2434 allmulti = 1;
2435 mc_count = 0;
2436 }
e81cd2d6
LB
2437
2438 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2439
e81cd2d6 2440 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2441 if (cmd == NULL)
e81cd2d6 2442 return NULL;
a66098da
LB
2443
2444 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2445 cmd->header.length = cpu_to_le16(size);
d5e30845
LB
2446 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2447 MWL8K_ENABLE_RX_BROADCAST);
2448
2449 if (allmulti) {
2450 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2451 } else if (mc_count) {
22bedad3
JP
2452 struct netdev_hw_addr *ha;
2453 int i = 0;
d5e30845
LB
2454
2455 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2456 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP
2457 netdev_hw_addr_list_for_each(ha, mc_list) {
2458 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2459 }
a66098da
LB
2460 }
2461
e81cd2d6 2462 return &cmd->header;
a66098da
LB
2463}
2464
2465/*
55489b6e 2466 * CMD_GET_STAT.
a66098da 2467 */
55489b6e 2468struct mwl8k_cmd_get_stat {
a66098da 2469 struct mwl8k_cmd_pkt header;
a66098da 2470 __le32 stats[64];
ba2d3587 2471} __packed;
a66098da
LB
2472
2473#define MWL8K_STAT_ACK_FAILURE 9
2474#define MWL8K_STAT_RTS_FAILURE 12
2475#define MWL8K_STAT_FCS_ERROR 24
2476#define MWL8K_STAT_RTS_SUCCESS 11
2477
55489b6e
LB
2478static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2479 struct ieee80211_low_level_stats *stats)
a66098da 2480{
55489b6e 2481 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB
2482 int rc;
2483
2484 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2485 if (cmd == NULL)
2486 return -ENOMEM;
2487
2488 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2489 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB
2490
2491 rc = mwl8k_post_cmd(hw, &cmd->header);
2492 if (!rc) {
2493 stats->dot11ACKFailureCount =
2494 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2495 stats->dot11RTSFailureCount =
2496 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2497 stats->dot11FCSErrorCount =
2498 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2499 stats->dot11RTSSuccessCount =
2500 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2501 }
2502 kfree(cmd);
2503
2504 return rc;
2505}
2506
2507/*
55489b6e 2508 * CMD_RADIO_CONTROL.
a66098da 2509 */
55489b6e 2510struct mwl8k_cmd_radio_control {
a66098da
LB
2511 struct mwl8k_cmd_pkt header;
2512 __le16 action;
2513 __le16 control;
2514 __le16 radio_on;
ba2d3587 2515} __packed;
a66098da 2516
c46563b7 2517static int
55489b6e 2518mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB
2519{
2520 struct mwl8k_priv *priv = hw->priv;
55489b6e 2521 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB
2522 int rc;
2523
c46563b7 2524 if (enable == priv->radio_on && !force)
a66098da
LB
2525 return 0;
2526
a66098da
LB
2527 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2528 if (cmd == NULL)
2529 return -ENOMEM;
2530
2531 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2532 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2533 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2534 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB
2535 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2536
2537 rc = mwl8k_post_cmd(hw, &cmd->header);
2538 kfree(cmd);
2539
2540 if (!rc)
c46563b7 2541 priv->radio_on = enable;
a66098da
LB
2542
2543 return rc;
2544}
2545
55489b6e 2546static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2547{
55489b6e 2548 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB
2549}
2550
55489b6e 2551static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2552{
55489b6e 2553 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB
2554}
2555
a66098da
LB
2556static int
2557mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2558{
99200a99 2559 struct mwl8k_priv *priv = hw->priv;
a66098da 2560
68ce3884 2561 priv->radio_short_preamble = short_preamble;
a66098da 2562
55489b6e 2563 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB
2564}
2565
2566/*
55489b6e 2567 * CMD_RF_TX_POWER.
a66098da 2568 */
41fdf097 2569#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2570
55489b6e 2571struct mwl8k_cmd_rf_tx_power {
a66098da
LB
2572 struct mwl8k_cmd_pkt header;
2573 __le16 action;
2574 __le16 support_level;
2575 __le16 current_level;
2576 __le16 reserved;
41fdf097 2577 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2578} __packed;
a66098da 2579
55489b6e 2580static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2581{
55489b6e 2582 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB
2583 int rc;
2584
2585 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2586 if (cmd == NULL)
2587 return -ENOMEM;
2588
2589 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2590 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2591 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2592 cmd->support_level = cpu_to_le16(dBm);
2593
2594 rc = mwl8k_post_cmd(hw, &cmd->header);
2595 kfree(cmd);
2596
2597 return rc;
2598}
2599
41fdf097
NS
2600/*
2601 * CMD_TX_POWER.
2602 */
2603#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2604
2605struct mwl8k_cmd_tx_power {
2606 struct mwl8k_cmd_pkt header;
2607 __le16 action;
2608 __le16 band;
2609 __le16 channel;
2610 __le16 bw;
2611 __le16 sub_ch;
2612 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2613} __attribute__((packed));
2614
2615static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2616 struct ieee80211_conf *conf,
2617 unsigned short pwr)
2618{
2619 struct ieee80211_channel *channel = conf->channel;
2620 struct mwl8k_cmd_tx_power *cmd;
2621 int rc;
2622 int i;
2623
2624 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2625 if (cmd == NULL)
2626 return -ENOMEM;
2627
2628 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2629 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2630 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2631
2632 if (channel->band == IEEE80211_BAND_2GHZ)
2633 cmd->band = cpu_to_le16(0x1);
2634 else if (channel->band == IEEE80211_BAND_5GHZ)
2635 cmd->band = cpu_to_le16(0x4);
2636
2637 cmd->channel = channel->hw_value;
2638
2639 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2640 conf->channel_type == NL80211_CHAN_HT20) {
2641 cmd->bw = cpu_to_le16(0x2);
2642 } else {
2643 cmd->bw = cpu_to_le16(0x4);
2644 if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2645 cmd->sub_ch = cpu_to_le16(0x3);
2646 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2647 cmd->sub_ch = cpu_to_le16(0x1);
2648 }
2649
2650 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2651 cmd->power_level_list[i] = cpu_to_le16(pwr);
2652
2653 rc = mwl8k_post_cmd(hw, &cmd->header);
2654 kfree(cmd);
2655
2656 return rc;
2657}
2658
08b06347
LB
2659/*
2660 * CMD_RF_ANTENNA.
2661 */
2662struct mwl8k_cmd_rf_antenna {
2663 struct mwl8k_cmd_pkt header;
2664 __le16 antenna;
2665 __le16 mode;
ba2d3587 2666} __packed;
08b06347
LB
2667
2668#define MWL8K_RF_ANTENNA_RX 1
2669#define MWL8K_RF_ANTENNA_TX 2
2670
2671static int
2672mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2673{
2674 struct mwl8k_cmd_rf_antenna *cmd;
2675 int rc;
2676
2677 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2678 if (cmd == NULL)
2679 return -ENOMEM;
2680
2681 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2682 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2683 cmd->antenna = cpu_to_le16(antenna);
2684 cmd->mode = cpu_to_le16(mask);
2685
2686 rc = mwl8k_post_cmd(hw, &cmd->header);
2687 kfree(cmd);
2688
2689 return rc;
2690}
2691
b64fe619
LB
2692/*
2693 * CMD_SET_BEACON.
2694 */
2695struct mwl8k_cmd_set_beacon {
2696 struct mwl8k_cmd_pkt header;
2697 __le16 beacon_len;
2698 __u8 beacon[0];
2699};
2700
aa21d0f6
LB
2701static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2702 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB
2703{
2704 struct mwl8k_cmd_set_beacon *cmd;
2705 int rc;
2706
2707 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2708 if (cmd == NULL)
2709 return -ENOMEM;
2710
2711 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2712 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2713 cmd->beacon_len = cpu_to_le16(len);
2714 memcpy(cmd->beacon, beacon, len);
2715
aa21d0f6 2716 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB
2717 kfree(cmd);
2718
2719 return rc;
2720}
2721
a66098da
LB
2722/*
2723 * CMD_SET_PRE_SCAN.
2724 */
2725struct mwl8k_cmd_set_pre_scan {
2726 struct mwl8k_cmd_pkt header;
ba2d3587 2727} __packed;
a66098da
LB
2728
2729static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2730{
2731 struct mwl8k_cmd_set_pre_scan *cmd;
2732 int rc;
2733
2734 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2735 if (cmd == NULL)
2736 return -ENOMEM;
2737
2738 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2739 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2740
2741 rc = mwl8k_post_cmd(hw, &cmd->header);
2742 kfree(cmd);
2743
2744 return rc;
2745}
2746
2747/*
2748 * CMD_SET_POST_SCAN.
2749 */
2750struct mwl8k_cmd_set_post_scan {
2751 struct mwl8k_cmd_pkt header;
2752 __le32 isibss;
d89173f2 2753 __u8 bssid[ETH_ALEN];
ba2d3587 2754} __packed;
a66098da
LB
2755
2756static int
0a11dfc3 2757mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB
2758{
2759 struct mwl8k_cmd_set_post_scan *cmd;
2760 int rc;
2761
2762 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2763 if (cmd == NULL)
2764 return -ENOMEM;
2765
2766 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2767 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2768 cmd->isibss = 0;
d89173f2 2769 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB
2770
2771 rc = mwl8k_post_cmd(hw, &cmd->header);
2772 kfree(cmd);
2773
2774 return rc;
2775}
2776
2777/*
2778 * CMD_SET_RF_CHANNEL.
2779 */
2780struct mwl8k_cmd_set_rf_channel {
2781 struct mwl8k_cmd_pkt header;
2782 __le16 action;
2783 __u8 current_channel;
2784 __le32 channel_flags;
ba2d3587 2785} __packed;
a66098da
LB
2786
2787static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2788 struct ieee80211_conf *conf)
a66098da 2789{
610677d2 2790 struct ieee80211_channel *channel = conf->channel;
a66098da
LB
2791 struct mwl8k_cmd_set_rf_channel *cmd;
2792 int rc;
2793
2794 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2795 if (cmd == NULL)
2796 return -ENOMEM;
2797
2798 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2799 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2800 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2801 cmd->current_channel = channel->hw_value;
610677d2 2802
a66098da 2803 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 2804 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB
2805 else if (channel->band == IEEE80211_BAND_5GHZ)
2806 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB
2807
2808 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2809 conf->channel_type == NL80211_CHAN_HT20)
2810 cmd->channel_flags |= cpu_to_le32(0x00000080);
2811 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2812 cmd->channel_flags |= cpu_to_le32(0x000001900);
2813 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2814 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB
2815
2816 rc = mwl8k_post_cmd(hw, &cmd->header);
2817 kfree(cmd);
2818
2819 return rc;
2820}
2821
2822/*
55489b6e 2823 * CMD_SET_AID.
a66098da 2824 */
55489b6e
LB
2825#define MWL8K_FRAME_PROT_DISABLED 0x00
2826#define MWL8K_FRAME_PROT_11G 0x07
2827#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2828#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2829
55489b6e
LB
2830struct mwl8k_cmd_update_set_aid {
2831 struct mwl8k_cmd_pkt header;
2832 __le16 aid;
a66098da 2833
55489b6e
LB
2834 /* AP's MAC address (BSSID) */
2835 __u8 bssid[ETH_ALEN];
2836 __le16 protection_mode;
2837 __u8 supp_rates[14];
ba2d3587 2838} __packed;
a66098da 2839
c6e96010
LB
2840static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2841{
2842 int i;
2843 int j;
2844
2845 /*
2846 * Clear nonstandard rates 4 and 13.
2847 */
2848 mask &= 0x1fef;
2849
2850 for (i = 0, j = 0; i < 14; i++) {
2851 if (mask & (1 << i))
777ad375 2852 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB
2853 }
2854}
2855
55489b6e 2856static int
c6e96010
LB
2857mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2858 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2859{
55489b6e
LB
2860 struct mwl8k_cmd_update_set_aid *cmd;
2861 u16 prot_mode;
a66098da
LB
2862 int rc;
2863
2864 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2865 if (cmd == NULL)
2866 return -ENOMEM;
2867
55489b6e 2868 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2869 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2870 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2871 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2872
7dc6a7a7 2873 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB
2874 prot_mode = MWL8K_FRAME_PROT_11G;
2875 } else {
7dc6a7a7 2876 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB
2877 IEEE80211_HT_OP_MODE_PROTECTION) {
2878 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2879 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2880 break;
2881 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2882 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2883 break;
2884 default:
2885 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2886 break;
2887 }
2888 }
2889 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2890
c6e96010 2891 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB
2892
2893 rc = mwl8k_post_cmd(hw, &cmd->header);
2894 kfree(cmd);
2895
2896 return rc;
2897}
2898
32060e1b 2899/*
55489b6e 2900 * CMD_SET_RATE.
32060e1b 2901 */
55489b6e
LB
2902struct mwl8k_cmd_set_rate {
2903 struct mwl8k_cmd_pkt header;
2904 __u8 legacy_rates[14];
2905
2906 /* Bitmap for supported MCS codes. */
2907 __u8 mcs_set[16];
2908 __u8 reserved[16];
ba2d3587 2909} __packed;
32060e1b 2910
55489b6e 2911static int
c6e96010 2912mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2913 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2914{
55489b6e 2915 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB
2916 int rc;
2917
2918 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2919 if (cmd == NULL)
2920 return -ENOMEM;
2921
55489b6e 2922 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2923 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2924 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2925 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB
2926
2927 rc = mwl8k_post_cmd(hw, &cmd->header);
2928 kfree(cmd);
2929
2930 return rc;
2931}
2932
a66098da 2933/*
55489b6e 2934 * CMD_FINALIZE_JOIN.
a66098da 2935 */
55489b6e
LB
2936#define MWL8K_FJ_BEACON_MAXLEN 128
2937
2938struct mwl8k_cmd_finalize_join {
a66098da 2939 struct mwl8k_cmd_pkt header;
55489b6e
LB
2940 __le32 sleep_interval; /* Number of beacon periods to sleep */
2941 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 2942} __packed;
a66098da 2943
55489b6e
LB
2944static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2945 int framelen, int dtim)
a66098da 2946{
55489b6e
LB
2947 struct mwl8k_cmd_finalize_join *cmd;
2948 struct ieee80211_mgmt *payload = frame;
2949 int payload_len;
a66098da
LB
2950 int rc;
2951
2952 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2953 if (cmd == NULL)
2954 return -ENOMEM;
2955
55489b6e 2956 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2957 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
2958 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2959
2960 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2961 if (payload_len < 0)
2962 payload_len = 0;
2963 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2964 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2965
2966 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB
2967
2968 rc = mwl8k_post_cmd(hw, &cmd->header);
2969 kfree(cmd);
2970
2971 return rc;
2972}
2973
2974/*
55489b6e 2975 * CMD_SET_RTS_THRESHOLD.
a66098da 2976 */
55489b6e 2977struct mwl8k_cmd_set_rts_threshold {
a66098da
LB
2978 struct mwl8k_cmd_pkt header;
2979 __le16 action;
55489b6e 2980 __le16 threshold;
ba2d3587 2981} __packed;
a66098da 2982
c2c2b12a
LB
2983static int
2984mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2985{
55489b6e 2986 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB
2987 int rc;
2988
2989 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2990 if (cmd == NULL)
2991 return -ENOMEM;
2992
55489b6e 2993 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2994 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB
2995 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2996 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB
2997
2998 rc = mwl8k_post_cmd(hw, &cmd->header);
2999 kfree(cmd);
3000
a66098da
LB
3001 return rc;
3002}
3003
3004/*
55489b6e 3005 * CMD_SET_SLOT.
a66098da 3006 */
55489b6e 3007struct mwl8k_cmd_set_slot {
a66098da
LB
3008 struct mwl8k_cmd_pkt header;
3009 __le16 action;
55489b6e 3010 __u8 short_slot;
ba2d3587 3011} __packed;
a66098da 3012
55489b6e 3013static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 3014{
55489b6e 3015 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB
3016 int rc;
3017
3018 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3019 if (cmd == NULL)
3020 return -ENOMEM;
3021
55489b6e 3022 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 3023 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
3024 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3025 cmd->short_slot = short_slot_time;
a66098da
LB
3026
3027 rc = mwl8k_post_cmd(hw, &cmd->header);
3028 kfree(cmd);
3029
3030 return rc;
3031}
3032
3033/*
3034 * CMD_SET_EDCA_PARAMS.
3035 */
3036struct mwl8k_cmd_set_edca_params {
3037 struct mwl8k_cmd_pkt header;
3038
3039 /* See MWL8K_SET_EDCA_XXX below */
3040 __le16 action;
3041
3042 /* TX opportunity in units of 32 us */
3043 __le16 txop;
3044
2e484c89
LB
3045 union {
3046 struct {
3047 /* Log exponent of max contention period: 0...15 */
3048 __le32 log_cw_max;
3049
3050 /* Log exponent of min contention period: 0...15 */
3051 __le32 log_cw_min;
3052
3053 /* Adaptive interframe spacing in units of 32us */
3054 __u8 aifs;
3055
3056 /* TX queue to configure */
3057 __u8 txq;
3058 } ap;
3059 struct {
3060 /* Log exponent of max contention period: 0...15 */
3061 __u8 log_cw_max;
a66098da 3062
2e484c89
LB
3063 /* Log exponent of min contention period: 0...15 */
3064 __u8 log_cw_min;
a66098da 3065
2e484c89
LB
3066 /* Adaptive interframe spacing in units of 32us */
3067 __u8 aifs;
a66098da 3068
2e484c89
LB
3069 /* TX queue to configure */
3070 __u8 txq;
3071 } sta;
3072 };
ba2d3587 3073} __packed;
a66098da 3074
a66098da
LB
3075#define MWL8K_SET_EDCA_CW 0x01
3076#define MWL8K_SET_EDCA_TXOP 0x02
3077#define MWL8K_SET_EDCA_AIFS 0x04
3078
3079#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
3080 MWL8K_SET_EDCA_TXOP | \
3081 MWL8K_SET_EDCA_AIFS)
3082
3083static int
55489b6e
LB
3084mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
3085 __u16 cw_min, __u16 cw_max,
3086 __u8 aifs, __u16 txop)
a66098da 3087{
2e484c89 3088 struct mwl8k_priv *priv = hw->priv;
a66098da 3089 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB
3090 int rc;
3091
3092 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3093 if (cmd == NULL)
3094 return -ENOMEM;
3095
a66098da
LB
3096 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
3097 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB
3098 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
3099 cmd->txop = cpu_to_le16(txop);
2e484c89
LB
3100 if (priv->ap_fw) {
3101 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
3102 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
3103 cmd->ap.aifs = aifs;
3104 cmd->ap.txq = qnum;
3105 } else {
3106 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
3107 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
3108 cmd->sta.aifs = aifs;
3109 cmd->sta.txq = qnum;
3110 }
a66098da
LB
3111
3112 rc = mwl8k_post_cmd(hw, &cmd->header);
3113 kfree(cmd);
3114
3115 return rc;
3116}
3117
3118/*
55489b6e 3119 * CMD_SET_WMM_MODE.
a66098da 3120 */
55489b6e 3121struct mwl8k_cmd_set_wmm_mode {
a66098da 3122 struct mwl8k_cmd_pkt header;
55489b6e 3123 __le16 action;
ba2d3587 3124} __packed;
a66098da 3125
55489b6e 3126static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 3127{
55489b6e
LB
3128 struct mwl8k_priv *priv = hw->priv;
3129 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB
3130 int rc;
3131
a66098da
LB
3132 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3133 if (cmd == NULL)
3134 return -ENOMEM;
3135
55489b6e 3136 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 3137 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 3138 cmd->action = cpu_to_le16(!!enable);
a66098da
LB
3139
3140 rc = mwl8k_post_cmd(hw, &cmd->header);
3141 kfree(cmd);
16cec43d 3142
55489b6e
LB
3143 if (!rc)
3144 priv->wmm_enabled = enable;
a66098da
LB
3145
3146 return rc;
3147}
3148
3149/*
55489b6e 3150 * CMD_MIMO_CONFIG.
a66098da 3151 */
55489b6e
LB
3152struct mwl8k_cmd_mimo_config {
3153 struct mwl8k_cmd_pkt header;
3154 __le32 action;
3155 __u8 rx_antenna_map;
3156 __u8 tx_antenna_map;
ba2d3587 3157} __packed;
a66098da 3158
55489b6e 3159static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 3160{
55489b6e 3161 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB
3162 int rc;
3163
3164 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3165 if (cmd == NULL)
3166 return -ENOMEM;
3167
55489b6e 3168 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 3169 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
3170 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
3171 cmd->rx_antenna_map = rx;
3172 cmd->tx_antenna_map = tx;
a66098da
LB
3173
3174 rc = mwl8k_post_cmd(hw, &cmd->header);
3175 kfree(cmd);
3176
3177 return rc;
3178}
3179
3180/*
b71ed2c6 3181 * CMD_USE_FIXED_RATE (STA version).
a66098da 3182 */
b71ed2c6
LB
3183struct mwl8k_cmd_use_fixed_rate_sta {
3184 struct mwl8k_cmd_pkt header;
3185 __le32 action;
3186 __le32 allow_rate_drop;
3187 __le32 num_rates;
3188 struct {
3189 __le32 is_ht_rate;
3190 __le32 enable_retry;
3191 __le32 rate;
3192 __le32 retry_count;
3193 } rate_entry[8];
3194 __le32 rate_type;
3195 __le32 reserved1;
3196 __le32 reserved2;
ba2d3587 3197} __packed;
a66098da 3198
b71ed2c6
LB
3199#define MWL8K_USE_AUTO_RATE 0x0002
3200#define MWL8K_UCAST_RATE 0
a66098da 3201
b71ed2c6 3202static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 3203{
b71ed2c6 3204 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB
3205 int rc;
3206
3207 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3208 if (cmd == NULL)
3209 return -ENOMEM;
3210
3211 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3212 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB
3213 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3214 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB
3215
3216 rc = mwl8k_post_cmd(hw, &cmd->header);
3217 kfree(cmd);
3218
3219 return rc;
3220}
3221
088aab8b
LB
3222/*
3223 * CMD_USE_FIXED_RATE (AP version).
3224 */
3225struct mwl8k_cmd_use_fixed_rate_ap {
3226 struct mwl8k_cmd_pkt header;
3227 __le32 action;
3228 __le32 allow_rate_drop;
3229 __le32 num_rates;
3230 struct mwl8k_rate_entry_ap {
3231 __le32 is_ht_rate;
3232 __le32 enable_retry;
3233 __le32 rate;
3234 __le32 retry_count;
3235 } rate_entry[4];
3236 u8 multicast_rate;
3237 u8 multicast_rate_type;
3238 u8 management_rate;
ba2d3587 3239} __packed;
088aab8b
LB
3240
3241static int
3242mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
3243{
3244 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
3245 int rc;
3246
3247 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3248 if (cmd == NULL)
3249 return -ENOMEM;
3250
3251 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3252 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3253 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3254 cmd->multicast_rate = mcast;
3255 cmd->management_rate = mgmt;
3256
3257 rc = mwl8k_post_cmd(hw, &cmd->header);
3258 kfree(cmd);
3259
3260 return rc;
3261}
3262
55489b6e
LB
3263/*
3264 * CMD_ENABLE_SNIFFER.
3265 */
3266struct mwl8k_cmd_enable_sniffer {
3267 struct mwl8k_cmd_pkt header;
3268 __le32 action;
ba2d3587 3269} __packed;
55489b6e
LB
3270
3271static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3272{
3273 struct mwl8k_cmd_enable_sniffer *cmd;
3274 int rc;
3275
3276 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3277 if (cmd == NULL)
3278 return -ENOMEM;
3279
3280 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3281 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3282 cmd->action = cpu_to_le32(!!enable);
3283
3284 rc = mwl8k_post_cmd(hw, &cmd->header);
3285 kfree(cmd);
3286
3287 return rc;
3288}
3289
3290/*
3291 * CMD_SET_MAC_ADDR.
3292 */
3293struct mwl8k_cmd_set_mac_addr {
3294 struct mwl8k_cmd_pkt header;
3295 union {
3296 struct {
3297 __le16 mac_type;
3298 __u8 mac_addr[ETH_ALEN];
3299 } mbss;
3300 __u8 mac_addr[ETH_ALEN];
3301 };
ba2d3587 3302} __packed;
55489b6e 3303
ee0ddf18
LB
3304#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3305#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3306#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3307#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3308
aa21d0f6
LB
3309static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3310 struct ieee80211_vif *vif, u8 *mac)
55489b6e
LB
3311{
3312 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3313 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
55489b6e 3314 struct mwl8k_cmd_set_mac_addr *cmd;
ee0ddf18 3315 int mac_type;
55489b6e
LB
3316 int rc;
3317
ee0ddf18
LB
3318 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3319 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3320 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
3321 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
3322 else
3323 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3324 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3325 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3326 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3327 else
3328 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3329 }
3330
55489b6e
LB
3331 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3332 if (cmd == NULL)
3333 return -ENOMEM;
3334
3335 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3336 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3337 if (priv->ap_fw) {
ee0ddf18 3338 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB
3339 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3340 } else {
3341 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3342 }
3343
aa21d0f6 3344 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB
3345 kfree(cmd);
3346
3347 return rc;
3348}
3349
3350/*
3351 * CMD_SET_RATEADAPT_MODE.
3352 */
3353struct mwl8k_cmd_set_rate_adapt_mode {
3354 struct mwl8k_cmd_pkt header;
3355 __le16 action;
3356 __le16 mode;
ba2d3587 3357} __packed;
55489b6e
LB
3358
3359static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3360{
3361 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3362 int rc;
3363
3364 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3365 if (cmd == NULL)
3366 return -ENOMEM;
3367
3368 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3369 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3370 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3371 cmd->mode = cpu_to_le16(mode);
3372
3373 rc = mwl8k_post_cmd(hw, &cmd->header);
3374 kfree(cmd);
3375
3376 return rc;
3377}
3378
3aefc37e
NS
3379/*
3380 * CMD_GET_WATCHDOG_BITMAP.
3381 */
3382struct mwl8k_cmd_get_watchdog_bitmap {
3383 struct mwl8k_cmd_pkt header;
3384 u8 bitmap;
3385} __packed;
3386
3387static int mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw *hw, u8 *bitmap)
3388{
3389 struct mwl8k_cmd_get_watchdog_bitmap *cmd;
3390 int rc;
3391
3392 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3393 if (cmd == NULL)
3394 return -ENOMEM;
3395
3396 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_WATCHDOG_BITMAP);
3397 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3398
3399 rc = mwl8k_post_cmd(hw, &cmd->header);
3400 if (!rc)
3401 *bitmap = cmd->bitmap;
3402
3403 kfree(cmd);
3404
3405 return rc;
3406}
3407
3408#define INVALID_BA 0xAA
3409static void mwl8k_watchdog_ba_events(struct work_struct *work)
3410{
3411 int rc;
3412 u8 bitmap = 0, stream_index;
3413 struct mwl8k_ampdu_stream *streams;
3414 struct mwl8k_priv *priv =
3415 container_of(work, struct mwl8k_priv, watchdog_ba_handle);
3416
3417 rc = mwl8k_cmd_get_watchdog_bitmap(priv->hw, &bitmap);
3418 if (rc)
3419 return;
3420
3421 if (bitmap == INVALID_BA)
3422 return;
3423
3424 /* the bitmap is the hw queue number. Map it to the ampdu queue. */
3425 stream_index = bitmap - MWL8K_TX_WMM_QUEUES;
3426
3427 BUG_ON(stream_index >= priv->num_ampdu_queues);
3428
3429 streams = &priv->ampdu[stream_index];
3430
3431 if (streams->state == AMPDU_STREAM_ACTIVE)
3432 ieee80211_stop_tx_ba_session(streams->sta, streams->tid);
3433
3434 return;
3435}
3436
3437
b64fe619
LB
3438/*
3439 * CMD_BSS_START.
3440 */
3441struct mwl8k_cmd_bss_start {
3442 struct mwl8k_cmd_pkt header;
3443 __le32 enable;
ba2d3587 3444} __packed;
b64fe619 3445
aa21d0f6
LB
3446static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3447 struct ieee80211_vif *vif, int enable)
b64fe619
LB
3448{
3449 struct mwl8k_cmd_bss_start *cmd;
3450 int rc;
3451
3452 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3453 if (cmd == NULL)
3454 return -ENOMEM;
3455
3456 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3457 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3458 cmd->enable = cpu_to_le32(enable);
3459
aa21d0f6 3460 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB
3461 kfree(cmd);
3462
3463 return rc;
3464}
3465
5faa1aff
NS
3466/*
3467 * CMD_BASTREAM.
3468 */
3469
3470/*
3471 * UPSTREAM is tx direction
3472 */
3473#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3474#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3475
3476enum {
3477 MWL8K_BA_CREATE,
3478 MWL8K_BA_UPDATE,
3479 MWL8K_BA_DESTROY,
3480 MWL8K_BA_FLUSH,
3481 MWL8K_BA_CHECK,
3482} ba_stream_action_type;
3483
3484
3485struct mwl8k_create_ba_stream {
3486 __le32 flags;
3487 __le32 idle_thrs;
3488 __le32 bar_thrs;
3489 __le32 window_size;
3490 u8 peer_mac_addr[6];
3491 u8 dialog_token;
3492 u8 tid;
3493 u8 queue_id;
3494 u8 param_info;
3495 __le32 ba_context;
3496 u8 reset_seq_no_flag;
3497 __le16 curr_seq_no;
3498 u8 sta_src_mac_addr[6];
3499} __packed;
3500
3501struct mwl8k_destroy_ba_stream {
3502 __le32 flags;
3503 __le32 ba_context;
3504} __packed;
3505
3506struct mwl8k_cmd_bastream {
3507 struct mwl8k_cmd_pkt header;
3508 __le32 action;
3509 union {
3510 struct mwl8k_create_ba_stream create_params;
3511 struct mwl8k_destroy_ba_stream destroy_params;
3512 };
3513} __packed;
3514
3515static int
3516mwl8k_check_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
3517{
3518 struct mwl8k_cmd_bastream *cmd;
3519 int rc;
3520
3521 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3522 if (cmd == NULL)
3523 return -ENOMEM;
3524
3525 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3526 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3527
3528 cmd->action = cpu_to_le32(MWL8K_BA_CHECK);
3529
3530 cmd->create_params.queue_id = stream->idx;
3531 memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr,
3532 ETH_ALEN);
3533 cmd->create_params.tid = stream->tid;
3534
3535 cmd->create_params.flags =
3536 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE) |
3537 cpu_to_le32(BASTREAM_FLAG_DIRECTION_UPSTREAM);
3538
3539 rc = mwl8k_post_cmd(hw, &cmd->header);
3540
3541 kfree(cmd);
3542
3543 return rc;
3544}
3545
3546static int
3547mwl8k_create_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
3548 u8 buf_size)
3549{
3550 struct mwl8k_cmd_bastream *cmd;
3551 int rc;
3552
3553 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3554 if (cmd == NULL)
3555 return -ENOMEM;
3556
3557
3558 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3559 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3560
3561 cmd->action = cpu_to_le32(MWL8K_BA_CREATE);
3562
3563 cmd->create_params.bar_thrs = cpu_to_le32((u32)buf_size);
3564 cmd->create_params.window_size = cpu_to_le32((u32)buf_size);
3565 cmd->create_params.queue_id = stream->idx;
3566
3567 memcpy(cmd->create_params.peer_mac_addr, stream->sta->addr, ETH_ALEN);
3568 cmd->create_params.tid = stream->tid;
3569 cmd->create_params.curr_seq_no = cpu_to_le16(0);
3570 cmd->create_params.reset_seq_no_flag = 1;
3571
3572 cmd->create_params.param_info =
3573 (stream->sta->ht_cap.ampdu_factor &
3574 IEEE80211_HT_AMPDU_PARM_FACTOR) |
3575 ((stream->sta->ht_cap.ampdu_density << 2) &
3576 IEEE80211_HT_AMPDU_PARM_DENSITY);
3577
3578 cmd->create_params.flags =
3579 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE |
3580 BASTREAM_FLAG_DIRECTION_UPSTREAM);
3581
3582 rc = mwl8k_post_cmd(hw, &cmd->header);
3583
3584 wiphy_debug(hw->wiphy, "Created a BA stream for %pM : tid %d\n",
3585 stream->sta->addr, stream->tid);
3586 kfree(cmd);
3587
3588 return rc;
3589}
3590
3591static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
3592 struct mwl8k_ampdu_stream *stream)
3593{
3594 struct mwl8k_cmd_bastream *cmd;
3595
3596 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3597 if (cmd == NULL)
3598 return;
3599
3600 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3601 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3602 cmd->action = cpu_to_le32(MWL8K_BA_DESTROY);
3603
3604 cmd->destroy_params.ba_context = cpu_to_le32(stream->idx);
3605 mwl8k_post_cmd(hw, &cmd->header);
3606
3607 wiphy_debug(hw->wiphy, "Deleted BA stream index %d\n", stream->idx);
3608
3609 kfree(cmd);
3610}
3611
3f5610ff
LB
3612/*
3613 * CMD_SET_NEW_STN.
3614 */
3615struct mwl8k_cmd_set_new_stn {
3616 struct mwl8k_cmd_pkt header;
3617 __le16 aid;
3618 __u8 mac_addr[6];
3619 __le16 stn_id;
3620 __le16 action;
3621 __le16 rsvd;
3622 __le32 legacy_rates;
3623 __u8 ht_rates[4];
3624 __le16 cap_info;
3625 __le16 ht_capabilities_info;
3626 __u8 mac_ht_param_info;
3627 __u8 rev;
3628 __u8 control_channel;
3629 __u8 add_channel;
3630 __le16 op_mode;
3631 __le16 stbc;
3632 __u8 add_qos_info;
3633 __u8 is_qos_sta;
3634 __le32 fw_sta_ptr;
ba2d3587 3635} __packed;
3f5610ff
LB
3636
3637#define MWL8K_STA_ACTION_ADD 0
3638#define MWL8K_STA_ACTION_REMOVE 2
3639
3640static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
3641 struct ieee80211_vif *vif,
3642 struct ieee80211_sta *sta)
3643{
3644 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 3645 u32 rates;
3f5610ff
LB
3646 int rc;
3647
3648 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3649 if (cmd == NULL)
3650 return -ENOMEM;
3651
3652 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3653 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3654 cmd->aid = cpu_to_le16(sta->aid);
3655 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
3656 cmd->stn_id = cpu_to_le16(sta->aid);
3657 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB
3658 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3659 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3660 else
3661 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3662 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB
3663 if (sta->ht_cap.ht_supported) {
3664 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
3665 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
3666 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
3667 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
3668 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
3669 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
3670 ((sta->ht_cap.ampdu_density & 7) << 2);
3671 cmd->is_qos_sta = 1;
3672 }
3673
aa21d0f6 3674 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB
3675 kfree(cmd);
3676
3677 return rc;
3678}
3679
b64fe619
LB
3680static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
3681 struct ieee80211_vif *vif)
3682{
3683 struct mwl8k_cmd_set_new_stn *cmd;
3684 int rc;
3685
3686 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3687 if (cmd == NULL)
3688 return -ENOMEM;
3689
3690 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3691 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3692 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
3693
aa21d0f6 3694 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB
3695 kfree(cmd);
3696
3697 return rc;
3698}
3699
3f5610ff
LB
3700static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
3701 struct ieee80211_vif *vif, u8 *addr)
3702{
3703 struct mwl8k_cmd_set_new_stn *cmd;
3704 int rc;
3705
3706 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3707 if (cmd == NULL)
3708 return -ENOMEM;
3709
3710 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3711 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3712 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3713 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
3714
aa21d0f6 3715 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB
3716 kfree(cmd);
3717
3718 return rc;
3719}
3720
fcdc403c
NS
3721/*
3722 * CMD_UPDATE_ENCRYPTION.
3723 */
3724
3725#define MAX_ENCR_KEY_LENGTH 16
3726#define MIC_KEY_LENGTH 8
3727
3728struct mwl8k_cmd_update_encryption {
3729 struct mwl8k_cmd_pkt header;
3730
3731 __le32 action;
3732 __le32 reserved;
3733 __u8 mac_addr[6];
3734 __u8 encr_type;
3735
3736} __attribute__((packed));
3737
3738struct mwl8k_cmd_set_key {
3739 struct mwl8k_cmd_pkt header;
3740
3741 __le32 action;
3742 __le32 reserved;
3743 __le16 length;
3744 __le16 key_type_id;
3745 __le32 key_info;
3746 __le32 key_id;
3747 __le16 key_len;
3748 __u8 key_material[MAX_ENCR_KEY_LENGTH];
3749 __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
3750 __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
3751 __le16 tkip_rsc_low;
3752 __le32 tkip_rsc_high;
3753 __le16 tkip_tsc_low;
3754 __le32 tkip_tsc_high;
3755 __u8 mac_addr[6];
3756} __attribute__((packed));
3757
3758enum {
3759 MWL8K_ENCR_ENABLE,
3760 MWL8K_ENCR_SET_KEY,
3761 MWL8K_ENCR_REMOVE_KEY,
3762 MWL8K_ENCR_SET_GROUP_KEY,
3763};
3764
3765#define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
3766#define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
3767#define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
3768#define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
3769#define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
3770
3771enum {
3772 MWL8K_ALG_WEP,
3773 MWL8K_ALG_TKIP,
3774 MWL8K_ALG_CCMP,
3775};
3776
3777#define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
3778#define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
3779#define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
3780#define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
3781#define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
3782
3783static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
3784 struct ieee80211_vif *vif,
3785 u8 *addr,
3786 u8 encr_type)
3787{
3788 struct mwl8k_cmd_update_encryption *cmd;
3789 int rc;
3790
3791 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3792 if (cmd == NULL)
3793 return -ENOMEM;
3794
3795 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
3796 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3797 cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
3798 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3799 cmd->encr_type = encr_type;
3800
3801 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3802 kfree(cmd);
3803
3804 return rc;
3805}
3806
3807static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
3808 u8 *addr,
3809 struct ieee80211_key_conf *key)
3810{
3811 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
3812 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3813 cmd->length = cpu_to_le16(sizeof(*cmd) -
3814 offsetof(struct mwl8k_cmd_set_key, length));
3815 cmd->key_id = cpu_to_le32(key->keyidx);
3816 cmd->key_len = cpu_to_le16(key->keylen);
3817 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3818
3819 switch (key->cipher) {
3820 case WLAN_CIPHER_SUITE_WEP40:
3821 case WLAN_CIPHER_SUITE_WEP104:
3822 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
3823 if (key->keyidx == 0)
3824 cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
3825
3826 break;
3827 case WLAN_CIPHER_SUITE_TKIP:
3828 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
3829 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3830 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
3831 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
3832 cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
3833 | MWL8K_KEY_FLAG_TSC_VALID);
3834 break;
3835 case WLAN_CIPHER_SUITE_CCMP:
3836 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
3837 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3838 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
3839 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
3840 break;
3841 default:
3842 return -ENOTSUPP;
3843 }
3844
3845 return 0;
3846}
3847
3848static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
3849 struct ieee80211_vif *vif,
3850 u8 *addr,
3851 struct ieee80211_key_conf *key)
3852{
3853 struct mwl8k_cmd_set_key *cmd;
3854 int rc;
3855 int keymlen;
3856 u32 action;
3857 u8 idx;
3858 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3859
3860 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3861 if (cmd == NULL)
3862 return -ENOMEM;
3863
3864 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
3865 if (rc < 0)
3866 goto done;
3867
3868 idx = key->keyidx;
3869
3870 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3871 action = MWL8K_ENCR_SET_KEY;
3872 else
3873 action = MWL8K_ENCR_SET_GROUP_KEY;
3874
3875 switch (key->cipher) {
3876 case WLAN_CIPHER_SUITE_WEP40:
3877 case WLAN_CIPHER_SUITE_WEP104:
3878 if (!mwl8k_vif->wep_key_conf[idx].enabled) {
3879 memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
3880 sizeof(*key) + key->keylen);
3881 mwl8k_vif->wep_key_conf[idx].enabled = 1;
3882 }
3883
3884 keymlen = 0;
3885 action = MWL8K_ENCR_SET_KEY;
3886 break;
3887 case WLAN_CIPHER_SUITE_TKIP:
3888 keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
3889 break;
3890 case WLAN_CIPHER_SUITE_CCMP:
3891 keymlen = key->keylen;
3892 break;
3893 default:
3894 rc = -ENOTSUPP;
3895 goto done;
3896 }
3897
3898 memcpy(cmd->key_material, key->key, keymlen);
3899 cmd->action = cpu_to_le32(action);
3900
3901 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3902done:
3903 kfree(cmd);
3904
3905 return rc;
3906}
3907
3908static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
3909 struct ieee80211_vif *vif,
3910 u8 *addr,
3911 struct ieee80211_key_conf *key)
3912{
3913 struct mwl8k_cmd_set_key *cmd;
3914 int rc;
3915 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3916
3917 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3918 if (cmd == NULL)
3919 return -ENOMEM;
3920
3921 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
3922 if (rc < 0)
3923 goto done;
3924
3925 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3926 WLAN_CIPHER_SUITE_WEP104)
3927 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
3928
3929 cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
3930
3931 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3932done:
3933 kfree(cmd);
3934
3935 return rc;
3936}
3937
3938static int mwl8k_set_key(struct ieee80211_hw *hw,
3939 enum set_key_cmd cmd_param,
3940 struct ieee80211_vif *vif,
3941 struct ieee80211_sta *sta,
3942 struct ieee80211_key_conf *key)
3943{
3944 int rc = 0;
3945 u8 encr_type;
3946 u8 *addr;
3947 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3948
3949 if (vif->type == NL80211_IFTYPE_STATION)
3950 return -EOPNOTSUPP;
3951
3952 if (sta == NULL)
3953 addr = hw->wiphy->perm_addr;
3954 else
3955 addr = sta->addr;
3956
3957 if (cmd_param == SET_KEY) {
3958 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3959 rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
3960 if (rc)
3961 goto out;
3962
3963 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
3964 || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
3965 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
3966 else
3967 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
3968
3969 rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
3970 encr_type);
3971 if (rc)
3972 goto out;
3973
3974 mwl8k_vif->is_hw_crypto_enabled = true;
3975
3976 } else {
3977 rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
3978
3979 if (rc)
3980 goto out;
3981
3982 mwl8k_vif->is_hw_crypto_enabled = false;
3983
3984 }
3985out:
3986 return rc;
3987}
3988
55489b6e
LB
3989/*
3990 * CMD_UPDATE_STADB.
3991 */
25d81b1e
LB
3992struct ewc_ht_info {
3993 __le16 control1;
3994 __le16 control2;
3995 __le16 control3;
ba2d3587 3996} __packed;
25d81b1e
LB
3997
3998struct peer_capability_info {
3999 /* Peer type - AP vs. STA. */
4000 __u8 peer_type;
4001
4002 /* Basic 802.11 capabilities from assoc resp. */
4003 __le16 basic_caps;
4004
4005 /* Set if peer supports 802.11n high throughput (HT). */
4006 __u8 ht_support;
4007
4008 /* Valid if HT is supported. */
4009 __le16 ht_caps;
4010 __u8 extended_ht_caps;
4011 struct ewc_ht_info ewc_info;
4012
4013 /* Legacy rate table. Intersection of our rates and peer rates. */
4014 __u8 legacy_rates[12];
4015
4016 /* HT rate table. Intersection of our rates and peer rates. */
4017 __u8 ht_rates[16];
4018 __u8 pad[16];
4019
4020 /* If set, interoperability mode, no proprietary extensions. */
4021 __u8 interop;
4022 __u8 pad2;
4023 __u8 station_id;
4024 __le16 amsdu_enabled;
ba2d3587 4025} __packed;
25d81b1e 4026
55489b6e
LB
4027struct mwl8k_cmd_update_stadb {
4028 struct mwl8k_cmd_pkt header;
4029
4030 /* See STADB_ACTION_TYPE */
4031 __le32 action;
4032
4033 /* Peer MAC address */
4034 __u8 peer_addr[ETH_ALEN];
4035
4036 __le32 reserved;
4037
4038 /* Peer info - valid during add/update. */
4039 struct peer_capability_info peer_info;
ba2d3587 4040} __packed;
55489b6e 4041
a680400e
LB
4042#define MWL8K_STA_DB_MODIFY_ENTRY 1
4043#define MWL8K_STA_DB_DEL_ENTRY 2
4044
4045/* Peer Entry flags - used to define the type of the peer node */
4046#define MWL8K_PEER_TYPE_ACCESSPOINT 2
4047
4048static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 4049 struct ieee80211_vif *vif,
13935e2c 4050 struct ieee80211_sta *sta)
55489b6e 4051{
55489b6e 4052 struct mwl8k_cmd_update_stadb *cmd;
a680400e 4053 struct peer_capability_info *p;
8707d026 4054 u32 rates;
55489b6e
LB
4055 int rc;
4056
4057 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4058 if (cmd == NULL)
4059 return -ENOMEM;
4060
4061 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4062 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 4063 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 4064 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 4065
a680400e
LB
4066 p = &cmd->peer_info;
4067 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
4068 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 4069 p->ht_support = sta->ht_cap.ht_supported;
b603742f 4070 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB
4071 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
4072 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB
4073 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4074 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4075 else
4076 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4077 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 4078 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB
4079 p->interop = 1;
4080 p->amsdu_enabled = 0;
4081
4082 rc = mwl8k_post_cmd(hw, &cmd->header);
4083 kfree(cmd);
4084
4085 return rc ? rc : p->station_id;
4086}
4087
4088static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
4089 struct ieee80211_vif *vif, u8 *addr)
4090{
4091 struct mwl8k_cmd_update_stadb *cmd;
4092 int rc;
4093
4094 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4095 if (cmd == NULL)
4096 return -ENOMEM;
4097
4098 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4099 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4100 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 4101 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 4102
a680400e 4103 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB
4104 kfree(cmd);
4105
4106 return rc;
4107}
4108
a66098da
LB
4109
4110/*
4111 * Interrupt handling.
4112 */
4113static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
4114{
4115 struct ieee80211_hw *hw = dev_id;
4116 struct mwl8k_priv *priv = hw->priv;
4117 u32 status;
4118
4119 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB
4120 if (!status)
4121 return IRQ_NONE;
4122
1e9f9de3
LB
4123 if (status & MWL8K_A2H_INT_TX_DONE) {
4124 status &= ~MWL8K_A2H_INT_TX_DONE;
4125 tasklet_schedule(&priv->poll_tx_task);
4126 }
4127
a66098da 4128 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB
4129 status &= ~MWL8K_A2H_INT_RX_READY;
4130 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB
4131 }
4132
3aefc37e
NS
4133 if (status & MWL8K_A2H_INT_BA_WATCHDOG) {
4134 status &= ~MWL8K_A2H_INT_BA_WATCHDOG;
4135 ieee80211_queue_work(hw, &priv->watchdog_ba_handle);
4136 }
4137
67e2eb27
LB
4138 if (status)
4139 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4140
a66098da 4141 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 4142 if (priv->hostcmd_wait != NULL)
a66098da 4143 complete(priv->hostcmd_wait);
a66098da
LB
4144 }
4145
4146 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 4147 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 4148 priv->radio_on && priv->pending_tx_pkts)
618952a7 4149 mwl8k_tx_start(priv);
a66098da
LB
4150 }
4151
4152 return IRQ_HANDLED;
4153}
4154
1e9f9de3
LB
4155static void mwl8k_tx_poll(unsigned long data)
4156{
4157 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4158 struct mwl8k_priv *priv = hw->priv;
4159 int limit;
4160 int i;
4161
4162 limit = 32;
4163
4164 spin_lock_bh(&priv->tx_lock);
4165
e600707b 4166 for (i = 0; i < mwl8k_tx_queues(priv); i++)
1e9f9de3
LB
4167 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
4168
4169 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
4170 complete(priv->tx_wait);
4171 priv->tx_wait = NULL;
4172 }
4173
4174 spin_unlock_bh(&priv->tx_lock);
4175
4176 if (limit) {
4177 writel(~MWL8K_A2H_INT_TX_DONE,
4178 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4179 } else {
4180 tasklet_schedule(&priv->poll_tx_task);
4181 }
4182}
4183
67e2eb27
LB
4184static void mwl8k_rx_poll(unsigned long data)
4185{
4186 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4187 struct mwl8k_priv *priv = hw->priv;
4188 int limit;
4189
4190 limit = 32;
4191 limit -= rxq_process(hw, 0, limit);
4192 limit -= rxq_refill(hw, 0, limit);
4193
4194 if (limit) {
4195 writel(~MWL8K_A2H_INT_RX_READY,
4196 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4197 } else {
4198 tasklet_schedule(&priv->poll_rx_task);
4199 }
4200}
4201
a66098da
LB
4202
4203/*
4204 * Core driver operations.
4205 */
7bb45683 4206static void mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
a66098da
LB
4207{
4208 struct mwl8k_priv *priv = hw->priv;
4209 int index = skb_get_queue_mapping(skb);
a66098da 4210
9189c100 4211 if (!priv->radio_on) {
c96c31e4
JP
4212 wiphy_debug(hw->wiphy,
4213 "dropped TX frame since radio disabled\n");
a66098da 4214 dev_kfree_skb(skb);
7bb45683 4215 return;
a66098da
LB
4216 }
4217
7bb45683 4218 mwl8k_txq_xmit(hw, index, skb);
a66098da
LB
4219}
4220
a66098da
LB
4221static int mwl8k_start(struct ieee80211_hw *hw)
4222{
a66098da
LB
4223 struct mwl8k_priv *priv = hw->priv;
4224 int rc;
4225
a0607fd3 4226 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB
4227 IRQF_SHARED, MWL8K_NAME, hw);
4228 if (rc) {
5db55844 4229 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 4230 return -EIO;
a66098da
LB
4231 }
4232
67e2eb27 4233 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 4234 tasklet_enable(&priv->poll_tx_task);
67e2eb27 4235 tasklet_enable(&priv->poll_rx_task);
2ec610cb 4236
a66098da 4237 /* Enable interrupts */
c23b5a69 4238 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 4239
2ec610cb
LB
4240 rc = mwl8k_fw_lock(hw);
4241 if (!rc) {
55489b6e 4242 rc = mwl8k_cmd_radio_enable(hw);
a66098da 4243
5e4cf166
LB
4244 if (!priv->ap_fw) {
4245 if (!rc)
55489b6e 4246 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 4247
5e4cf166
LB
4248 if (!rc)
4249 rc = mwl8k_cmd_set_pre_scan(hw);
4250
4251 if (!rc)
4252 rc = mwl8k_cmd_set_post_scan(hw,
4253 "\x00\x00\x00\x00\x00\x00");
4254 }
2ec610cb
LB
4255
4256 if (!rc)
55489b6e 4257 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 4258
2ec610cb 4259 if (!rc)
55489b6e 4260 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 4261
2ec610cb
LB
4262 mwl8k_fw_unlock(hw);
4263 }
4264
4265 if (rc) {
4266 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4267 free_irq(priv->pdev->irq, hw);
1e9f9de3 4268 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4269 tasklet_disable(&priv->poll_rx_task);
2ec610cb 4270 }
a66098da
LB
4271
4272 return rc;
4273}
4274
a66098da
LB
4275static void mwl8k_stop(struct ieee80211_hw *hw)
4276{
a66098da
LB
4277 struct mwl8k_priv *priv = hw->priv;
4278 int i;
4279
55489b6e 4280 mwl8k_cmd_radio_disable(hw);
a66098da
LB
4281
4282 ieee80211_stop_queues(hw);
4283
a66098da 4284 /* Disable interrupts */
a66098da 4285 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
4286 free_irq(priv->pdev->irq, hw);
4287
4288 /* Stop finalize join worker */
4289 cancel_work_sync(&priv->finalize_join_worker);
3aefc37e 4290 cancel_work_sync(&priv->watchdog_ba_handle);
a66098da
LB
4291 if (priv->beacon_skb != NULL)
4292 dev_kfree_skb(priv->beacon_skb);
4293
67e2eb27 4294 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 4295 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4296 tasklet_disable(&priv->poll_rx_task);
a66098da 4297
a66098da 4298 /* Return all skbs to mac80211 */
e600707b 4299 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 4300 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB
4301}
4302
0863ade8
BC
4303static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
4304
a66098da 4305static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 4306 struct ieee80211_vif *vif)
a66098da
LB
4307{
4308 struct mwl8k_priv *priv = hw->priv;
4309 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 4310 u32 macids_supported;
0863ade8
BC
4311 int macid, rc;
4312 struct mwl8k_device_info *di;
a66098da 4313
a43c49a8
LB
4314 /*
4315 * Reject interface creation if sniffer mode is active, as
4316 * STA operation is mutually exclusive with hardware sniffer
b64fe619 4317 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB
4318 */
4319 if (priv->sniffer_enabled) {
c96c31e4
JP
4320 wiphy_info(hw->wiphy,
4321 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB
4322 return -EINVAL;
4323 }
4324
0863ade8 4325 di = priv->device_info;
ee0ddf18
LB
4326 switch (vif->type) {
4327 case NL80211_IFTYPE_AP:
0863ade8
BC
4328 if (!priv->ap_fw && di->fw_image_ap) {
4329 /* we must load the ap fw to meet this request */
4330 if (!list_empty(&priv->vif_list))
4331 return -EBUSY;
4332 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4333 if (rc)
4334 return rc;
4335 }
ee0ddf18
LB
4336 macids_supported = priv->ap_macids_supported;
4337 break;
4338 case NL80211_IFTYPE_STATION:
0863ade8
BC
4339 if (priv->ap_fw && di->fw_image_sta) {
4340 /* we must load the sta fw to meet this request */
4341 if (!list_empty(&priv->vif_list))
4342 return -EBUSY;
4343 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
4344 if (rc)
4345 return rc;
4346 }
ee0ddf18
LB
4347 macids_supported = priv->sta_macids_supported;
4348 break;
4349 default:
4350 return -EINVAL;
4351 }
4352
4353 macid = ffs(macids_supported & ~priv->macids_used);
4354 if (!macid--)
4355 return -EBUSY;
4356
f5bb87cf 4357 /* Setup driver private area. */
1ed32e4f 4358 mwl8k_vif = MWL8K_VIF(vif);
a66098da 4359 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 4360 mwl8k_vif->vif = vif;
ee0ddf18 4361 mwl8k_vif->macid = macid;
a66098da 4362 mwl8k_vif->seqno = 0;
d9a07d49
NS
4363 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
4364 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 4365
aa21d0f6
LB
4366 /* Set the mac address. */
4367 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
4368
4369 if (priv->ap_fw)
4370 mwl8k_cmd_set_new_stn_add_self(hw, vif);
4371
ee0ddf18 4372 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 4373 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB
4374
4375 return 0;
4376}
4377
4378static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4379 struct ieee80211_vif *vif)
a66098da
LB
4380{
4381 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 4382 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 4383
b64fe619
LB
4384 if (priv->ap_fw)
4385 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
4386
aa21d0f6 4387 mwl8k_cmd_set_mac_addr(hw, vif, "\x00\x00\x00\x00\x00\x00");
32060e1b 4388
ee0ddf18 4389 priv->macids_used &= ~(1 << mwl8k_vif->macid);
f5bb87cf 4390 list_del(&mwl8k_vif->list);
a66098da
LB
4391}
4392
ee03a932 4393static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 4394{
a66098da
LB
4395 struct ieee80211_conf *conf = &hw->conf;
4396 struct mwl8k_priv *priv = hw->priv;
ee03a932 4397 int rc;
a66098da 4398
7595d67a 4399 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 4400 mwl8k_cmd_radio_disable(hw);
ee03a932 4401 return 0;
7595d67a
LB
4402 }
4403
ee03a932
LB
4404 rc = mwl8k_fw_lock(hw);
4405 if (rc)
4406 return rc;
a66098da 4407
55489b6e 4408 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB
4409 if (rc)
4410 goto out;
a66098da 4411
610677d2 4412 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB
4413 if (rc)
4414 goto out;
4415
a66098da
LB
4416 if (conf->power_level > 18)
4417 conf->power_level = 18;
a66098da 4418
08b06347 4419 if (priv->ap_fw) {
41fdf097
NS
4420 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
4421 if (rc)
4422 goto out;
4423
da62b761
NS
4424 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3);
4425 if (rc)
4426 wiphy_warn(hw->wiphy, "failed to set # of RX antennas");
4427 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
4428 if (rc)
4429 wiphy_warn(hw->wiphy, "failed to set # of TX antennas");
4430
08b06347 4431 } else {
41fdf097
NS
4432 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
4433 if (rc)
4434 goto out;
08b06347
LB
4435 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
4436 }
a66098da 4437
ee03a932
LB
4438out:
4439 mwl8k_fw_unlock(hw);
a66098da 4440
ee03a932 4441 return rc;
a66098da
LB
4442}
4443
b64fe619
LB
4444static void
4445mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4446 struct ieee80211_bss_conf *info, u32 changed)
a66098da 4447{
a66098da 4448 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 4449 u32 ap_legacy_rates;
13935e2c 4450 u8 ap_mcs_rates[16];
3a980d0a
LB
4451 int rc;
4452
c3cbbe8a 4453 if (mwl8k_fw_lock(hw))
3a980d0a 4454 return;
a66098da 4455
c3cbbe8a
LB
4456 /*
4457 * No need to capture a beacon if we're no longer associated.
4458 */
4459 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
4460 priv->capture_beacon = false;
3a980d0a 4461
c3cbbe8a 4462 /*
13935e2c 4463 * Get the AP's legacy and MCS rates.
c3cbbe8a 4464 */
7dc6a7a7 4465 if (vif->bss_conf.assoc) {
c6e96010 4466 struct ieee80211_sta *ap;
c97470dd 4467
c6e96010 4468 rcu_read_lock();
c6e96010 4469
c3cbbe8a
LB
4470 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
4471 if (ap == NULL) {
4472 rcu_read_unlock();
c6e96010 4473 goto out;
c3cbbe8a
LB
4474 }
4475
8707d026
LB
4476 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
4477 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
4478 } else {
4479 ap_legacy_rates =
4480 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4481 }
13935e2c 4482 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB
4483
4484 rcu_read_unlock();
4485 }
c6e96010 4486
c3cbbe8a 4487 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 4488 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB
4489 if (rc)
4490 goto out;
a66098da 4491
b71ed2c6 4492 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB
4493 if (rc)
4494 goto out;
c3cbbe8a 4495 }
a66098da 4496
c3cbbe8a 4497 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB
4498 rc = mwl8k_set_radio_preamble(hw,
4499 vif->bss_conf.use_short_preamble);
3a980d0a
LB
4500 if (rc)
4501 goto out;
c3cbbe8a 4502 }
a66098da 4503
c3cbbe8a 4504 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 4505 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB
4506 if (rc)
4507 goto out;
c3cbbe8a 4508 }
a66098da 4509
c97470dd
LB
4510 if (vif->bss_conf.assoc &&
4511 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
4512 BSS_CHANGED_HT))) {
c3cbbe8a 4513 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB
4514 if (rc)
4515 goto out;
c3cbbe8a 4516 }
a66098da 4517
c3cbbe8a
LB
4518 if (vif->bss_conf.assoc &&
4519 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB
4520 /*
4521 * Finalize the join. Tell rx handler to process
4522 * next beacon from our BSSID.
4523 */
0a11dfc3 4524 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 4525 priv->capture_beacon = true;
a66098da
LB
4526 }
4527
3a980d0a
LB
4528out:
4529 mwl8k_fw_unlock(hw);
a66098da
LB
4530}
4531
b64fe619
LB
4532static void
4533mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4534 struct ieee80211_bss_conf *info, u32 changed)
4535{
4536 int rc;
4537
4538 if (mwl8k_fw_lock(hw))
4539 return;
4540
4541 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4542 rc = mwl8k_set_radio_preamble(hw,
4543 vif->bss_conf.use_short_preamble);
4544 if (rc)
4545 goto out;
4546 }
4547
4548 if (changed & BSS_CHANGED_BASIC_RATES) {
4549 int idx;
4550 int rate;
4551
4552 /*
4553 * Use lowest supported basic rate for multicasts
4554 * and management frames (such as probe responses --
4555 * beacons will always go out at 1 Mb/s).
4556 */
4557 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB
4558 if (idx)
4559 idx--;
4560
4561 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4562 rate = mwl8k_rates_24[idx].hw_value;
4563 else
4564 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB
4565
4566 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
4567 }
4568
4569 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
4570 struct sk_buff *skb;
4571
4572 skb = ieee80211_beacon_get(hw, vif);
4573 if (skb != NULL) {
aa21d0f6 4574 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB
4575 kfree_skb(skb);
4576 }
4577 }
4578
4579 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 4580 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB
4581
4582out:
4583 mwl8k_fw_unlock(hw);
4584}
4585
4586static void
4587mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4588 struct ieee80211_bss_conf *info, u32 changed)
4589{
4590 struct mwl8k_priv *priv = hw->priv;
4591
4592 if (!priv->ap_fw)
4593 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
4594 else
4595 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
4596}
4597
e81cd2d6 4598static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 4599 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB
4600{
4601 struct mwl8k_cmd_pkt *cmd;
4602
447ced07
LB
4603 /*
4604 * Synthesize and return a command packet that programs the
4605 * hardware multicast address filter. At this point we don't
4606 * know whether FIF_ALLMULTI is being requested, but if it is,
4607 * we'll end up throwing this packet away and creating a new
4608 * one in mwl8k_configure_filter().
4609 */
22bedad3 4610 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB
4611
4612 return (unsigned long)cmd;
4613}
4614
a43c49a8
LB
4615static int
4616mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
4617 unsigned int changed_flags,
4618 unsigned int *total_flags)
4619{
4620 struct mwl8k_priv *priv = hw->priv;
4621
4622 /*
4623 * Hardware sniffer mode is mutually exclusive with STA
4624 * operation, so refuse to enable sniffer mode if a STA
4625 * interface is active.
4626 */
f5bb87cf 4627 if (!list_empty(&priv->vif_list)) {
a43c49a8 4628 if (net_ratelimit())
c96c31e4
JP
4629 wiphy_info(hw->wiphy,
4630 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB
4631 return 0;
4632 }
4633
4634 if (!priv->sniffer_enabled) {
55489b6e 4635 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB
4636 return 0;
4637 priv->sniffer_enabled = true;
4638 }
4639
4640 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
4641 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
4642 FIF_OTHER_BSS;
4643
4644 return 1;
4645}
4646
f5bb87cf
LB
4647static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
4648{
4649 if (!list_empty(&priv->vif_list))
4650 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
4651
4652 return NULL;
4653}
4654
e6935ea1
LB
4655static void mwl8k_configure_filter(struct ieee80211_hw *hw,
4656 unsigned int changed_flags,
4657 unsigned int *total_flags,
4658 u64 multicast)
4659{
4660 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB
4661 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
4662
c0adae2c
LB
4663 /*
4664 * AP firmware doesn't allow fine-grained control over
4665 * the receive filter.
4666 */
4667 if (priv->ap_fw) {
4668 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
4669 kfree(cmd);
4670 return;
4671 }
4672
a43c49a8
LB
4673 /*
4674 * Enable hardware sniffer mode if FIF_CONTROL or
4675 * FIF_OTHER_BSS is requested.
4676 */
4677 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
4678 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
4679 kfree(cmd);
4680 return;
4681 }
a66098da 4682
e6935ea1 4683 /* Clear unsupported feature flags */
447ced07 4684 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 4685
90852f7a
LB
4686 if (mwl8k_fw_lock(hw)) {
4687 kfree(cmd);
e6935ea1 4688 return;
90852f7a 4689 }
a66098da 4690
a43c49a8 4691 if (priv->sniffer_enabled) {
55489b6e 4692 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB
4693 priv->sniffer_enabled = false;
4694 }
4695
e6935ea1 4696 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB
4697 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
4698 /*
4699 * Disable the BSS filter.
4700 */
e6935ea1 4701 mwl8k_cmd_set_pre_scan(hw);
77165d88 4702 } else {
f5bb87cf 4703 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 4704 const u8 *bssid;
a94cc97e 4705
77165d88
LB
4706 /*
4707 * Enable the BSS filter.
4708 *
4709 * If there is an active STA interface, use that
4710 * interface's BSSID, otherwise use a dummy one
4711 * (where the OUI part needs to be nonzero for
4712 * the BSSID to be accepted by POST_SCAN).
4713 */
f5bb87cf
LB
4714 mwl8k_vif = mwl8k_first_vif(priv);
4715 if (mwl8k_vif != NULL)
4716 bssid = mwl8k_vif->vif->bss_conf.bssid;
4717 else
4718 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 4719
e6935ea1 4720 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB
4721 }
4722 }
4723
447ced07
LB
4724 /*
4725 * If FIF_ALLMULTI is being requested, throw away the command
4726 * packet that ->prepare_multicast() built and replace it with
4727 * a command packet that enables reception of all multicast
4728 * packets.
4729 */
4730 if (*total_flags & FIF_ALLMULTI) {
4731 kfree(cmd);
22bedad3 4732 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB
4733 }
4734
4735 if (cmd != NULL) {
4736 mwl8k_post_cmd(hw, cmd);
4737 kfree(cmd);
e6935ea1 4738 }
a66098da 4739
e6935ea1 4740 mwl8k_fw_unlock(hw);
a66098da
LB
4741}
4742
a66098da
LB
4743static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4744{
c2c2b12a 4745 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB
4746}
4747
4a6967b8
JB
4748static int mwl8k_sta_remove(struct ieee80211_hw *hw,
4749 struct ieee80211_vif *vif,
4750 struct ieee80211_sta *sta)
3f5610ff
LB
4751{
4752 struct mwl8k_priv *priv = hw->priv;
4753
4a6967b8
JB
4754 if (priv->ap_fw)
4755 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
4756 else
4757 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB
4758}
4759
4a6967b8
JB
4760static int mwl8k_sta_add(struct ieee80211_hw *hw,
4761 struct ieee80211_vif *vif,
4762 struct ieee80211_sta *sta)
bbfd9128
LB
4763{
4764 struct mwl8k_priv *priv = hw->priv;
4a6967b8 4765 int ret;
fcdc403c
NS
4766 int i;
4767 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4768 struct ieee80211_key_conf *key;
bbfd9128 4769
4a6967b8
JB
4770 if (!priv->ap_fw) {
4771 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
4772 if (ret >= 0) {
4773 MWL8K_STA(sta)->peer_id = ret;
17033543
NS
4774 if (sta->ht_cap.ht_supported)
4775 MWL8K_STA(sta)->is_ampdu_allowed = true;
fcdc403c 4776 ret = 0;
4a6967b8 4777 }
bbfd9128 4778
d9a07d49
NS
4779 } else {
4780 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128 4781 }
4a6967b8 4782
d9a07d49
NS
4783 for (i = 0; i < NUM_WEP_KEYS; i++) {
4784 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
4785 if (mwl8k_vif->wep_key_conf[i].enabled)
4786 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
4787 }
fcdc403c 4788 return ret;
bbfd9128
LB
4789}
4790
a66098da
LB
4791static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
4792 const struct ieee80211_tx_queue_params *params)
4793{
3e4f542c 4794 struct mwl8k_priv *priv = hw->priv;
a66098da 4795 int rc;
a66098da 4796
3e4f542c
LB
4797 rc = mwl8k_fw_lock(hw);
4798 if (!rc) {
e600707b 4799 BUG_ON(queue > MWL8K_TX_WMM_QUEUES - 1);
0863ade8
BC
4800 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
4801
3e4f542c 4802 if (!priv->wmm_enabled)
55489b6e 4803 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 4804
85c9205c 4805 if (!rc) {
e600707b 4806 int q = MWL8K_TX_WMM_QUEUES - 1 - queue;
85c9205c 4807 rc = mwl8k_cmd_set_edca_params(hw, q,
55489b6e
LB
4808 params->cw_min,
4809 params->cw_max,
4810 params->aifs,
4811 params->txop);
85c9205c 4812 }
3e4f542c
LB
4813
4814 mwl8k_fw_unlock(hw);
a66098da 4815 }
3e4f542c 4816
a66098da
LB
4817 return rc;
4818}
4819
a66098da
LB
4820static int mwl8k_get_stats(struct ieee80211_hw *hw,
4821 struct ieee80211_low_level_stats *stats)
4822{
55489b6e 4823 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB
4824}
4825
0d462bbb
JL
4826static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
4827 struct survey_info *survey)
4828{
4829 struct mwl8k_priv *priv = hw->priv;
4830 struct ieee80211_conf *conf = &hw->conf;
4831
4832 if (idx != 0)
4833 return -ENOENT;
4834
4835 survey->channel = conf->channel;
4836 survey->filled = SURVEY_INFO_NOISE_DBM;
4837 survey->noise = priv->noise;
4838
4839 return 0;
4840}
4841
65f3ddcd
NS
4842#define MAX_AMPDU_ATTEMPTS 5
4843
a2292d83
LB
4844static int
4845mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4846 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB
4847 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4848 u8 buf_size)
a2292d83 4849{
65f3ddcd
NS
4850
4851 int i, rc = 0;
4852 struct mwl8k_priv *priv = hw->priv;
4853 struct mwl8k_ampdu_stream *stream;
4854 u8 *addr = sta->addr;
4855
4856 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
4857 return -ENOTSUPP;
4858
4859 spin_lock(&priv->stream_lock);
4860 stream = mwl8k_lookup_stream(hw, addr, tid);
4861
a2292d83
LB
4862 switch (action) {
4863 case IEEE80211_AMPDU_RX_START:
4864 case IEEE80211_AMPDU_RX_STOP:
65f3ddcd
NS
4865 break;
4866 case IEEE80211_AMPDU_TX_START:
4867 /* By the time we get here the hw queues may contain outgoing
4868 * packets for this RA/TID that are not part of this BA
4869 * session. The hw will assign sequence numbers to these
4870 * packets as they go out. So if we query the hw for its next
4871 * sequence number and use that for the SSN here, it may end up
4872 * being wrong, which will lead to sequence number mismatch at
4873 * the recipient. To avoid this, we reset the sequence number
4874 * to O for the first MPDU in this BA stream.
4875 */
4876 *ssn = 0;
4877 if (stream == NULL) {
4878 /* This means that somebody outside this driver called
4879 * ieee80211_start_tx_ba_session. This is unexpected
4880 * because we do our own rate control. Just warn and
4881 * move on.
4882 */
4883 wiphy_warn(hw->wiphy, "Unexpected call to %s. "
4884 "Proceeding anyway.\n", __func__);
4885 stream = mwl8k_add_stream(hw, sta, tid);
4886 }
4887 if (stream == NULL) {
4888 wiphy_debug(hw->wiphy, "no free AMPDU streams\n");
4889 rc = -EBUSY;
4890 break;
4891 }
4892 stream->state = AMPDU_STREAM_IN_PROGRESS;
4893
4894 /* Release the lock before we do the time consuming stuff */
4895 spin_unlock(&priv->stream_lock);
4896 for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) {
4897 rc = mwl8k_check_ba(hw, stream);
4898
4899 if (!rc)
4900 break;
4901 /*
4902 * HW queues take time to be flushed, give them
4903 * sufficient time
4904 */
4905
4906 msleep(1000);
4907 }
4908 spin_lock(&priv->stream_lock);
4909 if (rc) {
4910 wiphy_err(hw->wiphy, "Stream for tid %d busy after %d"
4911 " attempts\n", tid, MAX_AMPDU_ATTEMPTS);
4912 mwl8k_remove_stream(hw, stream);
4913 rc = -EBUSY;
4914 break;
4915 }
4916 ieee80211_start_tx_ba_cb_irqsafe(vif, addr, tid);
4917 break;
4918 case IEEE80211_AMPDU_TX_STOP:
4919 if (stream == NULL)
4920 break;
4921 if (stream->state == AMPDU_STREAM_ACTIVE) {
4922 spin_unlock(&priv->stream_lock);
4923 mwl8k_destroy_ba(hw, stream);
4924 spin_lock(&priv->stream_lock);
4925 }
4926 mwl8k_remove_stream(hw, stream);
4927 ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
4928 break;
4929 case IEEE80211_AMPDU_TX_OPERATIONAL:
4930 BUG_ON(stream == NULL);
4931 BUG_ON(stream->state != AMPDU_STREAM_IN_PROGRESS);
4932 spin_unlock(&priv->stream_lock);
4933 rc = mwl8k_create_ba(hw, stream, buf_size);
4934 spin_lock(&priv->stream_lock);
4935 if (!rc)
4936 stream->state = AMPDU_STREAM_ACTIVE;
4937 else {
4938 spin_unlock(&priv->stream_lock);
4939 mwl8k_destroy_ba(hw, stream);
4940 spin_lock(&priv->stream_lock);
4941 wiphy_debug(hw->wiphy,
4942 "Failed adding stream for sta %pM tid %d\n",
4943 addr, tid);
4944 mwl8k_remove_stream(hw, stream);
4945 }
4946 break;
4947
a2292d83 4948 default:
65f3ddcd 4949 rc = -ENOTSUPP;
a2292d83 4950 }
65f3ddcd
NS
4951
4952 spin_unlock(&priv->stream_lock);
4953 return rc;
a2292d83
LB
4954}
4955
a66098da
LB
4956static const struct ieee80211_ops mwl8k_ops = {
4957 .tx = mwl8k_tx,
4958 .start = mwl8k_start,
4959 .stop = mwl8k_stop,
4960 .add_interface = mwl8k_add_interface,
4961 .remove_interface = mwl8k_remove_interface,
4962 .config = mwl8k_config,
a66098da 4963 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 4964 .prepare_multicast = mwl8k_prepare_multicast,
a66098da 4965 .configure_filter = mwl8k_configure_filter,
fcdc403c 4966 .set_key = mwl8k_set_key,
a66098da 4967 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB
4968 .sta_add = mwl8k_sta_add,
4969 .sta_remove = mwl8k_sta_remove,
a66098da 4970 .conf_tx = mwl8k_conf_tx,
a66098da 4971 .get_stats = mwl8k_get_stats,
0d462bbb 4972 .get_survey = mwl8k_get_survey,
a2292d83 4973 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB
4974};
4975
a66098da
LB
4976static void mwl8k_finalize_join_worker(struct work_struct *work)
4977{
4978 struct mwl8k_priv *priv =
4979 container_of(work, struct mwl8k_priv, finalize_join_worker);
4980 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB
4981 struct ieee80211_mgmt *mgmt = (void *)skb->data;
4982 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
4983 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
4984 mgmt->u.beacon.variable, len);
4985 int dtim_period = 1;
4986
4987 if (tim && tim[1] >= 2)
4988 dtim_period = tim[3];
a66098da 4989
56007a02 4990 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 4991
f5bb87cf 4992 dev_kfree_skb(skb);
a66098da
LB
4993 priv->beacon_skb = NULL;
4994}
4995
bcb628d5 4996enum {
9e1b17ea
LB
4997 MWL8363 = 0,
4998 MWL8687,
bcb628d5 4999 MWL8366,
6f6d1e9a
LB
5000};
5001
8a7a578c 5002#define MWL8K_8366_AP_FW_API 2
952a0e96
BC
5003#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
5004#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
5005
bcb628d5 5006static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB
5007 [MWL8363] = {
5008 .part_name = "88w8363",
5009 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 5010 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 5011 },
49eb691c 5012 [MWL8687] = {
bcb628d5
JL
5013 .part_name = "88w8687",
5014 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 5015 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 5016 },
49eb691c 5017 [MWL8366] = {
bcb628d5
JL
5018 .part_name = "88w8366",
5019 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 5020 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC
5021 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
5022 .fw_api_ap = MWL8K_8366_AP_FW_API,
89a91f4f 5023 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 5024 },
45a390dd
LB
5025};
5026
c92d4ede
LB
5027MODULE_FIRMWARE("mwl8k/helper_8363.fw");
5028MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
5029MODULE_FIRMWARE("mwl8k/helper_8687.fw");
5030MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
5031MODULE_FIRMWARE("mwl8k/helper_8366.fw");
5032MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 5033MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 5034
45a390dd 5035static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 5036 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB
5037 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5038 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL
5039 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5040 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5041 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 5042 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 5043 { },
45a390dd
LB
5044};
5045MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
5046
99020471
BC
5047static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
5048{
5049 int rc;
5050 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
5051 "Trying alternative firmware %s\n", pci_name(priv->pdev),
5052 priv->fw_pref, priv->fw_alt);
5053 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
5054 if (rc) {
5055 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5056 pci_name(priv->pdev), priv->fw_alt);
5057 return rc;
5058 }
5059 return 0;
5060}
5061
5062static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
5063static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
5064{
5065 struct mwl8k_priv *priv = context;
5066 struct mwl8k_device_info *di = priv->device_info;
5067 int rc;
5068
5069 switch (priv->fw_state) {
5070 case FW_STATE_INIT:
5071 if (!fw) {
5072 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
5073 pci_name(priv->pdev), di->helper_image);
5074 goto fail;
5075 }
5076 priv->fw_helper = fw;
5077 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
5078 true);
5079 if (rc && priv->fw_alt) {
5080 rc = mwl8k_request_alt_fw(priv);
5081 if (rc)
5082 goto fail;
5083 priv->fw_state = FW_STATE_LOADING_ALT;
5084 } else if (rc)
5085 goto fail;
5086 else
5087 priv->fw_state = FW_STATE_LOADING_PREF;
5088 break;
5089
5090 case FW_STATE_LOADING_PREF:
5091 if (!fw) {
5092 if (priv->fw_alt) {
5093 rc = mwl8k_request_alt_fw(priv);
5094 if (rc)
5095 goto fail;
5096 priv->fw_state = FW_STATE_LOADING_ALT;
5097 } else
5098 goto fail;
5099 } else {
5100 priv->fw_ucode = fw;
5101 rc = mwl8k_firmware_load_success(priv);
5102 if (rc)
5103 goto fail;
5104 else
5105 complete(&priv->firmware_loading_complete);
5106 }
5107 break;
5108
5109 case FW_STATE_LOADING_ALT:
5110 if (!fw) {
5111 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5112 pci_name(priv->pdev), di->helper_image);
5113 goto fail;
5114 }
5115 priv->fw_ucode = fw;
5116 rc = mwl8k_firmware_load_success(priv);
5117 if (rc)
5118 goto fail;
5119 else
5120 complete(&priv->firmware_loading_complete);
5121 break;
5122
5123 default:
5124 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
5125 MWL8K_NAME, priv->fw_state);
5126 BUG_ON(1);
5127 }
5128
5129 return;
5130
5131fail:
5132 priv->fw_state = FW_STATE_ERROR;
5133 complete(&priv->firmware_loading_complete);
5134 device_release_driver(&priv->pdev->dev);
5135 mwl8k_release_firmware(priv);
5136}
5137
5138static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
5139 bool nowait)
a66098da 5140{
3cc7772c 5141 struct mwl8k_priv *priv = hw->priv;
a66098da 5142 int rc;
be695fc4
LB
5143
5144 /* Reset firmware and hardware */
5145 mwl8k_hw_reset(priv);
5146
5147 /* Ask userland hotplug daemon for the device firmware */
99020471 5148 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 5149 if (rc) {
5db55844 5150 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 5151 return rc;
be695fc4
LB
5152 }
5153
99020471
BC
5154 if (nowait)
5155 return rc;
5156
be695fc4
LB
5157 /* Load firmware into hardware */
5158 rc = mwl8k_load_firmware(hw);
3cc7772c 5159 if (rc)
5db55844 5160 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB
5161
5162 /* Reclaim memory once firmware is successfully loaded */
5163 mwl8k_release_firmware(priv);
5164
3cc7772c
BC
5165 return rc;
5166}
5167
73b46320
BC
5168static int mwl8k_init_txqs(struct ieee80211_hw *hw)
5169{
5170 struct mwl8k_priv *priv = hw->priv;
5171 int rc = 0;
5172 int i;
5173
e600707b 5174 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
73b46320
BC
5175 rc = mwl8k_txq_init(hw, i);
5176 if (rc)
5177 break;
5178 if (priv->ap_fw)
5179 iowrite32(priv->txq[i].txd_dma,
5180 priv->sram + priv->txq_offset[i]);
5181 }
5182 return rc;
5183}
5184
3cc7772c
BC
5185/* initialize hw after successfully loading a firmware image */
5186static int mwl8k_probe_hw(struct ieee80211_hw *hw)
5187{
5188 struct mwl8k_priv *priv = hw->priv;
5189 int rc = 0;
5190 int i;
be695fc4 5191
91942230 5192 if (priv->ap_fw) {
89a91f4f 5193 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 5194 if (priv->rxd_ops == NULL) {
c96c31e4
JP
5195 wiphy_err(hw->wiphy,
5196 "Driver does not have AP firmware image support for this hardware\n");
91942230
LB
5197 goto err_stop_firmware;
5198 }
5199 } else {
89a91f4f 5200 priv->rxd_ops = &rxd_sta_ops;
91942230 5201 }
be695fc4
LB
5202
5203 priv->sniffer_enabled = false;
5204 priv->wmm_enabled = false;
5205 priv->pending_tx_pkts = 0;
5206
a66098da
LB
5207 rc = mwl8k_rxq_init(hw, 0);
5208 if (rc)
3cc7772c 5209 goto err_stop_firmware;
a66098da
LB
5210 rxq_refill(hw, 0, INT_MAX);
5211
73b46320
BC
5212 /* For the sta firmware, we need to know the dma addresses of tx queues
5213 * before sending MWL8K_CMD_GET_HW_SPEC. So we must initialize them
5214 * prior to issuing this command. But for the AP case, we learn the
5215 * total number of queues from the result CMD_GET_HW_SPEC, so for this
5216 * case we must initialize the tx queues after.
5217 */
8a7a578c 5218 priv->num_ampdu_queues = 0;
73b46320
BC
5219 if (!priv->ap_fw) {
5220 rc = mwl8k_init_txqs(hw);
a66098da
LB
5221 if (rc)
5222 goto err_free_queues;
5223 }
5224
5225 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 5226 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3aefc37e
NS
5227 iowrite32(MWL8K_A2H_INT_TX_DONE|MWL8K_A2H_INT_RX_READY|
5228 MWL8K_A2H_INT_BA_WATCHDOG,
1e9f9de3 5229 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB
5230 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
5231
a0607fd3 5232 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB
5233 IRQF_SHARED, MWL8K_NAME, hw);
5234 if (rc) {
5db55844 5235 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB
5236 goto err_free_queues;
5237 }
5238
ac109fd0
BC
5239 memset(priv->ampdu, 0, sizeof(priv->ampdu));
5240
a66098da
LB
5241 /*
5242 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 5243 * commands use interrupts and avoid polling. Disable
a66098da
LB
5244 * interrupts when done.
5245 */
c23b5a69 5246 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
5247
5248 /* Get config data, mac addrs etc */
42fba21d
LB
5249 if (priv->ap_fw) {
5250 rc = mwl8k_cmd_get_hw_spec_ap(hw);
73b46320
BC
5251 if (!rc)
5252 rc = mwl8k_init_txqs(hw);
42fba21d
LB
5253 if (!rc)
5254 rc = mwl8k_cmd_set_hw_spec(hw);
5255 } else {
5256 rc = mwl8k_cmd_get_hw_spec_sta(hw);
5257 }
a66098da 5258 if (rc) {
5db55844 5259 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 5260 goto err_free_irq;
a66098da
LB
5261 }
5262
5263 /* Turn radio off */
55489b6e 5264 rc = mwl8k_cmd_radio_disable(hw);
a66098da 5265 if (rc) {
5db55844 5266 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 5267 goto err_free_irq;
a66098da
LB
5268 }
5269
32060e1b 5270 /* Clear MAC address */
aa21d0f6 5271 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 5272 if (rc) {
5db55844 5273 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 5274 goto err_free_irq;
32060e1b
LB
5275 }
5276
a66098da 5277 /* Disable interrupts */
a66098da 5278 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
5279 free_irq(priv->pdev->irq, hw);
5280
c96c31e4
JP
5281 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
5282 priv->device_info->part_name,
5283 priv->hw_rev, hw->wiphy->perm_addr,
5284 priv->ap_fw ? "AP" : "STA",
5285 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
5286 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB
5287
5288 return 0;
5289
a66098da 5290err_free_irq:
a66098da 5291 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
5292 free_irq(priv->pdev->irq, hw);
5293
5294err_free_queues:
e600707b 5295 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB
5296 mwl8k_txq_deinit(hw, i);
5297 mwl8k_rxq_deinit(hw, 0);
5298
3cc7772c
BC
5299err_stop_firmware:
5300 mwl8k_hw_reset(priv);
5301
5302 return rc;
5303}
5304
5305/*
5306 * invoke mwl8k_reload_firmware to change the firmware image after the device
5307 * has already been registered
5308 */
5309static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
5310{
5311 int i, rc = 0;
5312 struct mwl8k_priv *priv = hw->priv;
5313
5314 mwl8k_stop(hw);
5315 mwl8k_rxq_deinit(hw, 0);
5316
e600707b 5317 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC
5318 mwl8k_txq_deinit(hw, i);
5319
99020471 5320 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC
5321 if (rc)
5322 goto fail;
5323
5324 rc = mwl8k_probe_hw(hw);
5325 if (rc)
5326 goto fail;
5327
5328 rc = mwl8k_start(hw);
5329 if (rc)
5330 goto fail;
5331
5332 rc = mwl8k_config(hw, ~0);
5333 if (rc)
5334 goto fail;
5335
e600707b 5336 for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) {
3cc7772c
BC
5337 rc = mwl8k_conf_tx(hw, i, &priv->wmm_params[i]);
5338 if (rc)
5339 goto fail;
5340 }
5341
5342 return rc;
5343
5344fail:
5345 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
5346 return rc;
5347}
5348
5349static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
5350{
5351 struct ieee80211_hw *hw = priv->hw;
5352 int i, rc;
5353
99020471
BC
5354 rc = mwl8k_load_firmware(hw);
5355 mwl8k_release_firmware(priv);
5356 if (rc) {
5357 wiphy_err(hw->wiphy, "Cannot start firmware\n");
5358 return rc;
5359 }
5360
3cc7772c
BC
5361 /*
5362 * Extra headroom is the size of the required DMA header
5363 * minus the size of the smallest 802.11 frame (CTS frame).
5364 */
5365 hw->extra_tx_headroom =
5366 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
5367
5368 hw->channel_change_time = 10;
5369
e600707b 5370 hw->queues = MWL8K_TX_WMM_QUEUES;
3cc7772c
BC
5371
5372 /* Set rssi values to dBm */
0bf22c37 5373 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL;
3cc7772c
BC
5374 hw->vif_data_size = sizeof(struct mwl8k_vif);
5375 hw->sta_data_size = sizeof(struct mwl8k_sta);
5376
5377 priv->macids_used = 0;
5378 INIT_LIST_HEAD(&priv->vif_list);
5379
5380 /* Set default radio state and preamble */
5381 priv->radio_on = 0;
5382 priv->radio_short_preamble = 0;
5383
5384 /* Finalize join worker */
5385 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3aefc37e
NS
5386 /* Handle watchdog ba events */
5387 INIT_WORK(&priv->watchdog_ba_handle, mwl8k_watchdog_ba_events);
3cc7772c
BC
5388
5389 /* TX reclaim and RX tasklets. */
5390 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
5391 tasklet_disable(&priv->poll_tx_task);
5392 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
5393 tasklet_disable(&priv->poll_rx_task);
5394
5395 /* Power management cookie */
5396 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
5397 if (priv->cookie == NULL)
5398 return -ENOMEM;
5399
5400 mutex_init(&priv->fw_mutex);
5401 priv->fw_mutex_owner = NULL;
5402 priv->fw_mutex_depth = 0;
5403 priv->hostcmd_wait = NULL;
5404
5405 spin_lock_init(&priv->tx_lock);
5406
ac109fd0
BC
5407 spin_lock_init(&priv->stream_lock);
5408
3cc7772c
BC
5409 priv->tx_wait = NULL;
5410
5411 rc = mwl8k_probe_hw(hw);
5412 if (rc)
5413 goto err_free_cookie;
5414
5415 hw->wiphy->interface_modes = 0;
5416 if (priv->ap_macids_supported || priv->device_info->fw_image_ap)
5417 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
5418 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
5419 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5420
5421 rc = ieee80211_register_hw(hw);
5422 if (rc) {
5423 wiphy_err(hw->wiphy, "Cannot register device\n");
5424 goto err_unprobe_hw;
5425 }
5426
5427 return 0;
5428
5429err_unprobe_hw:
e600707b 5430 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC
5431 mwl8k_txq_deinit(hw, i);
5432 mwl8k_rxq_deinit(hw, 0);
5433
be695fc4 5434err_free_cookie:
a66098da
LB
5435 if (priv->cookie != NULL)
5436 pci_free_consistent(priv->pdev, 4,
5437 priv->cookie, priv->cookie_dma);
5438
3cc7772c
BC
5439 return rc;
5440}
5441static int __devinit mwl8k_probe(struct pci_dev *pdev,
5442 const struct pci_device_id *id)
5443{
5444 static int printed_version;
5445 struct ieee80211_hw *hw;
5446 struct mwl8k_priv *priv;
0863ade8 5447 struct mwl8k_device_info *di;
3cc7772c
BC
5448 int rc;
5449
5450 if (!printed_version) {
5451 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
5452 printed_version = 1;
5453 }
5454
5455
5456 rc = pci_enable_device(pdev);
5457 if (rc) {
5458 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
5459 MWL8K_NAME);
5460 return rc;
5461 }
5462
5463 rc = pci_request_regions(pdev, MWL8K_NAME);
5464 if (rc) {
5465 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
5466 MWL8K_NAME);
5467 goto err_disable_device;
5468 }
5469
5470 pci_set_master(pdev);
5471
5472
5473 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
5474 if (hw == NULL) {
5475 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
5476 rc = -ENOMEM;
5477 goto err_free_reg;
5478 }
5479
5480 SET_IEEE80211_DEV(hw, &pdev->dev);
5481 pci_set_drvdata(pdev, hw);
5482
5483 priv = hw->priv;
5484 priv->hw = hw;
5485 priv->pdev = pdev;
5486 priv->device_info = &mwl8k_info_tbl[id->driver_data];
5487
5488
5489 priv->sram = pci_iomap(pdev, 0, 0x10000);
5490 if (priv->sram == NULL) {
5491 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
5492 goto err_iounmap;
5493 }
5494
5495 /*
5496 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
5497 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
5498 */
5499 priv->regs = pci_iomap(pdev, 1, 0x10000);
5500 if (priv->regs == NULL) {
5501 priv->regs = pci_iomap(pdev, 2, 0x10000);
5502 if (priv->regs == NULL) {
5503 wiphy_err(hw->wiphy, "Cannot map device registers\n");
5504 goto err_iounmap;
5505 }
5506 }
5507
0863ade8 5508 /*
99020471
BC
5509 * Choose the initial fw image depending on user input. If a second
5510 * image is available, make it the alternative image that will be
5511 * loaded if the first one fails.
0863ade8 5512 */
99020471 5513 init_completion(&priv->firmware_loading_complete);
0863ade8 5514 di = priv->device_info;
99020471
BC
5515 if (ap_mode_default && di->fw_image_ap) {
5516 priv->fw_pref = di->fw_image_ap;
5517 priv->fw_alt = di->fw_image_sta;
5518 } else if (!ap_mode_default && di->fw_image_sta) {
5519 priv->fw_pref = di->fw_image_sta;
5520 priv->fw_alt = di->fw_image_ap;
5521 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 5522 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 5523 priv->fw_pref = di->fw_image_sta;
0863ade8
BC
5524 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
5525 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC
5526 priv->fw_pref = di->fw_image_ap;
5527 }
5528 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC
5529 if (rc)
5530 goto err_stop_firmware;
99020471 5531 return rc;
3cc7772c 5532
be695fc4
LB
5533err_stop_firmware:
5534 mwl8k_hw_reset(priv);
be695fc4
LB
5535
5536err_iounmap:
a66098da
LB
5537 if (priv->regs != NULL)
5538 pci_iounmap(pdev, priv->regs);
5539
5b9482dd
LB
5540 if (priv->sram != NULL)
5541 pci_iounmap(pdev, priv->sram);
5542
a66098da
LB
5543 pci_set_drvdata(pdev, NULL);
5544 ieee80211_free_hw(hw);
5545
5546err_free_reg:
5547 pci_release_regions(pdev);
3db95e50
LB
5548
5549err_disable_device:
a66098da
LB
5550 pci_disable_device(pdev);
5551
5552 return rc;
5553}
5554
230f7af0 5555static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB
5556{
5557 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
5558}
5559
230f7af0 5560static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB
5561{
5562 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
5563 struct mwl8k_priv *priv;
5564 int i;
5565
5566 if (hw == NULL)
5567 return;
5568 priv = hw->priv;
5569
99020471
BC
5570 wait_for_completion(&priv->firmware_loading_complete);
5571
5572 if (priv->fw_state == FW_STATE_ERROR) {
5573 mwl8k_hw_reset(priv);
5574 goto unmap;
5575 }
5576
a66098da
LB
5577 ieee80211_stop_queues(hw);
5578
60aa569f
LB
5579 ieee80211_unregister_hw(hw);
5580
67e2eb27 5581 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 5582 tasklet_kill(&priv->poll_tx_task);
67e2eb27 5583 tasklet_kill(&priv->poll_rx_task);
a66098da 5584
a66098da
LB
5585 /* Stop hardware */
5586 mwl8k_hw_reset(priv);
5587
5588 /* Return all skbs to mac80211 */
e600707b 5589 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 5590 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 5591
e600707b 5592 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB
5593 mwl8k_txq_deinit(hw, i);
5594
5595 mwl8k_rxq_deinit(hw, 0);
5596
c2c357ce 5597 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 5598
99020471 5599unmap:
a66098da 5600 pci_iounmap(pdev, priv->regs);
5b9482dd 5601 pci_iounmap(pdev, priv->sram);
a66098da
LB
5602 pci_set_drvdata(pdev, NULL);
5603 ieee80211_free_hw(hw);
5604 pci_release_regions(pdev);
5605 pci_disable_device(pdev);
5606}
5607
5608static struct pci_driver mwl8k_driver = {
5609 .name = MWL8K_NAME,
45a390dd 5610 .id_table = mwl8k_pci_id_table,
a66098da
LB
5611 .probe = mwl8k_probe,
5612 .remove = __devexit_p(mwl8k_remove),
5613 .shutdown = __devexit_p(mwl8k_shutdown),
5614};
5615
5616static int __init mwl8k_init(void)
5617{
5618 return pci_register_driver(&mwl8k_driver);
5619}
5620
5621static void __exit mwl8k_exit(void)
5622{
5623 pci_unregister_driver(&mwl8k_driver);
5624}
5625
5626module_init(mwl8k_init);
5627module_exit(mwl8k_exit);
c2c357ce
LB
5628
5629MODULE_DESCRIPTION(MWL8K_DESC);
5630MODULE_VERSION(MWL8K_VERSION);
5631MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
5632MODULE_LICENSE("GPL");
This page took 0.635407 seconds and 5 git commands to generate.