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mwl8k: Do not stop tx queues
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
5a0e3ad6 22#include <linux/slab.h>
a66098da
LB		 23#include <net/mac80211.h>
24#include <linux/moduleparam.h>
25#include <linux/firmware.h>
26#include <linux/workqueue.h>
27
28#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29#define MWL8K_NAME KBUILD_MODNAME
a5fb297d 30#define MWL8K_VERSION "0.12"
a66098da 31
0863ade8
BC		 32/* Module parameters */
33static unsigned ap_mode_default;
34module_param(ap_mode_default, bool, 0);
35MODULE_PARM_DESC(ap_mode_default,
36 "Set to 1 to make ap mode the default instead of sta mode");
37
a66098da
LB		 38/* Register definitions */
39#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 40#define MWL8K_MODE_STA 0x0000005a
41#define MWL8K_MODE_AP 0x000000a5
a66098da 42#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 43#define MWL8K_FWSTA_READY 0xf0f1f2f4
44#define MWL8K_FWAP_READY 0xf1f2f4a5
45#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 46#define MWL8K_HIU_SCRATCH 0x00000c40
47
48/* Host->device communications */
49#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
50#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
51#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
52#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
53#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 54#define MWL8K_H2A_INT_DUMMY (1 << 20)
55#define MWL8K_H2A_INT_RESET (1 << 15)
56#define MWL8K_H2A_INT_DOORBELL (1 << 1)
57#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 58
59/* Device->host communications */
60#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
61#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
62#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
63#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
64#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b 65#define MWL8K_A2H_INT_DUMMY (1 << 20)
3aefc37e 66#define MWL8K_A2H_INT_BA_WATCHDOG (1 << 14)
ce9e2e1b
LB		 67#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
68#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
69#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
70#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
71#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
72#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
73#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
74#define MWL8K_A2H_INT_RX_READY (1 << 1)
75#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 76
77#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
78 MWL8K_A2H_INT_CHNL_SWITCHED | \
79 MWL8K_A2H_INT_QUEUE_EMPTY | \
80 MWL8K_A2H_INT_RADAR_DETECT | \
81 MWL8K_A2H_INT_RADIO_ON | \
82 MWL8K_A2H_INT_RADIO_OFF | \
83 MWL8K_A2H_INT_MAC_EVENT | \
84 MWL8K_A2H_INT_OPC_DONE | \
85 MWL8K_A2H_INT_RX_READY | \
3aefc37e
NS		 86 MWL8K_A2H_INT_TX_DONE | \
87 MWL8K_A2H_INT_BA_WATCHDOG)
a66098da 88
a66098da 89#define MWL8K_RX_QUEUES 1
e600707b 90#define MWL8K_TX_WMM_QUEUES 4
8a7a578c 91#define MWL8K_MAX_AMPDU_QUEUES 8
e600707b
BC		 92#define MWL8K_MAX_TX_QUEUES (MWL8K_TX_WMM_QUEUES + MWL8K_MAX_AMPDU_QUEUES)
93#define mwl8k_tx_queues(priv) (MWL8K_TX_WMM_QUEUES + (priv)->num_ampdu_queues)
a66098da 94
54bc3a0d
LB		 95struct rxd_ops {
96 int rxd_size;
97 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
98 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 99 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 100 __le16 *qos, s8 *noise);
54bc3a0d
LB		 101};
102
45a390dd 103struct mwl8k_device_info {
a74b295e
LB		 104 char *part_name;
105 char *helper_image;
0863ade8
BC		 106 char *fw_image_sta;
107 char *fw_image_ap;
89a91f4f 108 struct rxd_ops *ap_rxd_ops;
952a0e96 109 u32 fw_api_ap;
45a390dd
LB		 110};
111
a66098da 112struct mwl8k_rx_queue {
45eb400d 113 int rxd_count;
a66098da
LB		 114
115 /* hw receives here */
45eb400d 116 int head;
a66098da
LB		 117
118 /* refill descs here */
45eb400d 119 int tail;
a66098da 120
54bc3a0d 121 void *rxd;
45eb400d 122 dma_addr_t rxd_dma;
788838eb
LB		 123 struct {
124 struct sk_buff *skb;
53b1b3e1 125 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 126 } *buf;
a66098da
LB		 127};
128
a66098da
LB		 129struct mwl8k_tx_queue {
130 /* hw transmits here */
45eb400d 131 int head;
a66098da
LB		 132
133 /* sw appends here */
45eb400d 134 int tail;
a66098da 135
8ccbc3b8 136 unsigned int len;
45eb400d
LB		 137 struct mwl8k_tx_desc *txd;
138 dma_addr_t txd_dma;
139 struct sk_buff **skb;
a66098da
LB		 140};
141
ac109fd0
BC		 142enum {
143 AMPDU_NO_STREAM,
144 AMPDU_STREAM_NEW,
145 AMPDU_STREAM_IN_PROGRESS,
146 AMPDU_STREAM_ACTIVE,
147};
148
5faa1aff
NS		 149struct mwl8k_ampdu_stream {
150 struct ieee80211_sta *sta;
151 u8 tid;
152 u8 state;
153 u8 idx;
154 u8 txq_idx; /* index of this stream in priv->txq */
155};
156
a66098da 157struct mwl8k_priv {
a66098da 158 struct ieee80211_hw *hw;
a66098da 159 struct pci_dev *pdev;
bf3ca7f7 160 int irq;
a66098da 161
45a390dd
LB		 162 struct mwl8k_device_info *device_info;
163
be695fc4
LB		 164 void __iomem *sram;
165 void __iomem *regs;
166
167 /* firmware */
d1f9e41d
BC		 168 const struct firmware *fw_helper;
169 const struct firmware *fw_ucode;
a66098da 170
be695fc4
LB		 171 /* hardware/firmware parameters */
172 bool ap_fw;
173 struct rxd_ops *rxd_ops;
777ad375
LB		 174 struct ieee80211_supported_band band_24;
175 struct ieee80211_channel channels_24[14];
176 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 177 struct ieee80211_supported_band band_50;
178 struct ieee80211_channel channels_50[4];
179 struct ieee80211_rate rates_50[9];
ee0ddf18
LB		 180 u32 ap_macids_supported;
181 u32 sta_macids_supported;
be695fc4 182
8a7a578c
BC		 183 /* Ampdu stream information */
184 u8 num_ampdu_queues;
ac109fd0
BC		 185 spinlock_t stream_lock;
186 struct mwl8k_ampdu_stream ampdu[MWL8K_MAX_AMPDU_QUEUES];
3aefc37e 187 struct work_struct watchdog_ba_handle;
8a7a578c 188
618952a7
LB		 189 /* firmware access */
190 struct mutex fw_mutex;
191 struct task_struct *fw_mutex_owner;
192 int fw_mutex_depth;
618952a7
LB		 193 struct completion *hostcmd_wait;
194
a66098da
LB		 195 /* lock held over TX and TX reap */
196 spinlock_t tx_lock;
a66098da 197
88de754a
LB		 198 /* TX quiesce completion, protected by fw_mutex and tx_lock */
199 struct completion *tx_wait;
200
f5bb87cf 201 /* List of interfaces. */
ee0ddf18 202 u32 macids_used;
f5bb87cf 203 struct list_head vif_list;
a66098da 204
a66098da
LB		 205 /* power management status cookie from firmware */
206 u32 *cookie;
207 dma_addr_t cookie_dma;
208
209 u16 num_mcaddrs;
a66098da 210 u8 hw_rev;
2aa7b01f 211 u32 fw_rev;
a66098da
LB		 212
213 /*
214 * Running count of TX packets in flight, to avoid
215 * iterating over the transmit rings each time.
216 */
217 int pending_tx_pkts;
218
219 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
e600707b
BC		 220 struct mwl8k_tx_queue txq[MWL8K_MAX_TX_QUEUES];
221 u32 txq_offset[MWL8K_MAX_TX_QUEUES];
a66098da 222
c46563b7 223 bool radio_on;
68ce3884 224 bool radio_short_preamble;
a43c49a8 225 bool sniffer_enabled;
0439b1f5 226 bool wmm_enabled;
a66098da 227
a66098da
LB		 228 /* XXX need to convert this to handle multiple interfaces */
229 bool capture_beacon;
d89173f2 230 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 231 struct sk_buff *beacon_skb;
232
233 /*
234 * This FJ worker has to be global as it is scheduled from the
235 * RX handler. At this point we don't know which interface it
236 * belongs to until the list of bssids waiting to complete join
237 * is checked.
238 */
239 struct work_struct finalize_join_worker;
240
1e9f9de3
LB		 241 /* Tasklet to perform TX reclaim. */
242 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 243
244 /* Tasklet to perform RX. */
245 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 246
247 /* Most recently reported noise in dBm */
248 s8 noise;
0863ade8
BC		 249
250 /*
251 * preserve the queue configurations so they can be restored if/when
252 * the firmware image is swapped.
253 */
e600707b 254 struct ieee80211_tx_queue_params wmm_params[MWL8K_TX_WMM_QUEUES];
99020471
BC		 255
256 /* async firmware loading state */
257 unsigned fw_state;
258 char *fw_pref;
259 char *fw_alt;
260 struct completion firmware_loading_complete;
a66098da
LB		 261};
262
e53d9b96
NS		 263#define MAX_WEP_KEY_LEN 13
264#define NUM_WEP_KEYS 4
265
a66098da
LB		 266/* Per interface specific private data */
267struct mwl8k_vif {
f5bb87cf
LB		 268 struct list_head list;
269 struct ieee80211_vif *vif;
270
f57ca9c1
LB		 271 /* Firmware macid for this vif. */
272 int macid;
273
c2c2b12a 274 /* Non AMPDU sequence number assigned by driver. */
a680400e 275 u16 seqno;
e53d9b96
NS		 276
277 /* Saved WEP keys */
278 struct {
279 u8 enabled;
280 u8 key[sizeof(struct ieee80211_key_conf) + MAX_WEP_KEY_LEN];
281 } wep_key_conf[NUM_WEP_KEYS];
d9a07d49
NS		 282
283 /* BSSID */
284 u8 bssid[ETH_ALEN];
285
286 /* A flag to indicate is HW crypto is enabled for this bssid */
287 bool is_hw_crypto_enabled;
a66098da 288};
a94cc97e 289#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
fcdc403c 290#define IEEE80211_KEY_CONF(_u8) ((struct ieee80211_key_conf *)(_u8))
a66098da 291
d0805c1c
BC		 292struct tx_traffic_info {
293 u32 start_time;
294 u32 pkts;
295};
296
297#define MWL8K_MAX_TID 8
a680400e
LB		 298struct mwl8k_sta {
299 /* Index into station database. Returned by UPDATE_STADB. */
300 u8 peer_id;
17033543 301 u8 is_ampdu_allowed;
d0805c1c 302 struct tx_traffic_info tx_stats[MWL8K_MAX_TID];
a680400e
LB		 303};
304#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
305
777ad375 306static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB		 307 { .center_freq = 2412, .hw_value = 1, },
308 { .center_freq = 2417, .hw_value = 2, },
309 { .center_freq = 2422, .hw_value = 3, },
310 { .center_freq = 2427, .hw_value = 4, },
311 { .center_freq = 2432, .hw_value = 5, },
312 { .center_freq = 2437, .hw_value = 6, },
313 { .center_freq = 2442, .hw_value = 7, },
314 { .center_freq = 2447, .hw_value = 8, },
315 { .center_freq = 2452, .hw_value = 9, },
316 { .center_freq = 2457, .hw_value = 10, },
317 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 318 { .center_freq = 2467, .hw_value = 12, },
319 { .center_freq = 2472, .hw_value = 13, },
320 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 321};
322
777ad375 323static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 324 { .bitrate = 10, .hw_value = 2, },
325 { .bitrate = 20, .hw_value = 4, },
326 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 327 { .bitrate = 110, .hw_value = 22, },
328 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 329 { .bitrate = 60, .hw_value = 12, },
330 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 331 { .bitrate = 120, .hw_value = 24, },
332 { .bitrate = 180, .hw_value = 36, },
333 { .bitrate = 240, .hw_value = 48, },
334 { .bitrate = 360, .hw_value = 72, },
335 { .bitrate = 480, .hw_value = 96, },
336 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 337 { .bitrate = 720, .hw_value = 144, },
338};
339
4eae9edd
LB		 340static const struct ieee80211_channel mwl8k_channels_50[] = {
341 { .center_freq = 5180, .hw_value = 36, },
342 { .center_freq = 5200, .hw_value = 40, },
343 { .center_freq = 5220, .hw_value = 44, },
344 { .center_freq = 5240, .hw_value = 48, },
345};
346
347static const struct ieee80211_rate mwl8k_rates_50[] = {
348 { .bitrate = 60, .hw_value = 12, },
349 { .bitrate = 90, .hw_value = 18, },
350 { .bitrate = 120, .hw_value = 24, },
351 { .bitrate = 180, .hw_value = 36, },
352 { .bitrate = 240, .hw_value = 48, },
353 { .bitrate = 360, .hw_value = 72, },
354 { .bitrate = 480, .hw_value = 96, },
355 { .bitrate = 540, .hw_value = 108, },
356 { .bitrate = 720, .hw_value = 144, },
357};
358
a66098da 359/* Set or get info from Firmware */
a66098da 360#define MWL8K_CMD_GET 0x0000
41fdf097
NS		 361#define MWL8K_CMD_SET 0x0001
362#define MWL8K_CMD_SET_LIST 0x0002
a66098da
LB		 363
364/* Firmware command codes */
365#define MWL8K_CMD_CODE_DNLD 0x0001
366#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 367#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 368#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
369#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 370#define MWL8K_CMD_RADIO_CONTROL 0x001c
371#define MWL8K_CMD_RF_TX_POWER 0x001e
41fdf097 372#define MWL8K_CMD_TX_POWER 0x001f
08b06347 373#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 374#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 375#define MWL8K_CMD_SET_PRE_SCAN 0x0107
376#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 377#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
378#define MWL8K_CMD_SET_AID 0x010d
379#define MWL8K_CMD_SET_RATE 0x0110
380#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
381#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 382#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 383#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
384#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 385#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 386#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 387#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 388#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 389#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
3aefc37e 390#define MWL8K_CMD_GET_WATCHDOG_BITMAP 0x0205
aa21d0f6
LB		 391#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
392#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
fcdc403c 393#define MWL8K_CMD_UPDATE_ENCRYPTION 0x1122 /* per-vif */
ff45fc60 394#define MWL8K_CMD_UPDATE_STADB 0x1123
5faa1aff 395#define MWL8K_CMD_BASTREAM 0x1125
a66098da 396
b603742f 397static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 398{
b603742f
JL		 399 u16 command = le16_to_cpu(cmd);
400
a66098da
LB		 401#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
402 snprintf(buf, bufsize, "%s", #x);\
403 return buf;\
404 } while (0)
b603742f 405 switch (command & ~0x8000) {
a66098da
LB		 406 MWL8K_CMDNAME(CODE_DNLD);
407 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 408 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 409 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
410 MWL8K_CMDNAME(GET_STAT);
411 MWL8K_CMDNAME(RADIO_CONTROL);
412 MWL8K_CMDNAME(RF_TX_POWER);
41fdf097 413 MWL8K_CMDNAME(TX_POWER);
08b06347 414 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 415 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 416 MWL8K_CMDNAME(SET_PRE_SCAN);
417 MWL8K_CMDNAME(SET_POST_SCAN);
418 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 419 MWL8K_CMDNAME(SET_AID);
420 MWL8K_CMDNAME(SET_RATE);
421 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
422 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 423 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 424 MWL8K_CMDNAME(SET_EDCA_PARAMS);
425 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 426 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 427 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 428 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 429 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 430 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 431 MWL8K_CMDNAME(BSS_START);
3f5610ff 432 MWL8K_CMDNAME(SET_NEW_STN);
fcdc403c 433 MWL8K_CMDNAME(UPDATE_ENCRYPTION);
ff45fc60 434 MWL8K_CMDNAME(UPDATE_STADB);
5faa1aff 435 MWL8K_CMDNAME(BASTREAM);
3aefc37e 436 MWL8K_CMDNAME(GET_WATCHDOG_BITMAP);
a66098da
LB		 437 default:
438 snprintf(buf, bufsize, "0x%x", cmd);
439 }
440#undef MWL8K_CMDNAME
441
442 return buf;
443}
444
445/* Hardware and firmware reset */
446static void mwl8k_hw_reset(struct mwl8k_priv *priv)
447{
448 iowrite32(MWL8K_H2A_INT_RESET,
449 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
450 iowrite32(MWL8K_H2A_INT_RESET,
451 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
452 msleep(20);
453}
454
455/* Release fw image */
d1f9e41d 456static void mwl8k_release_fw(const struct firmware **fw)
a66098da
LB		 457{
458 if (*fw == NULL)
459 return;
460 release_firmware(*fw);
461 *fw = NULL;
462}
463
464static void mwl8k_release_firmware(struct mwl8k_priv *priv)
465{
22be40d9
LB		 466 mwl8k_release_fw(&priv->fw_ucode);
467 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 468}
469
99020471
BC		 470/* states for asynchronous f/w loading */
471static void mwl8k_fw_state_machine(const struct firmware *fw, void *context);
472enum {
473 FW_STATE_INIT = 0,
474 FW_STATE_LOADING_PREF,
475 FW_STATE_LOADING_ALT,
476 FW_STATE_ERROR,
477};
478
a66098da
LB		 479/* Request fw image */
480static int mwl8k_request_fw(struct mwl8k_priv *priv,
d1f9e41d 481 const char *fname, const struct firmware **fw,
99020471 482 bool nowait)
a66098da
LB		 483{
484 /* release current image */
485 if (*fw != NULL)
486 mwl8k_release_fw(fw);
487
99020471
BC		 488 if (nowait)
489 return request_firmware_nowait(THIS_MODULE, 1, fname,
490 &priv->pdev->dev, GFP_KERNEL,
491 priv, mwl8k_fw_state_machine);
492 else
d1f9e41d 493 return request_firmware(fw, fname, &priv->pdev->dev);
a66098da
LB		 494}
495
99020471
BC		 496static int mwl8k_request_firmware(struct mwl8k_priv *priv, char *fw_image,
497 bool nowait)
a66098da 498{
a74b295e 499 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 500 int rc;
501
a74b295e 502 if (di->helper_image != NULL) {
99020471
BC		 503 if (nowait)
504 rc = mwl8k_request_fw(priv, di->helper_image,
505 &priv->fw_helper, true);
506 else
507 rc = mwl8k_request_fw(priv, di->helper_image,
508 &priv->fw_helper, false);
509 if (rc)
510 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
511 pci_name(priv->pdev), di->helper_image);
512
513 if (rc || nowait)
a74b295e 514 return rc;
a66098da
LB		 515 }
516
99020471
BC		 517 if (nowait) {
518 /*
519 * if we get here, no helper image is needed. Skip the
520 * FW_STATE_INIT state.
521 */
522 priv->fw_state = FW_STATE_LOADING_PREF;
523 rc = mwl8k_request_fw(priv, fw_image,
524 &priv->fw_ucode,
525 true);
526 } else
527 rc = mwl8k_request_fw(priv, fw_image,
528 &priv->fw_ucode, false);
a66098da 529 if (rc) {
c2c357ce 530 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
0863ade8 531 pci_name(priv->pdev), fw_image);
22be40d9 532 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 533 return rc;
534 }
535
536 return 0;
537}
538
539struct mwl8k_cmd_pkt {
540 __le16 code;
541 __le16 length;
f57ca9c1
LB		 542 __u8 seq_num;
543 __u8 macid;
a66098da
LB		 544 __le16 result;
545 char payload[0];
ba2d3587 546} __packed;
a66098da
LB		 547
548/*
549 * Firmware loading.
550 */
551static int
552mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
553{
554 void __iomem *regs = priv->regs;
555 dma_addr_t dma_addr;
a66098da
LB		 556 int loops;
557
558 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
559 if (pci_dma_mapping_error(priv->pdev, dma_addr))
560 return -ENOMEM;
561
562 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
563 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
564 iowrite32(MWL8K_H2A_INT_DOORBELL,
565 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
566 iowrite32(MWL8K_H2A_INT_DUMMY,
567 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
568
a66098da
LB		 569 loops = 1000;
570 do {
571 u32 int_code;
572
573 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
574 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
575 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 576 break;
577 }
578
3d76e82c 579 cond_resched();
a66098da
LB		 580 udelay(1);
581 } while (--loops);
582
583 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
584
d4b70570 585 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 586}
587
588static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
589 const u8 *data, size_t length)
590{
591 struct mwl8k_cmd_pkt *cmd;
592 int done;
593 int rc = 0;
594
595 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
596 if (cmd == NULL)
597 return -ENOMEM;
598
599 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
600 cmd->seq_num = 0;
f57ca9c1 601 cmd->macid = 0;
a66098da
LB		 602 cmd->result = 0;
603
604 done = 0;
605 while (length) {
606 int block_size = length > 256 ? 256 : length;
607
608 memcpy(cmd->payload, data + done, block_size);
609 cmd->length = cpu_to_le16(block_size);
610
611 rc = mwl8k_send_fw_load_cmd(priv, cmd,
612 sizeof(*cmd) + block_size);
613 if (rc)
614 break;
615
616 done += block_size;
617 length -= block_size;
618 }
619
620 if (!rc) {
621 cmd->length = 0;
622 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
623 }
624
625 kfree(cmd);
626
627 return rc;
628}
629
630static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
631 const u8 *data, size_t length)
632{
633 unsigned char *buffer;
634 int may_continue, rc = 0;
635 u32 done, prev_block_size;
636
637 buffer = kmalloc(1024, GFP_KERNEL);
638 if (buffer == NULL)
639 return -ENOMEM;
640
641 done = 0;
642 prev_block_size = 0;
643 may_continue = 1000;
644 while (may_continue > 0) {
645 u32 block_size;
646
647 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
648 if (block_size & 1) {
649 block_size &= ~1;
650 may_continue--;
651 } else {
652 done += prev_block_size;
653 length -= prev_block_size;
654 }
655
656 if (block_size > 1024 || block_size > length) {
657 rc = -EOVERFLOW;
658 break;
659 }
660
661 if (length == 0) {
662 rc = 0;
663 break;
664 }
665
666 if (block_size == 0) {
667 rc = -EPROTO;
668 may_continue--;
669 udelay(1);
670 continue;
671 }
672
673 prev_block_size = block_size;
674 memcpy(buffer, data + done, block_size);
675
676 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
677 if (rc)
678 break;
679 }
680
681 if (!rc && length != 0)
682 rc = -EREMOTEIO;
683
684 kfree(buffer);
685
686 return rc;
687}
688
c2c357ce 689static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 690{
c2c357ce 691 struct mwl8k_priv *priv = hw->priv;
d1f9e41d 692 const struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 693 int rc;
694 int loops;
695
696 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
d1f9e41d 697 const struct firmware *helper = priv->fw_helper;
a66098da 698
c2c357ce
LB		 699 if (helper == NULL) {
700 printk(KERN_ERR "%s: helper image needed but none "
701 "given\n", pci_name(priv->pdev));
702 return -EINVAL;
703 }
a66098da 704
c2c357ce 705 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 706 if (rc) {
707 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 708 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 709 return rc;
710 }
ba30c4a5 711 msleep(20);
a66098da 712
c2c357ce 713 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 714 } else {
c2c357ce 715 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 716 }
717
718 if (rc) {
c2c357ce
LB		 719 printk(KERN_ERR "%s: unable to load firmware image\n",
720 pci_name(priv->pdev));
a66098da
LB		 721 return rc;
722 }
723
89a91f4f 724 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 725
89b872e2 726 loops = 500000;
a66098da 727 do {
eae74e65
LB		 728 u32 ready_code;
729
730 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
731 if (ready_code == MWL8K_FWAP_READY) {
732 priv->ap_fw = 1;
733 break;
734 } else if (ready_code == MWL8K_FWSTA_READY) {
735 priv->ap_fw = 0;
a66098da 736 break;
eae74e65
LB		 737 }
738
739 cond_resched();
a66098da
LB		 740 udelay(1);
741 } while (--loops);
742
743 return loops ? 0 : -ETIMEDOUT;
744}
745
746
a66098da
LB		 747/* DMA header used by firmware and hardware. */
748struct mwl8k_dma_data {
749 __le16 fwlen;
750 struct ieee80211_hdr wh;
20f09c3d 751 char data[0];
ba2d3587 752} __packed;
a66098da
LB		 753
754/* Routines to add/remove DMA header from skb. */
20f09c3d 755static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 756{
20f09c3d
LB		 757 struct mwl8k_dma_data *tr;
758 int hdrlen;
759
760 tr = (struct mwl8k_dma_data *)skb->data;
761 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
762
763 if (hdrlen != sizeof(tr->wh)) {
764 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
765 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
766 *((__le16 *)(tr->data - 2)) = qos;
767 } else {
768 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
769 }
a66098da 770 }
20f09c3d
LB		 771
772 if (hdrlen != sizeof(*tr))
773 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 774}
775
252486a1
NS		 776static void
777mwl8k_add_dma_header(struct sk_buff *skb, int tail_pad)
a66098da
LB		 778{
779 struct ieee80211_hdr *wh;
ca009301 780 int hdrlen;
252486a1 781 int reqd_hdrlen;
a66098da
LB		 782 struct mwl8k_dma_data *tr;
783
ca009301
LB		 784 /*
785 * Add a firmware DMA header; the firmware requires that we
786 * present a 2-byte payload length followed by a 4-address
787 * header (without QoS field), followed (optionally) by any
788 * WEP/ExtIV header (but only filled in for CCMP).
789 */
a66098da 790 wh = (struct ieee80211_hdr *)skb->data;
ca009301 791
a66098da 792 hdrlen = ieee80211_hdrlen(wh->frame_control);
252486a1
NS		 793 reqd_hdrlen = sizeof(*tr);
794
795 if (hdrlen != reqd_hdrlen)
796 skb_push(skb, reqd_hdrlen - hdrlen);
a66098da 797
ca009301 798 if (ieee80211_is_data_qos(wh->frame_control))
252486a1 799 hdrlen -= IEEE80211_QOS_CTL_LEN;
a66098da
LB		 800
801 tr = (struct mwl8k_dma_data *)skb->data;
802 if (wh != &tr->wh)
803 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 804 if (hdrlen != sizeof(tr->wh))
805 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 806
807 /*
808 * Firmware length is the length of the fully formed "802.11
809 * payload". That is, everything except for the 802.11 header.
810 * This includes all crypto material including the MIC.
811 */
252486a1 812 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr) + tail_pad);
a66098da
LB		 813}
814
e53d9b96
NS		 815static void mwl8k_encapsulate_tx_frame(struct sk_buff *skb)
816{
817 struct ieee80211_hdr *wh;
818 struct ieee80211_tx_info *tx_info;
819 struct ieee80211_key_conf *key_conf;
820 int data_pad;
821
822 wh = (struct ieee80211_hdr *)skb->data;
823
824 tx_info = IEEE80211_SKB_CB(skb);
825
826 key_conf = NULL;
827 if (ieee80211_is_data(wh->frame_control))
828 key_conf = tx_info->control.hw_key;
829
830 /*
831 * Make sure the packet header is in the DMA header format (4-address
832 * without QoS), the necessary crypto padding between the header and the
ba30c4a5
YAP		 833 * payload has already been provided by mac80211, but it doesn't add
834 * tail padding when HW crypto is enabled.
e53d9b96
NS		 835 *
836 * We have the following trailer padding requirements:
837 * - WEP: 4 trailer bytes (ICV)
838 * - TKIP: 12 trailer bytes (8 MIC + 4 ICV)
839 * - CCMP: 8 trailer bytes (MIC)
840 */
841 data_pad = 0;
842 if (key_conf != NULL) {
843 switch (key_conf->cipher) {
844 case WLAN_CIPHER_SUITE_WEP40:
845 case WLAN_CIPHER_SUITE_WEP104:
846 data_pad = 4;
847 break;
848 case WLAN_CIPHER_SUITE_TKIP:
849 data_pad = 12;
850 break;
851 case WLAN_CIPHER_SUITE_CCMP:
852 data_pad = 8;
853 break;
854 }
855 }
856 mwl8k_add_dma_header(skb, data_pad);
857}
a66098da
LB		 858
859/*
89a91f4f 860 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 861 */
89a91f4f 862struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 863 __le16 pkt_len;
864 __u8 sq2;
865 __u8 rate;
866 __le32 pkt_phys_addr;
867 __le32 next_rxd_phys_addr;
868 __le16 qos_control;
869 __le16 htsig2;
870 __le32 hw_rssi_info;
871 __le32 hw_noise_floor_info;
872 __u8 noise_floor;
873 __u8 pad0[3];
874 __u8 rssi;
875 __u8 rx_status;
876 __u8 channel;
877 __u8 rx_ctrl;
ba2d3587 878} __packed;
6f6d1e9a 879
89a91f4f
LB		 880#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
881#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
882#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 883
89a91f4f 884#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 885
d9a07d49
NS		 886/* 8366 AP rx_status bits */
887#define MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK 0x80
888#define MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR 0xFF
889#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR 0x02
890#define MWL8K_8366_AP_RXSTAT_WEP_DECRYPT_ICV_ERR 0x04
891#define MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_ICV_ERR 0x08
892
89a91f4f 893static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 894{
89a91f4f 895 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 896
897 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 898 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 899}
900
89a91f4f 901static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 902{
89a91f4f 903 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 904
905 rxd->pkt_len = cpu_to_le16(len);
906 rxd->pkt_phys_addr = cpu_to_le32(addr);
907 wmb();
908 rxd->rx_ctrl = 0;
909}
910
911static int
89a91f4f 912mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 913 __le16 *qos, s8 *noise)
6f6d1e9a 914{
89a91f4f 915 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 916
89a91f4f 917 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 918 return -1;
919 rmb();
920
921 memset(status, 0, sizeof(*status));
922
923 status->signal = -rxd->rssi;
0d462bbb 924 *noise = -rxd->noise_floor;
6f6d1e9a 925
89a91f4f 926 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 927 status->flag |= RX_FLAG_HT;
89a91f4f 928 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 929 status->flag |= RX_FLAG_40MHZ;
89a91f4f 930 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 931 } else {
932 int i;
933
777ad375
LB		 934 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
935 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 936 status->rate_idx = i;
937 break;
938 }
939 }
940 }
941
85478344
LB		 942 if (rxd->channel > 14) {
943 status->band = IEEE80211_BAND_5GHZ;
944 if (!(status->flag & RX_FLAG_HT))
945 status->rate_idx -= 5;
946 } else {
947 status->band = IEEE80211_BAND_2GHZ;
948 }
59eb21a6
BR		 949 status->freq = ieee80211_channel_to_frequency(rxd->channel,
950 status->band);
6f6d1e9a 951
20f09c3d
LB		 952 *qos = rxd->qos_control;
953
d9a07d49
NS		 954 if ((rxd->rx_status != MWL8K_8366_AP_RXSTAT_GENERAL_DECRYPT_ERR) &&
955 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_DECRYPT_ERR_MASK) &&
956 (rxd->rx_status & MWL8K_8366_AP_RXSTAT_TKIP_DECRYPT_MIC_ERR))
957 status->flag |= RX_FLAG_MMIC_ERROR;
958
6f6d1e9a
LB		 959 return le16_to_cpu(rxd->pkt_len);
960}
961
89a91f4f
LB		 962static struct rxd_ops rxd_8366_ap_ops = {
963 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
964 .rxd_init = mwl8k_rxd_8366_ap_init,
965 .rxd_refill = mwl8k_rxd_8366_ap_refill,
966 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 967};
968
969/*
89a91f4f 970 * Packet reception for STA firmware.
a66098da 971 */
89a91f4f 972struct mwl8k_rxd_sta {
a66098da
LB		 973 __le16 pkt_len;
974 __u8 link_quality;
975 __u8 noise_level;
976 __le32 pkt_phys_addr;
45eb400d 977 __le32 next_rxd_phys_addr;
a66098da
LB		 978 __le16 qos_control;
979 __le16 rate_info;
980 __le32 pad0[4];
981 __u8 rssi;
982 __u8 channel;
983 __le16 pad1;
984 __u8 rx_ctrl;
985 __u8 rx_status;
986 __u8 pad2[2];
ba2d3587 987} __packed;
a66098da 988
89a91f4f
LB		 989#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
990#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
991#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
992#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
993#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
994#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 995
89a91f4f 996#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
d9a07d49
NS		 997#define MWL8K_STA_RX_CTRL_DECRYPT_ERROR 0x04
998/* ICV=0 or MIC=1 */
999#define MWL8K_STA_RX_CTRL_DEC_ERR_TYPE 0x08
1000/* Key is uploaded only in failure case */
1001#define MWL8K_STA_RX_CTRL_KEY_INDEX 0x30
54bc3a0d 1002
89a91f4f 1003static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 1004{
89a91f4f 1005 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1006
1007 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 1008 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 1009}
1010
89a91f4f 1011static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 1012{
89a91f4f 1013 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1014
1015 rxd->pkt_len = cpu_to_le16(len);
1016 rxd->pkt_phys_addr = cpu_to_le32(addr);
1017 wmb();
1018 rxd->rx_ctrl = 0;
1019}
1020
1021static int
89a91f4f 1022mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 1023 __le16 *qos, s8 *noise)
54bc3a0d 1024{
89a91f4f 1025 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 1026 u16 rate_info;
1027
89a91f4f 1028 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 1029 return -1;
1030 rmb();
1031
1032 rate_info = le16_to_cpu(rxd->rate_info);
1033
1034 memset(status, 0, sizeof(*status));
1035
1036 status->signal = -rxd->rssi;
0d462bbb 1037 *noise = -rxd->noise_level;
89a91f4f
LB		 1038 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
1039 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 1040
89a91f4f 1041 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 1042 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 1043 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 1044 status->flag |= RX_FLAG_40MHZ;
89a91f4f 1045 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 1046 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 1047 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 1048 status->flag |= RX_FLAG_HT;
1049
85478344
LB		 1050 if (rxd->channel > 14) {
1051 status->band = IEEE80211_BAND_5GHZ;
1052 if (!(status->flag & RX_FLAG_HT))
1053 status->rate_idx -= 5;
1054 } else {
1055 status->band = IEEE80211_BAND_2GHZ;
1056 }
59eb21a6
BR		 1057 status->freq = ieee80211_channel_to_frequency(rxd->channel,
1058 status->band);
54bc3a0d 1059
20f09c3d 1060 *qos = rxd->qos_control;
d9a07d49
NS		 1061 if ((rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DECRYPT_ERROR) &&
1062 (rxd->rx_ctrl & MWL8K_STA_RX_CTRL_DEC_ERR_TYPE))
1063 status->flag |= RX_FLAG_MMIC_ERROR;
20f09c3d 1064
54bc3a0d
LB		 1065 return le16_to_cpu(rxd->pkt_len);
1066}
1067
89a91f4f
LB		 1068static struct rxd_ops rxd_sta_ops = {
1069 .rxd_size = sizeof(struct mwl8k_rxd_sta),
1070 .rxd_init = mwl8k_rxd_sta_init,
1071 .rxd_refill = mwl8k_rxd_sta_refill,
1072 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 1073};
1074
1075
a66098da
LB		 1076#define MWL8K_RX_DESCS 256
1077#define MWL8K_RX_MAXSZ 3800
1078
1079static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
1080{
1081 struct mwl8k_priv *priv = hw->priv;
1082 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1083 int size;
1084 int i;
1085
45eb400d
LB		 1086 rxq->rxd_count = 0;
1087 rxq->head = 0;
1088 rxq->tail = 0;
a66098da 1089
54bc3a0d 1090 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 1091
45eb400d
LB		 1092 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
1093 if (rxq->rxd == NULL) {
5db55844 1094 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 1095 return -ENOMEM;
1096 }
45eb400d 1097 memset(rxq->rxd, 0, size);
a66098da 1098
b9ede5f1 1099 rxq->buf = kcalloc(MWL8K_RX_DESCS, sizeof(*rxq->buf), GFP_KERNEL);
788838eb 1100 if (rxq->buf == NULL) {
5db55844 1101 wiphy_err(hw->wiphy, "failed to alloc RX skbuff list\n");
45eb400d 1102 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 1103 return -ENOMEM;
1104 }
a66098da
LB		 1105
1106 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 1107 int desc_size;
1108 void *rxd;
a66098da 1109 int nexti;
54bc3a0d
LB		 1110 dma_addr_t next_dma_addr;
1111
1112 desc_size = priv->rxd_ops->rxd_size;
1113 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 1114
54bc3a0d
LB		 1115 nexti = i + 1;
1116 if (nexti == MWL8K_RX_DESCS)
1117 nexti = 0;
1118 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 1119
54bc3a0d 1120 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 1121 }
1122
1123 return 0;
1124}
1125
1126static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
1127{
1128 struct mwl8k_priv *priv = hw->priv;
1129 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1130 int refilled;
1131
1132 refilled = 0;
45eb400d 1133 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 1134 struct sk_buff *skb;
788838eb 1135 dma_addr_t addr;
a66098da 1136 int rx;
54bc3a0d 1137 void *rxd;
a66098da
LB		 1138
1139 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
1140 if (skb == NULL)
1141 break;
1142
788838eb
LB		 1143 addr = pci_map_single(priv->pdev, skb->data,
1144 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 1145
54bc3a0d
LB		 1146 rxq->rxd_count++;
1147 rx = rxq->tail++;
1148 if (rxq->tail == MWL8K_RX_DESCS)
1149 rxq->tail = 0;
788838eb 1150 rxq->buf[rx].skb = skb;
53b1b3e1 1151 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 1152
1153 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
1154 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 1155
1156 refilled++;
1157 }
1158
1159 return refilled;
1160}
1161
1162/* Must be called only when the card's reception is completely halted */
1163static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
1164{
1165 struct mwl8k_priv *priv = hw->priv;
1166 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1167 int i;
1168
73b46320
BC		 1169 if (rxq->rxd == NULL)
1170 return;
1171
a66098da 1172 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 1173 if (rxq->buf[i].skb != NULL) {
1174 pci_unmap_single(priv->pdev,
53b1b3e1 1175 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 1176 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1177 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 1178
1179 kfree_skb(rxq->buf[i].skb);
1180 rxq->buf[i].skb = NULL;
a66098da
LB		 1181 }
1182 }
1183
788838eb
LB		 1184 kfree(rxq->buf);
1185 rxq->buf = NULL;
a66098da
LB		 1186
1187 pci_free_consistent(priv->pdev,
54bc3a0d 1188 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1189 rxq->rxd, rxq->rxd_dma);
1190 rxq->rxd = NULL;
a66098da
LB		 1191}
1192
1193
1194/*
1195 * Scan a list of BSSIDs to process for finalize join.
1196 * Allows for extension to process multiple BSSIDs.
1197 */
1198static inline int
1199mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1200{
1201 return priv->capture_beacon &&
1202 ieee80211_is_beacon(wh->frame_control) &&
1203 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1204}
1205
3779752d
LB		 1206static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1207 struct sk_buff *skb)
a66098da 1208{
3779752d
LB		 1209 struct mwl8k_priv *priv = hw->priv;
1210
a66098da 1211 priv->capture_beacon = false;
d89173f2 1212 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1213
1214 /*
1215 * Use GFP_ATOMIC as rxq_process is called from
1216 * the primary interrupt handler, memory allocation call
1217 * must not sleep.
1218 */
1219 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1220 if (priv->beacon_skb != NULL)
3779752d 1221 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1222}
1223
d9a07d49
NS		 1224static inline struct mwl8k_vif *mwl8k_find_vif_bss(struct list_head *vif_list,
1225 u8 *bssid)
1226{
1227 struct mwl8k_vif *mwl8k_vif;
1228
1229 list_for_each_entry(mwl8k_vif,
1230 vif_list, list) {
1231 if (memcmp(bssid, mwl8k_vif->bssid,
1232 ETH_ALEN) == 0)
1233 return mwl8k_vif;
1234 }
1235
1236 return NULL;
1237}
1238
a66098da
LB		 1239static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1240{
1241 struct mwl8k_priv *priv = hw->priv;
d9a07d49 1242 struct mwl8k_vif *mwl8k_vif = NULL;
a66098da
LB		 1243 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1244 int processed;
1245
1246 processed = 0;
45eb400d 1247 while (rxq->rxd_count && limit--) {
a66098da 1248 struct sk_buff *skb;
54bc3a0d
LB		 1249 void *rxd;
1250 int pkt_len;
a66098da 1251 struct ieee80211_rx_status status;
d9a07d49 1252 struct ieee80211_hdr *wh;
20f09c3d 1253 __le16 qos;
a66098da 1254
788838eb 1255 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1256 if (skb == NULL)
1257 break;
54bc3a0d
LB		 1258
1259 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1260
0d462bbb
JL		 1261 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1262 &priv->noise);
54bc3a0d
LB		 1263 if (pkt_len < 0)
1264 break;
1265
788838eb
LB		 1266 rxq->buf[rxq->head].skb = NULL;
1267
1268 pci_unmap_single(priv->pdev,
53b1b3e1 1269 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1270 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1271 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1272
54bc3a0d
LB		 1273 rxq->head++;
1274 if (rxq->head == MWL8K_RX_DESCS)
1275 rxq->head = 0;
1276
45eb400d 1277 rxq->rxd_count--;
a66098da 1278
d9a07d49 1279 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da 1280
a66098da 1281 /*
c2c357ce
LB		 1282 * Check for a pending join operation. Save a
1283 * copy of the beacon and schedule a tasklet to
1284 * send a FINALIZE_JOIN command to the firmware.
a66098da 1285 */
54bc3a0d 1286 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1287 mwl8k_save_beacon(hw, skb);
a66098da 1288
d9a07d49
NS		 1289 if (ieee80211_has_protected(wh->frame_control)) {
1290
1291 /* Check if hw crypto has been enabled for
1292 * this bss. If yes, set the status flags
1293 * accordingly
1294 */
1295 mwl8k_vif = mwl8k_find_vif_bss(&priv->vif_list,
1296 wh->addr1);
1297
1298 if (mwl8k_vif != NULL &&
1299 mwl8k_vif->is_hw_crypto_enabled == true) {
1300 /*
1301 * When MMIC ERROR is encountered
1302 * by the firmware, payload is
1303 * dropped and only 32 bytes of
1304 * mwl8k Firmware header is sent
1305 * to the host.
1306 *
1307 * We need to add four bytes of
1308 * key information. In it
1309 * MAC80211 expects keyidx set to
1310 * 0 for triggering Counter
1311 * Measure of MMIC failure.
1312 */
1313 if (status.flag & RX_FLAG_MMIC_ERROR) {
1314 struct mwl8k_dma_data *tr;
1315 tr = (struct mwl8k_dma_data *)skb->data;
1316 memset((void *)&(tr->data), 0, 4);
1317 pkt_len += 4;
1318 }
1319
1320 if (!ieee80211_is_auth(wh->frame_control))
1321 status.flag |= RX_FLAG_IV_STRIPPED |
1322 RX_FLAG_DECRYPTED |
1323 RX_FLAG_MMIC_STRIPPED;
1324 }
1325 }
1326
1327 skb_put(skb, pkt_len);
1328 mwl8k_remove_dma_header(skb, qos);
f1d58c25
JB		 1329 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1330 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1331
1332 processed++;
1333 }
1334
1335 return processed;
1336}
1337
1338
1339/*
1340 * Packet transmission.
1341 */
1342
a66098da
LB		 1343#define MWL8K_TXD_STATUS_OK 0x00000001
1344#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1345#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1346#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1347#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1348
e0493a8d
LB		 1349#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1350#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1351#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1352#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1353#define MWL8K_QOS_EOSP 0x0010
1354
a66098da
LB		 1355struct mwl8k_tx_desc {
1356 __le32 status;
1357 __u8 data_rate;
1358 __u8 tx_priority;
1359 __le16 qos_control;
1360 __le32 pkt_phys_addr;
1361 __le16 pkt_len;
d89173f2 1362 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1363 __le32 next_txd_phys_addr;
8a7a578c 1364 __le32 timestamp;
a66098da
LB		 1365 __le16 rate_info;
1366 __u8 peer_id;
a1fe24b0 1367 __u8 tx_frag_cnt;
ba2d3587 1368} __packed;
a66098da
LB		 1369
1370#define MWL8K_TX_DESCS 128
1371
1372static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1373{
1374 struct mwl8k_priv *priv = hw->priv;
1375 struct mwl8k_tx_queue *txq = priv->txq + index;
1376 int size;
1377 int i;
1378
8ccbc3b8 1379 txq->len = 0;
45eb400d
LB		 1380 txq->head = 0;
1381 txq->tail = 0;
a66098da
LB		 1382
1383 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1384
45eb400d
LB		 1385 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1386 if (txq->txd == NULL) {
5db55844 1387 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1388 return -ENOMEM;
1389 }
45eb400d 1390 memset(txq->txd, 0, size);
a66098da 1391
b9ede5f1 1392 txq->skb = kcalloc(MWL8K_TX_DESCS, sizeof(*txq->skb), GFP_KERNEL);
45eb400d 1393 if (txq->skb == NULL) {
5db55844 1394 wiphy_err(hw->wiphy, "failed to alloc TX skbuff list\n");
45eb400d 1395 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1396 return -ENOMEM;
1397 }
a66098da
LB		 1398
1399 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1400 struct mwl8k_tx_desc *tx_desc;
1401 int nexti;
1402
45eb400d 1403 tx_desc = txq->txd + i;
a66098da
LB		 1404 nexti = (i + 1) % MWL8K_TX_DESCS;
1405
1406 tx_desc->status = 0;
45eb400d
LB		 1407 tx_desc->next_txd_phys_addr =
1408 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1409 }
1410
1411 return 0;
1412}
1413
1414static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1415{
1416 iowrite32(MWL8K_H2A_INT_PPA_READY,
1417 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1418 iowrite32(MWL8K_H2A_INT_DUMMY,
1419 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1420 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1421}
1422
7e1112d3 1423static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1424{
7e1112d3
LB		 1425 struct mwl8k_priv *priv = hw->priv;
1426 int i;
1427
e600707b 1428 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
7e1112d3
LB		 1429 struct mwl8k_tx_queue *txq = priv->txq + i;
1430 int fw_owned = 0;
1431 int drv_owned = 0;
1432 int unused = 0;
1433 int desc;
1434
a66098da 1435 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1436 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1437 u32 status;
a66098da 1438
7e1112d3 1439 status = le32_to_cpu(tx_desc->status);
a66098da 1440 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1441 fw_owned++;
a66098da 1442 else
7e1112d3 1443 drv_owned++;
a66098da
LB		 1444
1445 if (tx_desc->pkt_len == 0)
7e1112d3 1446 unused++;
a66098da 1447 }
a66098da 1448
c96c31e4
JP		 1449 wiphy_err(hw->wiphy,
1450 "txq[%d] len=%d head=%d tail=%d "
1451 "fw_owned=%d drv_owned=%d unused=%d\n",
1452 i,
1453 txq->len, txq->head, txq->tail,
1454 fw_owned, drv_owned, unused);
7e1112d3 1455 }
a66098da
LB		 1456}
1457
618952a7 1458/*
88de754a 1459 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1460 */
62abd3cf 1461#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1462
950d5b01 1463static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1464{
a66098da 1465 struct mwl8k_priv *priv = hw->priv;
88de754a 1466 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1467 int retry;
1468 int rc;
a66098da
LB		 1469
1470 might_sleep();
1471
7e1112d3
LB		 1472 /*
1473 * The TX queues are stopped at this point, so this test
1474 * doesn't need to take ->tx_lock.
1475 */
1476 if (!priv->pending_tx_pkts)
1477 return 0;
1478
1479 retry = 0;
1480 rc = 0;
1481
a66098da 1482 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1483 priv->tx_wait = &tx_wait;
1484 while (!rc) {
1485 int oldcount;
1486 unsigned long timeout;
a66098da 1487
7e1112d3 1488 oldcount = priv->pending_tx_pkts;
a66098da 1489
7e1112d3 1490 spin_unlock_bh(&priv->tx_lock);
88de754a 1491 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1492 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1493 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1494
1495 if (timeout) {
1496 WARN_ON(priv->pending_tx_pkts);
ba30c4a5 1497 if (retry)
c96c31e4 1498 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1499 break;
1500 }
1501
1502 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1503 wiphy_notice(hw->wiphy,
1504 "waiting for tx rings to drain (%d -> %d pkts)\n",
1505 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1506 retry = 1;
1507 continue;
1508 }
1509
a66098da 1510 priv->tx_wait = NULL;
a66098da 1511
c96c31e4
JP		 1512 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1513 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3
LB		 1514 mwl8k_dump_tx_rings(hw);
1515
1516 rc = -ETIMEDOUT;
a66098da 1517 }
7e1112d3 1518 spin_unlock_bh(&priv->tx_lock);
a66098da 1519
7e1112d3 1520 return rc;
a66098da
LB		 1521}
1522
c23b5a69
LB		 1523#define MWL8K_TXD_SUCCESS(status) \
1524 ((status) & (MWL8K_TXD_STATUS_OK | \
1525 MWL8K_TXD_STATUS_OK_RETRY | \
1526 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1527
a0e7c6cf
NS		 1528static int mwl8k_tid_queue_mapping(u8 tid)
1529{
1530 BUG_ON(tid > 7);
1531
1532 switch (tid) {
1533 case 0:
1534 case 3:
1535 return IEEE80211_AC_BE;
1536 break;
1537 case 1:
1538 case 2:
1539 return IEEE80211_AC_BK;
1540 break;
1541 case 4:
1542 case 5:
1543 return IEEE80211_AC_VI;
1544 break;
1545 case 6:
1546 case 7:
1547 return IEEE80211_AC_VO;
1548 break;
1549 default:
1550 return -1;
1551 break;
1552 }
1553}
1554
17033543
NS		 1555/* The firmware will fill in the rate information
1556 * for each packet that gets queued in the hardware
1557 * in this structure
1558 */
1559
1560struct rateinfo {
1561 __le16 format:1;
1562 __le16 short_gi:1;
1563 __le16 band_width:1;
1564 __le16 rate_id_mcs:6;
1565 __le16 adv_coding:2;
1566 __le16 antenna:2;
1567 __le16 act_sub_chan:2;
1568 __le16 preamble_type:1;
1569 __le16 power_id:4;
1570 __le16 antenna2:1;
1571 __le16 reserved:1;
1572 __le16 tx_bf_frame:1;
1573 __le16 green_field:1;
1574} __packed;
1575
efb7c49a
LB		 1576static int
1577mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1578{
1579 struct mwl8k_priv *priv = hw->priv;
1580 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1581 int processed;
a66098da 1582
efb7c49a 1583 processed = 0;
8ccbc3b8 1584 while (txq->len > 0 && limit--) {
a66098da 1585 int tx;
a66098da
LB		 1586 struct mwl8k_tx_desc *tx_desc;
1587 unsigned long addr;
ce9e2e1b 1588 int size;
a66098da
LB		 1589 struct sk_buff *skb;
1590 struct ieee80211_tx_info *info;
1591 u32 status;
17033543
NS		 1592 struct ieee80211_sta *sta;
1593 struct mwl8k_sta *sta_info = NULL;
1594 u16 rate_info;
1595 struct rateinfo *rate;
1596 struct ieee80211_hdr *wh;
a66098da 1597
45eb400d
LB		 1598 tx = txq->head;
1599 tx_desc = txq->txd + tx;
a66098da
LB		 1600
1601 status = le32_to_cpu(tx_desc->status);
1602
1603 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1604 if (!force)
1605 break;
1606 tx_desc->status &=
1607 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1608 }
1609
45eb400d 1610 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1611 BUG_ON(txq->len == 0);
1612 txq->len--;
a66098da
LB		 1613 priv->pending_tx_pkts--;
1614
1615 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1616 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1617 skb = txq->skb[tx];
1618 txq->skb[tx] = NULL;
a66098da
LB		 1619
1620 BUG_ON(skb == NULL);
1621 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1622
20f09c3d 1623 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da 1624
17033543
NS		 1625 wh = (struct ieee80211_hdr *) skb->data;
1626
a66098da
LB		 1627 /* Mark descriptor as unused */
1628 tx_desc->pkt_phys_addr = 0;
1629 tx_desc->pkt_len = 0;
1630
a66098da 1631 info = IEEE80211_SKB_CB(skb);
17033543
NS		 1632 if (ieee80211_is_data(wh->frame_control)) {
1633 sta = info->control.sta;
1634 if (sta) {
1635 sta_info = MWL8K_STA(sta);
1636 BUG_ON(sta_info == NULL);
1637 rate_info = le16_to_cpu(tx_desc->rate_info);
1638 rate = (struct rateinfo *)&rate_info;
1639 /* If rate is < 6.5 Mpbs for an ht station
1640 * do not form an ampdu. If the station is a
1641 * legacy station (format = 0), do not form an
1642 * ampdu
1643 */
1644 if (rate->rate_id_mcs < 1 ||
1645 rate->format == 0) {
1646 sta_info->is_ampdu_allowed = false;
1647 } else {
1648 sta_info->is_ampdu_allowed = true;
1649 }
1650 }
1651 }
1652
a66098da 1653 ieee80211_tx_info_clear_status(info);
0bf22c37
NS		 1654
1655 /* Rate control is happening in the firmware.
1656 * Ensure no tx rate is being reported.
1657 */
ba30c4a5
YAP		 1658 info->status.rates[0].idx = -1;
1659 info->status.rates[0].count = 1;
0bf22c37 1660
ce9e2e1b 1661 if (MWL8K_TXD_SUCCESS(status))
a66098da 1662 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1663
1664 ieee80211_tx_status_irqsafe(hw, skb);
1665
efb7c49a 1666 processed++;
a66098da
LB		 1667 }
1668
efb7c49a 1669 return processed;
a66098da
LB		 1670}
1671
1672/* must be called only when the card's transmit is completely halted */
1673static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1674{
1675 struct mwl8k_priv *priv = hw->priv;
1676 struct mwl8k_tx_queue *txq = priv->txq + index;
1677
73b46320
BC		 1678 if (txq->txd == NULL)
1679 return;
1680
efb7c49a 1681 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1682
45eb400d
LB		 1683 kfree(txq->skb);
1684 txq->skb = NULL;
a66098da
LB		 1685
1686 pci_free_consistent(priv->pdev,
1687 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1688 txq->txd, txq->txd_dma);
1689 txq->txd = NULL;
a66098da
LB		 1690}
1691
ac109fd0 1692/* caller must hold priv->stream_lock when calling the stream functions */
ba30c4a5 1693static struct mwl8k_ampdu_stream *
ac109fd0
BC		 1694mwl8k_add_stream(struct ieee80211_hw *hw, struct ieee80211_sta *sta, u8 tid)
1695{
1696 struct mwl8k_ampdu_stream *stream;
1697 struct mwl8k_priv *priv = hw->priv;
1698 int i;
1699
1700 for (i = 0; i < priv->num_ampdu_queues; i++) {
1701 stream = &priv->ampdu[i];
1702 if (stream->state == AMPDU_NO_STREAM) {
1703 stream->sta = sta;
1704 stream->state = AMPDU_STREAM_NEW;
1705 stream->tid = tid;
1706 stream->idx = i;
1707 stream->txq_idx = MWL8K_TX_WMM_QUEUES + i;
1708 wiphy_debug(hw->wiphy, "Added a new stream for %pM %d",
1709 sta->addr, tid);
1710 return stream;
1711 }
1712 }
1713 return NULL;
1714}
1715
1716static int
1717mwl8k_start_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1718{
1719 int ret;
1720
1721 /* if the stream has already been started, don't start it again */
1722 if (stream->state != AMPDU_STREAM_NEW)
1723 return 0;
1724 ret = ieee80211_start_tx_ba_session(stream->sta, stream->tid, 0);
1725 if (ret)
1726 wiphy_debug(hw->wiphy, "Failed to start stream for %pM %d: "
1727 "%d\n", stream->sta->addr, stream->tid, ret);
1728 else
1729 wiphy_debug(hw->wiphy, "Started stream for %pM %d\n",
1730 stream->sta->addr, stream->tid);
1731 return ret;
1732}
1733
1734static void
1735mwl8k_remove_stream(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
1736{
1737 wiphy_debug(hw->wiphy, "Remove stream for %pM %d\n", stream->sta->addr,
1738 stream->tid);
1739 memset(stream, 0, sizeof(*stream));
1740}
1741
1742static struct mwl8k_ampdu_stream *
1743mwl8k_lookup_stream(struct ieee80211_hw *hw, u8 *addr, u8 tid)
1744{
1745 struct mwl8k_priv *priv = hw->priv;
1746 int i;
1747
1748 for (i = 0 ; i < priv->num_ampdu_queues; i++) {
1749 struct mwl8k_ampdu_stream *stream;
1750 stream = &priv->ampdu[i];
1751 if (stream->state == AMPDU_NO_STREAM)
1752 continue;
1753 if (!memcmp(stream->sta->addr, addr, ETH_ALEN) &&
1754 stream->tid == tid)
1755 return stream;
1756 }
1757 return NULL;
1758}
1759
d0805c1c
BC		 1760#define MWL8K_AMPDU_PACKET_THRESHOLD 64
1761static inline bool mwl8k_ampdu_allowed(struct ieee80211_sta *sta, u8 tid)
1762{
1763 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1764 struct tx_traffic_info *tx_stats;
1765
1766 BUG_ON(tid >= MWL8K_MAX_TID);
1767 tx_stats = &sta_info->tx_stats[tid];
1768
1769 return sta_info->is_ampdu_allowed &&
1770 tx_stats->pkts > MWL8K_AMPDU_PACKET_THRESHOLD;
1771}
1772
1773static inline void mwl8k_tx_count_packet(struct ieee80211_sta *sta, u8 tid)
1774{
1775 struct mwl8k_sta *sta_info = MWL8K_STA(sta);
1776 struct tx_traffic_info *tx_stats;
1777
1778 BUG_ON(tid >= MWL8K_MAX_TID);
1779 tx_stats = &sta_info->tx_stats[tid];
1780
1781 if (tx_stats->start_time == 0)
1782 tx_stats->start_time = jiffies;
1783
1784 /* reset the packet count after each second elapses. If the number of
1785 * packets ever exceeds the ampdu_min_traffic threshold, we will allow
1786 * an ampdu stream to be started.
1787 */
1788 if (jiffies - tx_stats->start_time > HZ) {
1789 tx_stats->pkts = 0;
1790 tx_stats->start_time = 0;
1791 } else
1792 tx_stats->pkts++;
1793}
1794
7bb45683 1795static void
a66098da
LB		 1796mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1797{
1798 struct mwl8k_priv *priv = hw->priv;
1799 struct ieee80211_tx_info *tx_info;
23b33906 1800 struct mwl8k_vif *mwl8k_vif;
65f3ddcd 1801 struct ieee80211_sta *sta;
a66098da
LB		 1802 struct ieee80211_hdr *wh;
1803 struct mwl8k_tx_queue *txq;
1804 struct mwl8k_tx_desc *tx;
a66098da 1805 dma_addr_t dma;
23b33906
LB		 1806 u32 txstatus;
1807 u8 txdatarate;
1808 u16 qos;
65f3ddcd
NS		 1809 int txpriority;
1810 u8 tid = 0;
1811 struct mwl8k_ampdu_stream *stream = NULL;
1812 bool start_ba_session = false;
a0e7c6cf 1813 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
a66098da 1814
23b33906
LB		 1815 wh = (struct ieee80211_hdr *)skb->data;
1816 if (ieee80211_is_data_qos(wh->frame_control))
1817 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1818 else
1819 qos = 0;
a66098da 1820
d9a07d49
NS		 1821 if (priv->ap_fw)
1822 mwl8k_encapsulate_tx_frame(skb);
1823 else
1824 mwl8k_add_dma_header(skb, 0);
1825
23b33906 1826 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1827
1828 tx_info = IEEE80211_SKB_CB(skb);
65f3ddcd 1829 sta = tx_info->control.sta;
a66098da 1830 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1831
1832 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1833 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1834 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1835 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1836 }
1837
23b33906
LB		 1838 /* Setup firmware control bit fields for each frame type. */
1839 txstatus = 0;
1840 txdatarate = 0;
1841 if (ieee80211_is_mgmt(wh->frame_control) ||
1842 ieee80211_is_ctl(wh->frame_control)) {
1843 txdatarate = 0;
e0493a8d 1844 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1845 } else if (ieee80211_is_data(wh->frame_control)) {
1846 txdatarate = 1;
1847 if (is_multicast_ether_addr(wh->addr1))
1848 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1849
e0493a8d 1850 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1851 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1852 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1853 else
e0493a8d 1854 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1855 }
a66098da 1856
a0e7c6cf
NS		 1857 /* Queue ADDBA request in the respective data queue. While setting up
1858 * the ampdu stream, mac80211 queues further packets for that
1859 * particular ra/tid pair. However, packets piled up in the hardware
1860 * for that ra/tid pair will still go out. ADDBA request and the
1861 * related data packets going out from different queues asynchronously
1862 * will cause a shift in the receiver window which might result in
1863 * ampdu packets getting dropped at the receiver after the stream has
1864 * been setup.
1865 */
1866 if (unlikely(ieee80211_is_action(wh->frame_control) &&
1867 mgmt->u.action.category == WLAN_CATEGORY_BACK &&
1868 mgmt->u.action.u.addba_req.action_code == WLAN_ACTION_ADDBA_REQ &&
1869 priv->ap_fw)) {
1870 u16 capab = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
1871 tid = (capab & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2;
1872 index = mwl8k_tid_queue_mapping(tid);
1873 }
1874
65f3ddcd
NS		 1875 txpriority = index;
1876
1877 if (ieee80211_is_data_qos(wh->frame_control) &&
1878 skb->protocol != cpu_to_be16(ETH_P_PAE) &&
1879 sta->ht_cap.ht_supported && priv->ap_fw) {
1880 tid = qos & 0xf;
d0805c1c 1881 mwl8k_tx_count_packet(sta, tid);
65f3ddcd
NS		 1882 spin_lock(&priv->stream_lock);
1883 stream = mwl8k_lookup_stream(hw, sta->addr, tid);
1884 if (stream != NULL) {
1885 if (stream->state == AMPDU_STREAM_ACTIVE) {
1886 txpriority = stream->txq_idx;
1887 index = stream->txq_idx;
1888 } else if (stream->state == AMPDU_STREAM_NEW) {
1889 /* We get here if the driver sends us packets
1890 * after we've initiated a stream, but before
1891 * our ampdu_action routine has been called
1892 * with IEEE80211_AMPDU_TX_START to get the SSN
1893 * for the ADDBA request. So this packet can
1894 * go out with no risk of sequence number
1895 * mismatch. No special handling is required.
1896 */
1897 } else {
1898 /* Drop packets that would go out after the
1899 * ADDBA request was sent but before the ADDBA
1900 * response is received. If we don't do this,
1901 * the recipient would probably receive it
1902 * after the ADDBA request with SSN 0. This
1903 * will cause the recipient's BA receive window
1904 * to shift, which would cause the subsequent
1905 * packets in the BA stream to be discarded.
1906 * mac80211 queues our packets for us in this
1907 * case, so this is really just a safety check.
1908 */
1909 wiphy_warn(hw->wiphy,
1910 "Cannot send packet while ADDBA "
1911 "dialog is underway.\n");
1912 spin_unlock(&priv->stream_lock);
1913 dev_kfree_skb(skb);
1914 return;
1915 }
1916 } else {
1917 /* Defer calling mwl8k_start_stream so that the current
1918 * skb can go out before the ADDBA request. This
1919 * prevents sequence number mismatch at the recepient
1920 * as described above.
1921 */
d0805c1c 1922 if (mwl8k_ampdu_allowed(sta, tid)) {
17033543
NS		 1923 stream = mwl8k_add_stream(hw, sta, tid);
1924 if (stream != NULL)
1925 start_ba_session = true;
1926 }
65f3ddcd
NS		 1927 }
1928 spin_unlock(&priv->stream_lock);
1929 }
1930
a66098da
LB		 1931 dma = pci_map_single(priv->pdev, skb->data,
1932 skb->len, PCI_DMA_TODEVICE);
1933
1934 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 1935 wiphy_debug(hw->wiphy,
1936 "failed to dma map skb, dropping TX frame.\n");
65f3ddcd
NS		 1937 if (start_ba_session) {
1938 spin_lock(&priv->stream_lock);
1939 mwl8k_remove_stream(hw, stream);
1940 spin_unlock(&priv->stream_lock);
1941 }
23b33906 1942 dev_kfree_skb(skb);
7bb45683 1943 return;
a66098da
LB		 1944 }
1945
23b33906 1946 spin_lock_bh(&priv->tx_lock);
a66098da 1947
23b33906 1948 txq = priv->txq + index;
a66098da 1949
3a7dbc3b
PN		 1950 if (txq->len >= MWL8K_TX_DESCS) {
1951 if (start_ba_session) {
1952 spin_lock(&priv->stream_lock);
1953 mwl8k_remove_stream(hw, stream);
1954 spin_unlock(&priv->stream_lock);
1955 }
65f3ddcd 1956 spin_unlock_bh(&priv->tx_lock);
3a7dbc3b 1957 dev_kfree_skb(skb);
65f3ddcd
NS		 1958 return;
1959 }
1960
45eb400d
LB		 1961 BUG_ON(txq->skb[txq->tail] != NULL);
1962 txq->skb[txq->tail] = skb;
a66098da 1963
45eb400d 1964 tx = txq->txd + txq->tail;
23b33906 1965 tx->data_rate = txdatarate;
65f3ddcd 1966 tx->tx_priority = txpriority;
a66098da 1967 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1968 tx->pkt_phys_addr = cpu_to_le32(dma);
1969 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1970 tx->rate_info = 0;
a680400e
LB		 1971 if (!priv->ap_fw && tx_info->control.sta != NULL)
1972 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1973 else
1974 tx->peer_id = 0;
a66098da 1975 wmb();
23b33906
LB		 1976 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1977
8ccbc3b8 1978 txq->len++;
a66098da 1979 priv->pending_tx_pkts++;
a66098da 1980
45eb400d
LB		 1981 txq->tail++;
1982 if (txq->tail == MWL8K_TX_DESCS)
1983 txq->tail = 0;
23b33906 1984
23b33906 1985 mwl8k_tx_start(priv);
a66098da
LB		 1986
1987 spin_unlock_bh(&priv->tx_lock);
65f3ddcd
NS		 1988
1989 /* Initiate the ampdu session here */
1990 if (start_ba_session) {
1991 spin_lock(&priv->stream_lock);
1992 if (mwl8k_start_stream(hw, stream))
1993 mwl8k_remove_stream(hw, stream);
1994 spin_unlock(&priv->stream_lock);
1995 }
a66098da
LB		 1996}
1997
1998
618952a7
LB		 1999/*
2000 * Firmware access.
2001 *
2002 * We have the following requirements for issuing firmware commands:
2003 * - Some commands require that the packet transmit path is idle when
2004 * the command is issued. (For simplicity, we'll just quiesce the
2005 * transmit path for every command.)
2006 * - There are certain sequences of commands that need to be issued to
2007 * the hardware sequentially, with no other intervening commands.
2008 *
2009 * This leads to an implementation of a "firmware lock" as a mutex that
2010 * can be taken recursively, and which is taken by both the low-level
2011 * command submission function (mwl8k_post_cmd) as well as any users of
2012 * that function that require issuing of an atomic sequence of commands,
2013 * and quiesces the transmit path whenever it's taken.
2014 */
2015static int mwl8k_fw_lock(struct ieee80211_hw *hw)
2016{
2017 struct mwl8k_priv *priv = hw->priv;
2018
2019 if (priv->fw_mutex_owner != current) {
2020 int rc;
2021
2022 mutex_lock(&priv->fw_mutex);
2023 ieee80211_stop_queues(hw);
2024
2025 rc = mwl8k_tx_wait_empty(hw);
2026 if (rc) {
2027 ieee80211_wake_queues(hw);
2028 mutex_unlock(&priv->fw_mutex);
2029
2030 return rc;
2031 }
2032
2033 priv->fw_mutex_owner = current;
2034 }
2035
2036 priv->fw_mutex_depth++;
2037
2038 return 0;
2039}
2040
2041static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
2042{
2043 struct mwl8k_priv *priv = hw->priv;
2044
2045 if (!--priv->fw_mutex_depth) {
2046 ieee80211_wake_queues(hw);
2047 priv->fw_mutex_owner = NULL;
2048 mutex_unlock(&priv->fw_mutex);
2049 }
2050}
2051
2052
a66098da
LB		 2053/*
2054 * Command processing.
2055 */
2056
0c9cc640
LB		 2057/* Timeout firmware commands after 10s */
2058#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 2059
2060static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
2061{
2062 DECLARE_COMPLETION_ONSTACK(cmd_wait);
2063 struct mwl8k_priv *priv = hw->priv;
2064 void __iomem *regs = priv->regs;
2065 dma_addr_t dma_addr;
2066 unsigned int dma_size;
2067 int rc;
a66098da
LB		 2068 unsigned long timeout = 0;
2069 u8 buf[32];
2070
b603742f 2071 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 2072 dma_size = le16_to_cpu(cmd->length);
2073 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
2074 PCI_DMA_BIDIRECTIONAL);
2075 if (pci_dma_mapping_error(priv->pdev, dma_addr))
2076 return -ENOMEM;
2077
618952a7 2078 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 2079 if (rc) {
2080 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2081 PCI_DMA_BIDIRECTIONAL);
618952a7 2082 return rc;
39a1e42e 2083 }
a66098da 2084
a66098da
LB		 2085 priv->hostcmd_wait = &cmd_wait;
2086 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
2087 iowrite32(MWL8K_H2A_INT_DOORBELL,
2088 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
2089 iowrite32(MWL8K_H2A_INT_DUMMY,
2090 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 2091
2092 timeout = wait_for_completion_timeout(&cmd_wait,
2093 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
2094
618952a7
LB		 2095 priv->hostcmd_wait = NULL;
2096
2097 mwl8k_fw_unlock(hw);
2098
37055bd4
LB		 2099 pci_unmap_single(priv->pdev, dma_addr, dma_size,
2100 PCI_DMA_BIDIRECTIONAL);
2101
a66098da 2102 if (!timeout) {
5db55844 2103 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 2104 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2105 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 2106 rc = -ETIMEDOUT;
2107 } else {
0c9cc640
LB		 2108 int ms;
2109
2110 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
2111
ce9e2e1b 2112 rc = cmd->result ? -EINVAL : 0;
a66098da 2113 if (rc)
5db55844 2114 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 2115 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
2116 le16_to_cpu(cmd->result));
0c9cc640 2117 else if (ms > 2000)
5db55844 2118 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 2119 mwl8k_cmd_name(cmd->code,
2120 buf, sizeof(buf)),
2121 ms);
a66098da
LB		 2122 }
2123
a66098da
LB		 2124 return rc;
2125}
2126
f57ca9c1
LB		 2127static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
2128 struct ieee80211_vif *vif,
2129 struct mwl8k_cmd_pkt *cmd)
2130{
2131 if (vif != NULL)
2132 cmd->macid = MWL8K_VIF(vif)->macid;
2133 return mwl8k_post_cmd(hw, cmd);
2134}
2135
1349ad2f
LB		 2136/*
2137 * Setup code shared between STA and AP firmware images.
2138 */
2139static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
2140{
2141 struct mwl8k_priv *priv = hw->priv;
2142
2143 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
2144 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
2145
2146 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
2147 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
2148
2149 priv->band_24.band = IEEE80211_BAND_2GHZ;
2150 priv->band_24.channels = priv->channels_24;
2151 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
2152 priv->band_24.bitrates = priv->rates_24;
2153 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
2154
2155 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
2156}
2157
4eae9edd
LB		 2158static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
2159{
2160 struct mwl8k_priv *priv = hw->priv;
2161
2162 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
2163 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
2164
2165 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
2166 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
2167
2168 priv->band_50.band = IEEE80211_BAND_5GHZ;
2169 priv->band_50.channels = priv->channels_50;
2170 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
2171 priv->band_50.bitrates = priv->rates_50;
2172 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
2173
2174 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
2175}
2176
a66098da 2177/*
04b147b1 2178 * CMD_GET_HW_SPEC (STA version).
a66098da 2179 */
04b147b1 2180struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 2181 struct mwl8k_cmd_pkt header;
2182 __u8 hw_rev;
2183 __u8 host_interface;
2184 __le16 num_mcaddrs;
d89173f2 2185 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 2186 __le16 region_code;
2187 __le32 fw_rev;
2188 __le32 ps_cookie;
2189 __le32 caps;
2190 __u8 mcs_bitmap[16];
2191 __le32 rx_queue_ptr;
2192 __le32 num_tx_queues;
e600707b 2193 __le32 tx_queue_ptrs[MWL8K_TX_WMM_QUEUES];
a66098da
LB		 2194 __le32 caps2;
2195 __le32 num_tx_desc_per_queue;
45eb400d 2196 __le32 total_rxd;
ba2d3587 2197} __packed;
a66098da 2198
341c9791
LB		 2199#define MWL8K_CAP_MAX_AMSDU 0x20000000
2200#define MWL8K_CAP_GREENFIELD 0x08000000
2201#define MWL8K_CAP_AMPDU 0x04000000
2202#define MWL8K_CAP_RX_STBC 0x01000000
2203#define MWL8K_CAP_TX_STBC 0x00800000
2204#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
2205#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
2206#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
2207#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
2208#define MWL8K_CAP_DELAY_BA 0x00003000
2209#define MWL8K_CAP_MIMO 0x00000200
2210#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 2211#define MWL8K_CAP_BAND_MASK 0x00000007
2212#define MWL8K_CAP_5GHZ 0x00000004
2213#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 2214
06953235
LB		 2215static void
2216mwl8k_set_ht_caps(struct ieee80211_hw *hw,
2217 struct ieee80211_supported_band *band, u32 cap)
341c9791 2218{
341c9791
LB		 2219 int rx_streams;
2220 int tx_streams;
2221
777ad375 2222 band->ht_cap.ht_supported = 1;
341c9791
LB		 2223
2224 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 2225 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 2226 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 2227 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 2228 if (cap & MWL8K_CAP_AMPDU) {
2229 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 2230 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
2231 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 2232 }
2233 if (cap & MWL8K_CAP_RX_STBC)
777ad375 2234 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 2235 if (cap & MWL8K_CAP_TX_STBC)
777ad375 2236 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 2237 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 2238 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 2239 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 2240 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 2241 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 2242 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 2243 if (cap & MWL8K_CAP_40MHZ)
777ad375 2244 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 2245
2246 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
2247 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
2248
777ad375 2249 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 2250 if (rx_streams >= 2)
777ad375 2251 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 2252 if (rx_streams >= 3)
777ad375
LB		 2253 band->ht_cap.mcs.rx_mask[2] = 0xff;
2254 band->ht_cap.mcs.rx_mask[4] = 0x01;
2255 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 2256
2257 if (rx_streams != tx_streams) {
777ad375
LB		 2258 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
2259 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 2260 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
2261 }
2262}
2263
06953235
LB		 2264static void
2265mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
2266{
2267 struct mwl8k_priv *priv = hw->priv;
2268
2269 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
2270 mwl8k_setup_2ghz_band(hw);
2271 if (caps & MWL8K_CAP_MIMO)
2272 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
2273 }
2274
2275 if (caps & MWL8K_CAP_5GHZ) {
2276 mwl8k_setup_5ghz_band(hw);
2277 if (caps & MWL8K_CAP_MIMO)
2278 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
2279 }
2280}
2281
04b147b1 2282static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 2283{
2284 struct mwl8k_priv *priv = hw->priv;
04b147b1 2285 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 2286 int rc;
2287 int i;
2288
2289 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2290 if (cmd == NULL)
2291 return -ENOMEM;
2292
2293 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2294 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2295
2296 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2297 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 2298 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b
BC		 2299 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
2300 for (i = 0; i < mwl8k_tx_queues(priv); i++)
45eb400d 2301 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 2302 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 2303 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 2304
2305 rc = mwl8k_post_cmd(hw, &cmd->header);
2306
2307 if (!rc) {
2308 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2309 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 2310 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 2311 priv->hw_rev = cmd->hw_rev;
06953235 2312 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 2313 priv->ap_macids_supported = 0x00000000;
2314 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 2315 }
2316
2317 kfree(cmd);
2318 return rc;
2319}
2320
42fba21d
LB		 2321/*
2322 * CMD_GET_HW_SPEC (AP version).
2323 */
2324struct mwl8k_cmd_get_hw_spec_ap {
2325 struct mwl8k_cmd_pkt header;
2326 __u8 hw_rev;
2327 __u8 host_interface;
2328 __le16 num_wcb;
2329 __le16 num_mcaddrs;
2330 __u8 perm_addr[ETH_ALEN];
2331 __le16 region_code;
2332 __le16 num_antenna;
2333 __le32 fw_rev;
2334 __le32 wcbbase0;
2335 __le32 rxwrptr;
2336 __le32 rxrdptr;
2337 __le32 ps_cookie;
2338 __le32 wcbbase1;
2339 __le32 wcbbase2;
2340 __le32 wcbbase3;
952a0e96 2341 __le32 fw_api_version;
8a7a578c
BC		 2342 __le32 caps;
2343 __le32 num_of_ampdu_queues;
2344 __le32 wcbbase_ampdu[MWL8K_MAX_AMPDU_QUEUES];
ba2d3587 2345} __packed;
42fba21d
LB		 2346
2347static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
2348{
2349 struct mwl8k_priv *priv = hw->priv;
2350 struct mwl8k_cmd_get_hw_spec_ap *cmd;
8a7a578c 2351 int rc, i;
952a0e96 2352 u32 api_version;
42fba21d
LB		 2353
2354 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2355 if (cmd == NULL)
2356 return -ENOMEM;
2357
2358 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
2359 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2360
2361 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
2362 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2363
2364 rc = mwl8k_post_cmd(hw, &cmd->header);
2365
2366 if (!rc) {
2367 int off;
2368
952a0e96
BC		 2369 api_version = le32_to_cpu(cmd->fw_api_version);
2370 if (priv->device_info->fw_api_ap != api_version) {
2371 printk(KERN_ERR "%s: Unsupported fw API version for %s."
2372 " Expected %d got %d.\n", MWL8K_NAME,
2373 priv->device_info->part_name,
2374 priv->device_info->fw_api_ap,
2375 api_version);
2376 rc = -EINVAL;
2377 goto done;
2378 }
42fba21d
LB		 2379 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
2380 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
2381 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
2382 priv->hw_rev = cmd->hw_rev;
8a7a578c 2383 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 2384 priv->ap_macids_supported = 0x000000ff;
2385 priv->sta_macids_supported = 0x00000000;
8a7a578c
BC		 2386 priv->num_ampdu_queues = le32_to_cpu(cmd->num_of_ampdu_queues);
2387 if (priv->num_ampdu_queues > MWL8K_MAX_AMPDU_QUEUES) {
2388 wiphy_warn(hw->wiphy, "fw reported %d ampdu queues"
2389 " but we only support %d.\n",
2390 priv->num_ampdu_queues,
2391 MWL8K_MAX_AMPDU_QUEUES);
2392 priv->num_ampdu_queues = MWL8K_MAX_AMPDU_QUEUES;
2393 }
42fba21d 2394 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 2395 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 2396
2397 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 2398 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d 2399
73b46320
BC		 2400 priv->txq_offset[0] = le32_to_cpu(cmd->wcbbase0) & 0xffff;
2401 priv->txq_offset[1] = le32_to_cpu(cmd->wcbbase1) & 0xffff;
2402 priv->txq_offset[2] = le32_to_cpu(cmd->wcbbase2) & 0xffff;
2403 priv->txq_offset[3] = le32_to_cpu(cmd->wcbbase3) & 0xffff;
8a7a578c
BC		 2404
2405 for (i = 0; i < priv->num_ampdu_queues; i++)
e600707b 2406 priv->txq_offset[i + MWL8K_TX_WMM_QUEUES] =
8a7a578c 2407 le32_to_cpu(cmd->wcbbase_ampdu[i]) & 0xffff;
42fba21d
LB		 2408 }
2409
952a0e96 2410done:
42fba21d
LB		 2411 kfree(cmd);
2412 return rc;
2413}
2414
2415/*
2416 * CMD_SET_HW_SPEC.
2417 */
2418struct mwl8k_cmd_set_hw_spec {
2419 struct mwl8k_cmd_pkt header;
2420 __u8 hw_rev;
2421 __u8 host_interface;
2422 __le16 num_mcaddrs;
2423 __u8 perm_addr[ETH_ALEN];
2424 __le16 region_code;
2425 __le32 fw_rev;
2426 __le32 ps_cookie;
2427 __le32 caps;
2428 __le32 rx_queue_ptr;
2429 __le32 num_tx_queues;
e600707b 2430 __le32 tx_queue_ptrs[MWL8K_MAX_TX_QUEUES];
42fba21d
LB		 2431 __le32 flags;
2432 __le32 num_tx_desc_per_queue;
2433 __le32 total_rxd;
ba2d3587 2434} __packed;
42fba21d 2435
8a7a578c
BC		 2436/* If enabled, MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY will cause
2437 * packets to expire 500 ms after the timestamp in the tx descriptor. That is,
2438 * the packets that are queued for more than 500ms, will be dropped in the
2439 * hardware. This helps minimizing the issues caused due to head-of-line
2440 * blocking where a slow client can hog the bandwidth and affect traffic to a
2441 * faster client.
2442 */
2443#define MWL8K_SET_HW_SPEC_FLAG_ENABLE_LIFE_TIME_EXPIRY 0x00000400
b64fe619
LB		 2444#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
2445#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
2446#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 2447
2448static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
2449{
2450 struct mwl8k_priv *priv = hw->priv;
2451 struct mwl8k_cmd_set_hw_spec *cmd;
2452 int rc;
2453 int i;
2454
2455 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2456 if (cmd == NULL)
2457 return -ENOMEM;
2458
2459 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
2460 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2461
2462 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
2463 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
e600707b 2464 cmd->num_tx_queues = cpu_to_le32(mwl8k_tx_queues(priv));
85c9205c
NS		 2465
2466 /*
2467 * Mac80211 stack has Q0 as highest priority and Q3 as lowest in
2468 * that order. Firmware has Q3 as highest priority and Q0 as lowest
2469 * in that order. Map Q3 of mac80211 to Q0 of firmware so that the
2470 * priority is interpreted the right way in firmware.
2471 */
e600707b
BC		 2472 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
2473 int j = mwl8k_tx_queues(priv) - 1 - i;
85c9205c
NS		 2474 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[j].txd_dma);
2475 }
2476
b64fe619
LB		 2477 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
2478 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
2479 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 2480 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
2481 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
2482
2483 rc = mwl8k_post_cmd(hw, &cmd->header);
2484 kfree(cmd);
2485
2486 return rc;
2487}
2488
a66098da
LB		 2489/*
2490 * CMD_MAC_MULTICAST_ADR.
2491 */
2492struct mwl8k_cmd_mac_multicast_adr {
2493 struct mwl8k_cmd_pkt header;
2494 __le16 action;
2495 __le16 numaddr;
ce9e2e1b 2496 __u8 addr[0][ETH_ALEN];
a66098da
LB		 2497};
2498
d5e30845
LB		 2499#define MWL8K_ENABLE_RX_DIRECTED 0x0001
2500#define MWL8K_ENABLE_RX_MULTICAST 0x0002
2501#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
2502#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 2503
e81cd2d6 2504static struct mwl8k_cmd_pkt *
447ced07 2505__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 2506 struct netdev_hw_addr_list *mc_list)
a66098da 2507{
e81cd2d6 2508 struct mwl8k_priv *priv = hw->priv;
a66098da 2509 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 2510 int size;
22bedad3
JP		 2511 int mc_count = 0;
2512
2513 if (mc_list)
2514 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 2515
447ced07 2516 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 2517 allmulti = 1;
2518 mc_count = 0;
2519 }
e81cd2d6
LB		 2520
2521 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 2522
e81cd2d6 2523 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 2524 if (cmd == NULL)
e81cd2d6 2525 return NULL;
a66098da
LB		 2526
2527 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
2528 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 2529 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
2530 MWL8K_ENABLE_RX_BROADCAST);
2531
2532 if (allmulti) {
2533 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
2534 } else if (mc_count) {
22bedad3
JP		 2535 struct netdev_hw_addr *ha;
2536 int i = 0;
d5e30845
LB		 2537
2538 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
2539 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 2540 netdev_hw_addr_list_for_each(ha, mc_list) {
2541 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 2542 }
a66098da
LB		 2543 }
2544
e81cd2d6 2545 return &cmd->header;
a66098da
LB		 2546}
2547
2548/*
55489b6e 2549 * CMD_GET_STAT.
a66098da 2550 */
55489b6e 2551struct mwl8k_cmd_get_stat {
a66098da 2552 struct mwl8k_cmd_pkt header;
a66098da 2553 __le32 stats[64];
ba2d3587 2554} __packed;
a66098da
LB		 2555
2556#define MWL8K_STAT_ACK_FAILURE 9
2557#define MWL8K_STAT_RTS_FAILURE 12
2558#define MWL8K_STAT_FCS_ERROR 24
2559#define MWL8K_STAT_RTS_SUCCESS 11
2560
55489b6e
LB		 2561static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2562 struct ieee80211_low_level_stats *stats)
a66098da 2563{
55489b6e 2564 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2565 int rc;
2566
2567 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2568 if (cmd == NULL)
2569 return -ENOMEM;
2570
2571 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2572 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2573
2574 rc = mwl8k_post_cmd(hw, &cmd->header);
2575 if (!rc) {
2576 stats->dot11ACKFailureCount =
2577 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2578 stats->dot11RTSFailureCount =
2579 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2580 stats->dot11FCSErrorCount =
2581 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2582 stats->dot11RTSSuccessCount =
2583 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2584 }
2585 kfree(cmd);
2586
2587 return rc;
2588}
2589
2590/*
55489b6e 2591 * CMD_RADIO_CONTROL.
a66098da 2592 */
55489b6e 2593struct mwl8k_cmd_radio_control {
a66098da
LB		 2594 struct mwl8k_cmd_pkt header;
2595 __le16 action;
2596 __le16 control;
2597 __le16 radio_on;
ba2d3587 2598} __packed;
a66098da 2599
c46563b7 2600static int
55489b6e 2601mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2602{
2603 struct mwl8k_priv *priv = hw->priv;
55489b6e 2604 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2605 int rc;
2606
c46563b7 2607 if (enable == priv->radio_on && !force)
a66098da
LB		 2608 return 0;
2609
a66098da
LB		 2610 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2611 if (cmd == NULL)
2612 return -ENOMEM;
2613
2614 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2615 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2616 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2617 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2618 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2619
2620 rc = mwl8k_post_cmd(hw, &cmd->header);
2621 kfree(cmd);
2622
2623 if (!rc)
c46563b7 2624 priv->radio_on = enable;
a66098da
LB		 2625
2626 return rc;
2627}
2628
55489b6e 2629static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2630{
55489b6e 2631 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2632}
2633
55489b6e 2634static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2635{
55489b6e 2636 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2637}
2638
a66098da
LB		 2639static int
2640mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2641{
99200a99 2642 struct mwl8k_priv *priv = hw->priv;
a66098da 2643
68ce3884 2644 priv->radio_short_preamble = short_preamble;
a66098da 2645
55489b6e 2646 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2647}
2648
2649/*
55489b6e 2650 * CMD_RF_TX_POWER.
a66098da 2651 */
41fdf097 2652#define MWL8K_RF_TX_POWER_LEVEL_TOTAL 8
a66098da 2653
55489b6e 2654struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2655 struct mwl8k_cmd_pkt header;
2656 __le16 action;
2657 __le16 support_level;
2658 __le16 current_level;
2659 __le16 reserved;
41fdf097 2660 __le16 power_level_list[MWL8K_RF_TX_POWER_LEVEL_TOTAL];
ba2d3587 2661} __packed;
a66098da 2662
55489b6e 2663static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2664{
55489b6e 2665 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2666 int rc;
2667
2668 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2669 if (cmd == NULL)
2670 return -ENOMEM;
2671
2672 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2673 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2674 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2675 cmd->support_level = cpu_to_le16(dBm);
2676
2677 rc = mwl8k_post_cmd(hw, &cmd->header);
2678 kfree(cmd);
2679
2680 return rc;
2681}
2682
41fdf097
NS		 2683/*
2684 * CMD_TX_POWER.
2685 */
2686#define MWL8K_TX_POWER_LEVEL_TOTAL 12
2687
2688struct mwl8k_cmd_tx_power {
2689 struct mwl8k_cmd_pkt header;
2690 __le16 action;
2691 __le16 band;
2692 __le16 channel;
2693 __le16 bw;
2694 __le16 sub_ch;
2695 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
ba30c4a5 2696} __packed;
41fdf097
NS		 2697
2698static int mwl8k_cmd_tx_power(struct ieee80211_hw *hw,
2699 struct ieee80211_conf *conf,
2700 unsigned short pwr)
2701{
2702 struct ieee80211_channel *channel = conf->channel;
2703 struct mwl8k_cmd_tx_power *cmd;
2704 int rc;
2705 int i;
2706
2707 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2708 if (cmd == NULL)
2709 return -ENOMEM;
2710
2711 cmd->header.code = cpu_to_le16(MWL8K_CMD_TX_POWER);
2712 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2713 cmd->action = cpu_to_le16(MWL8K_CMD_SET_LIST);
2714
2715 if (channel->band == IEEE80211_BAND_2GHZ)
2716 cmd->band = cpu_to_le16(0x1);
2717 else if (channel->band == IEEE80211_BAND_5GHZ)
2718 cmd->band = cpu_to_le16(0x4);
2719
2720 cmd->channel = channel->hw_value;
2721
2722 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2723 conf->channel_type == NL80211_CHAN_HT20) {
2724 cmd->bw = cpu_to_le16(0x2);
2725 } else {
2726 cmd->bw = cpu_to_le16(0x4);
2727 if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2728 cmd->sub_ch = cpu_to_le16(0x3);
2729 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2730 cmd->sub_ch = cpu_to_le16(0x1);
2731 }
2732
2733 for (i = 0; i < MWL8K_TX_POWER_LEVEL_TOTAL; i++)
2734 cmd->power_level_list[i] = cpu_to_le16(pwr);
2735
2736 rc = mwl8k_post_cmd(hw, &cmd->header);
2737 kfree(cmd);
2738
2739 return rc;
2740}
2741
08b06347
LB		 2742/*
2743 * CMD_RF_ANTENNA.
2744 */
2745struct mwl8k_cmd_rf_antenna {
2746 struct mwl8k_cmd_pkt header;
2747 __le16 antenna;
2748 __le16 mode;
ba2d3587 2749} __packed;
08b06347
LB		 2750
2751#define MWL8K_RF_ANTENNA_RX 1
2752#define MWL8K_RF_ANTENNA_TX 2
2753
2754static int
2755mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2756{
2757 struct mwl8k_cmd_rf_antenna *cmd;
2758 int rc;
2759
2760 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2761 if (cmd == NULL)
2762 return -ENOMEM;
2763
2764 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2765 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2766 cmd->antenna = cpu_to_le16(antenna);
2767 cmd->mode = cpu_to_le16(mask);
2768
2769 rc = mwl8k_post_cmd(hw, &cmd->header);
2770 kfree(cmd);
2771
2772 return rc;
2773}
2774
b64fe619
LB		 2775/*
2776 * CMD_SET_BEACON.
2777 */
2778struct mwl8k_cmd_set_beacon {
2779 struct mwl8k_cmd_pkt header;
2780 __le16 beacon_len;
2781 __u8 beacon[0];
2782};
2783
aa21d0f6
LB		 2784static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2785 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2786{
2787 struct mwl8k_cmd_set_beacon *cmd;
2788 int rc;
2789
2790 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2791 if (cmd == NULL)
2792 return -ENOMEM;
2793
2794 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2795 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2796 cmd->beacon_len = cpu_to_le16(len);
2797 memcpy(cmd->beacon, beacon, len);
2798
aa21d0f6 2799 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2800 kfree(cmd);
2801
2802 return rc;
2803}
2804
a66098da
LB		 2805/*
2806 * CMD_SET_PRE_SCAN.
2807 */
2808struct mwl8k_cmd_set_pre_scan {
2809 struct mwl8k_cmd_pkt header;
ba2d3587 2810} __packed;
a66098da
LB		 2811
2812static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2813{
2814 struct mwl8k_cmd_set_pre_scan *cmd;
2815 int rc;
2816
2817 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2818 if (cmd == NULL)
2819 return -ENOMEM;
2820
2821 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2822 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2823
2824 rc = mwl8k_post_cmd(hw, &cmd->header);
2825 kfree(cmd);
2826
2827 return rc;
2828}
2829
2830/*
2831 * CMD_SET_POST_SCAN.
2832 */
2833struct mwl8k_cmd_set_post_scan {
2834 struct mwl8k_cmd_pkt header;
2835 __le32 isibss;
d89173f2 2836 __u8 bssid[ETH_ALEN];
ba2d3587 2837} __packed;
a66098da
LB		 2838
2839static int
0a11dfc3 2840mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2841{
2842 struct mwl8k_cmd_set_post_scan *cmd;
2843 int rc;
2844
2845 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2846 if (cmd == NULL)
2847 return -ENOMEM;
2848
2849 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2850 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2851 cmd->isibss = 0;
d89173f2 2852 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2853
2854 rc = mwl8k_post_cmd(hw, &cmd->header);
2855 kfree(cmd);
2856
2857 return rc;
2858}
2859
2860/*
2861 * CMD_SET_RF_CHANNEL.
2862 */
2863struct mwl8k_cmd_set_rf_channel {
2864 struct mwl8k_cmd_pkt header;
2865 __le16 action;
2866 __u8 current_channel;
2867 __le32 channel_flags;
ba2d3587 2868} __packed;
a66098da
LB		 2869
2870static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2871 struct ieee80211_conf *conf)
a66098da 2872{
610677d2 2873 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2874 struct mwl8k_cmd_set_rf_channel *cmd;
2875 int rc;
2876
2877 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2878 if (cmd == NULL)
2879 return -ENOMEM;
2880
2881 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2882 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2883 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2884 cmd->current_channel = channel->hw_value;
610677d2 2885
a66098da 2886 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 2887 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 2888 else if (channel->band == IEEE80211_BAND_5GHZ)
2889 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB		 2890
2891 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2892 conf->channel_type == NL80211_CHAN_HT20)
2893 cmd->channel_flags |= cpu_to_le32(0x00000080);
2894 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2895 cmd->channel_flags |= cpu_to_le32(0x000001900);
2896 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2897 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2898
2899 rc = mwl8k_post_cmd(hw, &cmd->header);
2900 kfree(cmd);
2901
2902 return rc;
2903}
2904
2905/*
55489b6e 2906 * CMD_SET_AID.
a66098da 2907 */
55489b6e
LB		 2908#define MWL8K_FRAME_PROT_DISABLED 0x00
2909#define MWL8K_FRAME_PROT_11G 0x07
2910#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2911#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2912
55489b6e
LB		 2913struct mwl8k_cmd_update_set_aid {
2914 struct mwl8k_cmd_pkt header;
2915 __le16 aid;
a66098da 2916
55489b6e
LB		 2917 /* AP's MAC address (BSSID) */
2918 __u8 bssid[ETH_ALEN];
2919 __le16 protection_mode;
2920 __u8 supp_rates[14];
ba2d3587 2921} __packed;
a66098da 2922
c6e96010
LB		 2923static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2924{
2925 int i;
2926 int j;
2927
2928 /*
2929 * Clear nonstandard rates 4 and 13.
2930 */
2931 mask &= 0x1fef;
2932
2933 for (i = 0, j = 0; i < 14; i++) {
2934 if (mask & (1 << i))
777ad375 2935 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 2936 }
2937}
2938
55489b6e 2939static int
c6e96010
LB		 2940mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2941 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2942{
55489b6e
LB		 2943 struct mwl8k_cmd_update_set_aid *cmd;
2944 u16 prot_mode;
a66098da
LB		 2945 int rc;
2946
2947 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2948 if (cmd == NULL)
2949 return -ENOMEM;
2950
55489b6e 2951 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2952 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2953 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2954 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2955
7dc6a7a7 2956 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2957 prot_mode = MWL8K_FRAME_PROT_11G;
2958 } else {
7dc6a7a7 2959 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2960 IEEE80211_HT_OP_MODE_PROTECTION) {
2961 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2962 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2963 break;
2964 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2965 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2966 break;
2967 default:
2968 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2969 break;
2970 }
2971 }
2972 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2973
c6e96010 2974 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2975
2976 rc = mwl8k_post_cmd(hw, &cmd->header);
2977 kfree(cmd);
2978
2979 return rc;
2980}
2981
32060e1b 2982/*
55489b6e 2983 * CMD_SET_RATE.
32060e1b 2984 */
55489b6e
LB		 2985struct mwl8k_cmd_set_rate {
2986 struct mwl8k_cmd_pkt header;
2987 __u8 legacy_rates[14];
2988
2989 /* Bitmap for supported MCS codes. */
2990 __u8 mcs_set[16];
2991 __u8 reserved[16];
ba2d3587 2992} __packed;
32060e1b 2993
55489b6e 2994static int
c6e96010 2995mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2996 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2997{
55489b6e 2998 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2999 int rc;
3000
3001 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3002 if (cmd == NULL)
3003 return -ENOMEM;
3004
55489b6e 3005 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 3006 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 3007 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 3008 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 3009
3010 rc = mwl8k_post_cmd(hw, &cmd->header);
3011 kfree(cmd);
3012
3013 return rc;
3014}
3015
a66098da 3016/*
55489b6e 3017 * CMD_FINALIZE_JOIN.
a66098da 3018 */
55489b6e
LB		 3019#define MWL8K_FJ_BEACON_MAXLEN 128
3020
3021struct mwl8k_cmd_finalize_join {
a66098da 3022 struct mwl8k_cmd_pkt header;
55489b6e
LB		 3023 __le32 sleep_interval; /* Number of beacon periods to sleep */
3024 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 3025} __packed;
a66098da 3026
55489b6e
LB		 3027static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
3028 int framelen, int dtim)
a66098da 3029{
55489b6e
LB		 3030 struct mwl8k_cmd_finalize_join *cmd;
3031 struct ieee80211_mgmt *payload = frame;
3032 int payload_len;
a66098da
LB		 3033 int rc;
3034
3035 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3036 if (cmd == NULL)
3037 return -ENOMEM;
3038
55489b6e 3039 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 3040 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3041 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
3042
3043 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
3044 if (payload_len < 0)
3045 payload_len = 0;
3046 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
3047 payload_len = MWL8K_FJ_BEACON_MAXLEN;
3048
3049 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 3050
3051 rc = mwl8k_post_cmd(hw, &cmd->header);
3052 kfree(cmd);
3053
3054 return rc;
3055}
3056
3057/*
55489b6e 3058 * CMD_SET_RTS_THRESHOLD.
a66098da 3059 */
55489b6e 3060struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 3061 struct mwl8k_cmd_pkt header;
3062 __le16 action;
55489b6e 3063 __le16 threshold;
ba2d3587 3064} __packed;
a66098da 3065
c2c2b12a
LB		 3066static int
3067mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 3068{
55489b6e 3069 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 3070 int rc;
3071
3072 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3073 if (cmd == NULL)
3074 return -ENOMEM;
3075
55489b6e 3076 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 3077 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 3078 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3079 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 3080
3081 rc = mwl8k_post_cmd(hw, &cmd->header);
3082 kfree(cmd);
3083
a66098da
LB		 3084 return rc;
3085}
3086
3087/*
55489b6e 3088 * CMD_SET_SLOT.
a66098da 3089 */
55489b6e 3090struct mwl8k_cmd_set_slot {
a66098da
LB		 3091 struct mwl8k_cmd_pkt header;
3092 __le16 action;
55489b6e 3093 __u8 short_slot;
ba2d3587 3094} __packed;
a66098da 3095
55489b6e 3096static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 3097{
55489b6e 3098 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 3099 int rc;
3100
3101 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3102 if (cmd == NULL)
3103 return -ENOMEM;
3104
55489b6e 3105 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 3106 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3107 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3108 cmd->short_slot = short_slot_time;
a66098da
LB		 3109
3110 rc = mwl8k_post_cmd(hw, &cmd->header);
3111 kfree(cmd);
3112
3113 return rc;
3114}
3115
3116/*
3117 * CMD_SET_EDCA_PARAMS.
3118 */
3119struct mwl8k_cmd_set_edca_params {
3120 struct mwl8k_cmd_pkt header;
3121
3122 /* See MWL8K_SET_EDCA_XXX below */
3123 __le16 action;
3124
3125 /* TX opportunity in units of 32 us */
3126 __le16 txop;
3127
2e484c89
LB		 3128 union {
3129 struct {
3130 /* Log exponent of max contention period: 0...15 */
3131 __le32 log_cw_max;
3132
3133 /* Log exponent of min contention period: 0...15 */
3134 __le32 log_cw_min;
3135
3136 /* Adaptive interframe spacing in units of 32us */
3137 __u8 aifs;
3138
3139 /* TX queue to configure */
3140 __u8 txq;
3141 } ap;
3142 struct {
3143 /* Log exponent of max contention period: 0...15 */
3144 __u8 log_cw_max;
a66098da 3145
2e484c89
LB		 3146 /* Log exponent of min contention period: 0...15 */
3147 __u8 log_cw_min;
a66098da 3148
2e484c89
LB		 3149 /* Adaptive interframe spacing in units of 32us */
3150 __u8 aifs;
a66098da 3151
2e484c89
LB		 3152 /* TX queue to configure */
3153 __u8 txq;
3154 } sta;
3155 };
ba2d3587 3156} __packed;
a66098da 3157
a66098da
LB		 3158#define MWL8K_SET_EDCA_CW 0x01
3159#define MWL8K_SET_EDCA_TXOP 0x02
3160#define MWL8K_SET_EDCA_AIFS 0x04
3161
3162#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
3163 MWL8K_SET_EDCA_TXOP | \
3164 MWL8K_SET_EDCA_AIFS)
3165
3166static int
55489b6e
LB		 3167mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
3168 __u16 cw_min, __u16 cw_max,
3169 __u8 aifs, __u16 txop)
a66098da 3170{
2e484c89 3171 struct mwl8k_priv *priv = hw->priv;
a66098da 3172 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 3173 int rc;
3174
3175 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3176 if (cmd == NULL)
3177 return -ENOMEM;
3178
a66098da
LB		 3179 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
3180 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 3181 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
3182 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 3183 if (priv->ap_fw) {
3184 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
3185 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
3186 cmd->ap.aifs = aifs;
3187 cmd->ap.txq = qnum;
3188 } else {
3189 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
3190 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
3191 cmd->sta.aifs = aifs;
3192 cmd->sta.txq = qnum;
3193 }
a66098da
LB		 3194
3195 rc = mwl8k_post_cmd(hw, &cmd->header);
3196 kfree(cmd);
3197
3198 return rc;
3199}
3200
3201/*
55489b6e 3202 * CMD_SET_WMM_MODE.
a66098da 3203 */
55489b6e 3204struct mwl8k_cmd_set_wmm_mode {
a66098da 3205 struct mwl8k_cmd_pkt header;
55489b6e 3206 __le16 action;
ba2d3587 3207} __packed;
a66098da 3208
55489b6e 3209static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 3210{
55489b6e
LB		 3211 struct mwl8k_priv *priv = hw->priv;
3212 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 3213 int rc;
3214
a66098da
LB		 3215 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3216 if (cmd == NULL)
3217 return -ENOMEM;
3218
55489b6e 3219 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 3220 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 3221 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 3222
3223 rc = mwl8k_post_cmd(hw, &cmd->header);
3224 kfree(cmd);
16cec43d 3225
55489b6e
LB		 3226 if (!rc)
3227 priv->wmm_enabled = enable;
a66098da
LB		 3228
3229 return rc;
3230}
3231
3232/*
55489b6e 3233 * CMD_MIMO_CONFIG.
a66098da 3234 */
55489b6e
LB		 3235struct mwl8k_cmd_mimo_config {
3236 struct mwl8k_cmd_pkt header;
3237 __le32 action;
3238 __u8 rx_antenna_map;
3239 __u8 tx_antenna_map;
ba2d3587 3240} __packed;
a66098da 3241
55489b6e 3242static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 3243{
55489b6e 3244 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 3245 int rc;
3246
3247 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3248 if (cmd == NULL)
3249 return -ENOMEM;
3250
55489b6e 3251 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 3252 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 3253 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
3254 cmd->rx_antenna_map = rx;
3255 cmd->tx_antenna_map = tx;
a66098da
LB		 3256
3257 rc = mwl8k_post_cmd(hw, &cmd->header);
3258 kfree(cmd);
3259
3260 return rc;
3261}
3262
3263/*
b71ed2c6 3264 * CMD_USE_FIXED_RATE (STA version).
a66098da 3265 */
b71ed2c6
LB		 3266struct mwl8k_cmd_use_fixed_rate_sta {
3267 struct mwl8k_cmd_pkt header;
3268 __le32 action;
3269 __le32 allow_rate_drop;
3270 __le32 num_rates;
3271 struct {
3272 __le32 is_ht_rate;
3273 __le32 enable_retry;
3274 __le32 rate;
3275 __le32 retry_count;
3276 } rate_entry[8];
3277 __le32 rate_type;
3278 __le32 reserved1;
3279 __le32 reserved2;
ba2d3587 3280} __packed;
a66098da 3281
b71ed2c6
LB		 3282#define MWL8K_USE_AUTO_RATE 0x0002
3283#define MWL8K_UCAST_RATE 0
a66098da 3284
b71ed2c6 3285static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 3286{
b71ed2c6 3287 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 3288 int rc;
3289
3290 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3291 if (cmd == NULL)
3292 return -ENOMEM;
3293
3294 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3295 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 3296 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3297 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 3298
3299 rc = mwl8k_post_cmd(hw, &cmd->header);
3300 kfree(cmd);
3301
3302 return rc;
3303}
3304
088aab8b
LB		 3305/*
3306 * CMD_USE_FIXED_RATE (AP version).
3307 */
3308struct mwl8k_cmd_use_fixed_rate_ap {
3309 struct mwl8k_cmd_pkt header;
3310 __le32 action;
3311 __le32 allow_rate_drop;
3312 __le32 num_rates;
3313 struct mwl8k_rate_entry_ap {
3314 __le32 is_ht_rate;
3315 __le32 enable_retry;
3316 __le32 rate;
3317 __le32 retry_count;
3318 } rate_entry[4];
3319 u8 multicast_rate;
3320 u8 multicast_rate_type;
3321 u8 management_rate;
ba2d3587 3322} __packed;
088aab8b
LB		 3323
3324static int
3325mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
3326{
3327 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
3328 int rc;
3329
3330 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3331 if (cmd == NULL)
3332 return -ENOMEM;
3333
3334 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
3335 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3336 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
3337 cmd->multicast_rate = mcast;
3338 cmd->management_rate = mgmt;
3339
3340 rc = mwl8k_post_cmd(hw, &cmd->header);
3341 kfree(cmd);
3342
3343 return rc;
3344}
3345
55489b6e
LB		 3346/*
3347 * CMD_ENABLE_SNIFFER.
3348 */
3349struct mwl8k_cmd_enable_sniffer {
3350 struct mwl8k_cmd_pkt header;
3351 __le32 action;
ba2d3587 3352} __packed;
55489b6e
LB		 3353
3354static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
3355{
3356 struct mwl8k_cmd_enable_sniffer *cmd;
3357 int rc;
3358
3359 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3360 if (cmd == NULL)
3361 return -ENOMEM;
3362
3363 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
3364 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3365 cmd->action = cpu_to_le32(!!enable);
3366
3367 rc = mwl8k_post_cmd(hw, &cmd->header);
3368 kfree(cmd);
3369
3370 return rc;
3371}
3372
3373/*
3374 * CMD_SET_MAC_ADDR.
3375 */
3376struct mwl8k_cmd_set_mac_addr {
3377 struct mwl8k_cmd_pkt header;
3378 union {
3379 struct {
3380 __le16 mac_type;
3381 __u8 mac_addr[ETH_ALEN];
3382 } mbss;
3383 __u8 mac_addr[ETH_ALEN];
3384 };
ba2d3587 3385} __packed;
55489b6e 3386
ee0ddf18
LB		 3387#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
3388#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
3389#define MWL8K_MAC_TYPE_PRIMARY_AP 2
3390#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 3391
aa21d0f6
LB		 3392static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
3393 struct ieee80211_vif *vif, u8 *mac)
55489b6e
LB		 3394{
3395 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 3396 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
55489b6e 3397 struct mwl8k_cmd_set_mac_addr *cmd;
ee0ddf18 3398 int mac_type;
55489b6e
LB		 3399 int rc;
3400
ee0ddf18
LB		 3401 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3402 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
3403 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
3404 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
3405 else
3406 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
3407 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
3408 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
3409 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
3410 else
3411 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
3412 }
3413
55489b6e
LB		 3414 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3415 if (cmd == NULL)
3416 return -ENOMEM;
3417
3418 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
3419 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3420 if (priv->ap_fw) {
ee0ddf18 3421 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 3422 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
3423 } else {
3424 memcpy(cmd->mac_addr, mac, ETH_ALEN);
3425 }
3426
aa21d0f6 3427 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 3428 kfree(cmd);
3429
3430 return rc;
3431}
3432
3433/*
3434 * CMD_SET_RATEADAPT_MODE.
3435 */
3436struct mwl8k_cmd_set_rate_adapt_mode {
3437 struct mwl8k_cmd_pkt header;
3438 __le16 action;
3439 __le16 mode;
ba2d3587 3440} __packed;
55489b6e
LB		 3441
3442static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
3443{
3444 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
3445 int rc;
3446
3447 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3448 if (cmd == NULL)
3449 return -ENOMEM;
3450
3451 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
3452 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3453 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
3454 cmd->mode = cpu_to_le16(mode);
3455
3456 rc = mwl8k_post_cmd(hw, &cmd->header);
3457 kfree(cmd);
3458
3459 return rc;
3460}
3461
3aefc37e
NS		 3462/*
3463 * CMD_GET_WATCHDOG_BITMAP.
3464 */
3465struct mwl8k_cmd_get_watchdog_bitmap {
3466 struct mwl8k_cmd_pkt header;
3467 u8 bitmap;
3468} __packed;
3469
3470static int mwl8k_cmd_get_watchdog_bitmap(struct ieee80211_hw *hw, u8 *bitmap)
3471{
3472 struct mwl8k_cmd_get_watchdog_bitmap *cmd;
3473 int rc;
3474
3475 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3476 if (cmd == NULL)
3477 return -ENOMEM;
3478
3479 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_WATCHDOG_BITMAP);
3480 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3481
3482 rc = mwl8k_post_cmd(hw, &cmd->header);
3483 if (!rc)
3484 *bitmap = cmd->bitmap;
3485
3486 kfree(cmd);
3487
3488 return rc;
3489}
3490
3491#define INVALID_BA 0xAA
3492static void mwl8k_watchdog_ba_events(struct work_struct *work)
3493{
3494 int rc;
3495 u8 bitmap = 0, stream_index;
3496 struct mwl8k_ampdu_stream *streams;
3497 struct mwl8k_priv *priv =
3498 container_of(work, struct mwl8k_priv, watchdog_ba_handle);
3499
3500 rc = mwl8k_cmd_get_watchdog_bitmap(priv->hw, &bitmap);
3501 if (rc)
3502 return;
3503
3504 if (bitmap == INVALID_BA)
3505 return;
3506
3507 /* the bitmap is the hw queue number. Map it to the ampdu queue. */
3508 stream_index = bitmap - MWL8K_TX_WMM_QUEUES;
3509
3510 BUG_ON(stream_index >= priv->num_ampdu_queues);
3511
3512 streams = &priv->ampdu[stream_index];
3513
3514 if (streams->state == AMPDU_STREAM_ACTIVE)
3515 ieee80211_stop_tx_ba_session(streams->sta, streams->tid);
3516
3517 return;
3518}
3519
3520
b64fe619
LB		 3521/*
3522 * CMD_BSS_START.
3523 */
3524struct mwl8k_cmd_bss_start {
3525 struct mwl8k_cmd_pkt header;
3526 __le32 enable;
ba2d3587 3527} __packed;
b64fe619 3528
aa21d0f6
LB		 3529static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
3530 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 3531{
3532 struct mwl8k_cmd_bss_start *cmd;
3533 int rc;
3534
3535 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3536 if (cmd == NULL)
3537 return -ENOMEM;
3538
3539 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
3540 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3541 cmd->enable = cpu_to_le32(enable);
3542
aa21d0f6 3543 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3544 kfree(cmd);
3545
3546 return rc;
3547}
3548
5faa1aff
NS		 3549/*
3550 * CMD_BASTREAM.
3551 */
3552
3553/*
3554 * UPSTREAM is tx direction
3555 */
3556#define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00
3557#define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01
3558
ba30c4a5 3559enum ba_stream_action_type {
5faa1aff
NS		 3560 MWL8K_BA_CREATE,
3561 MWL8K_BA_UPDATE,
3562 MWL8K_BA_DESTROY,
3563 MWL8K_BA_FLUSH,
3564 MWL8K_BA_CHECK,
ba30c4a5 3565};
5faa1aff
NS		 3566
3567
3568struct mwl8k_create_ba_stream {
3569 __le32 flags;
3570 __le32 idle_thrs;
3571 __le32 bar_thrs;
3572 __le32 window_size;
3573 u8 peer_mac_addr[6];
3574 u8 dialog_token;
3575 u8 tid;
3576 u8 queue_id;
3577 u8 param_info;
3578 __le32 ba_context;
3579 u8 reset_seq_no_flag;
3580 __le16 curr_seq_no;
3581 u8 sta_src_mac_addr[6];
3582} __packed;
3583
3584struct mwl8k_destroy_ba_stream {
3585 __le32 flags;
3586 __le32 ba_context;
3587} __packed;
3588
3589struct mwl8k_cmd_bastream {
3590 struct mwl8k_cmd_pkt header;
3591 __le32 action;
3592 union {
3593 struct mwl8k_create_ba_stream create_params;
3594 struct mwl8k_destroy_ba_stream destroy_params;
3595 };
3596} __packed;
3597
3598static int
3599mwl8k_check_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream)
3600{
3601 struct mwl8k_cmd_bastream *cmd;
3602 int rc;
3603
3604 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3605 if (cmd == NULL)
3606 return -ENOMEM;
3607
3608 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3609 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3610
3611 cmd->action = cpu_to_le32(MWL8K_BA_CHECK);
3612
3613 cmd->create_params.queue_id = stream->idx;
3614 memcpy(&cmd->create_params.peer_mac_addr[0], stream->sta->addr,
3615 ETH_ALEN);
3616 cmd->create_params.tid = stream->tid;
3617
3618 cmd->create_params.flags =
3619 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE) |
3620 cpu_to_le32(BASTREAM_FLAG_DIRECTION_UPSTREAM);
3621
3622 rc = mwl8k_post_cmd(hw, &cmd->header);
3623
3624 kfree(cmd);
3625
3626 return rc;
3627}
3628
3629static int
3630mwl8k_create_ba(struct ieee80211_hw *hw, struct mwl8k_ampdu_stream *stream,
3631 u8 buf_size)
3632{
3633 struct mwl8k_cmd_bastream *cmd;
3634 int rc;
3635
3636 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3637 if (cmd == NULL)
3638 return -ENOMEM;
3639
3640
3641 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3642 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3643
3644 cmd->action = cpu_to_le32(MWL8K_BA_CREATE);
3645
3646 cmd->create_params.bar_thrs = cpu_to_le32((u32)buf_size);
3647 cmd->create_params.window_size = cpu_to_le32((u32)buf_size);
3648 cmd->create_params.queue_id = stream->idx;
3649
3650 memcpy(cmd->create_params.peer_mac_addr, stream->sta->addr, ETH_ALEN);
3651 cmd->create_params.tid = stream->tid;
3652 cmd->create_params.curr_seq_no = cpu_to_le16(0);
3653 cmd->create_params.reset_seq_no_flag = 1;
3654
3655 cmd->create_params.param_info =
3656 (stream->sta->ht_cap.ampdu_factor &
3657 IEEE80211_HT_AMPDU_PARM_FACTOR) |
3658 ((stream->sta->ht_cap.ampdu_density << 2) &
3659 IEEE80211_HT_AMPDU_PARM_DENSITY);
3660
3661 cmd->create_params.flags =
3662 cpu_to_le32(BASTREAM_FLAG_IMMEDIATE_TYPE |
3663 BASTREAM_FLAG_DIRECTION_UPSTREAM);
3664
3665 rc = mwl8k_post_cmd(hw, &cmd->header);
3666
3667 wiphy_debug(hw->wiphy, "Created a BA stream for %pM : tid %d\n",
3668 stream->sta->addr, stream->tid);
3669 kfree(cmd);
3670
3671 return rc;
3672}
3673
3674static void mwl8k_destroy_ba(struct ieee80211_hw *hw,
3675 struct mwl8k_ampdu_stream *stream)
3676{
3677 struct mwl8k_cmd_bastream *cmd;
3678
3679 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3680 if (cmd == NULL)
3681 return;
3682
3683 cmd->header.code = cpu_to_le16(MWL8K_CMD_BASTREAM);
3684 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3685 cmd->action = cpu_to_le32(MWL8K_BA_DESTROY);
3686
3687 cmd->destroy_params.ba_context = cpu_to_le32(stream->idx);
3688 mwl8k_post_cmd(hw, &cmd->header);
3689
3690 wiphy_debug(hw->wiphy, "Deleted BA stream index %d\n", stream->idx);
3691
3692 kfree(cmd);
3693}
3694
3f5610ff
LB		 3695/*
3696 * CMD_SET_NEW_STN.
3697 */
3698struct mwl8k_cmd_set_new_stn {
3699 struct mwl8k_cmd_pkt header;
3700 __le16 aid;
3701 __u8 mac_addr[6];
3702 __le16 stn_id;
3703 __le16 action;
3704 __le16 rsvd;
3705 __le32 legacy_rates;
3706 __u8 ht_rates[4];
3707 __le16 cap_info;
3708 __le16 ht_capabilities_info;
3709 __u8 mac_ht_param_info;
3710 __u8 rev;
3711 __u8 control_channel;
3712 __u8 add_channel;
3713 __le16 op_mode;
3714 __le16 stbc;
3715 __u8 add_qos_info;
3716 __u8 is_qos_sta;
3717 __le32 fw_sta_ptr;
ba2d3587 3718} __packed;
3f5610ff
LB		 3719
3720#define MWL8K_STA_ACTION_ADD 0
3721#define MWL8K_STA_ACTION_REMOVE 2
3722
3723static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
3724 struct ieee80211_vif *vif,
3725 struct ieee80211_sta *sta)
3726{
3727 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 3728 u32 rates;
3f5610ff
LB		 3729 int rc;
3730
3731 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3732 if (cmd == NULL)
3733 return -ENOMEM;
3734
3735 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3736 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3737 cmd->aid = cpu_to_le16(sta->aid);
3738 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
3739 cmd->stn_id = cpu_to_le16(sta->aid);
3740 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 3741 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3742 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3743 else
3744 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3745 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 3746 if (sta->ht_cap.ht_supported) {
3747 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
3748 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
3749 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
3750 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
3751 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
3752 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
3753 ((sta->ht_cap.ampdu_density & 7) << 2);
3754 cmd->is_qos_sta = 1;
3755 }
3756
aa21d0f6 3757 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3758 kfree(cmd);
3759
3760 return rc;
3761}
3762
b64fe619
LB		 3763static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
3764 struct ieee80211_vif *vif)
3765{
3766 struct mwl8k_cmd_set_new_stn *cmd;
3767 int rc;
3768
3769 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3770 if (cmd == NULL)
3771 return -ENOMEM;
3772
3773 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3774 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3775 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
3776
aa21d0f6 3777 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 3778 kfree(cmd);
3779
3780 return rc;
3781}
3782
3f5610ff
LB		 3783static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
3784 struct ieee80211_vif *vif, u8 *addr)
3785{
3786 struct mwl8k_cmd_set_new_stn *cmd;
3787 int rc;
3788
3789 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3790 if (cmd == NULL)
3791 return -ENOMEM;
3792
3793 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
3794 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3795 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3796 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
3797
aa21d0f6 3798 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 3799 kfree(cmd);
3800
3801 return rc;
3802}
3803
fcdc403c
NS		 3804/*
3805 * CMD_UPDATE_ENCRYPTION.
3806 */
3807
3808#define MAX_ENCR_KEY_LENGTH 16
3809#define MIC_KEY_LENGTH 8
3810
3811struct mwl8k_cmd_update_encryption {
3812 struct mwl8k_cmd_pkt header;
3813
3814 __le32 action;
3815 __le32 reserved;
3816 __u8 mac_addr[6];
3817 __u8 encr_type;
3818
ba30c4a5 3819} __packed;
fcdc403c
NS		 3820
3821struct mwl8k_cmd_set_key {
3822 struct mwl8k_cmd_pkt header;
3823
3824 __le32 action;
3825 __le32 reserved;
3826 __le16 length;
3827 __le16 key_type_id;
3828 __le32 key_info;
3829 __le32 key_id;
3830 __le16 key_len;
3831 __u8 key_material[MAX_ENCR_KEY_LENGTH];
3832 __u8 tkip_tx_mic_key[MIC_KEY_LENGTH];
3833 __u8 tkip_rx_mic_key[MIC_KEY_LENGTH];
3834 __le16 tkip_rsc_low;
3835 __le32 tkip_rsc_high;
3836 __le16 tkip_tsc_low;
3837 __le32 tkip_tsc_high;
3838 __u8 mac_addr[6];
ba30c4a5 3839} __packed;
fcdc403c
NS		 3840
3841enum {
3842 MWL8K_ENCR_ENABLE,
3843 MWL8K_ENCR_SET_KEY,
3844 MWL8K_ENCR_REMOVE_KEY,
3845 MWL8K_ENCR_SET_GROUP_KEY,
3846};
3847
3848#define MWL8K_UPDATE_ENCRYPTION_TYPE_WEP 0
3849#define MWL8K_UPDATE_ENCRYPTION_TYPE_DISABLE 1
3850#define MWL8K_UPDATE_ENCRYPTION_TYPE_TKIP 4
3851#define MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED 7
3852#define MWL8K_UPDATE_ENCRYPTION_TYPE_AES 8
3853
3854enum {
3855 MWL8K_ALG_WEP,
3856 MWL8K_ALG_TKIP,
3857 MWL8K_ALG_CCMP,
3858};
3859
3860#define MWL8K_KEY_FLAG_TXGROUPKEY 0x00000004
3861#define MWL8K_KEY_FLAG_PAIRWISE 0x00000008
3862#define MWL8K_KEY_FLAG_TSC_VALID 0x00000040
3863#define MWL8K_KEY_FLAG_WEP_TXKEY 0x01000000
3864#define MWL8K_KEY_FLAG_MICKEY_VALID 0x02000000
3865
3866static int mwl8k_cmd_update_encryption_enable(struct ieee80211_hw *hw,
3867 struct ieee80211_vif *vif,
3868 u8 *addr,
3869 u8 encr_type)
3870{
3871 struct mwl8k_cmd_update_encryption *cmd;
3872 int rc;
3873
3874 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3875 if (cmd == NULL)
3876 return -ENOMEM;
3877
3878 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
3879 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3880 cmd->action = cpu_to_le32(MWL8K_ENCR_ENABLE);
3881 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3882 cmd->encr_type = encr_type;
3883
3884 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3885 kfree(cmd);
3886
3887 return rc;
3888}
3889
3890static int mwl8k_encryption_set_cmd_info(struct mwl8k_cmd_set_key *cmd,
3891 u8 *addr,
3892 struct ieee80211_key_conf *key)
3893{
3894 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_ENCRYPTION);
3895 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3896 cmd->length = cpu_to_le16(sizeof(*cmd) -
3897 offsetof(struct mwl8k_cmd_set_key, length));
3898 cmd->key_id = cpu_to_le32(key->keyidx);
3899 cmd->key_len = cpu_to_le16(key->keylen);
3900 memcpy(cmd->mac_addr, addr, ETH_ALEN);
3901
3902 switch (key->cipher) {
3903 case WLAN_CIPHER_SUITE_WEP40:
3904 case WLAN_CIPHER_SUITE_WEP104:
3905 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_WEP);
3906 if (key->keyidx == 0)
3907 cmd->key_info = cpu_to_le32(MWL8K_KEY_FLAG_WEP_TXKEY);
3908
3909 break;
3910 case WLAN_CIPHER_SUITE_TKIP:
3911 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_TKIP);
3912 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3913 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
3914 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
3915 cmd->key_info |= cpu_to_le32(MWL8K_KEY_FLAG_MICKEY_VALID
3916 | MWL8K_KEY_FLAG_TSC_VALID);
3917 break;
3918 case WLAN_CIPHER_SUITE_CCMP:
3919 cmd->key_type_id = cpu_to_le16(MWL8K_ALG_CCMP);
3920 cmd->key_info = (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3921 ? cpu_to_le32(MWL8K_KEY_FLAG_PAIRWISE)
3922 : cpu_to_le32(MWL8K_KEY_FLAG_TXGROUPKEY);
3923 break;
3924 default:
3925 return -ENOTSUPP;
3926 }
3927
3928 return 0;
3929}
3930
3931static int mwl8k_cmd_encryption_set_key(struct ieee80211_hw *hw,
3932 struct ieee80211_vif *vif,
3933 u8 *addr,
3934 struct ieee80211_key_conf *key)
3935{
3936 struct mwl8k_cmd_set_key *cmd;
3937 int rc;
3938 int keymlen;
3939 u32 action;
3940 u8 idx;
3941 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3942
3943 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3944 if (cmd == NULL)
3945 return -ENOMEM;
3946
3947 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
3948 if (rc < 0)
3949 goto done;
3950
3951 idx = key->keyidx;
3952
3953 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE)
3954 action = MWL8K_ENCR_SET_KEY;
3955 else
3956 action = MWL8K_ENCR_SET_GROUP_KEY;
3957
3958 switch (key->cipher) {
3959 case WLAN_CIPHER_SUITE_WEP40:
3960 case WLAN_CIPHER_SUITE_WEP104:
3961 if (!mwl8k_vif->wep_key_conf[idx].enabled) {
3962 memcpy(mwl8k_vif->wep_key_conf[idx].key, key,
3963 sizeof(*key) + key->keylen);
3964 mwl8k_vif->wep_key_conf[idx].enabled = 1;
3965 }
3966
3967 keymlen = 0;
3968 action = MWL8K_ENCR_SET_KEY;
3969 break;
3970 case WLAN_CIPHER_SUITE_TKIP:
3971 keymlen = MAX_ENCR_KEY_LENGTH + 2 * MIC_KEY_LENGTH;
3972 break;
3973 case WLAN_CIPHER_SUITE_CCMP:
3974 keymlen = key->keylen;
3975 break;
3976 default:
3977 rc = -ENOTSUPP;
3978 goto done;
3979 }
3980
3981 memcpy(cmd->key_material, key->key, keymlen);
3982 cmd->action = cpu_to_le32(action);
3983
3984 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3985done:
3986 kfree(cmd);
3987
3988 return rc;
3989}
3990
3991static int mwl8k_cmd_encryption_remove_key(struct ieee80211_hw *hw,
3992 struct ieee80211_vif *vif,
3993 u8 *addr,
3994 struct ieee80211_key_conf *key)
3995{
3996 struct mwl8k_cmd_set_key *cmd;
3997 int rc;
3998 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3999
4000 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4001 if (cmd == NULL)
4002 return -ENOMEM;
4003
4004 rc = mwl8k_encryption_set_cmd_info(cmd, addr, key);
4005 if (rc < 0)
4006 goto done;
4007
4008 if (key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
4009 WLAN_CIPHER_SUITE_WEP104)
4010 mwl8k_vif->wep_key_conf[key->keyidx].enabled = 0;
4011
4012 cmd->action = cpu_to_le32(MWL8K_ENCR_REMOVE_KEY);
4013
4014 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
4015done:
4016 kfree(cmd);
4017
4018 return rc;
4019}
4020
4021static int mwl8k_set_key(struct ieee80211_hw *hw,
4022 enum set_key_cmd cmd_param,
4023 struct ieee80211_vif *vif,
4024 struct ieee80211_sta *sta,
4025 struct ieee80211_key_conf *key)
4026{
4027 int rc = 0;
4028 u8 encr_type;
4029 u8 *addr;
4030 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4031
4032 if (vif->type == NL80211_IFTYPE_STATION)
4033 return -EOPNOTSUPP;
4034
4035 if (sta == NULL)
4036 addr = hw->wiphy->perm_addr;
4037 else
4038 addr = sta->addr;
4039
4040 if (cmd_param == SET_KEY) {
4041 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
4042 rc = mwl8k_cmd_encryption_set_key(hw, vif, addr, key);
4043 if (rc)
4044 goto out;
4045
4046 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40)
4047 || (key->cipher == WLAN_CIPHER_SUITE_WEP104))
4048 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_WEP;
4049 else
4050 encr_type = MWL8K_UPDATE_ENCRYPTION_TYPE_MIXED;
4051
4052 rc = mwl8k_cmd_update_encryption_enable(hw, vif, addr,
4053 encr_type);
4054 if (rc)
4055 goto out;
4056
4057 mwl8k_vif->is_hw_crypto_enabled = true;
4058
4059 } else {
4060 rc = mwl8k_cmd_encryption_remove_key(hw, vif, addr, key);
4061
4062 if (rc)
4063 goto out;
4064
4065 mwl8k_vif->is_hw_crypto_enabled = false;
4066
4067 }
4068out:
4069 return rc;
4070}
4071
55489b6e
LB		 4072/*
4073 * CMD_UPDATE_STADB.
4074 */
25d81b1e
LB		 4075struct ewc_ht_info {
4076 __le16 control1;
4077 __le16 control2;
4078 __le16 control3;
ba2d3587 4079} __packed;
25d81b1e
LB		 4080
4081struct peer_capability_info {
4082 /* Peer type - AP vs. STA. */
4083 __u8 peer_type;
4084
4085 /* Basic 802.11 capabilities from assoc resp. */
4086 __le16 basic_caps;
4087
4088 /* Set if peer supports 802.11n high throughput (HT). */
4089 __u8 ht_support;
4090
4091 /* Valid if HT is supported. */
4092 __le16 ht_caps;
4093 __u8 extended_ht_caps;
4094 struct ewc_ht_info ewc_info;
4095
4096 /* Legacy rate table. Intersection of our rates and peer rates. */
4097 __u8 legacy_rates[12];
4098
4099 /* HT rate table. Intersection of our rates and peer rates. */
4100 __u8 ht_rates[16];
4101 __u8 pad[16];
4102
4103 /* If set, interoperability mode, no proprietary extensions. */
4104 __u8 interop;
4105 __u8 pad2;
4106 __u8 station_id;
4107 __le16 amsdu_enabled;
ba2d3587 4108} __packed;
25d81b1e 4109
55489b6e
LB		 4110struct mwl8k_cmd_update_stadb {
4111 struct mwl8k_cmd_pkt header;
4112
4113 /* See STADB_ACTION_TYPE */
4114 __le32 action;
4115
4116 /* Peer MAC address */
4117 __u8 peer_addr[ETH_ALEN];
4118
4119 __le32 reserved;
4120
4121 /* Peer info - valid during add/update. */
4122 struct peer_capability_info peer_info;
ba2d3587 4123} __packed;
55489b6e 4124
a680400e
LB		 4125#define MWL8K_STA_DB_MODIFY_ENTRY 1
4126#define MWL8K_STA_DB_DEL_ENTRY 2
4127
4128/* Peer Entry flags - used to define the type of the peer node */
4129#define MWL8K_PEER_TYPE_ACCESSPOINT 2
4130
4131static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 4132 struct ieee80211_vif *vif,
13935e2c 4133 struct ieee80211_sta *sta)
55489b6e 4134{
55489b6e 4135 struct mwl8k_cmd_update_stadb *cmd;
a680400e 4136 struct peer_capability_info *p;
8707d026 4137 u32 rates;
55489b6e
LB		 4138 int rc;
4139
4140 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4141 if (cmd == NULL)
4142 return -ENOMEM;
4143
4144 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4145 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 4146 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 4147 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 4148
a680400e
LB		 4149 p = &cmd->peer_info;
4150 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
4151 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 4152 p->ht_support = sta->ht_cap.ht_supported;
b603742f 4153 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 4154 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
4155 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 4156 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4157 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
4158 else
4159 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4160 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 4161 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 4162 p->interop = 1;
4163 p->amsdu_enabled = 0;
4164
4165 rc = mwl8k_post_cmd(hw, &cmd->header);
4166 kfree(cmd);
4167
4168 return rc ? rc : p->station_id;
4169}
4170
4171static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
4172 struct ieee80211_vif *vif, u8 *addr)
4173{
4174 struct mwl8k_cmd_update_stadb *cmd;
4175 int rc;
4176
4177 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
4178 if (cmd == NULL)
4179 return -ENOMEM;
4180
4181 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
4182 cmd->header.length = cpu_to_le16(sizeof(*cmd));
4183 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 4184 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 4185
a680400e 4186 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 4187 kfree(cmd);
4188
4189 return rc;
4190}
4191
a66098da
LB		 4192
4193/*
4194 * Interrupt handling.
4195 */
4196static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
4197{
4198 struct ieee80211_hw *hw = dev_id;
4199 struct mwl8k_priv *priv = hw->priv;
4200 u32 status;
4201
4202 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 4203 if (!status)
4204 return IRQ_NONE;
4205
1e9f9de3
LB		 4206 if (status & MWL8K_A2H_INT_TX_DONE) {
4207 status &= ~MWL8K_A2H_INT_TX_DONE;
4208 tasklet_schedule(&priv->poll_tx_task);
4209 }
4210
a66098da 4211 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 4212 status &= ~MWL8K_A2H_INT_RX_READY;
4213 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 4214 }
4215
3aefc37e
NS		 4216 if (status & MWL8K_A2H_INT_BA_WATCHDOG) {
4217 status &= ~MWL8K_A2H_INT_BA_WATCHDOG;
4218 ieee80211_queue_work(hw, &priv->watchdog_ba_handle);
4219 }
4220
67e2eb27
LB		 4221 if (status)
4222 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4223
a66098da 4224 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 4225 if (priv->hostcmd_wait != NULL)
a66098da 4226 complete(priv->hostcmd_wait);
a66098da
LB		 4227 }
4228
4229 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 4230 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 4231 priv->radio_on && priv->pending_tx_pkts)
618952a7 4232 mwl8k_tx_start(priv);
a66098da
LB		 4233 }
4234
4235 return IRQ_HANDLED;
4236}
4237
1e9f9de3
LB		 4238static void mwl8k_tx_poll(unsigned long data)
4239{
4240 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4241 struct mwl8k_priv *priv = hw->priv;
4242 int limit;
4243 int i;
4244
4245 limit = 32;
4246
4247 spin_lock_bh(&priv->tx_lock);
4248
e600707b 4249 for (i = 0; i < mwl8k_tx_queues(priv); i++)
1e9f9de3
LB		 4250 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
4251
4252 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
4253 complete(priv->tx_wait);
4254 priv->tx_wait = NULL;
4255 }
4256
4257 spin_unlock_bh(&priv->tx_lock);
4258
4259 if (limit) {
4260 writel(~MWL8K_A2H_INT_TX_DONE,
4261 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4262 } else {
4263 tasklet_schedule(&priv->poll_tx_task);
4264 }
4265}
4266
67e2eb27
LB		 4267static void mwl8k_rx_poll(unsigned long data)
4268{
4269 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
4270 struct mwl8k_priv *priv = hw->priv;
4271 int limit;
4272
4273 limit = 32;
4274 limit -= rxq_process(hw, 0, limit);
4275 limit -= rxq_refill(hw, 0, limit);
4276
4277 if (limit) {
4278 writel(~MWL8K_A2H_INT_RX_READY,
4279 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
4280 } else {
4281 tasklet_schedule(&priv->poll_rx_task);
4282 }
4283}
4284
a66098da
LB		 4285
4286/*
4287 * Core driver operations.
4288 */
7bb45683 4289static void mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
a66098da
LB		 4290{
4291 struct mwl8k_priv *priv = hw->priv;
4292 int index = skb_get_queue_mapping(skb);
a66098da 4293
9189c100 4294 if (!priv->radio_on) {
c96c31e4
JP		 4295 wiphy_debug(hw->wiphy,
4296 "dropped TX frame since radio disabled\n");
a66098da 4297 dev_kfree_skb(skb);
7bb45683 4298 return;
a66098da
LB		 4299 }
4300
7bb45683 4301 mwl8k_txq_xmit(hw, index, skb);
a66098da
LB		 4302}
4303
a66098da
LB		 4304static int mwl8k_start(struct ieee80211_hw *hw)
4305{
a66098da
LB		 4306 struct mwl8k_priv *priv = hw->priv;
4307 int rc;
4308
a0607fd3 4309 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4310 IRQF_SHARED, MWL8K_NAME, hw);
4311 if (rc) {
bf3ca7f7 4312 priv->irq = -1;
5db55844 4313 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 4314 return -EIO;
a66098da 4315 }
bf3ca7f7 4316 priv->irq = priv->pdev->irq;
a66098da 4317
67e2eb27 4318 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 4319 tasklet_enable(&priv->poll_tx_task);
67e2eb27 4320 tasklet_enable(&priv->poll_rx_task);
2ec610cb 4321
a66098da 4322 /* Enable interrupts */
c23b5a69 4323 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
12488e01
NS		 4324 iowrite32(MWL8K_A2H_EVENTS,
4325 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 4326
2ec610cb
LB		 4327 rc = mwl8k_fw_lock(hw);
4328 if (!rc) {
55489b6e 4329 rc = mwl8k_cmd_radio_enable(hw);
a66098da 4330
5e4cf166
LB		 4331 if (!priv->ap_fw) {
4332 if (!rc)
55489b6e 4333 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 4334
5e4cf166
LB		 4335 if (!rc)
4336 rc = mwl8k_cmd_set_pre_scan(hw);
4337
4338 if (!rc)
4339 rc = mwl8k_cmd_set_post_scan(hw,
4340 "\x00\x00\x00\x00\x00\x00");
4341 }
2ec610cb
LB		 4342
4343 if (!rc)
55489b6e 4344 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 4345
2ec610cb 4346 if (!rc)
55489b6e 4347 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 4348
2ec610cb
LB		 4349 mwl8k_fw_unlock(hw);
4350 }
4351
4352 if (rc) {
4353 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
4354 free_irq(priv->pdev->irq, hw);
bf3ca7f7 4355 priv->irq = -1;
1e9f9de3 4356 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4357 tasklet_disable(&priv->poll_rx_task);
2ec610cb 4358 }
a66098da
LB		 4359
4360 return rc;
4361}
4362
a66098da
LB		 4363static void mwl8k_stop(struct ieee80211_hw *hw)
4364{
a66098da
LB		 4365 struct mwl8k_priv *priv = hw->priv;
4366 int i;
4367
55489b6e 4368 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 4369
4370 ieee80211_stop_queues(hw);
4371
a66098da 4372 /* Disable interrupts */
a66098da 4373 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
bf3ca7f7
BC		 4374 if (priv->irq != -1) {
4375 free_irq(priv->pdev->irq, hw);
4376 priv->irq = -1;
4377 }
a66098da
LB		 4378
4379 /* Stop finalize join worker */
4380 cancel_work_sync(&priv->finalize_join_worker);
3aefc37e 4381 cancel_work_sync(&priv->watchdog_ba_handle);
a66098da
LB		 4382 if (priv->beacon_skb != NULL)
4383 dev_kfree_skb(priv->beacon_skb);
4384
67e2eb27 4385 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 4386 tasklet_disable(&priv->poll_tx_task);
67e2eb27 4387 tasklet_disable(&priv->poll_rx_task);
a66098da 4388
a66098da 4389 /* Return all skbs to mac80211 */
e600707b 4390 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 4391 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 4392}
4393
0863ade8
BC		 4394static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image);
4395
a66098da 4396static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 4397 struct ieee80211_vif *vif)
a66098da
LB		 4398{
4399 struct mwl8k_priv *priv = hw->priv;
4400 struct mwl8k_vif *mwl8k_vif;
ee0ddf18 4401 u32 macids_supported;
0863ade8
BC		 4402 int macid, rc;
4403 struct mwl8k_device_info *di;
a66098da 4404
a43c49a8
LB		 4405 /*
4406 * Reject interface creation if sniffer mode is active, as
4407 * STA operation is mutually exclusive with hardware sniffer
b64fe619 4408 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 4409 */
4410 if (priv->sniffer_enabled) {
c96c31e4
JP		 4411 wiphy_info(hw->wiphy,
4412 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 4413 return -EINVAL;
4414 }
4415
0863ade8 4416 di = priv->device_info;
ee0ddf18
LB		 4417 switch (vif->type) {
4418 case NL80211_IFTYPE_AP:
0863ade8
BC		 4419 if (!priv->ap_fw && di->fw_image_ap) {
4420 /* we must load the ap fw to meet this request */
4421 if (!list_empty(&priv->vif_list))
4422 return -EBUSY;
4423 rc = mwl8k_reload_firmware(hw, di->fw_image_ap);
4424 if (rc)
4425 return rc;
4426 }
ee0ddf18
LB		 4427 macids_supported = priv->ap_macids_supported;
4428 break;
4429 case NL80211_IFTYPE_STATION:
0863ade8
BC		 4430 if (priv->ap_fw && di->fw_image_sta) {
4431 /* we must load the sta fw to meet this request */
4432 if (!list_empty(&priv->vif_list))
4433 return -EBUSY;
4434 rc = mwl8k_reload_firmware(hw, di->fw_image_sta);
4435 if (rc)
4436 return rc;
4437 }
ee0ddf18
LB		 4438 macids_supported = priv->sta_macids_supported;
4439 break;
4440 default:
4441 return -EINVAL;
4442 }
4443
4444 macid = ffs(macids_supported & ~priv->macids_used);
4445 if (!macid--)
4446 return -EBUSY;
4447
f5bb87cf 4448 /* Setup driver private area. */
1ed32e4f 4449 mwl8k_vif = MWL8K_VIF(vif);
a66098da 4450 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 4451 mwl8k_vif->vif = vif;
ee0ddf18 4452 mwl8k_vif->macid = macid;
a66098da 4453 mwl8k_vif->seqno = 0;
d9a07d49
NS		 4454 memcpy(mwl8k_vif->bssid, vif->addr, ETH_ALEN);
4455 mwl8k_vif->is_hw_crypto_enabled = false;
a66098da 4456
aa21d0f6
LB		 4457 /* Set the mac address. */
4458 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
4459
4460 if (priv->ap_fw)
4461 mwl8k_cmd_set_new_stn_add_self(hw, vif);
4462
ee0ddf18 4463 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 4464 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 4465
4466 return 0;
4467}
4468
4469static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4470 struct ieee80211_vif *vif)
a66098da
LB		 4471{
4472 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 4473 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 4474
b64fe619
LB		 4475 if (priv->ap_fw)
4476 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
4477
aa21d0f6 4478 mwl8k_cmd_set_mac_addr(hw, vif, "\x00\x00\x00\x00\x00\x00");
32060e1b 4479
ee0ddf18 4480 priv->macids_used &= ~(1 << mwl8k_vif->macid);
f5bb87cf 4481 list_del(&mwl8k_vif->list);
a66098da
LB		 4482}
4483
ee03a932 4484static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 4485{
a66098da
LB		 4486 struct ieee80211_conf *conf = &hw->conf;
4487 struct mwl8k_priv *priv = hw->priv;
ee03a932 4488 int rc;
a66098da 4489
7595d67a 4490 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 4491 mwl8k_cmd_radio_disable(hw);
ee03a932 4492 return 0;
7595d67a
LB		 4493 }
4494
ee03a932
LB		 4495 rc = mwl8k_fw_lock(hw);
4496 if (rc)
4497 return rc;
a66098da 4498
55489b6e 4499 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 4500 if (rc)
4501 goto out;
a66098da 4502
610677d2 4503 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 4504 if (rc)
4505 goto out;
4506
a66098da
LB		 4507 if (conf->power_level > 18)
4508 conf->power_level = 18;
a66098da 4509
08b06347 4510 if (priv->ap_fw) {
03217087
NS		 4511
4512 if (conf->flags & IEEE80211_CONF_CHANGE_POWER) {
4513 rc = mwl8k_cmd_tx_power(hw, conf, conf->power_level);
4514 if (rc)
4515 goto out;
4516 }
41fdf097 4517
da62b761
NS		 4518 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x3);
4519 if (rc)
4520 wiphy_warn(hw->wiphy, "failed to set # of RX antennas");
4521 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
4522 if (rc)
4523 wiphy_warn(hw->wiphy, "failed to set # of TX antennas");
4524
08b06347 4525 } else {
41fdf097
NS		 4526 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
4527 if (rc)
4528 goto out;
08b06347
LB		 4529 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
4530 }
a66098da 4531
ee03a932
LB		 4532out:
4533 mwl8k_fw_unlock(hw);
a66098da 4534
ee03a932 4535 return rc;
a66098da
LB		 4536}
4537
b64fe619
LB		 4538static void
4539mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4540 struct ieee80211_bss_conf *info, u32 changed)
a66098da 4541{
a66098da 4542 struct mwl8k_priv *priv = hw->priv;
ba30c4a5 4543 u32 ap_legacy_rates = 0;
13935e2c 4544 u8 ap_mcs_rates[16];
3a980d0a
LB		 4545 int rc;
4546
c3cbbe8a 4547 if (mwl8k_fw_lock(hw))
3a980d0a 4548 return;
a66098da 4549
c3cbbe8a
LB		 4550 /*
4551 * No need to capture a beacon if we're no longer associated.
4552 */
4553 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
4554 priv->capture_beacon = false;
3a980d0a 4555
c3cbbe8a 4556 /*
13935e2c 4557 * Get the AP's legacy and MCS rates.
c3cbbe8a 4558 */
7dc6a7a7 4559 if (vif->bss_conf.assoc) {
c6e96010 4560 struct ieee80211_sta *ap;
c97470dd 4561
c6e96010 4562 rcu_read_lock();
c6e96010 4563
c3cbbe8a
LB		 4564 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
4565 if (ap == NULL) {
4566 rcu_read_unlock();
c6e96010 4567 goto out;
c3cbbe8a
LB		 4568 }
4569
8707d026
LB		 4570 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
4571 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
4572 } else {
4573 ap_legacy_rates =
4574 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
4575 }
13935e2c 4576 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 4577
4578 rcu_read_unlock();
4579 }
c6e96010 4580
c3cbbe8a 4581 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 4582 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 4583 if (rc)
4584 goto out;
a66098da 4585
b71ed2c6 4586 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 4587 if (rc)
4588 goto out;
c3cbbe8a 4589 }
a66098da 4590
c3cbbe8a 4591 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 4592 rc = mwl8k_set_radio_preamble(hw,
4593 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 4594 if (rc)
4595 goto out;
c3cbbe8a 4596 }
a66098da 4597
c3cbbe8a 4598 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 4599 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 4600 if (rc)
4601 goto out;
c3cbbe8a 4602 }
a66098da 4603
c97470dd
LB		 4604 if (vif->bss_conf.assoc &&
4605 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
4606 BSS_CHANGED_HT))) {
c3cbbe8a 4607 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 4608 if (rc)
4609 goto out;
c3cbbe8a 4610 }
a66098da 4611
c3cbbe8a
LB		 4612 if (vif->bss_conf.assoc &&
4613 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 4614 /*
4615 * Finalize the join. Tell rx handler to process
4616 * next beacon from our BSSID.
4617 */
0a11dfc3 4618 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 4619 priv->capture_beacon = true;
a66098da
LB		 4620 }
4621
3a980d0a
LB		 4622out:
4623 mwl8k_fw_unlock(hw);
a66098da
LB		 4624}
4625
b64fe619
LB		 4626static void
4627mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4628 struct ieee80211_bss_conf *info, u32 changed)
4629{
4630 int rc;
4631
4632 if (mwl8k_fw_lock(hw))
4633 return;
4634
4635 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4636 rc = mwl8k_set_radio_preamble(hw,
4637 vif->bss_conf.use_short_preamble);
4638 if (rc)
4639 goto out;
4640 }
4641
4642 if (changed & BSS_CHANGED_BASIC_RATES) {
4643 int idx;
4644 int rate;
4645
4646 /*
4647 * Use lowest supported basic rate for multicasts
4648 * and management frames (such as probe responses --
4649 * beacons will always go out at 1 Mb/s).
4650 */
4651 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 4652 if (idx)
4653 idx--;
4654
4655 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
4656 rate = mwl8k_rates_24[idx].hw_value;
4657 else
4658 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 4659
4660 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
4661 }
4662
4663 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
4664 struct sk_buff *skb;
4665
4666 skb = ieee80211_beacon_get(hw, vif);
4667 if (skb != NULL) {
aa21d0f6 4668 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 4669 kfree_skb(skb);
4670 }
4671 }
4672
4673 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 4674 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 4675
4676out:
4677 mwl8k_fw_unlock(hw);
4678}
4679
4680static void
4681mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4682 struct ieee80211_bss_conf *info, u32 changed)
4683{
4684 struct mwl8k_priv *priv = hw->priv;
4685
4686 if (!priv->ap_fw)
4687 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
4688 else
4689 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
4690}
4691
e81cd2d6 4692static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 4693 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 4694{
4695 struct mwl8k_cmd_pkt *cmd;
4696
447ced07
LB		 4697 /*
4698 * Synthesize and return a command packet that programs the
4699 * hardware multicast address filter. At this point we don't
4700 * know whether FIF_ALLMULTI is being requested, but if it is,
4701 * we'll end up throwing this packet away and creating a new
4702 * one in mwl8k_configure_filter().
4703 */
22bedad3 4704 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 4705
4706 return (unsigned long)cmd;
4707}
4708
a43c49a8
LB		 4709static int
4710mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
4711 unsigned int changed_flags,
4712 unsigned int *total_flags)
4713{
4714 struct mwl8k_priv *priv = hw->priv;
4715
4716 /*
4717 * Hardware sniffer mode is mutually exclusive with STA
4718 * operation, so refuse to enable sniffer mode if a STA
4719 * interface is active.
4720 */
f5bb87cf 4721 if (!list_empty(&priv->vif_list)) {
a43c49a8 4722 if (net_ratelimit())
c96c31e4
JP		 4723 wiphy_info(hw->wiphy,
4724 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 4725 return 0;
4726 }
4727
4728 if (!priv->sniffer_enabled) {
55489b6e 4729 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 4730 return 0;
4731 priv->sniffer_enabled = true;
4732 }
4733
4734 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
4735 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
4736 FIF_OTHER_BSS;
4737
4738 return 1;
4739}
4740
f5bb87cf
LB		 4741static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
4742{
4743 if (!list_empty(&priv->vif_list))
4744 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
4745
4746 return NULL;
4747}
4748
e6935ea1
LB		 4749static void mwl8k_configure_filter(struct ieee80211_hw *hw,
4750 unsigned int changed_flags,
4751 unsigned int *total_flags,
4752 u64 multicast)
4753{
4754 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 4755 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
4756
c0adae2c
LB		 4757 /*
4758 * AP firmware doesn't allow fine-grained control over
4759 * the receive filter.
4760 */
4761 if (priv->ap_fw) {
4762 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
4763 kfree(cmd);
4764 return;
4765 }
4766
a43c49a8
LB		 4767 /*
4768 * Enable hardware sniffer mode if FIF_CONTROL or
4769 * FIF_OTHER_BSS is requested.
4770 */
4771 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
4772 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
4773 kfree(cmd);
4774 return;
4775 }
a66098da 4776
e6935ea1 4777 /* Clear unsupported feature flags */
447ced07 4778 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 4779
90852f7a
LB		 4780 if (mwl8k_fw_lock(hw)) {
4781 kfree(cmd);
e6935ea1 4782 return;
90852f7a 4783 }
a66098da 4784
a43c49a8 4785 if (priv->sniffer_enabled) {
55489b6e 4786 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 4787 priv->sniffer_enabled = false;
4788 }
4789
e6935ea1 4790 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 4791 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
4792 /*
4793 * Disable the BSS filter.
4794 */
e6935ea1 4795 mwl8k_cmd_set_pre_scan(hw);
77165d88 4796 } else {
f5bb87cf 4797 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 4798 const u8 *bssid;
a94cc97e 4799
77165d88
LB		 4800 /*
4801 * Enable the BSS filter.
4802 *
4803 * If there is an active STA interface, use that
4804 * interface's BSSID, otherwise use a dummy one
4805 * (where the OUI part needs to be nonzero for
4806 * the BSSID to be accepted by POST_SCAN).
4807 */
f5bb87cf
LB		 4808 mwl8k_vif = mwl8k_first_vif(priv);
4809 if (mwl8k_vif != NULL)
4810 bssid = mwl8k_vif->vif->bss_conf.bssid;
4811 else
4812 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 4813
e6935ea1 4814 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 4815 }
4816 }
4817
447ced07
LB		 4818 /*
4819 * If FIF_ALLMULTI is being requested, throw away the command
4820 * packet that ->prepare_multicast() built and replace it with
4821 * a command packet that enables reception of all multicast
4822 * packets.
4823 */
4824 if (*total_flags & FIF_ALLMULTI) {
4825 kfree(cmd);
22bedad3 4826 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 4827 }
4828
4829 if (cmd != NULL) {
4830 mwl8k_post_cmd(hw, cmd);
4831 kfree(cmd);
e6935ea1 4832 }
a66098da 4833
e6935ea1 4834 mwl8k_fw_unlock(hw);
a66098da
LB		 4835}
4836
a66098da
LB		 4837static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4838{
c2c2b12a 4839 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 4840}
4841
4a6967b8
JB		 4842static int mwl8k_sta_remove(struct ieee80211_hw *hw,
4843 struct ieee80211_vif *vif,
4844 struct ieee80211_sta *sta)
3f5610ff
LB		 4845{
4846 struct mwl8k_priv *priv = hw->priv;
4847
4a6967b8
JB		 4848 if (priv->ap_fw)
4849 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
4850 else
4851 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 4852}
4853
4a6967b8
JB		 4854static int mwl8k_sta_add(struct ieee80211_hw *hw,
4855 struct ieee80211_vif *vif,
4856 struct ieee80211_sta *sta)
bbfd9128
LB		 4857{
4858 struct mwl8k_priv *priv = hw->priv;
4a6967b8 4859 int ret;
fcdc403c
NS		 4860 int i;
4861 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
4862 struct ieee80211_key_conf *key;
bbfd9128 4863
4a6967b8
JB		 4864 if (!priv->ap_fw) {
4865 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
4866 if (ret >= 0) {
4867 MWL8K_STA(sta)->peer_id = ret;
17033543
NS		 4868 if (sta->ht_cap.ht_supported)
4869 MWL8K_STA(sta)->is_ampdu_allowed = true;
fcdc403c 4870 ret = 0;
4a6967b8 4871 }
bbfd9128 4872
d9a07d49
NS		 4873 } else {
4874 ret = mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128 4875 }
4a6967b8 4876
d9a07d49
NS		 4877 for (i = 0; i < NUM_WEP_KEYS; i++) {
4878 key = IEEE80211_KEY_CONF(mwl8k_vif->wep_key_conf[i].key);
4879 if (mwl8k_vif->wep_key_conf[i].enabled)
4880 mwl8k_set_key(hw, SET_KEY, vif, sta, key);
4881 }
fcdc403c 4882 return ret;
bbfd9128
LB		 4883}
4884
a66098da
LB		 4885static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
4886 const struct ieee80211_tx_queue_params *params)
4887{
3e4f542c 4888 struct mwl8k_priv *priv = hw->priv;
a66098da 4889 int rc;
a66098da 4890
3e4f542c
LB		 4891 rc = mwl8k_fw_lock(hw);
4892 if (!rc) {
e600707b 4893 BUG_ON(queue > MWL8K_TX_WMM_QUEUES - 1);
0863ade8
BC		 4894 memcpy(&priv->wmm_params[queue], params, sizeof(*params));
4895
3e4f542c 4896 if (!priv->wmm_enabled)
55489b6e 4897 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 4898
85c9205c 4899 if (!rc) {
e600707b 4900 int q = MWL8K_TX_WMM_QUEUES - 1 - queue;
85c9205c 4901 rc = mwl8k_cmd_set_edca_params(hw, q,
55489b6e
LB		 4902 params->cw_min,
4903 params->cw_max,
4904 params->aifs,
4905 params->txop);
85c9205c 4906 }
3e4f542c
LB		 4907
4908 mwl8k_fw_unlock(hw);
a66098da 4909 }
3e4f542c 4910
a66098da
LB		 4911 return rc;
4912}
4913
a66098da
LB		 4914static int mwl8k_get_stats(struct ieee80211_hw *hw,
4915 struct ieee80211_low_level_stats *stats)
4916{
55489b6e 4917 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 4918}
4919
0d462bbb
JL		 4920static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
4921 struct survey_info *survey)
4922{
4923 struct mwl8k_priv *priv = hw->priv;
4924 struct ieee80211_conf *conf = &hw->conf;
4925
4926 if (idx != 0)
4927 return -ENOENT;
4928
4929 survey->channel = conf->channel;
4930 survey->filled = SURVEY_INFO_NOISE_DBM;
4931 survey->noise = priv->noise;
4932
4933 return 0;
4934}
4935
65f3ddcd
NS		 4936#define MAX_AMPDU_ATTEMPTS 5
4937
a2292d83
LB		 4938static int
4939mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4940 enum ieee80211_ampdu_mlme_action action,
0b01f030
JB		 4941 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
4942 u8 buf_size)
a2292d83 4943{
65f3ddcd
NS		 4944
4945 int i, rc = 0;
4946 struct mwl8k_priv *priv = hw->priv;
4947 struct mwl8k_ampdu_stream *stream;
4948 u8 *addr = sta->addr;
4949
4950 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
4951 return -ENOTSUPP;
4952
4953 spin_lock(&priv->stream_lock);
4954 stream = mwl8k_lookup_stream(hw, addr, tid);
4955
a2292d83
LB		 4956 switch (action) {
4957 case IEEE80211_AMPDU_RX_START:
4958 case IEEE80211_AMPDU_RX_STOP:
65f3ddcd
NS		 4959 break;
4960 case IEEE80211_AMPDU_TX_START:
4961 /* By the time we get here the hw queues may contain outgoing
4962 * packets for this RA/TID that are not part of this BA
4963 * session. The hw will assign sequence numbers to these
4964 * packets as they go out. So if we query the hw for its next
4965 * sequence number and use that for the SSN here, it may end up
4966 * being wrong, which will lead to sequence number mismatch at
4967 * the recipient. To avoid this, we reset the sequence number
4968 * to O for the first MPDU in this BA stream.
4969 */
4970 *ssn = 0;
4971 if (stream == NULL) {
4972 /* This means that somebody outside this driver called
4973 * ieee80211_start_tx_ba_session. This is unexpected
4974 * because we do our own rate control. Just warn and
4975 * move on.
4976 */
4977 wiphy_warn(hw->wiphy, "Unexpected call to %s. "
4978 "Proceeding anyway.\n", __func__);
4979 stream = mwl8k_add_stream(hw, sta, tid);
4980 }
4981 if (stream == NULL) {
4982 wiphy_debug(hw->wiphy, "no free AMPDU streams\n");
4983 rc = -EBUSY;
4984 break;
4985 }
4986 stream->state = AMPDU_STREAM_IN_PROGRESS;
4987
4988 /* Release the lock before we do the time consuming stuff */
4989 spin_unlock(&priv->stream_lock);
4990 for (i = 0; i < MAX_AMPDU_ATTEMPTS; i++) {
4991 rc = mwl8k_check_ba(hw, stream);
4992
4993 if (!rc)
4994 break;
4995 /*
4996 * HW queues take time to be flushed, give them
4997 * sufficient time
4998 */
4999
5000 msleep(1000);
5001 }
5002 spin_lock(&priv->stream_lock);
5003 if (rc) {
5004 wiphy_err(hw->wiphy, "Stream for tid %d busy after %d"
5005 " attempts\n", tid, MAX_AMPDU_ATTEMPTS);
5006 mwl8k_remove_stream(hw, stream);
5007 rc = -EBUSY;
5008 break;
5009 }
5010 ieee80211_start_tx_ba_cb_irqsafe(vif, addr, tid);
5011 break;
5012 case IEEE80211_AMPDU_TX_STOP:
5013 if (stream == NULL)
5014 break;
5015 if (stream->state == AMPDU_STREAM_ACTIVE) {
5016 spin_unlock(&priv->stream_lock);
5017 mwl8k_destroy_ba(hw, stream);
5018 spin_lock(&priv->stream_lock);
5019 }
5020 mwl8k_remove_stream(hw, stream);
5021 ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);
5022 break;
5023 case IEEE80211_AMPDU_TX_OPERATIONAL:
5024 BUG_ON(stream == NULL);
5025 BUG_ON(stream->state != AMPDU_STREAM_IN_PROGRESS);
5026 spin_unlock(&priv->stream_lock);
5027 rc = mwl8k_create_ba(hw, stream, buf_size);
5028 spin_lock(&priv->stream_lock);
5029 if (!rc)
5030 stream->state = AMPDU_STREAM_ACTIVE;
5031 else {
5032 spin_unlock(&priv->stream_lock);
5033 mwl8k_destroy_ba(hw, stream);
5034 spin_lock(&priv->stream_lock);
5035 wiphy_debug(hw->wiphy,
5036 "Failed adding stream for sta %pM tid %d\n",
5037 addr, tid);
5038 mwl8k_remove_stream(hw, stream);
5039 }
5040 break;
5041
a2292d83 5042 default:
65f3ddcd 5043 rc = -ENOTSUPP;
a2292d83 5044 }
65f3ddcd
NS		 5045
5046 spin_unlock(&priv->stream_lock);
5047 return rc;
a2292d83
LB		 5048}
5049
a66098da
LB		 5050static const struct ieee80211_ops mwl8k_ops = {
5051 .tx = mwl8k_tx,
5052 .start = mwl8k_start,
5053 .stop = mwl8k_stop,
5054 .add_interface = mwl8k_add_interface,
5055 .remove_interface = mwl8k_remove_interface,
5056 .config = mwl8k_config,
a66098da 5057 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 5058 .prepare_multicast = mwl8k_prepare_multicast,
a66098da 5059 .configure_filter = mwl8k_configure_filter,
fcdc403c 5060 .set_key = mwl8k_set_key,
a66098da 5061 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 5062 .sta_add = mwl8k_sta_add,
5063 .sta_remove = mwl8k_sta_remove,
a66098da 5064 .conf_tx = mwl8k_conf_tx,
a66098da 5065 .get_stats = mwl8k_get_stats,
0d462bbb 5066 .get_survey = mwl8k_get_survey,
a2292d83 5067 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 5068};
5069
a66098da
LB		 5070static void mwl8k_finalize_join_worker(struct work_struct *work)
5071{
5072 struct mwl8k_priv *priv =
5073 container_of(work, struct mwl8k_priv, finalize_join_worker);
5074 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 5075 struct ieee80211_mgmt *mgmt = (void *)skb->data;
5076 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
5077 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
5078 mgmt->u.beacon.variable, len);
5079 int dtim_period = 1;
5080
5081 if (tim && tim[1] >= 2)
5082 dtim_period = tim[3];
a66098da 5083
56007a02 5084 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 5085
f5bb87cf 5086 dev_kfree_skb(skb);
a66098da
LB		 5087 priv->beacon_skb = NULL;
5088}
5089
bcb628d5 5090enum {
9e1b17ea
LB		 5091 MWL8363 = 0,
5092 MWL8687,
bcb628d5 5093 MWL8366,
6f6d1e9a
LB		 5094};
5095
8a7a578c 5096#define MWL8K_8366_AP_FW_API 2
952a0e96
BC		 5097#define _MWL8K_8366_AP_FW(api) "mwl8k/fmimage_8366_ap-" #api ".fw"
5098#define MWL8K_8366_AP_FW(api) _MWL8K_8366_AP_FW(api)
5099
bcb628d5 5100static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 5101 [MWL8363] = {
5102 .part_name = "88w8363",
5103 .helper_image = "mwl8k/helper_8363.fw",
0863ade8 5104 .fw_image_sta = "mwl8k/fmimage_8363.fw",
9e1b17ea 5105 },
49eb691c 5106 [MWL8687] = {
bcb628d5
JL		 5107 .part_name = "88w8687",
5108 .helper_image = "mwl8k/helper_8687.fw",
0863ade8 5109 .fw_image_sta = "mwl8k/fmimage_8687.fw",
bcb628d5 5110 },
49eb691c 5111 [MWL8366] = {
bcb628d5
JL		 5112 .part_name = "88w8366",
5113 .helper_image = "mwl8k/helper_8366.fw",
0863ade8 5114 .fw_image_sta = "mwl8k/fmimage_8366.fw",
952a0e96
BC		 5115 .fw_image_ap = MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API),
5116 .fw_api_ap = MWL8K_8366_AP_FW_API,
89a91f4f 5117 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 5118 },
45a390dd
LB		 5119};
5120
c92d4ede
LB		 5121MODULE_FIRMWARE("mwl8k/helper_8363.fw");
5122MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
5123MODULE_FIRMWARE("mwl8k/helper_8687.fw");
5124MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
5125MODULE_FIRMWARE("mwl8k/helper_8366.fw");
5126MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
952a0e96 5127MODULE_FIRMWARE(MWL8K_8366_AP_FW(MWL8K_8366_AP_FW_API));
c92d4ede 5128
45a390dd 5129static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 5130 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 5131 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
5132 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 5133 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
5134 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
5135 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 5136 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 5137 { },
45a390dd
LB		 5138};
5139MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
5140
99020471
BC		 5141static int mwl8k_request_alt_fw(struct mwl8k_priv *priv)
5142{
5143 int rc;
5144 printk(KERN_ERR "%s: Error requesting preferred fw %s.\n"
5145 "Trying alternative firmware %s\n", pci_name(priv->pdev),
5146 priv->fw_pref, priv->fw_alt);
5147 rc = mwl8k_request_fw(priv, priv->fw_alt, &priv->fw_ucode, true);
5148 if (rc) {
5149 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5150 pci_name(priv->pdev), priv->fw_alt);
5151 return rc;
5152 }
5153 return 0;
5154}
5155
5156static int mwl8k_firmware_load_success(struct mwl8k_priv *priv);
5157static void mwl8k_fw_state_machine(const struct firmware *fw, void *context)
5158{
5159 struct mwl8k_priv *priv = context;
5160 struct mwl8k_device_info *di = priv->device_info;
5161 int rc;
5162
5163 switch (priv->fw_state) {
5164 case FW_STATE_INIT:
5165 if (!fw) {
5166 printk(KERN_ERR "%s: Error requesting helper fw %s\n",
5167 pci_name(priv->pdev), di->helper_image);
5168 goto fail;
5169 }
5170 priv->fw_helper = fw;
5171 rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode,
5172 true);
5173 if (rc && priv->fw_alt) {
5174 rc = mwl8k_request_alt_fw(priv);
5175 if (rc)
5176 goto fail;
5177 priv->fw_state = FW_STATE_LOADING_ALT;
5178 } else if (rc)
5179 goto fail;
5180 else
5181 priv->fw_state = FW_STATE_LOADING_PREF;
5182 break;
5183
5184 case FW_STATE_LOADING_PREF:
5185 if (!fw) {
5186 if (priv->fw_alt) {
5187 rc = mwl8k_request_alt_fw(priv);
5188 if (rc)
5189 goto fail;
5190 priv->fw_state = FW_STATE_LOADING_ALT;
5191 } else
5192 goto fail;
5193 } else {
5194 priv->fw_ucode = fw;
5195 rc = mwl8k_firmware_load_success(priv);
5196 if (rc)
5197 goto fail;
5198 else
5199 complete(&priv->firmware_loading_complete);
5200 }
5201 break;
5202
5203 case FW_STATE_LOADING_ALT:
5204 if (!fw) {
5205 printk(KERN_ERR "%s: Error requesting alt fw %s\n",
5206 pci_name(priv->pdev), di->helper_image);
5207 goto fail;
5208 }
5209 priv->fw_ucode = fw;
5210 rc = mwl8k_firmware_load_success(priv);
5211 if (rc)
5212 goto fail;
5213 else
5214 complete(&priv->firmware_loading_complete);
5215 break;
5216
5217 default:
5218 printk(KERN_ERR "%s: Unexpected firmware loading state: %d\n",
5219 MWL8K_NAME, priv->fw_state);
5220 BUG_ON(1);
5221 }
5222
5223 return;
5224
5225fail:
5226 priv->fw_state = FW_STATE_ERROR;
5227 complete(&priv->firmware_loading_complete);
5228 device_release_driver(&priv->pdev->dev);
5229 mwl8k_release_firmware(priv);
5230}
5231
5232static int mwl8k_init_firmware(struct ieee80211_hw *hw, char *fw_image,
5233 bool nowait)
a66098da 5234{
3cc7772c 5235 struct mwl8k_priv *priv = hw->priv;
a66098da 5236 int rc;
be695fc4
LB		 5237
5238 /* Reset firmware and hardware */
5239 mwl8k_hw_reset(priv);
5240
5241 /* Ask userland hotplug daemon for the device firmware */
99020471 5242 rc = mwl8k_request_firmware(priv, fw_image, nowait);
be695fc4 5243 if (rc) {
5db55844 5244 wiphy_err(hw->wiphy, "Firmware files not found\n");
3cc7772c 5245 return rc;
be695fc4
LB		 5246 }
5247
99020471
BC		 5248 if (nowait)
5249 return rc;
5250
be695fc4
LB		 5251 /* Load firmware into hardware */
5252 rc = mwl8k_load_firmware(hw);
3cc7772c 5253 if (rc)
5db55844 5254 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 5255
5256 /* Reclaim memory once firmware is successfully loaded */
5257 mwl8k_release_firmware(priv);
5258
3cc7772c
BC		 5259 return rc;
5260}
5261
73b46320
BC		 5262static int mwl8k_init_txqs(struct ieee80211_hw *hw)
5263{
5264 struct mwl8k_priv *priv = hw->priv;
5265 int rc = 0;
5266 int i;
5267
e600707b 5268 for (i = 0; i < mwl8k_tx_queues(priv); i++) {
73b46320
BC		 5269 rc = mwl8k_txq_init(hw, i);
5270 if (rc)
5271 break;
5272 if (priv->ap_fw)
5273 iowrite32(priv->txq[i].txd_dma,
5274 priv->sram + priv->txq_offset[i]);
5275 }
5276 return rc;
5277}
5278
3cc7772c
BC		 5279/* initialize hw after successfully loading a firmware image */
5280static int mwl8k_probe_hw(struct ieee80211_hw *hw)
5281{
5282 struct mwl8k_priv *priv = hw->priv;
5283 int rc = 0;
5284 int i;
be695fc4 5285
91942230 5286 if (priv->ap_fw) {
89a91f4f 5287 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 5288 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 5289 wiphy_err(hw->wiphy,
5290 "Driver does not have AP firmware image support for this hardware\n");
91942230
LB		 5291 goto err_stop_firmware;
5292 }
5293 } else {
89a91f4f 5294 priv->rxd_ops = &rxd_sta_ops;
91942230 5295 }
be695fc4
LB		 5296
5297 priv->sniffer_enabled = false;
5298 priv->wmm_enabled = false;
5299 priv->pending_tx_pkts = 0;
5300
a66098da
LB		 5301 rc = mwl8k_rxq_init(hw, 0);
5302 if (rc)
3cc7772c 5303 goto err_stop_firmware;
a66098da
LB		 5304 rxq_refill(hw, 0, INT_MAX);
5305
73b46320
BC		 5306 /* For the sta firmware, we need to know the dma addresses of tx queues
5307 * before sending MWL8K_CMD_GET_HW_SPEC. So we must initialize them
5308 * prior to issuing this command. But for the AP case, we learn the
5309 * total number of queues from the result CMD_GET_HW_SPEC, so for this
5310 * case we must initialize the tx queues after.
5311 */
8a7a578c 5312 priv->num_ampdu_queues = 0;
73b46320
BC		 5313 if (!priv->ap_fw) {
5314 rc = mwl8k_init_txqs(hw);
a66098da
LB		 5315 if (rc)
5316 goto err_free_queues;
5317 }
5318
5319 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 5320 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3aefc37e
NS		 5321 iowrite32(MWL8K_A2H_INT_TX_DONE|MWL8K_A2H_INT_RX_READY|
5322 MWL8K_A2H_INT_BA_WATCHDOG,
1e9f9de3 5323 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
12488e01
NS		 5324 iowrite32(MWL8K_A2H_INT_OPC_DONE,
5325 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
a66098da 5326
a0607fd3 5327 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 5328 IRQF_SHARED, MWL8K_NAME, hw);
5329 if (rc) {
5db55844 5330 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 5331 goto err_free_queues;
5332 }
5333
ac109fd0
BC		 5334 memset(priv->ampdu, 0, sizeof(priv->ampdu));
5335
a66098da
LB		 5336 /*
5337 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 5338 * commands use interrupts and avoid polling. Disable
a66098da
LB		 5339 * interrupts when done.
5340 */
c23b5a69 5341 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5342
5343 /* Get config data, mac addrs etc */
42fba21d
LB		 5344 if (priv->ap_fw) {
5345 rc = mwl8k_cmd_get_hw_spec_ap(hw);
73b46320
BC		 5346 if (!rc)
5347 rc = mwl8k_init_txqs(hw);
42fba21d
LB		 5348 if (!rc)
5349 rc = mwl8k_cmd_set_hw_spec(hw);
5350 } else {
5351 rc = mwl8k_cmd_get_hw_spec_sta(hw);
5352 }
a66098da 5353 if (rc) {
5db55844 5354 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 5355 goto err_free_irq;
a66098da
LB		 5356 }
5357
5358 /* Turn radio off */
55489b6e 5359 rc = mwl8k_cmd_radio_disable(hw);
a66098da 5360 if (rc) {
5db55844 5361 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 5362 goto err_free_irq;
a66098da
LB		 5363 }
5364
32060e1b 5365 /* Clear MAC address */
aa21d0f6 5366 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 5367 if (rc) {
5db55844 5368 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 5369 goto err_free_irq;
32060e1b
LB		 5370 }
5371
a66098da 5372 /* Disable interrupts */
a66098da 5373 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5374 free_irq(priv->pdev->irq, hw);
5375
c96c31e4
JP		 5376 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
5377 priv->device_info->part_name,
5378 priv->hw_rev, hw->wiphy->perm_addr,
5379 priv->ap_fw ? "AP" : "STA",
5380 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
5381 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 5382
5383 return 0;
5384
a66098da 5385err_free_irq:
a66098da 5386 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 5387 free_irq(priv->pdev->irq, hw);
5388
5389err_free_queues:
e600707b 5390 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 5391 mwl8k_txq_deinit(hw, i);
5392 mwl8k_rxq_deinit(hw, 0);
5393
3cc7772c
BC		 5394err_stop_firmware:
5395 mwl8k_hw_reset(priv);
5396
5397 return rc;
5398}
5399
5400/*
5401 * invoke mwl8k_reload_firmware to change the firmware image after the device
5402 * has already been registered
5403 */
5404static int mwl8k_reload_firmware(struct ieee80211_hw *hw, char *fw_image)
5405{
5406 int i, rc = 0;
5407 struct mwl8k_priv *priv = hw->priv;
5408
5409 mwl8k_stop(hw);
5410 mwl8k_rxq_deinit(hw, 0);
5411
e600707b 5412 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 5413 mwl8k_txq_deinit(hw, i);
5414
99020471 5415 rc = mwl8k_init_firmware(hw, fw_image, false);
3cc7772c
BC		 5416 if (rc)
5417 goto fail;
5418
5419 rc = mwl8k_probe_hw(hw);
5420 if (rc)
5421 goto fail;
5422
5423 rc = mwl8k_start(hw);
5424 if (rc)
5425 goto fail;
5426
5427 rc = mwl8k_config(hw, ~0);
5428 if (rc)
5429 goto fail;
5430
e600707b 5431 for (i = 0; i < MWL8K_TX_WMM_QUEUES; i++) {
3cc7772c
BC		 5432 rc = mwl8k_conf_tx(hw, i, &priv->wmm_params[i]);
5433 if (rc)
5434 goto fail;
5435 }
5436
5437 return rc;
5438
5439fail:
5440 printk(KERN_WARNING "mwl8k: Failed to reload firmware image.\n");
5441 return rc;
5442}
5443
5444static int mwl8k_firmware_load_success(struct mwl8k_priv *priv)
5445{
5446 struct ieee80211_hw *hw = priv->hw;
5447 int i, rc;
5448
99020471
BC		 5449 rc = mwl8k_load_firmware(hw);
5450 mwl8k_release_firmware(priv);
5451 if (rc) {
5452 wiphy_err(hw->wiphy, "Cannot start firmware\n");
5453 return rc;
5454 }
5455
3cc7772c
BC		 5456 /*
5457 * Extra headroom is the size of the required DMA header
5458 * minus the size of the smallest 802.11 frame (CTS frame).
5459 */
5460 hw->extra_tx_headroom =
5461 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
5462
5463 hw->channel_change_time = 10;
5464
e600707b 5465 hw->queues = MWL8K_TX_WMM_QUEUES;
3cc7772c
BC		 5466
5467 /* Set rssi values to dBm */
0bf22c37 5468 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_HAS_RATE_CONTROL;
3cc7772c
BC		 5469 hw->vif_data_size = sizeof(struct mwl8k_vif);
5470 hw->sta_data_size = sizeof(struct mwl8k_sta);
5471
5472 priv->macids_used = 0;
5473 INIT_LIST_HEAD(&priv->vif_list);
5474
5475 /* Set default radio state and preamble */
5476 priv->radio_on = 0;
5477 priv->radio_short_preamble = 0;
5478
5479 /* Finalize join worker */
5480 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3aefc37e
NS		 5481 /* Handle watchdog ba events */
5482 INIT_WORK(&priv->watchdog_ba_handle, mwl8k_watchdog_ba_events);
3cc7772c
BC		 5483
5484 /* TX reclaim and RX tasklets. */
5485 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
5486 tasklet_disable(&priv->poll_tx_task);
5487 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
5488 tasklet_disable(&priv->poll_rx_task);
5489
5490 /* Power management cookie */
5491 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
5492 if (priv->cookie == NULL)
5493 return -ENOMEM;
5494
5495 mutex_init(&priv->fw_mutex);
5496 priv->fw_mutex_owner = NULL;
5497 priv->fw_mutex_depth = 0;
5498 priv->hostcmd_wait = NULL;
5499
5500 spin_lock_init(&priv->tx_lock);
5501
ac109fd0
BC		 5502 spin_lock_init(&priv->stream_lock);
5503
3cc7772c
BC		 5504 priv->tx_wait = NULL;
5505
5506 rc = mwl8k_probe_hw(hw);
5507 if (rc)
5508 goto err_free_cookie;
5509
5510 hw->wiphy->interface_modes = 0;
5511 if (priv->ap_macids_supported || priv->device_info->fw_image_ap)
5512 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
5513 if (priv->sta_macids_supported || priv->device_info->fw_image_sta)
5514 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
5515
5516 rc = ieee80211_register_hw(hw);
5517 if (rc) {
5518 wiphy_err(hw->wiphy, "Cannot register device\n");
5519 goto err_unprobe_hw;
5520 }
5521
5522 return 0;
5523
5524err_unprobe_hw:
e600707b 5525 for (i = 0; i < mwl8k_tx_queues(priv); i++)
3cc7772c
BC		 5526 mwl8k_txq_deinit(hw, i);
5527 mwl8k_rxq_deinit(hw, 0);
5528
be695fc4 5529err_free_cookie:
a66098da
LB		 5530 if (priv->cookie != NULL)
5531 pci_free_consistent(priv->pdev, 4,
5532 priv->cookie, priv->cookie_dma);
5533
3cc7772c
BC		 5534 return rc;
5535}
5536static int __devinit mwl8k_probe(struct pci_dev *pdev,
5537 const struct pci_device_id *id)
5538{
5539 static int printed_version;
5540 struct ieee80211_hw *hw;
5541 struct mwl8k_priv *priv;
0863ade8 5542 struct mwl8k_device_info *di;
3cc7772c
BC		 5543 int rc;
5544
5545 if (!printed_version) {
5546 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
5547 printed_version = 1;
5548 }
5549
5550
5551 rc = pci_enable_device(pdev);
5552 if (rc) {
5553 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
5554 MWL8K_NAME);
5555 return rc;
5556 }
5557
5558 rc = pci_request_regions(pdev, MWL8K_NAME);
5559 if (rc) {
5560 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
5561 MWL8K_NAME);
5562 goto err_disable_device;
5563 }
5564
5565 pci_set_master(pdev);
5566
5567
5568 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
5569 if (hw == NULL) {
5570 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
5571 rc = -ENOMEM;
5572 goto err_free_reg;
5573 }
5574
5575 SET_IEEE80211_DEV(hw, &pdev->dev);
5576 pci_set_drvdata(pdev, hw);
5577
5578 priv = hw->priv;
5579 priv->hw = hw;
5580 priv->pdev = pdev;
5581 priv->device_info = &mwl8k_info_tbl[id->driver_data];
5582
5583
5584 priv->sram = pci_iomap(pdev, 0, 0x10000);
5585 if (priv->sram == NULL) {
5586 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
5587 goto err_iounmap;
5588 }
5589
5590 /*
5591 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
5592 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
5593 */
5594 priv->regs = pci_iomap(pdev, 1, 0x10000);
5595 if (priv->regs == NULL) {
5596 priv->regs = pci_iomap(pdev, 2, 0x10000);
5597 if (priv->regs == NULL) {
5598 wiphy_err(hw->wiphy, "Cannot map device registers\n");
5599 goto err_iounmap;
5600 }
5601 }
5602
0863ade8 5603 /*
99020471
BC		 5604 * Choose the initial fw image depending on user input. If a second
5605 * image is available, make it the alternative image that will be
5606 * loaded if the first one fails.
0863ade8 5607 */
99020471 5608 init_completion(&priv->firmware_loading_complete);
0863ade8 5609 di = priv->device_info;
99020471
BC		 5610 if (ap_mode_default && di->fw_image_ap) {
5611 priv->fw_pref = di->fw_image_ap;
5612 priv->fw_alt = di->fw_image_sta;
5613 } else if (!ap_mode_default && di->fw_image_sta) {
5614 priv->fw_pref = di->fw_image_sta;
5615 priv->fw_alt = di->fw_image_ap;
5616 } else if (ap_mode_default && !di->fw_image_ap && di->fw_image_sta) {
0863ade8 5617 printk(KERN_WARNING "AP fw is unavailable. Using STA fw.");
99020471 5618 priv->fw_pref = di->fw_image_sta;
0863ade8
BC		 5619 } else if (!ap_mode_default && !di->fw_image_sta && di->fw_image_ap) {
5620 printk(KERN_WARNING "STA fw is unavailable. Using AP fw.");
99020471
BC		 5621 priv->fw_pref = di->fw_image_ap;
5622 }
5623 rc = mwl8k_init_firmware(hw, priv->fw_pref, true);
3cc7772c
BC		 5624 if (rc)
5625 goto err_stop_firmware;
99020471 5626 return rc;
3cc7772c 5627
be695fc4
LB		 5628err_stop_firmware:
5629 mwl8k_hw_reset(priv);
be695fc4
LB		 5630
5631err_iounmap:
a66098da
LB		 5632 if (priv->regs != NULL)
5633 pci_iounmap(pdev, priv->regs);
5634
5b9482dd
LB		 5635 if (priv->sram != NULL)
5636 pci_iounmap(pdev, priv->sram);
5637
a66098da
LB		 5638 pci_set_drvdata(pdev, NULL);
5639 ieee80211_free_hw(hw);
5640
5641err_free_reg:
5642 pci_release_regions(pdev);
3db95e50
LB		 5643
5644err_disable_device:
a66098da
LB		 5645 pci_disable_device(pdev);
5646
5647 return rc;
5648}
5649
230f7af0 5650static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 5651{
5652 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
5653}
5654
230f7af0 5655static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 5656{
5657 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
5658 struct mwl8k_priv *priv;
5659 int i;
5660
5661 if (hw == NULL)
5662 return;
5663 priv = hw->priv;
5664
99020471
BC		 5665 wait_for_completion(&priv->firmware_loading_complete);
5666
5667 if (priv->fw_state == FW_STATE_ERROR) {
5668 mwl8k_hw_reset(priv);
5669 goto unmap;
5670 }
5671
a66098da
LB		 5672 ieee80211_stop_queues(hw);
5673
60aa569f
LB		 5674 ieee80211_unregister_hw(hw);
5675
67e2eb27 5676 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 5677 tasklet_kill(&priv->poll_tx_task);
67e2eb27 5678 tasklet_kill(&priv->poll_rx_task);
a66098da 5679
a66098da
LB		 5680 /* Stop hardware */
5681 mwl8k_hw_reset(priv);
5682
5683 /* Return all skbs to mac80211 */
e600707b 5684 for (i = 0; i < mwl8k_tx_queues(priv); i++)
efb7c49a 5685 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 5686
e600707b 5687 for (i = 0; i < mwl8k_tx_queues(priv); i++)
a66098da
LB		 5688 mwl8k_txq_deinit(hw, i);
5689
5690 mwl8k_rxq_deinit(hw, 0);
5691
c2c357ce 5692 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da 5693
99020471 5694unmap:
a66098da 5695 pci_iounmap(pdev, priv->regs);
5b9482dd 5696 pci_iounmap(pdev, priv->sram);
a66098da
LB		 5697 pci_set_drvdata(pdev, NULL);
5698 ieee80211_free_hw(hw);
5699 pci_release_regions(pdev);
5700 pci_disable_device(pdev);
5701}
5702
5703static struct pci_driver mwl8k_driver = {
5704 .name = MWL8K_NAME,
45a390dd 5705 .id_table = mwl8k_pci_id_table,
a66098da
LB		 5706 .probe = mwl8k_probe,
5707 .remove = __devexit_p(mwl8k_remove),
5708 .shutdown = __devexit_p(mwl8k_shutdown),
5709};
5710
5711static int __init mwl8k_init(void)
5712{
5713 return pci_register_driver(&mwl8k_driver);
5714}
5715
5716static void __exit mwl8k_exit(void)
5717{
5718 pci_unregister_driver(&mwl8k_driver);
5719}
5720
5721module_init(mwl8k_init);
5722module_exit(mwl8k_exit);
c2c357ce
LB		 5723
5724MODULE_DESCRIPTION(MWL8K_DESC);
5725MODULE_VERSION(MWL8K_VERSION);
5726MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
5727MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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