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wl1251: add U-APSD support
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
45a390dd
LB		 132 struct mwl8k_device_info *device_info;
133
be695fc4
LB		 134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
22be40d9
LB		 138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
be695fc4
LB		 141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
144
618952a7
LB		 145 /* firmware access */
146 struct mutex fw_mutex;
147 struct task_struct *fw_mutex_owner;
148 int fw_mutex_depth;
618952a7
LB		 149 struct completion *hostcmd_wait;
150
a66098da
LB		 151 /* lock held over TX and TX reap */
152 spinlock_t tx_lock;
a66098da 153
88de754a
LB		 154 /* TX quiesce completion, protected by fw_mutex and tx_lock */
155 struct completion *tx_wait;
156
a66098da 157 struct ieee80211_vif *vif;
a66098da
LB		 158
159 struct ieee80211_channel *current_channel;
160
161 /* power management status cookie from firmware */
162 u32 *cookie;
163 dma_addr_t cookie_dma;
164
165 u16 num_mcaddrs;
a66098da 166 u8 hw_rev;
2aa7b01f 167 u32 fw_rev;
a66098da
LB		 168
169 /*
170 * Running count of TX packets in flight, to avoid
171 * iterating over the transmit rings each time.
172 */
173 int pending_tx_pkts;
174
175 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
176 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
177
178 /* PHY parameters */
179 struct ieee80211_supported_band band;
180 struct ieee80211_channel channels[14];
140eb5e2 181 struct ieee80211_rate rates[14];
a66098da 182
c46563b7 183 bool radio_on;
68ce3884 184 bool radio_short_preamble;
a43c49a8 185 bool sniffer_enabled;
0439b1f5 186 bool wmm_enabled;
a66098da 187
bbfd9128
LB		 188 struct work_struct sta_notify_worker;
189 spinlock_t sta_notify_list_lock;
190 struct list_head sta_notify_list;
191
a66098da
LB		 192 /* XXX need to convert this to handle multiple interfaces */
193 bool capture_beacon;
d89173f2 194 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 195 struct sk_buff *beacon_skb;
196
197 /*
198 * This FJ worker has to be global as it is scheduled from the
199 * RX handler. At this point we don't know which interface it
200 * belongs to until the list of bssids waiting to complete join
201 * is checked.
202 */
203 struct work_struct finalize_join_worker;
204
1e9f9de3
LB		 205 /* Tasklet to perform TX reclaim. */
206 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 207
208 /* Tasklet to perform RX. */
209 struct tasklet_struct poll_rx_task;
a66098da
LB		 210};
211
212/* Per interface specific private data */
213struct mwl8k_vif {
c2c2b12a 214 /* Non AMPDU sequence number assigned by driver. */
a680400e 215 u16 seqno;
a66098da 216};
a94cc97e 217#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 218
a680400e
LB		 219struct mwl8k_sta {
220 /* Index into station database. Returned by UPDATE_STADB. */
221 u8 peer_id;
222};
223#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
224
a66098da
LB		 225static const struct ieee80211_channel mwl8k_channels[] = {
226 { .center_freq = 2412, .hw_value = 1, },
227 { .center_freq = 2417, .hw_value = 2, },
228 { .center_freq = 2422, .hw_value = 3, },
229 { .center_freq = 2427, .hw_value = 4, },
230 { .center_freq = 2432, .hw_value = 5, },
231 { .center_freq = 2437, .hw_value = 6, },
232 { .center_freq = 2442, .hw_value = 7, },
233 { .center_freq = 2447, .hw_value = 8, },
234 { .center_freq = 2452, .hw_value = 9, },
235 { .center_freq = 2457, .hw_value = 10, },
236 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 237 { .center_freq = 2467, .hw_value = 12, },
238 { .center_freq = 2472, .hw_value = 13, },
239 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 240};
241
242static const struct ieee80211_rate mwl8k_rates[] = {
243 { .bitrate = 10, .hw_value = 2, },
244 { .bitrate = 20, .hw_value = 4, },
245 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 246 { .bitrate = 110, .hw_value = 22, },
247 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 248 { .bitrate = 60, .hw_value = 12, },
249 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 250 { .bitrate = 120, .hw_value = 24, },
251 { .bitrate = 180, .hw_value = 36, },
252 { .bitrate = 240, .hw_value = 48, },
253 { .bitrate = 360, .hw_value = 72, },
254 { .bitrate = 480, .hw_value = 96, },
255 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 256 { .bitrate = 720, .hw_value = 144, },
257};
258
a66098da
LB		 259/* Set or get info from Firmware */
260#define MWL8K_CMD_SET 0x0001
261#define MWL8K_CMD_GET 0x0000
262
263/* Firmware command codes */
264#define MWL8K_CMD_CODE_DNLD 0x0001
265#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 266#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 267#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
268#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 269#define MWL8K_CMD_RADIO_CONTROL 0x001c
270#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 271#define MWL8K_CMD_RF_ANTENNA 0x0020
b64fe619 272#define MWL8K_CMD_SET_BEACON 0x0100
a66098da
LB		 273#define MWL8K_CMD_SET_PRE_SCAN 0x0107
274#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 275#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
276#define MWL8K_CMD_SET_AID 0x010d
277#define MWL8K_CMD_SET_RATE 0x0110
278#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
279#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 280#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 281#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
282#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 283#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 284#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 285#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 286#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 287#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
b64fe619 288#define MWL8K_CMD_BSS_START 0x1100
3f5610ff 289#define MWL8K_CMD_SET_NEW_STN 0x1111
ff45fc60 290#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 291
292static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
293{
294#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
295 snprintf(buf, bufsize, "%s", #x);\
296 return buf;\
297 } while (0)
ce9e2e1b 298 switch (cmd & ~0x8000) {
a66098da
LB		 299 MWL8K_CMDNAME(CODE_DNLD);
300 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 301 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 302 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
303 MWL8K_CMDNAME(GET_STAT);
304 MWL8K_CMDNAME(RADIO_CONTROL);
305 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 306 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 307 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 308 MWL8K_CMDNAME(SET_PRE_SCAN);
309 MWL8K_CMDNAME(SET_POST_SCAN);
310 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 311 MWL8K_CMDNAME(SET_AID);
312 MWL8K_CMDNAME(SET_RATE);
313 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
314 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 315 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 316 MWL8K_CMDNAME(SET_EDCA_PARAMS);
317 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 318 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 319 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 320 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 321 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 322 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 323 MWL8K_CMDNAME(BSS_START);
3f5610ff 324 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 325 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 326 default:
327 snprintf(buf, bufsize, "0x%x", cmd);
328 }
329#undef MWL8K_CMDNAME
330
331 return buf;
332}
333
334/* Hardware and firmware reset */
335static void mwl8k_hw_reset(struct mwl8k_priv *priv)
336{
337 iowrite32(MWL8K_H2A_INT_RESET,
338 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
339 iowrite32(MWL8K_H2A_INT_RESET,
340 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
341 msleep(20);
342}
343
344/* Release fw image */
345static void mwl8k_release_fw(struct firmware **fw)
346{
347 if (*fw == NULL)
348 return;
349 release_firmware(*fw);
350 *fw = NULL;
351}
352
353static void mwl8k_release_firmware(struct mwl8k_priv *priv)
354{
22be40d9
LB		 355 mwl8k_release_fw(&priv->fw_ucode);
356 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 357}
358
359/* Request fw image */
360static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 361 const char *fname, struct firmware **fw)
a66098da
LB		 362{
363 /* release current image */
364 if (*fw != NULL)
365 mwl8k_release_fw(fw);
366
367 return request_firmware((const struct firmware **)fw,
c2c357ce 368 fname, &priv->pdev->dev);
a66098da
LB		 369}
370
45a390dd 371static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 372{
a74b295e 373 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 374 int rc;
375
a74b295e 376 if (di->helper_image != NULL) {
22be40d9 377 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
a74b295e
LB		 378 if (rc) {
379 printk(KERN_ERR "%s: Error requesting helper "
380 "firmware file %s\n", pci_name(priv->pdev),
381 di->helper_image);
382 return rc;
383 }
a66098da
LB		 384 }
385
22be40d9 386 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 387 if (rc) {
c2c357ce 388 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 389 pci_name(priv->pdev), di->fw_image);
22be40d9 390 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 391 return rc;
392 }
393
394 return 0;
395}
396
7e75b942
BH		 397MODULE_FIRMWARE("mwl8k/helper_8687.fw");
398MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
399
a66098da
LB		 400struct mwl8k_cmd_pkt {
401 __le16 code;
402 __le16 length;
403 __le16 seq_num;
404 __le16 result;
405 char payload[0];
406} __attribute__((packed));
407
408/*
409 * Firmware loading.
410 */
411static int
412mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
413{
414 void __iomem *regs = priv->regs;
415 dma_addr_t dma_addr;
a66098da
LB		 416 int loops;
417
418 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
419 if (pci_dma_mapping_error(priv->pdev, dma_addr))
420 return -ENOMEM;
421
422 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
423 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
424 iowrite32(MWL8K_H2A_INT_DOORBELL,
425 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
426 iowrite32(MWL8K_H2A_INT_DUMMY,
427 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
428
a66098da
LB		 429 loops = 1000;
430 do {
431 u32 int_code;
432
433 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
434 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
435 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 436 break;
437 }
438
3d76e82c 439 cond_resched();
a66098da
LB		 440 udelay(1);
441 } while (--loops);
442
443 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
444
d4b70570 445 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 446}
447
448static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
449 const u8 *data, size_t length)
450{
451 struct mwl8k_cmd_pkt *cmd;
452 int done;
453 int rc = 0;
454
455 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
456 if (cmd == NULL)
457 return -ENOMEM;
458
459 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
460 cmd->seq_num = 0;
461 cmd->result = 0;
462
463 done = 0;
464 while (length) {
465 int block_size = length > 256 ? 256 : length;
466
467 memcpy(cmd->payload, data + done, block_size);
468 cmd->length = cpu_to_le16(block_size);
469
470 rc = mwl8k_send_fw_load_cmd(priv, cmd,
471 sizeof(*cmd) + block_size);
472 if (rc)
473 break;
474
475 done += block_size;
476 length -= block_size;
477 }
478
479 if (!rc) {
480 cmd->length = 0;
481 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
482 }
483
484 kfree(cmd);
485
486 return rc;
487}
488
489static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
490 const u8 *data, size_t length)
491{
492 unsigned char *buffer;
493 int may_continue, rc = 0;
494 u32 done, prev_block_size;
495
496 buffer = kmalloc(1024, GFP_KERNEL);
497 if (buffer == NULL)
498 return -ENOMEM;
499
500 done = 0;
501 prev_block_size = 0;
502 may_continue = 1000;
503 while (may_continue > 0) {
504 u32 block_size;
505
506 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
507 if (block_size & 1) {
508 block_size &= ~1;
509 may_continue--;
510 } else {
511 done += prev_block_size;
512 length -= prev_block_size;
513 }
514
515 if (block_size > 1024 || block_size > length) {
516 rc = -EOVERFLOW;
517 break;
518 }
519
520 if (length == 0) {
521 rc = 0;
522 break;
523 }
524
525 if (block_size == 0) {
526 rc = -EPROTO;
527 may_continue--;
528 udelay(1);
529 continue;
530 }
531
532 prev_block_size = block_size;
533 memcpy(buffer, data + done, block_size);
534
535 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
536 if (rc)
537 break;
538 }
539
540 if (!rc && length != 0)
541 rc = -EREMOTEIO;
542
543 kfree(buffer);
544
545 return rc;
546}
547
c2c357ce 548static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 549{
c2c357ce 550 struct mwl8k_priv *priv = hw->priv;
22be40d9 551 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 552 int rc;
553 int loops;
554
555 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 556 struct firmware *helper = priv->fw_helper;
a66098da 557
c2c357ce
LB		 558 if (helper == NULL) {
559 printk(KERN_ERR "%s: helper image needed but none "
560 "given\n", pci_name(priv->pdev));
561 return -EINVAL;
562 }
a66098da 563
c2c357ce 564 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 565 if (rc) {
566 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 567 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 568 return rc;
569 }
89b872e2 570 msleep(5);
a66098da 571
c2c357ce 572 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 573 } else {
c2c357ce 574 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 575 }
576
577 if (rc) {
c2c357ce
LB		 578 printk(KERN_ERR "%s: unable to load firmware image\n",
579 pci_name(priv->pdev));
a66098da
LB		 580 return rc;
581 }
582
89a91f4f 583 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 584
89b872e2 585 loops = 500000;
a66098da 586 do {
eae74e65
LB		 587 u32 ready_code;
588
589 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
590 if (ready_code == MWL8K_FWAP_READY) {
591 priv->ap_fw = 1;
592 break;
593 } else if (ready_code == MWL8K_FWSTA_READY) {
594 priv->ap_fw = 0;
a66098da 595 break;
eae74e65
LB		 596 }
597
598 cond_resched();
a66098da
LB		 599 udelay(1);
600 } while (--loops);
601
602 return loops ? 0 : -ETIMEDOUT;
603}
604
605
a66098da
LB		 606/* DMA header used by firmware and hardware. */
607struct mwl8k_dma_data {
608 __le16 fwlen;
609 struct ieee80211_hdr wh;
20f09c3d 610 char data[0];
a66098da
LB		 611} __attribute__((packed));
612
613/* Routines to add/remove DMA header from skb. */
20f09c3d 614static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 615{
20f09c3d
LB		 616 struct mwl8k_dma_data *tr;
617 int hdrlen;
618
619 tr = (struct mwl8k_dma_data *)skb->data;
620 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
621
622 if (hdrlen != sizeof(tr->wh)) {
623 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
624 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
625 *((__le16 *)(tr->data - 2)) = qos;
626 } else {
627 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
628 }
a66098da 629 }
20f09c3d
LB		 630
631 if (hdrlen != sizeof(*tr))
632 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 633}
634
76266b2a 635static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 636{
637 struct ieee80211_hdr *wh;
ca009301 638 int hdrlen;
a66098da
LB		 639 struct mwl8k_dma_data *tr;
640
ca009301
LB		 641 /*
642 * Add a firmware DMA header; the firmware requires that we
643 * present a 2-byte payload length followed by a 4-address
644 * header (without QoS field), followed (optionally) by any
645 * WEP/ExtIV header (but only filled in for CCMP).
646 */
a66098da 647 wh = (struct ieee80211_hdr *)skb->data;
ca009301 648
a66098da 649 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 650 if (hdrlen != sizeof(*tr))
651 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 652
ca009301
LB		 653 if (ieee80211_is_data_qos(wh->frame_control))
654 hdrlen -= 2;
a66098da
LB		 655
656 tr = (struct mwl8k_dma_data *)skb->data;
657 if (wh != &tr->wh)
658 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 659 if (hdrlen != sizeof(tr->wh))
660 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 661
662 /*
663 * Firmware length is the length of the fully formed "802.11
664 * payload". That is, everything except for the 802.11 header.
665 * This includes all crypto material including the MIC.
666 */
ca009301 667 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 668}
669
670
671/*
89a91f4f 672 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 673 */
89a91f4f 674struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 675 __le16 pkt_len;
676 __u8 sq2;
677 __u8 rate;
678 __le32 pkt_phys_addr;
679 __le32 next_rxd_phys_addr;
680 __le16 qos_control;
681 __le16 htsig2;
682 __le32 hw_rssi_info;
683 __le32 hw_noise_floor_info;
684 __u8 noise_floor;
685 __u8 pad0[3];
686 __u8 rssi;
687 __u8 rx_status;
688 __u8 channel;
689 __u8 rx_ctrl;
690} __attribute__((packed));
691
89a91f4f
LB		 692#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
693#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
694#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 695
89a91f4f 696#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 697
89a91f4f 698static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 699{
89a91f4f 700 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 701
702 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 703 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 704}
705
89a91f4f 706static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 707{
89a91f4f 708 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 709
710 rxd->pkt_len = cpu_to_le16(len);
711 rxd->pkt_phys_addr = cpu_to_le32(addr);
712 wmb();
713 rxd->rx_ctrl = 0;
714}
715
716static int
89a91f4f
LB		 717mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
718 __le16 *qos)
6f6d1e9a 719{
89a91f4f 720 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 721
89a91f4f 722 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 723 return -1;
724 rmb();
725
726 memset(status, 0, sizeof(*status));
727
728 status->signal = -rxd->rssi;
729 status->noise = -rxd->noise_floor;
730
89a91f4f 731 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 732 status->flag |= RX_FLAG_HT;
89a91f4f 733 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 734 status->flag |= RX_FLAG_40MHZ;
89a91f4f 735 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 736 } else {
737 int i;
738
739 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
740 if (mwl8k_rates[i].hw_value == rxd->rate) {
741 status->rate_idx = i;
742 break;
743 }
744 }
745 }
746
747 status->band = IEEE80211_BAND_2GHZ;
748 status->freq = ieee80211_channel_to_frequency(rxd->channel);
749
20f09c3d
LB		 750 *qos = rxd->qos_control;
751
6f6d1e9a
LB		 752 return le16_to_cpu(rxd->pkt_len);
753}
754
89a91f4f
LB		 755static struct rxd_ops rxd_8366_ap_ops = {
756 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
757 .rxd_init = mwl8k_rxd_8366_ap_init,
758 .rxd_refill = mwl8k_rxd_8366_ap_refill,
759 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 760};
761
762/*
89a91f4f 763 * Packet reception for STA firmware.
a66098da 764 */
89a91f4f 765struct mwl8k_rxd_sta {
a66098da
LB		 766 __le16 pkt_len;
767 __u8 link_quality;
768 __u8 noise_level;
769 __le32 pkt_phys_addr;
45eb400d 770 __le32 next_rxd_phys_addr;
a66098da
LB		 771 __le16 qos_control;
772 __le16 rate_info;
773 __le32 pad0[4];
774 __u8 rssi;
775 __u8 channel;
776 __le16 pad1;
777 __u8 rx_ctrl;
778 __u8 rx_status;
779 __u8 pad2[2];
780} __attribute__((packed));
781
89a91f4f
LB		 782#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
783#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
784#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
785#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
786#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
787#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 788
89a91f4f 789#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 790
89a91f4f 791static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 792{
89a91f4f 793 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 794
795 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 796 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 797}
798
89a91f4f 799static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 800{
89a91f4f 801 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 802
803 rxd->pkt_len = cpu_to_le16(len);
804 rxd->pkt_phys_addr = cpu_to_le32(addr);
805 wmb();
806 rxd->rx_ctrl = 0;
807}
808
809static int
89a91f4f 810mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 811 __le16 *qos)
54bc3a0d 812{
89a91f4f 813 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 814 u16 rate_info;
815
89a91f4f 816 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 817 return -1;
818 rmb();
819
820 rate_info = le16_to_cpu(rxd->rate_info);
821
822 memset(status, 0, sizeof(*status));
823
824 status->signal = -rxd->rssi;
825 status->noise = -rxd->noise_level;
89a91f4f
LB		 826 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
827 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 828
89a91f4f 829 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 830 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 831 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 832 status->flag |= RX_FLAG_40MHZ;
89a91f4f 833 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 834 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 835 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 836 status->flag |= RX_FLAG_HT;
837
838 status->band = IEEE80211_BAND_2GHZ;
839 status->freq = ieee80211_channel_to_frequency(rxd->channel);
840
20f09c3d
LB		 841 *qos = rxd->qos_control;
842
54bc3a0d
LB		 843 return le16_to_cpu(rxd->pkt_len);
844}
845
89a91f4f
LB		 846static struct rxd_ops rxd_sta_ops = {
847 .rxd_size = sizeof(struct mwl8k_rxd_sta),
848 .rxd_init = mwl8k_rxd_sta_init,
849 .rxd_refill = mwl8k_rxd_sta_refill,
850 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 851};
852
853
a66098da
LB		 854#define MWL8K_RX_DESCS 256
855#define MWL8K_RX_MAXSZ 3800
856
857static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
858{
859 struct mwl8k_priv *priv = hw->priv;
860 struct mwl8k_rx_queue *rxq = priv->rxq + index;
861 int size;
862 int i;
863
45eb400d
LB		 864 rxq->rxd_count = 0;
865 rxq->head = 0;
866 rxq->tail = 0;
a66098da 867
54bc3a0d 868 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 869
45eb400d
LB		 870 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
871 if (rxq->rxd == NULL) {
a66098da 872 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 873 wiphy_name(hw->wiphy));
a66098da
LB		 874 return -ENOMEM;
875 }
45eb400d 876 memset(rxq->rxd, 0, size);
a66098da 877
788838eb
LB		 878 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
879 if (rxq->buf == NULL) {
a66098da 880 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 881 wiphy_name(hw->wiphy));
45eb400d 882 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 883 return -ENOMEM;
884 }
788838eb 885 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 886
887 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 888 int desc_size;
889 void *rxd;
a66098da 890 int nexti;
54bc3a0d
LB		 891 dma_addr_t next_dma_addr;
892
893 desc_size = priv->rxd_ops->rxd_size;
894 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 895
54bc3a0d
LB		 896 nexti = i + 1;
897 if (nexti == MWL8K_RX_DESCS)
898 nexti = 0;
899 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 900
54bc3a0d 901 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 902 }
903
904 return 0;
905}
906
907static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
908{
909 struct mwl8k_priv *priv = hw->priv;
910 struct mwl8k_rx_queue *rxq = priv->rxq + index;
911 int refilled;
912
913 refilled = 0;
45eb400d 914 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 915 struct sk_buff *skb;
788838eb 916 dma_addr_t addr;
a66098da 917 int rx;
54bc3a0d 918 void *rxd;
a66098da
LB		 919
920 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
921 if (skb == NULL)
922 break;
923
788838eb
LB		 924 addr = pci_map_single(priv->pdev, skb->data,
925 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 926
54bc3a0d
LB		 927 rxq->rxd_count++;
928 rx = rxq->tail++;
929 if (rxq->tail == MWL8K_RX_DESCS)
930 rxq->tail = 0;
788838eb
LB		 931 rxq->buf[rx].skb = skb;
932 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 933
934 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
935 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 936
937 refilled++;
938 }
939
940 return refilled;
941}
942
943/* Must be called only when the card's reception is completely halted */
944static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
945{
946 struct mwl8k_priv *priv = hw->priv;
947 struct mwl8k_rx_queue *rxq = priv->rxq + index;
948 int i;
949
950 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 951 if (rxq->buf[i].skb != NULL) {
952 pci_unmap_single(priv->pdev,
953 pci_unmap_addr(&rxq->buf[i], dma),
954 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
955 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
956
957 kfree_skb(rxq->buf[i].skb);
958 rxq->buf[i].skb = NULL;
a66098da
LB		 959 }
960 }
961
788838eb
LB		 962 kfree(rxq->buf);
963 rxq->buf = NULL;
a66098da
LB		 964
965 pci_free_consistent(priv->pdev,
54bc3a0d 966 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 967 rxq->rxd, rxq->rxd_dma);
968 rxq->rxd = NULL;
a66098da
LB		 969}
970
971
972/*
973 * Scan a list of BSSIDs to process for finalize join.
974 * Allows for extension to process multiple BSSIDs.
975 */
976static inline int
977mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
978{
979 return priv->capture_beacon &&
980 ieee80211_is_beacon(wh->frame_control) &&
981 !compare_ether_addr(wh->addr3, priv->capture_bssid);
982}
983
3779752d
LB		 984static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
985 struct sk_buff *skb)
a66098da 986{
3779752d
LB		 987 struct mwl8k_priv *priv = hw->priv;
988
a66098da 989 priv->capture_beacon = false;
d89173f2 990 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 991
992 /*
993 * Use GFP_ATOMIC as rxq_process is called from
994 * the primary interrupt handler, memory allocation call
995 * must not sleep.
996 */
997 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
998 if (priv->beacon_skb != NULL)
3779752d 999 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1000}
1001
1002static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1003{
1004 struct mwl8k_priv *priv = hw->priv;
1005 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1006 int processed;
1007
1008 processed = 0;
45eb400d 1009 while (rxq->rxd_count && limit--) {
a66098da 1010 struct sk_buff *skb;
54bc3a0d
LB		 1011 void *rxd;
1012 int pkt_len;
a66098da 1013 struct ieee80211_rx_status status;
20f09c3d 1014 __le16 qos;
a66098da 1015
788838eb 1016 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1017 if (skb == NULL)
1018 break;
54bc3a0d
LB		 1019
1020 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1021
20f09c3d 1022 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1023 if (pkt_len < 0)
1024 break;
1025
788838eb
LB		 1026 rxq->buf[rxq->head].skb = NULL;
1027
1028 pci_unmap_single(priv->pdev,
1029 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1030 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1031 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1032
54bc3a0d
LB		 1033 rxq->head++;
1034 if (rxq->head == MWL8K_RX_DESCS)
1035 rxq->head = 0;
1036
45eb400d 1037 rxq->rxd_count--;
a66098da 1038
54bc3a0d 1039 skb_put(skb, pkt_len);
20f09c3d 1040 mwl8k_remove_dma_header(skb, qos);
a66098da 1041
a66098da 1042 /*
c2c357ce
LB		 1043 * Check for a pending join operation. Save a
1044 * copy of the beacon and schedule a tasklet to
1045 * send a FINALIZE_JOIN command to the firmware.
a66098da 1046 */
54bc3a0d 1047 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1048 mwl8k_save_beacon(hw, skb);
a66098da 1049
f1d58c25
JB		 1050 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1051 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1052
1053 processed++;
1054 }
1055
1056 return processed;
1057}
1058
1059
1060/*
1061 * Packet transmission.
1062 */
1063
a66098da
LB		 1064#define MWL8K_TXD_STATUS_OK 0x00000001
1065#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1066#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1067#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1068#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1069
e0493a8d
LB		 1070#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1071#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1072#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1073#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1074#define MWL8K_QOS_EOSP 0x0010
1075
a66098da
LB		 1076struct mwl8k_tx_desc {
1077 __le32 status;
1078 __u8 data_rate;
1079 __u8 tx_priority;
1080 __le16 qos_control;
1081 __le32 pkt_phys_addr;
1082 __le16 pkt_len;
d89173f2 1083 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1084 __le32 next_txd_phys_addr;
a66098da
LB		 1085 __le32 reserved;
1086 __le16 rate_info;
1087 __u8 peer_id;
1088 __u8 tx_frag_cnt;
1089} __attribute__((packed));
1090
1091#define MWL8K_TX_DESCS 128
1092
1093static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1094{
1095 struct mwl8k_priv *priv = hw->priv;
1096 struct mwl8k_tx_queue *txq = priv->txq + index;
1097 int size;
1098 int i;
1099
45eb400d
LB		 1100 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1101 txq->stats.limit = MWL8K_TX_DESCS;
1102 txq->head = 0;
1103 txq->tail = 0;
a66098da
LB		 1104
1105 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1106
45eb400d
LB		 1107 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1108 if (txq->txd == NULL) {
a66098da 1109 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1110 wiphy_name(hw->wiphy));
a66098da
LB		 1111 return -ENOMEM;
1112 }
45eb400d 1113 memset(txq->txd, 0, size);
a66098da 1114
45eb400d
LB		 1115 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1116 if (txq->skb == NULL) {
a66098da 1117 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1118 wiphy_name(hw->wiphy));
45eb400d 1119 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1120 return -ENOMEM;
1121 }
45eb400d 1122 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1123
1124 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1125 struct mwl8k_tx_desc *tx_desc;
1126 int nexti;
1127
45eb400d 1128 tx_desc = txq->txd + i;
a66098da
LB		 1129 nexti = (i + 1) % MWL8K_TX_DESCS;
1130
1131 tx_desc->status = 0;
45eb400d
LB		 1132 tx_desc->next_txd_phys_addr =
1133 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1134 }
1135
1136 return 0;
1137}
1138
1139static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1140{
1141 iowrite32(MWL8K_H2A_INT_PPA_READY,
1142 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1143 iowrite32(MWL8K_H2A_INT_DUMMY,
1144 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1145 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1146}
1147
7e1112d3 1148static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1149{
7e1112d3
LB		 1150 struct mwl8k_priv *priv = hw->priv;
1151 int i;
1152
1153 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1154 struct mwl8k_tx_queue *txq = priv->txq + i;
1155 int fw_owned = 0;
1156 int drv_owned = 0;
1157 int unused = 0;
1158 int desc;
1159
a66098da 1160 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1161 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1162 u32 status;
a66098da 1163
7e1112d3 1164 status = le32_to_cpu(tx_desc->status);
a66098da 1165 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1166 fw_owned++;
a66098da 1167 else
7e1112d3 1168 drv_owned++;
a66098da
LB		 1169
1170 if (tx_desc->pkt_len == 0)
7e1112d3 1171 unused++;
a66098da 1172 }
a66098da 1173
7e1112d3
LB		 1174 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1175 "fw_owned=%d drv_owned=%d unused=%d\n",
1176 wiphy_name(hw->wiphy), i,
1177 txq->stats.len, txq->head, txq->tail,
1178 fw_owned, drv_owned, unused);
1179 }
a66098da
LB		 1180}
1181
618952a7 1182/*
88de754a 1183 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1184 */
62abd3cf 1185#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1186
950d5b01 1187static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1188{
a66098da 1189 struct mwl8k_priv *priv = hw->priv;
88de754a 1190 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1191 int retry;
1192 int rc;
a66098da
LB		 1193
1194 might_sleep();
1195
7e1112d3
LB		 1196 /*
1197 * The TX queues are stopped at this point, so this test
1198 * doesn't need to take ->tx_lock.
1199 */
1200 if (!priv->pending_tx_pkts)
1201 return 0;
1202
1203 retry = 0;
1204 rc = 0;
1205
a66098da 1206 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1207 priv->tx_wait = &tx_wait;
1208 while (!rc) {
1209 int oldcount;
1210 unsigned long timeout;
a66098da 1211
7e1112d3 1212 oldcount = priv->pending_tx_pkts;
a66098da 1213
7e1112d3 1214 spin_unlock_bh(&priv->tx_lock);
88de754a 1215 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1216 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1217 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1218
1219 if (timeout) {
1220 WARN_ON(priv->pending_tx_pkts);
1221 if (retry) {
1222 printk(KERN_NOTICE "%s: tx rings drained\n",
1223 wiphy_name(hw->wiphy));
1224 }
1225 break;
1226 }
1227
1228 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB		 1229 printk(KERN_NOTICE "%s: waiting for tx rings "
1230 "to drain (%d -> %d pkts)\n",
7e1112d3
LB		 1231 wiphy_name(hw->wiphy), oldcount,
1232 priv->pending_tx_pkts);
1233 retry = 1;
1234 continue;
1235 }
1236
a66098da 1237 priv->tx_wait = NULL;
a66098da 1238
7e1112d3
LB		 1239 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1240 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1241 mwl8k_dump_tx_rings(hw);
1242
1243 rc = -ETIMEDOUT;
a66098da 1244 }
7e1112d3 1245 spin_unlock_bh(&priv->tx_lock);
a66098da 1246
7e1112d3 1247 return rc;
a66098da
LB		 1248}
1249
c23b5a69
LB		 1250#define MWL8K_TXD_SUCCESS(status) \
1251 ((status) & (MWL8K_TXD_STATUS_OK | \
1252 MWL8K_TXD_STATUS_OK_RETRY | \
1253 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1254
efb7c49a
LB		 1255static int
1256mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1257{
1258 struct mwl8k_priv *priv = hw->priv;
1259 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1260 int processed;
a66098da 1261
efb7c49a
LB		 1262 processed = 0;
1263 while (txq->stats.len > 0 && limit--) {
a66098da 1264 int tx;
a66098da
LB		 1265 struct mwl8k_tx_desc *tx_desc;
1266 unsigned long addr;
ce9e2e1b 1267 int size;
a66098da
LB		 1268 struct sk_buff *skb;
1269 struct ieee80211_tx_info *info;
1270 u32 status;
1271
45eb400d
LB		 1272 tx = txq->head;
1273 tx_desc = txq->txd + tx;
a66098da
LB		 1274
1275 status = le32_to_cpu(tx_desc->status);
1276
1277 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1278 if (!force)
1279 break;
1280 tx_desc->status &=
1281 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1282 }
1283
45eb400d
LB		 1284 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1285 BUG_ON(txq->stats.len == 0);
1286 txq->stats.len--;
a66098da
LB		 1287 priv->pending_tx_pkts--;
1288
1289 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1290 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1291 skb = txq->skb[tx];
1292 txq->skb[tx] = NULL;
a66098da
LB		 1293
1294 BUG_ON(skb == NULL);
1295 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1296
20f09c3d 1297 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1298
1299 /* Mark descriptor as unused */
1300 tx_desc->pkt_phys_addr = 0;
1301 tx_desc->pkt_len = 0;
1302
a66098da
LB		 1303 info = IEEE80211_SKB_CB(skb);
1304 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1305 if (MWL8K_TXD_SUCCESS(status))
a66098da 1306 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1307
1308 ieee80211_tx_status_irqsafe(hw, skb);
1309
efb7c49a 1310 processed++;
a66098da
LB		 1311 }
1312
efb7c49a 1313 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1314 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1315
1316 return processed;
a66098da
LB		 1317}
1318
1319/* must be called only when the card's transmit is completely halted */
1320static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1321{
1322 struct mwl8k_priv *priv = hw->priv;
1323 struct mwl8k_tx_queue *txq = priv->txq + index;
1324
efb7c49a 1325 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1326
45eb400d
LB		 1327 kfree(txq->skb);
1328 txq->skb = NULL;
a66098da
LB		 1329
1330 pci_free_consistent(priv->pdev,
1331 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1332 txq->txd, txq->txd_dma);
1333 txq->txd = NULL;
a66098da
LB		 1334}
1335
1336static int
1337mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1338{
1339 struct mwl8k_priv *priv = hw->priv;
1340 struct ieee80211_tx_info *tx_info;
23b33906 1341 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1342 struct ieee80211_hdr *wh;
1343 struct mwl8k_tx_queue *txq;
1344 struct mwl8k_tx_desc *tx;
a66098da 1345 dma_addr_t dma;
23b33906
LB		 1346 u32 txstatus;
1347 u8 txdatarate;
1348 u16 qos;
a66098da 1349
23b33906
LB		 1350 wh = (struct ieee80211_hdr *)skb->data;
1351 if (ieee80211_is_data_qos(wh->frame_control))
1352 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1353 else
1354 qos = 0;
a66098da 1355
76266b2a 1356 mwl8k_add_dma_header(skb);
23b33906 1357 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1358
1359 tx_info = IEEE80211_SKB_CB(skb);
1360 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1361
1362 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1363 u16 seqno = mwl8k_vif->seqno;
23b33906 1364
a66098da
LB		 1365 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1366 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1367 mwl8k_vif->seqno = seqno++ % 4096;
1368 }
1369
23b33906
LB		 1370 /* Setup firmware control bit fields for each frame type. */
1371 txstatus = 0;
1372 txdatarate = 0;
1373 if (ieee80211_is_mgmt(wh->frame_control) ||
1374 ieee80211_is_ctl(wh->frame_control)) {
1375 txdatarate = 0;
e0493a8d 1376 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1377 } else if (ieee80211_is_data(wh->frame_control)) {
1378 txdatarate = 1;
1379 if (is_multicast_ether_addr(wh->addr1))
1380 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1381
e0493a8d 1382 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1383 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1384 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1385 else
e0493a8d 1386 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1387 }
a66098da
LB		 1388
1389 dma = pci_map_single(priv->pdev, skb->data,
1390 skb->len, PCI_DMA_TODEVICE);
1391
1392 if (pci_dma_mapping_error(priv->pdev, dma)) {
1393 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1394 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1395 dev_kfree_skb(skb);
a66098da
LB		 1396 return NETDEV_TX_OK;
1397 }
1398
23b33906 1399 spin_lock_bh(&priv->tx_lock);
a66098da 1400
23b33906 1401 txq = priv->txq + index;
a66098da 1402
45eb400d
LB		 1403 BUG_ON(txq->skb[txq->tail] != NULL);
1404 txq->skb[txq->tail] = skb;
a66098da 1405
45eb400d 1406 tx = txq->txd + txq->tail;
23b33906
LB		 1407 tx->data_rate = txdatarate;
1408 tx->tx_priority = index;
a66098da 1409 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1410 tx->pkt_phys_addr = cpu_to_le32(dma);
1411 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1412 tx->rate_info = 0;
a680400e
LB		 1413 if (!priv->ap_fw && tx_info->control.sta != NULL)
1414 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1415 else
1416 tx->peer_id = 0;
a66098da 1417 wmb();
23b33906
LB		 1418 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1419
45eb400d
LB		 1420 txq->stats.count++;
1421 txq->stats.len++;
a66098da 1422 priv->pending_tx_pkts++;
a66098da 1423
45eb400d
LB		 1424 txq->tail++;
1425 if (txq->tail == MWL8K_TX_DESCS)
1426 txq->tail = 0;
23b33906 1427
45eb400d 1428 if (txq->head == txq->tail)
a66098da
LB		 1429 ieee80211_stop_queue(hw, index);
1430
23b33906 1431 mwl8k_tx_start(priv);
a66098da
LB		 1432
1433 spin_unlock_bh(&priv->tx_lock);
1434
1435 return NETDEV_TX_OK;
1436}
1437
1438
618952a7
LB		 1439/*
1440 * Firmware access.
1441 *
1442 * We have the following requirements for issuing firmware commands:
1443 * - Some commands require that the packet transmit path is idle when
1444 * the command is issued. (For simplicity, we'll just quiesce the
1445 * transmit path for every command.)
1446 * - There are certain sequences of commands that need to be issued to
1447 * the hardware sequentially, with no other intervening commands.
1448 *
1449 * This leads to an implementation of a "firmware lock" as a mutex that
1450 * can be taken recursively, and which is taken by both the low-level
1451 * command submission function (mwl8k_post_cmd) as well as any users of
1452 * that function that require issuing of an atomic sequence of commands,
1453 * and quiesces the transmit path whenever it's taken.
1454 */
1455static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1456{
1457 struct mwl8k_priv *priv = hw->priv;
1458
1459 if (priv->fw_mutex_owner != current) {
1460 int rc;
1461
1462 mutex_lock(&priv->fw_mutex);
1463 ieee80211_stop_queues(hw);
1464
1465 rc = mwl8k_tx_wait_empty(hw);
1466 if (rc) {
1467 ieee80211_wake_queues(hw);
1468 mutex_unlock(&priv->fw_mutex);
1469
1470 return rc;
1471 }
1472
1473 priv->fw_mutex_owner = current;
1474 }
1475
1476 priv->fw_mutex_depth++;
1477
1478 return 0;
1479}
1480
1481static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1482{
1483 struct mwl8k_priv *priv = hw->priv;
1484
1485 if (!--priv->fw_mutex_depth) {
1486 ieee80211_wake_queues(hw);
1487 priv->fw_mutex_owner = NULL;
1488 mutex_unlock(&priv->fw_mutex);
1489 }
1490}
1491
1492
a66098da
LB		 1493/*
1494 * Command processing.
1495 */
1496
0c9cc640
LB		 1497/* Timeout firmware commands after 10s */
1498#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1499
1500static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1501{
1502 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1503 struct mwl8k_priv *priv = hw->priv;
1504 void __iomem *regs = priv->regs;
1505 dma_addr_t dma_addr;
1506 unsigned int dma_size;
1507 int rc;
a66098da
LB		 1508 unsigned long timeout = 0;
1509 u8 buf[32];
1510
c2c357ce 1511 cmd->result = 0xffff;
a66098da
LB		 1512 dma_size = le16_to_cpu(cmd->length);
1513 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1514 PCI_DMA_BIDIRECTIONAL);
1515 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1516 return -ENOMEM;
1517
618952a7 1518 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1519 if (rc) {
1520 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1521 PCI_DMA_BIDIRECTIONAL);
618952a7 1522 return rc;
39a1e42e 1523 }
a66098da 1524
a66098da
LB		 1525 priv->hostcmd_wait = &cmd_wait;
1526 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1527 iowrite32(MWL8K_H2A_INT_DOORBELL,
1528 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1529 iowrite32(MWL8K_H2A_INT_DUMMY,
1530 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1531
1532 timeout = wait_for_completion_timeout(&cmd_wait,
1533 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1534
618952a7
LB		 1535 priv->hostcmd_wait = NULL;
1536
1537 mwl8k_fw_unlock(hw);
1538
37055bd4
LB		 1539 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1540 PCI_DMA_BIDIRECTIONAL);
1541
a66098da 1542 if (!timeout) {
a66098da 1543 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1544 wiphy_name(hw->wiphy),
a66098da
LB		 1545 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1546 MWL8K_CMD_TIMEOUT_MS);
1547 rc = -ETIMEDOUT;
1548 } else {
0c9cc640
LB		 1549 int ms;
1550
1551 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1552
ce9e2e1b 1553 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1554 if (rc)
1555 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1556 wiphy_name(hw->wiphy),
a66098da 1557 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1558 le16_to_cpu(cmd->result));
0c9cc640
LB		 1559 else if (ms > 2000)
1560 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1561 wiphy_name(hw->wiphy),
1562 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1563 ms);
a66098da
LB		 1564 }
1565
a66098da
LB		 1566 return rc;
1567}
1568
1569/*
04b147b1 1570 * CMD_GET_HW_SPEC (STA version).
a66098da 1571 */
04b147b1 1572struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1573 struct mwl8k_cmd_pkt header;
1574 __u8 hw_rev;
1575 __u8 host_interface;
1576 __le16 num_mcaddrs;
d89173f2 1577 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1578 __le16 region_code;
1579 __le32 fw_rev;
1580 __le32 ps_cookie;
1581 __le32 caps;
1582 __u8 mcs_bitmap[16];
1583 __le32 rx_queue_ptr;
1584 __le32 num_tx_queues;
1585 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1586 __le32 caps2;
1587 __le32 num_tx_desc_per_queue;
45eb400d 1588 __le32 total_rxd;
a66098da
LB		 1589} __attribute__((packed));
1590
341c9791
LB		 1591#define MWL8K_CAP_MAX_AMSDU 0x20000000
1592#define MWL8K_CAP_GREENFIELD 0x08000000
1593#define MWL8K_CAP_AMPDU 0x04000000
1594#define MWL8K_CAP_RX_STBC 0x01000000
1595#define MWL8K_CAP_TX_STBC 0x00800000
1596#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1597#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1598#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1599#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1600#define MWL8K_CAP_DELAY_BA 0x00003000
1601#define MWL8K_CAP_MIMO 0x00000200
1602#define MWL8K_CAP_40MHZ 0x00000100
1603
1604static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
1605{
1606 struct mwl8k_priv *priv = hw->priv;
1607 int rx_streams;
1608 int tx_streams;
1609
1610 priv->band.ht_cap.ht_supported = 1;
1611
1612 if (cap & MWL8K_CAP_MAX_AMSDU)
1613 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
1614 if (cap & MWL8K_CAP_GREENFIELD)
1615 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
1616 if (cap & MWL8K_CAP_AMPDU) {
1617 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
1618 priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1619 priv->band.ht_cap.ampdu_density =
1620 IEEE80211_HT_MPDU_DENSITY_NONE;
1621 }
1622 if (cap & MWL8K_CAP_RX_STBC)
1623 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
1624 if (cap & MWL8K_CAP_TX_STBC)
1625 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
1626 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
1627 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
1628 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
1629 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
1630 if (cap & MWL8K_CAP_DELAY_BA)
1631 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
1632 if (cap & MWL8K_CAP_40MHZ)
1633 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
1634
1635 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1636 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1637
1638 priv->band.ht_cap.mcs.rx_mask[0] = 0xff;
1639 if (rx_streams >= 2)
1640 priv->band.ht_cap.mcs.rx_mask[1] = 0xff;
1641 if (rx_streams >= 3)
1642 priv->band.ht_cap.mcs.rx_mask[2] = 0xff;
1643 priv->band.ht_cap.mcs.rx_mask[4] = 0x01;
1644 priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1645
1646 if (rx_streams != tx_streams) {
1647 priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1648 priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) <<
1649 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1650 }
1651}
1652
04b147b1 1653static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1654{
1655 struct mwl8k_priv *priv = hw->priv;
04b147b1 1656 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1657 int rc;
1658 int i;
1659
1660 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1661 if (cmd == NULL)
1662 return -ENOMEM;
1663
1664 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1665 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1666
1667 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1668 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1669 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1670 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1671 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1672 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1673 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1674 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1675
1676 rc = mwl8k_post_cmd(hw, &cmd->header);
1677
1678 if (!rc) {
1679 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1680 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1681 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1682 priv->hw_rev = cmd->hw_rev;
341c9791
LB		 1683 if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
1684 mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
a66098da
LB		 1685 }
1686
1687 kfree(cmd);
1688 return rc;
1689}
1690
42fba21d
LB		 1691/*
1692 * CMD_GET_HW_SPEC (AP version).
1693 */
1694struct mwl8k_cmd_get_hw_spec_ap {
1695 struct mwl8k_cmd_pkt header;
1696 __u8 hw_rev;
1697 __u8 host_interface;
1698 __le16 num_wcb;
1699 __le16 num_mcaddrs;
1700 __u8 perm_addr[ETH_ALEN];
1701 __le16 region_code;
1702 __le16 num_antenna;
1703 __le32 fw_rev;
1704 __le32 wcbbase0;
1705 __le32 rxwrptr;
1706 __le32 rxrdptr;
1707 __le32 ps_cookie;
1708 __le32 wcbbase1;
1709 __le32 wcbbase2;
1710 __le32 wcbbase3;
1711} __attribute__((packed));
1712
1713static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1714{
1715 struct mwl8k_priv *priv = hw->priv;
1716 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1717 int rc;
1718
1719 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1720 if (cmd == NULL)
1721 return -ENOMEM;
1722
1723 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1724 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1725
1726 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1727 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1728
1729 rc = mwl8k_post_cmd(hw, &cmd->header);
1730
1731 if (!rc) {
1732 int off;
1733
1734 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1735 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1736 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1737 priv->hw_rev = cmd->hw_rev;
1738
1739 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1740 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1741
1742 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1743 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1744
1745 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1746 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1747
1748 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1749 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1750
1751 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1752 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1753
1754 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1755 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1756 }
1757
1758 kfree(cmd);
1759 return rc;
1760}
1761
1762/*
1763 * CMD_SET_HW_SPEC.
1764 */
1765struct mwl8k_cmd_set_hw_spec {
1766 struct mwl8k_cmd_pkt header;
1767 __u8 hw_rev;
1768 __u8 host_interface;
1769 __le16 num_mcaddrs;
1770 __u8 perm_addr[ETH_ALEN];
1771 __le16 region_code;
1772 __le32 fw_rev;
1773 __le32 ps_cookie;
1774 __le32 caps;
1775 __le32 rx_queue_ptr;
1776 __le32 num_tx_queues;
1777 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1778 __le32 flags;
1779 __le32 num_tx_desc_per_queue;
1780 __le32 total_rxd;
1781} __attribute__((packed));
1782
b64fe619
LB		 1783#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1784#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
1785#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 1786
1787static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1788{
1789 struct mwl8k_priv *priv = hw->priv;
1790 struct mwl8k_cmd_set_hw_spec *cmd;
1791 int rc;
1792 int i;
1793
1794 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1795 if (cmd == NULL)
1796 return -ENOMEM;
1797
1798 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1799 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1800
1801 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1802 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1803 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1804 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1805 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB		 1806 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
1807 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
1808 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 1809 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1810 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1811
1812 rc = mwl8k_post_cmd(hw, &cmd->header);
1813 kfree(cmd);
1814
1815 return rc;
1816}
1817
a66098da
LB		 1818/*
1819 * CMD_MAC_MULTICAST_ADR.
1820 */
1821struct mwl8k_cmd_mac_multicast_adr {
1822 struct mwl8k_cmd_pkt header;
1823 __le16 action;
1824 __le16 numaddr;
ce9e2e1b 1825 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1826};
1827
d5e30845
LB		 1828#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1829#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1830#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1831#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1832
e81cd2d6 1833static struct mwl8k_cmd_pkt *
447ced07 1834__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1835 int mc_count, struct dev_addr_list *mclist)
a66098da 1836{
e81cd2d6 1837 struct mwl8k_priv *priv = hw->priv;
a66098da 1838 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1839 int size;
e81cd2d6 1840
447ced07 1841 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1842 allmulti = 1;
1843 mc_count = 0;
1844 }
e81cd2d6
LB		 1845
1846 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1847
e81cd2d6 1848 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1849 if (cmd == NULL)
e81cd2d6 1850 return NULL;
a66098da
LB		 1851
1852 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1853 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1854 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1855 MWL8K_ENABLE_RX_BROADCAST);
1856
1857 if (allmulti) {
1858 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1859 } else if (mc_count) {
1860 int i;
1861
1862 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1863 cmd->numaddr = cpu_to_le16(mc_count);
1864 for (i = 0; i < mc_count && mclist; i++) {
1865 if (mclist->da_addrlen != ETH_ALEN) {
1866 kfree(cmd);
1867 return NULL;
1868 }
1869 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1870 mclist = mclist->next;
a66098da 1871 }
a66098da
LB		 1872 }
1873
e81cd2d6 1874 return &cmd->header;
a66098da
LB		 1875}
1876
1877/*
55489b6e 1878 * CMD_GET_STAT.
a66098da 1879 */
55489b6e 1880struct mwl8k_cmd_get_stat {
a66098da 1881 struct mwl8k_cmd_pkt header;
a66098da
LB		 1882 __le32 stats[64];
1883} __attribute__((packed));
1884
1885#define MWL8K_STAT_ACK_FAILURE 9
1886#define MWL8K_STAT_RTS_FAILURE 12
1887#define MWL8K_STAT_FCS_ERROR 24
1888#define MWL8K_STAT_RTS_SUCCESS 11
1889
55489b6e
LB		 1890static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1891 struct ieee80211_low_level_stats *stats)
a66098da 1892{
55489b6e 1893 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 1894 int rc;
1895
1896 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1897 if (cmd == NULL)
1898 return -ENOMEM;
1899
1900 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1901 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1902
1903 rc = mwl8k_post_cmd(hw, &cmd->header);
1904 if (!rc) {
1905 stats->dot11ACKFailureCount =
1906 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1907 stats->dot11RTSFailureCount =
1908 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1909 stats->dot11FCSErrorCount =
1910 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1911 stats->dot11RTSSuccessCount =
1912 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1913 }
1914 kfree(cmd);
1915
1916 return rc;
1917}
1918
1919/*
55489b6e 1920 * CMD_RADIO_CONTROL.
a66098da 1921 */
55489b6e 1922struct mwl8k_cmd_radio_control {
a66098da
LB		 1923 struct mwl8k_cmd_pkt header;
1924 __le16 action;
1925 __le16 control;
1926 __le16 radio_on;
1927} __attribute__((packed));
1928
c46563b7 1929static int
55489b6e 1930mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1931{
1932 struct mwl8k_priv *priv = hw->priv;
55489b6e 1933 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 1934 int rc;
1935
c46563b7 1936 if (enable == priv->radio_on && !force)
a66098da
LB		 1937 return 0;
1938
a66098da
LB		 1939 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1940 if (cmd == NULL)
1941 return -ENOMEM;
1942
1943 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1944 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1945 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1946 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1947 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1948
1949 rc = mwl8k_post_cmd(hw, &cmd->header);
1950 kfree(cmd);
1951
1952 if (!rc)
c46563b7 1953 priv->radio_on = enable;
a66098da
LB		 1954
1955 return rc;
1956}
1957
55489b6e 1958static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 1959{
55489b6e 1960 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 1961}
1962
55489b6e 1963static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 1964{
55489b6e 1965 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 1966}
1967
a66098da
LB		 1968static int
1969mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1970{
99200a99 1971 struct mwl8k_priv *priv = hw->priv;
a66098da 1972
68ce3884 1973 priv->radio_short_preamble = short_preamble;
a66098da 1974
55489b6e 1975 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 1976}
1977
1978/*
55489b6e 1979 * CMD_RF_TX_POWER.
a66098da
LB		 1980 */
1981#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1982
55489b6e 1983struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 1984 struct mwl8k_cmd_pkt header;
1985 __le16 action;
1986 __le16 support_level;
1987 __le16 current_level;
1988 __le16 reserved;
1989 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1990} __attribute__((packed));
1991
55489b6e 1992static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 1993{
55489b6e 1994 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 1995 int rc;
1996
1997 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1998 if (cmd == NULL)
1999 return -ENOMEM;
2000
2001 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2002 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2003 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2004 cmd->support_level = cpu_to_le16(dBm);
2005
2006 rc = mwl8k_post_cmd(hw, &cmd->header);
2007 kfree(cmd);
2008
2009 return rc;
2010}
2011
08b06347
LB		 2012/*
2013 * CMD_RF_ANTENNA.
2014 */
2015struct mwl8k_cmd_rf_antenna {
2016 struct mwl8k_cmd_pkt header;
2017 __le16 antenna;
2018 __le16 mode;
2019} __attribute__((packed));
2020
2021#define MWL8K_RF_ANTENNA_RX 1
2022#define MWL8K_RF_ANTENNA_TX 2
2023
2024static int
2025mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2026{
2027 struct mwl8k_cmd_rf_antenna *cmd;
2028 int rc;
2029
2030 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2031 if (cmd == NULL)
2032 return -ENOMEM;
2033
2034 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2035 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2036 cmd->antenna = cpu_to_le16(antenna);
2037 cmd->mode = cpu_to_le16(mask);
2038
2039 rc = mwl8k_post_cmd(hw, &cmd->header);
2040 kfree(cmd);
2041
2042 return rc;
2043}
2044
b64fe619
LB		 2045/*
2046 * CMD_SET_BEACON.
2047 */
2048struct mwl8k_cmd_set_beacon {
2049 struct mwl8k_cmd_pkt header;
2050 __le16 beacon_len;
2051 __u8 beacon[0];
2052};
2053
2054static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
2055{
2056 struct mwl8k_cmd_set_beacon *cmd;
2057 int rc;
2058
2059 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2060 if (cmd == NULL)
2061 return -ENOMEM;
2062
2063 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2064 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2065 cmd->beacon_len = cpu_to_le16(len);
2066 memcpy(cmd->beacon, beacon, len);
2067
2068 rc = mwl8k_post_cmd(hw, &cmd->header);
2069 kfree(cmd);
2070
2071 return rc;
2072}
2073
a66098da
LB		 2074/*
2075 * CMD_SET_PRE_SCAN.
2076 */
2077struct mwl8k_cmd_set_pre_scan {
2078 struct mwl8k_cmd_pkt header;
2079} __attribute__((packed));
2080
2081static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2082{
2083 struct mwl8k_cmd_set_pre_scan *cmd;
2084 int rc;
2085
2086 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2087 if (cmd == NULL)
2088 return -ENOMEM;
2089
2090 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2091 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2092
2093 rc = mwl8k_post_cmd(hw, &cmd->header);
2094 kfree(cmd);
2095
2096 return rc;
2097}
2098
2099/*
2100 * CMD_SET_POST_SCAN.
2101 */
2102struct mwl8k_cmd_set_post_scan {
2103 struct mwl8k_cmd_pkt header;
2104 __le32 isibss;
d89173f2 2105 __u8 bssid[ETH_ALEN];
a66098da
LB		 2106} __attribute__((packed));
2107
2108static int
0a11dfc3 2109mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2110{
2111 struct mwl8k_cmd_set_post_scan *cmd;
2112 int rc;
2113
2114 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2115 if (cmd == NULL)
2116 return -ENOMEM;
2117
2118 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2119 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2120 cmd->isibss = 0;
d89173f2 2121 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2122
2123 rc = mwl8k_post_cmd(hw, &cmd->header);
2124 kfree(cmd);
2125
2126 return rc;
2127}
2128
2129/*
2130 * CMD_SET_RF_CHANNEL.
2131 */
2132struct mwl8k_cmd_set_rf_channel {
2133 struct mwl8k_cmd_pkt header;
2134 __le16 action;
2135 __u8 current_channel;
2136 __le32 channel_flags;
2137} __attribute__((packed));
2138
2139static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2140 struct ieee80211_conf *conf)
a66098da 2141{
610677d2 2142 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2143 struct mwl8k_cmd_set_rf_channel *cmd;
2144 int rc;
2145
2146 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2147 if (cmd == NULL)
2148 return -ENOMEM;
2149
2150 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2151 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2152 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2153 cmd->current_channel = channel->hw_value;
610677d2 2154
a66098da 2155 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2
LB		 2156 cmd->channel_flags |= cpu_to_le32(0x00000001);
2157
2158 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2159 conf->channel_type == NL80211_CHAN_HT20)
2160 cmd->channel_flags |= cpu_to_le32(0x00000080);
2161 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2162 cmd->channel_flags |= cpu_to_le32(0x000001900);
2163 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2164 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2165
2166 rc = mwl8k_post_cmd(hw, &cmd->header);
2167 kfree(cmd);
2168
2169 return rc;
2170}
2171
2172/*
55489b6e 2173 * CMD_SET_AID.
a66098da 2174 */
55489b6e
LB		 2175#define MWL8K_FRAME_PROT_DISABLED 0x00
2176#define MWL8K_FRAME_PROT_11G 0x07
2177#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2178#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2179
55489b6e
LB		 2180struct mwl8k_cmd_update_set_aid {
2181 struct mwl8k_cmd_pkt header;
2182 __le16 aid;
a66098da 2183
55489b6e
LB		 2184 /* AP's MAC address (BSSID) */
2185 __u8 bssid[ETH_ALEN];
2186 __le16 protection_mode;
2187 __u8 supp_rates[14];
a66098da
LB		 2188} __attribute__((packed));
2189
c6e96010
LB		 2190static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2191{
2192 int i;
2193 int j;
2194
2195 /*
2196 * Clear nonstandard rates 4 and 13.
2197 */
2198 mask &= 0x1fef;
2199
2200 for (i = 0, j = 0; i < 14; i++) {
2201 if (mask & (1 << i))
2202 rates[j++] = mwl8k_rates[i].hw_value;
2203 }
2204}
2205
55489b6e 2206static int
c6e96010
LB		 2207mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2208 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2209{
55489b6e
LB		 2210 struct mwl8k_cmd_update_set_aid *cmd;
2211 u16 prot_mode;
a66098da
LB		 2212 int rc;
2213
2214 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2215 if (cmd == NULL)
2216 return -ENOMEM;
2217
55489b6e 2218 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2219 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2220 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2221 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2222
7dc6a7a7 2223 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2224 prot_mode = MWL8K_FRAME_PROT_11G;
2225 } else {
7dc6a7a7 2226 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2227 IEEE80211_HT_OP_MODE_PROTECTION) {
2228 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2229 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2230 break;
2231 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2232 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2233 break;
2234 default:
2235 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2236 break;
2237 }
2238 }
2239 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2240
c6e96010 2241 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2242
2243 rc = mwl8k_post_cmd(hw, &cmd->header);
2244 kfree(cmd);
2245
2246 return rc;
2247}
2248
32060e1b 2249/*
55489b6e 2250 * CMD_SET_RATE.
32060e1b 2251 */
55489b6e
LB		 2252struct mwl8k_cmd_set_rate {
2253 struct mwl8k_cmd_pkt header;
2254 __u8 legacy_rates[14];
2255
2256 /* Bitmap for supported MCS codes. */
2257 __u8 mcs_set[16];
2258 __u8 reserved[16];
32060e1b
LB		 2259} __attribute__((packed));
2260
55489b6e 2261static int
c6e96010 2262mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2263 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2264{
55489b6e 2265 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2266 int rc;
2267
2268 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2269 if (cmd == NULL)
2270 return -ENOMEM;
2271
55489b6e 2272 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2273 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2274 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2275 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2276
2277 rc = mwl8k_post_cmd(hw, &cmd->header);
2278 kfree(cmd);
2279
2280 return rc;
2281}
2282
a66098da 2283/*
55489b6e 2284 * CMD_FINALIZE_JOIN.
a66098da 2285 */
55489b6e
LB		 2286#define MWL8K_FJ_BEACON_MAXLEN 128
2287
2288struct mwl8k_cmd_finalize_join {
a66098da 2289 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2290 __le32 sleep_interval; /* Number of beacon periods to sleep */
2291 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB		 2292} __attribute__((packed));
2293
55489b6e
LB		 2294static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2295 int framelen, int dtim)
a66098da 2296{
55489b6e
LB		 2297 struct mwl8k_cmd_finalize_join *cmd;
2298 struct ieee80211_mgmt *payload = frame;
2299 int payload_len;
a66098da
LB		 2300 int rc;
2301
2302 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2303 if (cmd == NULL)
2304 return -ENOMEM;
2305
55489b6e 2306 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2307 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2308 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2309
2310 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2311 if (payload_len < 0)
2312 payload_len = 0;
2313 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2314 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2315
2316 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2317
2318 rc = mwl8k_post_cmd(hw, &cmd->header);
2319 kfree(cmd);
2320
2321 return rc;
2322}
2323
2324/*
55489b6e 2325 * CMD_SET_RTS_THRESHOLD.
a66098da 2326 */
55489b6e 2327struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2328 struct mwl8k_cmd_pkt header;
2329 __le16 action;
55489b6e 2330 __le16 threshold;
a66098da
LB		 2331} __attribute__((packed));
2332
c2c2b12a
LB		 2333static int
2334mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2335{
55489b6e 2336 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2337 int rc;
2338
2339 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2340 if (cmd == NULL)
2341 return -ENOMEM;
2342
55489b6e 2343 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2344 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 2345 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2346 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 2347
2348 rc = mwl8k_post_cmd(hw, &cmd->header);
2349 kfree(cmd);
2350
a66098da
LB		 2351 return rc;
2352}
2353
2354/*
55489b6e 2355 * CMD_SET_SLOT.
a66098da 2356 */
55489b6e 2357struct mwl8k_cmd_set_slot {
a66098da
LB		 2358 struct mwl8k_cmd_pkt header;
2359 __le16 action;
55489b6e 2360 __u8 short_slot;
a66098da
LB		 2361} __attribute__((packed));
2362
55489b6e 2363static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2364{
55489b6e 2365 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2366 int rc;
2367
2368 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2369 if (cmd == NULL)
2370 return -ENOMEM;
2371
55489b6e 2372 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2373 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2374 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2375 cmd->short_slot = short_slot_time;
a66098da
LB		 2376
2377 rc = mwl8k_post_cmd(hw, &cmd->header);
2378 kfree(cmd);
2379
2380 return rc;
2381}
2382
2383/*
2384 * CMD_SET_EDCA_PARAMS.
2385 */
2386struct mwl8k_cmd_set_edca_params {
2387 struct mwl8k_cmd_pkt header;
2388
2389 /* See MWL8K_SET_EDCA_XXX below */
2390 __le16 action;
2391
2392 /* TX opportunity in units of 32 us */
2393 __le16 txop;
2394
2e484c89
LB		 2395 union {
2396 struct {
2397 /* Log exponent of max contention period: 0...15 */
2398 __le32 log_cw_max;
2399
2400 /* Log exponent of min contention period: 0...15 */
2401 __le32 log_cw_min;
2402
2403 /* Adaptive interframe spacing in units of 32us */
2404 __u8 aifs;
2405
2406 /* TX queue to configure */
2407 __u8 txq;
2408 } ap;
2409 struct {
2410 /* Log exponent of max contention period: 0...15 */
2411 __u8 log_cw_max;
a66098da 2412
2e484c89
LB		 2413 /* Log exponent of min contention period: 0...15 */
2414 __u8 log_cw_min;
a66098da 2415
2e484c89
LB		 2416 /* Adaptive interframe spacing in units of 32us */
2417 __u8 aifs;
a66098da 2418
2e484c89
LB		 2419 /* TX queue to configure */
2420 __u8 txq;
2421 } sta;
2422 };
a66098da
LB		 2423} __attribute__((packed));
2424
a66098da
LB		 2425#define MWL8K_SET_EDCA_CW 0x01
2426#define MWL8K_SET_EDCA_TXOP 0x02
2427#define MWL8K_SET_EDCA_AIFS 0x04
2428
2429#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2430 MWL8K_SET_EDCA_TXOP | \
2431 MWL8K_SET_EDCA_AIFS)
2432
2433static int
55489b6e
LB		 2434mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2435 __u16 cw_min, __u16 cw_max,
2436 __u8 aifs, __u16 txop)
a66098da 2437{
2e484c89 2438 struct mwl8k_priv *priv = hw->priv;
a66098da 2439 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2440 int rc;
2441
2442 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2443 if (cmd == NULL)
2444 return -ENOMEM;
2445
a66098da
LB		 2446 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2447 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2448 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2449 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2450 if (priv->ap_fw) {
2451 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2452 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2453 cmd->ap.aifs = aifs;
2454 cmd->ap.txq = qnum;
2455 } else {
2456 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2457 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2458 cmd->sta.aifs = aifs;
2459 cmd->sta.txq = qnum;
2460 }
a66098da
LB		 2461
2462 rc = mwl8k_post_cmd(hw, &cmd->header);
2463 kfree(cmd);
2464
2465 return rc;
2466}
2467
2468/*
55489b6e 2469 * CMD_SET_WMM_MODE.
a66098da 2470 */
55489b6e 2471struct mwl8k_cmd_set_wmm_mode {
a66098da 2472 struct mwl8k_cmd_pkt header;
55489b6e 2473 __le16 action;
a66098da
LB		 2474} __attribute__((packed));
2475
55489b6e 2476static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2477{
55489b6e
LB		 2478 struct mwl8k_priv *priv = hw->priv;
2479 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2480 int rc;
2481
a66098da
LB		 2482 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2483 if (cmd == NULL)
2484 return -ENOMEM;
2485
55489b6e 2486 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2487 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2488 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2489
2490 rc = mwl8k_post_cmd(hw, &cmd->header);
2491 kfree(cmd);
16cec43d 2492
55489b6e
LB		 2493 if (!rc)
2494 priv->wmm_enabled = enable;
a66098da
LB		 2495
2496 return rc;
2497}
2498
2499/*
55489b6e 2500 * CMD_MIMO_CONFIG.
a66098da 2501 */
55489b6e
LB		 2502struct mwl8k_cmd_mimo_config {
2503 struct mwl8k_cmd_pkt header;
2504 __le32 action;
2505 __u8 rx_antenna_map;
2506 __u8 tx_antenna_map;
a66098da
LB		 2507} __attribute__((packed));
2508
55489b6e 2509static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2510{
55489b6e 2511 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2512 int rc;
2513
2514 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2515 if (cmd == NULL)
2516 return -ENOMEM;
2517
55489b6e 2518 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2519 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2520 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2521 cmd->rx_antenna_map = rx;
2522 cmd->tx_antenna_map = tx;
a66098da
LB		 2523
2524 rc = mwl8k_post_cmd(hw, &cmd->header);
2525 kfree(cmd);
2526
2527 return rc;
2528}
2529
2530/*
b71ed2c6 2531 * CMD_USE_FIXED_RATE (STA version).
a66098da 2532 */
b71ed2c6
LB		 2533struct mwl8k_cmd_use_fixed_rate_sta {
2534 struct mwl8k_cmd_pkt header;
2535 __le32 action;
2536 __le32 allow_rate_drop;
2537 __le32 num_rates;
2538 struct {
2539 __le32 is_ht_rate;
2540 __le32 enable_retry;
2541 __le32 rate;
2542 __le32 retry_count;
2543 } rate_entry[8];
2544 __le32 rate_type;
2545 __le32 reserved1;
2546 __le32 reserved2;
a66098da
LB		 2547} __attribute__((packed));
2548
b71ed2c6
LB		 2549#define MWL8K_USE_AUTO_RATE 0x0002
2550#define MWL8K_UCAST_RATE 0
a66098da 2551
b71ed2c6 2552static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2553{
b71ed2c6 2554 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 2555 int rc;
2556
2557 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2558 if (cmd == NULL)
2559 return -ENOMEM;
2560
2561 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2562 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 2563 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2564 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 2565
2566 rc = mwl8k_post_cmd(hw, &cmd->header);
2567 kfree(cmd);
2568
2569 return rc;
2570}
2571
088aab8b
LB		 2572/*
2573 * CMD_USE_FIXED_RATE (AP version).
2574 */
2575struct mwl8k_cmd_use_fixed_rate_ap {
2576 struct mwl8k_cmd_pkt header;
2577 __le32 action;
2578 __le32 allow_rate_drop;
2579 __le32 num_rates;
2580 struct mwl8k_rate_entry_ap {
2581 __le32 is_ht_rate;
2582 __le32 enable_retry;
2583 __le32 rate;
2584 __le32 retry_count;
2585 } rate_entry[4];
2586 u8 multicast_rate;
2587 u8 multicast_rate_type;
2588 u8 management_rate;
2589} __attribute__((packed));
2590
2591static int
2592mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2593{
2594 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2595 int rc;
2596
2597 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2598 if (cmd == NULL)
2599 return -ENOMEM;
2600
2601 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2602 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2603 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2604 cmd->multicast_rate = mcast;
2605 cmd->management_rate = mgmt;
2606
2607 rc = mwl8k_post_cmd(hw, &cmd->header);
2608 kfree(cmd);
2609
2610 return rc;
2611}
2612
55489b6e
LB		 2613/*
2614 * CMD_ENABLE_SNIFFER.
2615 */
2616struct mwl8k_cmd_enable_sniffer {
2617 struct mwl8k_cmd_pkt header;
2618 __le32 action;
2619} __attribute__((packed));
2620
2621static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2622{
2623 struct mwl8k_cmd_enable_sniffer *cmd;
2624 int rc;
2625
2626 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2627 if (cmd == NULL)
2628 return -ENOMEM;
2629
2630 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2631 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2632 cmd->action = cpu_to_le32(!!enable);
2633
2634 rc = mwl8k_post_cmd(hw, &cmd->header);
2635 kfree(cmd);
2636
2637 return rc;
2638}
2639
2640/*
2641 * CMD_SET_MAC_ADDR.
2642 */
2643struct mwl8k_cmd_set_mac_addr {
2644 struct mwl8k_cmd_pkt header;
2645 union {
2646 struct {
2647 __le16 mac_type;
2648 __u8 mac_addr[ETH_ALEN];
2649 } mbss;
2650 __u8 mac_addr[ETH_ALEN];
2651 };
2652} __attribute__((packed));
2653
a9e00b15
LB		 2654#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
2655#define MWL8K_MAC_TYPE_PRIMARY_AP 2
2656
55489b6e
LB		 2657static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2658{
2659 struct mwl8k_priv *priv = hw->priv;
2660 struct mwl8k_cmd_set_mac_addr *cmd;
2661 int rc;
2662
2663 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2664 if (cmd == NULL)
2665 return -ENOMEM;
2666
2667 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2668 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2669 if (priv->ap_fw) {
a9e00b15 2670 cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
55489b6e
LB		 2671 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2672 } else {
2673 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2674 }
2675
2676 rc = mwl8k_post_cmd(hw, &cmd->header);
2677 kfree(cmd);
2678
2679 return rc;
2680}
2681
2682/*
2683 * CMD_SET_RATEADAPT_MODE.
2684 */
2685struct mwl8k_cmd_set_rate_adapt_mode {
2686 struct mwl8k_cmd_pkt header;
2687 __le16 action;
2688 __le16 mode;
2689} __attribute__((packed));
2690
2691static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2692{
2693 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2694 int rc;
2695
2696 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2697 if (cmd == NULL)
2698 return -ENOMEM;
2699
2700 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2701 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2702 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2703 cmd->mode = cpu_to_le16(mode);
2704
2705 rc = mwl8k_post_cmd(hw, &cmd->header);
2706 kfree(cmd);
2707
2708 return rc;
2709}
2710
b64fe619
LB		 2711/*
2712 * CMD_BSS_START.
2713 */
2714struct mwl8k_cmd_bss_start {
2715 struct mwl8k_cmd_pkt header;
2716 __le32 enable;
2717} __attribute__((packed));
2718
2719static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
2720{
2721 struct mwl8k_cmd_bss_start *cmd;
2722 int rc;
2723
2724 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2725 if (cmd == NULL)
2726 return -ENOMEM;
2727
2728 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
2729 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2730 cmd->enable = cpu_to_le32(enable);
2731
2732 rc = mwl8k_post_cmd(hw, &cmd->header);
2733 kfree(cmd);
2734
2735 return rc;
2736}
2737
3f5610ff
LB		 2738/*
2739 * CMD_SET_NEW_STN.
2740 */
2741struct mwl8k_cmd_set_new_stn {
2742 struct mwl8k_cmd_pkt header;
2743 __le16 aid;
2744 __u8 mac_addr[6];
2745 __le16 stn_id;
2746 __le16 action;
2747 __le16 rsvd;
2748 __le32 legacy_rates;
2749 __u8 ht_rates[4];
2750 __le16 cap_info;
2751 __le16 ht_capabilities_info;
2752 __u8 mac_ht_param_info;
2753 __u8 rev;
2754 __u8 control_channel;
2755 __u8 add_channel;
2756 __le16 op_mode;
2757 __le16 stbc;
2758 __u8 add_qos_info;
2759 __u8 is_qos_sta;
2760 __le32 fw_sta_ptr;
2761} __attribute__((packed));
2762
2763#define MWL8K_STA_ACTION_ADD 0
2764#define MWL8K_STA_ACTION_REMOVE 2
2765
2766static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
2767 struct ieee80211_vif *vif,
2768 struct ieee80211_sta *sta)
2769{
2770 struct mwl8k_cmd_set_new_stn *cmd;
2771 int rc;
2772
2773 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2774 if (cmd == NULL)
2775 return -ENOMEM;
2776
2777 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2778 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2779 cmd->aid = cpu_to_le16(sta->aid);
2780 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
2781 cmd->stn_id = cpu_to_le16(sta->aid);
2782 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
2783 cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]);
2784 if (sta->ht_cap.ht_supported) {
2785 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
2786 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
2787 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
2788 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
2789 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
2790 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
2791 ((sta->ht_cap.ampdu_density & 7) << 2);
2792 cmd->is_qos_sta = 1;
2793 }
2794
2795 rc = mwl8k_post_cmd(hw, &cmd->header);
2796 kfree(cmd);
2797
2798 return rc;
2799}
2800
b64fe619
LB		 2801static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
2802 struct ieee80211_vif *vif)
2803{
2804 struct mwl8k_cmd_set_new_stn *cmd;
2805 int rc;
2806
2807 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2808 if (cmd == NULL)
2809 return -ENOMEM;
2810
2811 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2812 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2813 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
2814
2815 rc = mwl8k_post_cmd(hw, &cmd->header);
2816 kfree(cmd);
2817
2818 return rc;
2819}
2820
3f5610ff
LB		 2821static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
2822 struct ieee80211_vif *vif, u8 *addr)
2823{
2824 struct mwl8k_cmd_set_new_stn *cmd;
2825 int rc;
2826
2827 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2828 if (cmd == NULL)
2829 return -ENOMEM;
2830
2831 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2832 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2833 memcpy(cmd->mac_addr, addr, ETH_ALEN);
2834 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
2835
2836 rc = mwl8k_post_cmd(hw, &cmd->header);
2837 kfree(cmd);
2838
2839 return rc;
2840}
2841
55489b6e
LB		 2842/*
2843 * CMD_UPDATE_STADB.
2844 */
25d81b1e
LB		 2845struct ewc_ht_info {
2846 __le16 control1;
2847 __le16 control2;
2848 __le16 control3;
2849} __attribute__((packed));
2850
2851struct peer_capability_info {
2852 /* Peer type - AP vs. STA. */
2853 __u8 peer_type;
2854
2855 /* Basic 802.11 capabilities from assoc resp. */
2856 __le16 basic_caps;
2857
2858 /* Set if peer supports 802.11n high throughput (HT). */
2859 __u8 ht_support;
2860
2861 /* Valid if HT is supported. */
2862 __le16 ht_caps;
2863 __u8 extended_ht_caps;
2864 struct ewc_ht_info ewc_info;
2865
2866 /* Legacy rate table. Intersection of our rates and peer rates. */
2867 __u8 legacy_rates[12];
2868
2869 /* HT rate table. Intersection of our rates and peer rates. */
2870 __u8 ht_rates[16];
2871 __u8 pad[16];
2872
2873 /* If set, interoperability mode, no proprietary extensions. */
2874 __u8 interop;
2875 __u8 pad2;
2876 __u8 station_id;
2877 __le16 amsdu_enabled;
2878} __attribute__((packed));
2879
55489b6e
LB		 2880struct mwl8k_cmd_update_stadb {
2881 struct mwl8k_cmd_pkt header;
2882
2883 /* See STADB_ACTION_TYPE */
2884 __le32 action;
2885
2886 /* Peer MAC address */
2887 __u8 peer_addr[ETH_ALEN];
2888
2889 __le32 reserved;
2890
2891 /* Peer info - valid during add/update. */
2892 struct peer_capability_info peer_info;
2893} __attribute__((packed));
2894
a680400e
LB		 2895#define MWL8K_STA_DB_MODIFY_ENTRY 1
2896#define MWL8K_STA_DB_DEL_ENTRY 2
2897
2898/* Peer Entry flags - used to define the type of the peer node */
2899#define MWL8K_PEER_TYPE_ACCESSPOINT 2
2900
2901static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 2902 struct ieee80211_vif *vif,
13935e2c 2903 struct ieee80211_sta *sta)
55489b6e 2904{
55489b6e 2905 struct mwl8k_cmd_update_stadb *cmd;
a680400e 2906 struct peer_capability_info *p;
55489b6e
LB		 2907 int rc;
2908
2909 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2910 if (cmd == NULL)
2911 return -ENOMEM;
2912
2913 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2914 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 2915 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 2916 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 2917
a680400e
LB		 2918 p = &cmd->peer_info;
2919 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2920 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c
LB		 2921 p->ht_support = sta->ht_cap.ht_supported;
2922 p->ht_caps = sta->ht_cap.cap;
2923 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
2924 ((sta->ht_cap.ampdu_density & 7) << 2);
2925 legacy_rate_mask_to_array(p->legacy_rates,
2926 sta->supp_rates[IEEE80211_BAND_2GHZ]);
2927 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 2928 p->interop = 1;
2929 p->amsdu_enabled = 0;
2930
2931 rc = mwl8k_post_cmd(hw, &cmd->header);
2932 kfree(cmd);
2933
2934 return rc ? rc : p->station_id;
2935}
2936
2937static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
2938 struct ieee80211_vif *vif, u8 *addr)
2939{
2940 struct mwl8k_cmd_update_stadb *cmd;
2941 int rc;
2942
2943 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2944 if (cmd == NULL)
2945 return -ENOMEM;
2946
2947 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2948 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2949 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 2950 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2951
a680400e 2952 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 2953 kfree(cmd);
2954
2955 return rc;
2956}
2957
a66098da
LB		 2958
2959/*
2960 * Interrupt handling.
2961 */
2962static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2963{
2964 struct ieee80211_hw *hw = dev_id;
2965 struct mwl8k_priv *priv = hw->priv;
2966 u32 status;
2967
2968 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 2969 if (!status)
2970 return IRQ_NONE;
2971
1e9f9de3
LB		 2972 if (status & MWL8K_A2H_INT_TX_DONE) {
2973 status &= ~MWL8K_A2H_INT_TX_DONE;
2974 tasklet_schedule(&priv->poll_tx_task);
2975 }
2976
a66098da 2977 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 2978 status &= ~MWL8K_A2H_INT_RX_READY;
2979 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 2980 }
2981
67e2eb27
LB		 2982 if (status)
2983 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2984
a66098da 2985 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2986 if (priv->hostcmd_wait != NULL)
a66098da 2987 complete(priv->hostcmd_wait);
a66098da
LB		 2988 }
2989
2990 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2991 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2992 priv->radio_on && priv->pending_tx_pkts)
618952a7 2993 mwl8k_tx_start(priv);
a66098da
LB		 2994 }
2995
2996 return IRQ_HANDLED;
2997}
2998
1e9f9de3
LB		 2999static void mwl8k_tx_poll(unsigned long data)
3000{
3001 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3002 struct mwl8k_priv *priv = hw->priv;
3003 int limit;
3004 int i;
3005
3006 limit = 32;
3007
3008 spin_lock_bh(&priv->tx_lock);
3009
3010 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3011 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3012
3013 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3014 complete(priv->tx_wait);
3015 priv->tx_wait = NULL;
3016 }
3017
3018 spin_unlock_bh(&priv->tx_lock);
3019
3020 if (limit) {
3021 writel(~MWL8K_A2H_INT_TX_DONE,
3022 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3023 } else {
3024 tasklet_schedule(&priv->poll_tx_task);
3025 }
3026}
3027
67e2eb27
LB		 3028static void mwl8k_rx_poll(unsigned long data)
3029{
3030 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3031 struct mwl8k_priv *priv = hw->priv;
3032 int limit;
3033
3034 limit = 32;
3035 limit -= rxq_process(hw, 0, limit);
3036 limit -= rxq_refill(hw, 0, limit);
3037
3038 if (limit) {
3039 writel(~MWL8K_A2H_INT_RX_READY,
3040 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3041 } else {
3042 tasklet_schedule(&priv->poll_rx_task);
3043 }
3044}
3045
a66098da
LB		 3046
3047/*
3048 * Core driver operations.
3049 */
3050static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3051{
3052 struct mwl8k_priv *priv = hw->priv;
3053 int index = skb_get_queue_mapping(skb);
3054 int rc;
3055
3056 if (priv->current_channel == NULL) {
3057 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 3058 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 3059 dev_kfree_skb(skb);
3060 return NETDEV_TX_OK;
3061 }
3062
3063 rc = mwl8k_txq_xmit(hw, index, skb);
3064
3065 return rc;
3066}
3067
a66098da
LB		 3068static int mwl8k_start(struct ieee80211_hw *hw)
3069{
a66098da
LB		 3070 struct mwl8k_priv *priv = hw->priv;
3071 int rc;
3072
a0607fd3 3073 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3074 IRQF_SHARED, MWL8K_NAME, hw);
3075 if (rc) {
3076 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3077 wiphy_name(hw->wiphy));
2ec610cb 3078 return -EIO;
a66098da
LB		 3079 }
3080
67e2eb27 3081 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3082 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3083 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3084
a66098da 3085 /* Enable interrupts */
c23b5a69 3086 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3087
2ec610cb
LB		 3088 rc = mwl8k_fw_lock(hw);
3089 if (!rc) {
55489b6e 3090 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3091
5e4cf166
LB		 3092 if (!priv->ap_fw) {
3093 if (!rc)
55489b6e 3094 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3095
5e4cf166
LB		 3096 if (!rc)
3097 rc = mwl8k_cmd_set_pre_scan(hw);
3098
3099 if (!rc)
3100 rc = mwl8k_cmd_set_post_scan(hw,
3101 "\x00\x00\x00\x00\x00\x00");
3102 }
2ec610cb
LB		 3103
3104 if (!rc)
55489b6e 3105 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3106
2ec610cb 3107 if (!rc)
55489b6e 3108 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3109
2ec610cb
LB		 3110 mwl8k_fw_unlock(hw);
3111 }
3112
3113 if (rc) {
3114 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3115 free_irq(priv->pdev->irq, hw);
1e9f9de3 3116 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3117 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3118 }
a66098da
LB		 3119
3120 return rc;
3121}
3122
a66098da
LB		 3123static void mwl8k_stop(struct ieee80211_hw *hw)
3124{
a66098da
LB		 3125 struct mwl8k_priv *priv = hw->priv;
3126 int i;
3127
55489b6e 3128 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 3129
3130 ieee80211_stop_queues(hw);
3131
a66098da 3132 /* Disable interrupts */
a66098da 3133 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3134 free_irq(priv->pdev->irq, hw);
3135
3136 /* Stop finalize join worker */
3137 cancel_work_sync(&priv->finalize_join_worker);
3138 if (priv->beacon_skb != NULL)
3139 dev_kfree_skb(priv->beacon_skb);
3140
67e2eb27 3141 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3142 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3143 tasklet_disable(&priv->poll_rx_task);
a66098da 3144
a66098da
LB		 3145 /* Return all skbs to mac80211 */
3146 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3147 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 3148}
3149
3150static int mwl8k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3151 struct ieee80211_vif *vif)
a66098da
LB		 3152{
3153 struct mwl8k_priv *priv = hw->priv;
3154 struct mwl8k_vif *mwl8k_vif;
3155
3156 /*
3157 * We only support one active interface at a time.
3158 */
3159 if (priv->vif != NULL)
3160 return -EBUSY;
3161
a43c49a8
LB		 3162 /*
3163 * Reject interface creation if sniffer mode is active, as
3164 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3165 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 3166 */
3167 if (priv->sniffer_enabled) {
3168 printk(KERN_INFO "%s: unable to create STA "
3169 "interface due to sniffer mode being enabled\n",
3170 wiphy_name(hw->wiphy));
3171 return -EINVAL;
3172 }
3173
c2c2b12a
LB		 3174 /* Set the mac address. */
3175 mwl8k_cmd_set_mac_addr(hw, vif->addr);
3176
b64fe619
LB		 3177 if (priv->ap_fw)
3178 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3179
a66098da 3180 /* Clean out driver private area */
1ed32e4f 3181 mwl8k_vif = MWL8K_VIF(vif);
a66098da
LB		 3182 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
3183
a66098da
LB		 3184 /* Set Initial sequence number to zero */
3185 mwl8k_vif->seqno = 0;
3186
1ed32e4f 3187 priv->vif = vif;
a66098da
LB		 3188 priv->current_channel = NULL;
3189
3190 return 0;
3191}
3192
3193static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3194 struct ieee80211_vif *vif)
a66098da
LB		 3195{
3196 struct mwl8k_priv *priv = hw->priv;
3197
b64fe619
LB		 3198 if (priv->ap_fw)
3199 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3200
55489b6e 3201 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 3202
a66098da
LB		 3203 priv->vif = NULL;
3204}
3205
ee03a932 3206static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3207{
a66098da
LB		 3208 struct ieee80211_conf *conf = &hw->conf;
3209 struct mwl8k_priv *priv = hw->priv;
ee03a932 3210 int rc;
a66098da 3211
7595d67a 3212 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3213 mwl8k_cmd_radio_disable(hw);
7595d67a 3214 priv->current_channel = NULL;
ee03a932 3215 return 0;
7595d67a
LB		 3216 }
3217
ee03a932
LB		 3218 rc = mwl8k_fw_lock(hw);
3219 if (rc)
3220 return rc;
a66098da 3221
55489b6e 3222 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 3223 if (rc)
3224 goto out;
a66098da 3225
610677d2 3226 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 3227 if (rc)
3228 goto out;
3229
3230 priv->current_channel = conf->channel;
a66098da
LB		 3231
3232 if (conf->power_level > 18)
3233 conf->power_level = 18;
55489b6e 3234 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB		 3235 if (rc)
3236 goto out;
a66098da 3237
08b06347
LB		 3238 if (priv->ap_fw) {
3239 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3240 if (!rc)
3241 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3242 } else {
3243 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3244 }
a66098da 3245
ee03a932
LB		 3246out:
3247 mwl8k_fw_unlock(hw);
a66098da 3248
ee03a932 3249 return rc;
a66098da
LB		 3250}
3251
b64fe619
LB		 3252static void
3253mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3254 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3255{
a66098da 3256 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3257 u32 ap_legacy_rates;
13935e2c 3258 u8 ap_mcs_rates[16];
3a980d0a
LB		 3259 int rc;
3260
c3cbbe8a 3261 if (mwl8k_fw_lock(hw))
3a980d0a 3262 return;
a66098da 3263
c3cbbe8a
LB		 3264 /*
3265 * No need to capture a beacon if we're no longer associated.
3266 */
3267 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3268 priv->capture_beacon = false;
3a980d0a 3269
c3cbbe8a 3270 /*
13935e2c 3271 * Get the AP's legacy and MCS rates.
c3cbbe8a
LB		 3272 */
3273 ap_legacy_rates = 0;
7dc6a7a7 3274 if (vif->bss_conf.assoc) {
c6e96010 3275 struct ieee80211_sta *ap;
c6e96010 3276 rcu_read_lock();
c6e96010 3277
c3cbbe8a
LB		 3278 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3279 if (ap == NULL) {
3280 rcu_read_unlock();
c6e96010 3281 goto out;
c3cbbe8a
LB		 3282 }
3283
3284 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
13935e2c 3285 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 3286
3287 rcu_read_unlock();
3288 }
c6e96010 3289
c3cbbe8a 3290 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3291 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 3292 if (rc)
3293 goto out;
a66098da 3294
b71ed2c6 3295 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 3296 if (rc)
3297 goto out;
c3cbbe8a 3298 }
a66098da 3299
c3cbbe8a 3300 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 3301 rc = mwl8k_set_radio_preamble(hw,
3302 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 3303 if (rc)
3304 goto out;
c3cbbe8a 3305 }
a66098da 3306
c3cbbe8a 3307 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3308 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 3309 if (rc)
3310 goto out;
c3cbbe8a 3311 }
a66098da 3312
c3cbbe8a
LB		 3313 if (((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) ||
3314 (changed & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT))) {
3315 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 3316 if (rc)
3317 goto out;
c3cbbe8a 3318 }
a66098da 3319
c3cbbe8a
LB		 3320 if (vif->bss_conf.assoc &&
3321 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 3322 /*
3323 * Finalize the join. Tell rx handler to process
3324 * next beacon from our BSSID.
3325 */
0a11dfc3 3326 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3327 priv->capture_beacon = true;
a66098da
LB		 3328 }
3329
3a980d0a
LB		 3330out:
3331 mwl8k_fw_unlock(hw);
a66098da
LB		 3332}
3333
b64fe619
LB		 3334static void
3335mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3336 struct ieee80211_bss_conf *info, u32 changed)
3337{
3338 int rc;
3339
3340 if (mwl8k_fw_lock(hw))
3341 return;
3342
3343 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3344 rc = mwl8k_set_radio_preamble(hw,
3345 vif->bss_conf.use_short_preamble);
3346 if (rc)
3347 goto out;
3348 }
3349
3350 if (changed & BSS_CHANGED_BASIC_RATES) {
3351 int idx;
3352 int rate;
3353
3354 /*
3355 * Use lowest supported basic rate for multicasts
3356 * and management frames (such as probe responses --
3357 * beacons will always go out at 1 Mb/s).
3358 */
3359 idx = ffs(vif->bss_conf.basic_rates);
3360 rate = idx ? mwl8k_rates[idx - 1].hw_value : 2;
3361
3362 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3363 }
3364
3365 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3366 struct sk_buff *skb;
3367
3368 skb = ieee80211_beacon_get(hw, vif);
3369 if (skb != NULL) {
3370 mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
3371 kfree_skb(skb);
3372 }
3373 }
3374
3375 if (changed & BSS_CHANGED_BEACON_ENABLED)
3376 mwl8k_cmd_bss_start(hw, info->enable_beacon);
3377
3378out:
3379 mwl8k_fw_unlock(hw);
3380}
3381
3382static void
3383mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3384 struct ieee80211_bss_conf *info, u32 changed)
3385{
3386 struct mwl8k_priv *priv = hw->priv;
3387
3388 if (!priv->ap_fw)
3389 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3390 else
3391 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3392}
3393
e81cd2d6
LB		 3394static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3395 int mc_count, struct dev_addr_list *mclist)
3396{
3397 struct mwl8k_cmd_pkt *cmd;
3398
447ced07
LB		 3399 /*
3400 * Synthesize and return a command packet that programs the
3401 * hardware multicast address filter. At this point we don't
3402 * know whether FIF_ALLMULTI is being requested, but if it is,
3403 * we'll end up throwing this packet away and creating a new
3404 * one in mwl8k_configure_filter().
3405 */
3406 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3407
3408 return (unsigned long)cmd;
3409}
3410
a43c49a8
LB		 3411static int
3412mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3413 unsigned int changed_flags,
3414 unsigned int *total_flags)
3415{
3416 struct mwl8k_priv *priv = hw->priv;
3417
3418 /*
3419 * Hardware sniffer mode is mutually exclusive with STA
3420 * operation, so refuse to enable sniffer mode if a STA
3421 * interface is active.
3422 */
3423 if (priv->vif != NULL) {
3424 if (net_ratelimit())
3425 printk(KERN_INFO "%s: not enabling sniffer "
3426 "mode because STA interface is active\n",
3427 wiphy_name(hw->wiphy));
3428 return 0;
3429 }
3430
3431 if (!priv->sniffer_enabled) {
55489b6e 3432 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3433 return 0;
3434 priv->sniffer_enabled = true;
3435 }
3436
3437 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3438 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3439 FIF_OTHER_BSS;
3440
3441 return 1;
3442}
3443
e6935ea1
LB		 3444static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3445 unsigned int changed_flags,
3446 unsigned int *total_flags,
3447 u64 multicast)
3448{
3449 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3450 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3451
c0adae2c
LB		 3452 /*
3453 * AP firmware doesn't allow fine-grained control over
3454 * the receive filter.
3455 */
3456 if (priv->ap_fw) {
3457 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3458 kfree(cmd);
3459 return;
3460 }
3461
a43c49a8
LB		 3462 /*
3463 * Enable hardware sniffer mode if FIF_CONTROL or
3464 * FIF_OTHER_BSS is requested.
3465 */
3466 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3467 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3468 kfree(cmd);
3469 return;
3470 }
a66098da 3471
e6935ea1 3472 /* Clear unsupported feature flags */
447ced07 3473 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3474
90852f7a
LB		 3475 if (mwl8k_fw_lock(hw)) {
3476 kfree(cmd);
e6935ea1 3477 return;
90852f7a 3478 }
a66098da 3479
a43c49a8 3480 if (priv->sniffer_enabled) {
55489b6e 3481 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3482 priv->sniffer_enabled = false;
3483 }
3484
e6935ea1 3485 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3486 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3487 /*
3488 * Disable the BSS filter.
3489 */
e6935ea1 3490 mwl8k_cmd_set_pre_scan(hw);
77165d88 3491 } else {
0a11dfc3 3492 const u8 *bssid;
a94cc97e 3493
77165d88
LB		 3494 /*
3495 * Enable the BSS filter.
3496 *
3497 * If there is an active STA interface, use that
3498 * interface's BSSID, otherwise use a dummy one
3499 * (where the OUI part needs to be nonzero for
3500 * the BSSID to be accepted by POST_SCAN).
3501 */
3502 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3503 if (priv->vif != NULL)
0a11dfc3 3504 bssid = priv->vif->bss_conf.bssid;
a94cc97e 3505
e6935ea1 3506 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3507 }
3508 }
3509
447ced07
LB		 3510 /*
3511 * If FIF_ALLMULTI is being requested, throw away the command
3512 * packet that ->prepare_multicast() built and replace it with
3513 * a command packet that enables reception of all multicast
3514 * packets.
3515 */
3516 if (*total_flags & FIF_ALLMULTI) {
3517 kfree(cmd);
3518 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3519 }
3520
3521 if (cmd != NULL) {
3522 mwl8k_post_cmd(hw, cmd);
3523 kfree(cmd);
e6935ea1 3524 }
a66098da 3525
e6935ea1 3526 mwl8k_fw_unlock(hw);
a66098da
LB		 3527}
3528
a66098da
LB		 3529static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3530{
c2c2b12a 3531 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 3532}
3533
bbfd9128
LB		 3534struct mwl8k_sta_notify_item
3535{
3536 struct list_head list;
3537 struct ieee80211_vif *vif;
3538 enum sta_notify_cmd cmd;
13935e2c 3539 struct ieee80211_sta sta;
bbfd9128
LB		 3540};
3541
3f5610ff
LB		 3542static void
3543mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
3544{
3545 struct mwl8k_priv *priv = hw->priv;
3546
3547 /*
3548 * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
3549 */
3550 if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3551 int rc;
3552
3553 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
3554 if (rc >= 0) {
3555 struct ieee80211_sta *sta;
3556
3557 rcu_read_lock();
3558 sta = ieee80211_find_sta(s->vif, s->sta.addr);
3559 if (sta != NULL)
3560 MWL8K_STA(sta)->peer_id = rc;
3561 rcu_read_unlock();
3562 }
3563 } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3564 mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
3565 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3566 mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
3567 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3568 mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
3569 }
3570}
3571
bbfd9128
LB		 3572static void mwl8k_sta_notify_worker(struct work_struct *work)
3573{
3574 struct mwl8k_priv *priv =
3575 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3576 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB		 3577
3578 spin_lock_bh(&priv->sta_notify_list_lock);
3579 while (!list_empty(&priv->sta_notify_list)) {
3580 struct mwl8k_sta_notify_item *s;
bbfd9128
LB		 3581
3582 s = list_entry(priv->sta_notify_list.next,
3583 struct mwl8k_sta_notify_item, list);
3584 list_del(&s->list);
3585
3586 spin_unlock_bh(&priv->sta_notify_list_lock);
3587
3f5610ff 3588 mwl8k_do_sta_notify(hw, s);
bbfd9128
LB		 3589 kfree(s);
3590
3591 spin_lock_bh(&priv->sta_notify_list_lock);
3592 }
3593 spin_unlock_bh(&priv->sta_notify_list_lock);
3594}
3595
3596static void
3597mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3598 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3599{
3600 struct mwl8k_priv *priv = hw->priv;
3601 struct mwl8k_sta_notify_item *s;
3602
3603 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3604 return;
3605
3606 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3607 if (s != NULL) {
3608 s->vif = vif;
3609 s->cmd = cmd;
13935e2c 3610 s->sta = *sta;
bbfd9128
LB		 3611
3612 spin_lock(&priv->sta_notify_list_lock);
3613 list_add_tail(&s->list, &priv->sta_notify_list);
3614 spin_unlock(&priv->sta_notify_list_lock);
3615
3616 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3617 }
3618}
3619
a66098da
LB		 3620static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3621 const struct ieee80211_tx_queue_params *params)
3622{
3e4f542c 3623 struct mwl8k_priv *priv = hw->priv;
a66098da 3624 int rc;
a66098da 3625
3e4f542c
LB		 3626 rc = mwl8k_fw_lock(hw);
3627 if (!rc) {
3628 if (!priv->wmm_enabled)
55489b6e 3629 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3630
3e4f542c 3631 if (!rc)
55489b6e
LB		 3632 rc = mwl8k_cmd_set_edca_params(hw, queue,
3633 params->cw_min,
3634 params->cw_max,
3635 params->aifs,
3636 params->txop);
3e4f542c
LB		 3637
3638 mwl8k_fw_unlock(hw);
a66098da 3639 }
3e4f542c 3640
a66098da
LB		 3641 return rc;
3642}
3643
3644static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3645 struct ieee80211_tx_queue_stats *stats)
3646{
3647 struct mwl8k_priv *priv = hw->priv;
3648 struct mwl8k_tx_queue *txq;
3649 int index;
3650
3651 spin_lock_bh(&priv->tx_lock);
3652 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3653 txq = priv->txq + index;
45eb400d 3654 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3655 sizeof(struct ieee80211_tx_queue_stats));
3656 }
3657 spin_unlock_bh(&priv->tx_lock);
a66098da 3658
954ef509 3659 return 0;
a66098da
LB		 3660}
3661
3662static int mwl8k_get_stats(struct ieee80211_hw *hw,
3663 struct ieee80211_low_level_stats *stats)
3664{
55489b6e 3665 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 3666}
3667
a2292d83
LB		 3668static int
3669mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3670 enum ieee80211_ampdu_mlme_action action,
3671 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3672{
3673 switch (action) {
3674 case IEEE80211_AMPDU_RX_START:
3675 case IEEE80211_AMPDU_RX_STOP:
3676 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
3677 return -ENOTSUPP;
3678 return 0;
3679 default:
3680 return -ENOTSUPP;
3681 }
3682}
3683
a66098da
LB		 3684static const struct ieee80211_ops mwl8k_ops = {
3685 .tx = mwl8k_tx,
3686 .start = mwl8k_start,
3687 .stop = mwl8k_stop,
3688 .add_interface = mwl8k_add_interface,
3689 .remove_interface = mwl8k_remove_interface,
3690 .config = mwl8k_config,
a66098da 3691 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3692 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3693 .configure_filter = mwl8k_configure_filter,
3694 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3695 .sta_notify = mwl8k_sta_notify,
a66098da
LB		 3696 .conf_tx = mwl8k_conf_tx,
3697 .get_tx_stats = mwl8k_get_tx_stats,
3698 .get_stats = mwl8k_get_stats,
a2292d83 3699 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 3700};
3701
a66098da
LB		 3702static void mwl8k_finalize_join_worker(struct work_struct *work)
3703{
3704 struct mwl8k_priv *priv =
3705 container_of(work, struct mwl8k_priv, finalize_join_worker);
3706 struct sk_buff *skb = priv->beacon_skb;
a66098da 3707
7dc6a7a7
LB		 3708 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3709 priv->vif->bss_conf.dtim_period);
a66098da
LB		 3710 dev_kfree_skb(skb);
3711
3712 priv->beacon_skb = NULL;
3713}
3714
bcb628d5 3715enum {
9e1b17ea
LB		 3716 MWL8363 = 0,
3717 MWL8687,
bcb628d5 3718 MWL8366,
6f6d1e9a
LB		 3719};
3720
bcb628d5 3721static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 3722 [MWL8363] = {
3723 .part_name = "88w8363",
3724 .helper_image = "mwl8k/helper_8363.fw",
3725 .fw_image = "mwl8k/fmimage_8363.fw",
3726 },
49eb691c 3727 [MWL8687] = {
bcb628d5
JL		 3728 .part_name = "88w8687",
3729 .helper_image = "mwl8k/helper_8687.fw",
3730 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3731 },
49eb691c 3732 [MWL8366] = {
bcb628d5
JL		 3733 .part_name = "88w8366",
3734 .helper_image = "mwl8k/helper_8366.fw",
3735 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3736 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3737 },
45a390dd
LB		 3738};
3739
3740static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
9e1b17ea
LB		 3741 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
3742 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 3743 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3744 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3745 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3746 { },
45a390dd
LB		 3747};
3748MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3749
a66098da
LB		 3750static int __devinit mwl8k_probe(struct pci_dev *pdev,
3751 const struct pci_device_id *id)
3752{
2aa7b01f 3753 static int printed_version = 0;
a66098da
LB		 3754 struct ieee80211_hw *hw;
3755 struct mwl8k_priv *priv;
a66098da
LB		 3756 int rc;
3757 int i;
2aa7b01f
LB		 3758
3759 if (!printed_version) {
3760 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3761 printed_version = 1;
3762 }
a66098da 3763
be695fc4 3764
a66098da
LB		 3765 rc = pci_enable_device(pdev);
3766 if (rc) {
3767 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3768 MWL8K_NAME);
3769 return rc;
3770 }
3771
3772 rc = pci_request_regions(pdev, MWL8K_NAME);
3773 if (rc) {
3774 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3775 MWL8K_NAME);
3db95e50 3776 goto err_disable_device;
a66098da
LB		 3777 }
3778
3779 pci_set_master(pdev);
3780
be695fc4 3781
a66098da
LB		 3782 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3783 if (hw == NULL) {
3784 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3785 rc = -ENOMEM;
3786 goto err_free_reg;
3787 }
3788
be695fc4
LB		 3789 SET_IEEE80211_DEV(hw, &pdev->dev);
3790 pci_set_drvdata(pdev, hw);
3791
a66098da
LB		 3792 priv = hw->priv;
3793 priv->hw = hw;
3794 priv->pdev = pdev;
bcb628d5 3795 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3796
a66098da 3797
5b9482dd
LB		 3798 priv->sram = pci_iomap(pdev, 0, 0x10000);
3799 if (priv->sram == NULL) {
3800 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3801 wiphy_name(hw->wiphy));
a66098da
LB		 3802 goto err_iounmap;
3803 }
3804
5b9482dd
LB		 3805 /*
3806 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3807 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3808 */
3809 priv->regs = pci_iomap(pdev, 1, 0x10000);
3810 if (priv->regs == NULL) {
3811 priv->regs = pci_iomap(pdev, 2, 0x10000);
3812 if (priv->regs == NULL) {
3813 printk(KERN_ERR "%s: Cannot map device registers\n",
3814 wiphy_name(hw->wiphy));
3815 goto err_iounmap;
3816 }
3817 }
3818
be695fc4
LB		 3819
3820 /* Reset firmware and hardware */
3821 mwl8k_hw_reset(priv);
3822
3823 /* Ask userland hotplug daemon for the device firmware */
3824 rc = mwl8k_request_firmware(priv);
3825 if (rc) {
3826 printk(KERN_ERR "%s: Firmware files not found\n",
3827 wiphy_name(hw->wiphy));
3828 goto err_stop_firmware;
3829 }
3830
3831 /* Load firmware into hardware */
3832 rc = mwl8k_load_firmware(hw);
3833 if (rc) {
3834 printk(KERN_ERR "%s: Cannot start firmware\n",
3835 wiphy_name(hw->wiphy));
3836 goto err_stop_firmware;
3837 }
3838
3839 /* Reclaim memory once firmware is successfully loaded */
3840 mwl8k_release_firmware(priv);
3841
3842
91942230 3843 if (priv->ap_fw) {
89a91f4f 3844 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB		 3845 if (priv->rxd_ops == NULL) {
3846 printk(KERN_ERR "%s: Driver does not have AP "
3847 "firmware image support for this hardware\n",
3848 wiphy_name(hw->wiphy));
3849 goto err_stop_firmware;
3850 }
3851 } else {
89a91f4f 3852 priv->rxd_ops = &rxd_sta_ops;
91942230 3853 }
be695fc4
LB		 3854
3855 priv->sniffer_enabled = false;
3856 priv->wmm_enabled = false;
3857 priv->pending_tx_pkts = 0;
3858
3859
a66098da
LB		 3860 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3861 priv->band.band = IEEE80211_BAND_2GHZ;
3862 priv->band.channels = priv->channels;
3863 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3864 priv->band.bitrates = priv->rates;
3865 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3866 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3867
3868 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3869 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3870
3871 /*
3872 * Extra headroom is the size of the required DMA header
3873 * minus the size of the smallest 802.11 frame (CTS frame).
3874 */
3875 hw->extra_tx_headroom =
3876 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3877
3878 hw->channel_change_time = 10;
3879
3880 hw->queues = MWL8K_TX_QUEUES;
3881
a66098da 3882 /* Set rssi and noise values to dBm */
ce9e2e1b 3883 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 3884 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 3885 hw->sta_data_size = sizeof(struct mwl8k_sta);
a66098da
LB		 3886 priv->vif = NULL;
3887
3888 /* Set default radio state and preamble */
c46563b7 3889 priv->radio_on = 0;
68ce3884 3890 priv->radio_short_preamble = 0;
a66098da 3891
bbfd9128
LB		 3892 /* Station database handling */
3893 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3894 spin_lock_init(&priv->sta_notify_list_lock);
3895 INIT_LIST_HEAD(&priv->sta_notify_list);
3896
a66098da
LB		 3897 /* Finalize join worker */
3898 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3899
67e2eb27 3900 /* TX reclaim and RX tasklets. */
1e9f9de3
LB		 3901 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
3902 tasklet_disable(&priv->poll_tx_task);
67e2eb27
LB		 3903 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
3904 tasklet_disable(&priv->poll_rx_task);
a66098da 3905
a66098da
LB		 3906 /* Power management cookie */
3907 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3908 if (priv->cookie == NULL)
be695fc4 3909 goto err_stop_firmware;
a66098da
LB		 3910
3911 rc = mwl8k_rxq_init(hw, 0);
3912 if (rc)
be695fc4 3913 goto err_free_cookie;
a66098da
LB		 3914 rxq_refill(hw, 0, INT_MAX);
3915
618952a7
LB		 3916 mutex_init(&priv->fw_mutex);
3917 priv->fw_mutex_owner = NULL;
3918 priv->fw_mutex_depth = 0;
618952a7
LB		 3919 priv->hostcmd_wait = NULL;
3920
a66098da
LB		 3921 spin_lock_init(&priv->tx_lock);
3922
88de754a
LB		 3923 priv->tx_wait = NULL;
3924
a66098da
LB		 3925 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3926 rc = mwl8k_txq_init(hw, i);
3927 if (rc)
3928 goto err_free_queues;
3929 }
3930
3931 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3932 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 3933 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 3934 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 3935 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3936
a0607fd3 3937 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3938 IRQF_SHARED, MWL8K_NAME, hw);
3939 if (rc) {
3940 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3941 wiphy_name(hw->wiphy));
a66098da
LB		 3942 goto err_free_queues;
3943 }
3944
a66098da
LB		 3945 /*
3946 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 3947 * commands use interrupts and avoid polling. Disable
a66098da
LB		 3948 * interrupts when done.
3949 */
c23b5a69 3950 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3951
3952 /* Get config data, mac addrs etc */
42fba21d
LB		 3953 if (priv->ap_fw) {
3954 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3955 if (!rc)
3956 rc = mwl8k_cmd_set_hw_spec(hw);
b64fe619
LB		 3957
3958 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
42fba21d
LB		 3959 } else {
3960 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB		 3961
3962 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 3963 }
a66098da 3964 if (rc) {
c2c357ce
LB		 3965 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3966 wiphy_name(hw->wiphy));
be695fc4 3967 goto err_free_irq;
a66098da
LB		 3968 }
3969
3970 /* Turn radio off */
55489b6e 3971 rc = mwl8k_cmd_radio_disable(hw);
a66098da 3972 if (rc) {
c2c357ce 3973 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 3974 goto err_free_irq;
a66098da
LB		 3975 }
3976
32060e1b 3977 /* Clear MAC address */
55489b6e 3978 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB		 3979 if (rc) {
3980 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3981 wiphy_name(hw->wiphy));
be695fc4 3982 goto err_free_irq;
32060e1b
LB		 3983 }
3984
a66098da 3985 /* Disable interrupts */
a66098da 3986 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3987 free_irq(priv->pdev->irq, hw);
3988
3989 rc = ieee80211_register_hw(hw);
3990 if (rc) {
c2c357ce
LB		 3991 printk(KERN_ERR "%s: Cannot register device\n",
3992 wiphy_name(hw->wiphy));
153458ff 3993 goto err_free_queues;
a66098da
LB		 3994 }
3995
eae74e65 3996 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3997 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3998 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3999 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 4000 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
4001 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 4002
4003 return 0;
4004
a66098da 4005err_free_irq:
a66098da 4006 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4007 free_irq(priv->pdev->irq, hw);
4008
4009err_free_queues:
4010 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4011 mwl8k_txq_deinit(hw, i);
4012 mwl8k_rxq_deinit(hw, 0);
4013
be695fc4 4014err_free_cookie:
a66098da
LB		 4015 if (priv->cookie != NULL)
4016 pci_free_consistent(priv->pdev, 4,
4017 priv->cookie, priv->cookie_dma);
4018
be695fc4
LB		 4019err_stop_firmware:
4020 mwl8k_hw_reset(priv);
4021 mwl8k_release_firmware(priv);
4022
4023err_iounmap:
a66098da
LB		 4024 if (priv->regs != NULL)
4025 pci_iounmap(pdev, priv->regs);
4026
5b9482dd
LB		 4027 if (priv->sram != NULL)
4028 pci_iounmap(pdev, priv->sram);
4029
a66098da
LB		 4030 pci_set_drvdata(pdev, NULL);
4031 ieee80211_free_hw(hw);
4032
4033err_free_reg:
4034 pci_release_regions(pdev);
3db95e50
LB		 4035
4036err_disable_device:
a66098da
LB		 4037 pci_disable_device(pdev);
4038
4039 return rc;
4040}
4041
230f7af0 4042static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 4043{
4044 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4045}
4046
230f7af0 4047static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 4048{
4049 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4050 struct mwl8k_priv *priv;
4051 int i;
4052
4053 if (hw == NULL)
4054 return;
4055 priv = hw->priv;
4056
4057 ieee80211_stop_queues(hw);
4058
60aa569f
LB		 4059 ieee80211_unregister_hw(hw);
4060
67e2eb27 4061 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4062 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4063 tasklet_kill(&priv->poll_rx_task);
a66098da 4064
a66098da
LB		 4065 /* Stop hardware */
4066 mwl8k_hw_reset(priv);
4067
4068 /* Return all skbs to mac80211 */
4069 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4070 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4071
a66098da
LB		 4072 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4073 mwl8k_txq_deinit(hw, i);
4074
4075 mwl8k_rxq_deinit(hw, 0);
4076
c2c357ce 4077 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 4078
4079 pci_iounmap(pdev, priv->regs);
5b9482dd 4080 pci_iounmap(pdev, priv->sram);
a66098da
LB		 4081 pci_set_drvdata(pdev, NULL);
4082 ieee80211_free_hw(hw);
4083 pci_release_regions(pdev);
4084 pci_disable_device(pdev);
4085}
4086
4087static struct pci_driver mwl8k_driver = {
4088 .name = MWL8K_NAME,
45a390dd 4089 .id_table = mwl8k_pci_id_table,
a66098da
LB		 4090 .probe = mwl8k_probe,
4091 .remove = __devexit_p(mwl8k_remove),
4092 .shutdown = __devexit_p(mwl8k_shutdown),
4093};
4094
4095static int __init mwl8k_init(void)
4096{
4097 return pci_register_driver(&mwl8k_driver);
4098}
4099
4100static void __exit mwl8k_exit(void)
4101{
4102 pci_unregister_driver(&mwl8k_driver);
4103}
4104
4105module_init(mwl8k_init);
4106module_exit(mwl8k_exit);
c2c357ce
LB		 4107
4108MODULE_DESCRIPTION(MWL8K_DESC);
4109MODULE_VERSION(MWL8K_VERSION);
4110MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4111MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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