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mwl8k: allow for different receive descriptor formats
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
a145d575 29#define MWL8K_VERSION "0.10"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status);
88};
89
45a390dd 90struct mwl8k_device_info {
a74b295e
LB		 91 char *part_name;
92 char *helper_image;
93 char *fw_image;
54bc3a0d 94 struct rxd_ops *rxd_ops;
45a390dd
LB		 95};
96
a66098da 97struct mwl8k_rx_queue {
45eb400d 98 int rxd_count;
a66098da
LB		 99
100 /* hw receives here */
45eb400d 101 int head;
a66098da
LB		 102
103 /* refill descs here */
45eb400d 104 int tail;
a66098da 105
54bc3a0d 106 void *rxd;
45eb400d 107 dma_addr_t rxd_dma;
788838eb
LB		 108 struct {
109 struct sk_buff *skb;
110 DECLARE_PCI_UNMAP_ADDR(dma)
111 } *buf;
a66098da
LB		 112};
113
a66098da
LB		 114struct mwl8k_tx_queue {
115 /* hw transmits here */
45eb400d 116 int head;
a66098da
LB		 117
118 /* sw appends here */
45eb400d 119 int tail;
a66098da 120
45eb400d
LB		 121 struct ieee80211_tx_queue_stats stats;
122 struct mwl8k_tx_desc *txd;
123 dma_addr_t txd_dma;
124 struct sk_buff **skb;
a66098da
LB		 125};
126
127/* Pointers to the firmware data and meta information about it. */
128struct mwl8k_firmware {
a66098da
LB		 129 /* Boot helper code */
130 struct firmware *helper;
a74b295e
LB		 131
132 /* Microcode */
133 struct firmware *ucode;
a66098da
LB		 134};
135
136struct mwl8k_priv {
5b9482dd 137 void __iomem *sram;
a66098da
LB		 138 void __iomem *regs;
139 struct ieee80211_hw *hw;
140
141 struct pci_dev *pdev;
a66098da 142
45a390dd 143 struct mwl8k_device_info *device_info;
eae74e65 144 bool ap_fw;
54bc3a0d 145 struct rxd_ops *rxd_ops;
45a390dd 146
a66098da
LB		 147 /* firmware files and meta data */
148 struct mwl8k_firmware fw;
a66098da 149
618952a7
LB		 150 /* firmware access */
151 struct mutex fw_mutex;
152 struct task_struct *fw_mutex_owner;
153 int fw_mutex_depth;
618952a7
LB		 154 struct completion *hostcmd_wait;
155
a66098da
LB		 156 /* lock held over TX and TX reap */
157 spinlock_t tx_lock;
a66098da 158
88de754a
LB		 159 /* TX quiesce completion, protected by fw_mutex and tx_lock */
160 struct completion *tx_wait;
161
a66098da 162 struct ieee80211_vif *vif;
a66098da
LB		 163
164 struct ieee80211_channel *current_channel;
165
166 /* power management status cookie from firmware */
167 u32 *cookie;
168 dma_addr_t cookie_dma;
169
170 u16 num_mcaddrs;
a66098da 171 u8 hw_rev;
2aa7b01f 172 u32 fw_rev;
a66098da
LB		 173
174 /*
175 * Running count of TX packets in flight, to avoid
176 * iterating over the transmit rings each time.
177 */
178 int pending_tx_pkts;
179
180 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
181 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
182
183 /* PHY parameters */
184 struct ieee80211_supported_band band;
185 struct ieee80211_channel channels[14];
5dfd3e2c 186 struct ieee80211_rate rates[13];
a66098da 187
c46563b7 188 bool radio_on;
68ce3884 189 bool radio_short_preamble;
a43c49a8 190 bool sniffer_enabled;
0439b1f5 191 bool wmm_enabled;
a66098da 192
a66098da
LB		 193 /* XXX need to convert this to handle multiple interfaces */
194 bool capture_beacon;
d89173f2 195 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 196 struct sk_buff *beacon_skb;
197
198 /*
199 * This FJ worker has to be global as it is scheduled from the
200 * RX handler. At this point we don't know which interface it
201 * belongs to until the list of bssids waiting to complete join
202 * is checked.
203 */
204 struct work_struct finalize_join_worker;
205
206 /* Tasklet to reclaim TX descriptors and buffers after tx */
207 struct tasklet_struct tx_reclaim_task;
a66098da
LB		 208};
209
210/* Per interface specific private data */
211struct mwl8k_vif {
a66098da
LB		 212 /* backpointer to parent config block */
213 struct mwl8k_priv *priv;
214
215 /* BSS config of AP or IBSS from mac80211*/
216 struct ieee80211_bss_conf bss_info;
217
218 /* BSSID of AP or IBSS */
d89173f2
LB		 219 u8 bssid[ETH_ALEN];
220 u8 mac_addr[ETH_ALEN];
a66098da
LB		 221
222 /*
223 * Subset of supported legacy rates.
224 * Intersection of AP and STA supported rates.
225 */
5dfd3e2c 226 struct ieee80211_rate legacy_rates[13];
a66098da
LB		 227
228 /* number of supported legacy rates */
229 u8 legacy_nrates;
230
a66098da
LB		 231 /* Index into station database.Returned by update_sta_db call */
232 u8 peer_id;
233
234 /* Non AMPDU sequence number assigned by driver */
235 u16 seqno;
a66098da
LB		 236};
237
a94cc97e 238#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da
LB		 239
240static const struct ieee80211_channel mwl8k_channels[] = {
241 { .center_freq = 2412, .hw_value = 1, },
242 { .center_freq = 2417, .hw_value = 2, },
243 { .center_freq = 2422, .hw_value = 3, },
244 { .center_freq = 2427, .hw_value = 4, },
245 { .center_freq = 2432, .hw_value = 5, },
246 { .center_freq = 2437, .hw_value = 6, },
247 { .center_freq = 2442, .hw_value = 7, },
248 { .center_freq = 2447, .hw_value = 8, },
249 { .center_freq = 2452, .hw_value = 9, },
250 { .center_freq = 2457, .hw_value = 10, },
251 { .center_freq = 2462, .hw_value = 11, },
252};
253
254static const struct ieee80211_rate mwl8k_rates[] = {
255 { .bitrate = 10, .hw_value = 2, },
256 { .bitrate = 20, .hw_value = 4, },
257 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 258 { .bitrate = 110, .hw_value = 22, },
259 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 260 { .bitrate = 60, .hw_value = 12, },
261 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 262 { .bitrate = 120, .hw_value = 24, },
263 { .bitrate = 180, .hw_value = 36, },
264 { .bitrate = 240, .hw_value = 48, },
265 { .bitrate = 360, .hw_value = 72, },
266 { .bitrate = 480, .hw_value = 96, },
267 { .bitrate = 540, .hw_value = 108, },
268};
269
a66098da
LB		 270/* Set or get info from Firmware */
271#define MWL8K_CMD_SET 0x0001
272#define MWL8K_CMD_GET 0x0000
273
274/* Firmware command codes */
275#define MWL8K_CMD_CODE_DNLD 0x0001
276#define MWL8K_CMD_GET_HW_SPEC 0x0003
277#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
278#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 279#define MWL8K_CMD_RADIO_CONTROL 0x001c
280#define MWL8K_CMD_RF_TX_POWER 0x001e
a66098da
LB		 281#define MWL8K_CMD_SET_PRE_SCAN 0x0107
282#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 283#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
284#define MWL8K_CMD_SET_AID 0x010d
285#define MWL8K_CMD_SET_RATE 0x0110
286#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
287#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 288#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 289#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
290#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 291#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 292#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 293#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 294#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 295#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
ff45fc60 296#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 297
298static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
299{
300#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
301 snprintf(buf, bufsize, "%s", #x);\
302 return buf;\
303 } while (0)
ce9e2e1b 304 switch (cmd & ~0x8000) {
a66098da
LB		 305 MWL8K_CMDNAME(CODE_DNLD);
306 MWL8K_CMDNAME(GET_HW_SPEC);
307 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
308 MWL8K_CMDNAME(GET_STAT);
309 MWL8K_CMDNAME(RADIO_CONTROL);
310 MWL8K_CMDNAME(RF_TX_POWER);
311 MWL8K_CMDNAME(SET_PRE_SCAN);
312 MWL8K_CMDNAME(SET_POST_SCAN);
313 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 314 MWL8K_CMDNAME(SET_AID);
315 MWL8K_CMDNAME(SET_RATE);
316 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
317 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 318 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 319 MWL8K_CMDNAME(SET_EDCA_PARAMS);
320 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 321 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 322 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 323 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 324 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 325 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
ff45fc60 326 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 327 default:
328 snprintf(buf, bufsize, "0x%x", cmd);
329 }
330#undef MWL8K_CMDNAME
331
332 return buf;
333}
334
335/* Hardware and firmware reset */
336static void mwl8k_hw_reset(struct mwl8k_priv *priv)
337{
338 iowrite32(MWL8K_H2A_INT_RESET,
339 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
340 iowrite32(MWL8K_H2A_INT_RESET,
341 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
342 msleep(20);
343}
344
345/* Release fw image */
346static void mwl8k_release_fw(struct firmware **fw)
347{
348 if (*fw == NULL)
349 return;
350 release_firmware(*fw);
351 *fw = NULL;
352}
353
354static void mwl8k_release_firmware(struct mwl8k_priv *priv)
355{
356 mwl8k_release_fw(&priv->fw.ucode);
357 mwl8k_release_fw(&priv->fw.helper);
358}
359
360/* Request fw image */
361static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 362 const char *fname, struct firmware **fw)
a66098da
LB		 363{
364 /* release current image */
365 if (*fw != NULL)
366 mwl8k_release_fw(fw);
367
368 return request_firmware((const struct firmware **)fw,
c2c357ce 369 fname, &priv->pdev->dev);
a66098da
LB		 370}
371
45a390dd 372static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 373{
a74b295e 374 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 375 int rc;
376
a74b295e
LB		 377 if (di->helper_image != NULL) {
378 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw.helper);
379 if (rc) {
380 printk(KERN_ERR "%s: Error requesting helper "
381 "firmware file %s\n", pci_name(priv->pdev),
382 di->helper_image);
383 return rc;
384 }
a66098da
LB		 385 }
386
a74b295e 387 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw.ucode);
a66098da 388 if (rc) {
c2c357ce 389 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 390 pci_name(priv->pdev), di->fw_image);
a66098da
LB		 391 mwl8k_release_fw(&priv->fw.helper);
392 return rc;
393 }
394
395 return 0;
396}
397
398struct mwl8k_cmd_pkt {
399 __le16 code;
400 __le16 length;
401 __le16 seq_num;
402 __le16 result;
403 char payload[0];
404} __attribute__((packed));
405
406/*
407 * Firmware loading.
408 */
409static int
410mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
411{
412 void __iomem *regs = priv->regs;
413 dma_addr_t dma_addr;
a66098da
LB		 414 int loops;
415
416 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
417 if (pci_dma_mapping_error(priv->pdev, dma_addr))
418 return -ENOMEM;
419
420 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
421 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
422 iowrite32(MWL8K_H2A_INT_DOORBELL,
423 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
424 iowrite32(MWL8K_H2A_INT_DUMMY,
425 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
426
a66098da
LB		 427 loops = 1000;
428 do {
429 u32 int_code;
430
431 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
432 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
433 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 434 break;
435 }
436
3d76e82c 437 cond_resched();
a66098da
LB		 438 udelay(1);
439 } while (--loops);
440
441 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
442
d4b70570 443 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 444}
445
446static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
447 const u8 *data, size_t length)
448{
449 struct mwl8k_cmd_pkt *cmd;
450 int done;
451 int rc = 0;
452
453 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
454 if (cmd == NULL)
455 return -ENOMEM;
456
457 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
458 cmd->seq_num = 0;
459 cmd->result = 0;
460
461 done = 0;
462 while (length) {
463 int block_size = length > 256 ? 256 : length;
464
465 memcpy(cmd->payload, data + done, block_size);
466 cmd->length = cpu_to_le16(block_size);
467
468 rc = mwl8k_send_fw_load_cmd(priv, cmd,
469 sizeof(*cmd) + block_size);
470 if (rc)
471 break;
472
473 done += block_size;
474 length -= block_size;
475 }
476
477 if (!rc) {
478 cmd->length = 0;
479 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
480 }
481
482 kfree(cmd);
483
484 return rc;
485}
486
487static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
488 const u8 *data, size_t length)
489{
490 unsigned char *buffer;
491 int may_continue, rc = 0;
492 u32 done, prev_block_size;
493
494 buffer = kmalloc(1024, GFP_KERNEL);
495 if (buffer == NULL)
496 return -ENOMEM;
497
498 done = 0;
499 prev_block_size = 0;
500 may_continue = 1000;
501 while (may_continue > 0) {
502 u32 block_size;
503
504 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
505 if (block_size & 1) {
506 block_size &= ~1;
507 may_continue--;
508 } else {
509 done += prev_block_size;
510 length -= prev_block_size;
511 }
512
513 if (block_size > 1024 || block_size > length) {
514 rc = -EOVERFLOW;
515 break;
516 }
517
518 if (length == 0) {
519 rc = 0;
520 break;
521 }
522
523 if (block_size == 0) {
524 rc = -EPROTO;
525 may_continue--;
526 udelay(1);
527 continue;
528 }
529
530 prev_block_size = block_size;
531 memcpy(buffer, data + done, block_size);
532
533 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
534 if (rc)
535 break;
536 }
537
538 if (!rc && length != 0)
539 rc = -EREMOTEIO;
540
541 kfree(buffer);
542
543 return rc;
544}
545
c2c357ce 546static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 547{
c2c357ce
LB		 548 struct mwl8k_priv *priv = hw->priv;
549 struct firmware *fw = priv->fw.ucode;
eae74e65 550 struct mwl8k_device_info *di = priv->device_info;
c2c357ce
LB		 551 int rc;
552 int loops;
553
554 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
555 struct firmware *helper = priv->fw.helper;
a66098da 556
c2c357ce
LB		 557 if (helper == NULL) {
558 printk(KERN_ERR "%s: helper image needed but none "
559 "given\n", pci_name(priv->pdev));
560 return -EINVAL;
561 }
a66098da 562
c2c357ce 563 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 564 if (rc) {
565 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 566 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 567 return rc;
568 }
569 msleep(1);
570
c2c357ce 571 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 572 } else {
c2c357ce 573 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 574 }
575
576 if (rc) {
c2c357ce
LB		 577 printk(KERN_ERR "%s: unable to load firmware image\n",
578 pci_name(priv->pdev));
a66098da
LB		 579 return rc;
580 }
581
eae74e65
LB		 582 if (di->modes & BIT(NL80211_IFTYPE_AP))
583 iowrite32(MWL8K_MODE_AP, priv->regs + MWL8K_HIU_GEN_PTR);
584 else
585 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da
LB		 586 msleep(1);
587
588 loops = 200000;
589 do {
eae74e65
LB		 590 u32 ready_code;
591
592 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
593 if (ready_code == MWL8K_FWAP_READY) {
594 priv->ap_fw = 1;
595 break;
596 } else if (ready_code == MWL8K_FWSTA_READY) {
597 priv->ap_fw = 0;
a66098da 598 break;
eae74e65
LB		 599 }
600
601 cond_resched();
a66098da
LB		 602 udelay(1);
603 } while (--loops);
604
605 return loops ? 0 : -ETIMEDOUT;
606}
607
608
609/*
610 * Defines shared between transmission and reception.
611 */
612/* HT control fields for firmware */
613struct ewc_ht_info {
614 __le16 control1;
615 __le16 control2;
616 __le16 control3;
617} __attribute__((packed));
618
619/* Firmware Station database operations */
620#define MWL8K_STA_DB_ADD_ENTRY 0
621#define MWL8K_STA_DB_MODIFY_ENTRY 1
622#define MWL8K_STA_DB_DEL_ENTRY 2
623#define MWL8K_STA_DB_FLUSH 3
624
625/* Peer Entry flags - used to define the type of the peer node */
626#define MWL8K_PEER_TYPE_ACCESSPOINT 2
a66098da 627
5dfd3e2c 628#define MWL8K_IEEE_LEGACY_DATA_RATES 13
a66098da 629#define MWL8K_MCS_BITMAP_SIZE 16
a66098da
LB		 630
631struct peer_capability_info {
632 /* Peer type - AP vs. STA. */
633 __u8 peer_type;
634
635 /* Basic 802.11 capabilities from assoc resp. */
636 __le16 basic_caps;
637
638 /* Set if peer supports 802.11n high throughput (HT). */
639 __u8 ht_support;
640
641 /* Valid if HT is supported. */
642 __le16 ht_caps;
643 __u8 extended_ht_caps;
644 struct ewc_ht_info ewc_info;
645
646 /* Legacy rate table. Intersection of our rates and peer rates. */
647 __u8 legacy_rates[MWL8K_IEEE_LEGACY_DATA_RATES];
648
649 /* HT rate table. Intersection of our rates and peer rates. */
650 __u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
c23b5a69 651 __u8 pad[16];
a66098da
LB		 652
653 /* If set, interoperability mode, no proprietary extensions. */
654 __u8 interop;
655 __u8 pad2;
656 __u8 station_id;
657 __le16 amsdu_enabled;
658} __attribute__((packed));
659
660/* Inline functions to manipulate QoS field in data descriptor. */
a66098da
LB		 661static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
662{
663 u16 val_mask = 1 << 4;
664
665 /* End of Service Period Bit 4 */
666 return qos | val_mask;
667}
668
669static inline u16 mwl8k_qos_setbit_ack(u16 qos, u8 ack_policy)
670{
671 u16 val_mask = 0x3;
672 u8 shift = 5;
673 u16 qos_mask = ~(val_mask << shift);
674
675 /* Ack Policy Bit 5-6 */
676 return (qos & qos_mask) | ((ack_policy & val_mask) << shift);
677}
678
679static inline u16 mwl8k_qos_setbit_amsdu(u16 qos)
680{
681 u16 val_mask = 1 << 7;
682
683 /* AMSDU present Bit 7 */
684 return qos | val_mask;
685}
686
687static inline u16 mwl8k_qos_setbit_qlen(u16 qos, u8 len)
688{
689 u16 val_mask = 0xff;
690 u8 shift = 8;
691 u16 qos_mask = ~(val_mask << shift);
692
693 /* Queue Length Bits 8-15 */
694 return (qos & qos_mask) | ((len & val_mask) << shift);
695}
696
697/* DMA header used by firmware and hardware. */
698struct mwl8k_dma_data {
699 __le16 fwlen;
700 struct ieee80211_hdr wh;
701} __attribute__((packed));
702
703/* Routines to add/remove DMA header from skb. */
76266b2a 704static inline void mwl8k_remove_dma_header(struct sk_buff *skb)
a66098da 705{
76266b2a 706 struct mwl8k_dma_data *tr = (struct mwl8k_dma_data *)skb->data;
a66098da 707 void *dst, *src = &tr->wh;
76266b2a 708 int hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
a66098da
LB		 709 u16 space = sizeof(struct mwl8k_dma_data) - hdrlen;
710
711 dst = (void *)tr + space;
712 if (dst != src) {
713 memmove(dst, src, hdrlen);
714 skb_pull(skb, space);
715 }
a66098da
LB		 716}
717
76266b2a 718static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 719{
720 struct ieee80211_hdr *wh;
721 u32 hdrlen, pktlen;
722 struct mwl8k_dma_data *tr;
723
724 wh = (struct ieee80211_hdr *)skb->data;
725 hdrlen = ieee80211_hdrlen(wh->frame_control);
726 pktlen = skb->len;
727
728 /*
729 * Copy up/down the 802.11 header; the firmware requires
730 * we present a 2-byte payload length followed by a
731 * 4-address header (w/o QoS), followed (optionally) by
732 * any WEP/ExtIV header (but only filled in for CCMP).
733 */
734 if (hdrlen != sizeof(struct mwl8k_dma_data))
735 skb_push(skb, sizeof(struct mwl8k_dma_data) - hdrlen);
736
737 tr = (struct mwl8k_dma_data *)skb->data;
738 if (wh != &tr->wh)
739 memmove(&tr->wh, wh, hdrlen);
740
741 /* Clear addr4 */
d89173f2 742 memset(tr->wh.addr4, 0, ETH_ALEN);
a66098da
LB		 743
744 /*
745 * Firmware length is the length of the fully formed "802.11
746 * payload". That is, everything except for the 802.11 header.
747 * This includes all crypto material including the MIC.
748 */
749 tr->fwlen = cpu_to_le16(pktlen - hdrlen);
a66098da
LB		 750}
751
752
753/*
754 * Packet reception.
755 */
54bc3a0d 756struct mwl8k_rxd_8687 {
a66098da
LB		 757 __le16 pkt_len;
758 __u8 link_quality;
759 __u8 noise_level;
760 __le32 pkt_phys_addr;
45eb400d 761 __le32 next_rxd_phys_addr;
a66098da
LB		 762 __le16 qos_control;
763 __le16 rate_info;
764 __le32 pad0[4];
765 __u8 rssi;
766 __u8 channel;
767 __le16 pad1;
768 __u8 rx_ctrl;
769 __u8 rx_status;
770 __u8 pad2[2];
771} __attribute__((packed));
772
54bc3a0d
LB		 773#define MWL8K_8687_RATE_INFO_SHORTPRE 0x8000
774#define MWL8K_8687_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
775#define MWL8K_8687_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
776#define MWL8K_8687_RATE_INFO_40MHZ 0x0004
777#define MWL8K_8687_RATE_INFO_SHORTGI 0x0002
778#define MWL8K_8687_RATE_INFO_MCS_FORMAT 0x0001
779
780#define MWL8K_8687_RX_CTRL_OWNED_BY_HOST 0x02
781
782static void mwl8k_rxd_8687_init(void *_rxd, dma_addr_t next_dma_addr)
783{
784 struct mwl8k_rxd_8687 *rxd = _rxd;
785
786 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
787 rxd->rx_ctrl = MWL8K_8687_RX_CTRL_OWNED_BY_HOST;
788}
789
790static void mwl8k_rxd_8687_refill(void *_rxd, dma_addr_t addr, int len)
791{
792 struct mwl8k_rxd_8687 *rxd = _rxd;
793
794 rxd->pkt_len = cpu_to_le16(len);
795 rxd->pkt_phys_addr = cpu_to_le32(addr);
796 wmb();
797 rxd->rx_ctrl = 0;
798}
799
800static int
801mwl8k_rxd_8687_process(void *_rxd, struct ieee80211_rx_status *status)
802{
803 struct mwl8k_rxd_8687 *rxd = _rxd;
804 u16 rate_info;
805
806 if (!(rxd->rx_ctrl & MWL8K_8687_RX_CTRL_OWNED_BY_HOST))
807 return -1;
808 rmb();
809
810 rate_info = le16_to_cpu(rxd->rate_info);
811
812 memset(status, 0, sizeof(*status));
813
814 status->signal = -rxd->rssi;
815 status->noise = -rxd->noise_level;
816 status->qual = rxd->link_quality;
817 status->antenna = MWL8K_8687_RATE_INFO_ANTSELECT(rate_info);
818 status->rate_idx = MWL8K_8687_RATE_INFO_RATEID(rate_info);
819
820 if (rate_info & MWL8K_8687_RATE_INFO_SHORTPRE)
821 status->flag |= RX_FLAG_SHORTPRE;
822 if (rate_info & MWL8K_8687_RATE_INFO_40MHZ)
823 status->flag |= RX_FLAG_40MHZ;
824 if (rate_info & MWL8K_8687_RATE_INFO_SHORTGI)
825 status->flag |= RX_FLAG_SHORT_GI;
826 if (rate_info & MWL8K_8687_RATE_INFO_MCS_FORMAT)
827 status->flag |= RX_FLAG_HT;
828
829 status->band = IEEE80211_BAND_2GHZ;
830 status->freq = ieee80211_channel_to_frequency(rxd->channel);
831
832 return le16_to_cpu(rxd->pkt_len);
833}
834
835static struct rxd_ops rxd_8687_ops = {
836 .rxd_size = sizeof(struct mwl8k_rxd_8687),
837 .rxd_init = mwl8k_rxd_8687_init,
838 .rxd_refill = mwl8k_rxd_8687_refill,
839 .rxd_process = mwl8k_rxd_8687_process,
840};
841
842
a66098da
LB		 843#define MWL8K_RX_DESCS 256
844#define MWL8K_RX_MAXSZ 3800
845
846static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
847{
848 struct mwl8k_priv *priv = hw->priv;
849 struct mwl8k_rx_queue *rxq = priv->rxq + index;
850 int size;
851 int i;
852
45eb400d
LB		 853 rxq->rxd_count = 0;
854 rxq->head = 0;
855 rxq->tail = 0;
a66098da 856
54bc3a0d 857 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 858
45eb400d
LB		 859 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
860 if (rxq->rxd == NULL) {
a66098da 861 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 862 wiphy_name(hw->wiphy));
a66098da
LB		 863 return -ENOMEM;
864 }
45eb400d 865 memset(rxq->rxd, 0, size);
a66098da 866
788838eb
LB		 867 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
868 if (rxq->buf == NULL) {
a66098da 869 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 870 wiphy_name(hw->wiphy));
45eb400d 871 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 872 return -ENOMEM;
873 }
788838eb 874 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 875
876 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 877 int desc_size;
878 void *rxd;
a66098da 879 int nexti;
54bc3a0d
LB		 880 dma_addr_t next_dma_addr;
881
882 desc_size = priv->rxd_ops->rxd_size;
883 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 884
54bc3a0d
LB		 885 nexti = i + 1;
886 if (nexti == MWL8K_RX_DESCS)
887 nexti = 0;
888 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 889
54bc3a0d 890 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 891 }
892
893 return 0;
894}
895
896static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
897{
898 struct mwl8k_priv *priv = hw->priv;
899 struct mwl8k_rx_queue *rxq = priv->rxq + index;
900 int refilled;
901
902 refilled = 0;
45eb400d 903 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 904 struct sk_buff *skb;
788838eb 905 dma_addr_t addr;
a66098da 906 int rx;
54bc3a0d 907 void *rxd;
a66098da
LB		 908
909 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
910 if (skb == NULL)
911 break;
912
788838eb
LB		 913 addr = pci_map_single(priv->pdev, skb->data,
914 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 915
54bc3a0d
LB		 916 rxq->rxd_count++;
917 rx = rxq->tail++;
918 if (rxq->tail == MWL8K_RX_DESCS)
919 rxq->tail = 0;
788838eb
LB		 920 rxq->buf[rx].skb = skb;
921 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 922
923 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
924 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 925
926 refilled++;
927 }
928
929 return refilled;
930}
931
932/* Must be called only when the card's reception is completely halted */
933static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
934{
935 struct mwl8k_priv *priv = hw->priv;
936 struct mwl8k_rx_queue *rxq = priv->rxq + index;
937 int i;
938
939 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 940 if (rxq->buf[i].skb != NULL) {
941 pci_unmap_single(priv->pdev,
942 pci_unmap_addr(&rxq->buf[i], dma),
943 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
944 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
945
946 kfree_skb(rxq->buf[i].skb);
947 rxq->buf[i].skb = NULL;
a66098da
LB		 948 }
949 }
950
788838eb
LB		 951 kfree(rxq->buf);
952 rxq->buf = NULL;
a66098da
LB		 953
954 pci_free_consistent(priv->pdev,
54bc3a0d 955 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 956 rxq->rxd, rxq->rxd_dma);
957 rxq->rxd = NULL;
a66098da
LB		 958}
959
960
961/*
962 * Scan a list of BSSIDs to process for finalize join.
963 * Allows for extension to process multiple BSSIDs.
964 */
965static inline int
966mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
967{
968 return priv->capture_beacon &&
969 ieee80211_is_beacon(wh->frame_control) &&
970 !compare_ether_addr(wh->addr3, priv->capture_bssid);
971}
972
3779752d
LB		 973static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
974 struct sk_buff *skb)
a66098da 975{
3779752d
LB		 976 struct mwl8k_priv *priv = hw->priv;
977
a66098da 978 priv->capture_beacon = false;
d89173f2 979 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 980
981 /*
982 * Use GFP_ATOMIC as rxq_process is called from
983 * the primary interrupt handler, memory allocation call
984 * must not sleep.
985 */
986 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
987 if (priv->beacon_skb != NULL)
3779752d 988 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 989}
990
991static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
992{
993 struct mwl8k_priv *priv = hw->priv;
994 struct mwl8k_rx_queue *rxq = priv->rxq + index;
995 int processed;
996
997 processed = 0;
45eb400d 998 while (rxq->rxd_count && limit--) {
a66098da 999 struct sk_buff *skb;
54bc3a0d
LB		 1000 void *rxd;
1001 int pkt_len;
a66098da 1002 struct ieee80211_rx_status status;
a66098da 1003
788838eb 1004 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1005 if (skb == NULL)
1006 break;
54bc3a0d
LB		 1007
1008 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1009
1010 pkt_len = priv->rxd_ops->rxd_process(rxd, &status);
1011 if (pkt_len < 0)
1012 break;
1013
788838eb
LB		 1014 rxq->buf[rxq->head].skb = NULL;
1015
1016 pci_unmap_single(priv->pdev,
1017 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1018 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1019 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1020
54bc3a0d
LB		 1021 rxq->head++;
1022 if (rxq->head == MWL8K_RX_DESCS)
1023 rxq->head = 0;
1024
45eb400d 1025 rxq->rxd_count--;
a66098da 1026
54bc3a0d 1027 skb_put(skb, pkt_len);
76266b2a 1028 mwl8k_remove_dma_header(skb);
a66098da 1029
a66098da 1030 /*
c2c357ce
LB		 1031 * Check for a pending join operation. Save a
1032 * copy of the beacon and schedule a tasklet to
1033 * send a FINALIZE_JOIN command to the firmware.
a66098da 1034 */
54bc3a0d 1035 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1036 mwl8k_save_beacon(hw, skb);
a66098da 1037
f1d58c25
JB		 1038 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1039 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1040
1041 processed++;
1042 }
1043
1044 return processed;
1045}
1046
1047
1048/*
1049 * Packet transmission.
1050 */
1051
a66098da
LB		 1052/* Transmit packet ACK policy */
1053#define MWL8K_TXD_ACK_POLICY_NORMAL 0
a66098da
LB		 1054#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
1055
a66098da
LB		 1056#define MWL8K_TXD_STATUS_OK 0x00000001
1057#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1058#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1059#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1060#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da
LB		 1061
1062struct mwl8k_tx_desc {
1063 __le32 status;
1064 __u8 data_rate;
1065 __u8 tx_priority;
1066 __le16 qos_control;
1067 __le32 pkt_phys_addr;
1068 __le16 pkt_len;
d89173f2 1069 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1070 __le32 next_txd_phys_addr;
a66098da
LB		 1071 __le32 reserved;
1072 __le16 rate_info;
1073 __u8 peer_id;
1074 __u8 tx_frag_cnt;
1075} __attribute__((packed));
1076
1077#define MWL8K_TX_DESCS 128
1078
1079static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1080{
1081 struct mwl8k_priv *priv = hw->priv;
1082 struct mwl8k_tx_queue *txq = priv->txq + index;
1083 int size;
1084 int i;
1085
45eb400d
LB		 1086 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1087 txq->stats.limit = MWL8K_TX_DESCS;
1088 txq->head = 0;
1089 txq->tail = 0;
a66098da
LB		 1090
1091 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1092
45eb400d
LB		 1093 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1094 if (txq->txd == NULL) {
a66098da 1095 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1096 wiphy_name(hw->wiphy));
a66098da
LB		 1097 return -ENOMEM;
1098 }
45eb400d 1099 memset(txq->txd, 0, size);
a66098da 1100
45eb400d
LB		 1101 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1102 if (txq->skb == NULL) {
a66098da 1103 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1104 wiphy_name(hw->wiphy));
45eb400d 1105 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1106 return -ENOMEM;
1107 }
45eb400d 1108 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1109
1110 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1111 struct mwl8k_tx_desc *tx_desc;
1112 int nexti;
1113
45eb400d 1114 tx_desc = txq->txd + i;
a66098da
LB		 1115 nexti = (i + 1) % MWL8K_TX_DESCS;
1116
1117 tx_desc->status = 0;
45eb400d
LB		 1118 tx_desc->next_txd_phys_addr =
1119 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1120 }
1121
1122 return 0;
1123}
1124
1125static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1126{
1127 iowrite32(MWL8K_H2A_INT_PPA_READY,
1128 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1129 iowrite32(MWL8K_H2A_INT_DUMMY,
1130 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1131 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1132}
1133
a66098da
LB		 1134struct mwl8k_txq_info {
1135 u32 fw_owned;
1136 u32 drv_owned;
1137 u32 unused;
1138 u32 len;
1139 u32 head;
1140 u32 tail;
1141};
1142
1143static int mwl8k_scan_tx_ring(struct mwl8k_priv *priv,
c3f967d3 1144 struct mwl8k_txq_info *txinfo)
a66098da
LB		 1145{
1146 int count, desc, status;
1147 struct mwl8k_tx_queue *txq;
1148 struct mwl8k_tx_desc *tx_desc;
1149 int ndescs = 0;
1150
c3f967d3
LB		 1151 memset(txinfo, 0, MWL8K_TX_QUEUES * sizeof(struct mwl8k_txq_info));
1152
c3f967d3 1153 for (count = 0; count < MWL8K_TX_QUEUES; count++) {
a66098da 1154 txq = priv->txq + count;
45eb400d
LB		 1155 txinfo[count].len = txq->stats.len;
1156 txinfo[count].head = txq->head;
1157 txinfo[count].tail = txq->tail;
a66098da 1158 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
45eb400d 1159 tx_desc = txq->txd + desc;
a66098da
LB		 1160 status = le32_to_cpu(tx_desc->status);
1161
1162 if (status & MWL8K_TXD_STATUS_FW_OWNED)
1163 txinfo[count].fw_owned++;
1164 else
1165 txinfo[count].drv_owned++;
1166
1167 if (tx_desc->pkt_len == 0)
1168 txinfo[count].unused++;
1169 }
1170 }
a66098da
LB		 1171
1172 return ndescs;
1173}
1174
618952a7 1175/*
88de754a 1176 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1177 */
950d5b01 1178static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1179{
a66098da 1180 struct mwl8k_priv *priv = hw->priv;
88de754a 1181 DECLARE_COMPLETION_ONSTACK(tx_wait);
ce9e2e1b
LB		 1182 u32 count;
1183 unsigned long timeout;
a66098da
LB		 1184
1185 might_sleep();
1186
a66098da 1187 spin_lock_bh(&priv->tx_lock);
88de754a
LB		 1188 count = priv->pending_tx_pkts;
1189 if (count)
1190 priv->tx_wait = &tx_wait;
a66098da
LB		 1191 spin_unlock_bh(&priv->tx_lock);
1192
1193 if (count) {
c3f967d3 1194 struct mwl8k_txq_info txinfo[MWL8K_TX_QUEUES];
a66098da
LB		 1195 int index;
1196 int newcount;
1197
88de754a 1198 timeout = wait_for_completion_timeout(&tx_wait,
618952a7 1199 msecs_to_jiffies(5000));
a66098da
LB		 1200 if (timeout)
1201 return 0;
1202
1203 spin_lock_bh(&priv->tx_lock);
1204 priv->tx_wait = NULL;
88de754a
LB		 1205 newcount = priv->pending_tx_pkts;
1206 mwl8k_scan_tx_ring(priv, txinfo);
a66098da
LB		 1207 spin_unlock_bh(&priv->tx_lock);
1208
618952a7 1209 printk(KERN_ERR "%s(%u) TIMEDOUT:5000ms Pend:%u-->%u\n",
950d5b01 1210 __func__, __LINE__, count, newcount);
a66098da 1211
c3f967d3 1212 for (index = 0; index < MWL8K_TX_QUEUES; index++)
c2c357ce
LB		 1213 printk(KERN_ERR "TXQ:%u L:%u H:%u T:%u FW:%u "
1214 "DRV:%u U:%u\n",
a66098da
LB		 1215 index,
1216 txinfo[index].len,
1217 txinfo[index].head,
1218 txinfo[index].tail,
1219 txinfo[index].fw_owned,
1220 txinfo[index].drv_owned,
1221 txinfo[index].unused);
ce9e2e1b 1222
a66098da
LB		 1223 return -ETIMEDOUT;
1224 }
1225
1226 return 0;
1227}
1228
c23b5a69
LB		 1229#define MWL8K_TXD_SUCCESS(status) \
1230 ((status) & (MWL8K_TXD_STATUS_OK | \
1231 MWL8K_TXD_STATUS_OK_RETRY | \
1232 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da
LB		 1233
1234static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
1235{
1236 struct mwl8k_priv *priv = hw->priv;
1237 struct mwl8k_tx_queue *txq = priv->txq + index;
1238 int wake = 0;
1239
45eb400d 1240 while (txq->stats.len > 0) {
a66098da 1241 int tx;
a66098da
LB		 1242 struct mwl8k_tx_desc *tx_desc;
1243 unsigned long addr;
ce9e2e1b 1244 int size;
a66098da
LB		 1245 struct sk_buff *skb;
1246 struct ieee80211_tx_info *info;
1247 u32 status;
1248
45eb400d
LB		 1249 tx = txq->head;
1250 tx_desc = txq->txd + tx;
a66098da
LB		 1251
1252 status = le32_to_cpu(tx_desc->status);
1253
1254 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1255 if (!force)
1256 break;
1257 tx_desc->status &=
1258 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1259 }
1260
45eb400d
LB		 1261 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1262 BUG_ON(txq->stats.len == 0);
1263 txq->stats.len--;
a66098da
LB		 1264 priv->pending_tx_pkts--;
1265
1266 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1267 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1268 skb = txq->skb[tx];
1269 txq->skb[tx] = NULL;
a66098da
LB		 1270
1271 BUG_ON(skb == NULL);
1272 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1273
76266b2a 1274 mwl8k_remove_dma_header(skb);
a66098da
LB		 1275
1276 /* Mark descriptor as unused */
1277 tx_desc->pkt_phys_addr = 0;
1278 tx_desc->pkt_len = 0;
1279
a66098da
LB		 1280 info = IEEE80211_SKB_CB(skb);
1281 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1282 if (MWL8K_TXD_SUCCESS(status))
a66098da 1283 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1284
1285 ieee80211_tx_status_irqsafe(hw, skb);
1286
618952a7 1287 wake = 1;
a66098da
LB		 1288 }
1289
618952a7 1290 if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da
LB		 1291 ieee80211_wake_queue(hw, index);
1292}
1293
1294/* must be called only when the card's transmit is completely halted */
1295static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1296{
1297 struct mwl8k_priv *priv = hw->priv;
1298 struct mwl8k_tx_queue *txq = priv->txq + index;
1299
1300 mwl8k_txq_reclaim(hw, index, 1);
1301
45eb400d
LB		 1302 kfree(txq->skb);
1303 txq->skb = NULL;
a66098da
LB		 1304
1305 pci_free_consistent(priv->pdev,
1306 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1307 txq->txd, txq->txd_dma);
1308 txq->txd = NULL;
a66098da
LB		 1309}
1310
1311static int
1312mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1313{
1314 struct mwl8k_priv *priv = hw->priv;
1315 struct ieee80211_tx_info *tx_info;
23b33906 1316 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1317 struct ieee80211_hdr *wh;
1318 struct mwl8k_tx_queue *txq;
1319 struct mwl8k_tx_desc *tx;
a66098da 1320 dma_addr_t dma;
23b33906
LB		 1321 u32 txstatus;
1322 u8 txdatarate;
1323 u16 qos;
a66098da 1324
23b33906
LB		 1325 wh = (struct ieee80211_hdr *)skb->data;
1326 if (ieee80211_is_data_qos(wh->frame_control))
1327 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1328 else
1329 qos = 0;
a66098da 1330
76266b2a 1331 mwl8k_add_dma_header(skb);
23b33906 1332 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1333
1334 tx_info = IEEE80211_SKB_CB(skb);
1335 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1336
1337 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1338 u16 seqno = mwl8k_vif->seqno;
23b33906 1339
a66098da
LB		 1340 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1341 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1342 mwl8k_vif->seqno = seqno++ % 4096;
1343 }
1344
23b33906
LB		 1345 /* Setup firmware control bit fields for each frame type. */
1346 txstatus = 0;
1347 txdatarate = 0;
1348 if (ieee80211_is_mgmt(wh->frame_control) ||
1349 ieee80211_is_ctl(wh->frame_control)) {
1350 txdatarate = 0;
1351 qos = mwl8k_qos_setbit_eosp(qos);
1352 /* Set Queue size to unspecified */
1353 qos = mwl8k_qos_setbit_qlen(qos, 0xff);
1354 } else if (ieee80211_is_data(wh->frame_control)) {
1355 txdatarate = 1;
1356 if (is_multicast_ether_addr(wh->addr1))
1357 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1358
1359 /* Send pkt in an aggregate if AMPDU frame. */
1360 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1361 qos = mwl8k_qos_setbit_ack(qos,
1362 MWL8K_TXD_ACK_POLICY_BLOCKACK);
1363 else
1364 qos = mwl8k_qos_setbit_ack(qos,
1365 MWL8K_TXD_ACK_POLICY_NORMAL);
1366
1367 if (qos & IEEE80211_QOS_CONTROL_A_MSDU_PRESENT)
1368 qos = mwl8k_qos_setbit_amsdu(qos);
1369 }
a66098da
LB		 1370
1371 dma = pci_map_single(priv->pdev, skb->data,
1372 skb->len, PCI_DMA_TODEVICE);
1373
1374 if (pci_dma_mapping_error(priv->pdev, dma)) {
1375 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1376 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1377 dev_kfree_skb(skb);
a66098da
LB		 1378 return NETDEV_TX_OK;
1379 }
1380
23b33906 1381 spin_lock_bh(&priv->tx_lock);
a66098da 1382
23b33906 1383 txq = priv->txq + index;
a66098da 1384
45eb400d
LB		 1385 BUG_ON(txq->skb[txq->tail] != NULL);
1386 txq->skb[txq->tail] = skb;
a66098da 1387
45eb400d 1388 tx = txq->txd + txq->tail;
23b33906
LB		 1389 tx->data_rate = txdatarate;
1390 tx->tx_priority = index;
a66098da 1391 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1392 tx->pkt_phys_addr = cpu_to_le32(dma);
1393 tx->pkt_len = cpu_to_le16(skb->len);
23b33906
LB		 1394 tx->rate_info = 0;
1395 tx->peer_id = mwl8k_vif->peer_id;
a66098da 1396 wmb();
23b33906
LB		 1397 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1398
45eb400d
LB		 1399 txq->stats.count++;
1400 txq->stats.len++;
a66098da 1401 priv->pending_tx_pkts++;
a66098da 1402
45eb400d
LB		 1403 txq->tail++;
1404 if (txq->tail == MWL8K_TX_DESCS)
1405 txq->tail = 0;
23b33906 1406
45eb400d 1407 if (txq->head == txq->tail)
a66098da
LB		 1408 ieee80211_stop_queue(hw, index);
1409
23b33906 1410 mwl8k_tx_start(priv);
a66098da
LB		 1411
1412 spin_unlock_bh(&priv->tx_lock);
1413
1414 return NETDEV_TX_OK;
1415}
1416
1417
618952a7
LB		 1418/*
1419 * Firmware access.
1420 *
1421 * We have the following requirements for issuing firmware commands:
1422 * - Some commands require that the packet transmit path is idle when
1423 * the command is issued. (For simplicity, we'll just quiesce the
1424 * transmit path for every command.)
1425 * - There are certain sequences of commands that need to be issued to
1426 * the hardware sequentially, with no other intervening commands.
1427 *
1428 * This leads to an implementation of a "firmware lock" as a mutex that
1429 * can be taken recursively, and which is taken by both the low-level
1430 * command submission function (mwl8k_post_cmd) as well as any users of
1431 * that function that require issuing of an atomic sequence of commands,
1432 * and quiesces the transmit path whenever it's taken.
1433 */
1434static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1435{
1436 struct mwl8k_priv *priv = hw->priv;
1437
1438 if (priv->fw_mutex_owner != current) {
1439 int rc;
1440
1441 mutex_lock(&priv->fw_mutex);
1442 ieee80211_stop_queues(hw);
1443
1444 rc = mwl8k_tx_wait_empty(hw);
1445 if (rc) {
1446 ieee80211_wake_queues(hw);
1447 mutex_unlock(&priv->fw_mutex);
1448
1449 return rc;
1450 }
1451
1452 priv->fw_mutex_owner = current;
1453 }
1454
1455 priv->fw_mutex_depth++;
1456
1457 return 0;
1458}
1459
1460static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1461{
1462 struct mwl8k_priv *priv = hw->priv;
1463
1464 if (!--priv->fw_mutex_depth) {
1465 ieee80211_wake_queues(hw);
1466 priv->fw_mutex_owner = NULL;
1467 mutex_unlock(&priv->fw_mutex);
1468 }
1469}
1470
1471
a66098da
LB		 1472/*
1473 * Command processing.
1474 */
1475
1476/* Timeout firmware commands after 2000ms */
1477#define MWL8K_CMD_TIMEOUT_MS 2000
1478
1479static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1480{
1481 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1482 struct mwl8k_priv *priv = hw->priv;
1483 void __iomem *regs = priv->regs;
1484 dma_addr_t dma_addr;
1485 unsigned int dma_size;
1486 int rc;
a66098da
LB		 1487 unsigned long timeout = 0;
1488 u8 buf[32];
1489
c2c357ce 1490 cmd->result = 0xffff;
a66098da
LB		 1491 dma_size = le16_to_cpu(cmd->length);
1492 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1493 PCI_DMA_BIDIRECTIONAL);
1494 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1495 return -ENOMEM;
1496
618952a7 1497 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1498 if (rc) {
1499 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1500 PCI_DMA_BIDIRECTIONAL);
618952a7 1501 return rc;
39a1e42e 1502 }
a66098da 1503
a66098da
LB		 1504 priv->hostcmd_wait = &cmd_wait;
1505 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1506 iowrite32(MWL8K_H2A_INT_DOORBELL,
1507 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1508 iowrite32(MWL8K_H2A_INT_DUMMY,
1509 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1510
1511 timeout = wait_for_completion_timeout(&cmd_wait,
1512 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1513
618952a7
LB		 1514 priv->hostcmd_wait = NULL;
1515
1516 mwl8k_fw_unlock(hw);
1517
37055bd4
LB		 1518 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1519 PCI_DMA_BIDIRECTIONAL);
1520
a66098da 1521 if (!timeout) {
a66098da 1522 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1523 wiphy_name(hw->wiphy),
a66098da
LB		 1524 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1525 MWL8K_CMD_TIMEOUT_MS);
1526 rc = -ETIMEDOUT;
1527 } else {
ce9e2e1b 1528 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1529 if (rc)
1530 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1531 wiphy_name(hw->wiphy),
a66098da 1532 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1533 le16_to_cpu(cmd->result));
a66098da
LB		 1534 }
1535
a66098da
LB		 1536 return rc;
1537}
1538
1539/*
1540 * GET_HW_SPEC.
1541 */
1542struct mwl8k_cmd_get_hw_spec {
1543 struct mwl8k_cmd_pkt header;
1544 __u8 hw_rev;
1545 __u8 host_interface;
1546 __le16 num_mcaddrs;
d89173f2 1547 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1548 __le16 region_code;
1549 __le32 fw_rev;
1550 __le32 ps_cookie;
1551 __le32 caps;
1552 __u8 mcs_bitmap[16];
1553 __le32 rx_queue_ptr;
1554 __le32 num_tx_queues;
1555 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1556 __le32 caps2;
1557 __le32 num_tx_desc_per_queue;
45eb400d 1558 __le32 total_rxd;
a66098da
LB		 1559} __attribute__((packed));
1560
1561static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
1562{
1563 struct mwl8k_priv *priv = hw->priv;
1564 struct mwl8k_cmd_get_hw_spec *cmd;
1565 int rc;
1566 int i;
1567
1568 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1569 if (cmd == NULL)
1570 return -ENOMEM;
1571
1572 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1573 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1574
1575 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1576 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1577 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1578 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1579 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1580 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1581 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1582 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1583
1584 rc = mwl8k_post_cmd(hw, &cmd->header);
1585
1586 if (!rc) {
1587 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1588 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1589 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1590 priv->hw_rev = cmd->hw_rev;
a66098da
LB		 1591 }
1592
1593 kfree(cmd);
1594 return rc;
1595}
1596
1597/*
1598 * CMD_MAC_MULTICAST_ADR.
1599 */
1600struct mwl8k_cmd_mac_multicast_adr {
1601 struct mwl8k_cmd_pkt header;
1602 __le16 action;
1603 __le16 numaddr;
ce9e2e1b 1604 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1605};
1606
d5e30845
LB		 1607#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1608#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1609#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1610#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1611
e81cd2d6 1612static struct mwl8k_cmd_pkt *
447ced07 1613__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1614 int mc_count, struct dev_addr_list *mclist)
a66098da 1615{
e81cd2d6 1616 struct mwl8k_priv *priv = hw->priv;
a66098da 1617 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1618 int size;
e81cd2d6 1619
447ced07 1620 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1621 allmulti = 1;
1622 mc_count = 0;
1623 }
e81cd2d6
LB		 1624
1625 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1626
e81cd2d6 1627 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1628 if (cmd == NULL)
e81cd2d6 1629 return NULL;
a66098da
LB		 1630
1631 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1632 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1633 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1634 MWL8K_ENABLE_RX_BROADCAST);
1635
1636 if (allmulti) {
1637 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1638 } else if (mc_count) {
1639 int i;
1640
1641 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1642 cmd->numaddr = cpu_to_le16(mc_count);
1643 for (i = 0; i < mc_count && mclist; i++) {
1644 if (mclist->da_addrlen != ETH_ALEN) {
1645 kfree(cmd);
1646 return NULL;
1647 }
1648 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1649 mclist = mclist->next;
a66098da 1650 }
a66098da
LB		 1651 }
1652
e81cd2d6 1653 return &cmd->header;
a66098da
LB		 1654}
1655
1656/*
1657 * CMD_802_11_GET_STAT.
1658 */
1659struct mwl8k_cmd_802_11_get_stat {
1660 struct mwl8k_cmd_pkt header;
a66098da
LB		 1661 __le32 stats[64];
1662} __attribute__((packed));
1663
1664#define MWL8K_STAT_ACK_FAILURE 9
1665#define MWL8K_STAT_RTS_FAILURE 12
1666#define MWL8K_STAT_FCS_ERROR 24
1667#define MWL8K_STAT_RTS_SUCCESS 11
1668
1669static int mwl8k_cmd_802_11_get_stat(struct ieee80211_hw *hw,
1670 struct ieee80211_low_level_stats *stats)
1671{
1672 struct mwl8k_cmd_802_11_get_stat *cmd;
1673 int rc;
1674
1675 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1676 if (cmd == NULL)
1677 return -ENOMEM;
1678
1679 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1680 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1681
1682 rc = mwl8k_post_cmd(hw, &cmd->header);
1683 if (!rc) {
1684 stats->dot11ACKFailureCount =
1685 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1686 stats->dot11RTSFailureCount =
1687 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1688 stats->dot11FCSErrorCount =
1689 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1690 stats->dot11RTSSuccessCount =
1691 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1692 }
1693 kfree(cmd);
1694
1695 return rc;
1696}
1697
1698/*
1699 * CMD_802_11_RADIO_CONTROL.
1700 */
1701struct mwl8k_cmd_802_11_radio_control {
1702 struct mwl8k_cmd_pkt header;
1703 __le16 action;
1704 __le16 control;
1705 __le16 radio_on;
1706} __attribute__((packed));
1707
c46563b7
LB		 1708static int
1709mwl8k_cmd_802_11_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1710{
1711 struct mwl8k_priv *priv = hw->priv;
1712 struct mwl8k_cmd_802_11_radio_control *cmd;
1713 int rc;
1714
c46563b7 1715 if (enable == priv->radio_on && !force)
a66098da
LB		 1716 return 0;
1717
a66098da
LB		 1718 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1719 if (cmd == NULL)
1720 return -ENOMEM;
1721
1722 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1723 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1724 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1725 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 1726 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1727
1728 rc = mwl8k_post_cmd(hw, &cmd->header);
1729 kfree(cmd);
1730
1731 if (!rc)
c46563b7 1732 priv->radio_on = enable;
a66098da
LB		 1733
1734 return rc;
1735}
1736
c46563b7
LB		 1737static int mwl8k_cmd_802_11_radio_disable(struct ieee80211_hw *hw)
1738{
1739 return mwl8k_cmd_802_11_radio_control(hw, 0, 0);
1740}
1741
1742static int mwl8k_cmd_802_11_radio_enable(struct ieee80211_hw *hw)
1743{
1744 return mwl8k_cmd_802_11_radio_control(hw, 1, 0);
1745}
1746
a66098da
LB		 1747static int
1748mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1749{
1750 struct mwl8k_priv *priv;
1751
1752 if (hw == NULL || hw->priv == NULL)
1753 return -EINVAL;
1754 priv = hw->priv;
1755
68ce3884 1756 priv->radio_short_preamble = short_preamble;
a66098da 1757
c46563b7 1758 return mwl8k_cmd_802_11_radio_control(hw, 1, 1);
a66098da
LB		 1759}
1760
1761/*
1762 * CMD_802_11_RF_TX_POWER.
1763 */
1764#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1765
1766struct mwl8k_cmd_802_11_rf_tx_power {
1767 struct mwl8k_cmd_pkt header;
1768 __le16 action;
1769 __le16 support_level;
1770 __le16 current_level;
1771 __le16 reserved;
1772 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1773} __attribute__((packed));
1774
1775static int mwl8k_cmd_802_11_rf_tx_power(struct ieee80211_hw *hw, int dBm)
1776{
1777 struct mwl8k_cmd_802_11_rf_tx_power *cmd;
1778 int rc;
1779
1780 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1781 if (cmd == NULL)
1782 return -ENOMEM;
1783
1784 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1785 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1786 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1787 cmd->support_level = cpu_to_le16(dBm);
1788
1789 rc = mwl8k_post_cmd(hw, &cmd->header);
1790 kfree(cmd);
1791
1792 return rc;
1793}
1794
1795/*
1796 * CMD_SET_PRE_SCAN.
1797 */
1798struct mwl8k_cmd_set_pre_scan {
1799 struct mwl8k_cmd_pkt header;
1800} __attribute__((packed));
1801
1802static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
1803{
1804 struct mwl8k_cmd_set_pre_scan *cmd;
1805 int rc;
1806
1807 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1808 if (cmd == NULL)
1809 return -ENOMEM;
1810
1811 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
1812 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1813
1814 rc = mwl8k_post_cmd(hw, &cmd->header);
1815 kfree(cmd);
1816
1817 return rc;
1818}
1819
1820/*
1821 * CMD_SET_POST_SCAN.
1822 */
1823struct mwl8k_cmd_set_post_scan {
1824 struct mwl8k_cmd_pkt header;
1825 __le32 isibss;
d89173f2 1826 __u8 bssid[ETH_ALEN];
a66098da
LB		 1827} __attribute__((packed));
1828
1829static int
ce9e2e1b 1830mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, __u8 *mac)
a66098da
LB		 1831{
1832 struct mwl8k_cmd_set_post_scan *cmd;
1833 int rc;
1834
1835 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1836 if (cmd == NULL)
1837 return -ENOMEM;
1838
1839 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
1840 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1841 cmd->isibss = 0;
d89173f2 1842 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 1843
1844 rc = mwl8k_post_cmd(hw, &cmd->header);
1845 kfree(cmd);
1846
1847 return rc;
1848}
1849
1850/*
1851 * CMD_SET_RF_CHANNEL.
1852 */
1853struct mwl8k_cmd_set_rf_channel {
1854 struct mwl8k_cmd_pkt header;
1855 __le16 action;
1856 __u8 current_channel;
1857 __le32 channel_flags;
1858} __attribute__((packed));
1859
1860static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
1861 struct ieee80211_channel *channel)
1862{
1863 struct mwl8k_cmd_set_rf_channel *cmd;
1864 int rc;
1865
1866 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1867 if (cmd == NULL)
1868 return -ENOMEM;
1869
1870 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
1871 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1872 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1873 cmd->current_channel = channel->hw_value;
1874 if (channel->band == IEEE80211_BAND_2GHZ)
1875 cmd->channel_flags = cpu_to_le32(0x00000081);
1876 else
1877 cmd->channel_flags = cpu_to_le32(0x00000000);
1878
1879 rc = mwl8k_post_cmd(hw, &cmd->header);
1880 kfree(cmd);
1881
1882 return rc;
1883}
1884
1885/*
1886 * CMD_SET_SLOT.
1887 */
1888struct mwl8k_cmd_set_slot {
1889 struct mwl8k_cmd_pkt header;
1890 __le16 action;
1891 __u8 short_slot;
1892} __attribute__((packed));
1893
5539bb51 1894static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da
LB		 1895{
1896 struct mwl8k_cmd_set_slot *cmd;
1897 int rc;
1898
1899 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1900 if (cmd == NULL)
1901 return -ENOMEM;
1902
1903 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
1904 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1905 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
5539bb51 1906 cmd->short_slot = short_slot_time;
a66098da
LB		 1907
1908 rc = mwl8k_post_cmd(hw, &cmd->header);
1909 kfree(cmd);
1910
1911 return rc;
1912}
1913
1914/*
1915 * CMD_MIMO_CONFIG.
1916 */
1917struct mwl8k_cmd_mimo_config {
1918 struct mwl8k_cmd_pkt header;
1919 __le32 action;
1920 __u8 rx_antenna_map;
1921 __u8 tx_antenna_map;
1922} __attribute__((packed));
1923
1924static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
1925{
1926 struct mwl8k_cmd_mimo_config *cmd;
1927 int rc;
1928
1929 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1930 if (cmd == NULL)
1931 return -ENOMEM;
1932
1933 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
1934 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1935 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
1936 cmd->rx_antenna_map = rx;
1937 cmd->tx_antenna_map = tx;
1938
1939 rc = mwl8k_post_cmd(hw, &cmd->header);
1940 kfree(cmd);
1941
1942 return rc;
1943}
1944
1945/*
1946 * CMD_ENABLE_SNIFFER.
1947 */
1948struct mwl8k_cmd_enable_sniffer {
1949 struct mwl8k_cmd_pkt header;
1950 __le32 action;
1951} __attribute__((packed));
1952
1953static int mwl8k_enable_sniffer(struct ieee80211_hw *hw, bool enable)
1954{
1955 struct mwl8k_cmd_enable_sniffer *cmd;
1956 int rc;
1957
1958 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1959 if (cmd == NULL)
1960 return -ENOMEM;
1961
1962 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
1963 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 1964 cmd->action = cpu_to_le32(!!enable);
a66098da
LB		 1965
1966 rc = mwl8k_post_cmd(hw, &cmd->header);
1967 kfree(cmd);
1968
1969 return rc;
1970}
1971
32060e1b
LB		 1972/*
1973 * CMD_SET_MAC_ADDR.
1974 */
1975struct mwl8k_cmd_set_mac_addr {
1976 struct mwl8k_cmd_pkt header;
1977 __u8 mac_addr[ETH_ALEN];
1978} __attribute__((packed));
1979
1980static int mwl8k_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
1981{
1982 struct mwl8k_cmd_set_mac_addr *cmd;
1983 int rc;
1984
1985 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1986 if (cmd == NULL)
1987 return -ENOMEM;
1988
1989 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
1990 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1991 memcpy(cmd->mac_addr, mac, ETH_ALEN);
1992
1993 rc = mwl8k_post_cmd(hw, &cmd->header);
1994 kfree(cmd);
1995
1996 return rc;
1997}
1998
1999
a66098da 2000/*
ce9e2e1b 2001 * CMD_SET_RATEADAPT_MODE.
a66098da
LB		 2002 */
2003struct mwl8k_cmd_set_rate_adapt_mode {
2004 struct mwl8k_cmd_pkt header;
2005 __le16 action;
2006 __le16 mode;
2007} __attribute__((packed));
2008
2009static int mwl8k_cmd_setrateadaptmode(struct ieee80211_hw *hw, __u16 mode)
2010{
2011 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2012 int rc;
2013
2014 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2015 if (cmd == NULL)
2016 return -ENOMEM;
2017
2018 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2019 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2020 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2021 cmd->mode = cpu_to_le16(mode);
2022
2023 rc = mwl8k_post_cmd(hw, &cmd->header);
2024 kfree(cmd);
2025
2026 return rc;
2027}
2028
2029/*
2030 * CMD_SET_WMM_MODE.
2031 */
2032struct mwl8k_cmd_set_wmm {
2033 struct mwl8k_cmd_pkt header;
2034 __le16 action;
2035} __attribute__((packed));
2036
2037static int mwl8k_set_wmm(struct ieee80211_hw *hw, bool enable)
2038{
2039 struct mwl8k_priv *priv = hw->priv;
2040 struct mwl8k_cmd_set_wmm *cmd;
2041 int rc;
2042
2043 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2044 if (cmd == NULL)
2045 return -ENOMEM;
2046
2047 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
2048 cmd->header.length = cpu_to_le16(sizeof(*cmd));
0439b1f5 2049 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2050
2051 rc = mwl8k_post_cmd(hw, &cmd->header);
2052 kfree(cmd);
2053
2054 if (!rc)
0439b1f5 2055 priv->wmm_enabled = enable;
a66098da
LB		 2056
2057 return rc;
2058}
2059
2060/*
2061 * CMD_SET_RTS_THRESHOLD.
2062 */
2063struct mwl8k_cmd_rts_threshold {
2064 struct mwl8k_cmd_pkt header;
2065 __le16 action;
2066 __le16 threshold;
2067} __attribute__((packed));
2068
2069static int mwl8k_rts_threshold(struct ieee80211_hw *hw,
733d3067 2070 u16 action, u16 threshold)
a66098da
LB		 2071{
2072 struct mwl8k_cmd_rts_threshold *cmd;
2073 int rc;
2074
2075 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2076 if (cmd == NULL)
2077 return -ENOMEM;
2078
2079 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
2080 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2081 cmd->action = cpu_to_le16(action);
733d3067 2082 cmd->threshold = cpu_to_le16(threshold);
a66098da
LB		 2083
2084 rc = mwl8k_post_cmd(hw, &cmd->header);
2085 kfree(cmd);
2086
2087 return rc;
2088}
2089
2090/*
2091 * CMD_SET_EDCA_PARAMS.
2092 */
2093struct mwl8k_cmd_set_edca_params {
2094 struct mwl8k_cmd_pkt header;
2095
2096 /* See MWL8K_SET_EDCA_XXX below */
2097 __le16 action;
2098
2099 /* TX opportunity in units of 32 us */
2100 __le16 txop;
2101
2102 /* Log exponent of max contention period: 0...15*/
2103 __u8 log_cw_max;
2104
2105 /* Log exponent of min contention period: 0...15 */
2106 __u8 log_cw_min;
2107
2108 /* Adaptive interframe spacing in units of 32us */
2109 __u8 aifs;
2110
2111 /* TX queue to configure */
2112 __u8 txq;
2113} __attribute__((packed));
2114
a66098da
LB		 2115#define MWL8K_SET_EDCA_CW 0x01
2116#define MWL8K_SET_EDCA_TXOP 0x02
2117#define MWL8K_SET_EDCA_AIFS 0x04
2118
2119#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2120 MWL8K_SET_EDCA_TXOP | \
2121 MWL8K_SET_EDCA_AIFS)
2122
2123static int
2124mwl8k_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2125 __u16 cw_min, __u16 cw_max,
2126 __u8 aifs, __u16 txop)
2127{
2128 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2129 int rc;
2130
2131 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2132 if (cmd == NULL)
2133 return -ENOMEM;
2134
22995b24
LB		 2135 /*
2136 * Queues 0 (BE) and 1 (BK) are swapped in hardware for
2137 * this call.
2138 */
2139 qnum ^= !(qnum >> 1);
2140
a66098da
LB		 2141 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2142 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2143 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2144 cmd->txop = cpu_to_le16(txop);
ce9e2e1b
LB		 2145 cmd->log_cw_max = (u8)ilog2(cw_max + 1);
2146 cmd->log_cw_min = (u8)ilog2(cw_min + 1);
a66098da
LB		 2147 cmd->aifs = aifs;
2148 cmd->txq = qnum;
2149
2150 rc = mwl8k_post_cmd(hw, &cmd->header);
2151 kfree(cmd);
2152
2153 return rc;
2154}
2155
2156/*
2157 * CMD_FINALIZE_JOIN.
2158 */
2159
2160/* FJ beacon buffer size is compiled into the firmware. */
2161#define MWL8K_FJ_BEACON_MAXLEN 128
2162
2163struct mwl8k_cmd_finalize_join {
2164 struct mwl8k_cmd_pkt header;
2165 __le32 sleep_interval; /* Number of beacon periods to sleep */
2166 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
2167} __attribute__((packed));
2168
2169static int mwl8k_finalize_join(struct ieee80211_hw *hw, void *frame,
2170 __u16 framelen, __u16 dtim)
2171{
2172 struct mwl8k_cmd_finalize_join *cmd;
2173 struct ieee80211_mgmt *payload = frame;
2174 u16 hdrlen;
2175 u32 payload_len;
2176 int rc;
2177
2178 if (frame == NULL)
2179 return -EINVAL;
2180
2181 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2182 if (cmd == NULL)
2183 return -ENOMEM;
2184
2185 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
2186 cmd->header.length = cpu_to_le16(sizeof(*cmd));
ce9e2e1b 2187 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
a66098da
LB		 2188
2189 hdrlen = ieee80211_hdrlen(payload->frame_control);
2190
2191 payload_len = framelen > hdrlen ? framelen - hdrlen : 0;
2192
2193 /* XXX TBD Might just have to abort and return an error */
2194 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2195 printk(KERN_ERR "%s(): WARNING: Incomplete beacon "
c2c357ce
LB		 2196 "sent to firmware. Sz=%u MAX=%u\n", __func__,
2197 payload_len, MWL8K_FJ_BEACON_MAXLEN);
a66098da 2198
ce9e2e1b
LB		 2199 if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2200 payload_len = MWL8K_FJ_BEACON_MAXLEN;
a66098da
LB		 2201
2202 if (payload && payload_len)
2203 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
2204
2205 rc = mwl8k_post_cmd(hw, &cmd->header);
2206 kfree(cmd);
2207 return rc;
2208}
2209
2210/*
2211 * CMD_UPDATE_STADB.
2212 */
2213struct mwl8k_cmd_update_sta_db {
2214 struct mwl8k_cmd_pkt header;
2215
2216 /* See STADB_ACTION_TYPE */
2217 __le32 action;
2218
2219 /* Peer MAC address */
d89173f2 2220 __u8 peer_addr[ETH_ALEN];
a66098da
LB		 2221
2222 __le32 reserved;
2223
2224 /* Peer info - valid during add/update. */
2225 struct peer_capability_info peer_info;
2226} __attribute__((packed));
2227
2228static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
2229 struct ieee80211_vif *vif, __u32 action)
2230{
2231 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2232 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2233 struct mwl8k_cmd_update_sta_db *cmd;
2234 struct peer_capability_info *peer_info;
2235 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
a66098da
LB		 2236 int rc;
2237 __u8 count, *rates;
2238
2239 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2240 if (cmd == NULL)
2241 return -ENOMEM;
2242
2243 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2244 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2245
2246 cmd->action = cpu_to_le32(action);
2247 peer_info = &cmd->peer_info;
d89173f2 2248 memcpy(cmd->peer_addr, mv_vif->bssid, ETH_ALEN);
a66098da
LB		 2249
2250 switch (action) {
2251 case MWL8K_STA_DB_ADD_ENTRY:
2252 case MWL8K_STA_DB_MODIFY_ENTRY:
2253 /* Build peer_info block */
2254 peer_info->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2255 peer_info->basic_caps = cpu_to_le16(info->assoc_capability);
2256 peer_info->interop = 1;
2257 peer_info->amsdu_enabled = 0;
2258
2259 rates = peer_info->legacy_rates;
ce9e2e1b 2260 for (count = 0; count < mv_vif->legacy_nrates; count++)
a66098da
LB		 2261 rates[count] = bitrates[count].hw_value;
2262
2263 rc = mwl8k_post_cmd(hw, &cmd->header);
2264 if (rc == 0)
2265 mv_vif->peer_id = peer_info->station_id;
2266
2267 break;
2268
2269 case MWL8K_STA_DB_DEL_ENTRY:
2270 case MWL8K_STA_DB_FLUSH:
2271 default:
2272 rc = mwl8k_post_cmd(hw, &cmd->header);
2273 if (rc == 0)
2274 mv_vif->peer_id = 0;
2275 break;
2276 }
2277 kfree(cmd);
2278
2279 return rc;
2280}
2281
2282/*
2283 * CMD_SET_AID.
2284 */
a66098da
LB		 2285#define MWL8K_RATE_INDEX_MAX_ARRAY 14
2286
2287#define MWL8K_FRAME_PROT_DISABLED 0x00
2288#define MWL8K_FRAME_PROT_11G 0x07
2289#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2290#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da
LB		 2291
2292struct mwl8k_cmd_update_set_aid {
2293 struct mwl8k_cmd_pkt header;
2294 __le16 aid;
2295
2296 /* AP's MAC address (BSSID) */
d89173f2 2297 __u8 bssid[ETH_ALEN];
a66098da
LB		 2298 __le16 protection_mode;
2299 __u8 supp_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2300} __attribute__((packed));
2301
2302static int mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2303 struct ieee80211_vif *vif)
2304{
2305 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2306 struct ieee80211_bss_conf *info = &mv_vif->bss_info;
2307 struct mwl8k_cmd_update_set_aid *cmd;
2308 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2309 int count;
2310 u16 prot_mode;
2311 int rc;
2312
2313 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2314 if (cmd == NULL)
2315 return -ENOMEM;
2316
2317 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
2318 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2319 cmd->aid = cpu_to_le16(info->aid);
2320
d89173f2 2321 memcpy(cmd->bssid, mv_vif->bssid, ETH_ALEN);
a66098da 2322
a66098da
LB		 2323 if (info->use_cts_prot) {
2324 prot_mode = MWL8K_FRAME_PROT_11G;
2325 } else {
9ed6bcce 2326 switch (info->ht_operation_mode &
a66098da
LB		 2327 IEEE80211_HT_OP_MODE_PROTECTION) {
2328 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2329 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2330 break;
2331 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2332 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2333 break;
2334 default:
2335 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2336 break;
2337 }
2338 }
a66098da
LB		 2339 cmd->protection_mode = cpu_to_le16(prot_mode);
2340
2341 for (count = 0; count < mv_vif->legacy_nrates; count++)
2342 cmd->supp_rates[count] = bitrates[count].hw_value;
2343
2344 rc = mwl8k_post_cmd(hw, &cmd->header);
2345 kfree(cmd);
2346
2347 return rc;
2348}
2349
2350/*
2351 * CMD_SET_RATE.
2352 */
2353struct mwl8k_cmd_update_rateset {
2354 struct mwl8k_cmd_pkt header;
2355 __u8 legacy_rates[MWL8K_RATE_INDEX_MAX_ARRAY];
2356
2357 /* Bitmap for supported MCS codes. */
2358 __u8 mcs_set[MWL8K_IEEE_LEGACY_DATA_RATES];
2359 __u8 reserved[MWL8K_IEEE_LEGACY_DATA_RATES];
2360} __attribute__((packed));
2361
2362static int mwl8k_update_rateset(struct ieee80211_hw *hw,
2363 struct ieee80211_vif *vif)
2364{
2365 struct mwl8k_vif *mv_vif = MWL8K_VIF(vif);
2366 struct mwl8k_cmd_update_rateset *cmd;
2367 struct ieee80211_rate *bitrates = mv_vif->legacy_rates;
2368 int count;
2369 int rc;
2370
2371 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2372 if (cmd == NULL)
2373 return -ENOMEM;
2374
2375 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
2376 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2377
2378 for (count = 0; count < mv_vif->legacy_nrates; count++)
2379 cmd->legacy_rates[count] = bitrates[count].hw_value;
2380
2381 rc = mwl8k_post_cmd(hw, &cmd->header);
2382 kfree(cmd);
2383
2384 return rc;
2385}
2386
2387/*
2388 * CMD_USE_FIXED_RATE.
2389 */
2390#define MWL8K_RATE_TABLE_SIZE 8
2391#define MWL8K_UCAST_RATE 0
a66098da
LB		 2392#define MWL8K_USE_AUTO_RATE 0x0002
2393
2394struct mwl8k_rate_entry {
2395 /* Set to 1 if HT rate, 0 if legacy. */
2396 __le32 is_ht_rate;
2397
2398 /* Set to 1 to use retry_count field. */
2399 __le32 enable_retry;
2400
2401 /* Specified legacy rate or MCS. */
2402 __le32 rate;
2403
2404 /* Number of allowed retries. */
2405 __le32 retry_count;
2406} __attribute__((packed));
2407
2408struct mwl8k_rate_table {
2409 /* 1 to allow specified rate and below */
2410 __le32 allow_rate_drop;
2411 __le32 num_rates;
2412 struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE];
2413} __attribute__((packed));
2414
2415struct mwl8k_cmd_use_fixed_rate {
2416 struct mwl8k_cmd_pkt header;
2417 __le32 action;
2418 struct mwl8k_rate_table rate_table;
2419
2420 /* Unicast, Broadcast or Multicast */
2421 __le32 rate_type;
2422 __le32 reserved1;
2423 __le32 reserved2;
2424} __attribute__((packed));
2425
2426static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw,
2427 u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table)
2428{
2429 struct mwl8k_cmd_use_fixed_rate *cmd;
2430 int count;
2431 int rc;
2432
2433 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2434 if (cmd == NULL)
2435 return -ENOMEM;
2436
2437 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2438 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2439
2440 cmd->action = cpu_to_le32(action);
2441 cmd->rate_type = cpu_to_le32(rate_type);
2442
2443 if (rate_table != NULL) {
c2c357ce
LB		 2444 /*
2445 * Copy over each field manually so that endian
2446 * conversion can be done.
2447 */
a66098da
LB		 2448 cmd->rate_table.allow_rate_drop =
2449 cpu_to_le32(rate_table->allow_rate_drop);
2450 cmd->rate_table.num_rates =
2451 cpu_to_le32(rate_table->num_rates);
2452
2453 for (count = 0; count < rate_table->num_rates; count++) {
2454 struct mwl8k_rate_entry *dst =
2455 &cmd->rate_table.rate_entry[count];
2456 struct mwl8k_rate_entry *src =
2457 &rate_table->rate_entry[count];
2458
2459 dst->is_ht_rate = cpu_to_le32(src->is_ht_rate);
2460 dst->enable_retry = cpu_to_le32(src->enable_retry);
2461 dst->rate = cpu_to_le32(src->rate);
2462 dst->retry_count = cpu_to_le32(src->retry_count);
2463 }
2464 }
2465
2466 rc = mwl8k_post_cmd(hw, &cmd->header);
2467 kfree(cmd);
2468
2469 return rc;
2470}
2471
2472
2473/*
2474 * Interrupt handling.
2475 */
2476static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2477{
2478 struct ieee80211_hw *hw = dev_id;
2479 struct mwl8k_priv *priv = hw->priv;
2480 u32 status;
2481
2482 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2483 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2484
a66098da
LB		 2485 if (!status)
2486 return IRQ_NONE;
2487
2488 if (status & MWL8K_A2H_INT_TX_DONE)
2489 tasklet_schedule(&priv->tx_reclaim_task);
2490
2491 if (status & MWL8K_A2H_INT_RX_READY) {
2492 while (rxq_process(hw, 0, 1))
2493 rxq_refill(hw, 0, 1);
2494 }
2495
2496 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2497 if (priv->hostcmd_wait != NULL)
a66098da 2498 complete(priv->hostcmd_wait);
a66098da
LB		 2499 }
2500
2501 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2502 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2503 priv->radio_on && priv->pending_tx_pkts)
618952a7 2504 mwl8k_tx_start(priv);
a66098da
LB		 2505 }
2506
2507 return IRQ_HANDLED;
2508}
2509
2510
2511/*
2512 * Core driver operations.
2513 */
2514static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2515{
2516 struct mwl8k_priv *priv = hw->priv;
2517 int index = skb_get_queue_mapping(skb);
2518 int rc;
2519
2520 if (priv->current_channel == NULL) {
2521 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 2522 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 2523 dev_kfree_skb(skb);
2524 return NETDEV_TX_OK;
2525 }
2526
2527 rc = mwl8k_txq_xmit(hw, index, skb);
2528
2529 return rc;
2530}
2531
a66098da
LB		 2532static int mwl8k_start(struct ieee80211_hw *hw)
2533{
a66098da
LB		 2534 struct mwl8k_priv *priv = hw->priv;
2535 int rc;
2536
a66098da
LB		 2537 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
2538 IRQF_SHARED, MWL8K_NAME, hw);
2539 if (rc) {
2540 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 2541 wiphy_name(hw->wiphy));
2ec610cb 2542 return -EIO;
a66098da
LB		 2543 }
2544
2ec610cb
LB		 2545 /* Enable tx reclaim tasklet */
2546 tasklet_enable(&priv->tx_reclaim_task);
2547
a66098da 2548 /* Enable interrupts */
c23b5a69 2549 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 2550
2ec610cb
LB		 2551 rc = mwl8k_fw_lock(hw);
2552 if (!rc) {
2553 rc = mwl8k_cmd_802_11_radio_enable(hw);
a66098da 2554
2ec610cb
LB		 2555 if (!rc)
2556 rc = mwl8k_cmd_set_pre_scan(hw);
a66098da 2557
2ec610cb
LB		 2558 if (!rc)
2559 rc = mwl8k_cmd_set_post_scan(hw,
2560 "\x00\x00\x00\x00\x00\x00");
2561
2562 if (!rc)
2563 rc = mwl8k_cmd_setrateadaptmode(hw, 0);
a66098da 2564
2ec610cb
LB		 2565 if (!rc)
2566 rc = mwl8k_set_wmm(hw, 0);
a66098da 2567
2ec610cb
LB		 2568 if (!rc)
2569 rc = mwl8k_enable_sniffer(hw, 0);
a66098da 2570
2ec610cb
LB		 2571 mwl8k_fw_unlock(hw);
2572 }
2573
2574 if (rc) {
2575 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
2576 free_irq(priv->pdev->irq, hw);
2577 tasklet_disable(&priv->tx_reclaim_task);
2578 }
a66098da
LB		 2579
2580 return rc;
2581}
2582
a66098da
LB		 2583static void mwl8k_stop(struct ieee80211_hw *hw)
2584{
a66098da
LB		 2585 struct mwl8k_priv *priv = hw->priv;
2586 int i;
2587
d3cea0b8 2588 mwl8k_cmd_802_11_radio_disable(hw);
a66098da
LB		 2589
2590 ieee80211_stop_queues(hw);
2591
a66098da 2592 /* Disable interrupts */
a66098da 2593 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 2594 free_irq(priv->pdev->irq, hw);
2595
2596 /* Stop finalize join worker */
2597 cancel_work_sync(&priv->finalize_join_worker);
2598 if (priv->beacon_skb != NULL)
2599 dev_kfree_skb(priv->beacon_skb);
2600
2601 /* Stop tx reclaim tasklet */
2602 tasklet_disable(&priv->tx_reclaim_task);
2603
a66098da
LB		 2604 /* Return all skbs to mac80211 */
2605 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2606 mwl8k_txq_reclaim(hw, i, 1);
2607}
2608
2609static int mwl8k_add_interface(struct ieee80211_hw *hw,
2610 struct ieee80211_if_init_conf *conf)
2611{
2612 struct mwl8k_priv *priv = hw->priv;
2613 struct mwl8k_vif *mwl8k_vif;
2614
2615 /*
2616 * We only support one active interface at a time.
2617 */
2618 if (priv->vif != NULL)
2619 return -EBUSY;
2620
2621 /*
2622 * We only support managed interfaces for now.
2623 */
240e86ef 2624 if (conf->type != NL80211_IFTYPE_STATION)
a66098da
LB		 2625 return -EINVAL;
2626
a43c49a8
LB		 2627 /*
2628 * Reject interface creation if sniffer mode is active, as
2629 * STA operation is mutually exclusive with hardware sniffer
2630 * mode.
2631 */
2632 if (priv->sniffer_enabled) {
2633 printk(KERN_INFO "%s: unable to create STA "
2634 "interface due to sniffer mode being enabled\n",
2635 wiphy_name(hw->wiphy));
2636 return -EINVAL;
2637 }
2638
a66098da
LB		 2639 /* Clean out driver private area */
2640 mwl8k_vif = MWL8K_VIF(conf->vif);
2641 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
2642
32060e1b
LB		 2643 /* Set and save the mac address */
2644 mwl8k_set_mac_addr(hw, conf->mac_addr);
d89173f2 2645 memcpy(mwl8k_vif->mac_addr, conf->mac_addr, ETH_ALEN);
a66098da
LB		 2646
2647 /* Back pointer to parent config block */
2648 mwl8k_vif->priv = priv;
2649
2650 /* Setup initial PHY parameters */
ce9e2e1b 2651 memcpy(mwl8k_vif->legacy_rates,
a66098da
LB		 2652 priv->rates, sizeof(mwl8k_vif->legacy_rates));
2653 mwl8k_vif->legacy_nrates = ARRAY_SIZE(priv->rates);
2654
2655 /* Set Initial sequence number to zero */
2656 mwl8k_vif->seqno = 0;
2657
2658 priv->vif = conf->vif;
2659 priv->current_channel = NULL;
2660
2661 return 0;
2662}
2663
2664static void mwl8k_remove_interface(struct ieee80211_hw *hw,
2665 struct ieee80211_if_init_conf *conf)
2666{
2667 struct mwl8k_priv *priv = hw->priv;
2668
2669 if (priv->vif == NULL)
2670 return;
2671
32060e1b
LB		 2672 mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
2673
a66098da
LB		 2674 priv->vif = NULL;
2675}
2676
ee03a932 2677static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 2678{
a66098da
LB		 2679 struct ieee80211_conf *conf = &hw->conf;
2680 struct mwl8k_priv *priv = hw->priv;
ee03a932 2681 int rc;
a66098da 2682
7595d67a
LB		 2683 if (conf->flags & IEEE80211_CONF_IDLE) {
2684 mwl8k_cmd_802_11_radio_disable(hw);
2685 priv->current_channel = NULL;
ee03a932 2686 return 0;
7595d67a
LB		 2687 }
2688
ee03a932
LB		 2689 rc = mwl8k_fw_lock(hw);
2690 if (rc)
2691 return rc;
a66098da 2692
ee03a932
LB		 2693 rc = mwl8k_cmd_802_11_radio_enable(hw);
2694 if (rc)
2695 goto out;
a66098da 2696
ee03a932
LB		 2697 rc = mwl8k_cmd_set_rf_channel(hw, conf->channel);
2698 if (rc)
2699 goto out;
2700
2701 priv->current_channel = conf->channel;
a66098da
LB		 2702
2703 if (conf->power_level > 18)
2704 conf->power_level = 18;
ee03a932
LB		 2705 rc = mwl8k_cmd_802_11_rf_tx_power(hw, conf->power_level);
2706 if (rc)
2707 goto out;
a66098da
LB		 2708
2709 if (mwl8k_cmd_mimo_config(hw, 0x7, 0x7))
2710 rc = -EINVAL;
2711
ee03a932
LB		 2712out:
2713 mwl8k_fw_unlock(hw);
a66098da 2714
ee03a932 2715 return rc;
a66098da
LB		 2716}
2717
3a980d0a
LB		 2718static void mwl8k_bss_info_changed(struct ieee80211_hw *hw,
2719 struct ieee80211_vif *vif,
2720 struct ieee80211_bss_conf *info,
2721 u32 changed)
a66098da 2722{
a66098da
LB		 2723 struct mwl8k_priv *priv = hw->priv;
2724 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
3a980d0a
LB		 2725 int rc;
2726
2727 if (changed & BSS_CHANGED_BSSID)
2728 memcpy(mwl8k_vif->bssid, info->bssid, ETH_ALEN);
2729
2730 if ((changed & BSS_CHANGED_ASSOC) == 0)
2731 return;
a66098da 2732
a66098da
LB		 2733 priv->capture_beacon = false;
2734
3a980d0a 2735 rc = mwl8k_fw_lock(hw);
942457d6 2736 if (rc)
3a980d0a
LB		 2737 return;
2738
a66098da
LB		 2739 if (info->assoc) {
2740 memcpy(&mwl8k_vif->bss_info, info,
2741 sizeof(struct ieee80211_bss_conf));
2742
2743 /* Install rates */
3a980d0a
LB		 2744 rc = mwl8k_update_rateset(hw, vif);
2745 if (rc)
2746 goto out;
a66098da
LB		 2747
2748 /* Turn on rate adaptation */
3a980d0a
LB		 2749 rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE,
2750 MWL8K_UCAST_RATE, NULL);
2751 if (rc)
2752 goto out;
a66098da
LB		 2753
2754 /* Set radio preamble */
3a980d0a
LB		 2755 rc = mwl8k_set_radio_preamble(hw, info->use_short_preamble);
2756 if (rc)
2757 goto out;
a66098da
LB		 2758
2759 /* Set slot time */
3a980d0a
LB		 2760 rc = mwl8k_cmd_set_slot(hw, info->use_short_slot);
2761 if (rc)
2762 goto out;
a66098da
LB		 2763
2764 /* Update peer rate info */
3a980d0a
LB		 2765 rc = mwl8k_cmd_update_sta_db(hw, vif,
2766 MWL8K_STA_DB_MODIFY_ENTRY);
2767 if (rc)
2768 goto out;
a66098da
LB		 2769
2770 /* Set AID */
3a980d0a
LB		 2771 rc = mwl8k_cmd_set_aid(hw, vif);
2772 if (rc)
2773 goto out;
a66098da
LB		 2774
2775 /*
2776 * Finalize the join. Tell rx handler to process
2777 * next beacon from our BSSID.
2778 */
d89173f2 2779 memcpy(priv->capture_bssid, mwl8k_vif->bssid, ETH_ALEN);
a66098da
LB		 2780 priv->capture_beacon = true;
2781 } else {
3a980d0a 2782 rc = mwl8k_cmd_update_sta_db(hw, vif, MWL8K_STA_DB_DEL_ENTRY);
a66098da
LB		 2783 memset(&mwl8k_vif->bss_info, 0,
2784 sizeof(struct ieee80211_bss_conf));
d89173f2 2785 memset(mwl8k_vif->bssid, 0, ETH_ALEN);
a66098da
LB		 2786 }
2787
3a980d0a
LB		 2788out:
2789 mwl8k_fw_unlock(hw);
a66098da
LB		 2790}
2791
e81cd2d6
LB		 2792static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
2793 int mc_count, struct dev_addr_list *mclist)
2794{
2795 struct mwl8k_cmd_pkt *cmd;
2796
447ced07
LB		 2797 /*
2798 * Synthesize and return a command packet that programs the
2799 * hardware multicast address filter. At this point we don't
2800 * know whether FIF_ALLMULTI is being requested, but if it is,
2801 * we'll end up throwing this packet away and creating a new
2802 * one in mwl8k_configure_filter().
2803 */
2804 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 2805
2806 return (unsigned long)cmd;
2807}
2808
a43c49a8
LB		 2809static int
2810mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
2811 unsigned int changed_flags,
2812 unsigned int *total_flags)
2813{
2814 struct mwl8k_priv *priv = hw->priv;
2815
2816 /*
2817 * Hardware sniffer mode is mutually exclusive with STA
2818 * operation, so refuse to enable sniffer mode if a STA
2819 * interface is active.
2820 */
2821 if (priv->vif != NULL) {
2822 if (net_ratelimit())
2823 printk(KERN_INFO "%s: not enabling sniffer "
2824 "mode because STA interface is active\n",
2825 wiphy_name(hw->wiphy));
2826 return 0;
2827 }
2828
2829 if (!priv->sniffer_enabled) {
2830 if (mwl8k_enable_sniffer(hw, 1))
2831 return 0;
2832 priv->sniffer_enabled = true;
2833 }
2834
2835 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
2836 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
2837 FIF_OTHER_BSS;
2838
2839 return 1;
2840}
2841
e6935ea1
LB		 2842static void mwl8k_configure_filter(struct ieee80211_hw *hw,
2843 unsigned int changed_flags,
2844 unsigned int *total_flags,
2845 u64 multicast)
2846{
2847 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 2848 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
2849
2850 /*
2851 * Enable hardware sniffer mode if FIF_CONTROL or
2852 * FIF_OTHER_BSS is requested.
2853 */
2854 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
2855 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
2856 kfree(cmd);
2857 return;
2858 }
a66098da 2859
e6935ea1 2860 /* Clear unsupported feature flags */
447ced07 2861 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 2862
e6935ea1
LB		 2863 if (mwl8k_fw_lock(hw))
2864 return;
a66098da 2865
a43c49a8
LB		 2866 if (priv->sniffer_enabled) {
2867 mwl8k_enable_sniffer(hw, 0);
2868 priv->sniffer_enabled = false;
2869 }
2870
e6935ea1 2871 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 2872 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2873 /*
2874 * Disable the BSS filter.
2875 */
e6935ea1 2876 mwl8k_cmd_set_pre_scan(hw);
77165d88 2877 } else {
a94cc97e
LB		 2878 u8 *bssid;
2879
77165d88
LB		 2880 /*
2881 * Enable the BSS filter.
2882 *
2883 * If there is an active STA interface, use that
2884 * interface's BSSID, otherwise use a dummy one
2885 * (where the OUI part needs to be nonzero for
2886 * the BSSID to be accepted by POST_SCAN).
2887 */
2888 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e
LB		 2889 if (priv->vif != NULL)
2890 bssid = MWL8K_VIF(priv->vif)->bssid;
2891
e6935ea1 2892 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 2893 }
2894 }
2895
447ced07
LB		 2896 /*
2897 * If FIF_ALLMULTI is being requested, throw away the command
2898 * packet that ->prepare_multicast() built and replace it with
2899 * a command packet that enables reception of all multicast
2900 * packets.
2901 */
2902 if (*total_flags & FIF_ALLMULTI) {
2903 kfree(cmd);
2904 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
2905 }
2906
2907 if (cmd != NULL) {
2908 mwl8k_post_cmd(hw, cmd);
2909 kfree(cmd);
e6935ea1 2910 }
a66098da 2911
e6935ea1 2912 mwl8k_fw_unlock(hw);
a66098da
LB		 2913}
2914
a66098da
LB		 2915static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2916{
733d3067 2917 return mwl8k_rts_threshold(hw, MWL8K_CMD_SET, value);
a66098da
LB		 2918}
2919
a66098da
LB		 2920static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2921 const struct ieee80211_tx_queue_params *params)
2922{
3e4f542c 2923 struct mwl8k_priv *priv = hw->priv;
a66098da 2924 int rc;
a66098da 2925
3e4f542c
LB		 2926 rc = mwl8k_fw_lock(hw);
2927 if (!rc) {
2928 if (!priv->wmm_enabled)
2929 rc = mwl8k_set_wmm(hw, 1);
a66098da 2930
3e4f542c
LB		 2931 if (!rc)
2932 rc = mwl8k_set_edca_params(hw, queue,
2933 params->cw_min,
2934 params->cw_max,
2935 params->aifs,
2936 params->txop);
2937
2938 mwl8k_fw_unlock(hw);
a66098da 2939 }
3e4f542c 2940
a66098da
LB		 2941 return rc;
2942}
2943
2944static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
2945 struct ieee80211_tx_queue_stats *stats)
2946{
2947 struct mwl8k_priv *priv = hw->priv;
2948 struct mwl8k_tx_queue *txq;
2949 int index;
2950
2951 spin_lock_bh(&priv->tx_lock);
2952 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
2953 txq = priv->txq + index;
45eb400d 2954 memcpy(&stats[index], &txq->stats,
a66098da
LB		 2955 sizeof(struct ieee80211_tx_queue_stats));
2956 }
2957 spin_unlock_bh(&priv->tx_lock);
a66098da 2958
954ef509 2959 return 0;
a66098da
LB		 2960}
2961
2962static int mwl8k_get_stats(struct ieee80211_hw *hw,
2963 struct ieee80211_low_level_stats *stats)
2964{
954ef509 2965 return mwl8k_cmd_802_11_get_stat(hw, stats);
a66098da
LB		 2966}
2967
2968static const struct ieee80211_ops mwl8k_ops = {
2969 .tx = mwl8k_tx,
2970 .start = mwl8k_start,
2971 .stop = mwl8k_stop,
2972 .add_interface = mwl8k_add_interface,
2973 .remove_interface = mwl8k_remove_interface,
2974 .config = mwl8k_config,
a66098da 2975 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 2976 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 2977 .configure_filter = mwl8k_configure_filter,
2978 .set_rts_threshold = mwl8k_set_rts_threshold,
2979 .conf_tx = mwl8k_conf_tx,
2980 .get_tx_stats = mwl8k_get_tx_stats,
2981 .get_stats = mwl8k_get_stats,
2982};
2983
2984static void mwl8k_tx_reclaim_handler(unsigned long data)
2985{
2986 int i;
2987 struct ieee80211_hw *hw = (struct ieee80211_hw *) data;
2988 struct mwl8k_priv *priv = hw->priv;
2989
2990 spin_lock_bh(&priv->tx_lock);
2991 for (i = 0; i < MWL8K_TX_QUEUES; i++)
2992 mwl8k_txq_reclaim(hw, i, 0);
2993
88de754a 2994 if (priv->tx_wait != NULL && !priv->pending_tx_pkts) {
ce9e2e1b
LB		 2995 complete(priv->tx_wait);
2996 priv->tx_wait = NULL;
a66098da
LB		 2997 }
2998 spin_unlock_bh(&priv->tx_lock);
2999}
3000
3001static void mwl8k_finalize_join_worker(struct work_struct *work)
3002{
3003 struct mwl8k_priv *priv =
3004 container_of(work, struct mwl8k_priv, finalize_join_worker);
3005 struct sk_buff *skb = priv->beacon_skb;
ce9e2e1b 3006 u8 dtim = MWL8K_VIF(priv->vif)->bss_info.dtim_period;
a66098da
LB		 3007
3008 mwl8k_finalize_join(priv->hw, skb->data, skb->len, dtim);
3009 dev_kfree_skb(skb);
3010
3011 priv->beacon_skb = NULL;
3012}
3013
45a390dd 3014static struct mwl8k_device_info di_8687 = {
a74b295e
LB		 3015 .part_name = "88w8687",
3016 .helper_image = "mwl8k/helper_8687.fw",
3017 .fw_image = "mwl8k/fmimage_8687.fw",
54bc3a0d 3018 .rxd_ops = &rxd_8687_ops,
45a390dd
LB		 3019};
3020
3021static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
3022 {
3023 PCI_VDEVICE(MARVELL, 0x2a2b),
3024 .driver_data = (unsigned long)&di_8687,
3025 }, {
3026 PCI_VDEVICE(MARVELL, 0x2a30),
3027 .driver_data = (unsigned long)&di_8687,
3028 }, {
3029 },
3030};
3031MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3032
a66098da
LB		 3033static int __devinit mwl8k_probe(struct pci_dev *pdev,
3034 const struct pci_device_id *id)
3035{
2aa7b01f 3036 static int printed_version = 0;
a66098da
LB		 3037 struct ieee80211_hw *hw;
3038 struct mwl8k_priv *priv;
a66098da
LB		 3039 int rc;
3040 int i;
2aa7b01f
LB		 3041
3042 if (!printed_version) {
3043 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3044 printed_version = 1;
3045 }
a66098da
LB		 3046
3047 rc = pci_enable_device(pdev);
3048 if (rc) {
3049 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3050 MWL8K_NAME);
3051 return rc;
3052 }
3053
3054 rc = pci_request_regions(pdev, MWL8K_NAME);
3055 if (rc) {
3056 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3057 MWL8K_NAME);
3058 return rc;
3059 }
3060
3061 pci_set_master(pdev);
3062
3063 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3064 if (hw == NULL) {
3065 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3066 rc = -ENOMEM;
3067 goto err_free_reg;
3068 }
3069
3070 priv = hw->priv;
3071 priv->hw = hw;
3072 priv->pdev = pdev;
45a390dd 3073 priv->device_info = (void *)id->driver_data;
54bc3a0d 3074 priv->rxd_ops = priv->device_info->rxd_ops;
a43c49a8 3075 priv->sniffer_enabled = false;
0439b1f5 3076 priv->wmm_enabled = false;
a66098da 3077 priv->pending_tx_pkts = 0;
a66098da 3078
a66098da
LB		 3079 SET_IEEE80211_DEV(hw, &pdev->dev);
3080 pci_set_drvdata(pdev, hw);
3081
5b9482dd
LB		 3082 priv->sram = pci_iomap(pdev, 0, 0x10000);
3083 if (priv->sram == NULL) {
3084 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3085 wiphy_name(hw->wiphy));
a66098da
LB		 3086 goto err_iounmap;
3087 }
3088
5b9482dd
LB		 3089 /*
3090 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3091 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3092 */
3093 priv->regs = pci_iomap(pdev, 1, 0x10000);
3094 if (priv->regs == NULL) {
3095 priv->regs = pci_iomap(pdev, 2, 0x10000);
3096 if (priv->regs == NULL) {
3097 printk(KERN_ERR "%s: Cannot map device registers\n",
3098 wiphy_name(hw->wiphy));
3099 goto err_iounmap;
3100 }
3101 }
3102
a66098da
LB		 3103 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3104 priv->band.band = IEEE80211_BAND_2GHZ;
3105 priv->band.channels = priv->channels;
3106 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3107 priv->band.bitrates = priv->rates;
3108 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3109 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3110
3111 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3112 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3113
3114 /*
3115 * Extra headroom is the size of the required DMA header
3116 * minus the size of the smallest 802.11 frame (CTS frame).
3117 */
3118 hw->extra_tx_headroom =
3119 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3120
3121 hw->channel_change_time = 10;
3122
3123 hw->queues = MWL8K_TX_QUEUES;
3124
240e86ef 3125 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
a66098da
LB		 3126
3127 /* Set rssi and noise values to dBm */
ce9e2e1b 3128 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da
LB		 3129 hw->vif_data_size = sizeof(struct mwl8k_vif);
3130 priv->vif = NULL;
3131
3132 /* Set default radio state and preamble */
c46563b7 3133 priv->radio_on = 0;
68ce3884 3134 priv->radio_short_preamble = 0;
a66098da
LB		 3135
3136 /* Finalize join worker */
3137 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3138
3139 /* TX reclaim tasklet */
3140 tasklet_init(&priv->tx_reclaim_task,
3141 mwl8k_tx_reclaim_handler, (unsigned long)hw);
3142 tasklet_disable(&priv->tx_reclaim_task);
3143
a66098da
LB		 3144 /* Power management cookie */
3145 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3146 if (priv->cookie == NULL)
3147 goto err_iounmap;
3148
3149 rc = mwl8k_rxq_init(hw, 0);
3150 if (rc)
3151 goto err_iounmap;
3152 rxq_refill(hw, 0, INT_MAX);
3153
618952a7
LB		 3154 mutex_init(&priv->fw_mutex);
3155 priv->fw_mutex_owner = NULL;
3156 priv->fw_mutex_depth = 0;
618952a7
LB		 3157 priv->hostcmd_wait = NULL;
3158
a66098da
LB		 3159 spin_lock_init(&priv->tx_lock);
3160
88de754a
LB		 3161 priv->tx_wait = NULL;
3162
a66098da
LB		 3163 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3164 rc = mwl8k_txq_init(hw, i);
3165 if (rc)
3166 goto err_free_queues;
3167 }
3168
3169 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3170 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3171 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
3172 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3173
3174 rc = request_irq(priv->pdev->irq, &mwl8k_interrupt,
3175 IRQF_SHARED, MWL8K_NAME, hw);
3176 if (rc) {
3177 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3178 wiphy_name(hw->wiphy));
a66098da
LB		 3179 goto err_free_queues;
3180 }
3181
3182 /* Reset firmware and hardware */
3183 mwl8k_hw_reset(priv);
3184
3185 /* Ask userland hotplug daemon for the device firmware */
45a390dd 3186 rc = mwl8k_request_firmware(priv);
a66098da 3187 if (rc) {
c2c357ce
LB		 3188 printk(KERN_ERR "%s: Firmware files not found\n",
3189 wiphy_name(hw->wiphy));
a66098da
LB		 3190 goto err_free_irq;
3191 }
3192
3193 /* Load firmware into hardware */
c2c357ce 3194 rc = mwl8k_load_firmware(hw);
a66098da 3195 if (rc) {
c2c357ce
LB		 3196 printk(KERN_ERR "%s: Cannot start firmware\n",
3197 wiphy_name(hw->wiphy));
a66098da
LB		 3198 goto err_stop_firmware;
3199 }
3200
3201 /* Reclaim memory once firmware is successfully loaded */
3202 mwl8k_release_firmware(priv);
3203
3204 /*
3205 * Temporarily enable interrupts. Initial firmware host
3206 * commands use interrupts and avoids polling. Disable
3207 * interrupts when done.
3208 */
c23b5a69 3209 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3210
3211 /* Get config data, mac addrs etc */
3212 rc = mwl8k_cmd_get_hw_spec(hw);
3213 if (rc) {
c2c357ce
LB		 3214 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3215 wiphy_name(hw->wiphy));
a66098da
LB		 3216 goto err_stop_firmware;
3217 }
3218
3219 /* Turn radio off */
c46563b7 3220 rc = mwl8k_cmd_802_11_radio_disable(hw);
a66098da 3221 if (rc) {
c2c357ce 3222 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
a66098da
LB		 3223 goto err_stop_firmware;
3224 }
3225
32060e1b
LB		 3226 /* Clear MAC address */
3227 rc = mwl8k_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
3228 if (rc) {
3229 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3230 wiphy_name(hw->wiphy));
3231 goto err_stop_firmware;
3232 }
3233
a66098da 3234 /* Disable interrupts */
a66098da 3235 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3236 free_irq(priv->pdev->irq, hw);
3237
3238 rc = ieee80211_register_hw(hw);
3239 if (rc) {
c2c357ce
LB		 3240 printk(KERN_ERR "%s: Cannot register device\n",
3241 wiphy_name(hw->wiphy));
a66098da
LB		 3242 goto err_stop_firmware;
3243 }
3244
eae74e65 3245 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3246 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3247 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3248 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 3249 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
3250 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 3251
3252 return 0;
3253
3254err_stop_firmware:
3255 mwl8k_hw_reset(priv);
3256 mwl8k_release_firmware(priv);
3257
3258err_free_irq:
a66098da 3259 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3260 free_irq(priv->pdev->irq, hw);
3261
3262err_free_queues:
3263 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3264 mwl8k_txq_deinit(hw, i);
3265 mwl8k_rxq_deinit(hw, 0);
3266
3267err_iounmap:
3268 if (priv->cookie != NULL)
3269 pci_free_consistent(priv->pdev, 4,
3270 priv->cookie, priv->cookie_dma);
3271
3272 if (priv->regs != NULL)
3273 pci_iounmap(pdev, priv->regs);
3274
5b9482dd
LB		 3275 if (priv->sram != NULL)
3276 pci_iounmap(pdev, priv->sram);
3277
a66098da
LB		 3278 pci_set_drvdata(pdev, NULL);
3279 ieee80211_free_hw(hw);
3280
3281err_free_reg:
3282 pci_release_regions(pdev);
3283 pci_disable_device(pdev);
3284
3285 return rc;
3286}
3287
230f7af0 3288static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 3289{
3290 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
3291}
3292
230f7af0 3293static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 3294{
3295 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
3296 struct mwl8k_priv *priv;
3297 int i;
3298
3299 if (hw == NULL)
3300 return;
3301 priv = hw->priv;
3302
3303 ieee80211_stop_queues(hw);
3304
60aa569f
LB		 3305 ieee80211_unregister_hw(hw);
3306
a66098da
LB		 3307 /* Remove tx reclaim tasklet */
3308 tasklet_kill(&priv->tx_reclaim_task);
3309
a66098da
LB		 3310 /* Stop hardware */
3311 mwl8k_hw_reset(priv);
3312
3313 /* Return all skbs to mac80211 */
3314 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3315 mwl8k_txq_reclaim(hw, i, 1);
3316
a66098da
LB		 3317 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3318 mwl8k_txq_deinit(hw, i);
3319
3320 mwl8k_rxq_deinit(hw, 0);
3321
c2c357ce 3322 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 3323
3324 pci_iounmap(pdev, priv->regs);
5b9482dd 3325 pci_iounmap(pdev, priv->sram);
a66098da
LB		 3326 pci_set_drvdata(pdev, NULL);
3327 ieee80211_free_hw(hw);
3328 pci_release_regions(pdev);
3329 pci_disable_device(pdev);
3330}
3331
3332static struct pci_driver mwl8k_driver = {
3333 .name = MWL8K_NAME,
45a390dd 3334 .id_table = mwl8k_pci_id_table,
a66098da
LB		 3335 .probe = mwl8k_probe,
3336 .remove = __devexit_p(mwl8k_remove),
3337 .shutdown = __devexit_p(mwl8k_shutdown),
3338};
3339
3340static int __init mwl8k_init(void)
3341{
3342 return pci_register_driver(&mwl8k_driver);
3343}
3344
3345static void __exit mwl8k_exit(void)
3346{
3347 pci_unregister_driver(&mwl8k_driver);
3348}
3349
3350module_init(mwl8k_init);
3351module_exit(mwl8k_exit);
c2c357ce
LB		 3352
3353MODULE_DESCRIPTION(MWL8K_DESC);
3354MODULE_VERSION(MWL8K_VERSION);
3355MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
3356MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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