Commit | Line | Data |
---|---|---|
a66098da | 1 | /* |
ce9e2e1b LB |
2 | * drivers/net/wireless/mwl8k.c |
3 | * Driver for Marvell TOPDOG 802.11 Wireless cards | |
a66098da | 4 | * |
a145d575 | 5 | * Copyright (C) 2008-2009 Marvell Semiconductor Inc. |
a66098da LB |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
3d76e82c | 15 | #include <linux/sched.h> |
a66098da LB |
16 | #include <linux/spinlock.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/workqueue.h> | |
26 | ||
27 | #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" | |
28 | #define MWL8K_NAME KBUILD_MODNAME | |
6976b665 | 29 | #define MWL8K_VERSION "0.11" |
a66098da | 30 | |
a66098da LB |
31 | /* Register definitions */ |
32 | #define MWL8K_HIU_GEN_PTR 0x00000c10 | |
ce9e2e1b LB |
33 | #define MWL8K_MODE_STA 0x0000005a |
34 | #define MWL8K_MODE_AP 0x000000a5 | |
a66098da | 35 | #define MWL8K_HIU_INT_CODE 0x00000c14 |
ce9e2e1b LB |
36 | #define MWL8K_FWSTA_READY 0xf0f1f2f4 |
37 | #define MWL8K_FWAP_READY 0xf1f2f4a5 | |
38 | #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 | |
a66098da LB |
39 | #define MWL8K_HIU_SCRATCH 0x00000c40 |
40 | ||
41 | /* Host->device communications */ | |
42 | #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 | |
43 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c | |
44 | #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 | |
45 | #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 | |
46 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 | |
ce9e2e1b LB |
47 | #define MWL8K_H2A_INT_DUMMY (1 << 20) |
48 | #define MWL8K_H2A_INT_RESET (1 << 15) | |
49 | #define MWL8K_H2A_INT_DOORBELL (1 << 1) | |
50 | #define MWL8K_H2A_INT_PPA_READY (1 << 0) | |
a66098da LB |
51 | |
52 | /* Device->host communications */ | |
53 | #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c | |
54 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 | |
55 | #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 | |
56 | #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 | |
57 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c | |
ce9e2e1b LB |
58 | #define MWL8K_A2H_INT_DUMMY (1 << 20) |
59 | #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) | |
60 | #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) | |
61 | #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) | |
62 | #define MWL8K_A2H_INT_RADIO_ON (1 << 6) | |
63 | #define MWL8K_A2H_INT_RADIO_OFF (1 << 5) | |
64 | #define MWL8K_A2H_INT_MAC_EVENT (1 << 3) | |
65 | #define MWL8K_A2H_INT_OPC_DONE (1 << 2) | |
66 | #define MWL8K_A2H_INT_RX_READY (1 << 1) | |
67 | #define MWL8K_A2H_INT_TX_DONE (1 << 0) | |
a66098da LB |
68 | |
69 | #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ | |
70 | MWL8K_A2H_INT_CHNL_SWITCHED | \ | |
71 | MWL8K_A2H_INT_QUEUE_EMPTY | \ | |
72 | MWL8K_A2H_INT_RADAR_DETECT | \ | |
73 | MWL8K_A2H_INT_RADIO_ON | \ | |
74 | MWL8K_A2H_INT_RADIO_OFF | \ | |
75 | MWL8K_A2H_INT_MAC_EVENT | \ | |
76 | MWL8K_A2H_INT_OPC_DONE | \ | |
77 | MWL8K_A2H_INT_RX_READY | \ | |
78 | MWL8K_A2H_INT_TX_DONE) | |
79 | ||
a66098da LB |
80 | #define MWL8K_RX_QUEUES 1 |
81 | #define MWL8K_TX_QUEUES 4 | |
82 | ||
54bc3a0d LB |
83 | struct rxd_ops { |
84 | int rxd_size; | |
85 | void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); | |
86 | void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); | |
20f09c3d LB |
87 | int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status, |
88 | __le16 *qos); | |
54bc3a0d LB |
89 | }; |
90 | ||
45a390dd | 91 | struct mwl8k_device_info { |
a74b295e LB |
92 | char *part_name; |
93 | char *helper_image; | |
94 | char *fw_image; | |
89a91f4f | 95 | struct rxd_ops *ap_rxd_ops; |
45a390dd LB |
96 | }; |
97 | ||
a66098da | 98 | struct mwl8k_rx_queue { |
45eb400d | 99 | int rxd_count; |
a66098da LB |
100 | |
101 | /* hw receives here */ | |
45eb400d | 102 | int head; |
a66098da LB |
103 | |
104 | /* refill descs here */ | |
45eb400d | 105 | int tail; |
a66098da | 106 | |
54bc3a0d | 107 | void *rxd; |
45eb400d | 108 | dma_addr_t rxd_dma; |
788838eb LB |
109 | struct { |
110 | struct sk_buff *skb; | |
111 | DECLARE_PCI_UNMAP_ADDR(dma) | |
112 | } *buf; | |
a66098da LB |
113 | }; |
114 | ||
a66098da LB |
115 | struct mwl8k_tx_queue { |
116 | /* hw transmits here */ | |
45eb400d | 117 | int head; |
a66098da LB |
118 | |
119 | /* sw appends here */ | |
45eb400d | 120 | int tail; |
a66098da | 121 | |
45eb400d LB |
122 | struct ieee80211_tx_queue_stats stats; |
123 | struct mwl8k_tx_desc *txd; | |
124 | dma_addr_t txd_dma; | |
125 | struct sk_buff **skb; | |
a66098da LB |
126 | }; |
127 | ||
a66098da | 128 | struct mwl8k_priv { |
a66098da | 129 | struct ieee80211_hw *hw; |
a66098da | 130 | struct pci_dev *pdev; |
a66098da | 131 | |
45a390dd LB |
132 | struct mwl8k_device_info *device_info; |
133 | ||
be695fc4 LB |
134 | void __iomem *sram; |
135 | void __iomem *regs; | |
136 | ||
137 | /* firmware */ | |
22be40d9 LB |
138 | struct firmware *fw_helper; |
139 | struct firmware *fw_ucode; | |
a66098da | 140 | |
be695fc4 LB |
141 | /* hardware/firmware parameters */ |
142 | bool ap_fw; | |
143 | struct rxd_ops *rxd_ops; | |
777ad375 LB |
144 | struct ieee80211_supported_band band_24; |
145 | struct ieee80211_channel channels_24[14]; | |
146 | struct ieee80211_rate rates_24[14]; | |
4eae9edd LB |
147 | struct ieee80211_supported_band band_50; |
148 | struct ieee80211_channel channels_50[4]; | |
149 | struct ieee80211_rate rates_50[9]; | |
be695fc4 | 150 | |
618952a7 LB |
151 | /* firmware access */ |
152 | struct mutex fw_mutex; | |
153 | struct task_struct *fw_mutex_owner; | |
154 | int fw_mutex_depth; | |
618952a7 LB |
155 | struct completion *hostcmd_wait; |
156 | ||
a66098da LB |
157 | /* lock held over TX and TX reap */ |
158 | spinlock_t tx_lock; | |
a66098da | 159 | |
88de754a LB |
160 | /* TX quiesce completion, protected by fw_mutex and tx_lock */ |
161 | struct completion *tx_wait; | |
162 | ||
a66098da | 163 | struct ieee80211_vif *vif; |
a66098da | 164 | |
a66098da LB |
165 | /* power management status cookie from firmware */ |
166 | u32 *cookie; | |
167 | dma_addr_t cookie_dma; | |
168 | ||
169 | u16 num_mcaddrs; | |
a66098da | 170 | u8 hw_rev; |
2aa7b01f | 171 | u32 fw_rev; |
a66098da LB |
172 | |
173 | /* | |
174 | * Running count of TX packets in flight, to avoid | |
175 | * iterating over the transmit rings each time. | |
176 | */ | |
177 | int pending_tx_pkts; | |
178 | ||
179 | struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; | |
180 | struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES]; | |
181 | ||
c46563b7 | 182 | bool radio_on; |
68ce3884 | 183 | bool radio_short_preamble; |
a43c49a8 | 184 | bool sniffer_enabled; |
0439b1f5 | 185 | bool wmm_enabled; |
a66098da | 186 | |
bbfd9128 LB |
187 | struct work_struct sta_notify_worker; |
188 | spinlock_t sta_notify_list_lock; | |
189 | struct list_head sta_notify_list; | |
190 | ||
a66098da LB |
191 | /* XXX need to convert this to handle multiple interfaces */ |
192 | bool capture_beacon; | |
d89173f2 | 193 | u8 capture_bssid[ETH_ALEN]; |
a66098da LB |
194 | struct sk_buff *beacon_skb; |
195 | ||
196 | /* | |
197 | * This FJ worker has to be global as it is scheduled from the | |
198 | * RX handler. At this point we don't know which interface it | |
199 | * belongs to until the list of bssids waiting to complete join | |
200 | * is checked. | |
201 | */ | |
202 | struct work_struct finalize_join_worker; | |
203 | ||
1e9f9de3 LB |
204 | /* Tasklet to perform TX reclaim. */ |
205 | struct tasklet_struct poll_tx_task; | |
67e2eb27 LB |
206 | |
207 | /* Tasklet to perform RX. */ | |
208 | struct tasklet_struct poll_rx_task; | |
a66098da LB |
209 | }; |
210 | ||
211 | /* Per interface specific private data */ | |
212 | struct mwl8k_vif { | |
c2c2b12a | 213 | /* Non AMPDU sequence number assigned by driver. */ |
a680400e | 214 | u16 seqno; |
a66098da | 215 | }; |
a94cc97e | 216 | #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) |
a66098da | 217 | |
a680400e LB |
218 | struct mwl8k_sta { |
219 | /* Index into station database. Returned by UPDATE_STADB. */ | |
220 | u8 peer_id; | |
221 | }; | |
222 | #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv)) | |
223 | ||
777ad375 | 224 | static const struct ieee80211_channel mwl8k_channels_24[] = { |
a66098da LB |
225 | { .center_freq = 2412, .hw_value = 1, }, |
226 | { .center_freq = 2417, .hw_value = 2, }, | |
227 | { .center_freq = 2422, .hw_value = 3, }, | |
228 | { .center_freq = 2427, .hw_value = 4, }, | |
229 | { .center_freq = 2432, .hw_value = 5, }, | |
230 | { .center_freq = 2437, .hw_value = 6, }, | |
231 | { .center_freq = 2442, .hw_value = 7, }, | |
232 | { .center_freq = 2447, .hw_value = 8, }, | |
233 | { .center_freq = 2452, .hw_value = 9, }, | |
234 | { .center_freq = 2457, .hw_value = 10, }, | |
235 | { .center_freq = 2462, .hw_value = 11, }, | |
647ca6b0 LB |
236 | { .center_freq = 2467, .hw_value = 12, }, |
237 | { .center_freq = 2472, .hw_value = 13, }, | |
238 | { .center_freq = 2484, .hw_value = 14, }, | |
a66098da LB |
239 | }; |
240 | ||
777ad375 | 241 | static const struct ieee80211_rate mwl8k_rates_24[] = { |
a66098da LB |
242 | { .bitrate = 10, .hw_value = 2, }, |
243 | { .bitrate = 20, .hw_value = 4, }, | |
244 | { .bitrate = 55, .hw_value = 11, }, | |
5dfd3e2c LB |
245 | { .bitrate = 110, .hw_value = 22, }, |
246 | { .bitrate = 220, .hw_value = 44, }, | |
a66098da LB |
247 | { .bitrate = 60, .hw_value = 12, }, |
248 | { .bitrate = 90, .hw_value = 18, }, | |
a66098da LB |
249 | { .bitrate = 120, .hw_value = 24, }, |
250 | { .bitrate = 180, .hw_value = 36, }, | |
251 | { .bitrate = 240, .hw_value = 48, }, | |
252 | { .bitrate = 360, .hw_value = 72, }, | |
253 | { .bitrate = 480, .hw_value = 96, }, | |
254 | { .bitrate = 540, .hw_value = 108, }, | |
140eb5e2 LB |
255 | { .bitrate = 720, .hw_value = 144, }, |
256 | }; | |
257 | ||
4eae9edd LB |
258 | static const struct ieee80211_channel mwl8k_channels_50[] = { |
259 | { .center_freq = 5180, .hw_value = 36, }, | |
260 | { .center_freq = 5200, .hw_value = 40, }, | |
261 | { .center_freq = 5220, .hw_value = 44, }, | |
262 | { .center_freq = 5240, .hw_value = 48, }, | |
263 | }; | |
264 | ||
265 | static const struct ieee80211_rate mwl8k_rates_50[] = { | |
266 | { .bitrate = 60, .hw_value = 12, }, | |
267 | { .bitrate = 90, .hw_value = 18, }, | |
268 | { .bitrate = 120, .hw_value = 24, }, | |
269 | { .bitrate = 180, .hw_value = 36, }, | |
270 | { .bitrate = 240, .hw_value = 48, }, | |
271 | { .bitrate = 360, .hw_value = 72, }, | |
272 | { .bitrate = 480, .hw_value = 96, }, | |
273 | { .bitrate = 540, .hw_value = 108, }, | |
274 | { .bitrate = 720, .hw_value = 144, }, | |
275 | }; | |
276 | ||
a66098da LB |
277 | /* Set or get info from Firmware */ |
278 | #define MWL8K_CMD_SET 0x0001 | |
279 | #define MWL8K_CMD_GET 0x0000 | |
280 | ||
281 | /* Firmware command codes */ | |
282 | #define MWL8K_CMD_CODE_DNLD 0x0001 | |
283 | #define MWL8K_CMD_GET_HW_SPEC 0x0003 | |
42fba21d | 284 | #define MWL8K_CMD_SET_HW_SPEC 0x0004 |
a66098da LB |
285 | #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 |
286 | #define MWL8K_CMD_GET_STAT 0x0014 | |
ff45fc60 LB |
287 | #define MWL8K_CMD_RADIO_CONTROL 0x001c |
288 | #define MWL8K_CMD_RF_TX_POWER 0x001e | |
08b06347 | 289 | #define MWL8K_CMD_RF_ANTENNA 0x0020 |
b64fe619 | 290 | #define MWL8K_CMD_SET_BEACON 0x0100 |
a66098da LB |
291 | #define MWL8K_CMD_SET_PRE_SCAN 0x0107 |
292 | #define MWL8K_CMD_SET_POST_SCAN 0x0108 | |
ff45fc60 LB |
293 | #define MWL8K_CMD_SET_RF_CHANNEL 0x010a |
294 | #define MWL8K_CMD_SET_AID 0x010d | |
295 | #define MWL8K_CMD_SET_RATE 0x0110 | |
296 | #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 | |
297 | #define MWL8K_CMD_RTS_THRESHOLD 0x0113 | |
a66098da | 298 | #define MWL8K_CMD_SET_SLOT 0x0114 |
ff45fc60 LB |
299 | #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 |
300 | #define MWL8K_CMD_SET_WMM_MODE 0x0123 | |
a66098da | 301 | #define MWL8K_CMD_MIMO_CONFIG 0x0125 |
ff45fc60 | 302 | #define MWL8K_CMD_USE_FIXED_RATE 0x0126 |
a66098da | 303 | #define MWL8K_CMD_ENABLE_SNIFFER 0x0150 |
32060e1b | 304 | #define MWL8K_CMD_SET_MAC_ADDR 0x0202 |
a66098da | 305 | #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 |
b64fe619 | 306 | #define MWL8K_CMD_BSS_START 0x1100 |
3f5610ff | 307 | #define MWL8K_CMD_SET_NEW_STN 0x1111 |
ff45fc60 | 308 | #define MWL8K_CMD_UPDATE_STADB 0x1123 |
a66098da LB |
309 | |
310 | static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize) | |
311 | { | |
312 | #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ | |
313 | snprintf(buf, bufsize, "%s", #x);\ | |
314 | return buf;\ | |
315 | } while (0) | |
ce9e2e1b | 316 | switch (cmd & ~0x8000) { |
a66098da LB |
317 | MWL8K_CMDNAME(CODE_DNLD); |
318 | MWL8K_CMDNAME(GET_HW_SPEC); | |
42fba21d | 319 | MWL8K_CMDNAME(SET_HW_SPEC); |
a66098da LB |
320 | MWL8K_CMDNAME(MAC_MULTICAST_ADR); |
321 | MWL8K_CMDNAME(GET_STAT); | |
322 | MWL8K_CMDNAME(RADIO_CONTROL); | |
323 | MWL8K_CMDNAME(RF_TX_POWER); | |
08b06347 | 324 | MWL8K_CMDNAME(RF_ANTENNA); |
b64fe619 | 325 | MWL8K_CMDNAME(SET_BEACON); |
a66098da LB |
326 | MWL8K_CMDNAME(SET_PRE_SCAN); |
327 | MWL8K_CMDNAME(SET_POST_SCAN); | |
328 | MWL8K_CMDNAME(SET_RF_CHANNEL); | |
ff45fc60 LB |
329 | MWL8K_CMDNAME(SET_AID); |
330 | MWL8K_CMDNAME(SET_RATE); | |
331 | MWL8K_CMDNAME(SET_FINALIZE_JOIN); | |
332 | MWL8K_CMDNAME(RTS_THRESHOLD); | |
a66098da | 333 | MWL8K_CMDNAME(SET_SLOT); |
ff45fc60 LB |
334 | MWL8K_CMDNAME(SET_EDCA_PARAMS); |
335 | MWL8K_CMDNAME(SET_WMM_MODE); | |
a66098da | 336 | MWL8K_CMDNAME(MIMO_CONFIG); |
ff45fc60 | 337 | MWL8K_CMDNAME(USE_FIXED_RATE); |
a66098da | 338 | MWL8K_CMDNAME(ENABLE_SNIFFER); |
32060e1b | 339 | MWL8K_CMDNAME(SET_MAC_ADDR); |
a66098da | 340 | MWL8K_CMDNAME(SET_RATEADAPT_MODE); |
b64fe619 | 341 | MWL8K_CMDNAME(BSS_START); |
3f5610ff | 342 | MWL8K_CMDNAME(SET_NEW_STN); |
ff45fc60 | 343 | MWL8K_CMDNAME(UPDATE_STADB); |
a66098da LB |
344 | default: |
345 | snprintf(buf, bufsize, "0x%x", cmd); | |
346 | } | |
347 | #undef MWL8K_CMDNAME | |
348 | ||
349 | return buf; | |
350 | } | |
351 | ||
352 | /* Hardware and firmware reset */ | |
353 | static void mwl8k_hw_reset(struct mwl8k_priv *priv) | |
354 | { | |
355 | iowrite32(MWL8K_H2A_INT_RESET, | |
356 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
357 | iowrite32(MWL8K_H2A_INT_RESET, | |
358 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
359 | msleep(20); | |
360 | } | |
361 | ||
362 | /* Release fw image */ | |
363 | static void mwl8k_release_fw(struct firmware **fw) | |
364 | { | |
365 | if (*fw == NULL) | |
366 | return; | |
367 | release_firmware(*fw); | |
368 | *fw = NULL; | |
369 | } | |
370 | ||
371 | static void mwl8k_release_firmware(struct mwl8k_priv *priv) | |
372 | { | |
22be40d9 LB |
373 | mwl8k_release_fw(&priv->fw_ucode); |
374 | mwl8k_release_fw(&priv->fw_helper); | |
a66098da LB |
375 | } |
376 | ||
377 | /* Request fw image */ | |
378 | static int mwl8k_request_fw(struct mwl8k_priv *priv, | |
c2c357ce | 379 | const char *fname, struct firmware **fw) |
a66098da LB |
380 | { |
381 | /* release current image */ | |
382 | if (*fw != NULL) | |
383 | mwl8k_release_fw(fw); | |
384 | ||
385 | return request_firmware((const struct firmware **)fw, | |
c2c357ce | 386 | fname, &priv->pdev->dev); |
a66098da LB |
387 | } |
388 | ||
45a390dd | 389 | static int mwl8k_request_firmware(struct mwl8k_priv *priv) |
a66098da | 390 | { |
a74b295e | 391 | struct mwl8k_device_info *di = priv->device_info; |
a66098da LB |
392 | int rc; |
393 | ||
a74b295e | 394 | if (di->helper_image != NULL) { |
22be40d9 | 395 | rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper); |
a74b295e LB |
396 | if (rc) { |
397 | printk(KERN_ERR "%s: Error requesting helper " | |
398 | "firmware file %s\n", pci_name(priv->pdev), | |
399 | di->helper_image); | |
400 | return rc; | |
401 | } | |
a66098da LB |
402 | } |
403 | ||
22be40d9 | 404 | rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode); |
a66098da | 405 | if (rc) { |
c2c357ce | 406 | printk(KERN_ERR "%s: Error requesting firmware file %s\n", |
a74b295e | 407 | pci_name(priv->pdev), di->fw_image); |
22be40d9 | 408 | mwl8k_release_fw(&priv->fw_helper); |
a66098da LB |
409 | return rc; |
410 | } | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | struct mwl8k_cmd_pkt { | |
416 | __le16 code; | |
417 | __le16 length; | |
418 | __le16 seq_num; | |
419 | __le16 result; | |
420 | char payload[0]; | |
421 | } __attribute__((packed)); | |
422 | ||
423 | /* | |
424 | * Firmware loading. | |
425 | */ | |
426 | static int | |
427 | mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) | |
428 | { | |
429 | void __iomem *regs = priv->regs; | |
430 | dma_addr_t dma_addr; | |
a66098da LB |
431 | int loops; |
432 | ||
433 | dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); | |
434 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
435 | return -ENOMEM; | |
436 | ||
437 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
438 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
439 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
440 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
441 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
442 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
443 | ||
a66098da LB |
444 | loops = 1000; |
445 | do { | |
446 | u32 int_code; | |
447 | ||
448 | int_code = ioread32(regs + MWL8K_HIU_INT_CODE); | |
449 | if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { | |
450 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
a66098da LB |
451 | break; |
452 | } | |
453 | ||
3d76e82c | 454 | cond_resched(); |
a66098da LB |
455 | udelay(1); |
456 | } while (--loops); | |
457 | ||
458 | pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); | |
459 | ||
d4b70570 | 460 | return loops ? 0 : -ETIMEDOUT; |
a66098da LB |
461 | } |
462 | ||
463 | static int mwl8k_load_fw_image(struct mwl8k_priv *priv, | |
464 | const u8 *data, size_t length) | |
465 | { | |
466 | struct mwl8k_cmd_pkt *cmd; | |
467 | int done; | |
468 | int rc = 0; | |
469 | ||
470 | cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); | |
471 | if (cmd == NULL) | |
472 | return -ENOMEM; | |
473 | ||
474 | cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); | |
475 | cmd->seq_num = 0; | |
476 | cmd->result = 0; | |
477 | ||
478 | done = 0; | |
479 | while (length) { | |
480 | int block_size = length > 256 ? 256 : length; | |
481 | ||
482 | memcpy(cmd->payload, data + done, block_size); | |
483 | cmd->length = cpu_to_le16(block_size); | |
484 | ||
485 | rc = mwl8k_send_fw_load_cmd(priv, cmd, | |
486 | sizeof(*cmd) + block_size); | |
487 | if (rc) | |
488 | break; | |
489 | ||
490 | done += block_size; | |
491 | length -= block_size; | |
492 | } | |
493 | ||
494 | if (!rc) { | |
495 | cmd->length = 0; | |
496 | rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); | |
497 | } | |
498 | ||
499 | kfree(cmd); | |
500 | ||
501 | return rc; | |
502 | } | |
503 | ||
504 | static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, | |
505 | const u8 *data, size_t length) | |
506 | { | |
507 | unsigned char *buffer; | |
508 | int may_continue, rc = 0; | |
509 | u32 done, prev_block_size; | |
510 | ||
511 | buffer = kmalloc(1024, GFP_KERNEL); | |
512 | if (buffer == NULL) | |
513 | return -ENOMEM; | |
514 | ||
515 | done = 0; | |
516 | prev_block_size = 0; | |
517 | may_continue = 1000; | |
518 | while (may_continue > 0) { | |
519 | u32 block_size; | |
520 | ||
521 | block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); | |
522 | if (block_size & 1) { | |
523 | block_size &= ~1; | |
524 | may_continue--; | |
525 | } else { | |
526 | done += prev_block_size; | |
527 | length -= prev_block_size; | |
528 | } | |
529 | ||
530 | if (block_size > 1024 || block_size > length) { | |
531 | rc = -EOVERFLOW; | |
532 | break; | |
533 | } | |
534 | ||
535 | if (length == 0) { | |
536 | rc = 0; | |
537 | break; | |
538 | } | |
539 | ||
540 | if (block_size == 0) { | |
541 | rc = -EPROTO; | |
542 | may_continue--; | |
543 | udelay(1); | |
544 | continue; | |
545 | } | |
546 | ||
547 | prev_block_size = block_size; | |
548 | memcpy(buffer, data + done, block_size); | |
549 | ||
550 | rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); | |
551 | if (rc) | |
552 | break; | |
553 | } | |
554 | ||
555 | if (!rc && length != 0) | |
556 | rc = -EREMOTEIO; | |
557 | ||
558 | kfree(buffer); | |
559 | ||
560 | return rc; | |
561 | } | |
562 | ||
c2c357ce | 563 | static int mwl8k_load_firmware(struct ieee80211_hw *hw) |
a66098da | 564 | { |
c2c357ce | 565 | struct mwl8k_priv *priv = hw->priv; |
22be40d9 | 566 | struct firmware *fw = priv->fw_ucode; |
c2c357ce LB |
567 | int rc; |
568 | int loops; | |
569 | ||
570 | if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) { | |
22be40d9 | 571 | struct firmware *helper = priv->fw_helper; |
a66098da | 572 | |
c2c357ce LB |
573 | if (helper == NULL) { |
574 | printk(KERN_ERR "%s: helper image needed but none " | |
575 | "given\n", pci_name(priv->pdev)); | |
576 | return -EINVAL; | |
577 | } | |
a66098da | 578 | |
c2c357ce | 579 | rc = mwl8k_load_fw_image(priv, helper->data, helper->size); |
a66098da LB |
580 | if (rc) { |
581 | printk(KERN_ERR "%s: unable to load firmware " | |
c2c357ce | 582 | "helper image\n", pci_name(priv->pdev)); |
a66098da LB |
583 | return rc; |
584 | } | |
89b872e2 | 585 | msleep(5); |
a66098da | 586 | |
c2c357ce | 587 | rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); |
a66098da | 588 | } else { |
c2c357ce | 589 | rc = mwl8k_load_fw_image(priv, fw->data, fw->size); |
a66098da LB |
590 | } |
591 | ||
592 | if (rc) { | |
c2c357ce LB |
593 | printk(KERN_ERR "%s: unable to load firmware image\n", |
594 | pci_name(priv->pdev)); | |
a66098da LB |
595 | return rc; |
596 | } | |
597 | ||
89a91f4f | 598 | iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); |
a66098da | 599 | |
89b872e2 | 600 | loops = 500000; |
a66098da | 601 | do { |
eae74e65 LB |
602 | u32 ready_code; |
603 | ||
604 | ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
605 | if (ready_code == MWL8K_FWAP_READY) { | |
606 | priv->ap_fw = 1; | |
607 | break; | |
608 | } else if (ready_code == MWL8K_FWSTA_READY) { | |
609 | priv->ap_fw = 0; | |
a66098da | 610 | break; |
eae74e65 LB |
611 | } |
612 | ||
613 | cond_resched(); | |
a66098da LB |
614 | udelay(1); |
615 | } while (--loops); | |
616 | ||
617 | return loops ? 0 : -ETIMEDOUT; | |
618 | } | |
619 | ||
620 | ||
a66098da LB |
621 | /* DMA header used by firmware and hardware. */ |
622 | struct mwl8k_dma_data { | |
623 | __le16 fwlen; | |
624 | struct ieee80211_hdr wh; | |
20f09c3d | 625 | char data[0]; |
a66098da LB |
626 | } __attribute__((packed)); |
627 | ||
628 | /* Routines to add/remove DMA header from skb. */ | |
20f09c3d | 629 | static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos) |
a66098da | 630 | { |
20f09c3d LB |
631 | struct mwl8k_dma_data *tr; |
632 | int hdrlen; | |
633 | ||
634 | tr = (struct mwl8k_dma_data *)skb->data; | |
635 | hdrlen = ieee80211_hdrlen(tr->wh.frame_control); | |
636 | ||
637 | if (hdrlen != sizeof(tr->wh)) { | |
638 | if (ieee80211_is_data_qos(tr->wh.frame_control)) { | |
639 | memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2); | |
640 | *((__le16 *)(tr->data - 2)) = qos; | |
641 | } else { | |
642 | memmove(tr->data - hdrlen, &tr->wh, hdrlen); | |
643 | } | |
a66098da | 644 | } |
20f09c3d LB |
645 | |
646 | if (hdrlen != sizeof(*tr)) | |
647 | skb_pull(skb, sizeof(*tr) - hdrlen); | |
a66098da LB |
648 | } |
649 | ||
76266b2a | 650 | static inline void mwl8k_add_dma_header(struct sk_buff *skb) |
a66098da LB |
651 | { |
652 | struct ieee80211_hdr *wh; | |
ca009301 | 653 | int hdrlen; |
a66098da LB |
654 | struct mwl8k_dma_data *tr; |
655 | ||
ca009301 LB |
656 | /* |
657 | * Add a firmware DMA header; the firmware requires that we | |
658 | * present a 2-byte payload length followed by a 4-address | |
659 | * header (without QoS field), followed (optionally) by any | |
660 | * WEP/ExtIV header (but only filled in for CCMP). | |
661 | */ | |
a66098da | 662 | wh = (struct ieee80211_hdr *)skb->data; |
ca009301 | 663 | |
a66098da | 664 | hdrlen = ieee80211_hdrlen(wh->frame_control); |
ca009301 LB |
665 | if (hdrlen != sizeof(*tr)) |
666 | skb_push(skb, sizeof(*tr) - hdrlen); | |
a66098da | 667 | |
ca009301 LB |
668 | if (ieee80211_is_data_qos(wh->frame_control)) |
669 | hdrlen -= 2; | |
a66098da LB |
670 | |
671 | tr = (struct mwl8k_dma_data *)skb->data; | |
672 | if (wh != &tr->wh) | |
673 | memmove(&tr->wh, wh, hdrlen); | |
ca009301 LB |
674 | if (hdrlen != sizeof(tr->wh)) |
675 | memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen); | |
a66098da LB |
676 | |
677 | /* | |
678 | * Firmware length is the length of the fully formed "802.11 | |
679 | * payload". That is, everything except for the 802.11 header. | |
680 | * This includes all crypto material including the MIC. | |
681 | */ | |
ca009301 | 682 | tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr)); |
a66098da LB |
683 | } |
684 | ||
685 | ||
686 | /* | |
89a91f4f | 687 | * Packet reception for 88w8366 AP firmware. |
6f6d1e9a | 688 | */ |
89a91f4f | 689 | struct mwl8k_rxd_8366_ap { |
6f6d1e9a LB |
690 | __le16 pkt_len; |
691 | __u8 sq2; | |
692 | __u8 rate; | |
693 | __le32 pkt_phys_addr; | |
694 | __le32 next_rxd_phys_addr; | |
695 | __le16 qos_control; | |
696 | __le16 htsig2; | |
697 | __le32 hw_rssi_info; | |
698 | __le32 hw_noise_floor_info; | |
699 | __u8 noise_floor; | |
700 | __u8 pad0[3]; | |
701 | __u8 rssi; | |
702 | __u8 rx_status; | |
703 | __u8 channel; | |
704 | __u8 rx_ctrl; | |
705 | } __attribute__((packed)); | |
706 | ||
89a91f4f LB |
707 | #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80 |
708 | #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40 | |
709 | #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f) | |
8e9f33f0 | 710 | |
89a91f4f | 711 | #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80 |
6f6d1e9a | 712 | |
89a91f4f | 713 | static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr) |
6f6d1e9a | 714 | { |
89a91f4f | 715 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a LB |
716 | |
717 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
89a91f4f | 718 | rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST; |
6f6d1e9a LB |
719 | } |
720 | ||
89a91f4f | 721 | static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len) |
6f6d1e9a | 722 | { |
89a91f4f | 723 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a LB |
724 | |
725 | rxd->pkt_len = cpu_to_le16(len); | |
726 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
727 | wmb(); | |
728 | rxd->rx_ctrl = 0; | |
729 | } | |
730 | ||
731 | static int | |
89a91f4f LB |
732 | mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status, |
733 | __le16 *qos) | |
6f6d1e9a | 734 | { |
89a91f4f | 735 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a | 736 | |
89a91f4f | 737 | if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST)) |
6f6d1e9a LB |
738 | return -1; |
739 | rmb(); | |
740 | ||
741 | memset(status, 0, sizeof(*status)); | |
742 | ||
743 | status->signal = -rxd->rssi; | |
744 | status->noise = -rxd->noise_floor; | |
745 | ||
89a91f4f | 746 | if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) { |
6f6d1e9a | 747 | status->flag |= RX_FLAG_HT; |
89a91f4f | 748 | if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ) |
8e9f33f0 | 749 | status->flag |= RX_FLAG_40MHZ; |
89a91f4f | 750 | status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate); |
6f6d1e9a LB |
751 | } else { |
752 | int i; | |
753 | ||
777ad375 LB |
754 | for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) { |
755 | if (mwl8k_rates_24[i].hw_value == rxd->rate) { | |
6f6d1e9a LB |
756 | status->rate_idx = i; |
757 | break; | |
758 | } | |
759 | } | |
760 | } | |
761 | ||
85478344 LB |
762 | if (rxd->channel > 14) { |
763 | status->band = IEEE80211_BAND_5GHZ; | |
764 | if (!(status->flag & RX_FLAG_HT)) | |
765 | status->rate_idx -= 5; | |
766 | } else { | |
767 | status->band = IEEE80211_BAND_2GHZ; | |
768 | } | |
6f6d1e9a LB |
769 | status->freq = ieee80211_channel_to_frequency(rxd->channel); |
770 | ||
20f09c3d LB |
771 | *qos = rxd->qos_control; |
772 | ||
6f6d1e9a LB |
773 | return le16_to_cpu(rxd->pkt_len); |
774 | } | |
775 | ||
89a91f4f LB |
776 | static struct rxd_ops rxd_8366_ap_ops = { |
777 | .rxd_size = sizeof(struct mwl8k_rxd_8366_ap), | |
778 | .rxd_init = mwl8k_rxd_8366_ap_init, | |
779 | .rxd_refill = mwl8k_rxd_8366_ap_refill, | |
780 | .rxd_process = mwl8k_rxd_8366_ap_process, | |
6f6d1e9a LB |
781 | }; |
782 | ||
783 | /* | |
89a91f4f | 784 | * Packet reception for STA firmware. |
a66098da | 785 | */ |
89a91f4f | 786 | struct mwl8k_rxd_sta { |
a66098da LB |
787 | __le16 pkt_len; |
788 | __u8 link_quality; | |
789 | __u8 noise_level; | |
790 | __le32 pkt_phys_addr; | |
45eb400d | 791 | __le32 next_rxd_phys_addr; |
a66098da LB |
792 | __le16 qos_control; |
793 | __le16 rate_info; | |
794 | __le32 pad0[4]; | |
795 | __u8 rssi; | |
796 | __u8 channel; | |
797 | __le16 pad1; | |
798 | __u8 rx_ctrl; | |
799 | __u8 rx_status; | |
800 | __u8 pad2[2]; | |
801 | } __attribute__((packed)); | |
802 | ||
89a91f4f LB |
803 | #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000 |
804 | #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) | |
805 | #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) | |
806 | #define MWL8K_STA_RATE_INFO_40MHZ 0x0004 | |
807 | #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002 | |
808 | #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001 | |
54bc3a0d | 809 | |
89a91f4f | 810 | #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02 |
54bc3a0d | 811 | |
89a91f4f | 812 | static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr) |
54bc3a0d | 813 | { |
89a91f4f | 814 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
815 | |
816 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
89a91f4f | 817 | rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST; |
54bc3a0d LB |
818 | } |
819 | ||
89a91f4f | 820 | static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len) |
54bc3a0d | 821 | { |
89a91f4f | 822 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
823 | |
824 | rxd->pkt_len = cpu_to_le16(len); | |
825 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
826 | wmb(); | |
827 | rxd->rx_ctrl = 0; | |
828 | } | |
829 | ||
830 | static int | |
89a91f4f | 831 | mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status, |
20f09c3d | 832 | __le16 *qos) |
54bc3a0d | 833 | { |
89a91f4f | 834 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
835 | u16 rate_info; |
836 | ||
89a91f4f | 837 | if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST)) |
54bc3a0d LB |
838 | return -1; |
839 | rmb(); | |
840 | ||
841 | rate_info = le16_to_cpu(rxd->rate_info); | |
842 | ||
843 | memset(status, 0, sizeof(*status)); | |
844 | ||
845 | status->signal = -rxd->rssi; | |
846 | status->noise = -rxd->noise_level; | |
89a91f4f LB |
847 | status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info); |
848 | status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info); | |
54bc3a0d | 849 | |
89a91f4f | 850 | if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE) |
54bc3a0d | 851 | status->flag |= RX_FLAG_SHORTPRE; |
89a91f4f | 852 | if (rate_info & MWL8K_STA_RATE_INFO_40MHZ) |
54bc3a0d | 853 | status->flag |= RX_FLAG_40MHZ; |
89a91f4f | 854 | if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI) |
54bc3a0d | 855 | status->flag |= RX_FLAG_SHORT_GI; |
89a91f4f | 856 | if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT) |
54bc3a0d LB |
857 | status->flag |= RX_FLAG_HT; |
858 | ||
85478344 LB |
859 | if (rxd->channel > 14) { |
860 | status->band = IEEE80211_BAND_5GHZ; | |
861 | if (!(status->flag & RX_FLAG_HT)) | |
862 | status->rate_idx -= 5; | |
863 | } else { | |
864 | status->band = IEEE80211_BAND_2GHZ; | |
865 | } | |
54bc3a0d LB |
866 | status->freq = ieee80211_channel_to_frequency(rxd->channel); |
867 | ||
20f09c3d LB |
868 | *qos = rxd->qos_control; |
869 | ||
54bc3a0d LB |
870 | return le16_to_cpu(rxd->pkt_len); |
871 | } | |
872 | ||
89a91f4f LB |
873 | static struct rxd_ops rxd_sta_ops = { |
874 | .rxd_size = sizeof(struct mwl8k_rxd_sta), | |
875 | .rxd_init = mwl8k_rxd_sta_init, | |
876 | .rxd_refill = mwl8k_rxd_sta_refill, | |
877 | .rxd_process = mwl8k_rxd_sta_process, | |
54bc3a0d LB |
878 | }; |
879 | ||
880 | ||
a66098da LB |
881 | #define MWL8K_RX_DESCS 256 |
882 | #define MWL8K_RX_MAXSZ 3800 | |
883 | ||
884 | static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) | |
885 | { | |
886 | struct mwl8k_priv *priv = hw->priv; | |
887 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
888 | int size; | |
889 | int i; | |
890 | ||
45eb400d LB |
891 | rxq->rxd_count = 0; |
892 | rxq->head = 0; | |
893 | rxq->tail = 0; | |
a66098da | 894 | |
54bc3a0d | 895 | size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; |
a66098da | 896 | |
45eb400d LB |
897 | rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); |
898 | if (rxq->rxd == NULL) { | |
a66098da | 899 | printk(KERN_ERR "%s: failed to alloc RX descriptors\n", |
c2c357ce | 900 | wiphy_name(hw->wiphy)); |
a66098da LB |
901 | return -ENOMEM; |
902 | } | |
45eb400d | 903 | memset(rxq->rxd, 0, size); |
a66098da | 904 | |
788838eb LB |
905 | rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL); |
906 | if (rxq->buf == NULL) { | |
a66098da | 907 | printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", |
c2c357ce | 908 | wiphy_name(hw->wiphy)); |
45eb400d | 909 | pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); |
a66098da LB |
910 | return -ENOMEM; |
911 | } | |
788838eb | 912 | memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf)); |
a66098da LB |
913 | |
914 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
54bc3a0d LB |
915 | int desc_size; |
916 | void *rxd; | |
a66098da | 917 | int nexti; |
54bc3a0d LB |
918 | dma_addr_t next_dma_addr; |
919 | ||
920 | desc_size = priv->rxd_ops->rxd_size; | |
921 | rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); | |
a66098da | 922 | |
54bc3a0d LB |
923 | nexti = i + 1; |
924 | if (nexti == MWL8K_RX_DESCS) | |
925 | nexti = 0; | |
926 | next_dma_addr = rxq->rxd_dma + (nexti * desc_size); | |
a66098da | 927 | |
54bc3a0d | 928 | priv->rxd_ops->rxd_init(rxd, next_dma_addr); |
a66098da LB |
929 | } |
930 | ||
931 | return 0; | |
932 | } | |
933 | ||
934 | static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) | |
935 | { | |
936 | struct mwl8k_priv *priv = hw->priv; | |
937 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
938 | int refilled; | |
939 | ||
940 | refilled = 0; | |
45eb400d | 941 | while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { |
a66098da | 942 | struct sk_buff *skb; |
788838eb | 943 | dma_addr_t addr; |
a66098da | 944 | int rx; |
54bc3a0d | 945 | void *rxd; |
a66098da LB |
946 | |
947 | skb = dev_alloc_skb(MWL8K_RX_MAXSZ); | |
948 | if (skb == NULL) | |
949 | break; | |
950 | ||
788838eb LB |
951 | addr = pci_map_single(priv->pdev, skb->data, |
952 | MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); | |
a66098da | 953 | |
54bc3a0d LB |
954 | rxq->rxd_count++; |
955 | rx = rxq->tail++; | |
956 | if (rxq->tail == MWL8K_RX_DESCS) | |
957 | rxq->tail = 0; | |
788838eb LB |
958 | rxq->buf[rx].skb = skb; |
959 | pci_unmap_addr_set(&rxq->buf[rx], dma, addr); | |
54bc3a0d LB |
960 | |
961 | rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); | |
962 | priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); | |
a66098da LB |
963 | |
964 | refilled++; | |
965 | } | |
966 | ||
967 | return refilled; | |
968 | } | |
969 | ||
970 | /* Must be called only when the card's reception is completely halted */ | |
971 | static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) | |
972 | { | |
973 | struct mwl8k_priv *priv = hw->priv; | |
974 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
975 | int i; | |
976 | ||
977 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
788838eb LB |
978 | if (rxq->buf[i].skb != NULL) { |
979 | pci_unmap_single(priv->pdev, | |
980 | pci_unmap_addr(&rxq->buf[i], dma), | |
981 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
982 | pci_unmap_addr_set(&rxq->buf[i], dma, 0); | |
983 | ||
984 | kfree_skb(rxq->buf[i].skb); | |
985 | rxq->buf[i].skb = NULL; | |
a66098da LB |
986 | } |
987 | } | |
988 | ||
788838eb LB |
989 | kfree(rxq->buf); |
990 | rxq->buf = NULL; | |
a66098da LB |
991 | |
992 | pci_free_consistent(priv->pdev, | |
54bc3a0d | 993 | MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, |
45eb400d LB |
994 | rxq->rxd, rxq->rxd_dma); |
995 | rxq->rxd = NULL; | |
a66098da LB |
996 | } |
997 | ||
998 | ||
999 | /* | |
1000 | * Scan a list of BSSIDs to process for finalize join. | |
1001 | * Allows for extension to process multiple BSSIDs. | |
1002 | */ | |
1003 | static inline int | |
1004 | mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) | |
1005 | { | |
1006 | return priv->capture_beacon && | |
1007 | ieee80211_is_beacon(wh->frame_control) && | |
1008 | !compare_ether_addr(wh->addr3, priv->capture_bssid); | |
1009 | } | |
1010 | ||
3779752d LB |
1011 | static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, |
1012 | struct sk_buff *skb) | |
a66098da | 1013 | { |
3779752d LB |
1014 | struct mwl8k_priv *priv = hw->priv; |
1015 | ||
a66098da | 1016 | priv->capture_beacon = false; |
d89173f2 | 1017 | memset(priv->capture_bssid, 0, ETH_ALEN); |
a66098da LB |
1018 | |
1019 | /* | |
1020 | * Use GFP_ATOMIC as rxq_process is called from | |
1021 | * the primary interrupt handler, memory allocation call | |
1022 | * must not sleep. | |
1023 | */ | |
1024 | priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); | |
1025 | if (priv->beacon_skb != NULL) | |
3779752d | 1026 | ieee80211_queue_work(hw, &priv->finalize_join_worker); |
a66098da LB |
1027 | } |
1028 | ||
1029 | static int rxq_process(struct ieee80211_hw *hw, int index, int limit) | |
1030 | { | |
1031 | struct mwl8k_priv *priv = hw->priv; | |
1032 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
1033 | int processed; | |
1034 | ||
1035 | processed = 0; | |
45eb400d | 1036 | while (rxq->rxd_count && limit--) { |
a66098da | 1037 | struct sk_buff *skb; |
54bc3a0d LB |
1038 | void *rxd; |
1039 | int pkt_len; | |
a66098da | 1040 | struct ieee80211_rx_status status; |
20f09c3d | 1041 | __le16 qos; |
a66098da | 1042 | |
788838eb | 1043 | skb = rxq->buf[rxq->head].skb; |
d25f9f13 LB |
1044 | if (skb == NULL) |
1045 | break; | |
54bc3a0d LB |
1046 | |
1047 | rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); | |
1048 | ||
20f09c3d | 1049 | pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos); |
54bc3a0d LB |
1050 | if (pkt_len < 0) |
1051 | break; | |
1052 | ||
788838eb LB |
1053 | rxq->buf[rxq->head].skb = NULL; |
1054 | ||
1055 | pci_unmap_single(priv->pdev, | |
1056 | pci_unmap_addr(&rxq->buf[rxq->head], dma), | |
1057 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
1058 | pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); | |
a66098da | 1059 | |
54bc3a0d LB |
1060 | rxq->head++; |
1061 | if (rxq->head == MWL8K_RX_DESCS) | |
1062 | rxq->head = 0; | |
1063 | ||
45eb400d | 1064 | rxq->rxd_count--; |
a66098da | 1065 | |
54bc3a0d | 1066 | skb_put(skb, pkt_len); |
20f09c3d | 1067 | mwl8k_remove_dma_header(skb, qos); |
a66098da | 1068 | |
a66098da | 1069 | /* |
c2c357ce LB |
1070 | * Check for a pending join operation. Save a |
1071 | * copy of the beacon and schedule a tasklet to | |
1072 | * send a FINALIZE_JOIN command to the firmware. | |
a66098da | 1073 | */ |
54bc3a0d | 1074 | if (mwl8k_capture_bssid(priv, (void *)skb->data)) |
3779752d | 1075 | mwl8k_save_beacon(hw, skb); |
a66098da | 1076 | |
f1d58c25 JB |
1077 | memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); |
1078 | ieee80211_rx_irqsafe(hw, skb); | |
a66098da LB |
1079 | |
1080 | processed++; | |
1081 | } | |
1082 | ||
1083 | return processed; | |
1084 | } | |
1085 | ||
1086 | ||
1087 | /* | |
1088 | * Packet transmission. | |
1089 | */ | |
1090 | ||
a66098da LB |
1091 | #define MWL8K_TXD_STATUS_OK 0x00000001 |
1092 | #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 | |
1093 | #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 | |
1094 | #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 | |
a66098da | 1095 | #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 |
a66098da | 1096 | |
e0493a8d LB |
1097 | #define MWL8K_QOS_QLEN_UNSPEC 0xff00 |
1098 | #define MWL8K_QOS_ACK_POLICY_MASK 0x0060 | |
1099 | #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000 | |
1100 | #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060 | |
1101 | #define MWL8K_QOS_EOSP 0x0010 | |
1102 | ||
a66098da LB |
1103 | struct mwl8k_tx_desc { |
1104 | __le32 status; | |
1105 | __u8 data_rate; | |
1106 | __u8 tx_priority; | |
1107 | __le16 qos_control; | |
1108 | __le32 pkt_phys_addr; | |
1109 | __le16 pkt_len; | |
d89173f2 | 1110 | __u8 dest_MAC_addr[ETH_ALEN]; |
45eb400d | 1111 | __le32 next_txd_phys_addr; |
a66098da LB |
1112 | __le32 reserved; |
1113 | __le16 rate_info; | |
1114 | __u8 peer_id; | |
1115 | __u8 tx_frag_cnt; | |
1116 | } __attribute__((packed)); | |
1117 | ||
1118 | #define MWL8K_TX_DESCS 128 | |
1119 | ||
1120 | static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) | |
1121 | { | |
1122 | struct mwl8k_priv *priv = hw->priv; | |
1123 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1124 | int size; | |
1125 | int i; | |
1126 | ||
45eb400d LB |
1127 | memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats)); |
1128 | txq->stats.limit = MWL8K_TX_DESCS; | |
1129 | txq->head = 0; | |
1130 | txq->tail = 0; | |
a66098da LB |
1131 | |
1132 | size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); | |
1133 | ||
45eb400d LB |
1134 | txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); |
1135 | if (txq->txd == NULL) { | |
a66098da | 1136 | printk(KERN_ERR "%s: failed to alloc TX descriptors\n", |
c2c357ce | 1137 | wiphy_name(hw->wiphy)); |
a66098da LB |
1138 | return -ENOMEM; |
1139 | } | |
45eb400d | 1140 | memset(txq->txd, 0, size); |
a66098da | 1141 | |
45eb400d LB |
1142 | txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL); |
1143 | if (txq->skb == NULL) { | |
a66098da | 1144 | printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", |
c2c357ce | 1145 | wiphy_name(hw->wiphy)); |
45eb400d | 1146 | pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); |
a66098da LB |
1147 | return -ENOMEM; |
1148 | } | |
45eb400d | 1149 | memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb)); |
a66098da LB |
1150 | |
1151 | for (i = 0; i < MWL8K_TX_DESCS; i++) { | |
1152 | struct mwl8k_tx_desc *tx_desc; | |
1153 | int nexti; | |
1154 | ||
45eb400d | 1155 | tx_desc = txq->txd + i; |
a66098da LB |
1156 | nexti = (i + 1) % MWL8K_TX_DESCS; |
1157 | ||
1158 | tx_desc->status = 0; | |
45eb400d LB |
1159 | tx_desc->next_txd_phys_addr = |
1160 | cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); | |
a66098da LB |
1161 | } |
1162 | ||
1163 | return 0; | |
1164 | } | |
1165 | ||
1166 | static inline void mwl8k_tx_start(struct mwl8k_priv *priv) | |
1167 | { | |
1168 | iowrite32(MWL8K_H2A_INT_PPA_READY, | |
1169 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1170 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1171 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1172 | ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
1173 | } | |
1174 | ||
7e1112d3 | 1175 | static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw) |
a66098da | 1176 | { |
7e1112d3 LB |
1177 | struct mwl8k_priv *priv = hw->priv; |
1178 | int i; | |
1179 | ||
1180 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { | |
1181 | struct mwl8k_tx_queue *txq = priv->txq + i; | |
1182 | int fw_owned = 0; | |
1183 | int drv_owned = 0; | |
1184 | int unused = 0; | |
1185 | int desc; | |
1186 | ||
a66098da | 1187 | for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { |
7e1112d3 LB |
1188 | struct mwl8k_tx_desc *tx_desc = txq->txd + desc; |
1189 | u32 status; | |
a66098da | 1190 | |
7e1112d3 | 1191 | status = le32_to_cpu(tx_desc->status); |
a66098da | 1192 | if (status & MWL8K_TXD_STATUS_FW_OWNED) |
7e1112d3 | 1193 | fw_owned++; |
a66098da | 1194 | else |
7e1112d3 | 1195 | drv_owned++; |
a66098da LB |
1196 | |
1197 | if (tx_desc->pkt_len == 0) | |
7e1112d3 | 1198 | unused++; |
a66098da | 1199 | } |
a66098da | 1200 | |
7e1112d3 LB |
1201 | printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d " |
1202 | "fw_owned=%d drv_owned=%d unused=%d\n", | |
1203 | wiphy_name(hw->wiphy), i, | |
1204 | txq->stats.len, txq->head, txq->tail, | |
1205 | fw_owned, drv_owned, unused); | |
1206 | } | |
a66098da LB |
1207 | } |
1208 | ||
618952a7 | 1209 | /* |
88de754a | 1210 | * Must be called with priv->fw_mutex held and tx queues stopped. |
618952a7 | 1211 | */ |
62abd3cf | 1212 | #define MWL8K_TX_WAIT_TIMEOUT_MS 5000 |
7e1112d3 | 1213 | |
950d5b01 | 1214 | static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) |
a66098da | 1215 | { |
a66098da | 1216 | struct mwl8k_priv *priv = hw->priv; |
88de754a | 1217 | DECLARE_COMPLETION_ONSTACK(tx_wait); |
7e1112d3 LB |
1218 | int retry; |
1219 | int rc; | |
a66098da LB |
1220 | |
1221 | might_sleep(); | |
1222 | ||
7e1112d3 LB |
1223 | /* |
1224 | * The TX queues are stopped at this point, so this test | |
1225 | * doesn't need to take ->tx_lock. | |
1226 | */ | |
1227 | if (!priv->pending_tx_pkts) | |
1228 | return 0; | |
1229 | ||
1230 | retry = 0; | |
1231 | rc = 0; | |
1232 | ||
a66098da | 1233 | spin_lock_bh(&priv->tx_lock); |
7e1112d3 LB |
1234 | priv->tx_wait = &tx_wait; |
1235 | while (!rc) { | |
1236 | int oldcount; | |
1237 | unsigned long timeout; | |
a66098da | 1238 | |
7e1112d3 | 1239 | oldcount = priv->pending_tx_pkts; |
a66098da | 1240 | |
7e1112d3 | 1241 | spin_unlock_bh(&priv->tx_lock); |
88de754a | 1242 | timeout = wait_for_completion_timeout(&tx_wait, |
7e1112d3 | 1243 | msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS)); |
a66098da | 1244 | spin_lock_bh(&priv->tx_lock); |
7e1112d3 LB |
1245 | |
1246 | if (timeout) { | |
1247 | WARN_ON(priv->pending_tx_pkts); | |
1248 | if (retry) { | |
1249 | printk(KERN_NOTICE "%s: tx rings drained\n", | |
1250 | wiphy_name(hw->wiphy)); | |
1251 | } | |
1252 | break; | |
1253 | } | |
1254 | ||
1255 | if (priv->pending_tx_pkts < oldcount) { | |
9a2303b9 LB |
1256 | printk(KERN_NOTICE "%s: waiting for tx rings " |
1257 | "to drain (%d -> %d pkts)\n", | |
7e1112d3 LB |
1258 | wiphy_name(hw->wiphy), oldcount, |
1259 | priv->pending_tx_pkts); | |
1260 | retry = 1; | |
1261 | continue; | |
1262 | } | |
1263 | ||
a66098da | 1264 | priv->tx_wait = NULL; |
a66098da | 1265 | |
7e1112d3 LB |
1266 | printk(KERN_ERR "%s: tx rings stuck for %d ms\n", |
1267 | wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS); | |
1268 | mwl8k_dump_tx_rings(hw); | |
1269 | ||
1270 | rc = -ETIMEDOUT; | |
a66098da | 1271 | } |
7e1112d3 | 1272 | spin_unlock_bh(&priv->tx_lock); |
a66098da | 1273 | |
7e1112d3 | 1274 | return rc; |
a66098da LB |
1275 | } |
1276 | ||
c23b5a69 LB |
1277 | #define MWL8K_TXD_SUCCESS(status) \ |
1278 | ((status) & (MWL8K_TXD_STATUS_OK | \ | |
1279 | MWL8K_TXD_STATUS_OK_RETRY | \ | |
1280 | MWL8K_TXD_STATUS_OK_MORE_RETRY)) | |
a66098da | 1281 | |
efb7c49a LB |
1282 | static int |
1283 | mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force) | |
a66098da LB |
1284 | { |
1285 | struct mwl8k_priv *priv = hw->priv; | |
1286 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
efb7c49a | 1287 | int processed; |
a66098da | 1288 | |
efb7c49a LB |
1289 | processed = 0; |
1290 | while (txq->stats.len > 0 && limit--) { | |
a66098da | 1291 | int tx; |
a66098da LB |
1292 | struct mwl8k_tx_desc *tx_desc; |
1293 | unsigned long addr; | |
ce9e2e1b | 1294 | int size; |
a66098da LB |
1295 | struct sk_buff *skb; |
1296 | struct ieee80211_tx_info *info; | |
1297 | u32 status; | |
1298 | ||
45eb400d LB |
1299 | tx = txq->head; |
1300 | tx_desc = txq->txd + tx; | |
a66098da LB |
1301 | |
1302 | status = le32_to_cpu(tx_desc->status); | |
1303 | ||
1304 | if (status & MWL8K_TXD_STATUS_FW_OWNED) { | |
1305 | if (!force) | |
1306 | break; | |
1307 | tx_desc->status &= | |
1308 | ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); | |
1309 | } | |
1310 | ||
45eb400d LB |
1311 | txq->head = (tx + 1) % MWL8K_TX_DESCS; |
1312 | BUG_ON(txq->stats.len == 0); | |
1313 | txq->stats.len--; | |
a66098da LB |
1314 | priv->pending_tx_pkts--; |
1315 | ||
1316 | addr = le32_to_cpu(tx_desc->pkt_phys_addr); | |
ce9e2e1b | 1317 | size = le16_to_cpu(tx_desc->pkt_len); |
45eb400d LB |
1318 | skb = txq->skb[tx]; |
1319 | txq->skb[tx] = NULL; | |
a66098da LB |
1320 | |
1321 | BUG_ON(skb == NULL); | |
1322 | pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); | |
1323 | ||
20f09c3d | 1324 | mwl8k_remove_dma_header(skb, tx_desc->qos_control); |
a66098da LB |
1325 | |
1326 | /* Mark descriptor as unused */ | |
1327 | tx_desc->pkt_phys_addr = 0; | |
1328 | tx_desc->pkt_len = 0; | |
1329 | ||
a66098da LB |
1330 | info = IEEE80211_SKB_CB(skb); |
1331 | ieee80211_tx_info_clear_status(info); | |
ce9e2e1b | 1332 | if (MWL8K_TXD_SUCCESS(status)) |
a66098da | 1333 | info->flags |= IEEE80211_TX_STAT_ACK; |
a66098da LB |
1334 | |
1335 | ieee80211_tx_status_irqsafe(hw, skb); | |
1336 | ||
efb7c49a | 1337 | processed++; |
a66098da LB |
1338 | } |
1339 | ||
efb7c49a | 1340 | if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex)) |
a66098da | 1341 | ieee80211_wake_queue(hw, index); |
efb7c49a LB |
1342 | |
1343 | return processed; | |
a66098da LB |
1344 | } |
1345 | ||
1346 | /* must be called only when the card's transmit is completely halted */ | |
1347 | static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) | |
1348 | { | |
1349 | struct mwl8k_priv *priv = hw->priv; | |
1350 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1351 | ||
efb7c49a | 1352 | mwl8k_txq_reclaim(hw, index, INT_MAX, 1); |
a66098da | 1353 | |
45eb400d LB |
1354 | kfree(txq->skb); |
1355 | txq->skb = NULL; | |
a66098da LB |
1356 | |
1357 | pci_free_consistent(priv->pdev, | |
1358 | MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), | |
45eb400d LB |
1359 | txq->txd, txq->txd_dma); |
1360 | txq->txd = NULL; | |
a66098da LB |
1361 | } |
1362 | ||
1363 | static int | |
1364 | mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb) | |
1365 | { | |
1366 | struct mwl8k_priv *priv = hw->priv; | |
1367 | struct ieee80211_tx_info *tx_info; | |
23b33906 | 1368 | struct mwl8k_vif *mwl8k_vif; |
a66098da LB |
1369 | struct ieee80211_hdr *wh; |
1370 | struct mwl8k_tx_queue *txq; | |
1371 | struct mwl8k_tx_desc *tx; | |
a66098da | 1372 | dma_addr_t dma; |
23b33906 LB |
1373 | u32 txstatus; |
1374 | u8 txdatarate; | |
1375 | u16 qos; | |
a66098da | 1376 | |
23b33906 LB |
1377 | wh = (struct ieee80211_hdr *)skb->data; |
1378 | if (ieee80211_is_data_qos(wh->frame_control)) | |
1379 | qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); | |
1380 | else | |
1381 | qos = 0; | |
a66098da | 1382 | |
76266b2a | 1383 | mwl8k_add_dma_header(skb); |
23b33906 | 1384 | wh = &((struct mwl8k_dma_data *)skb->data)->wh; |
a66098da LB |
1385 | |
1386 | tx_info = IEEE80211_SKB_CB(skb); | |
1387 | mwl8k_vif = MWL8K_VIF(tx_info->control.vif); | |
a66098da LB |
1388 | |
1389 | if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
a66098da | 1390 | wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
657232b6 LB |
1391 | wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno); |
1392 | mwl8k_vif->seqno += 0x10; | |
a66098da LB |
1393 | } |
1394 | ||
23b33906 LB |
1395 | /* Setup firmware control bit fields for each frame type. */ |
1396 | txstatus = 0; | |
1397 | txdatarate = 0; | |
1398 | if (ieee80211_is_mgmt(wh->frame_control) || | |
1399 | ieee80211_is_ctl(wh->frame_control)) { | |
1400 | txdatarate = 0; | |
e0493a8d | 1401 | qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP; |
23b33906 LB |
1402 | } else if (ieee80211_is_data(wh->frame_control)) { |
1403 | txdatarate = 1; | |
1404 | if (is_multicast_ether_addr(wh->addr1)) | |
1405 | txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; | |
1406 | ||
e0493a8d | 1407 | qos &= ~MWL8K_QOS_ACK_POLICY_MASK; |
23b33906 | 1408 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) |
e0493a8d | 1409 | qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK; |
23b33906 | 1410 | else |
e0493a8d | 1411 | qos |= MWL8K_QOS_ACK_POLICY_NORMAL; |
23b33906 | 1412 | } |
a66098da LB |
1413 | |
1414 | dma = pci_map_single(priv->pdev, skb->data, | |
1415 | skb->len, PCI_DMA_TODEVICE); | |
1416 | ||
1417 | if (pci_dma_mapping_error(priv->pdev, dma)) { | |
1418 | printk(KERN_DEBUG "%s: failed to dma map skb, " | |
c2c357ce | 1419 | "dropping TX frame.\n", wiphy_name(hw->wiphy)); |
23b33906 | 1420 | dev_kfree_skb(skb); |
a66098da LB |
1421 | return NETDEV_TX_OK; |
1422 | } | |
1423 | ||
23b33906 | 1424 | spin_lock_bh(&priv->tx_lock); |
a66098da | 1425 | |
23b33906 | 1426 | txq = priv->txq + index; |
a66098da | 1427 | |
45eb400d LB |
1428 | BUG_ON(txq->skb[txq->tail] != NULL); |
1429 | txq->skb[txq->tail] = skb; | |
a66098da | 1430 | |
45eb400d | 1431 | tx = txq->txd + txq->tail; |
23b33906 LB |
1432 | tx->data_rate = txdatarate; |
1433 | tx->tx_priority = index; | |
a66098da | 1434 | tx->qos_control = cpu_to_le16(qos); |
a66098da LB |
1435 | tx->pkt_phys_addr = cpu_to_le32(dma); |
1436 | tx->pkt_len = cpu_to_le16(skb->len); | |
23b33906 | 1437 | tx->rate_info = 0; |
a680400e LB |
1438 | if (!priv->ap_fw && tx_info->control.sta != NULL) |
1439 | tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id; | |
1440 | else | |
1441 | tx->peer_id = 0; | |
a66098da | 1442 | wmb(); |
23b33906 LB |
1443 | tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); |
1444 | ||
45eb400d LB |
1445 | txq->stats.count++; |
1446 | txq->stats.len++; | |
a66098da | 1447 | priv->pending_tx_pkts++; |
a66098da | 1448 | |
45eb400d LB |
1449 | txq->tail++; |
1450 | if (txq->tail == MWL8K_TX_DESCS) | |
1451 | txq->tail = 0; | |
23b33906 | 1452 | |
45eb400d | 1453 | if (txq->head == txq->tail) |
a66098da LB |
1454 | ieee80211_stop_queue(hw, index); |
1455 | ||
23b33906 | 1456 | mwl8k_tx_start(priv); |
a66098da LB |
1457 | |
1458 | spin_unlock_bh(&priv->tx_lock); | |
1459 | ||
1460 | return NETDEV_TX_OK; | |
1461 | } | |
1462 | ||
1463 | ||
618952a7 LB |
1464 | /* |
1465 | * Firmware access. | |
1466 | * | |
1467 | * We have the following requirements for issuing firmware commands: | |
1468 | * - Some commands require that the packet transmit path is idle when | |
1469 | * the command is issued. (For simplicity, we'll just quiesce the | |
1470 | * transmit path for every command.) | |
1471 | * - There are certain sequences of commands that need to be issued to | |
1472 | * the hardware sequentially, with no other intervening commands. | |
1473 | * | |
1474 | * This leads to an implementation of a "firmware lock" as a mutex that | |
1475 | * can be taken recursively, and which is taken by both the low-level | |
1476 | * command submission function (mwl8k_post_cmd) as well as any users of | |
1477 | * that function that require issuing of an atomic sequence of commands, | |
1478 | * and quiesces the transmit path whenever it's taken. | |
1479 | */ | |
1480 | static int mwl8k_fw_lock(struct ieee80211_hw *hw) | |
1481 | { | |
1482 | struct mwl8k_priv *priv = hw->priv; | |
1483 | ||
1484 | if (priv->fw_mutex_owner != current) { | |
1485 | int rc; | |
1486 | ||
1487 | mutex_lock(&priv->fw_mutex); | |
1488 | ieee80211_stop_queues(hw); | |
1489 | ||
1490 | rc = mwl8k_tx_wait_empty(hw); | |
1491 | if (rc) { | |
1492 | ieee80211_wake_queues(hw); | |
1493 | mutex_unlock(&priv->fw_mutex); | |
1494 | ||
1495 | return rc; | |
1496 | } | |
1497 | ||
1498 | priv->fw_mutex_owner = current; | |
1499 | } | |
1500 | ||
1501 | priv->fw_mutex_depth++; | |
1502 | ||
1503 | return 0; | |
1504 | } | |
1505 | ||
1506 | static void mwl8k_fw_unlock(struct ieee80211_hw *hw) | |
1507 | { | |
1508 | struct mwl8k_priv *priv = hw->priv; | |
1509 | ||
1510 | if (!--priv->fw_mutex_depth) { | |
1511 | ieee80211_wake_queues(hw); | |
1512 | priv->fw_mutex_owner = NULL; | |
1513 | mutex_unlock(&priv->fw_mutex); | |
1514 | } | |
1515 | } | |
1516 | ||
1517 | ||
a66098da LB |
1518 | /* |
1519 | * Command processing. | |
1520 | */ | |
1521 | ||
0c9cc640 LB |
1522 | /* Timeout firmware commands after 10s */ |
1523 | #define MWL8K_CMD_TIMEOUT_MS 10000 | |
a66098da LB |
1524 | |
1525 | static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd) | |
1526 | { | |
1527 | DECLARE_COMPLETION_ONSTACK(cmd_wait); | |
1528 | struct mwl8k_priv *priv = hw->priv; | |
1529 | void __iomem *regs = priv->regs; | |
1530 | dma_addr_t dma_addr; | |
1531 | unsigned int dma_size; | |
1532 | int rc; | |
a66098da LB |
1533 | unsigned long timeout = 0; |
1534 | u8 buf[32]; | |
1535 | ||
c2c357ce | 1536 | cmd->result = 0xffff; |
a66098da LB |
1537 | dma_size = le16_to_cpu(cmd->length); |
1538 | dma_addr = pci_map_single(priv->pdev, cmd, dma_size, | |
1539 | PCI_DMA_BIDIRECTIONAL); | |
1540 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
1541 | return -ENOMEM; | |
1542 | ||
618952a7 | 1543 | rc = mwl8k_fw_lock(hw); |
39a1e42e LB |
1544 | if (rc) { |
1545 | pci_unmap_single(priv->pdev, dma_addr, dma_size, | |
1546 | PCI_DMA_BIDIRECTIONAL); | |
618952a7 | 1547 | return rc; |
39a1e42e | 1548 | } |
a66098da | 1549 | |
a66098da LB |
1550 | priv->hostcmd_wait = &cmd_wait; |
1551 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
1552 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
1553 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1554 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1555 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
a66098da LB |
1556 | |
1557 | timeout = wait_for_completion_timeout(&cmd_wait, | |
1558 | msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS)); | |
1559 | ||
618952a7 LB |
1560 | priv->hostcmd_wait = NULL; |
1561 | ||
1562 | mwl8k_fw_unlock(hw); | |
1563 | ||
37055bd4 LB |
1564 | pci_unmap_single(priv->pdev, dma_addr, dma_size, |
1565 | PCI_DMA_BIDIRECTIONAL); | |
1566 | ||
a66098da | 1567 | if (!timeout) { |
a66098da | 1568 | printk(KERN_ERR "%s: Command %s timeout after %u ms\n", |
c2c357ce | 1569 | wiphy_name(hw->wiphy), |
a66098da LB |
1570 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
1571 | MWL8K_CMD_TIMEOUT_MS); | |
1572 | rc = -ETIMEDOUT; | |
1573 | } else { | |
0c9cc640 LB |
1574 | int ms; |
1575 | ||
1576 | ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout); | |
1577 | ||
ce9e2e1b | 1578 | rc = cmd->result ? -EINVAL : 0; |
a66098da LB |
1579 | if (rc) |
1580 | printk(KERN_ERR "%s: Command %s error 0x%x\n", | |
c2c357ce | 1581 | wiphy_name(hw->wiphy), |
a66098da | 1582 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
76c962a2 | 1583 | le16_to_cpu(cmd->result)); |
0c9cc640 LB |
1584 | else if (ms > 2000) |
1585 | printk(KERN_NOTICE "%s: Command %s took %d ms\n", | |
1586 | wiphy_name(hw->wiphy), | |
1587 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), | |
1588 | ms); | |
a66098da LB |
1589 | } |
1590 | ||
a66098da LB |
1591 | return rc; |
1592 | } | |
1593 | ||
1349ad2f LB |
1594 | /* |
1595 | * Setup code shared between STA and AP firmware images. | |
1596 | */ | |
1597 | static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw) | |
1598 | { | |
1599 | struct mwl8k_priv *priv = hw->priv; | |
1600 | ||
1601 | BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24)); | |
1602 | memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24)); | |
1603 | ||
1604 | BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24)); | |
1605 | memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24)); | |
1606 | ||
1607 | priv->band_24.band = IEEE80211_BAND_2GHZ; | |
1608 | priv->band_24.channels = priv->channels_24; | |
1609 | priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24); | |
1610 | priv->band_24.bitrates = priv->rates_24; | |
1611 | priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24); | |
1612 | ||
1613 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24; | |
1614 | } | |
1615 | ||
4eae9edd LB |
1616 | static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw) |
1617 | { | |
1618 | struct mwl8k_priv *priv = hw->priv; | |
1619 | ||
1620 | BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50)); | |
1621 | memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50)); | |
1622 | ||
1623 | BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50)); | |
1624 | memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50)); | |
1625 | ||
1626 | priv->band_50.band = IEEE80211_BAND_5GHZ; | |
1627 | priv->band_50.channels = priv->channels_50; | |
1628 | priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50); | |
1629 | priv->band_50.bitrates = priv->rates_50; | |
1630 | priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50); | |
1631 | ||
1632 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50; | |
1633 | } | |
1634 | ||
a66098da | 1635 | /* |
04b147b1 | 1636 | * CMD_GET_HW_SPEC (STA version). |
a66098da | 1637 | */ |
04b147b1 | 1638 | struct mwl8k_cmd_get_hw_spec_sta { |
a66098da LB |
1639 | struct mwl8k_cmd_pkt header; |
1640 | __u8 hw_rev; | |
1641 | __u8 host_interface; | |
1642 | __le16 num_mcaddrs; | |
d89173f2 | 1643 | __u8 perm_addr[ETH_ALEN]; |
a66098da LB |
1644 | __le16 region_code; |
1645 | __le32 fw_rev; | |
1646 | __le32 ps_cookie; | |
1647 | __le32 caps; | |
1648 | __u8 mcs_bitmap[16]; | |
1649 | __le32 rx_queue_ptr; | |
1650 | __le32 num_tx_queues; | |
1651 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1652 | __le32 caps2; | |
1653 | __le32 num_tx_desc_per_queue; | |
45eb400d | 1654 | __le32 total_rxd; |
a66098da LB |
1655 | } __attribute__((packed)); |
1656 | ||
341c9791 LB |
1657 | #define MWL8K_CAP_MAX_AMSDU 0x20000000 |
1658 | #define MWL8K_CAP_GREENFIELD 0x08000000 | |
1659 | #define MWL8K_CAP_AMPDU 0x04000000 | |
1660 | #define MWL8K_CAP_RX_STBC 0x01000000 | |
1661 | #define MWL8K_CAP_TX_STBC 0x00800000 | |
1662 | #define MWL8K_CAP_SHORTGI_40MHZ 0x00400000 | |
1663 | #define MWL8K_CAP_SHORTGI_20MHZ 0x00200000 | |
1664 | #define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000 | |
1665 | #define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000 | |
1666 | #define MWL8K_CAP_DELAY_BA 0x00003000 | |
1667 | #define MWL8K_CAP_MIMO 0x00000200 | |
1668 | #define MWL8K_CAP_40MHZ 0x00000100 | |
1669 | ||
1670 | static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap) | |
1671 | { | |
1672 | struct mwl8k_priv *priv = hw->priv; | |
777ad375 | 1673 | struct ieee80211_supported_band *band = &priv->band_24; |
341c9791 LB |
1674 | int rx_streams; |
1675 | int tx_streams; | |
1676 | ||
777ad375 | 1677 | band->ht_cap.ht_supported = 1; |
341c9791 LB |
1678 | |
1679 | if (cap & MWL8K_CAP_MAX_AMSDU) | |
777ad375 | 1680 | band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU; |
341c9791 | 1681 | if (cap & MWL8K_CAP_GREENFIELD) |
777ad375 | 1682 | band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD; |
341c9791 LB |
1683 | if (cap & MWL8K_CAP_AMPDU) { |
1684 | hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION; | |
777ad375 LB |
1685 | band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
1686 | band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; | |
341c9791 LB |
1687 | } |
1688 | if (cap & MWL8K_CAP_RX_STBC) | |
777ad375 | 1689 | band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC; |
341c9791 | 1690 | if (cap & MWL8K_CAP_TX_STBC) |
777ad375 | 1691 | band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC; |
341c9791 | 1692 | if (cap & MWL8K_CAP_SHORTGI_40MHZ) |
777ad375 | 1693 | band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; |
341c9791 | 1694 | if (cap & MWL8K_CAP_SHORTGI_20MHZ) |
777ad375 | 1695 | band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20; |
341c9791 | 1696 | if (cap & MWL8K_CAP_DELAY_BA) |
777ad375 | 1697 | band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA; |
341c9791 | 1698 | if (cap & MWL8K_CAP_40MHZ) |
777ad375 | 1699 | band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
341c9791 LB |
1700 | |
1701 | rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK); | |
1702 | tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK); | |
1703 | ||
777ad375 | 1704 | band->ht_cap.mcs.rx_mask[0] = 0xff; |
341c9791 | 1705 | if (rx_streams >= 2) |
777ad375 | 1706 | band->ht_cap.mcs.rx_mask[1] = 0xff; |
341c9791 | 1707 | if (rx_streams >= 3) |
777ad375 LB |
1708 | band->ht_cap.mcs.rx_mask[2] = 0xff; |
1709 | band->ht_cap.mcs.rx_mask[4] = 0x01; | |
1710 | band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
341c9791 LB |
1711 | |
1712 | if (rx_streams != tx_streams) { | |
777ad375 LB |
1713 | band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; |
1714 | band->ht_cap.mcs.tx_params |= (tx_streams - 1) << | |
341c9791 LB |
1715 | IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT; |
1716 | } | |
1717 | } | |
1718 | ||
04b147b1 | 1719 | static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw) |
a66098da LB |
1720 | { |
1721 | struct mwl8k_priv *priv = hw->priv; | |
04b147b1 | 1722 | struct mwl8k_cmd_get_hw_spec_sta *cmd; |
a66098da LB |
1723 | int rc; |
1724 | int i; | |
1725 | ||
1726 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1727 | if (cmd == NULL) | |
1728 | return -ENOMEM; | |
1729 | ||
1730 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1731 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1732 | ||
1733 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1734 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
45eb400d | 1735 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); |
4ff6432e | 1736 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); |
a66098da | 1737 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
45eb400d | 1738 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); |
4ff6432e | 1739 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); |
45eb400d | 1740 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); |
a66098da LB |
1741 | |
1742 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1743 | ||
1744 | if (!rc) { | |
1745 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1746 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
4ff6432e | 1747 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); |
a66098da | 1748 | priv->hw_rev = cmd->hw_rev; |
1349ad2f | 1749 | mwl8k_setup_2ghz_band(hw); |
341c9791 LB |
1750 | if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO)) |
1751 | mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps)); | |
a66098da LB |
1752 | } |
1753 | ||
1754 | kfree(cmd); | |
1755 | return rc; | |
1756 | } | |
1757 | ||
42fba21d LB |
1758 | /* |
1759 | * CMD_GET_HW_SPEC (AP version). | |
1760 | */ | |
1761 | struct mwl8k_cmd_get_hw_spec_ap { | |
1762 | struct mwl8k_cmd_pkt header; | |
1763 | __u8 hw_rev; | |
1764 | __u8 host_interface; | |
1765 | __le16 num_wcb; | |
1766 | __le16 num_mcaddrs; | |
1767 | __u8 perm_addr[ETH_ALEN]; | |
1768 | __le16 region_code; | |
1769 | __le16 num_antenna; | |
1770 | __le32 fw_rev; | |
1771 | __le32 wcbbase0; | |
1772 | __le32 rxwrptr; | |
1773 | __le32 rxrdptr; | |
1774 | __le32 ps_cookie; | |
1775 | __le32 wcbbase1; | |
1776 | __le32 wcbbase2; | |
1777 | __le32 wcbbase3; | |
1778 | } __attribute__((packed)); | |
1779 | ||
1780 | static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) | |
1781 | { | |
1782 | struct mwl8k_priv *priv = hw->priv; | |
1783 | struct mwl8k_cmd_get_hw_spec_ap *cmd; | |
1784 | int rc; | |
1785 | ||
1786 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1787 | if (cmd == NULL) | |
1788 | return -ENOMEM; | |
1789 | ||
1790 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1791 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1792 | ||
1793 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1794 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1795 | ||
1796 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1797 | ||
1798 | if (!rc) { | |
1799 | int off; | |
1800 | ||
1801 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1802 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
1803 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); | |
1804 | priv->hw_rev = cmd->hw_rev; | |
1349ad2f | 1805 | mwl8k_setup_2ghz_band(hw); |
42fba21d LB |
1806 | |
1807 | off = le32_to_cpu(cmd->wcbbase0) & 0xffff; | |
1808 | iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off); | |
1809 | ||
1810 | off = le32_to_cpu(cmd->rxwrptr) & 0xffff; | |
1811 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1812 | ||
1813 | off = le32_to_cpu(cmd->rxrdptr) & 0xffff; | |
1814 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1815 | ||
1816 | off = le32_to_cpu(cmd->wcbbase1) & 0xffff; | |
1817 | iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off); | |
1818 | ||
1819 | off = le32_to_cpu(cmd->wcbbase2) & 0xffff; | |
1820 | iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off); | |
1821 | ||
1822 | off = le32_to_cpu(cmd->wcbbase3) & 0xffff; | |
1823 | iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off); | |
1824 | } | |
1825 | ||
1826 | kfree(cmd); | |
1827 | return rc; | |
1828 | } | |
1829 | ||
1830 | /* | |
1831 | * CMD_SET_HW_SPEC. | |
1832 | */ | |
1833 | struct mwl8k_cmd_set_hw_spec { | |
1834 | struct mwl8k_cmd_pkt header; | |
1835 | __u8 hw_rev; | |
1836 | __u8 host_interface; | |
1837 | __le16 num_mcaddrs; | |
1838 | __u8 perm_addr[ETH_ALEN]; | |
1839 | __le16 region_code; | |
1840 | __le32 fw_rev; | |
1841 | __le32 ps_cookie; | |
1842 | __le32 caps; | |
1843 | __le32 rx_queue_ptr; | |
1844 | __le32 num_tx_queues; | |
1845 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1846 | __le32 flags; | |
1847 | __le32 num_tx_desc_per_queue; | |
1848 | __le32 total_rxd; | |
1849 | } __attribute__((packed)); | |
1850 | ||
b64fe619 LB |
1851 | #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080 |
1852 | #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020 | |
1853 | #define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010 | |
42fba21d LB |
1854 | |
1855 | static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw) | |
1856 | { | |
1857 | struct mwl8k_priv *priv = hw->priv; | |
1858 | struct mwl8k_cmd_set_hw_spec *cmd; | |
1859 | int rc; | |
1860 | int i; | |
1861 | ||
1862 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1863 | if (cmd == NULL) | |
1864 | return -ENOMEM; | |
1865 | ||
1866 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC); | |
1867 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1868 | ||
1869 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1870 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); | |
1871 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); | |
1872 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
1873 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); | |
b64fe619 LB |
1874 | cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT | |
1875 | MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP | | |
1876 | MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON); | |
42fba21d LB |
1877 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); |
1878 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); | |
1879 | ||
1880 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1881 | kfree(cmd); | |
1882 | ||
1883 | return rc; | |
1884 | } | |
1885 | ||
a66098da LB |
1886 | /* |
1887 | * CMD_MAC_MULTICAST_ADR. | |
1888 | */ | |
1889 | struct mwl8k_cmd_mac_multicast_adr { | |
1890 | struct mwl8k_cmd_pkt header; | |
1891 | __le16 action; | |
1892 | __le16 numaddr; | |
ce9e2e1b | 1893 | __u8 addr[0][ETH_ALEN]; |
a66098da LB |
1894 | }; |
1895 | ||
d5e30845 LB |
1896 | #define MWL8K_ENABLE_RX_DIRECTED 0x0001 |
1897 | #define MWL8K_ENABLE_RX_MULTICAST 0x0002 | |
1898 | #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004 | |
1899 | #define MWL8K_ENABLE_RX_BROADCAST 0x0008 | |
ce9e2e1b | 1900 | |
e81cd2d6 | 1901 | static struct mwl8k_cmd_pkt * |
447ced07 | 1902 | __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti, |
e81cd2d6 | 1903 | int mc_count, struct dev_addr_list *mclist) |
a66098da | 1904 | { |
e81cd2d6 | 1905 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1906 | struct mwl8k_cmd_mac_multicast_adr *cmd; |
e81cd2d6 | 1907 | int size; |
e81cd2d6 | 1908 | |
447ced07 | 1909 | if (allmulti || mc_count > priv->num_mcaddrs) { |
d5e30845 LB |
1910 | allmulti = 1; |
1911 | mc_count = 0; | |
1912 | } | |
e81cd2d6 LB |
1913 | |
1914 | size = sizeof(*cmd) + mc_count * ETH_ALEN; | |
ce9e2e1b | 1915 | |
e81cd2d6 | 1916 | cmd = kzalloc(size, GFP_ATOMIC); |
a66098da | 1917 | if (cmd == NULL) |
e81cd2d6 | 1918 | return NULL; |
a66098da LB |
1919 | |
1920 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); | |
1921 | cmd->header.length = cpu_to_le16(size); | |
d5e30845 LB |
1922 | cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED | |
1923 | MWL8K_ENABLE_RX_BROADCAST); | |
1924 | ||
1925 | if (allmulti) { | |
1926 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST); | |
1927 | } else if (mc_count) { | |
1928 | int i; | |
1929 | ||
1930 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); | |
1931 | cmd->numaddr = cpu_to_le16(mc_count); | |
1932 | for (i = 0; i < mc_count && mclist; i++) { | |
1933 | if (mclist->da_addrlen != ETH_ALEN) { | |
1934 | kfree(cmd); | |
1935 | return NULL; | |
1936 | } | |
1937 | memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN); | |
1938 | mclist = mclist->next; | |
a66098da | 1939 | } |
a66098da LB |
1940 | } |
1941 | ||
e81cd2d6 | 1942 | return &cmd->header; |
a66098da LB |
1943 | } |
1944 | ||
1945 | /* | |
55489b6e | 1946 | * CMD_GET_STAT. |
a66098da | 1947 | */ |
55489b6e | 1948 | struct mwl8k_cmd_get_stat { |
a66098da | 1949 | struct mwl8k_cmd_pkt header; |
a66098da LB |
1950 | __le32 stats[64]; |
1951 | } __attribute__((packed)); | |
1952 | ||
1953 | #define MWL8K_STAT_ACK_FAILURE 9 | |
1954 | #define MWL8K_STAT_RTS_FAILURE 12 | |
1955 | #define MWL8K_STAT_FCS_ERROR 24 | |
1956 | #define MWL8K_STAT_RTS_SUCCESS 11 | |
1957 | ||
55489b6e LB |
1958 | static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw, |
1959 | struct ieee80211_low_level_stats *stats) | |
a66098da | 1960 | { |
55489b6e | 1961 | struct mwl8k_cmd_get_stat *cmd; |
a66098da LB |
1962 | int rc; |
1963 | ||
1964 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1965 | if (cmd == NULL) | |
1966 | return -ENOMEM; | |
1967 | ||
1968 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); | |
1969 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
1970 | |
1971 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1972 | if (!rc) { | |
1973 | stats->dot11ACKFailureCount = | |
1974 | le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]); | |
1975 | stats->dot11RTSFailureCount = | |
1976 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]); | |
1977 | stats->dot11FCSErrorCount = | |
1978 | le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]); | |
1979 | stats->dot11RTSSuccessCount = | |
1980 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]); | |
1981 | } | |
1982 | kfree(cmd); | |
1983 | ||
1984 | return rc; | |
1985 | } | |
1986 | ||
1987 | /* | |
55489b6e | 1988 | * CMD_RADIO_CONTROL. |
a66098da | 1989 | */ |
55489b6e | 1990 | struct mwl8k_cmd_radio_control { |
a66098da LB |
1991 | struct mwl8k_cmd_pkt header; |
1992 | __le16 action; | |
1993 | __le16 control; | |
1994 | __le16 radio_on; | |
1995 | } __attribute__((packed)); | |
1996 | ||
c46563b7 | 1997 | static int |
55489b6e | 1998 | mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force) |
a66098da LB |
1999 | { |
2000 | struct mwl8k_priv *priv = hw->priv; | |
55489b6e | 2001 | struct mwl8k_cmd_radio_control *cmd; |
a66098da LB |
2002 | int rc; |
2003 | ||
c46563b7 | 2004 | if (enable == priv->radio_on && !force) |
a66098da LB |
2005 | return 0; |
2006 | ||
a66098da LB |
2007 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
2008 | if (cmd == NULL) | |
2009 | return -ENOMEM; | |
2010 | ||
2011 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL); | |
2012 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2013 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
68ce3884 | 2014 | cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1); |
a66098da LB |
2015 | cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); |
2016 | ||
2017 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2018 | kfree(cmd); | |
2019 | ||
2020 | if (!rc) | |
c46563b7 | 2021 | priv->radio_on = enable; |
a66098da LB |
2022 | |
2023 | return rc; | |
2024 | } | |
2025 | ||
55489b6e | 2026 | static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw) |
c46563b7 | 2027 | { |
55489b6e | 2028 | return mwl8k_cmd_radio_control(hw, 0, 0); |
c46563b7 LB |
2029 | } |
2030 | ||
55489b6e | 2031 | static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw) |
c46563b7 | 2032 | { |
55489b6e | 2033 | return mwl8k_cmd_radio_control(hw, 1, 0); |
c46563b7 LB |
2034 | } |
2035 | ||
a66098da LB |
2036 | static int |
2037 | mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble) | |
2038 | { | |
99200a99 | 2039 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 2040 | |
68ce3884 | 2041 | priv->radio_short_preamble = short_preamble; |
a66098da | 2042 | |
55489b6e | 2043 | return mwl8k_cmd_radio_control(hw, 1, 1); |
a66098da LB |
2044 | } |
2045 | ||
2046 | /* | |
55489b6e | 2047 | * CMD_RF_TX_POWER. |
a66098da LB |
2048 | */ |
2049 | #define MWL8K_TX_POWER_LEVEL_TOTAL 8 | |
2050 | ||
55489b6e | 2051 | struct mwl8k_cmd_rf_tx_power { |
a66098da LB |
2052 | struct mwl8k_cmd_pkt header; |
2053 | __le16 action; | |
2054 | __le16 support_level; | |
2055 | __le16 current_level; | |
2056 | __le16 reserved; | |
2057 | __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL]; | |
2058 | } __attribute__((packed)); | |
2059 | ||
55489b6e | 2060 | static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm) |
a66098da | 2061 | { |
55489b6e | 2062 | struct mwl8k_cmd_rf_tx_power *cmd; |
a66098da LB |
2063 | int rc; |
2064 | ||
2065 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2066 | if (cmd == NULL) | |
2067 | return -ENOMEM; | |
2068 | ||
2069 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER); | |
2070 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2071 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2072 | cmd->support_level = cpu_to_le16(dBm); | |
2073 | ||
2074 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2075 | kfree(cmd); | |
2076 | ||
2077 | return rc; | |
2078 | } | |
2079 | ||
08b06347 LB |
2080 | /* |
2081 | * CMD_RF_ANTENNA. | |
2082 | */ | |
2083 | struct mwl8k_cmd_rf_antenna { | |
2084 | struct mwl8k_cmd_pkt header; | |
2085 | __le16 antenna; | |
2086 | __le16 mode; | |
2087 | } __attribute__((packed)); | |
2088 | ||
2089 | #define MWL8K_RF_ANTENNA_RX 1 | |
2090 | #define MWL8K_RF_ANTENNA_TX 2 | |
2091 | ||
2092 | static int | |
2093 | mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) | |
2094 | { | |
2095 | struct mwl8k_cmd_rf_antenna *cmd; | |
2096 | int rc; | |
2097 | ||
2098 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2099 | if (cmd == NULL) | |
2100 | return -ENOMEM; | |
2101 | ||
2102 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA); | |
2103 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2104 | cmd->antenna = cpu_to_le16(antenna); | |
2105 | cmd->mode = cpu_to_le16(mask); | |
2106 | ||
2107 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2108 | kfree(cmd); | |
2109 | ||
2110 | return rc; | |
2111 | } | |
2112 | ||
b64fe619 LB |
2113 | /* |
2114 | * CMD_SET_BEACON. | |
2115 | */ | |
2116 | struct mwl8k_cmd_set_beacon { | |
2117 | struct mwl8k_cmd_pkt header; | |
2118 | __le16 beacon_len; | |
2119 | __u8 beacon[0]; | |
2120 | }; | |
2121 | ||
2122 | static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len) | |
2123 | { | |
2124 | struct mwl8k_cmd_set_beacon *cmd; | |
2125 | int rc; | |
2126 | ||
2127 | cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL); | |
2128 | if (cmd == NULL) | |
2129 | return -ENOMEM; | |
2130 | ||
2131 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON); | |
2132 | cmd->header.length = cpu_to_le16(sizeof(*cmd) + len); | |
2133 | cmd->beacon_len = cpu_to_le16(len); | |
2134 | memcpy(cmd->beacon, beacon, len); | |
2135 | ||
2136 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2137 | kfree(cmd); | |
2138 | ||
2139 | return rc; | |
2140 | } | |
2141 | ||
a66098da LB |
2142 | /* |
2143 | * CMD_SET_PRE_SCAN. | |
2144 | */ | |
2145 | struct mwl8k_cmd_set_pre_scan { | |
2146 | struct mwl8k_cmd_pkt header; | |
2147 | } __attribute__((packed)); | |
2148 | ||
2149 | static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw) | |
2150 | { | |
2151 | struct mwl8k_cmd_set_pre_scan *cmd; | |
2152 | int rc; | |
2153 | ||
2154 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2155 | if (cmd == NULL) | |
2156 | return -ENOMEM; | |
2157 | ||
2158 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN); | |
2159 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2160 | ||
2161 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2162 | kfree(cmd); | |
2163 | ||
2164 | return rc; | |
2165 | } | |
2166 | ||
2167 | /* | |
2168 | * CMD_SET_POST_SCAN. | |
2169 | */ | |
2170 | struct mwl8k_cmd_set_post_scan { | |
2171 | struct mwl8k_cmd_pkt header; | |
2172 | __le32 isibss; | |
d89173f2 | 2173 | __u8 bssid[ETH_ALEN]; |
a66098da LB |
2174 | } __attribute__((packed)); |
2175 | ||
2176 | static int | |
0a11dfc3 | 2177 | mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac) |
a66098da LB |
2178 | { |
2179 | struct mwl8k_cmd_set_post_scan *cmd; | |
2180 | int rc; | |
2181 | ||
2182 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2183 | if (cmd == NULL) | |
2184 | return -ENOMEM; | |
2185 | ||
2186 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN); | |
2187 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2188 | cmd->isibss = 0; | |
d89173f2 | 2189 | memcpy(cmd->bssid, mac, ETH_ALEN); |
a66098da LB |
2190 | |
2191 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2192 | kfree(cmd); | |
2193 | ||
2194 | return rc; | |
2195 | } | |
2196 | ||
2197 | /* | |
2198 | * CMD_SET_RF_CHANNEL. | |
2199 | */ | |
2200 | struct mwl8k_cmd_set_rf_channel { | |
2201 | struct mwl8k_cmd_pkt header; | |
2202 | __le16 action; | |
2203 | __u8 current_channel; | |
2204 | __le32 channel_flags; | |
2205 | } __attribute__((packed)); | |
2206 | ||
2207 | static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw, | |
610677d2 | 2208 | struct ieee80211_conf *conf) |
a66098da | 2209 | { |
610677d2 | 2210 | struct ieee80211_channel *channel = conf->channel; |
a66098da LB |
2211 | struct mwl8k_cmd_set_rf_channel *cmd; |
2212 | int rc; | |
2213 | ||
2214 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2215 | if (cmd == NULL) | |
2216 | return -ENOMEM; | |
2217 | ||
2218 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL); | |
2219 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2220 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2221 | cmd->current_channel = channel->hw_value; | |
610677d2 | 2222 | |
a66098da | 2223 | if (channel->band == IEEE80211_BAND_2GHZ) |
610677d2 LB |
2224 | cmd->channel_flags |= cpu_to_le32(0x00000001); |
2225 | ||
2226 | if (conf->channel_type == NL80211_CHAN_NO_HT || | |
2227 | conf->channel_type == NL80211_CHAN_HT20) | |
2228 | cmd->channel_flags |= cpu_to_le32(0x00000080); | |
2229 | else if (conf->channel_type == NL80211_CHAN_HT40MINUS) | |
2230 | cmd->channel_flags |= cpu_to_le32(0x000001900); | |
2231 | else if (conf->channel_type == NL80211_CHAN_HT40PLUS) | |
2232 | cmd->channel_flags |= cpu_to_le32(0x000000900); | |
a66098da LB |
2233 | |
2234 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2235 | kfree(cmd); | |
2236 | ||
2237 | return rc; | |
2238 | } | |
2239 | ||
2240 | /* | |
55489b6e | 2241 | * CMD_SET_AID. |
a66098da | 2242 | */ |
55489b6e LB |
2243 | #define MWL8K_FRAME_PROT_DISABLED 0x00 |
2244 | #define MWL8K_FRAME_PROT_11G 0x07 | |
2245 | #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02 | |
2246 | #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06 | |
a66098da | 2247 | |
55489b6e LB |
2248 | struct mwl8k_cmd_update_set_aid { |
2249 | struct mwl8k_cmd_pkt header; | |
2250 | __le16 aid; | |
a66098da | 2251 | |
55489b6e LB |
2252 | /* AP's MAC address (BSSID) */ |
2253 | __u8 bssid[ETH_ALEN]; | |
2254 | __le16 protection_mode; | |
2255 | __u8 supp_rates[14]; | |
a66098da LB |
2256 | } __attribute__((packed)); |
2257 | ||
c6e96010 LB |
2258 | static void legacy_rate_mask_to_array(u8 *rates, u32 mask) |
2259 | { | |
2260 | int i; | |
2261 | int j; | |
2262 | ||
2263 | /* | |
2264 | * Clear nonstandard rates 4 and 13. | |
2265 | */ | |
2266 | mask &= 0x1fef; | |
2267 | ||
2268 | for (i = 0, j = 0; i < 14; i++) { | |
2269 | if (mask & (1 << i)) | |
777ad375 | 2270 | rates[j++] = mwl8k_rates_24[i].hw_value; |
c6e96010 LB |
2271 | } |
2272 | } | |
2273 | ||
55489b6e | 2274 | static int |
c6e96010 LB |
2275 | mwl8k_cmd_set_aid(struct ieee80211_hw *hw, |
2276 | struct ieee80211_vif *vif, u32 legacy_rate_mask) | |
a66098da | 2277 | { |
55489b6e LB |
2278 | struct mwl8k_cmd_update_set_aid *cmd; |
2279 | u16 prot_mode; | |
a66098da LB |
2280 | int rc; |
2281 | ||
2282 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2283 | if (cmd == NULL) | |
2284 | return -ENOMEM; | |
2285 | ||
55489b6e | 2286 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID); |
a66098da | 2287 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
7dc6a7a7 | 2288 | cmd->aid = cpu_to_le16(vif->bss_conf.aid); |
0a11dfc3 | 2289 | memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN); |
a66098da | 2290 | |
7dc6a7a7 | 2291 | if (vif->bss_conf.use_cts_prot) { |
55489b6e LB |
2292 | prot_mode = MWL8K_FRAME_PROT_11G; |
2293 | } else { | |
7dc6a7a7 | 2294 | switch (vif->bss_conf.ht_operation_mode & |
55489b6e LB |
2295 | IEEE80211_HT_OP_MODE_PROTECTION) { |
2296 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
2297 | prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY; | |
2298 | break; | |
2299 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
2300 | prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL; | |
2301 | break; | |
2302 | default: | |
2303 | prot_mode = MWL8K_FRAME_PROT_DISABLED; | |
2304 | break; | |
2305 | } | |
2306 | } | |
2307 | cmd->protection_mode = cpu_to_le16(prot_mode); | |
a66098da | 2308 | |
c6e96010 | 2309 | legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask); |
a66098da LB |
2310 | |
2311 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2312 | kfree(cmd); | |
2313 | ||
2314 | return rc; | |
2315 | } | |
2316 | ||
32060e1b | 2317 | /* |
55489b6e | 2318 | * CMD_SET_RATE. |
32060e1b | 2319 | */ |
55489b6e LB |
2320 | struct mwl8k_cmd_set_rate { |
2321 | struct mwl8k_cmd_pkt header; | |
2322 | __u8 legacy_rates[14]; | |
2323 | ||
2324 | /* Bitmap for supported MCS codes. */ | |
2325 | __u8 mcs_set[16]; | |
2326 | __u8 reserved[16]; | |
32060e1b LB |
2327 | } __attribute__((packed)); |
2328 | ||
55489b6e | 2329 | static int |
c6e96010 | 2330 | mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
13935e2c | 2331 | u32 legacy_rate_mask, u8 *mcs_rates) |
32060e1b | 2332 | { |
55489b6e | 2333 | struct mwl8k_cmd_set_rate *cmd; |
32060e1b LB |
2334 | int rc; |
2335 | ||
2336 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2337 | if (cmd == NULL) | |
2338 | return -ENOMEM; | |
2339 | ||
55489b6e | 2340 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE); |
32060e1b | 2341 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
c6e96010 | 2342 | legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask); |
13935e2c | 2343 | memcpy(cmd->mcs_set, mcs_rates, 16); |
32060e1b LB |
2344 | |
2345 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2346 | kfree(cmd); | |
2347 | ||
2348 | return rc; | |
2349 | } | |
2350 | ||
a66098da | 2351 | /* |
55489b6e | 2352 | * CMD_FINALIZE_JOIN. |
a66098da | 2353 | */ |
55489b6e LB |
2354 | #define MWL8K_FJ_BEACON_MAXLEN 128 |
2355 | ||
2356 | struct mwl8k_cmd_finalize_join { | |
a66098da | 2357 | struct mwl8k_cmd_pkt header; |
55489b6e LB |
2358 | __le32 sleep_interval; /* Number of beacon periods to sleep */ |
2359 | __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN]; | |
a66098da LB |
2360 | } __attribute__((packed)); |
2361 | ||
55489b6e LB |
2362 | static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame, |
2363 | int framelen, int dtim) | |
a66098da | 2364 | { |
55489b6e LB |
2365 | struct mwl8k_cmd_finalize_join *cmd; |
2366 | struct ieee80211_mgmt *payload = frame; | |
2367 | int payload_len; | |
a66098da LB |
2368 | int rc; |
2369 | ||
2370 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2371 | if (cmd == NULL) | |
2372 | return -ENOMEM; | |
2373 | ||
55489b6e | 2374 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN); |
a66098da | 2375 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2376 | cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1); |
2377 | ||
2378 | payload_len = framelen - ieee80211_hdrlen(payload->frame_control); | |
2379 | if (payload_len < 0) | |
2380 | payload_len = 0; | |
2381 | else if (payload_len > MWL8K_FJ_BEACON_MAXLEN) | |
2382 | payload_len = MWL8K_FJ_BEACON_MAXLEN; | |
2383 | ||
2384 | memcpy(cmd->beacon_data, &payload->u.beacon, payload_len); | |
a66098da LB |
2385 | |
2386 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2387 | kfree(cmd); | |
2388 | ||
2389 | return rc; | |
2390 | } | |
2391 | ||
2392 | /* | |
55489b6e | 2393 | * CMD_SET_RTS_THRESHOLD. |
a66098da | 2394 | */ |
55489b6e | 2395 | struct mwl8k_cmd_set_rts_threshold { |
a66098da LB |
2396 | struct mwl8k_cmd_pkt header; |
2397 | __le16 action; | |
55489b6e | 2398 | __le16 threshold; |
a66098da LB |
2399 | } __attribute__((packed)); |
2400 | ||
c2c2b12a LB |
2401 | static int |
2402 | mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh) | |
a66098da | 2403 | { |
55489b6e | 2404 | struct mwl8k_cmd_set_rts_threshold *cmd; |
a66098da LB |
2405 | int rc; |
2406 | ||
2407 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2408 | if (cmd == NULL) | |
2409 | return -ENOMEM; | |
2410 | ||
55489b6e | 2411 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD); |
a66098da | 2412 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
c2c2b12a LB |
2413 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); |
2414 | cmd->threshold = cpu_to_le16(rts_thresh); | |
a66098da LB |
2415 | |
2416 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2417 | kfree(cmd); | |
2418 | ||
a66098da LB |
2419 | return rc; |
2420 | } | |
2421 | ||
2422 | /* | |
55489b6e | 2423 | * CMD_SET_SLOT. |
a66098da | 2424 | */ |
55489b6e | 2425 | struct mwl8k_cmd_set_slot { |
a66098da LB |
2426 | struct mwl8k_cmd_pkt header; |
2427 | __le16 action; | |
55489b6e | 2428 | __u8 short_slot; |
a66098da LB |
2429 | } __attribute__((packed)); |
2430 | ||
55489b6e | 2431 | static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time) |
a66098da | 2432 | { |
55489b6e | 2433 | struct mwl8k_cmd_set_slot *cmd; |
a66098da LB |
2434 | int rc; |
2435 | ||
2436 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2437 | if (cmd == NULL) | |
2438 | return -ENOMEM; | |
2439 | ||
55489b6e | 2440 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT); |
a66098da | 2441 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2442 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); |
2443 | cmd->short_slot = short_slot_time; | |
a66098da LB |
2444 | |
2445 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2446 | kfree(cmd); | |
2447 | ||
2448 | return rc; | |
2449 | } | |
2450 | ||
2451 | /* | |
2452 | * CMD_SET_EDCA_PARAMS. | |
2453 | */ | |
2454 | struct mwl8k_cmd_set_edca_params { | |
2455 | struct mwl8k_cmd_pkt header; | |
2456 | ||
2457 | /* See MWL8K_SET_EDCA_XXX below */ | |
2458 | __le16 action; | |
2459 | ||
2460 | /* TX opportunity in units of 32 us */ | |
2461 | __le16 txop; | |
2462 | ||
2e484c89 LB |
2463 | union { |
2464 | struct { | |
2465 | /* Log exponent of max contention period: 0...15 */ | |
2466 | __le32 log_cw_max; | |
2467 | ||
2468 | /* Log exponent of min contention period: 0...15 */ | |
2469 | __le32 log_cw_min; | |
2470 | ||
2471 | /* Adaptive interframe spacing in units of 32us */ | |
2472 | __u8 aifs; | |
2473 | ||
2474 | /* TX queue to configure */ | |
2475 | __u8 txq; | |
2476 | } ap; | |
2477 | struct { | |
2478 | /* Log exponent of max contention period: 0...15 */ | |
2479 | __u8 log_cw_max; | |
a66098da | 2480 | |
2e484c89 LB |
2481 | /* Log exponent of min contention period: 0...15 */ |
2482 | __u8 log_cw_min; | |
a66098da | 2483 | |
2e484c89 LB |
2484 | /* Adaptive interframe spacing in units of 32us */ |
2485 | __u8 aifs; | |
a66098da | 2486 | |
2e484c89 LB |
2487 | /* TX queue to configure */ |
2488 | __u8 txq; | |
2489 | } sta; | |
2490 | }; | |
a66098da LB |
2491 | } __attribute__((packed)); |
2492 | ||
a66098da LB |
2493 | #define MWL8K_SET_EDCA_CW 0x01 |
2494 | #define MWL8K_SET_EDCA_TXOP 0x02 | |
2495 | #define MWL8K_SET_EDCA_AIFS 0x04 | |
2496 | ||
2497 | #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \ | |
2498 | MWL8K_SET_EDCA_TXOP | \ | |
2499 | MWL8K_SET_EDCA_AIFS) | |
2500 | ||
2501 | static int | |
55489b6e LB |
2502 | mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum, |
2503 | __u16 cw_min, __u16 cw_max, | |
2504 | __u8 aifs, __u16 txop) | |
a66098da | 2505 | { |
2e484c89 | 2506 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 2507 | struct mwl8k_cmd_set_edca_params *cmd; |
a66098da LB |
2508 | int rc; |
2509 | ||
2510 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2511 | if (cmd == NULL) | |
2512 | return -ENOMEM; | |
2513 | ||
a66098da LB |
2514 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); |
2515 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
2516 | cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); |
2517 | cmd->txop = cpu_to_le16(txop); | |
2e484c89 LB |
2518 | if (priv->ap_fw) { |
2519 | cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1)); | |
2520 | cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1)); | |
2521 | cmd->ap.aifs = aifs; | |
2522 | cmd->ap.txq = qnum; | |
2523 | } else { | |
2524 | cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1); | |
2525 | cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1); | |
2526 | cmd->sta.aifs = aifs; | |
2527 | cmd->sta.txq = qnum; | |
2528 | } | |
a66098da LB |
2529 | |
2530 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2531 | kfree(cmd); | |
2532 | ||
2533 | return rc; | |
2534 | } | |
2535 | ||
2536 | /* | |
55489b6e | 2537 | * CMD_SET_WMM_MODE. |
a66098da | 2538 | */ |
55489b6e | 2539 | struct mwl8k_cmd_set_wmm_mode { |
a66098da | 2540 | struct mwl8k_cmd_pkt header; |
55489b6e | 2541 | __le16 action; |
a66098da LB |
2542 | } __attribute__((packed)); |
2543 | ||
55489b6e | 2544 | static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable) |
a66098da | 2545 | { |
55489b6e LB |
2546 | struct mwl8k_priv *priv = hw->priv; |
2547 | struct mwl8k_cmd_set_wmm_mode *cmd; | |
a66098da LB |
2548 | int rc; |
2549 | ||
a66098da LB |
2550 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
2551 | if (cmd == NULL) | |
2552 | return -ENOMEM; | |
2553 | ||
55489b6e | 2554 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE); |
a66098da | 2555 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e | 2556 | cmd->action = cpu_to_le16(!!enable); |
a66098da LB |
2557 | |
2558 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2559 | kfree(cmd); | |
16cec43d | 2560 | |
55489b6e LB |
2561 | if (!rc) |
2562 | priv->wmm_enabled = enable; | |
a66098da LB |
2563 | |
2564 | return rc; | |
2565 | } | |
2566 | ||
2567 | /* | |
55489b6e | 2568 | * CMD_MIMO_CONFIG. |
a66098da | 2569 | */ |
55489b6e LB |
2570 | struct mwl8k_cmd_mimo_config { |
2571 | struct mwl8k_cmd_pkt header; | |
2572 | __le32 action; | |
2573 | __u8 rx_antenna_map; | |
2574 | __u8 tx_antenna_map; | |
a66098da LB |
2575 | } __attribute__((packed)); |
2576 | ||
55489b6e | 2577 | static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx) |
a66098da | 2578 | { |
55489b6e | 2579 | struct mwl8k_cmd_mimo_config *cmd; |
a66098da LB |
2580 | int rc; |
2581 | ||
2582 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2583 | if (cmd == NULL) | |
2584 | return -ENOMEM; | |
2585 | ||
55489b6e | 2586 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG); |
a66098da | 2587 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2588 | cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET); |
2589 | cmd->rx_antenna_map = rx; | |
2590 | cmd->tx_antenna_map = tx; | |
a66098da LB |
2591 | |
2592 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2593 | kfree(cmd); | |
2594 | ||
2595 | return rc; | |
2596 | } | |
2597 | ||
2598 | /* | |
b71ed2c6 | 2599 | * CMD_USE_FIXED_RATE (STA version). |
a66098da | 2600 | */ |
b71ed2c6 LB |
2601 | struct mwl8k_cmd_use_fixed_rate_sta { |
2602 | struct mwl8k_cmd_pkt header; | |
2603 | __le32 action; | |
2604 | __le32 allow_rate_drop; | |
2605 | __le32 num_rates; | |
2606 | struct { | |
2607 | __le32 is_ht_rate; | |
2608 | __le32 enable_retry; | |
2609 | __le32 rate; | |
2610 | __le32 retry_count; | |
2611 | } rate_entry[8]; | |
2612 | __le32 rate_type; | |
2613 | __le32 reserved1; | |
2614 | __le32 reserved2; | |
a66098da LB |
2615 | } __attribute__((packed)); |
2616 | ||
b71ed2c6 LB |
2617 | #define MWL8K_USE_AUTO_RATE 0x0002 |
2618 | #define MWL8K_UCAST_RATE 0 | |
a66098da | 2619 | |
b71ed2c6 | 2620 | static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw) |
a66098da | 2621 | { |
b71ed2c6 | 2622 | struct mwl8k_cmd_use_fixed_rate_sta *cmd; |
a66098da LB |
2623 | int rc; |
2624 | ||
2625 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2626 | if (cmd == NULL) | |
2627 | return -ENOMEM; | |
2628 | ||
2629 | cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); | |
2630 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
b71ed2c6 LB |
2631 | cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE); |
2632 | cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE); | |
a66098da LB |
2633 | |
2634 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2635 | kfree(cmd); | |
2636 | ||
2637 | return rc; | |
2638 | } | |
2639 | ||
088aab8b LB |
2640 | /* |
2641 | * CMD_USE_FIXED_RATE (AP version). | |
2642 | */ | |
2643 | struct mwl8k_cmd_use_fixed_rate_ap { | |
2644 | struct mwl8k_cmd_pkt header; | |
2645 | __le32 action; | |
2646 | __le32 allow_rate_drop; | |
2647 | __le32 num_rates; | |
2648 | struct mwl8k_rate_entry_ap { | |
2649 | __le32 is_ht_rate; | |
2650 | __le32 enable_retry; | |
2651 | __le32 rate; | |
2652 | __le32 retry_count; | |
2653 | } rate_entry[4]; | |
2654 | u8 multicast_rate; | |
2655 | u8 multicast_rate_type; | |
2656 | u8 management_rate; | |
2657 | } __attribute__((packed)); | |
2658 | ||
2659 | static int | |
2660 | mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt) | |
2661 | { | |
2662 | struct mwl8k_cmd_use_fixed_rate_ap *cmd; | |
2663 | int rc; | |
2664 | ||
2665 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2666 | if (cmd == NULL) | |
2667 | return -ENOMEM; | |
2668 | ||
2669 | cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); | |
2670 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2671 | cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE); | |
2672 | cmd->multicast_rate = mcast; | |
2673 | cmd->management_rate = mgmt; | |
2674 | ||
2675 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2676 | kfree(cmd); | |
2677 | ||
2678 | return rc; | |
2679 | } | |
2680 | ||
55489b6e LB |
2681 | /* |
2682 | * CMD_ENABLE_SNIFFER. | |
2683 | */ | |
2684 | struct mwl8k_cmd_enable_sniffer { | |
2685 | struct mwl8k_cmd_pkt header; | |
2686 | __le32 action; | |
2687 | } __attribute__((packed)); | |
2688 | ||
2689 | static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable) | |
2690 | { | |
2691 | struct mwl8k_cmd_enable_sniffer *cmd; | |
2692 | int rc; | |
2693 | ||
2694 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2695 | if (cmd == NULL) | |
2696 | return -ENOMEM; | |
2697 | ||
2698 | cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER); | |
2699 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2700 | cmd->action = cpu_to_le32(!!enable); | |
2701 | ||
2702 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2703 | kfree(cmd); | |
2704 | ||
2705 | return rc; | |
2706 | } | |
2707 | ||
2708 | /* | |
2709 | * CMD_SET_MAC_ADDR. | |
2710 | */ | |
2711 | struct mwl8k_cmd_set_mac_addr { | |
2712 | struct mwl8k_cmd_pkt header; | |
2713 | union { | |
2714 | struct { | |
2715 | __le16 mac_type; | |
2716 | __u8 mac_addr[ETH_ALEN]; | |
2717 | } mbss; | |
2718 | __u8 mac_addr[ETH_ALEN]; | |
2719 | }; | |
2720 | } __attribute__((packed)); | |
2721 | ||
a9e00b15 LB |
2722 | #define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0 |
2723 | #define MWL8K_MAC_TYPE_PRIMARY_AP 2 | |
2724 | ||
55489b6e LB |
2725 | static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac) |
2726 | { | |
2727 | struct mwl8k_priv *priv = hw->priv; | |
2728 | struct mwl8k_cmd_set_mac_addr *cmd; | |
2729 | int rc; | |
2730 | ||
2731 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2732 | if (cmd == NULL) | |
2733 | return -ENOMEM; | |
2734 | ||
2735 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR); | |
2736 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2737 | if (priv->ap_fw) { | |
a9e00b15 | 2738 | cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP); |
55489b6e LB |
2739 | memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN); |
2740 | } else { | |
2741 | memcpy(cmd->mac_addr, mac, ETH_ALEN); | |
2742 | } | |
2743 | ||
2744 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2745 | kfree(cmd); | |
2746 | ||
2747 | return rc; | |
2748 | } | |
2749 | ||
2750 | /* | |
2751 | * CMD_SET_RATEADAPT_MODE. | |
2752 | */ | |
2753 | struct mwl8k_cmd_set_rate_adapt_mode { | |
2754 | struct mwl8k_cmd_pkt header; | |
2755 | __le16 action; | |
2756 | __le16 mode; | |
2757 | } __attribute__((packed)); | |
2758 | ||
2759 | static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode) | |
2760 | { | |
2761 | struct mwl8k_cmd_set_rate_adapt_mode *cmd; | |
2762 | int rc; | |
2763 | ||
2764 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2765 | if (cmd == NULL) | |
2766 | return -ENOMEM; | |
2767 | ||
2768 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE); | |
2769 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2770 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2771 | cmd->mode = cpu_to_le16(mode); | |
2772 | ||
2773 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2774 | kfree(cmd); | |
2775 | ||
2776 | return rc; | |
2777 | } | |
2778 | ||
b64fe619 LB |
2779 | /* |
2780 | * CMD_BSS_START. | |
2781 | */ | |
2782 | struct mwl8k_cmd_bss_start { | |
2783 | struct mwl8k_cmd_pkt header; | |
2784 | __le32 enable; | |
2785 | } __attribute__((packed)); | |
2786 | ||
2787 | static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable) | |
2788 | { | |
2789 | struct mwl8k_cmd_bss_start *cmd; | |
2790 | int rc; | |
2791 | ||
2792 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2793 | if (cmd == NULL) | |
2794 | return -ENOMEM; | |
2795 | ||
2796 | cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START); | |
2797 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2798 | cmd->enable = cpu_to_le32(enable); | |
2799 | ||
2800 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2801 | kfree(cmd); | |
2802 | ||
2803 | return rc; | |
2804 | } | |
2805 | ||
3f5610ff LB |
2806 | /* |
2807 | * CMD_SET_NEW_STN. | |
2808 | */ | |
2809 | struct mwl8k_cmd_set_new_stn { | |
2810 | struct mwl8k_cmd_pkt header; | |
2811 | __le16 aid; | |
2812 | __u8 mac_addr[6]; | |
2813 | __le16 stn_id; | |
2814 | __le16 action; | |
2815 | __le16 rsvd; | |
2816 | __le32 legacy_rates; | |
2817 | __u8 ht_rates[4]; | |
2818 | __le16 cap_info; | |
2819 | __le16 ht_capabilities_info; | |
2820 | __u8 mac_ht_param_info; | |
2821 | __u8 rev; | |
2822 | __u8 control_channel; | |
2823 | __u8 add_channel; | |
2824 | __le16 op_mode; | |
2825 | __le16 stbc; | |
2826 | __u8 add_qos_info; | |
2827 | __u8 is_qos_sta; | |
2828 | __le32 fw_sta_ptr; | |
2829 | } __attribute__((packed)); | |
2830 | ||
2831 | #define MWL8K_STA_ACTION_ADD 0 | |
2832 | #define MWL8K_STA_ACTION_REMOVE 2 | |
2833 | ||
2834 | static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw, | |
2835 | struct ieee80211_vif *vif, | |
2836 | struct ieee80211_sta *sta) | |
2837 | { | |
2838 | struct mwl8k_cmd_set_new_stn *cmd; | |
2839 | int rc; | |
2840 | ||
2841 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2842 | if (cmd == NULL) | |
2843 | return -ENOMEM; | |
2844 | ||
2845 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN); | |
2846 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2847 | cmd->aid = cpu_to_le16(sta->aid); | |
2848 | memcpy(cmd->mac_addr, sta->addr, ETH_ALEN); | |
2849 | cmd->stn_id = cpu_to_le16(sta->aid); | |
2850 | cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD); | |
2851 | cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]); | |
2852 | if (sta->ht_cap.ht_supported) { | |
2853 | cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0]; | |
2854 | cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1]; | |
2855 | cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2]; | |
2856 | cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3]; | |
2857 | cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap); | |
2858 | cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) | | |
2859 | ((sta->ht_cap.ampdu_density & 7) << 2); | |
2860 | cmd->is_qos_sta = 1; | |
2861 | } | |
2862 | ||
2863 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2864 | kfree(cmd); | |
2865 | ||
2866 | return rc; | |
2867 | } | |
2868 | ||
b64fe619 LB |
2869 | static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw, |
2870 | struct ieee80211_vif *vif) | |
2871 | { | |
2872 | struct mwl8k_cmd_set_new_stn *cmd; | |
2873 | int rc; | |
2874 | ||
2875 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2876 | if (cmd == NULL) | |
2877 | return -ENOMEM; | |
2878 | ||
2879 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN); | |
2880 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2881 | memcpy(cmd->mac_addr, vif->addr, ETH_ALEN); | |
2882 | ||
2883 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2884 | kfree(cmd); | |
2885 | ||
2886 | return rc; | |
2887 | } | |
2888 | ||
3f5610ff LB |
2889 | static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw, |
2890 | struct ieee80211_vif *vif, u8 *addr) | |
2891 | { | |
2892 | struct mwl8k_cmd_set_new_stn *cmd; | |
2893 | int rc; | |
2894 | ||
2895 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2896 | if (cmd == NULL) | |
2897 | return -ENOMEM; | |
2898 | ||
2899 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN); | |
2900 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2901 | memcpy(cmd->mac_addr, addr, ETH_ALEN); | |
2902 | cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE); | |
2903 | ||
2904 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2905 | kfree(cmd); | |
2906 | ||
2907 | return rc; | |
2908 | } | |
2909 | ||
55489b6e LB |
2910 | /* |
2911 | * CMD_UPDATE_STADB. | |
2912 | */ | |
25d81b1e LB |
2913 | struct ewc_ht_info { |
2914 | __le16 control1; | |
2915 | __le16 control2; | |
2916 | __le16 control3; | |
2917 | } __attribute__((packed)); | |
2918 | ||
2919 | struct peer_capability_info { | |
2920 | /* Peer type - AP vs. STA. */ | |
2921 | __u8 peer_type; | |
2922 | ||
2923 | /* Basic 802.11 capabilities from assoc resp. */ | |
2924 | __le16 basic_caps; | |
2925 | ||
2926 | /* Set if peer supports 802.11n high throughput (HT). */ | |
2927 | __u8 ht_support; | |
2928 | ||
2929 | /* Valid if HT is supported. */ | |
2930 | __le16 ht_caps; | |
2931 | __u8 extended_ht_caps; | |
2932 | struct ewc_ht_info ewc_info; | |
2933 | ||
2934 | /* Legacy rate table. Intersection of our rates and peer rates. */ | |
2935 | __u8 legacy_rates[12]; | |
2936 | ||
2937 | /* HT rate table. Intersection of our rates and peer rates. */ | |
2938 | __u8 ht_rates[16]; | |
2939 | __u8 pad[16]; | |
2940 | ||
2941 | /* If set, interoperability mode, no proprietary extensions. */ | |
2942 | __u8 interop; | |
2943 | __u8 pad2; | |
2944 | __u8 station_id; | |
2945 | __le16 amsdu_enabled; | |
2946 | } __attribute__((packed)); | |
2947 | ||
55489b6e LB |
2948 | struct mwl8k_cmd_update_stadb { |
2949 | struct mwl8k_cmd_pkt header; | |
2950 | ||
2951 | /* See STADB_ACTION_TYPE */ | |
2952 | __le32 action; | |
2953 | ||
2954 | /* Peer MAC address */ | |
2955 | __u8 peer_addr[ETH_ALEN]; | |
2956 | ||
2957 | __le32 reserved; | |
2958 | ||
2959 | /* Peer info - valid during add/update. */ | |
2960 | struct peer_capability_info peer_info; | |
2961 | } __attribute__((packed)); | |
2962 | ||
a680400e LB |
2963 | #define MWL8K_STA_DB_MODIFY_ENTRY 1 |
2964 | #define MWL8K_STA_DB_DEL_ENTRY 2 | |
2965 | ||
2966 | /* Peer Entry flags - used to define the type of the peer node */ | |
2967 | #define MWL8K_PEER_TYPE_ACCESSPOINT 2 | |
2968 | ||
2969 | static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw, | |
c6e96010 | 2970 | struct ieee80211_vif *vif, |
13935e2c | 2971 | struct ieee80211_sta *sta) |
55489b6e | 2972 | { |
55489b6e | 2973 | struct mwl8k_cmd_update_stadb *cmd; |
a680400e | 2974 | struct peer_capability_info *p; |
55489b6e LB |
2975 | int rc; |
2976 | ||
2977 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2978 | if (cmd == NULL) | |
2979 | return -ENOMEM; | |
2980 | ||
2981 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
2982 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a680400e | 2983 | cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY); |
13935e2c | 2984 | memcpy(cmd->peer_addr, sta->addr, ETH_ALEN); |
55489b6e | 2985 | |
a680400e LB |
2986 | p = &cmd->peer_info; |
2987 | p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT; | |
2988 | p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability); | |
13935e2c LB |
2989 | p->ht_support = sta->ht_cap.ht_supported; |
2990 | p->ht_caps = sta->ht_cap.cap; | |
2991 | p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) | | |
2992 | ((sta->ht_cap.ampdu_density & 7) << 2); | |
2993 | legacy_rate_mask_to_array(p->legacy_rates, | |
2994 | sta->supp_rates[IEEE80211_BAND_2GHZ]); | |
2995 | memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16); | |
a680400e LB |
2996 | p->interop = 1; |
2997 | p->amsdu_enabled = 0; | |
2998 | ||
2999 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
3000 | kfree(cmd); | |
3001 | ||
3002 | return rc ? rc : p->station_id; | |
3003 | } | |
3004 | ||
3005 | static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw, | |
3006 | struct ieee80211_vif *vif, u8 *addr) | |
3007 | { | |
3008 | struct mwl8k_cmd_update_stadb *cmd; | |
3009 | int rc; | |
3010 | ||
3011 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
3012 | if (cmd == NULL) | |
3013 | return -ENOMEM; | |
3014 | ||
3015 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
3016 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
3017 | cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY); | |
bbfd9128 | 3018 | memcpy(cmd->peer_addr, addr, ETH_ALEN); |
55489b6e | 3019 | |
a680400e | 3020 | rc = mwl8k_post_cmd(hw, &cmd->header); |
55489b6e LB |
3021 | kfree(cmd); |
3022 | ||
3023 | return rc; | |
3024 | } | |
3025 | ||
a66098da LB |
3026 | |
3027 | /* | |
3028 | * Interrupt handling. | |
3029 | */ | |
3030 | static irqreturn_t mwl8k_interrupt(int irq, void *dev_id) | |
3031 | { | |
3032 | struct ieee80211_hw *hw = dev_id; | |
3033 | struct mwl8k_priv *priv = hw->priv; | |
3034 | u32 status; | |
3035 | ||
3036 | status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
a66098da LB |
3037 | if (!status) |
3038 | return IRQ_NONE; | |
3039 | ||
1e9f9de3 LB |
3040 | if (status & MWL8K_A2H_INT_TX_DONE) { |
3041 | status &= ~MWL8K_A2H_INT_TX_DONE; | |
3042 | tasklet_schedule(&priv->poll_tx_task); | |
3043 | } | |
3044 | ||
a66098da | 3045 | if (status & MWL8K_A2H_INT_RX_READY) { |
67e2eb27 LB |
3046 | status &= ~MWL8K_A2H_INT_RX_READY; |
3047 | tasklet_schedule(&priv->poll_rx_task); | |
a66098da LB |
3048 | } |
3049 | ||
67e2eb27 LB |
3050 | if (status) |
3051 | iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
3052 | ||
a66098da | 3053 | if (status & MWL8K_A2H_INT_OPC_DONE) { |
618952a7 | 3054 | if (priv->hostcmd_wait != NULL) |
a66098da | 3055 | complete(priv->hostcmd_wait); |
a66098da LB |
3056 | } |
3057 | ||
3058 | if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { | |
618952a7 | 3059 | if (!mutex_is_locked(&priv->fw_mutex) && |
88de754a | 3060 | priv->radio_on && priv->pending_tx_pkts) |
618952a7 | 3061 | mwl8k_tx_start(priv); |
a66098da LB |
3062 | } |
3063 | ||
3064 | return IRQ_HANDLED; | |
3065 | } | |
3066 | ||
1e9f9de3 LB |
3067 | static void mwl8k_tx_poll(unsigned long data) |
3068 | { | |
3069 | struct ieee80211_hw *hw = (struct ieee80211_hw *)data; | |
3070 | struct mwl8k_priv *priv = hw->priv; | |
3071 | int limit; | |
3072 | int i; | |
3073 | ||
3074 | limit = 32; | |
3075 | ||
3076 | spin_lock_bh(&priv->tx_lock); | |
3077 | ||
3078 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3079 | limit -= mwl8k_txq_reclaim(hw, i, limit, 0); | |
3080 | ||
3081 | if (!priv->pending_tx_pkts && priv->tx_wait != NULL) { | |
3082 | complete(priv->tx_wait); | |
3083 | priv->tx_wait = NULL; | |
3084 | } | |
3085 | ||
3086 | spin_unlock_bh(&priv->tx_lock); | |
3087 | ||
3088 | if (limit) { | |
3089 | writel(~MWL8K_A2H_INT_TX_DONE, | |
3090 | priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
3091 | } else { | |
3092 | tasklet_schedule(&priv->poll_tx_task); | |
3093 | } | |
3094 | } | |
3095 | ||
67e2eb27 LB |
3096 | static void mwl8k_rx_poll(unsigned long data) |
3097 | { | |
3098 | struct ieee80211_hw *hw = (struct ieee80211_hw *)data; | |
3099 | struct mwl8k_priv *priv = hw->priv; | |
3100 | int limit; | |
3101 | ||
3102 | limit = 32; | |
3103 | limit -= rxq_process(hw, 0, limit); | |
3104 | limit -= rxq_refill(hw, 0, limit); | |
3105 | ||
3106 | if (limit) { | |
3107 | writel(~MWL8K_A2H_INT_RX_READY, | |
3108 | priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
3109 | } else { | |
3110 | tasklet_schedule(&priv->poll_rx_task); | |
3111 | } | |
3112 | } | |
3113 | ||
a66098da LB |
3114 | |
3115 | /* | |
3116 | * Core driver operations. | |
3117 | */ | |
3118 | static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |
3119 | { | |
3120 | struct mwl8k_priv *priv = hw->priv; | |
3121 | int index = skb_get_queue_mapping(skb); | |
3122 | int rc; | |
3123 | ||
9189c100 | 3124 | if (!priv->radio_on) { |
a66098da | 3125 | printk(KERN_DEBUG "%s: dropped TX frame since radio " |
c2c357ce | 3126 | "disabled\n", wiphy_name(hw->wiphy)); |
a66098da LB |
3127 | dev_kfree_skb(skb); |
3128 | return NETDEV_TX_OK; | |
3129 | } | |
3130 | ||
3131 | rc = mwl8k_txq_xmit(hw, index, skb); | |
3132 | ||
3133 | return rc; | |
3134 | } | |
3135 | ||
a66098da LB |
3136 | static int mwl8k_start(struct ieee80211_hw *hw) |
3137 | { | |
a66098da LB |
3138 | struct mwl8k_priv *priv = hw->priv; |
3139 | int rc; | |
3140 | ||
a0607fd3 | 3141 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
3142 | IRQF_SHARED, MWL8K_NAME, hw); |
3143 | if (rc) { | |
3144 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 3145 | wiphy_name(hw->wiphy)); |
2ec610cb | 3146 | return -EIO; |
a66098da LB |
3147 | } |
3148 | ||
67e2eb27 | 3149 | /* Enable TX reclaim and RX tasklets. */ |
1e9f9de3 | 3150 | tasklet_enable(&priv->poll_tx_task); |
67e2eb27 | 3151 | tasklet_enable(&priv->poll_rx_task); |
2ec610cb | 3152 | |
a66098da | 3153 | /* Enable interrupts */ |
c23b5a69 | 3154 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da | 3155 | |
2ec610cb LB |
3156 | rc = mwl8k_fw_lock(hw); |
3157 | if (!rc) { | |
55489b6e | 3158 | rc = mwl8k_cmd_radio_enable(hw); |
a66098da | 3159 | |
5e4cf166 LB |
3160 | if (!priv->ap_fw) { |
3161 | if (!rc) | |
55489b6e | 3162 | rc = mwl8k_cmd_enable_sniffer(hw, 0); |
a66098da | 3163 | |
5e4cf166 LB |
3164 | if (!rc) |
3165 | rc = mwl8k_cmd_set_pre_scan(hw); | |
3166 | ||
3167 | if (!rc) | |
3168 | rc = mwl8k_cmd_set_post_scan(hw, | |
3169 | "\x00\x00\x00\x00\x00\x00"); | |
3170 | } | |
2ec610cb LB |
3171 | |
3172 | if (!rc) | |
55489b6e | 3173 | rc = mwl8k_cmd_set_rateadapt_mode(hw, 0); |
a66098da | 3174 | |
2ec610cb | 3175 | if (!rc) |
55489b6e | 3176 | rc = mwl8k_cmd_set_wmm_mode(hw, 0); |
a66098da | 3177 | |
2ec610cb LB |
3178 | mwl8k_fw_unlock(hw); |
3179 | } | |
3180 | ||
3181 | if (rc) { | |
3182 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); | |
3183 | free_irq(priv->pdev->irq, hw); | |
1e9f9de3 | 3184 | tasklet_disable(&priv->poll_tx_task); |
67e2eb27 | 3185 | tasklet_disable(&priv->poll_rx_task); |
2ec610cb | 3186 | } |
a66098da LB |
3187 | |
3188 | return rc; | |
3189 | } | |
3190 | ||
a66098da LB |
3191 | static void mwl8k_stop(struct ieee80211_hw *hw) |
3192 | { | |
a66098da LB |
3193 | struct mwl8k_priv *priv = hw->priv; |
3194 | int i; | |
3195 | ||
55489b6e | 3196 | mwl8k_cmd_radio_disable(hw); |
a66098da LB |
3197 | |
3198 | ieee80211_stop_queues(hw); | |
3199 | ||
a66098da | 3200 | /* Disable interrupts */ |
a66098da | 3201 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3202 | free_irq(priv->pdev->irq, hw); |
3203 | ||
3204 | /* Stop finalize join worker */ | |
3205 | cancel_work_sync(&priv->finalize_join_worker); | |
3206 | if (priv->beacon_skb != NULL) | |
3207 | dev_kfree_skb(priv->beacon_skb); | |
3208 | ||
67e2eb27 | 3209 | /* Stop TX reclaim and RX tasklets. */ |
1e9f9de3 | 3210 | tasklet_disable(&priv->poll_tx_task); |
67e2eb27 | 3211 | tasklet_disable(&priv->poll_rx_task); |
a66098da | 3212 | |
a66098da LB |
3213 | /* Return all skbs to mac80211 */ |
3214 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
efb7c49a | 3215 | mwl8k_txq_reclaim(hw, i, INT_MAX, 1); |
a66098da LB |
3216 | } |
3217 | ||
3218 | static int mwl8k_add_interface(struct ieee80211_hw *hw, | |
1ed32e4f | 3219 | struct ieee80211_vif *vif) |
a66098da LB |
3220 | { |
3221 | struct mwl8k_priv *priv = hw->priv; | |
3222 | struct mwl8k_vif *mwl8k_vif; | |
3223 | ||
3224 | /* | |
3225 | * We only support one active interface at a time. | |
3226 | */ | |
3227 | if (priv->vif != NULL) | |
3228 | return -EBUSY; | |
3229 | ||
a43c49a8 LB |
3230 | /* |
3231 | * Reject interface creation if sniffer mode is active, as | |
3232 | * STA operation is mutually exclusive with hardware sniffer | |
b64fe619 | 3233 | * mode. (Sniffer mode is only used on STA firmware.) |
a43c49a8 LB |
3234 | */ |
3235 | if (priv->sniffer_enabled) { | |
3236 | printk(KERN_INFO "%s: unable to create STA " | |
3237 | "interface due to sniffer mode being enabled\n", | |
3238 | wiphy_name(hw->wiphy)); | |
3239 | return -EINVAL; | |
3240 | } | |
3241 | ||
c2c2b12a LB |
3242 | /* Set the mac address. */ |
3243 | mwl8k_cmd_set_mac_addr(hw, vif->addr); | |
3244 | ||
b64fe619 LB |
3245 | if (priv->ap_fw) |
3246 | mwl8k_cmd_set_new_stn_add_self(hw, vif); | |
3247 | ||
a66098da | 3248 | /* Clean out driver private area */ |
1ed32e4f | 3249 | mwl8k_vif = MWL8K_VIF(vif); |
a66098da LB |
3250 | memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); |
3251 | ||
a66098da LB |
3252 | /* Set Initial sequence number to zero */ |
3253 | mwl8k_vif->seqno = 0; | |
3254 | ||
1ed32e4f | 3255 | priv->vif = vif; |
a66098da LB |
3256 | |
3257 | return 0; | |
3258 | } | |
3259 | ||
3260 | static void mwl8k_remove_interface(struct ieee80211_hw *hw, | |
1ed32e4f | 3261 | struct ieee80211_vif *vif) |
a66098da LB |
3262 | { |
3263 | struct mwl8k_priv *priv = hw->priv; | |
3264 | ||
b64fe619 LB |
3265 | if (priv->ap_fw) |
3266 | mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr); | |
3267 | ||
55489b6e | 3268 | mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
32060e1b | 3269 | |
a66098da LB |
3270 | priv->vif = NULL; |
3271 | } | |
3272 | ||
ee03a932 | 3273 | static int mwl8k_config(struct ieee80211_hw *hw, u32 changed) |
a66098da | 3274 | { |
a66098da LB |
3275 | struct ieee80211_conf *conf = &hw->conf; |
3276 | struct mwl8k_priv *priv = hw->priv; | |
ee03a932 | 3277 | int rc; |
a66098da | 3278 | |
7595d67a | 3279 | if (conf->flags & IEEE80211_CONF_IDLE) { |
55489b6e | 3280 | mwl8k_cmd_radio_disable(hw); |
ee03a932 | 3281 | return 0; |
7595d67a LB |
3282 | } |
3283 | ||
ee03a932 LB |
3284 | rc = mwl8k_fw_lock(hw); |
3285 | if (rc) | |
3286 | return rc; | |
a66098da | 3287 | |
55489b6e | 3288 | rc = mwl8k_cmd_radio_enable(hw); |
ee03a932 LB |
3289 | if (rc) |
3290 | goto out; | |
a66098da | 3291 | |
610677d2 | 3292 | rc = mwl8k_cmd_set_rf_channel(hw, conf); |
ee03a932 LB |
3293 | if (rc) |
3294 | goto out; | |
3295 | ||
a66098da LB |
3296 | if (conf->power_level > 18) |
3297 | conf->power_level = 18; | |
55489b6e | 3298 | rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level); |
ee03a932 LB |
3299 | if (rc) |
3300 | goto out; | |
a66098da | 3301 | |
08b06347 LB |
3302 | if (priv->ap_fw) { |
3303 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7); | |
3304 | if (!rc) | |
3305 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); | |
3306 | } else { | |
3307 | rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); | |
3308 | } | |
a66098da | 3309 | |
ee03a932 LB |
3310 | out: |
3311 | mwl8k_fw_unlock(hw); | |
a66098da | 3312 | |
ee03a932 | 3313 | return rc; |
a66098da LB |
3314 | } |
3315 | ||
b64fe619 LB |
3316 | static void |
3317 | mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3318 | struct ieee80211_bss_conf *info, u32 changed) | |
a66098da | 3319 | { |
a66098da | 3320 | struct mwl8k_priv *priv = hw->priv; |
c3cbbe8a | 3321 | u32 ap_legacy_rates; |
13935e2c | 3322 | u8 ap_mcs_rates[16]; |
3a980d0a LB |
3323 | int rc; |
3324 | ||
c3cbbe8a | 3325 | if (mwl8k_fw_lock(hw)) |
3a980d0a | 3326 | return; |
a66098da | 3327 | |
c3cbbe8a LB |
3328 | /* |
3329 | * No need to capture a beacon if we're no longer associated. | |
3330 | */ | |
3331 | if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc) | |
3332 | priv->capture_beacon = false; | |
3a980d0a | 3333 | |
c3cbbe8a | 3334 | /* |
13935e2c | 3335 | * Get the AP's legacy and MCS rates. |
c3cbbe8a | 3336 | */ |
7dc6a7a7 | 3337 | if (vif->bss_conf.assoc) { |
c6e96010 | 3338 | struct ieee80211_sta *ap; |
c97470dd | 3339 | |
c6e96010 | 3340 | rcu_read_lock(); |
c6e96010 | 3341 | |
c3cbbe8a LB |
3342 | ap = ieee80211_find_sta(vif, vif->bss_conf.bssid); |
3343 | if (ap == NULL) { | |
3344 | rcu_read_unlock(); | |
c6e96010 | 3345 | goto out; |
c3cbbe8a LB |
3346 | } |
3347 | ||
3348 | ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ]; | |
13935e2c | 3349 | memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16); |
c3cbbe8a LB |
3350 | |
3351 | rcu_read_unlock(); | |
3352 | } | |
c6e96010 | 3353 | |
c3cbbe8a | 3354 | if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) { |
13935e2c | 3355 | rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates); |
3a980d0a LB |
3356 | if (rc) |
3357 | goto out; | |
a66098da | 3358 | |
b71ed2c6 | 3359 | rc = mwl8k_cmd_use_fixed_rate_sta(hw); |
3a980d0a LB |
3360 | if (rc) |
3361 | goto out; | |
c3cbbe8a | 3362 | } |
a66098da | 3363 | |
c3cbbe8a | 3364 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
7dc6a7a7 LB |
3365 | rc = mwl8k_set_radio_preamble(hw, |
3366 | vif->bss_conf.use_short_preamble); | |
3a980d0a LB |
3367 | if (rc) |
3368 | goto out; | |
c3cbbe8a | 3369 | } |
a66098da | 3370 | |
c3cbbe8a | 3371 | if (changed & BSS_CHANGED_ERP_SLOT) { |
7dc6a7a7 | 3372 | rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot); |
3a980d0a LB |
3373 | if (rc) |
3374 | goto out; | |
c3cbbe8a | 3375 | } |
a66098da | 3376 | |
c97470dd LB |
3377 | if (vif->bss_conf.assoc && |
3378 | (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT | | |
3379 | BSS_CHANGED_HT))) { | |
c3cbbe8a | 3380 | rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates); |
3a980d0a LB |
3381 | if (rc) |
3382 | goto out; | |
c3cbbe8a | 3383 | } |
a66098da | 3384 | |
c3cbbe8a LB |
3385 | if (vif->bss_conf.assoc && |
3386 | (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) { | |
a66098da LB |
3387 | /* |
3388 | * Finalize the join. Tell rx handler to process | |
3389 | * next beacon from our BSSID. | |
3390 | */ | |
0a11dfc3 | 3391 | memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN); |
a66098da | 3392 | priv->capture_beacon = true; |
a66098da LB |
3393 | } |
3394 | ||
3a980d0a LB |
3395 | out: |
3396 | mwl8k_fw_unlock(hw); | |
a66098da LB |
3397 | } |
3398 | ||
b64fe619 LB |
3399 | static void |
3400 | mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3401 | struct ieee80211_bss_conf *info, u32 changed) | |
3402 | { | |
3403 | int rc; | |
3404 | ||
3405 | if (mwl8k_fw_lock(hw)) | |
3406 | return; | |
3407 | ||
3408 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { | |
3409 | rc = mwl8k_set_radio_preamble(hw, | |
3410 | vif->bss_conf.use_short_preamble); | |
3411 | if (rc) | |
3412 | goto out; | |
3413 | } | |
3414 | ||
3415 | if (changed & BSS_CHANGED_BASIC_RATES) { | |
3416 | int idx; | |
3417 | int rate; | |
3418 | ||
3419 | /* | |
3420 | * Use lowest supported basic rate for multicasts | |
3421 | * and management frames (such as probe responses -- | |
3422 | * beacons will always go out at 1 Mb/s). | |
3423 | */ | |
3424 | idx = ffs(vif->bss_conf.basic_rates); | |
777ad375 | 3425 | rate = idx ? mwl8k_rates_24[idx - 1].hw_value : 2; |
b64fe619 LB |
3426 | |
3427 | mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate); | |
3428 | } | |
3429 | ||
3430 | if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) { | |
3431 | struct sk_buff *skb; | |
3432 | ||
3433 | skb = ieee80211_beacon_get(hw, vif); | |
3434 | if (skb != NULL) { | |
3435 | mwl8k_cmd_set_beacon(hw, skb->data, skb->len); | |
3436 | kfree_skb(skb); | |
3437 | } | |
3438 | } | |
3439 | ||
3440 | if (changed & BSS_CHANGED_BEACON_ENABLED) | |
3441 | mwl8k_cmd_bss_start(hw, info->enable_beacon); | |
3442 | ||
3443 | out: | |
3444 | mwl8k_fw_unlock(hw); | |
3445 | } | |
3446 | ||
3447 | static void | |
3448 | mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3449 | struct ieee80211_bss_conf *info, u32 changed) | |
3450 | { | |
3451 | struct mwl8k_priv *priv = hw->priv; | |
3452 | ||
3453 | if (!priv->ap_fw) | |
3454 | mwl8k_bss_info_changed_sta(hw, vif, info, changed); | |
3455 | else | |
3456 | mwl8k_bss_info_changed_ap(hw, vif, info, changed); | |
3457 | } | |
3458 | ||
e81cd2d6 LB |
3459 | static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw, |
3460 | int mc_count, struct dev_addr_list *mclist) | |
3461 | { | |
3462 | struct mwl8k_cmd_pkt *cmd; | |
3463 | ||
447ced07 LB |
3464 | /* |
3465 | * Synthesize and return a command packet that programs the | |
3466 | * hardware multicast address filter. At this point we don't | |
3467 | * know whether FIF_ALLMULTI is being requested, but if it is, | |
3468 | * we'll end up throwing this packet away and creating a new | |
3469 | * one in mwl8k_configure_filter(). | |
3470 | */ | |
3471 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist); | |
e81cd2d6 LB |
3472 | |
3473 | return (unsigned long)cmd; | |
3474 | } | |
3475 | ||
a43c49a8 LB |
3476 | static int |
3477 | mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw, | |
3478 | unsigned int changed_flags, | |
3479 | unsigned int *total_flags) | |
3480 | { | |
3481 | struct mwl8k_priv *priv = hw->priv; | |
3482 | ||
3483 | /* | |
3484 | * Hardware sniffer mode is mutually exclusive with STA | |
3485 | * operation, so refuse to enable sniffer mode if a STA | |
3486 | * interface is active. | |
3487 | */ | |
3488 | if (priv->vif != NULL) { | |
3489 | if (net_ratelimit()) | |
3490 | printk(KERN_INFO "%s: not enabling sniffer " | |
3491 | "mode because STA interface is active\n", | |
3492 | wiphy_name(hw->wiphy)); | |
3493 | return 0; | |
3494 | } | |
3495 | ||
3496 | if (!priv->sniffer_enabled) { | |
55489b6e | 3497 | if (mwl8k_cmd_enable_sniffer(hw, 1)) |
a43c49a8 LB |
3498 | return 0; |
3499 | priv->sniffer_enabled = true; | |
3500 | } | |
3501 | ||
3502 | *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI | | |
3503 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | | |
3504 | FIF_OTHER_BSS; | |
3505 | ||
3506 | return 1; | |
3507 | } | |
3508 | ||
e6935ea1 LB |
3509 | static void mwl8k_configure_filter(struct ieee80211_hw *hw, |
3510 | unsigned int changed_flags, | |
3511 | unsigned int *total_flags, | |
3512 | u64 multicast) | |
3513 | { | |
3514 | struct mwl8k_priv *priv = hw->priv; | |
a43c49a8 LB |
3515 | struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast; |
3516 | ||
c0adae2c LB |
3517 | /* |
3518 | * AP firmware doesn't allow fine-grained control over | |
3519 | * the receive filter. | |
3520 | */ | |
3521 | if (priv->ap_fw) { | |
3522 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; | |
3523 | kfree(cmd); | |
3524 | return; | |
3525 | } | |
3526 | ||
a43c49a8 LB |
3527 | /* |
3528 | * Enable hardware sniffer mode if FIF_CONTROL or | |
3529 | * FIF_OTHER_BSS is requested. | |
3530 | */ | |
3531 | if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) && | |
3532 | mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) { | |
3533 | kfree(cmd); | |
3534 | return; | |
3535 | } | |
a66098da | 3536 | |
e6935ea1 | 3537 | /* Clear unsupported feature flags */ |
447ced07 | 3538 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; |
a66098da | 3539 | |
90852f7a LB |
3540 | if (mwl8k_fw_lock(hw)) { |
3541 | kfree(cmd); | |
e6935ea1 | 3542 | return; |
90852f7a | 3543 | } |
a66098da | 3544 | |
a43c49a8 | 3545 | if (priv->sniffer_enabled) { |
55489b6e | 3546 | mwl8k_cmd_enable_sniffer(hw, 0); |
a43c49a8 LB |
3547 | priv->sniffer_enabled = false; |
3548 | } | |
3549 | ||
e6935ea1 | 3550 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
77165d88 LB |
3551 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { |
3552 | /* | |
3553 | * Disable the BSS filter. | |
3554 | */ | |
e6935ea1 | 3555 | mwl8k_cmd_set_pre_scan(hw); |
77165d88 | 3556 | } else { |
0a11dfc3 | 3557 | const u8 *bssid; |
a94cc97e | 3558 | |
77165d88 LB |
3559 | /* |
3560 | * Enable the BSS filter. | |
3561 | * | |
3562 | * If there is an active STA interface, use that | |
3563 | * interface's BSSID, otherwise use a dummy one | |
3564 | * (where the OUI part needs to be nonzero for | |
3565 | * the BSSID to be accepted by POST_SCAN). | |
3566 | */ | |
3567 | bssid = "\x01\x00\x00\x00\x00\x00"; | |
a94cc97e | 3568 | if (priv->vif != NULL) |
0a11dfc3 | 3569 | bssid = priv->vif->bss_conf.bssid; |
a94cc97e | 3570 | |
e6935ea1 | 3571 | mwl8k_cmd_set_post_scan(hw, bssid); |
a66098da LB |
3572 | } |
3573 | } | |
3574 | ||
447ced07 LB |
3575 | /* |
3576 | * If FIF_ALLMULTI is being requested, throw away the command | |
3577 | * packet that ->prepare_multicast() built and replace it with | |
3578 | * a command packet that enables reception of all multicast | |
3579 | * packets. | |
3580 | */ | |
3581 | if (*total_flags & FIF_ALLMULTI) { | |
3582 | kfree(cmd); | |
3583 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL); | |
3584 | } | |
3585 | ||
3586 | if (cmd != NULL) { | |
3587 | mwl8k_post_cmd(hw, cmd); | |
3588 | kfree(cmd); | |
e6935ea1 | 3589 | } |
a66098da | 3590 | |
e6935ea1 | 3591 | mwl8k_fw_unlock(hw); |
a66098da LB |
3592 | } |
3593 | ||
a66098da LB |
3594 | static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
3595 | { | |
c2c2b12a | 3596 | return mwl8k_cmd_set_rts_threshold(hw, value); |
a66098da LB |
3597 | } |
3598 | ||
bbfd9128 LB |
3599 | struct mwl8k_sta_notify_item |
3600 | { | |
3601 | struct list_head list; | |
3602 | struct ieee80211_vif *vif; | |
3603 | enum sta_notify_cmd cmd; | |
13935e2c | 3604 | struct ieee80211_sta sta; |
bbfd9128 LB |
3605 | }; |
3606 | ||
3f5610ff LB |
3607 | static void |
3608 | mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s) | |
3609 | { | |
3610 | struct mwl8k_priv *priv = hw->priv; | |
3611 | ||
3612 | /* | |
3613 | * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN. | |
3614 | */ | |
3615 | if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) { | |
3616 | int rc; | |
3617 | ||
3618 | rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta); | |
3619 | if (rc >= 0) { | |
3620 | struct ieee80211_sta *sta; | |
3621 | ||
3622 | rcu_read_lock(); | |
3623 | sta = ieee80211_find_sta(s->vif, s->sta.addr); | |
3624 | if (sta != NULL) | |
3625 | MWL8K_STA(sta)->peer_id = rc; | |
3626 | rcu_read_unlock(); | |
3627 | } | |
3628 | } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) { | |
3629 | mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr); | |
3630 | } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) { | |
3631 | mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta); | |
3632 | } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) { | |
3633 | mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr); | |
3634 | } | |
3635 | } | |
3636 | ||
bbfd9128 LB |
3637 | static void mwl8k_sta_notify_worker(struct work_struct *work) |
3638 | { | |
3639 | struct mwl8k_priv *priv = | |
3640 | container_of(work, struct mwl8k_priv, sta_notify_worker); | |
a680400e | 3641 | struct ieee80211_hw *hw = priv->hw; |
bbfd9128 LB |
3642 | |
3643 | spin_lock_bh(&priv->sta_notify_list_lock); | |
3644 | while (!list_empty(&priv->sta_notify_list)) { | |
3645 | struct mwl8k_sta_notify_item *s; | |
bbfd9128 LB |
3646 | |
3647 | s = list_entry(priv->sta_notify_list.next, | |
3648 | struct mwl8k_sta_notify_item, list); | |
3649 | list_del(&s->list); | |
3650 | ||
3651 | spin_unlock_bh(&priv->sta_notify_list_lock); | |
3652 | ||
3f5610ff | 3653 | mwl8k_do_sta_notify(hw, s); |
bbfd9128 LB |
3654 | kfree(s); |
3655 | ||
3656 | spin_lock_bh(&priv->sta_notify_list_lock); | |
3657 | } | |
3658 | spin_unlock_bh(&priv->sta_notify_list_lock); | |
3659 | } | |
3660 | ||
3661 | static void | |
3662 | mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3663 | enum sta_notify_cmd cmd, struct ieee80211_sta *sta) | |
3664 | { | |
3665 | struct mwl8k_priv *priv = hw->priv; | |
3666 | struct mwl8k_sta_notify_item *s; | |
3667 | ||
3668 | if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE) | |
3669 | return; | |
3670 | ||
3671 | s = kmalloc(sizeof(*s), GFP_ATOMIC); | |
3672 | if (s != NULL) { | |
3673 | s->vif = vif; | |
3674 | s->cmd = cmd; | |
13935e2c | 3675 | s->sta = *sta; |
bbfd9128 LB |
3676 | |
3677 | spin_lock(&priv->sta_notify_list_lock); | |
3678 | list_add_tail(&s->list, &priv->sta_notify_list); | |
3679 | spin_unlock(&priv->sta_notify_list_lock); | |
3680 | ||
3681 | ieee80211_queue_work(hw, &priv->sta_notify_worker); | |
3682 | } | |
3683 | } | |
3684 | ||
a66098da LB |
3685 | static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
3686 | const struct ieee80211_tx_queue_params *params) | |
3687 | { | |
3e4f542c | 3688 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 3689 | int rc; |
a66098da | 3690 | |
3e4f542c LB |
3691 | rc = mwl8k_fw_lock(hw); |
3692 | if (!rc) { | |
3693 | if (!priv->wmm_enabled) | |
55489b6e | 3694 | rc = mwl8k_cmd_set_wmm_mode(hw, 1); |
a66098da | 3695 | |
3e4f542c | 3696 | if (!rc) |
55489b6e LB |
3697 | rc = mwl8k_cmd_set_edca_params(hw, queue, |
3698 | params->cw_min, | |
3699 | params->cw_max, | |
3700 | params->aifs, | |
3701 | params->txop); | |
3e4f542c LB |
3702 | |
3703 | mwl8k_fw_unlock(hw); | |
a66098da | 3704 | } |
3e4f542c | 3705 | |
a66098da LB |
3706 | return rc; |
3707 | } | |
3708 | ||
3709 | static int mwl8k_get_tx_stats(struct ieee80211_hw *hw, | |
3710 | struct ieee80211_tx_queue_stats *stats) | |
3711 | { | |
3712 | struct mwl8k_priv *priv = hw->priv; | |
3713 | struct mwl8k_tx_queue *txq; | |
3714 | int index; | |
3715 | ||
3716 | spin_lock_bh(&priv->tx_lock); | |
3717 | for (index = 0; index < MWL8K_TX_QUEUES; index++) { | |
3718 | txq = priv->txq + index; | |
45eb400d | 3719 | memcpy(&stats[index], &txq->stats, |
a66098da LB |
3720 | sizeof(struct ieee80211_tx_queue_stats)); |
3721 | } | |
3722 | spin_unlock_bh(&priv->tx_lock); | |
a66098da | 3723 | |
954ef509 | 3724 | return 0; |
a66098da LB |
3725 | } |
3726 | ||
3727 | static int mwl8k_get_stats(struct ieee80211_hw *hw, | |
3728 | struct ieee80211_low_level_stats *stats) | |
3729 | { | |
55489b6e | 3730 | return mwl8k_cmd_get_stat(hw, stats); |
a66098da LB |
3731 | } |
3732 | ||
a2292d83 LB |
3733 | static int |
3734 | mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3735 | enum ieee80211_ampdu_mlme_action action, | |
3736 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) | |
3737 | { | |
3738 | switch (action) { | |
3739 | case IEEE80211_AMPDU_RX_START: | |
3740 | case IEEE80211_AMPDU_RX_STOP: | |
3741 | if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION)) | |
3742 | return -ENOTSUPP; | |
3743 | return 0; | |
3744 | default: | |
3745 | return -ENOTSUPP; | |
3746 | } | |
3747 | } | |
3748 | ||
a66098da LB |
3749 | static const struct ieee80211_ops mwl8k_ops = { |
3750 | .tx = mwl8k_tx, | |
3751 | .start = mwl8k_start, | |
3752 | .stop = mwl8k_stop, | |
3753 | .add_interface = mwl8k_add_interface, | |
3754 | .remove_interface = mwl8k_remove_interface, | |
3755 | .config = mwl8k_config, | |
a66098da | 3756 | .bss_info_changed = mwl8k_bss_info_changed, |
3ac64bee | 3757 | .prepare_multicast = mwl8k_prepare_multicast, |
a66098da LB |
3758 | .configure_filter = mwl8k_configure_filter, |
3759 | .set_rts_threshold = mwl8k_set_rts_threshold, | |
bbfd9128 | 3760 | .sta_notify = mwl8k_sta_notify, |
a66098da LB |
3761 | .conf_tx = mwl8k_conf_tx, |
3762 | .get_tx_stats = mwl8k_get_tx_stats, | |
3763 | .get_stats = mwl8k_get_stats, | |
a2292d83 | 3764 | .ampdu_action = mwl8k_ampdu_action, |
a66098da LB |
3765 | }; |
3766 | ||
a66098da LB |
3767 | static void mwl8k_finalize_join_worker(struct work_struct *work) |
3768 | { | |
3769 | struct mwl8k_priv *priv = | |
3770 | container_of(work, struct mwl8k_priv, finalize_join_worker); | |
3771 | struct sk_buff *skb = priv->beacon_skb; | |
a66098da | 3772 | |
7dc6a7a7 LB |
3773 | mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, |
3774 | priv->vif->bss_conf.dtim_period); | |
a66098da LB |
3775 | dev_kfree_skb(skb); |
3776 | ||
3777 | priv->beacon_skb = NULL; | |
3778 | } | |
3779 | ||
bcb628d5 | 3780 | enum { |
9e1b17ea LB |
3781 | MWL8363 = 0, |
3782 | MWL8687, | |
bcb628d5 | 3783 | MWL8366, |
6f6d1e9a LB |
3784 | }; |
3785 | ||
bcb628d5 | 3786 | static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = { |
9e1b17ea LB |
3787 | [MWL8363] = { |
3788 | .part_name = "88w8363", | |
3789 | .helper_image = "mwl8k/helper_8363.fw", | |
3790 | .fw_image = "mwl8k/fmimage_8363.fw", | |
3791 | }, | |
49eb691c | 3792 | [MWL8687] = { |
bcb628d5 JL |
3793 | .part_name = "88w8687", |
3794 | .helper_image = "mwl8k/helper_8687.fw", | |
3795 | .fw_image = "mwl8k/fmimage_8687.fw", | |
bcb628d5 | 3796 | }, |
49eb691c | 3797 | [MWL8366] = { |
bcb628d5 JL |
3798 | .part_name = "88w8366", |
3799 | .helper_image = "mwl8k/helper_8366.fw", | |
3800 | .fw_image = "mwl8k/fmimage_8366.fw", | |
89a91f4f | 3801 | .ap_rxd_ops = &rxd_8366_ap_ops, |
bcb628d5 | 3802 | }, |
45a390dd LB |
3803 | }; |
3804 | ||
c92d4ede LB |
3805 | MODULE_FIRMWARE("mwl8k/helper_8363.fw"); |
3806 | MODULE_FIRMWARE("mwl8k/fmimage_8363.fw"); | |
3807 | MODULE_FIRMWARE("mwl8k/helper_8687.fw"); | |
3808 | MODULE_FIRMWARE("mwl8k/fmimage_8687.fw"); | |
3809 | MODULE_FIRMWARE("mwl8k/helper_8366.fw"); | |
3810 | MODULE_FIRMWARE("mwl8k/fmimage_8366.fw"); | |
3811 | ||
45a390dd | 3812 | static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = { |
9e1b17ea LB |
3813 | { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, }, |
3814 | { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, }, | |
bcb628d5 JL |
3815 | { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, }, |
3816 | { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, }, | |
3817 | { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, }, | |
ca66527c | 3818 | { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, }, |
bcb628d5 | 3819 | { }, |
45a390dd LB |
3820 | }; |
3821 | MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table); | |
3822 | ||
a66098da LB |
3823 | static int __devinit mwl8k_probe(struct pci_dev *pdev, |
3824 | const struct pci_device_id *id) | |
3825 | { | |
2aa7b01f | 3826 | static int printed_version = 0; |
a66098da LB |
3827 | struct ieee80211_hw *hw; |
3828 | struct mwl8k_priv *priv; | |
a66098da LB |
3829 | int rc; |
3830 | int i; | |
2aa7b01f LB |
3831 | |
3832 | if (!printed_version) { | |
3833 | printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION); | |
3834 | printed_version = 1; | |
3835 | } | |
a66098da | 3836 | |
be695fc4 | 3837 | |
a66098da LB |
3838 | rc = pci_enable_device(pdev); |
3839 | if (rc) { | |
3840 | printk(KERN_ERR "%s: Cannot enable new PCI device\n", | |
3841 | MWL8K_NAME); | |
3842 | return rc; | |
3843 | } | |
3844 | ||
3845 | rc = pci_request_regions(pdev, MWL8K_NAME); | |
3846 | if (rc) { | |
3847 | printk(KERN_ERR "%s: Cannot obtain PCI resources\n", | |
3848 | MWL8K_NAME); | |
3db95e50 | 3849 | goto err_disable_device; |
a66098da LB |
3850 | } |
3851 | ||
3852 | pci_set_master(pdev); | |
3853 | ||
be695fc4 | 3854 | |
a66098da LB |
3855 | hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops); |
3856 | if (hw == NULL) { | |
3857 | printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME); | |
3858 | rc = -ENOMEM; | |
3859 | goto err_free_reg; | |
3860 | } | |
3861 | ||
be695fc4 LB |
3862 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3863 | pci_set_drvdata(pdev, hw); | |
3864 | ||
a66098da LB |
3865 | priv = hw->priv; |
3866 | priv->hw = hw; | |
3867 | priv->pdev = pdev; | |
bcb628d5 | 3868 | priv->device_info = &mwl8k_info_tbl[id->driver_data]; |
a66098da | 3869 | |
a66098da | 3870 | |
5b9482dd LB |
3871 | priv->sram = pci_iomap(pdev, 0, 0x10000); |
3872 | if (priv->sram == NULL) { | |
3873 | printk(KERN_ERR "%s: Cannot map device SRAM\n", | |
c2c357ce | 3874 | wiphy_name(hw->wiphy)); |
a66098da LB |
3875 | goto err_iounmap; |
3876 | } | |
3877 | ||
5b9482dd LB |
3878 | /* |
3879 | * If BAR0 is a 32 bit BAR, the register BAR will be BAR1. | |
3880 | * If BAR0 is a 64 bit BAR, the register BAR will be BAR2. | |
3881 | */ | |
3882 | priv->regs = pci_iomap(pdev, 1, 0x10000); | |
3883 | if (priv->regs == NULL) { | |
3884 | priv->regs = pci_iomap(pdev, 2, 0x10000); | |
3885 | if (priv->regs == NULL) { | |
3886 | printk(KERN_ERR "%s: Cannot map device registers\n", | |
3887 | wiphy_name(hw->wiphy)); | |
3888 | goto err_iounmap; | |
3889 | } | |
3890 | } | |
3891 | ||
be695fc4 LB |
3892 | |
3893 | /* Reset firmware and hardware */ | |
3894 | mwl8k_hw_reset(priv); | |
3895 | ||
3896 | /* Ask userland hotplug daemon for the device firmware */ | |
3897 | rc = mwl8k_request_firmware(priv); | |
3898 | if (rc) { | |
3899 | printk(KERN_ERR "%s: Firmware files not found\n", | |
3900 | wiphy_name(hw->wiphy)); | |
3901 | goto err_stop_firmware; | |
3902 | } | |
3903 | ||
3904 | /* Load firmware into hardware */ | |
3905 | rc = mwl8k_load_firmware(hw); | |
3906 | if (rc) { | |
3907 | printk(KERN_ERR "%s: Cannot start firmware\n", | |
3908 | wiphy_name(hw->wiphy)); | |
3909 | goto err_stop_firmware; | |
3910 | } | |
3911 | ||
3912 | /* Reclaim memory once firmware is successfully loaded */ | |
3913 | mwl8k_release_firmware(priv); | |
3914 | ||
3915 | ||
91942230 | 3916 | if (priv->ap_fw) { |
89a91f4f | 3917 | priv->rxd_ops = priv->device_info->ap_rxd_ops; |
91942230 LB |
3918 | if (priv->rxd_ops == NULL) { |
3919 | printk(KERN_ERR "%s: Driver does not have AP " | |
3920 | "firmware image support for this hardware\n", | |
3921 | wiphy_name(hw->wiphy)); | |
3922 | goto err_stop_firmware; | |
3923 | } | |
3924 | } else { | |
89a91f4f | 3925 | priv->rxd_ops = &rxd_sta_ops; |
91942230 | 3926 | } |
be695fc4 LB |
3927 | |
3928 | priv->sniffer_enabled = false; | |
3929 | priv->wmm_enabled = false; | |
3930 | priv->pending_tx_pkts = 0; | |
3931 | ||
3932 | ||
a66098da LB |
3933 | /* |
3934 | * Extra headroom is the size of the required DMA header | |
3935 | * minus the size of the smallest 802.11 frame (CTS frame). | |
3936 | */ | |
3937 | hw->extra_tx_headroom = | |
3938 | sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts); | |
3939 | ||
3940 | hw->channel_change_time = 10; | |
3941 | ||
3942 | hw->queues = MWL8K_TX_QUEUES; | |
3943 | ||
a66098da | 3944 | /* Set rssi and noise values to dBm */ |
ce9e2e1b | 3945 | hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; |
a66098da | 3946 | hw->vif_data_size = sizeof(struct mwl8k_vif); |
a680400e | 3947 | hw->sta_data_size = sizeof(struct mwl8k_sta); |
a66098da LB |
3948 | priv->vif = NULL; |
3949 | ||
3950 | /* Set default radio state and preamble */ | |
c46563b7 | 3951 | priv->radio_on = 0; |
68ce3884 | 3952 | priv->radio_short_preamble = 0; |
a66098da | 3953 | |
bbfd9128 LB |
3954 | /* Station database handling */ |
3955 | INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker); | |
3956 | spin_lock_init(&priv->sta_notify_list_lock); | |
3957 | INIT_LIST_HEAD(&priv->sta_notify_list); | |
3958 | ||
a66098da LB |
3959 | /* Finalize join worker */ |
3960 | INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker); | |
3961 | ||
67e2eb27 | 3962 | /* TX reclaim and RX tasklets. */ |
1e9f9de3 LB |
3963 | tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw); |
3964 | tasklet_disable(&priv->poll_tx_task); | |
67e2eb27 LB |
3965 | tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw); |
3966 | tasklet_disable(&priv->poll_rx_task); | |
a66098da | 3967 | |
a66098da LB |
3968 | /* Power management cookie */ |
3969 | priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); | |
3970 | if (priv->cookie == NULL) | |
be695fc4 | 3971 | goto err_stop_firmware; |
a66098da LB |
3972 | |
3973 | rc = mwl8k_rxq_init(hw, 0); | |
3974 | if (rc) | |
be695fc4 | 3975 | goto err_free_cookie; |
a66098da LB |
3976 | rxq_refill(hw, 0, INT_MAX); |
3977 | ||
618952a7 LB |
3978 | mutex_init(&priv->fw_mutex); |
3979 | priv->fw_mutex_owner = NULL; | |
3980 | priv->fw_mutex_depth = 0; | |
618952a7 LB |
3981 | priv->hostcmd_wait = NULL; |
3982 | ||
a66098da LB |
3983 | spin_lock_init(&priv->tx_lock); |
3984 | ||
88de754a LB |
3985 | priv->tx_wait = NULL; |
3986 | ||
a66098da LB |
3987 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { |
3988 | rc = mwl8k_txq_init(hw, i); | |
3989 | if (rc) | |
3990 | goto err_free_queues; | |
3991 | } | |
3992 | ||
3993 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
c23b5a69 | 3994 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
67e2eb27 | 3995 | iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY, |
1e9f9de3 | 3996 | priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL); |
a66098da LB |
3997 | iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK); |
3998 | ||
a0607fd3 | 3999 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
4000 | IRQF_SHARED, MWL8K_NAME, hw); |
4001 | if (rc) { | |
4002 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 4003 | wiphy_name(hw->wiphy)); |
a66098da LB |
4004 | goto err_free_queues; |
4005 | } | |
4006 | ||
a66098da LB |
4007 | /* |
4008 | * Temporarily enable interrupts. Initial firmware host | |
c2c2b12a | 4009 | * commands use interrupts and avoid polling. Disable |
a66098da LB |
4010 | * interrupts when done. |
4011 | */ | |
c23b5a69 | 4012 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
4013 | |
4014 | /* Get config data, mac addrs etc */ | |
42fba21d LB |
4015 | if (priv->ap_fw) { |
4016 | rc = mwl8k_cmd_get_hw_spec_ap(hw); | |
4017 | if (!rc) | |
4018 | rc = mwl8k_cmd_set_hw_spec(hw); | |
b64fe619 LB |
4019 | |
4020 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP); | |
42fba21d LB |
4021 | } else { |
4022 | rc = mwl8k_cmd_get_hw_spec_sta(hw); | |
89a91f4f LB |
4023 | |
4024 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
42fba21d | 4025 | } |
a66098da | 4026 | if (rc) { |
c2c357ce LB |
4027 | printk(KERN_ERR "%s: Cannot initialise firmware\n", |
4028 | wiphy_name(hw->wiphy)); | |
be695fc4 | 4029 | goto err_free_irq; |
a66098da LB |
4030 | } |
4031 | ||
4032 | /* Turn radio off */ | |
55489b6e | 4033 | rc = mwl8k_cmd_radio_disable(hw); |
a66098da | 4034 | if (rc) { |
c2c357ce | 4035 | printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy)); |
be695fc4 | 4036 | goto err_free_irq; |
a66098da LB |
4037 | } |
4038 | ||
32060e1b | 4039 | /* Clear MAC address */ |
55489b6e | 4040 | rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
32060e1b LB |
4041 | if (rc) { |
4042 | printk(KERN_ERR "%s: Cannot clear MAC address\n", | |
4043 | wiphy_name(hw->wiphy)); | |
be695fc4 | 4044 | goto err_free_irq; |
32060e1b LB |
4045 | } |
4046 | ||
a66098da | 4047 | /* Disable interrupts */ |
a66098da | 4048 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
4049 | free_irq(priv->pdev->irq, hw); |
4050 | ||
4051 | rc = ieee80211_register_hw(hw); | |
4052 | if (rc) { | |
c2c357ce LB |
4053 | printk(KERN_ERR "%s: Cannot register device\n", |
4054 | wiphy_name(hw->wiphy)); | |
153458ff | 4055 | goto err_free_queues; |
a66098da LB |
4056 | } |
4057 | ||
eae74e65 | 4058 | printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n", |
a74b295e | 4059 | wiphy_name(hw->wiphy), priv->device_info->part_name, |
45a390dd | 4060 | priv->hw_rev, hw->wiphy->perm_addr, |
eae74e65 | 4061 | priv->ap_fw ? "AP" : "STA", |
2aa7b01f LB |
4062 | (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, |
4063 | (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); | |
a66098da LB |
4064 | |
4065 | return 0; | |
4066 | ||
a66098da | 4067 | err_free_irq: |
a66098da | 4068 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
4069 | free_irq(priv->pdev->irq, hw); |
4070 | ||
4071 | err_free_queues: | |
4072 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
4073 | mwl8k_txq_deinit(hw, i); | |
4074 | mwl8k_rxq_deinit(hw, 0); | |
4075 | ||
be695fc4 | 4076 | err_free_cookie: |
a66098da LB |
4077 | if (priv->cookie != NULL) |
4078 | pci_free_consistent(priv->pdev, 4, | |
4079 | priv->cookie, priv->cookie_dma); | |
4080 | ||
be695fc4 LB |
4081 | err_stop_firmware: |
4082 | mwl8k_hw_reset(priv); | |
4083 | mwl8k_release_firmware(priv); | |
4084 | ||
4085 | err_iounmap: | |
a66098da LB |
4086 | if (priv->regs != NULL) |
4087 | pci_iounmap(pdev, priv->regs); | |
4088 | ||
5b9482dd LB |
4089 | if (priv->sram != NULL) |
4090 | pci_iounmap(pdev, priv->sram); | |
4091 | ||
a66098da LB |
4092 | pci_set_drvdata(pdev, NULL); |
4093 | ieee80211_free_hw(hw); | |
4094 | ||
4095 | err_free_reg: | |
4096 | pci_release_regions(pdev); | |
3db95e50 LB |
4097 | |
4098 | err_disable_device: | |
a66098da LB |
4099 | pci_disable_device(pdev); |
4100 | ||
4101 | return rc; | |
4102 | } | |
4103 | ||
230f7af0 | 4104 | static void __devexit mwl8k_shutdown(struct pci_dev *pdev) |
a66098da LB |
4105 | { |
4106 | printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__); | |
4107 | } | |
4108 | ||
230f7af0 | 4109 | static void __devexit mwl8k_remove(struct pci_dev *pdev) |
a66098da LB |
4110 | { |
4111 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
4112 | struct mwl8k_priv *priv; | |
4113 | int i; | |
4114 | ||
4115 | if (hw == NULL) | |
4116 | return; | |
4117 | priv = hw->priv; | |
4118 | ||
4119 | ieee80211_stop_queues(hw); | |
4120 | ||
60aa569f LB |
4121 | ieee80211_unregister_hw(hw); |
4122 | ||
67e2eb27 | 4123 | /* Remove TX reclaim and RX tasklets. */ |
1e9f9de3 | 4124 | tasklet_kill(&priv->poll_tx_task); |
67e2eb27 | 4125 | tasklet_kill(&priv->poll_rx_task); |
a66098da | 4126 | |
a66098da LB |
4127 | /* Stop hardware */ |
4128 | mwl8k_hw_reset(priv); | |
4129 | ||
4130 | /* Return all skbs to mac80211 */ | |
4131 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
efb7c49a | 4132 | mwl8k_txq_reclaim(hw, i, INT_MAX, 1); |
a66098da | 4133 | |
a66098da LB |
4134 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
4135 | mwl8k_txq_deinit(hw, i); | |
4136 | ||
4137 | mwl8k_rxq_deinit(hw, 0); | |
4138 | ||
c2c357ce | 4139 | pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma); |
a66098da LB |
4140 | |
4141 | pci_iounmap(pdev, priv->regs); | |
5b9482dd | 4142 | pci_iounmap(pdev, priv->sram); |
a66098da LB |
4143 | pci_set_drvdata(pdev, NULL); |
4144 | ieee80211_free_hw(hw); | |
4145 | pci_release_regions(pdev); | |
4146 | pci_disable_device(pdev); | |
4147 | } | |
4148 | ||
4149 | static struct pci_driver mwl8k_driver = { | |
4150 | .name = MWL8K_NAME, | |
45a390dd | 4151 | .id_table = mwl8k_pci_id_table, |
a66098da LB |
4152 | .probe = mwl8k_probe, |
4153 | .remove = __devexit_p(mwl8k_remove), | |
4154 | .shutdown = __devexit_p(mwl8k_shutdown), | |
4155 | }; | |
4156 | ||
4157 | static int __init mwl8k_init(void) | |
4158 | { | |
4159 | return pci_register_driver(&mwl8k_driver); | |
4160 | } | |
4161 | ||
4162 | static void __exit mwl8k_exit(void) | |
4163 | { | |
4164 | pci_unregister_driver(&mwl8k_driver); | |
4165 | } | |
4166 | ||
4167 | module_init(mwl8k_init); | |
4168 | module_exit(mwl8k_exit); | |
c2c357ce LB |
4169 | |
4170 | MODULE_DESCRIPTION(MWL8K_DESC); | |
4171 | MODULE_VERSION(MWL8K_VERSION); | |
4172 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>"); | |
4173 | MODULE_LICENSE("GPL"); |