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mwl8k: handle 5 GHz legacy rate bitmaps in firmware commands
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
45a390dd
LB		 132 struct mwl8k_device_info *device_info;
133
be695fc4
LB		 134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
22be40d9
LB		 138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
be695fc4
LB		 141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
777ad375
LB		 144 struct ieee80211_supported_band band_24;
145 struct ieee80211_channel channels_24[14];
146 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 147 struct ieee80211_supported_band band_50;
148 struct ieee80211_channel channels_50[4];
149 struct ieee80211_rate rates_50[9];
be695fc4 150
618952a7
LB		 151 /* firmware access */
152 struct mutex fw_mutex;
153 struct task_struct *fw_mutex_owner;
154 int fw_mutex_depth;
618952a7
LB		 155 struct completion *hostcmd_wait;
156
a66098da
LB		 157 /* lock held over TX and TX reap */
158 spinlock_t tx_lock;
a66098da 159
88de754a
LB		 160 /* TX quiesce completion, protected by fw_mutex and tx_lock */
161 struct completion *tx_wait;
162
a66098da 163 struct ieee80211_vif *vif;
a66098da 164
a66098da
LB		 165 /* power management status cookie from firmware */
166 u32 *cookie;
167 dma_addr_t cookie_dma;
168
169 u16 num_mcaddrs;
a66098da 170 u8 hw_rev;
2aa7b01f 171 u32 fw_rev;
a66098da
LB		 172
173 /*
174 * Running count of TX packets in flight, to avoid
175 * iterating over the transmit rings each time.
176 */
177 int pending_tx_pkts;
178
179 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
180 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
181
c46563b7 182 bool radio_on;
68ce3884 183 bool radio_short_preamble;
a43c49a8 184 bool sniffer_enabled;
0439b1f5 185 bool wmm_enabled;
a66098da 186
bbfd9128
LB		 187 struct work_struct sta_notify_worker;
188 spinlock_t sta_notify_list_lock;
189 struct list_head sta_notify_list;
190
a66098da
LB		 191 /* XXX need to convert this to handle multiple interfaces */
192 bool capture_beacon;
d89173f2 193 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 194 struct sk_buff *beacon_skb;
195
196 /*
197 * This FJ worker has to be global as it is scheduled from the
198 * RX handler. At this point we don't know which interface it
199 * belongs to until the list of bssids waiting to complete join
200 * is checked.
201 */
202 struct work_struct finalize_join_worker;
203
1e9f9de3
LB		 204 /* Tasklet to perform TX reclaim. */
205 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 206
207 /* Tasklet to perform RX. */
208 struct tasklet_struct poll_rx_task;
a66098da
LB		 209};
210
211/* Per interface specific private data */
212struct mwl8k_vif {
c2c2b12a 213 /* Non AMPDU sequence number assigned by driver. */
a680400e 214 u16 seqno;
a66098da 215};
a94cc97e 216#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 217
a680400e
LB		 218struct mwl8k_sta {
219 /* Index into station database. Returned by UPDATE_STADB. */
220 u8 peer_id;
221};
222#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
223
777ad375 224static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB		 225 { .center_freq = 2412, .hw_value = 1, },
226 { .center_freq = 2417, .hw_value = 2, },
227 { .center_freq = 2422, .hw_value = 3, },
228 { .center_freq = 2427, .hw_value = 4, },
229 { .center_freq = 2432, .hw_value = 5, },
230 { .center_freq = 2437, .hw_value = 6, },
231 { .center_freq = 2442, .hw_value = 7, },
232 { .center_freq = 2447, .hw_value = 8, },
233 { .center_freq = 2452, .hw_value = 9, },
234 { .center_freq = 2457, .hw_value = 10, },
235 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 236 { .center_freq = 2467, .hw_value = 12, },
237 { .center_freq = 2472, .hw_value = 13, },
238 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 239};
240
777ad375 241static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 242 { .bitrate = 10, .hw_value = 2, },
243 { .bitrate = 20, .hw_value = 4, },
244 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 245 { .bitrate = 110, .hw_value = 22, },
246 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 247 { .bitrate = 60, .hw_value = 12, },
248 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 249 { .bitrate = 120, .hw_value = 24, },
250 { .bitrate = 180, .hw_value = 36, },
251 { .bitrate = 240, .hw_value = 48, },
252 { .bitrate = 360, .hw_value = 72, },
253 { .bitrate = 480, .hw_value = 96, },
254 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 255 { .bitrate = 720, .hw_value = 144, },
256};
257
4eae9edd
LB		 258static const struct ieee80211_channel mwl8k_channels_50[] = {
259 { .center_freq = 5180, .hw_value = 36, },
260 { .center_freq = 5200, .hw_value = 40, },
261 { .center_freq = 5220, .hw_value = 44, },
262 { .center_freq = 5240, .hw_value = 48, },
263};
264
265static const struct ieee80211_rate mwl8k_rates_50[] = {
266 { .bitrate = 60, .hw_value = 12, },
267 { .bitrate = 90, .hw_value = 18, },
268 { .bitrate = 120, .hw_value = 24, },
269 { .bitrate = 180, .hw_value = 36, },
270 { .bitrate = 240, .hw_value = 48, },
271 { .bitrate = 360, .hw_value = 72, },
272 { .bitrate = 480, .hw_value = 96, },
273 { .bitrate = 540, .hw_value = 108, },
274 { .bitrate = 720, .hw_value = 144, },
275};
276
a66098da
LB		 277/* Set or get info from Firmware */
278#define MWL8K_CMD_SET 0x0001
279#define MWL8K_CMD_GET 0x0000
280
281/* Firmware command codes */
282#define MWL8K_CMD_CODE_DNLD 0x0001
283#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 284#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 285#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
286#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 287#define MWL8K_CMD_RADIO_CONTROL 0x001c
288#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 289#define MWL8K_CMD_RF_ANTENNA 0x0020
b64fe619 290#define MWL8K_CMD_SET_BEACON 0x0100
a66098da
LB		 291#define MWL8K_CMD_SET_PRE_SCAN 0x0107
292#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 293#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
294#define MWL8K_CMD_SET_AID 0x010d
295#define MWL8K_CMD_SET_RATE 0x0110
296#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
297#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 298#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 299#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
300#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 301#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 302#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 303#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 304#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 305#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
b64fe619 306#define MWL8K_CMD_BSS_START 0x1100
3f5610ff 307#define MWL8K_CMD_SET_NEW_STN 0x1111
ff45fc60 308#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 309
310static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
311{
312#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
313 snprintf(buf, bufsize, "%s", #x);\
314 return buf;\
315 } while (0)
ce9e2e1b 316 switch (cmd & ~0x8000) {
a66098da
LB		 317 MWL8K_CMDNAME(CODE_DNLD);
318 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 319 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 320 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
321 MWL8K_CMDNAME(GET_STAT);
322 MWL8K_CMDNAME(RADIO_CONTROL);
323 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 324 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 325 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 326 MWL8K_CMDNAME(SET_PRE_SCAN);
327 MWL8K_CMDNAME(SET_POST_SCAN);
328 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 329 MWL8K_CMDNAME(SET_AID);
330 MWL8K_CMDNAME(SET_RATE);
331 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
332 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 333 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 334 MWL8K_CMDNAME(SET_EDCA_PARAMS);
335 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 336 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 337 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 338 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 339 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 340 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 341 MWL8K_CMDNAME(BSS_START);
3f5610ff 342 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 343 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 344 default:
345 snprintf(buf, bufsize, "0x%x", cmd);
346 }
347#undef MWL8K_CMDNAME
348
349 return buf;
350}
351
352/* Hardware and firmware reset */
353static void mwl8k_hw_reset(struct mwl8k_priv *priv)
354{
355 iowrite32(MWL8K_H2A_INT_RESET,
356 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
357 iowrite32(MWL8K_H2A_INT_RESET,
358 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
359 msleep(20);
360}
361
362/* Release fw image */
363static void mwl8k_release_fw(struct firmware **fw)
364{
365 if (*fw == NULL)
366 return;
367 release_firmware(*fw);
368 *fw = NULL;
369}
370
371static void mwl8k_release_firmware(struct mwl8k_priv *priv)
372{
22be40d9
LB		 373 mwl8k_release_fw(&priv->fw_ucode);
374 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 375}
376
377/* Request fw image */
378static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 379 const char *fname, struct firmware **fw)
a66098da
LB		 380{
381 /* release current image */
382 if (*fw != NULL)
383 mwl8k_release_fw(fw);
384
385 return request_firmware((const struct firmware **)fw,
c2c357ce 386 fname, &priv->pdev->dev);
a66098da
LB		 387}
388
45a390dd 389static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 390{
a74b295e 391 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 392 int rc;
393
a74b295e 394 if (di->helper_image != NULL) {
22be40d9 395 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
a74b295e
LB		 396 if (rc) {
397 printk(KERN_ERR "%s: Error requesting helper "
398 "firmware file %s\n", pci_name(priv->pdev),
399 di->helper_image);
400 return rc;
401 }
a66098da
LB		 402 }
403
22be40d9 404 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 405 if (rc) {
c2c357ce 406 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 407 pci_name(priv->pdev), di->fw_image);
22be40d9 408 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 409 return rc;
410 }
411
412 return 0;
413}
414
415struct mwl8k_cmd_pkt {
416 __le16 code;
417 __le16 length;
418 __le16 seq_num;
419 __le16 result;
420 char payload[0];
421} __attribute__((packed));
422
423/*
424 * Firmware loading.
425 */
426static int
427mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
428{
429 void __iomem *regs = priv->regs;
430 dma_addr_t dma_addr;
a66098da
LB		 431 int loops;
432
433 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
434 if (pci_dma_mapping_error(priv->pdev, dma_addr))
435 return -ENOMEM;
436
437 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
438 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
439 iowrite32(MWL8K_H2A_INT_DOORBELL,
440 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
441 iowrite32(MWL8K_H2A_INT_DUMMY,
442 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
443
a66098da
LB		 444 loops = 1000;
445 do {
446 u32 int_code;
447
448 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
449 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
450 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 451 break;
452 }
453
3d76e82c 454 cond_resched();
a66098da
LB		 455 udelay(1);
456 } while (--loops);
457
458 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
459
d4b70570 460 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 461}
462
463static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
464 const u8 *data, size_t length)
465{
466 struct mwl8k_cmd_pkt *cmd;
467 int done;
468 int rc = 0;
469
470 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
471 if (cmd == NULL)
472 return -ENOMEM;
473
474 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
475 cmd->seq_num = 0;
476 cmd->result = 0;
477
478 done = 0;
479 while (length) {
480 int block_size = length > 256 ? 256 : length;
481
482 memcpy(cmd->payload, data + done, block_size);
483 cmd->length = cpu_to_le16(block_size);
484
485 rc = mwl8k_send_fw_load_cmd(priv, cmd,
486 sizeof(*cmd) + block_size);
487 if (rc)
488 break;
489
490 done += block_size;
491 length -= block_size;
492 }
493
494 if (!rc) {
495 cmd->length = 0;
496 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
497 }
498
499 kfree(cmd);
500
501 return rc;
502}
503
504static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
505 const u8 *data, size_t length)
506{
507 unsigned char *buffer;
508 int may_continue, rc = 0;
509 u32 done, prev_block_size;
510
511 buffer = kmalloc(1024, GFP_KERNEL);
512 if (buffer == NULL)
513 return -ENOMEM;
514
515 done = 0;
516 prev_block_size = 0;
517 may_continue = 1000;
518 while (may_continue > 0) {
519 u32 block_size;
520
521 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
522 if (block_size & 1) {
523 block_size &= ~1;
524 may_continue--;
525 } else {
526 done += prev_block_size;
527 length -= prev_block_size;
528 }
529
530 if (block_size > 1024 || block_size > length) {
531 rc = -EOVERFLOW;
532 break;
533 }
534
535 if (length == 0) {
536 rc = 0;
537 break;
538 }
539
540 if (block_size == 0) {
541 rc = -EPROTO;
542 may_continue--;
543 udelay(1);
544 continue;
545 }
546
547 prev_block_size = block_size;
548 memcpy(buffer, data + done, block_size);
549
550 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
551 if (rc)
552 break;
553 }
554
555 if (!rc && length != 0)
556 rc = -EREMOTEIO;
557
558 kfree(buffer);
559
560 return rc;
561}
562
c2c357ce 563static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 564{
c2c357ce 565 struct mwl8k_priv *priv = hw->priv;
22be40d9 566 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 567 int rc;
568 int loops;
569
570 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 571 struct firmware *helper = priv->fw_helper;
a66098da 572
c2c357ce
LB		 573 if (helper == NULL) {
574 printk(KERN_ERR "%s: helper image needed but none "
575 "given\n", pci_name(priv->pdev));
576 return -EINVAL;
577 }
a66098da 578
c2c357ce 579 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 580 if (rc) {
581 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 582 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 583 return rc;
584 }
89b872e2 585 msleep(5);
a66098da 586
c2c357ce 587 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 588 } else {
c2c357ce 589 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 590 }
591
592 if (rc) {
c2c357ce
LB		 593 printk(KERN_ERR "%s: unable to load firmware image\n",
594 pci_name(priv->pdev));
a66098da
LB		 595 return rc;
596 }
597
89a91f4f 598 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 599
89b872e2 600 loops = 500000;
a66098da 601 do {
eae74e65
LB		 602 u32 ready_code;
603
604 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
605 if (ready_code == MWL8K_FWAP_READY) {
606 priv->ap_fw = 1;
607 break;
608 } else if (ready_code == MWL8K_FWSTA_READY) {
609 priv->ap_fw = 0;
a66098da 610 break;
eae74e65
LB		 611 }
612
613 cond_resched();
a66098da
LB		 614 udelay(1);
615 } while (--loops);
616
617 return loops ? 0 : -ETIMEDOUT;
618}
619
620
a66098da
LB		 621/* DMA header used by firmware and hardware. */
622struct mwl8k_dma_data {
623 __le16 fwlen;
624 struct ieee80211_hdr wh;
20f09c3d 625 char data[0];
a66098da
LB		 626} __attribute__((packed));
627
628/* Routines to add/remove DMA header from skb. */
20f09c3d 629static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 630{
20f09c3d
LB		 631 struct mwl8k_dma_data *tr;
632 int hdrlen;
633
634 tr = (struct mwl8k_dma_data *)skb->data;
635 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
636
637 if (hdrlen != sizeof(tr->wh)) {
638 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
639 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
640 *((__le16 *)(tr->data - 2)) = qos;
641 } else {
642 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
643 }
a66098da 644 }
20f09c3d
LB		 645
646 if (hdrlen != sizeof(*tr))
647 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 648}
649
76266b2a 650static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 651{
652 struct ieee80211_hdr *wh;
ca009301 653 int hdrlen;
a66098da
LB		 654 struct mwl8k_dma_data *tr;
655
ca009301
LB		 656 /*
657 * Add a firmware DMA header; the firmware requires that we
658 * present a 2-byte payload length followed by a 4-address
659 * header (without QoS field), followed (optionally) by any
660 * WEP/ExtIV header (but only filled in for CCMP).
661 */
a66098da 662 wh = (struct ieee80211_hdr *)skb->data;
ca009301 663
a66098da 664 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 665 if (hdrlen != sizeof(*tr))
666 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 667
ca009301
LB		 668 if (ieee80211_is_data_qos(wh->frame_control))
669 hdrlen -= 2;
a66098da
LB		 670
671 tr = (struct mwl8k_dma_data *)skb->data;
672 if (wh != &tr->wh)
673 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 674 if (hdrlen != sizeof(tr->wh))
675 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 676
677 /*
678 * Firmware length is the length of the fully formed "802.11
679 * payload". That is, everything except for the 802.11 header.
680 * This includes all crypto material including the MIC.
681 */
ca009301 682 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 683}
684
685
686/*
89a91f4f 687 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 688 */
89a91f4f 689struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 690 __le16 pkt_len;
691 __u8 sq2;
692 __u8 rate;
693 __le32 pkt_phys_addr;
694 __le32 next_rxd_phys_addr;
695 __le16 qos_control;
696 __le16 htsig2;
697 __le32 hw_rssi_info;
698 __le32 hw_noise_floor_info;
699 __u8 noise_floor;
700 __u8 pad0[3];
701 __u8 rssi;
702 __u8 rx_status;
703 __u8 channel;
704 __u8 rx_ctrl;
705} __attribute__((packed));
706
89a91f4f
LB		 707#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
708#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
709#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 710
89a91f4f 711#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 712
89a91f4f 713static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 714{
89a91f4f 715 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 716
717 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 718 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 719}
720
89a91f4f 721static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 722{
89a91f4f 723 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 724
725 rxd->pkt_len = cpu_to_le16(len);
726 rxd->pkt_phys_addr = cpu_to_le32(addr);
727 wmb();
728 rxd->rx_ctrl = 0;
729}
730
731static int
89a91f4f
LB		 732mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
733 __le16 *qos)
6f6d1e9a 734{
89a91f4f 735 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 736
89a91f4f 737 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 738 return -1;
739 rmb();
740
741 memset(status, 0, sizeof(*status));
742
743 status->signal = -rxd->rssi;
744 status->noise = -rxd->noise_floor;
745
89a91f4f 746 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 747 status->flag |= RX_FLAG_HT;
89a91f4f 748 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 749 status->flag |= RX_FLAG_40MHZ;
89a91f4f 750 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 751 } else {
752 int i;
753
777ad375
LB		 754 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
755 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 756 status->rate_idx = i;
757 break;
758 }
759 }
760 }
761
85478344
LB		 762 if (rxd->channel > 14) {
763 status->band = IEEE80211_BAND_5GHZ;
764 if (!(status->flag & RX_FLAG_HT))
765 status->rate_idx -= 5;
766 } else {
767 status->band = IEEE80211_BAND_2GHZ;
768 }
6f6d1e9a
LB		 769 status->freq = ieee80211_channel_to_frequency(rxd->channel);
770
20f09c3d
LB		 771 *qos = rxd->qos_control;
772
6f6d1e9a
LB		 773 return le16_to_cpu(rxd->pkt_len);
774}
775
89a91f4f
LB		 776static struct rxd_ops rxd_8366_ap_ops = {
777 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
778 .rxd_init = mwl8k_rxd_8366_ap_init,
779 .rxd_refill = mwl8k_rxd_8366_ap_refill,
780 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 781};
782
783/*
89a91f4f 784 * Packet reception for STA firmware.
a66098da 785 */
89a91f4f 786struct mwl8k_rxd_sta {
a66098da
LB		 787 __le16 pkt_len;
788 __u8 link_quality;
789 __u8 noise_level;
790 __le32 pkt_phys_addr;
45eb400d 791 __le32 next_rxd_phys_addr;
a66098da
LB		 792 __le16 qos_control;
793 __le16 rate_info;
794 __le32 pad0[4];
795 __u8 rssi;
796 __u8 channel;
797 __le16 pad1;
798 __u8 rx_ctrl;
799 __u8 rx_status;
800 __u8 pad2[2];
801} __attribute__((packed));
802
89a91f4f
LB		 803#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
804#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
805#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
806#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
807#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
808#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 809
89a91f4f 810#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 811
89a91f4f 812static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 813{
89a91f4f 814 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 815
816 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 817 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 818}
819
89a91f4f 820static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 821{
89a91f4f 822 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 823
824 rxd->pkt_len = cpu_to_le16(len);
825 rxd->pkt_phys_addr = cpu_to_le32(addr);
826 wmb();
827 rxd->rx_ctrl = 0;
828}
829
830static int
89a91f4f 831mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 832 __le16 *qos)
54bc3a0d 833{
89a91f4f 834 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 835 u16 rate_info;
836
89a91f4f 837 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 838 return -1;
839 rmb();
840
841 rate_info = le16_to_cpu(rxd->rate_info);
842
843 memset(status, 0, sizeof(*status));
844
845 status->signal = -rxd->rssi;
846 status->noise = -rxd->noise_level;
89a91f4f
LB		 847 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
848 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 849
89a91f4f 850 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 851 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 852 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 853 status->flag |= RX_FLAG_40MHZ;
89a91f4f 854 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 855 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 856 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 857 status->flag |= RX_FLAG_HT;
858
85478344
LB		 859 if (rxd->channel > 14) {
860 status->band = IEEE80211_BAND_5GHZ;
861 if (!(status->flag & RX_FLAG_HT))
862 status->rate_idx -= 5;
863 } else {
864 status->band = IEEE80211_BAND_2GHZ;
865 }
54bc3a0d
LB		 866 status->freq = ieee80211_channel_to_frequency(rxd->channel);
867
20f09c3d
LB		 868 *qos = rxd->qos_control;
869
54bc3a0d
LB		 870 return le16_to_cpu(rxd->pkt_len);
871}
872
89a91f4f
LB		 873static struct rxd_ops rxd_sta_ops = {
874 .rxd_size = sizeof(struct mwl8k_rxd_sta),
875 .rxd_init = mwl8k_rxd_sta_init,
876 .rxd_refill = mwl8k_rxd_sta_refill,
877 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 878};
879
880
a66098da
LB		 881#define MWL8K_RX_DESCS 256
882#define MWL8K_RX_MAXSZ 3800
883
884static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
885{
886 struct mwl8k_priv *priv = hw->priv;
887 struct mwl8k_rx_queue *rxq = priv->rxq + index;
888 int size;
889 int i;
890
45eb400d
LB		 891 rxq->rxd_count = 0;
892 rxq->head = 0;
893 rxq->tail = 0;
a66098da 894
54bc3a0d 895 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 896
45eb400d
LB		 897 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
898 if (rxq->rxd == NULL) {
a66098da 899 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 900 wiphy_name(hw->wiphy));
a66098da
LB		 901 return -ENOMEM;
902 }
45eb400d 903 memset(rxq->rxd, 0, size);
a66098da 904
788838eb
LB		 905 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
906 if (rxq->buf == NULL) {
a66098da 907 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 908 wiphy_name(hw->wiphy));
45eb400d 909 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 910 return -ENOMEM;
911 }
788838eb 912 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 913
914 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 915 int desc_size;
916 void *rxd;
a66098da 917 int nexti;
54bc3a0d
LB		 918 dma_addr_t next_dma_addr;
919
920 desc_size = priv->rxd_ops->rxd_size;
921 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 922
54bc3a0d
LB		 923 nexti = i + 1;
924 if (nexti == MWL8K_RX_DESCS)
925 nexti = 0;
926 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 927
54bc3a0d 928 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 929 }
930
931 return 0;
932}
933
934static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
935{
936 struct mwl8k_priv *priv = hw->priv;
937 struct mwl8k_rx_queue *rxq = priv->rxq + index;
938 int refilled;
939
940 refilled = 0;
45eb400d 941 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 942 struct sk_buff *skb;
788838eb 943 dma_addr_t addr;
a66098da 944 int rx;
54bc3a0d 945 void *rxd;
a66098da
LB		 946
947 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
948 if (skb == NULL)
949 break;
950
788838eb
LB		 951 addr = pci_map_single(priv->pdev, skb->data,
952 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 953
54bc3a0d
LB		 954 rxq->rxd_count++;
955 rx = rxq->tail++;
956 if (rxq->tail == MWL8K_RX_DESCS)
957 rxq->tail = 0;
788838eb
LB		 958 rxq->buf[rx].skb = skb;
959 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 960
961 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
962 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 963
964 refilled++;
965 }
966
967 return refilled;
968}
969
970/* Must be called only when the card's reception is completely halted */
971static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
972{
973 struct mwl8k_priv *priv = hw->priv;
974 struct mwl8k_rx_queue *rxq = priv->rxq + index;
975 int i;
976
977 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 978 if (rxq->buf[i].skb != NULL) {
979 pci_unmap_single(priv->pdev,
980 pci_unmap_addr(&rxq->buf[i], dma),
981 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
982 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
983
984 kfree_skb(rxq->buf[i].skb);
985 rxq->buf[i].skb = NULL;
a66098da
LB		 986 }
987 }
988
788838eb
LB		 989 kfree(rxq->buf);
990 rxq->buf = NULL;
a66098da
LB		 991
992 pci_free_consistent(priv->pdev,
54bc3a0d 993 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 994 rxq->rxd, rxq->rxd_dma);
995 rxq->rxd = NULL;
a66098da
LB		 996}
997
998
999/*
1000 * Scan a list of BSSIDs to process for finalize join.
1001 * Allows for extension to process multiple BSSIDs.
1002 */
1003static inline int
1004mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1005{
1006 return priv->capture_beacon &&
1007 ieee80211_is_beacon(wh->frame_control) &&
1008 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1009}
1010
3779752d
LB		 1011static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1012 struct sk_buff *skb)
a66098da 1013{
3779752d
LB		 1014 struct mwl8k_priv *priv = hw->priv;
1015
a66098da 1016 priv->capture_beacon = false;
d89173f2 1017 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1018
1019 /*
1020 * Use GFP_ATOMIC as rxq_process is called from
1021 * the primary interrupt handler, memory allocation call
1022 * must not sleep.
1023 */
1024 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1025 if (priv->beacon_skb != NULL)
3779752d 1026 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1027}
1028
1029static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1030{
1031 struct mwl8k_priv *priv = hw->priv;
1032 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1033 int processed;
1034
1035 processed = 0;
45eb400d 1036 while (rxq->rxd_count && limit--) {
a66098da 1037 struct sk_buff *skb;
54bc3a0d
LB		 1038 void *rxd;
1039 int pkt_len;
a66098da 1040 struct ieee80211_rx_status status;
20f09c3d 1041 __le16 qos;
a66098da 1042
788838eb 1043 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1044 if (skb == NULL)
1045 break;
54bc3a0d
LB		 1046
1047 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1048
20f09c3d 1049 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1050 if (pkt_len < 0)
1051 break;
1052
788838eb
LB		 1053 rxq->buf[rxq->head].skb = NULL;
1054
1055 pci_unmap_single(priv->pdev,
1056 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1057 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1058 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1059
54bc3a0d
LB		 1060 rxq->head++;
1061 if (rxq->head == MWL8K_RX_DESCS)
1062 rxq->head = 0;
1063
45eb400d 1064 rxq->rxd_count--;
a66098da 1065
54bc3a0d 1066 skb_put(skb, pkt_len);
20f09c3d 1067 mwl8k_remove_dma_header(skb, qos);
a66098da 1068
a66098da 1069 /*
c2c357ce
LB		 1070 * Check for a pending join operation. Save a
1071 * copy of the beacon and schedule a tasklet to
1072 * send a FINALIZE_JOIN command to the firmware.
a66098da 1073 */
54bc3a0d 1074 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1075 mwl8k_save_beacon(hw, skb);
a66098da 1076
f1d58c25
JB		 1077 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1078 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1079
1080 processed++;
1081 }
1082
1083 return processed;
1084}
1085
1086
1087/*
1088 * Packet transmission.
1089 */
1090
a66098da
LB		 1091#define MWL8K_TXD_STATUS_OK 0x00000001
1092#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1093#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1094#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1095#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1096
e0493a8d
LB		 1097#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1098#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1099#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1100#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1101#define MWL8K_QOS_EOSP 0x0010
1102
a66098da
LB		 1103struct mwl8k_tx_desc {
1104 __le32 status;
1105 __u8 data_rate;
1106 __u8 tx_priority;
1107 __le16 qos_control;
1108 __le32 pkt_phys_addr;
1109 __le16 pkt_len;
d89173f2 1110 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1111 __le32 next_txd_phys_addr;
a66098da
LB		 1112 __le32 reserved;
1113 __le16 rate_info;
1114 __u8 peer_id;
1115 __u8 tx_frag_cnt;
1116} __attribute__((packed));
1117
1118#define MWL8K_TX_DESCS 128
1119
1120static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1121{
1122 struct mwl8k_priv *priv = hw->priv;
1123 struct mwl8k_tx_queue *txq = priv->txq + index;
1124 int size;
1125 int i;
1126
45eb400d
LB		 1127 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1128 txq->stats.limit = MWL8K_TX_DESCS;
1129 txq->head = 0;
1130 txq->tail = 0;
a66098da
LB		 1131
1132 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1133
45eb400d
LB		 1134 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1135 if (txq->txd == NULL) {
a66098da 1136 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1137 wiphy_name(hw->wiphy));
a66098da
LB		 1138 return -ENOMEM;
1139 }
45eb400d 1140 memset(txq->txd, 0, size);
a66098da 1141
45eb400d
LB		 1142 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1143 if (txq->skb == NULL) {
a66098da 1144 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1145 wiphy_name(hw->wiphy));
45eb400d 1146 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1147 return -ENOMEM;
1148 }
45eb400d 1149 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1150
1151 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1152 struct mwl8k_tx_desc *tx_desc;
1153 int nexti;
1154
45eb400d 1155 tx_desc = txq->txd + i;
a66098da
LB		 1156 nexti = (i + 1) % MWL8K_TX_DESCS;
1157
1158 tx_desc->status = 0;
45eb400d
LB		 1159 tx_desc->next_txd_phys_addr =
1160 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1161 }
1162
1163 return 0;
1164}
1165
1166static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1167{
1168 iowrite32(MWL8K_H2A_INT_PPA_READY,
1169 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1170 iowrite32(MWL8K_H2A_INT_DUMMY,
1171 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1172 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1173}
1174
7e1112d3 1175static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1176{
7e1112d3
LB		 1177 struct mwl8k_priv *priv = hw->priv;
1178 int i;
1179
1180 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1181 struct mwl8k_tx_queue *txq = priv->txq + i;
1182 int fw_owned = 0;
1183 int drv_owned = 0;
1184 int unused = 0;
1185 int desc;
1186
a66098da 1187 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1188 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1189 u32 status;
a66098da 1190
7e1112d3 1191 status = le32_to_cpu(tx_desc->status);
a66098da 1192 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1193 fw_owned++;
a66098da 1194 else
7e1112d3 1195 drv_owned++;
a66098da
LB		 1196
1197 if (tx_desc->pkt_len == 0)
7e1112d3 1198 unused++;
a66098da 1199 }
a66098da 1200
7e1112d3
LB		 1201 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1202 "fw_owned=%d drv_owned=%d unused=%d\n",
1203 wiphy_name(hw->wiphy), i,
1204 txq->stats.len, txq->head, txq->tail,
1205 fw_owned, drv_owned, unused);
1206 }
a66098da
LB		 1207}
1208
618952a7 1209/*
88de754a 1210 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1211 */
62abd3cf 1212#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1213
950d5b01 1214static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1215{
a66098da 1216 struct mwl8k_priv *priv = hw->priv;
88de754a 1217 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1218 int retry;
1219 int rc;
a66098da
LB		 1220
1221 might_sleep();
1222
7e1112d3
LB		 1223 /*
1224 * The TX queues are stopped at this point, so this test
1225 * doesn't need to take ->tx_lock.
1226 */
1227 if (!priv->pending_tx_pkts)
1228 return 0;
1229
1230 retry = 0;
1231 rc = 0;
1232
a66098da 1233 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1234 priv->tx_wait = &tx_wait;
1235 while (!rc) {
1236 int oldcount;
1237 unsigned long timeout;
a66098da 1238
7e1112d3 1239 oldcount = priv->pending_tx_pkts;
a66098da 1240
7e1112d3 1241 spin_unlock_bh(&priv->tx_lock);
88de754a 1242 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1243 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1244 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1245
1246 if (timeout) {
1247 WARN_ON(priv->pending_tx_pkts);
1248 if (retry) {
1249 printk(KERN_NOTICE "%s: tx rings drained\n",
1250 wiphy_name(hw->wiphy));
1251 }
1252 break;
1253 }
1254
1255 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB		 1256 printk(KERN_NOTICE "%s: waiting for tx rings "
1257 "to drain (%d -> %d pkts)\n",
7e1112d3
LB		 1258 wiphy_name(hw->wiphy), oldcount,
1259 priv->pending_tx_pkts);
1260 retry = 1;
1261 continue;
1262 }
1263
a66098da 1264 priv->tx_wait = NULL;
a66098da 1265
7e1112d3
LB		 1266 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1267 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1268 mwl8k_dump_tx_rings(hw);
1269
1270 rc = -ETIMEDOUT;
a66098da 1271 }
7e1112d3 1272 spin_unlock_bh(&priv->tx_lock);
a66098da 1273
7e1112d3 1274 return rc;
a66098da
LB		 1275}
1276
c23b5a69
LB		 1277#define MWL8K_TXD_SUCCESS(status) \
1278 ((status) & (MWL8K_TXD_STATUS_OK | \
1279 MWL8K_TXD_STATUS_OK_RETRY | \
1280 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1281
efb7c49a
LB		 1282static int
1283mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1284{
1285 struct mwl8k_priv *priv = hw->priv;
1286 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1287 int processed;
a66098da 1288
efb7c49a
LB		 1289 processed = 0;
1290 while (txq->stats.len > 0 && limit--) {
a66098da 1291 int tx;
a66098da
LB		 1292 struct mwl8k_tx_desc *tx_desc;
1293 unsigned long addr;
ce9e2e1b 1294 int size;
a66098da
LB		 1295 struct sk_buff *skb;
1296 struct ieee80211_tx_info *info;
1297 u32 status;
1298
45eb400d
LB		 1299 tx = txq->head;
1300 tx_desc = txq->txd + tx;
a66098da
LB		 1301
1302 status = le32_to_cpu(tx_desc->status);
1303
1304 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1305 if (!force)
1306 break;
1307 tx_desc->status &=
1308 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1309 }
1310
45eb400d
LB		 1311 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1312 BUG_ON(txq->stats.len == 0);
1313 txq->stats.len--;
a66098da
LB		 1314 priv->pending_tx_pkts--;
1315
1316 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1317 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1318 skb = txq->skb[tx];
1319 txq->skb[tx] = NULL;
a66098da
LB		 1320
1321 BUG_ON(skb == NULL);
1322 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1323
20f09c3d 1324 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1325
1326 /* Mark descriptor as unused */
1327 tx_desc->pkt_phys_addr = 0;
1328 tx_desc->pkt_len = 0;
1329
a66098da
LB		 1330 info = IEEE80211_SKB_CB(skb);
1331 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1332 if (MWL8K_TXD_SUCCESS(status))
a66098da 1333 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1334
1335 ieee80211_tx_status_irqsafe(hw, skb);
1336
efb7c49a 1337 processed++;
a66098da
LB		 1338 }
1339
efb7c49a 1340 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1341 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1342
1343 return processed;
a66098da
LB		 1344}
1345
1346/* must be called only when the card's transmit is completely halted */
1347static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1348{
1349 struct mwl8k_priv *priv = hw->priv;
1350 struct mwl8k_tx_queue *txq = priv->txq + index;
1351
efb7c49a 1352 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1353
45eb400d
LB		 1354 kfree(txq->skb);
1355 txq->skb = NULL;
a66098da
LB		 1356
1357 pci_free_consistent(priv->pdev,
1358 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1359 txq->txd, txq->txd_dma);
1360 txq->txd = NULL;
a66098da
LB		 1361}
1362
1363static int
1364mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1365{
1366 struct mwl8k_priv *priv = hw->priv;
1367 struct ieee80211_tx_info *tx_info;
23b33906 1368 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1369 struct ieee80211_hdr *wh;
1370 struct mwl8k_tx_queue *txq;
1371 struct mwl8k_tx_desc *tx;
a66098da 1372 dma_addr_t dma;
23b33906
LB		 1373 u32 txstatus;
1374 u8 txdatarate;
1375 u16 qos;
a66098da 1376
23b33906
LB		 1377 wh = (struct ieee80211_hdr *)skb->data;
1378 if (ieee80211_is_data_qos(wh->frame_control))
1379 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1380 else
1381 qos = 0;
a66098da 1382
76266b2a 1383 mwl8k_add_dma_header(skb);
23b33906 1384 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1385
1386 tx_info = IEEE80211_SKB_CB(skb);
1387 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1388
1389 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1390 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1391 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1392 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1393 }
1394
23b33906
LB		 1395 /* Setup firmware control bit fields for each frame type. */
1396 txstatus = 0;
1397 txdatarate = 0;
1398 if (ieee80211_is_mgmt(wh->frame_control) ||
1399 ieee80211_is_ctl(wh->frame_control)) {
1400 txdatarate = 0;
e0493a8d 1401 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1402 } else if (ieee80211_is_data(wh->frame_control)) {
1403 txdatarate = 1;
1404 if (is_multicast_ether_addr(wh->addr1))
1405 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1406
e0493a8d 1407 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1408 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1409 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1410 else
e0493a8d 1411 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1412 }
a66098da
LB		 1413
1414 dma = pci_map_single(priv->pdev, skb->data,
1415 skb->len, PCI_DMA_TODEVICE);
1416
1417 if (pci_dma_mapping_error(priv->pdev, dma)) {
1418 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1419 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1420 dev_kfree_skb(skb);
a66098da
LB		 1421 return NETDEV_TX_OK;
1422 }
1423
23b33906 1424 spin_lock_bh(&priv->tx_lock);
a66098da 1425
23b33906 1426 txq = priv->txq + index;
a66098da 1427
45eb400d
LB		 1428 BUG_ON(txq->skb[txq->tail] != NULL);
1429 txq->skb[txq->tail] = skb;
a66098da 1430
45eb400d 1431 tx = txq->txd + txq->tail;
23b33906
LB		 1432 tx->data_rate = txdatarate;
1433 tx->tx_priority = index;
a66098da 1434 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1435 tx->pkt_phys_addr = cpu_to_le32(dma);
1436 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1437 tx->rate_info = 0;
a680400e
LB		 1438 if (!priv->ap_fw && tx_info->control.sta != NULL)
1439 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1440 else
1441 tx->peer_id = 0;
a66098da 1442 wmb();
23b33906
LB		 1443 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1444
45eb400d
LB		 1445 txq->stats.count++;
1446 txq->stats.len++;
a66098da 1447 priv->pending_tx_pkts++;
a66098da 1448
45eb400d
LB		 1449 txq->tail++;
1450 if (txq->tail == MWL8K_TX_DESCS)
1451 txq->tail = 0;
23b33906 1452
45eb400d 1453 if (txq->head == txq->tail)
a66098da
LB		 1454 ieee80211_stop_queue(hw, index);
1455
23b33906 1456 mwl8k_tx_start(priv);
a66098da
LB		 1457
1458 spin_unlock_bh(&priv->tx_lock);
1459
1460 return NETDEV_TX_OK;
1461}
1462
1463
618952a7
LB		 1464/*
1465 * Firmware access.
1466 *
1467 * We have the following requirements for issuing firmware commands:
1468 * - Some commands require that the packet transmit path is idle when
1469 * the command is issued. (For simplicity, we'll just quiesce the
1470 * transmit path for every command.)
1471 * - There are certain sequences of commands that need to be issued to
1472 * the hardware sequentially, with no other intervening commands.
1473 *
1474 * This leads to an implementation of a "firmware lock" as a mutex that
1475 * can be taken recursively, and which is taken by both the low-level
1476 * command submission function (mwl8k_post_cmd) as well as any users of
1477 * that function that require issuing of an atomic sequence of commands,
1478 * and quiesces the transmit path whenever it's taken.
1479 */
1480static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1481{
1482 struct mwl8k_priv *priv = hw->priv;
1483
1484 if (priv->fw_mutex_owner != current) {
1485 int rc;
1486
1487 mutex_lock(&priv->fw_mutex);
1488 ieee80211_stop_queues(hw);
1489
1490 rc = mwl8k_tx_wait_empty(hw);
1491 if (rc) {
1492 ieee80211_wake_queues(hw);
1493 mutex_unlock(&priv->fw_mutex);
1494
1495 return rc;
1496 }
1497
1498 priv->fw_mutex_owner = current;
1499 }
1500
1501 priv->fw_mutex_depth++;
1502
1503 return 0;
1504}
1505
1506static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1507{
1508 struct mwl8k_priv *priv = hw->priv;
1509
1510 if (!--priv->fw_mutex_depth) {
1511 ieee80211_wake_queues(hw);
1512 priv->fw_mutex_owner = NULL;
1513 mutex_unlock(&priv->fw_mutex);
1514 }
1515}
1516
1517
a66098da
LB		 1518/*
1519 * Command processing.
1520 */
1521
0c9cc640
LB		 1522/* Timeout firmware commands after 10s */
1523#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1524
1525static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1526{
1527 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1528 struct mwl8k_priv *priv = hw->priv;
1529 void __iomem *regs = priv->regs;
1530 dma_addr_t dma_addr;
1531 unsigned int dma_size;
1532 int rc;
a66098da
LB		 1533 unsigned long timeout = 0;
1534 u8 buf[32];
1535
c2c357ce 1536 cmd->result = 0xffff;
a66098da
LB		 1537 dma_size = le16_to_cpu(cmd->length);
1538 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1539 PCI_DMA_BIDIRECTIONAL);
1540 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1541 return -ENOMEM;
1542
618952a7 1543 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1544 if (rc) {
1545 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1546 PCI_DMA_BIDIRECTIONAL);
618952a7 1547 return rc;
39a1e42e 1548 }
a66098da 1549
a66098da
LB		 1550 priv->hostcmd_wait = &cmd_wait;
1551 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1552 iowrite32(MWL8K_H2A_INT_DOORBELL,
1553 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1554 iowrite32(MWL8K_H2A_INT_DUMMY,
1555 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1556
1557 timeout = wait_for_completion_timeout(&cmd_wait,
1558 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1559
618952a7
LB		 1560 priv->hostcmd_wait = NULL;
1561
1562 mwl8k_fw_unlock(hw);
1563
37055bd4
LB		 1564 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1565 PCI_DMA_BIDIRECTIONAL);
1566
a66098da 1567 if (!timeout) {
a66098da 1568 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1569 wiphy_name(hw->wiphy),
a66098da
LB		 1570 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1571 MWL8K_CMD_TIMEOUT_MS);
1572 rc = -ETIMEDOUT;
1573 } else {
0c9cc640
LB		 1574 int ms;
1575
1576 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1577
ce9e2e1b 1578 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1579 if (rc)
1580 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1581 wiphy_name(hw->wiphy),
a66098da 1582 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1583 le16_to_cpu(cmd->result));
0c9cc640
LB		 1584 else if (ms > 2000)
1585 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1586 wiphy_name(hw->wiphy),
1587 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1588 ms);
a66098da
LB		 1589 }
1590
a66098da
LB		 1591 return rc;
1592}
1593
1349ad2f
LB		 1594/*
1595 * Setup code shared between STA and AP firmware images.
1596 */
1597static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
1598{
1599 struct mwl8k_priv *priv = hw->priv;
1600
1601 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
1602 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
1603
1604 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
1605 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
1606
1607 priv->band_24.band = IEEE80211_BAND_2GHZ;
1608 priv->band_24.channels = priv->channels_24;
1609 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
1610 priv->band_24.bitrates = priv->rates_24;
1611 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
1612
1613 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
1614}
1615
4eae9edd
LB		 1616static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
1617{
1618 struct mwl8k_priv *priv = hw->priv;
1619
1620 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
1621 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
1622
1623 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
1624 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
1625
1626 priv->band_50.band = IEEE80211_BAND_5GHZ;
1627 priv->band_50.channels = priv->channels_50;
1628 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
1629 priv->band_50.bitrates = priv->rates_50;
1630 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
1631
1632 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
1633}
1634
a66098da 1635/*
04b147b1 1636 * CMD_GET_HW_SPEC (STA version).
a66098da 1637 */
04b147b1 1638struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1639 struct mwl8k_cmd_pkt header;
1640 __u8 hw_rev;
1641 __u8 host_interface;
1642 __le16 num_mcaddrs;
d89173f2 1643 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1644 __le16 region_code;
1645 __le32 fw_rev;
1646 __le32 ps_cookie;
1647 __le32 caps;
1648 __u8 mcs_bitmap[16];
1649 __le32 rx_queue_ptr;
1650 __le32 num_tx_queues;
1651 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1652 __le32 caps2;
1653 __le32 num_tx_desc_per_queue;
45eb400d 1654 __le32 total_rxd;
a66098da
LB		 1655} __attribute__((packed));
1656
341c9791
LB		 1657#define MWL8K_CAP_MAX_AMSDU 0x20000000
1658#define MWL8K_CAP_GREENFIELD 0x08000000
1659#define MWL8K_CAP_AMPDU 0x04000000
1660#define MWL8K_CAP_RX_STBC 0x01000000
1661#define MWL8K_CAP_TX_STBC 0x00800000
1662#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1663#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1664#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1665#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1666#define MWL8K_CAP_DELAY_BA 0x00003000
1667#define MWL8K_CAP_MIMO 0x00000200
1668#define MWL8K_CAP_40MHZ 0x00000100
1669
1670static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
1671{
1672 struct mwl8k_priv *priv = hw->priv;
777ad375 1673 struct ieee80211_supported_band *band = &priv->band_24;
341c9791
LB		 1674 int rx_streams;
1675 int tx_streams;
1676
777ad375 1677 band->ht_cap.ht_supported = 1;
341c9791
LB		 1678
1679 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 1680 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 1681 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 1682 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 1683 if (cap & MWL8K_CAP_AMPDU) {
1684 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 1685 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1686 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 1687 }
1688 if (cap & MWL8K_CAP_RX_STBC)
777ad375 1689 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 1690 if (cap & MWL8K_CAP_TX_STBC)
777ad375 1691 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 1692 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 1693 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 1694 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 1695 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 1696 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 1697 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 1698 if (cap & MWL8K_CAP_40MHZ)
777ad375 1699 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 1700
1701 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1702 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1703
777ad375 1704 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 1705 if (rx_streams >= 2)
777ad375 1706 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 1707 if (rx_streams >= 3)
777ad375
LB		 1708 band->ht_cap.mcs.rx_mask[2] = 0xff;
1709 band->ht_cap.mcs.rx_mask[4] = 0x01;
1710 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 1711
1712 if (rx_streams != tx_streams) {
777ad375
LB		 1713 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1714 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 1715 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1716 }
1717}
1718
04b147b1 1719static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1720{
1721 struct mwl8k_priv *priv = hw->priv;
04b147b1 1722 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1723 int rc;
1724 int i;
1725
1726 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1727 if (cmd == NULL)
1728 return -ENOMEM;
1729
1730 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1731 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1732
1733 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1734 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1735 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1736 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1737 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1738 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1739 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1740 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1741
1742 rc = mwl8k_post_cmd(hw, &cmd->header);
1743
1744 if (!rc) {
1745 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1746 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1747 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1748 priv->hw_rev = cmd->hw_rev;
1349ad2f 1749 mwl8k_setup_2ghz_band(hw);
341c9791
LB		 1750 if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
1751 mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
a66098da
LB		 1752 }
1753
1754 kfree(cmd);
1755 return rc;
1756}
1757
42fba21d
LB		 1758/*
1759 * CMD_GET_HW_SPEC (AP version).
1760 */
1761struct mwl8k_cmd_get_hw_spec_ap {
1762 struct mwl8k_cmd_pkt header;
1763 __u8 hw_rev;
1764 __u8 host_interface;
1765 __le16 num_wcb;
1766 __le16 num_mcaddrs;
1767 __u8 perm_addr[ETH_ALEN];
1768 __le16 region_code;
1769 __le16 num_antenna;
1770 __le32 fw_rev;
1771 __le32 wcbbase0;
1772 __le32 rxwrptr;
1773 __le32 rxrdptr;
1774 __le32 ps_cookie;
1775 __le32 wcbbase1;
1776 __le32 wcbbase2;
1777 __le32 wcbbase3;
1778} __attribute__((packed));
1779
1780static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1781{
1782 struct mwl8k_priv *priv = hw->priv;
1783 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1784 int rc;
1785
1786 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1787 if (cmd == NULL)
1788 return -ENOMEM;
1789
1790 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1791 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1792
1793 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1794 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1795
1796 rc = mwl8k_post_cmd(hw, &cmd->header);
1797
1798 if (!rc) {
1799 int off;
1800
1801 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1802 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1803 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1804 priv->hw_rev = cmd->hw_rev;
1349ad2f 1805 mwl8k_setup_2ghz_band(hw);
42fba21d
LB		 1806
1807 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1808 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1809
1810 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1811 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1812
1813 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1814 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1815
1816 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1817 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1818
1819 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1820 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1821
1822 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1823 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1824 }
1825
1826 kfree(cmd);
1827 return rc;
1828}
1829
1830/*
1831 * CMD_SET_HW_SPEC.
1832 */
1833struct mwl8k_cmd_set_hw_spec {
1834 struct mwl8k_cmd_pkt header;
1835 __u8 hw_rev;
1836 __u8 host_interface;
1837 __le16 num_mcaddrs;
1838 __u8 perm_addr[ETH_ALEN];
1839 __le16 region_code;
1840 __le32 fw_rev;
1841 __le32 ps_cookie;
1842 __le32 caps;
1843 __le32 rx_queue_ptr;
1844 __le32 num_tx_queues;
1845 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1846 __le32 flags;
1847 __le32 num_tx_desc_per_queue;
1848 __le32 total_rxd;
1849} __attribute__((packed));
1850
b64fe619
LB		 1851#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1852#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
1853#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 1854
1855static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1856{
1857 struct mwl8k_priv *priv = hw->priv;
1858 struct mwl8k_cmd_set_hw_spec *cmd;
1859 int rc;
1860 int i;
1861
1862 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1863 if (cmd == NULL)
1864 return -ENOMEM;
1865
1866 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1867 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1868
1869 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1870 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1871 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1872 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1873 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB		 1874 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
1875 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
1876 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 1877 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1878 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1879
1880 rc = mwl8k_post_cmd(hw, &cmd->header);
1881 kfree(cmd);
1882
1883 return rc;
1884}
1885
a66098da
LB		 1886/*
1887 * CMD_MAC_MULTICAST_ADR.
1888 */
1889struct mwl8k_cmd_mac_multicast_adr {
1890 struct mwl8k_cmd_pkt header;
1891 __le16 action;
1892 __le16 numaddr;
ce9e2e1b 1893 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1894};
1895
d5e30845
LB		 1896#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1897#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1898#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1899#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1900
e81cd2d6 1901static struct mwl8k_cmd_pkt *
447ced07 1902__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1903 int mc_count, struct dev_addr_list *mclist)
a66098da 1904{
e81cd2d6 1905 struct mwl8k_priv *priv = hw->priv;
a66098da 1906 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1907 int size;
e81cd2d6 1908
447ced07 1909 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1910 allmulti = 1;
1911 mc_count = 0;
1912 }
e81cd2d6
LB		 1913
1914 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1915
e81cd2d6 1916 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1917 if (cmd == NULL)
e81cd2d6 1918 return NULL;
a66098da
LB		 1919
1920 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1921 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1922 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1923 MWL8K_ENABLE_RX_BROADCAST);
1924
1925 if (allmulti) {
1926 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1927 } else if (mc_count) {
1928 int i;
1929
1930 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1931 cmd->numaddr = cpu_to_le16(mc_count);
1932 for (i = 0; i < mc_count && mclist; i++) {
1933 if (mclist->da_addrlen != ETH_ALEN) {
1934 kfree(cmd);
1935 return NULL;
1936 }
1937 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1938 mclist = mclist->next;
a66098da 1939 }
a66098da
LB		 1940 }
1941
e81cd2d6 1942 return &cmd->header;
a66098da
LB		 1943}
1944
1945/*
55489b6e 1946 * CMD_GET_STAT.
a66098da 1947 */
55489b6e 1948struct mwl8k_cmd_get_stat {
a66098da 1949 struct mwl8k_cmd_pkt header;
a66098da
LB		 1950 __le32 stats[64];
1951} __attribute__((packed));
1952
1953#define MWL8K_STAT_ACK_FAILURE 9
1954#define MWL8K_STAT_RTS_FAILURE 12
1955#define MWL8K_STAT_FCS_ERROR 24
1956#define MWL8K_STAT_RTS_SUCCESS 11
1957
55489b6e
LB		 1958static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1959 struct ieee80211_low_level_stats *stats)
a66098da 1960{
55489b6e 1961 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 1962 int rc;
1963
1964 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1965 if (cmd == NULL)
1966 return -ENOMEM;
1967
1968 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1969 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 1970
1971 rc = mwl8k_post_cmd(hw, &cmd->header);
1972 if (!rc) {
1973 stats->dot11ACKFailureCount =
1974 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1975 stats->dot11RTSFailureCount =
1976 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1977 stats->dot11FCSErrorCount =
1978 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1979 stats->dot11RTSSuccessCount =
1980 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1981 }
1982 kfree(cmd);
1983
1984 return rc;
1985}
1986
1987/*
55489b6e 1988 * CMD_RADIO_CONTROL.
a66098da 1989 */
55489b6e 1990struct mwl8k_cmd_radio_control {
a66098da
LB		 1991 struct mwl8k_cmd_pkt header;
1992 __le16 action;
1993 __le16 control;
1994 __le16 radio_on;
1995} __attribute__((packed));
1996
c46563b7 1997static int
55489b6e 1998mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 1999{
2000 struct mwl8k_priv *priv = hw->priv;
55489b6e 2001 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2002 int rc;
2003
c46563b7 2004 if (enable == priv->radio_on && !force)
a66098da
LB		 2005 return 0;
2006
a66098da
LB		 2007 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2008 if (cmd == NULL)
2009 return -ENOMEM;
2010
2011 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2012 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2013 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2014 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2015 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2016
2017 rc = mwl8k_post_cmd(hw, &cmd->header);
2018 kfree(cmd);
2019
2020 if (!rc)
c46563b7 2021 priv->radio_on = enable;
a66098da
LB		 2022
2023 return rc;
2024}
2025
55489b6e 2026static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2027{
55489b6e 2028 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2029}
2030
55489b6e 2031static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2032{
55489b6e 2033 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2034}
2035
a66098da
LB		 2036static int
2037mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2038{
99200a99 2039 struct mwl8k_priv *priv = hw->priv;
a66098da 2040
68ce3884 2041 priv->radio_short_preamble = short_preamble;
a66098da 2042
55489b6e 2043 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2044}
2045
2046/*
55489b6e 2047 * CMD_RF_TX_POWER.
a66098da
LB		 2048 */
2049#define MWL8K_TX_POWER_LEVEL_TOTAL 8
2050
55489b6e 2051struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2052 struct mwl8k_cmd_pkt header;
2053 __le16 action;
2054 __le16 support_level;
2055 __le16 current_level;
2056 __le16 reserved;
2057 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2058} __attribute__((packed));
2059
55489b6e 2060static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2061{
55489b6e 2062 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2063 int rc;
2064
2065 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2066 if (cmd == NULL)
2067 return -ENOMEM;
2068
2069 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2070 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2071 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2072 cmd->support_level = cpu_to_le16(dBm);
2073
2074 rc = mwl8k_post_cmd(hw, &cmd->header);
2075 kfree(cmd);
2076
2077 return rc;
2078}
2079
08b06347
LB		 2080/*
2081 * CMD_RF_ANTENNA.
2082 */
2083struct mwl8k_cmd_rf_antenna {
2084 struct mwl8k_cmd_pkt header;
2085 __le16 antenna;
2086 __le16 mode;
2087} __attribute__((packed));
2088
2089#define MWL8K_RF_ANTENNA_RX 1
2090#define MWL8K_RF_ANTENNA_TX 2
2091
2092static int
2093mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2094{
2095 struct mwl8k_cmd_rf_antenna *cmd;
2096 int rc;
2097
2098 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2099 if (cmd == NULL)
2100 return -ENOMEM;
2101
2102 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2103 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2104 cmd->antenna = cpu_to_le16(antenna);
2105 cmd->mode = cpu_to_le16(mask);
2106
2107 rc = mwl8k_post_cmd(hw, &cmd->header);
2108 kfree(cmd);
2109
2110 return rc;
2111}
2112
b64fe619
LB		 2113/*
2114 * CMD_SET_BEACON.
2115 */
2116struct mwl8k_cmd_set_beacon {
2117 struct mwl8k_cmd_pkt header;
2118 __le16 beacon_len;
2119 __u8 beacon[0];
2120};
2121
2122static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
2123{
2124 struct mwl8k_cmd_set_beacon *cmd;
2125 int rc;
2126
2127 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2128 if (cmd == NULL)
2129 return -ENOMEM;
2130
2131 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2132 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2133 cmd->beacon_len = cpu_to_le16(len);
2134 memcpy(cmd->beacon, beacon, len);
2135
2136 rc = mwl8k_post_cmd(hw, &cmd->header);
2137 kfree(cmd);
2138
2139 return rc;
2140}
2141
a66098da
LB		 2142/*
2143 * CMD_SET_PRE_SCAN.
2144 */
2145struct mwl8k_cmd_set_pre_scan {
2146 struct mwl8k_cmd_pkt header;
2147} __attribute__((packed));
2148
2149static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2150{
2151 struct mwl8k_cmd_set_pre_scan *cmd;
2152 int rc;
2153
2154 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2155 if (cmd == NULL)
2156 return -ENOMEM;
2157
2158 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2159 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2160
2161 rc = mwl8k_post_cmd(hw, &cmd->header);
2162 kfree(cmd);
2163
2164 return rc;
2165}
2166
2167/*
2168 * CMD_SET_POST_SCAN.
2169 */
2170struct mwl8k_cmd_set_post_scan {
2171 struct mwl8k_cmd_pkt header;
2172 __le32 isibss;
d89173f2 2173 __u8 bssid[ETH_ALEN];
a66098da
LB		 2174} __attribute__((packed));
2175
2176static int
0a11dfc3 2177mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2178{
2179 struct mwl8k_cmd_set_post_scan *cmd;
2180 int rc;
2181
2182 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2183 if (cmd == NULL)
2184 return -ENOMEM;
2185
2186 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2187 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2188 cmd->isibss = 0;
d89173f2 2189 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2190
2191 rc = mwl8k_post_cmd(hw, &cmd->header);
2192 kfree(cmd);
2193
2194 return rc;
2195}
2196
2197/*
2198 * CMD_SET_RF_CHANNEL.
2199 */
2200struct mwl8k_cmd_set_rf_channel {
2201 struct mwl8k_cmd_pkt header;
2202 __le16 action;
2203 __u8 current_channel;
2204 __le32 channel_flags;
2205} __attribute__((packed));
2206
2207static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2208 struct ieee80211_conf *conf)
a66098da 2209{
610677d2 2210 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2211 struct mwl8k_cmd_set_rf_channel *cmd;
2212 int rc;
2213
2214 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2215 if (cmd == NULL)
2216 return -ENOMEM;
2217
2218 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2219 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2220 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2221 cmd->current_channel = channel->hw_value;
610677d2 2222
a66098da 2223 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2
LB		 2224 cmd->channel_flags |= cpu_to_le32(0x00000001);
2225
2226 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2227 conf->channel_type == NL80211_CHAN_HT20)
2228 cmd->channel_flags |= cpu_to_le32(0x00000080);
2229 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2230 cmd->channel_flags |= cpu_to_le32(0x000001900);
2231 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2232 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2233
2234 rc = mwl8k_post_cmd(hw, &cmd->header);
2235 kfree(cmd);
2236
2237 return rc;
2238}
2239
2240/*
55489b6e 2241 * CMD_SET_AID.
a66098da 2242 */
55489b6e
LB		 2243#define MWL8K_FRAME_PROT_DISABLED 0x00
2244#define MWL8K_FRAME_PROT_11G 0x07
2245#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2246#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2247
55489b6e
LB		 2248struct mwl8k_cmd_update_set_aid {
2249 struct mwl8k_cmd_pkt header;
2250 __le16 aid;
a66098da 2251
55489b6e
LB		 2252 /* AP's MAC address (BSSID) */
2253 __u8 bssid[ETH_ALEN];
2254 __le16 protection_mode;
2255 __u8 supp_rates[14];
a66098da
LB		 2256} __attribute__((packed));
2257
c6e96010
LB		 2258static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2259{
2260 int i;
2261 int j;
2262
2263 /*
2264 * Clear nonstandard rates 4 and 13.
2265 */
2266 mask &= 0x1fef;
2267
2268 for (i = 0, j = 0; i < 14; i++) {
2269 if (mask & (1 << i))
777ad375 2270 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 2271 }
2272}
2273
55489b6e 2274static int
c6e96010
LB		 2275mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2276 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2277{
55489b6e
LB		 2278 struct mwl8k_cmd_update_set_aid *cmd;
2279 u16 prot_mode;
a66098da
LB		 2280 int rc;
2281
2282 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2283 if (cmd == NULL)
2284 return -ENOMEM;
2285
55489b6e 2286 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2287 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2288 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2289 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2290
7dc6a7a7 2291 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2292 prot_mode = MWL8K_FRAME_PROT_11G;
2293 } else {
7dc6a7a7 2294 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2295 IEEE80211_HT_OP_MODE_PROTECTION) {
2296 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2297 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2298 break;
2299 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2300 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2301 break;
2302 default:
2303 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2304 break;
2305 }
2306 }
2307 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2308
c6e96010 2309 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2310
2311 rc = mwl8k_post_cmd(hw, &cmd->header);
2312 kfree(cmd);
2313
2314 return rc;
2315}
2316
32060e1b 2317/*
55489b6e 2318 * CMD_SET_RATE.
32060e1b 2319 */
55489b6e
LB		 2320struct mwl8k_cmd_set_rate {
2321 struct mwl8k_cmd_pkt header;
2322 __u8 legacy_rates[14];
2323
2324 /* Bitmap for supported MCS codes. */
2325 __u8 mcs_set[16];
2326 __u8 reserved[16];
32060e1b
LB		 2327} __attribute__((packed));
2328
55489b6e 2329static int
c6e96010 2330mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2331 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2332{
55489b6e 2333 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2334 int rc;
2335
2336 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2337 if (cmd == NULL)
2338 return -ENOMEM;
2339
55489b6e 2340 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2341 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2342 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2343 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2344
2345 rc = mwl8k_post_cmd(hw, &cmd->header);
2346 kfree(cmd);
2347
2348 return rc;
2349}
2350
a66098da 2351/*
55489b6e 2352 * CMD_FINALIZE_JOIN.
a66098da 2353 */
55489b6e
LB		 2354#define MWL8K_FJ_BEACON_MAXLEN 128
2355
2356struct mwl8k_cmd_finalize_join {
a66098da 2357 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2358 __le32 sleep_interval; /* Number of beacon periods to sleep */
2359 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB		 2360} __attribute__((packed));
2361
55489b6e
LB		 2362static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2363 int framelen, int dtim)
a66098da 2364{
55489b6e
LB		 2365 struct mwl8k_cmd_finalize_join *cmd;
2366 struct ieee80211_mgmt *payload = frame;
2367 int payload_len;
a66098da
LB		 2368 int rc;
2369
2370 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2371 if (cmd == NULL)
2372 return -ENOMEM;
2373
55489b6e 2374 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2375 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2376 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2377
2378 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2379 if (payload_len < 0)
2380 payload_len = 0;
2381 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2382 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2383
2384 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2385
2386 rc = mwl8k_post_cmd(hw, &cmd->header);
2387 kfree(cmd);
2388
2389 return rc;
2390}
2391
2392/*
55489b6e 2393 * CMD_SET_RTS_THRESHOLD.
a66098da 2394 */
55489b6e 2395struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2396 struct mwl8k_cmd_pkt header;
2397 __le16 action;
55489b6e 2398 __le16 threshold;
a66098da
LB		 2399} __attribute__((packed));
2400
c2c2b12a
LB		 2401static int
2402mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2403{
55489b6e 2404 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2405 int rc;
2406
2407 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2408 if (cmd == NULL)
2409 return -ENOMEM;
2410
55489b6e 2411 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2412 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 2413 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2414 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 2415
2416 rc = mwl8k_post_cmd(hw, &cmd->header);
2417 kfree(cmd);
2418
a66098da
LB		 2419 return rc;
2420}
2421
2422/*
55489b6e 2423 * CMD_SET_SLOT.
a66098da 2424 */
55489b6e 2425struct mwl8k_cmd_set_slot {
a66098da
LB		 2426 struct mwl8k_cmd_pkt header;
2427 __le16 action;
55489b6e 2428 __u8 short_slot;
a66098da
LB		 2429} __attribute__((packed));
2430
55489b6e 2431static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2432{
55489b6e 2433 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2434 int rc;
2435
2436 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2437 if (cmd == NULL)
2438 return -ENOMEM;
2439
55489b6e 2440 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2441 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2442 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2443 cmd->short_slot = short_slot_time;
a66098da
LB		 2444
2445 rc = mwl8k_post_cmd(hw, &cmd->header);
2446 kfree(cmd);
2447
2448 return rc;
2449}
2450
2451/*
2452 * CMD_SET_EDCA_PARAMS.
2453 */
2454struct mwl8k_cmd_set_edca_params {
2455 struct mwl8k_cmd_pkt header;
2456
2457 /* See MWL8K_SET_EDCA_XXX below */
2458 __le16 action;
2459
2460 /* TX opportunity in units of 32 us */
2461 __le16 txop;
2462
2e484c89
LB		 2463 union {
2464 struct {
2465 /* Log exponent of max contention period: 0...15 */
2466 __le32 log_cw_max;
2467
2468 /* Log exponent of min contention period: 0...15 */
2469 __le32 log_cw_min;
2470
2471 /* Adaptive interframe spacing in units of 32us */
2472 __u8 aifs;
2473
2474 /* TX queue to configure */
2475 __u8 txq;
2476 } ap;
2477 struct {
2478 /* Log exponent of max contention period: 0...15 */
2479 __u8 log_cw_max;
a66098da 2480
2e484c89
LB		 2481 /* Log exponent of min contention period: 0...15 */
2482 __u8 log_cw_min;
a66098da 2483
2e484c89
LB		 2484 /* Adaptive interframe spacing in units of 32us */
2485 __u8 aifs;
a66098da 2486
2e484c89
LB		 2487 /* TX queue to configure */
2488 __u8 txq;
2489 } sta;
2490 };
a66098da
LB		 2491} __attribute__((packed));
2492
a66098da
LB		 2493#define MWL8K_SET_EDCA_CW 0x01
2494#define MWL8K_SET_EDCA_TXOP 0x02
2495#define MWL8K_SET_EDCA_AIFS 0x04
2496
2497#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2498 MWL8K_SET_EDCA_TXOP | \
2499 MWL8K_SET_EDCA_AIFS)
2500
2501static int
55489b6e
LB		 2502mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2503 __u16 cw_min, __u16 cw_max,
2504 __u8 aifs, __u16 txop)
a66098da 2505{
2e484c89 2506 struct mwl8k_priv *priv = hw->priv;
a66098da 2507 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2508 int rc;
2509
2510 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2511 if (cmd == NULL)
2512 return -ENOMEM;
2513
a66098da
LB		 2514 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2515 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2516 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2517 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2518 if (priv->ap_fw) {
2519 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2520 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2521 cmd->ap.aifs = aifs;
2522 cmd->ap.txq = qnum;
2523 } else {
2524 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2525 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2526 cmd->sta.aifs = aifs;
2527 cmd->sta.txq = qnum;
2528 }
a66098da
LB		 2529
2530 rc = mwl8k_post_cmd(hw, &cmd->header);
2531 kfree(cmd);
2532
2533 return rc;
2534}
2535
2536/*
55489b6e 2537 * CMD_SET_WMM_MODE.
a66098da 2538 */
55489b6e 2539struct mwl8k_cmd_set_wmm_mode {
a66098da 2540 struct mwl8k_cmd_pkt header;
55489b6e 2541 __le16 action;
a66098da
LB		 2542} __attribute__((packed));
2543
55489b6e 2544static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2545{
55489b6e
LB		 2546 struct mwl8k_priv *priv = hw->priv;
2547 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2548 int rc;
2549
a66098da
LB		 2550 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2551 if (cmd == NULL)
2552 return -ENOMEM;
2553
55489b6e 2554 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2555 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2556 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2557
2558 rc = mwl8k_post_cmd(hw, &cmd->header);
2559 kfree(cmd);
16cec43d 2560
55489b6e
LB		 2561 if (!rc)
2562 priv->wmm_enabled = enable;
a66098da
LB		 2563
2564 return rc;
2565}
2566
2567/*
55489b6e 2568 * CMD_MIMO_CONFIG.
a66098da 2569 */
55489b6e
LB		 2570struct mwl8k_cmd_mimo_config {
2571 struct mwl8k_cmd_pkt header;
2572 __le32 action;
2573 __u8 rx_antenna_map;
2574 __u8 tx_antenna_map;
a66098da
LB		 2575} __attribute__((packed));
2576
55489b6e 2577static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2578{
55489b6e 2579 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2580 int rc;
2581
2582 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2583 if (cmd == NULL)
2584 return -ENOMEM;
2585
55489b6e 2586 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2587 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2588 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2589 cmd->rx_antenna_map = rx;
2590 cmd->tx_antenna_map = tx;
a66098da
LB		 2591
2592 rc = mwl8k_post_cmd(hw, &cmd->header);
2593 kfree(cmd);
2594
2595 return rc;
2596}
2597
2598/*
b71ed2c6 2599 * CMD_USE_FIXED_RATE (STA version).
a66098da 2600 */
b71ed2c6
LB		 2601struct mwl8k_cmd_use_fixed_rate_sta {
2602 struct mwl8k_cmd_pkt header;
2603 __le32 action;
2604 __le32 allow_rate_drop;
2605 __le32 num_rates;
2606 struct {
2607 __le32 is_ht_rate;
2608 __le32 enable_retry;
2609 __le32 rate;
2610 __le32 retry_count;
2611 } rate_entry[8];
2612 __le32 rate_type;
2613 __le32 reserved1;
2614 __le32 reserved2;
a66098da
LB		 2615} __attribute__((packed));
2616
b71ed2c6
LB		 2617#define MWL8K_USE_AUTO_RATE 0x0002
2618#define MWL8K_UCAST_RATE 0
a66098da 2619
b71ed2c6 2620static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2621{
b71ed2c6 2622 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 2623 int rc;
2624
2625 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2626 if (cmd == NULL)
2627 return -ENOMEM;
2628
2629 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2630 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 2631 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2632 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 2633
2634 rc = mwl8k_post_cmd(hw, &cmd->header);
2635 kfree(cmd);
2636
2637 return rc;
2638}
2639
088aab8b
LB		 2640/*
2641 * CMD_USE_FIXED_RATE (AP version).
2642 */
2643struct mwl8k_cmd_use_fixed_rate_ap {
2644 struct mwl8k_cmd_pkt header;
2645 __le32 action;
2646 __le32 allow_rate_drop;
2647 __le32 num_rates;
2648 struct mwl8k_rate_entry_ap {
2649 __le32 is_ht_rate;
2650 __le32 enable_retry;
2651 __le32 rate;
2652 __le32 retry_count;
2653 } rate_entry[4];
2654 u8 multicast_rate;
2655 u8 multicast_rate_type;
2656 u8 management_rate;
2657} __attribute__((packed));
2658
2659static int
2660mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2661{
2662 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2663 int rc;
2664
2665 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2666 if (cmd == NULL)
2667 return -ENOMEM;
2668
2669 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2670 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2671 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2672 cmd->multicast_rate = mcast;
2673 cmd->management_rate = mgmt;
2674
2675 rc = mwl8k_post_cmd(hw, &cmd->header);
2676 kfree(cmd);
2677
2678 return rc;
2679}
2680
55489b6e
LB		 2681/*
2682 * CMD_ENABLE_SNIFFER.
2683 */
2684struct mwl8k_cmd_enable_sniffer {
2685 struct mwl8k_cmd_pkt header;
2686 __le32 action;
2687} __attribute__((packed));
2688
2689static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2690{
2691 struct mwl8k_cmd_enable_sniffer *cmd;
2692 int rc;
2693
2694 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2695 if (cmd == NULL)
2696 return -ENOMEM;
2697
2698 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2699 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2700 cmd->action = cpu_to_le32(!!enable);
2701
2702 rc = mwl8k_post_cmd(hw, &cmd->header);
2703 kfree(cmd);
2704
2705 return rc;
2706}
2707
2708/*
2709 * CMD_SET_MAC_ADDR.
2710 */
2711struct mwl8k_cmd_set_mac_addr {
2712 struct mwl8k_cmd_pkt header;
2713 union {
2714 struct {
2715 __le16 mac_type;
2716 __u8 mac_addr[ETH_ALEN];
2717 } mbss;
2718 __u8 mac_addr[ETH_ALEN];
2719 };
2720} __attribute__((packed));
2721
a9e00b15
LB		 2722#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
2723#define MWL8K_MAC_TYPE_PRIMARY_AP 2
2724
55489b6e
LB		 2725static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2726{
2727 struct mwl8k_priv *priv = hw->priv;
2728 struct mwl8k_cmd_set_mac_addr *cmd;
2729 int rc;
2730
2731 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2732 if (cmd == NULL)
2733 return -ENOMEM;
2734
2735 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2736 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2737 if (priv->ap_fw) {
a9e00b15 2738 cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
55489b6e
LB		 2739 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2740 } else {
2741 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2742 }
2743
2744 rc = mwl8k_post_cmd(hw, &cmd->header);
2745 kfree(cmd);
2746
2747 return rc;
2748}
2749
2750/*
2751 * CMD_SET_RATEADAPT_MODE.
2752 */
2753struct mwl8k_cmd_set_rate_adapt_mode {
2754 struct mwl8k_cmd_pkt header;
2755 __le16 action;
2756 __le16 mode;
2757} __attribute__((packed));
2758
2759static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2760{
2761 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2762 int rc;
2763
2764 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2765 if (cmd == NULL)
2766 return -ENOMEM;
2767
2768 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2769 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2770 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2771 cmd->mode = cpu_to_le16(mode);
2772
2773 rc = mwl8k_post_cmd(hw, &cmd->header);
2774 kfree(cmd);
2775
2776 return rc;
2777}
2778
b64fe619
LB		 2779/*
2780 * CMD_BSS_START.
2781 */
2782struct mwl8k_cmd_bss_start {
2783 struct mwl8k_cmd_pkt header;
2784 __le32 enable;
2785} __attribute__((packed));
2786
2787static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
2788{
2789 struct mwl8k_cmd_bss_start *cmd;
2790 int rc;
2791
2792 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2793 if (cmd == NULL)
2794 return -ENOMEM;
2795
2796 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
2797 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2798 cmd->enable = cpu_to_le32(enable);
2799
2800 rc = mwl8k_post_cmd(hw, &cmd->header);
2801 kfree(cmd);
2802
2803 return rc;
2804}
2805
3f5610ff
LB		 2806/*
2807 * CMD_SET_NEW_STN.
2808 */
2809struct mwl8k_cmd_set_new_stn {
2810 struct mwl8k_cmd_pkt header;
2811 __le16 aid;
2812 __u8 mac_addr[6];
2813 __le16 stn_id;
2814 __le16 action;
2815 __le16 rsvd;
2816 __le32 legacy_rates;
2817 __u8 ht_rates[4];
2818 __le16 cap_info;
2819 __le16 ht_capabilities_info;
2820 __u8 mac_ht_param_info;
2821 __u8 rev;
2822 __u8 control_channel;
2823 __u8 add_channel;
2824 __le16 op_mode;
2825 __le16 stbc;
2826 __u8 add_qos_info;
2827 __u8 is_qos_sta;
2828 __le32 fw_sta_ptr;
2829} __attribute__((packed));
2830
2831#define MWL8K_STA_ACTION_ADD 0
2832#define MWL8K_STA_ACTION_REMOVE 2
2833
2834static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
2835 struct ieee80211_vif *vif,
2836 struct ieee80211_sta *sta)
2837{
2838 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 2839 u32 rates;
3f5610ff
LB		 2840 int rc;
2841
2842 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2843 if (cmd == NULL)
2844 return -ENOMEM;
2845
2846 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2847 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2848 cmd->aid = cpu_to_le16(sta->aid);
2849 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
2850 cmd->stn_id = cpu_to_le16(sta->aid);
2851 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 2852 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
2853 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
2854 else
2855 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
2856 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 2857 if (sta->ht_cap.ht_supported) {
2858 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
2859 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
2860 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
2861 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
2862 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
2863 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
2864 ((sta->ht_cap.ampdu_density & 7) << 2);
2865 cmd->is_qos_sta = 1;
2866 }
2867
2868 rc = mwl8k_post_cmd(hw, &cmd->header);
2869 kfree(cmd);
2870
2871 return rc;
2872}
2873
b64fe619
LB		 2874static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
2875 struct ieee80211_vif *vif)
2876{
2877 struct mwl8k_cmd_set_new_stn *cmd;
2878 int rc;
2879
2880 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2881 if (cmd == NULL)
2882 return -ENOMEM;
2883
2884 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2885 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2886 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
2887
2888 rc = mwl8k_post_cmd(hw, &cmd->header);
2889 kfree(cmd);
2890
2891 return rc;
2892}
2893
3f5610ff
LB		 2894static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
2895 struct ieee80211_vif *vif, u8 *addr)
2896{
2897 struct mwl8k_cmd_set_new_stn *cmd;
2898 int rc;
2899
2900 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2901 if (cmd == NULL)
2902 return -ENOMEM;
2903
2904 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2905 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2906 memcpy(cmd->mac_addr, addr, ETH_ALEN);
2907 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
2908
2909 rc = mwl8k_post_cmd(hw, &cmd->header);
2910 kfree(cmd);
2911
2912 return rc;
2913}
2914
55489b6e
LB		 2915/*
2916 * CMD_UPDATE_STADB.
2917 */
25d81b1e
LB		 2918struct ewc_ht_info {
2919 __le16 control1;
2920 __le16 control2;
2921 __le16 control3;
2922} __attribute__((packed));
2923
2924struct peer_capability_info {
2925 /* Peer type - AP vs. STA. */
2926 __u8 peer_type;
2927
2928 /* Basic 802.11 capabilities from assoc resp. */
2929 __le16 basic_caps;
2930
2931 /* Set if peer supports 802.11n high throughput (HT). */
2932 __u8 ht_support;
2933
2934 /* Valid if HT is supported. */
2935 __le16 ht_caps;
2936 __u8 extended_ht_caps;
2937 struct ewc_ht_info ewc_info;
2938
2939 /* Legacy rate table. Intersection of our rates and peer rates. */
2940 __u8 legacy_rates[12];
2941
2942 /* HT rate table. Intersection of our rates and peer rates. */
2943 __u8 ht_rates[16];
2944 __u8 pad[16];
2945
2946 /* If set, interoperability mode, no proprietary extensions. */
2947 __u8 interop;
2948 __u8 pad2;
2949 __u8 station_id;
2950 __le16 amsdu_enabled;
2951} __attribute__((packed));
2952
55489b6e
LB		 2953struct mwl8k_cmd_update_stadb {
2954 struct mwl8k_cmd_pkt header;
2955
2956 /* See STADB_ACTION_TYPE */
2957 __le32 action;
2958
2959 /* Peer MAC address */
2960 __u8 peer_addr[ETH_ALEN];
2961
2962 __le32 reserved;
2963
2964 /* Peer info - valid during add/update. */
2965 struct peer_capability_info peer_info;
2966} __attribute__((packed));
2967
a680400e
LB		 2968#define MWL8K_STA_DB_MODIFY_ENTRY 1
2969#define MWL8K_STA_DB_DEL_ENTRY 2
2970
2971/* Peer Entry flags - used to define the type of the peer node */
2972#define MWL8K_PEER_TYPE_ACCESSPOINT 2
2973
2974static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 2975 struct ieee80211_vif *vif,
13935e2c 2976 struct ieee80211_sta *sta)
55489b6e 2977{
55489b6e 2978 struct mwl8k_cmd_update_stadb *cmd;
a680400e 2979 struct peer_capability_info *p;
8707d026 2980 u32 rates;
55489b6e
LB		 2981 int rc;
2982
2983 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2984 if (cmd == NULL)
2985 return -ENOMEM;
2986
2987 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2988 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 2989 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 2990 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 2991
a680400e
LB		 2992 p = &cmd->peer_info;
2993 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2994 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c
LB		 2995 p->ht_support = sta->ht_cap.ht_supported;
2996 p->ht_caps = sta->ht_cap.cap;
2997 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
2998 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 2999 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3000 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3001 else
3002 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3003 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 3004 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 3005 p->interop = 1;
3006 p->amsdu_enabled = 0;
3007
3008 rc = mwl8k_post_cmd(hw, &cmd->header);
3009 kfree(cmd);
3010
3011 return rc ? rc : p->station_id;
3012}
3013
3014static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
3015 struct ieee80211_vif *vif, u8 *addr)
3016{
3017 struct mwl8k_cmd_update_stadb *cmd;
3018 int rc;
3019
3020 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3021 if (cmd == NULL)
3022 return -ENOMEM;
3023
3024 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3025 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3026 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 3027 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 3028
a680400e 3029 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 3030 kfree(cmd);
3031
3032 return rc;
3033}
3034
a66098da
LB		 3035
3036/*
3037 * Interrupt handling.
3038 */
3039static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
3040{
3041 struct ieee80211_hw *hw = dev_id;
3042 struct mwl8k_priv *priv = hw->priv;
3043 u32 status;
3044
3045 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 3046 if (!status)
3047 return IRQ_NONE;
3048
1e9f9de3
LB		 3049 if (status & MWL8K_A2H_INT_TX_DONE) {
3050 status &= ~MWL8K_A2H_INT_TX_DONE;
3051 tasklet_schedule(&priv->poll_tx_task);
3052 }
3053
a66098da 3054 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 3055 status &= ~MWL8K_A2H_INT_RX_READY;
3056 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 3057 }
3058
67e2eb27
LB		 3059 if (status)
3060 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3061
a66098da 3062 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 3063 if (priv->hostcmd_wait != NULL)
a66098da 3064 complete(priv->hostcmd_wait);
a66098da
LB		 3065 }
3066
3067 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 3068 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 3069 priv->radio_on && priv->pending_tx_pkts)
618952a7 3070 mwl8k_tx_start(priv);
a66098da
LB		 3071 }
3072
3073 return IRQ_HANDLED;
3074}
3075
1e9f9de3
LB		 3076static void mwl8k_tx_poll(unsigned long data)
3077{
3078 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3079 struct mwl8k_priv *priv = hw->priv;
3080 int limit;
3081 int i;
3082
3083 limit = 32;
3084
3085 spin_lock_bh(&priv->tx_lock);
3086
3087 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3088 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3089
3090 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3091 complete(priv->tx_wait);
3092 priv->tx_wait = NULL;
3093 }
3094
3095 spin_unlock_bh(&priv->tx_lock);
3096
3097 if (limit) {
3098 writel(~MWL8K_A2H_INT_TX_DONE,
3099 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3100 } else {
3101 tasklet_schedule(&priv->poll_tx_task);
3102 }
3103}
3104
67e2eb27
LB		 3105static void mwl8k_rx_poll(unsigned long data)
3106{
3107 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3108 struct mwl8k_priv *priv = hw->priv;
3109 int limit;
3110
3111 limit = 32;
3112 limit -= rxq_process(hw, 0, limit);
3113 limit -= rxq_refill(hw, 0, limit);
3114
3115 if (limit) {
3116 writel(~MWL8K_A2H_INT_RX_READY,
3117 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3118 } else {
3119 tasklet_schedule(&priv->poll_rx_task);
3120 }
3121}
3122
a66098da
LB		 3123
3124/*
3125 * Core driver operations.
3126 */
3127static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3128{
3129 struct mwl8k_priv *priv = hw->priv;
3130 int index = skb_get_queue_mapping(skb);
3131 int rc;
3132
9189c100 3133 if (!priv->radio_on) {
a66098da 3134 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 3135 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 3136 dev_kfree_skb(skb);
3137 return NETDEV_TX_OK;
3138 }
3139
3140 rc = mwl8k_txq_xmit(hw, index, skb);
3141
3142 return rc;
3143}
3144
a66098da
LB		 3145static int mwl8k_start(struct ieee80211_hw *hw)
3146{
a66098da
LB		 3147 struct mwl8k_priv *priv = hw->priv;
3148 int rc;
3149
a0607fd3 3150 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3151 IRQF_SHARED, MWL8K_NAME, hw);
3152 if (rc) {
3153 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3154 wiphy_name(hw->wiphy));
2ec610cb 3155 return -EIO;
a66098da
LB		 3156 }
3157
67e2eb27 3158 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3159 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3160 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3161
a66098da 3162 /* Enable interrupts */
c23b5a69 3163 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3164
2ec610cb
LB		 3165 rc = mwl8k_fw_lock(hw);
3166 if (!rc) {
55489b6e 3167 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3168
5e4cf166
LB		 3169 if (!priv->ap_fw) {
3170 if (!rc)
55489b6e 3171 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3172
5e4cf166
LB		 3173 if (!rc)
3174 rc = mwl8k_cmd_set_pre_scan(hw);
3175
3176 if (!rc)
3177 rc = mwl8k_cmd_set_post_scan(hw,
3178 "\x00\x00\x00\x00\x00\x00");
3179 }
2ec610cb
LB		 3180
3181 if (!rc)
55489b6e 3182 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3183
2ec610cb 3184 if (!rc)
55489b6e 3185 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3186
2ec610cb
LB		 3187 mwl8k_fw_unlock(hw);
3188 }
3189
3190 if (rc) {
3191 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3192 free_irq(priv->pdev->irq, hw);
1e9f9de3 3193 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3194 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3195 }
a66098da
LB		 3196
3197 return rc;
3198}
3199
a66098da
LB		 3200static void mwl8k_stop(struct ieee80211_hw *hw)
3201{
a66098da
LB		 3202 struct mwl8k_priv *priv = hw->priv;
3203 int i;
3204
55489b6e 3205 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 3206
3207 ieee80211_stop_queues(hw);
3208
a66098da 3209 /* Disable interrupts */
a66098da 3210 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3211 free_irq(priv->pdev->irq, hw);
3212
3213 /* Stop finalize join worker */
3214 cancel_work_sync(&priv->finalize_join_worker);
3215 if (priv->beacon_skb != NULL)
3216 dev_kfree_skb(priv->beacon_skb);
3217
67e2eb27 3218 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3219 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3220 tasklet_disable(&priv->poll_rx_task);
a66098da 3221
a66098da
LB		 3222 /* Return all skbs to mac80211 */
3223 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3224 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 3225}
3226
3227static int mwl8k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3228 struct ieee80211_vif *vif)
a66098da
LB		 3229{
3230 struct mwl8k_priv *priv = hw->priv;
3231 struct mwl8k_vif *mwl8k_vif;
3232
3233 /*
3234 * We only support one active interface at a time.
3235 */
3236 if (priv->vif != NULL)
3237 return -EBUSY;
3238
a43c49a8
LB		 3239 /*
3240 * Reject interface creation if sniffer mode is active, as
3241 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3242 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 3243 */
3244 if (priv->sniffer_enabled) {
3245 printk(KERN_INFO "%s: unable to create STA "
3246 "interface due to sniffer mode being enabled\n",
3247 wiphy_name(hw->wiphy));
3248 return -EINVAL;
3249 }
3250
c2c2b12a
LB		 3251 /* Set the mac address. */
3252 mwl8k_cmd_set_mac_addr(hw, vif->addr);
3253
b64fe619
LB		 3254 if (priv->ap_fw)
3255 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3256
a66098da 3257 /* Clean out driver private area */
1ed32e4f 3258 mwl8k_vif = MWL8K_VIF(vif);
a66098da
LB		 3259 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
3260
a66098da
LB		 3261 /* Set Initial sequence number to zero */
3262 mwl8k_vif->seqno = 0;
3263
1ed32e4f 3264 priv->vif = vif;
a66098da
LB		 3265
3266 return 0;
3267}
3268
3269static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3270 struct ieee80211_vif *vif)
a66098da
LB		 3271{
3272 struct mwl8k_priv *priv = hw->priv;
3273
b64fe619
LB		 3274 if (priv->ap_fw)
3275 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3276
55489b6e 3277 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 3278
a66098da
LB		 3279 priv->vif = NULL;
3280}
3281
ee03a932 3282static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3283{
a66098da
LB		 3284 struct ieee80211_conf *conf = &hw->conf;
3285 struct mwl8k_priv *priv = hw->priv;
ee03a932 3286 int rc;
a66098da 3287
7595d67a 3288 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3289 mwl8k_cmd_radio_disable(hw);
ee03a932 3290 return 0;
7595d67a
LB		 3291 }
3292
ee03a932
LB		 3293 rc = mwl8k_fw_lock(hw);
3294 if (rc)
3295 return rc;
a66098da 3296
55489b6e 3297 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 3298 if (rc)
3299 goto out;
a66098da 3300
610677d2 3301 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 3302 if (rc)
3303 goto out;
3304
a66098da
LB		 3305 if (conf->power_level > 18)
3306 conf->power_level = 18;
55489b6e 3307 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB		 3308 if (rc)
3309 goto out;
a66098da 3310
08b06347
LB		 3311 if (priv->ap_fw) {
3312 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3313 if (!rc)
3314 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3315 } else {
3316 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3317 }
a66098da 3318
ee03a932
LB		 3319out:
3320 mwl8k_fw_unlock(hw);
a66098da 3321
ee03a932 3322 return rc;
a66098da
LB		 3323}
3324
b64fe619
LB		 3325static void
3326mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3327 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3328{
a66098da 3329 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3330 u32 ap_legacy_rates;
13935e2c 3331 u8 ap_mcs_rates[16];
3a980d0a
LB		 3332 int rc;
3333
c3cbbe8a 3334 if (mwl8k_fw_lock(hw))
3a980d0a 3335 return;
a66098da 3336
c3cbbe8a
LB		 3337 /*
3338 * No need to capture a beacon if we're no longer associated.
3339 */
3340 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3341 priv->capture_beacon = false;
3a980d0a 3342
c3cbbe8a 3343 /*
13935e2c 3344 * Get the AP's legacy and MCS rates.
c3cbbe8a 3345 */
7dc6a7a7 3346 if (vif->bss_conf.assoc) {
c6e96010 3347 struct ieee80211_sta *ap;
c97470dd 3348
c6e96010 3349 rcu_read_lock();
c6e96010 3350
c3cbbe8a
LB		 3351 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3352 if (ap == NULL) {
3353 rcu_read_unlock();
c6e96010 3354 goto out;
c3cbbe8a
LB		 3355 }
3356
8707d026
LB		 3357 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
3358 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
3359 } else {
3360 ap_legacy_rates =
3361 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3362 }
13935e2c 3363 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 3364
3365 rcu_read_unlock();
3366 }
c6e96010 3367
c3cbbe8a 3368 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3369 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 3370 if (rc)
3371 goto out;
a66098da 3372
b71ed2c6 3373 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 3374 if (rc)
3375 goto out;
c3cbbe8a 3376 }
a66098da 3377
c3cbbe8a 3378 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 3379 rc = mwl8k_set_radio_preamble(hw,
3380 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 3381 if (rc)
3382 goto out;
c3cbbe8a 3383 }
a66098da 3384
c3cbbe8a 3385 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3386 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 3387 if (rc)
3388 goto out;
c3cbbe8a 3389 }
a66098da 3390
c97470dd
LB		 3391 if (vif->bss_conf.assoc &&
3392 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
3393 BSS_CHANGED_HT))) {
c3cbbe8a 3394 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 3395 if (rc)
3396 goto out;
c3cbbe8a 3397 }
a66098da 3398
c3cbbe8a
LB		 3399 if (vif->bss_conf.assoc &&
3400 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 3401 /*
3402 * Finalize the join. Tell rx handler to process
3403 * next beacon from our BSSID.
3404 */
0a11dfc3 3405 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3406 priv->capture_beacon = true;
a66098da
LB		 3407 }
3408
3a980d0a
LB		 3409out:
3410 mwl8k_fw_unlock(hw);
a66098da
LB		 3411}
3412
b64fe619
LB		 3413static void
3414mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3415 struct ieee80211_bss_conf *info, u32 changed)
3416{
3417 int rc;
3418
3419 if (mwl8k_fw_lock(hw))
3420 return;
3421
3422 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3423 rc = mwl8k_set_radio_preamble(hw,
3424 vif->bss_conf.use_short_preamble);
3425 if (rc)
3426 goto out;
3427 }
3428
3429 if (changed & BSS_CHANGED_BASIC_RATES) {
3430 int idx;
3431 int rate;
3432
3433 /*
3434 * Use lowest supported basic rate for multicasts
3435 * and management frames (such as probe responses --
3436 * beacons will always go out at 1 Mb/s).
3437 */
3438 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 3439 if (idx)
3440 idx--;
3441
3442 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3443 rate = mwl8k_rates_24[idx].hw_value;
3444 else
3445 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 3446
3447 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3448 }
3449
3450 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3451 struct sk_buff *skb;
3452
3453 skb = ieee80211_beacon_get(hw, vif);
3454 if (skb != NULL) {
3455 mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
3456 kfree_skb(skb);
3457 }
3458 }
3459
3460 if (changed & BSS_CHANGED_BEACON_ENABLED)
3461 mwl8k_cmd_bss_start(hw, info->enable_beacon);
3462
3463out:
3464 mwl8k_fw_unlock(hw);
3465}
3466
3467static void
3468mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3469 struct ieee80211_bss_conf *info, u32 changed)
3470{
3471 struct mwl8k_priv *priv = hw->priv;
3472
3473 if (!priv->ap_fw)
3474 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3475 else
3476 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3477}
3478
e81cd2d6
LB		 3479static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3480 int mc_count, struct dev_addr_list *mclist)
3481{
3482 struct mwl8k_cmd_pkt *cmd;
3483
447ced07
LB		 3484 /*
3485 * Synthesize and return a command packet that programs the
3486 * hardware multicast address filter. At this point we don't
3487 * know whether FIF_ALLMULTI is being requested, but if it is,
3488 * we'll end up throwing this packet away and creating a new
3489 * one in mwl8k_configure_filter().
3490 */
3491 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3492
3493 return (unsigned long)cmd;
3494}
3495
a43c49a8
LB		 3496static int
3497mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3498 unsigned int changed_flags,
3499 unsigned int *total_flags)
3500{
3501 struct mwl8k_priv *priv = hw->priv;
3502
3503 /*
3504 * Hardware sniffer mode is mutually exclusive with STA
3505 * operation, so refuse to enable sniffer mode if a STA
3506 * interface is active.
3507 */
3508 if (priv->vif != NULL) {
3509 if (net_ratelimit())
3510 printk(KERN_INFO "%s: not enabling sniffer "
3511 "mode because STA interface is active\n",
3512 wiphy_name(hw->wiphy));
3513 return 0;
3514 }
3515
3516 if (!priv->sniffer_enabled) {
55489b6e 3517 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3518 return 0;
3519 priv->sniffer_enabled = true;
3520 }
3521
3522 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3523 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3524 FIF_OTHER_BSS;
3525
3526 return 1;
3527}
3528
e6935ea1
LB		 3529static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3530 unsigned int changed_flags,
3531 unsigned int *total_flags,
3532 u64 multicast)
3533{
3534 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3535 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3536
c0adae2c
LB		 3537 /*
3538 * AP firmware doesn't allow fine-grained control over
3539 * the receive filter.
3540 */
3541 if (priv->ap_fw) {
3542 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3543 kfree(cmd);
3544 return;
3545 }
3546
a43c49a8
LB		 3547 /*
3548 * Enable hardware sniffer mode if FIF_CONTROL or
3549 * FIF_OTHER_BSS is requested.
3550 */
3551 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3552 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3553 kfree(cmd);
3554 return;
3555 }
a66098da 3556
e6935ea1 3557 /* Clear unsupported feature flags */
447ced07 3558 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3559
90852f7a
LB		 3560 if (mwl8k_fw_lock(hw)) {
3561 kfree(cmd);
e6935ea1 3562 return;
90852f7a 3563 }
a66098da 3564
a43c49a8 3565 if (priv->sniffer_enabled) {
55489b6e 3566 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3567 priv->sniffer_enabled = false;
3568 }
3569
e6935ea1 3570 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3571 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3572 /*
3573 * Disable the BSS filter.
3574 */
e6935ea1 3575 mwl8k_cmd_set_pre_scan(hw);
77165d88 3576 } else {
0a11dfc3 3577 const u8 *bssid;
a94cc97e 3578
77165d88
LB		 3579 /*
3580 * Enable the BSS filter.
3581 *
3582 * If there is an active STA interface, use that
3583 * interface's BSSID, otherwise use a dummy one
3584 * (where the OUI part needs to be nonzero for
3585 * the BSSID to be accepted by POST_SCAN).
3586 */
3587 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3588 if (priv->vif != NULL)
0a11dfc3 3589 bssid = priv->vif->bss_conf.bssid;
a94cc97e 3590
e6935ea1 3591 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3592 }
3593 }
3594
447ced07
LB		 3595 /*
3596 * If FIF_ALLMULTI is being requested, throw away the command
3597 * packet that ->prepare_multicast() built and replace it with
3598 * a command packet that enables reception of all multicast
3599 * packets.
3600 */
3601 if (*total_flags & FIF_ALLMULTI) {
3602 kfree(cmd);
3603 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3604 }
3605
3606 if (cmd != NULL) {
3607 mwl8k_post_cmd(hw, cmd);
3608 kfree(cmd);
e6935ea1 3609 }
a66098da 3610
e6935ea1 3611 mwl8k_fw_unlock(hw);
a66098da
LB		 3612}
3613
a66098da
LB		 3614static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3615{
c2c2b12a 3616 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 3617}
3618
bbfd9128
LB		 3619struct mwl8k_sta_notify_item
3620{
3621 struct list_head list;
3622 struct ieee80211_vif *vif;
3623 enum sta_notify_cmd cmd;
13935e2c 3624 struct ieee80211_sta sta;
bbfd9128
LB		 3625};
3626
3f5610ff
LB		 3627static void
3628mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
3629{
3630 struct mwl8k_priv *priv = hw->priv;
3631
3632 /*
3633 * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
3634 */
3635 if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3636 int rc;
3637
3638 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
3639 if (rc >= 0) {
3640 struct ieee80211_sta *sta;
3641
3642 rcu_read_lock();
3643 sta = ieee80211_find_sta(s->vif, s->sta.addr);
3644 if (sta != NULL)
3645 MWL8K_STA(sta)->peer_id = rc;
3646 rcu_read_unlock();
3647 }
3648 } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3649 mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
3650 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3651 mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
3652 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3653 mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
3654 }
3655}
3656
bbfd9128
LB		 3657static void mwl8k_sta_notify_worker(struct work_struct *work)
3658{
3659 struct mwl8k_priv *priv =
3660 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3661 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB		 3662
3663 spin_lock_bh(&priv->sta_notify_list_lock);
3664 while (!list_empty(&priv->sta_notify_list)) {
3665 struct mwl8k_sta_notify_item *s;
bbfd9128
LB		 3666
3667 s = list_entry(priv->sta_notify_list.next,
3668 struct mwl8k_sta_notify_item, list);
3669 list_del(&s->list);
3670
3671 spin_unlock_bh(&priv->sta_notify_list_lock);
3672
3f5610ff 3673 mwl8k_do_sta_notify(hw, s);
bbfd9128
LB		 3674 kfree(s);
3675
3676 spin_lock_bh(&priv->sta_notify_list_lock);
3677 }
3678 spin_unlock_bh(&priv->sta_notify_list_lock);
3679}
3680
3681static void
3682mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3683 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3684{
3685 struct mwl8k_priv *priv = hw->priv;
3686 struct mwl8k_sta_notify_item *s;
3687
3688 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3689 return;
3690
3691 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3692 if (s != NULL) {
3693 s->vif = vif;
3694 s->cmd = cmd;
13935e2c 3695 s->sta = *sta;
bbfd9128
LB		 3696
3697 spin_lock(&priv->sta_notify_list_lock);
3698 list_add_tail(&s->list, &priv->sta_notify_list);
3699 spin_unlock(&priv->sta_notify_list_lock);
3700
3701 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3702 }
3703}
3704
a66098da
LB		 3705static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3706 const struct ieee80211_tx_queue_params *params)
3707{
3e4f542c 3708 struct mwl8k_priv *priv = hw->priv;
a66098da 3709 int rc;
a66098da 3710
3e4f542c
LB		 3711 rc = mwl8k_fw_lock(hw);
3712 if (!rc) {
3713 if (!priv->wmm_enabled)
55489b6e 3714 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3715
3e4f542c 3716 if (!rc)
55489b6e
LB		 3717 rc = mwl8k_cmd_set_edca_params(hw, queue,
3718 params->cw_min,
3719 params->cw_max,
3720 params->aifs,
3721 params->txop);
3e4f542c
LB		 3722
3723 mwl8k_fw_unlock(hw);
a66098da 3724 }
3e4f542c 3725
a66098da
LB		 3726 return rc;
3727}
3728
3729static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3730 struct ieee80211_tx_queue_stats *stats)
3731{
3732 struct mwl8k_priv *priv = hw->priv;
3733 struct mwl8k_tx_queue *txq;
3734 int index;
3735
3736 spin_lock_bh(&priv->tx_lock);
3737 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3738 txq = priv->txq + index;
45eb400d 3739 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3740 sizeof(struct ieee80211_tx_queue_stats));
3741 }
3742 spin_unlock_bh(&priv->tx_lock);
a66098da 3743
954ef509 3744 return 0;
a66098da
LB		 3745}
3746
3747static int mwl8k_get_stats(struct ieee80211_hw *hw,
3748 struct ieee80211_low_level_stats *stats)
3749{
55489b6e 3750 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 3751}
3752
a2292d83
LB		 3753static int
3754mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3755 enum ieee80211_ampdu_mlme_action action,
3756 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3757{
3758 switch (action) {
3759 case IEEE80211_AMPDU_RX_START:
3760 case IEEE80211_AMPDU_RX_STOP:
3761 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
3762 return -ENOTSUPP;
3763 return 0;
3764 default:
3765 return -ENOTSUPP;
3766 }
3767}
3768
a66098da
LB		 3769static const struct ieee80211_ops mwl8k_ops = {
3770 .tx = mwl8k_tx,
3771 .start = mwl8k_start,
3772 .stop = mwl8k_stop,
3773 .add_interface = mwl8k_add_interface,
3774 .remove_interface = mwl8k_remove_interface,
3775 .config = mwl8k_config,
a66098da 3776 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3777 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3778 .configure_filter = mwl8k_configure_filter,
3779 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3780 .sta_notify = mwl8k_sta_notify,
a66098da
LB		 3781 .conf_tx = mwl8k_conf_tx,
3782 .get_tx_stats = mwl8k_get_tx_stats,
3783 .get_stats = mwl8k_get_stats,
a2292d83 3784 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 3785};
3786
a66098da
LB		 3787static void mwl8k_finalize_join_worker(struct work_struct *work)
3788{
3789 struct mwl8k_priv *priv =
3790 container_of(work, struct mwl8k_priv, finalize_join_worker);
3791 struct sk_buff *skb = priv->beacon_skb;
a66098da 3792
7dc6a7a7
LB		 3793 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3794 priv->vif->bss_conf.dtim_period);
a66098da
LB		 3795 dev_kfree_skb(skb);
3796
3797 priv->beacon_skb = NULL;
3798}
3799
bcb628d5 3800enum {
9e1b17ea
LB		 3801 MWL8363 = 0,
3802 MWL8687,
bcb628d5 3803 MWL8366,
6f6d1e9a
LB		 3804};
3805
bcb628d5 3806static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 3807 [MWL8363] = {
3808 .part_name = "88w8363",
3809 .helper_image = "mwl8k/helper_8363.fw",
3810 .fw_image = "mwl8k/fmimage_8363.fw",
3811 },
49eb691c 3812 [MWL8687] = {
bcb628d5
JL		 3813 .part_name = "88w8687",
3814 .helper_image = "mwl8k/helper_8687.fw",
3815 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3816 },
49eb691c 3817 [MWL8366] = {
bcb628d5
JL		 3818 .part_name = "88w8366",
3819 .helper_image = "mwl8k/helper_8366.fw",
3820 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3821 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3822 },
45a390dd
LB		 3823};
3824
c92d4ede
LB		 3825MODULE_FIRMWARE("mwl8k/helper_8363.fw");
3826MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
3827MODULE_FIRMWARE("mwl8k/helper_8687.fw");
3828MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
3829MODULE_FIRMWARE("mwl8k/helper_8366.fw");
3830MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
3831
45a390dd 3832static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
9e1b17ea
LB		 3833 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
3834 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 3835 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3836 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3837 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 3838 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 3839 { },
45a390dd
LB		 3840};
3841MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3842
a66098da
LB		 3843static int __devinit mwl8k_probe(struct pci_dev *pdev,
3844 const struct pci_device_id *id)
3845{
2aa7b01f 3846 static int printed_version = 0;
a66098da
LB		 3847 struct ieee80211_hw *hw;
3848 struct mwl8k_priv *priv;
a66098da
LB		 3849 int rc;
3850 int i;
2aa7b01f
LB		 3851
3852 if (!printed_version) {
3853 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3854 printed_version = 1;
3855 }
a66098da 3856
be695fc4 3857
a66098da
LB		 3858 rc = pci_enable_device(pdev);
3859 if (rc) {
3860 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3861 MWL8K_NAME);
3862 return rc;
3863 }
3864
3865 rc = pci_request_regions(pdev, MWL8K_NAME);
3866 if (rc) {
3867 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3868 MWL8K_NAME);
3db95e50 3869 goto err_disable_device;
a66098da
LB		 3870 }
3871
3872 pci_set_master(pdev);
3873
be695fc4 3874
a66098da
LB		 3875 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3876 if (hw == NULL) {
3877 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3878 rc = -ENOMEM;
3879 goto err_free_reg;
3880 }
3881
be695fc4
LB		 3882 SET_IEEE80211_DEV(hw, &pdev->dev);
3883 pci_set_drvdata(pdev, hw);
3884
a66098da
LB		 3885 priv = hw->priv;
3886 priv->hw = hw;
3887 priv->pdev = pdev;
bcb628d5 3888 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3889
a66098da 3890
5b9482dd
LB		 3891 priv->sram = pci_iomap(pdev, 0, 0x10000);
3892 if (priv->sram == NULL) {
3893 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3894 wiphy_name(hw->wiphy));
a66098da
LB		 3895 goto err_iounmap;
3896 }
3897
5b9482dd
LB		 3898 /*
3899 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3900 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3901 */
3902 priv->regs = pci_iomap(pdev, 1, 0x10000);
3903 if (priv->regs == NULL) {
3904 priv->regs = pci_iomap(pdev, 2, 0x10000);
3905 if (priv->regs == NULL) {
3906 printk(KERN_ERR "%s: Cannot map device registers\n",
3907 wiphy_name(hw->wiphy));
3908 goto err_iounmap;
3909 }
3910 }
3911
be695fc4
LB		 3912
3913 /* Reset firmware and hardware */
3914 mwl8k_hw_reset(priv);
3915
3916 /* Ask userland hotplug daemon for the device firmware */
3917 rc = mwl8k_request_firmware(priv);
3918 if (rc) {
3919 printk(KERN_ERR "%s: Firmware files not found\n",
3920 wiphy_name(hw->wiphy));
3921 goto err_stop_firmware;
3922 }
3923
3924 /* Load firmware into hardware */
3925 rc = mwl8k_load_firmware(hw);
3926 if (rc) {
3927 printk(KERN_ERR "%s: Cannot start firmware\n",
3928 wiphy_name(hw->wiphy));
3929 goto err_stop_firmware;
3930 }
3931
3932 /* Reclaim memory once firmware is successfully loaded */
3933 mwl8k_release_firmware(priv);
3934
3935
91942230 3936 if (priv->ap_fw) {
89a91f4f 3937 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB		 3938 if (priv->rxd_ops == NULL) {
3939 printk(KERN_ERR "%s: Driver does not have AP "
3940 "firmware image support for this hardware\n",
3941 wiphy_name(hw->wiphy));
3942 goto err_stop_firmware;
3943 }
3944 } else {
89a91f4f 3945 priv->rxd_ops = &rxd_sta_ops;
91942230 3946 }
be695fc4
LB		 3947
3948 priv->sniffer_enabled = false;
3949 priv->wmm_enabled = false;
3950 priv->pending_tx_pkts = 0;
3951
3952
a66098da
LB		 3953 /*
3954 * Extra headroom is the size of the required DMA header
3955 * minus the size of the smallest 802.11 frame (CTS frame).
3956 */
3957 hw->extra_tx_headroom =
3958 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3959
3960 hw->channel_change_time = 10;
3961
3962 hw->queues = MWL8K_TX_QUEUES;
3963
a66098da 3964 /* Set rssi and noise values to dBm */
ce9e2e1b 3965 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 3966 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 3967 hw->sta_data_size = sizeof(struct mwl8k_sta);
a66098da
LB		 3968 priv->vif = NULL;
3969
3970 /* Set default radio state and preamble */
c46563b7 3971 priv->radio_on = 0;
68ce3884 3972 priv->radio_short_preamble = 0;
a66098da 3973
bbfd9128
LB		 3974 /* Station database handling */
3975 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3976 spin_lock_init(&priv->sta_notify_list_lock);
3977 INIT_LIST_HEAD(&priv->sta_notify_list);
3978
a66098da
LB		 3979 /* Finalize join worker */
3980 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3981
67e2eb27 3982 /* TX reclaim and RX tasklets. */
1e9f9de3
LB		 3983 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
3984 tasklet_disable(&priv->poll_tx_task);
67e2eb27
LB		 3985 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
3986 tasklet_disable(&priv->poll_rx_task);
a66098da 3987
a66098da
LB		 3988 /* Power management cookie */
3989 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3990 if (priv->cookie == NULL)
be695fc4 3991 goto err_stop_firmware;
a66098da
LB		 3992
3993 rc = mwl8k_rxq_init(hw, 0);
3994 if (rc)
be695fc4 3995 goto err_free_cookie;
a66098da
LB		 3996 rxq_refill(hw, 0, INT_MAX);
3997
618952a7
LB		 3998 mutex_init(&priv->fw_mutex);
3999 priv->fw_mutex_owner = NULL;
4000 priv->fw_mutex_depth = 0;
618952a7
LB		 4001 priv->hostcmd_wait = NULL;
4002
a66098da
LB		 4003 spin_lock_init(&priv->tx_lock);
4004
88de754a
LB		 4005 priv->tx_wait = NULL;
4006
a66098da
LB		 4007 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
4008 rc = mwl8k_txq_init(hw, i);
4009 if (rc)
4010 goto err_free_queues;
4011 }
4012
4013 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 4014 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 4015 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 4016 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 4017 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4018
a0607fd3 4019 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4020 IRQF_SHARED, MWL8K_NAME, hw);
4021 if (rc) {
4022 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 4023 wiphy_name(hw->wiphy));
a66098da
LB		 4024 goto err_free_queues;
4025 }
4026
a66098da
LB		 4027 /*
4028 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 4029 * commands use interrupts and avoid polling. Disable
a66098da
LB		 4030 * interrupts when done.
4031 */
c23b5a69 4032 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4033
4034 /* Get config data, mac addrs etc */
42fba21d
LB		 4035 if (priv->ap_fw) {
4036 rc = mwl8k_cmd_get_hw_spec_ap(hw);
4037 if (!rc)
4038 rc = mwl8k_cmd_set_hw_spec(hw);
b64fe619
LB		 4039
4040 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
42fba21d
LB		 4041 } else {
4042 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB		 4043
4044 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 4045 }
a66098da 4046 if (rc) {
c2c357ce
LB		 4047 printk(KERN_ERR "%s: Cannot initialise firmware\n",
4048 wiphy_name(hw->wiphy));
be695fc4 4049 goto err_free_irq;
a66098da
LB		 4050 }
4051
4052 /* Turn radio off */
55489b6e 4053 rc = mwl8k_cmd_radio_disable(hw);
a66098da 4054 if (rc) {
c2c357ce 4055 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 4056 goto err_free_irq;
a66098da
LB		 4057 }
4058
32060e1b 4059 /* Clear MAC address */
55489b6e 4060 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB		 4061 if (rc) {
4062 printk(KERN_ERR "%s: Cannot clear MAC address\n",
4063 wiphy_name(hw->wiphy));
be695fc4 4064 goto err_free_irq;
32060e1b
LB		 4065 }
4066
a66098da 4067 /* Disable interrupts */
a66098da 4068 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4069 free_irq(priv->pdev->irq, hw);
4070
4071 rc = ieee80211_register_hw(hw);
4072 if (rc) {
c2c357ce
LB		 4073 printk(KERN_ERR "%s: Cannot register device\n",
4074 wiphy_name(hw->wiphy));
153458ff 4075 goto err_free_queues;
a66098da
LB		 4076 }
4077
eae74e65 4078 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 4079 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 4080 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 4081 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 4082 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
4083 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 4084
4085 return 0;
4086
a66098da 4087err_free_irq:
a66098da 4088 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4089 free_irq(priv->pdev->irq, hw);
4090
4091err_free_queues:
4092 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4093 mwl8k_txq_deinit(hw, i);
4094 mwl8k_rxq_deinit(hw, 0);
4095
be695fc4 4096err_free_cookie:
a66098da
LB		 4097 if (priv->cookie != NULL)
4098 pci_free_consistent(priv->pdev, 4,
4099 priv->cookie, priv->cookie_dma);
4100
be695fc4
LB		 4101err_stop_firmware:
4102 mwl8k_hw_reset(priv);
4103 mwl8k_release_firmware(priv);
4104
4105err_iounmap:
a66098da
LB		 4106 if (priv->regs != NULL)
4107 pci_iounmap(pdev, priv->regs);
4108
5b9482dd
LB		 4109 if (priv->sram != NULL)
4110 pci_iounmap(pdev, priv->sram);
4111
a66098da
LB		 4112 pci_set_drvdata(pdev, NULL);
4113 ieee80211_free_hw(hw);
4114
4115err_free_reg:
4116 pci_release_regions(pdev);
3db95e50
LB		 4117
4118err_disable_device:
a66098da
LB		 4119 pci_disable_device(pdev);
4120
4121 return rc;
4122}
4123
230f7af0 4124static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 4125{
4126 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4127}
4128
230f7af0 4129static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 4130{
4131 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4132 struct mwl8k_priv *priv;
4133 int i;
4134
4135 if (hw == NULL)
4136 return;
4137 priv = hw->priv;
4138
4139 ieee80211_stop_queues(hw);
4140
60aa569f
LB		 4141 ieee80211_unregister_hw(hw);
4142
67e2eb27 4143 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4144 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4145 tasklet_kill(&priv->poll_rx_task);
a66098da 4146
a66098da
LB		 4147 /* Stop hardware */
4148 mwl8k_hw_reset(priv);
4149
4150 /* Return all skbs to mac80211 */
4151 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4152 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4153
a66098da
LB		 4154 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4155 mwl8k_txq_deinit(hw, i);
4156
4157 mwl8k_rxq_deinit(hw, 0);
4158
c2c357ce 4159 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 4160
4161 pci_iounmap(pdev, priv->regs);
5b9482dd 4162 pci_iounmap(pdev, priv->sram);
a66098da
LB		 4163 pci_set_drvdata(pdev, NULL);
4164 ieee80211_free_hw(hw);
4165 pci_release_regions(pdev);
4166 pci_disable_device(pdev);
4167}
4168
4169static struct pci_driver mwl8k_driver = {
4170 .name = MWL8K_NAME,
45a390dd 4171 .id_table = mwl8k_pci_id_table,
a66098da
LB		 4172 .probe = mwl8k_probe,
4173 .remove = __devexit_p(mwl8k_remove),
4174 .shutdown = __devexit_p(mwl8k_shutdown),
4175};
4176
4177static int __init mwl8k_init(void)
4178{
4179 return pci_register_driver(&mwl8k_driver);
4180}
4181
4182static void __exit mwl8k_exit(void)
4183{
4184 pci_unregister_driver(&mwl8k_driver);
4185}
4186
4187module_init(mwl8k_init);
4188module_exit(mwl8k_exit);
c2c357ce
LB		 4189
4190MODULE_DESCRIPTION(MWL8K_DESC);
4191MODULE_VERSION(MWL8K_VERSION);
4192MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4193MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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