Commit | Line | Data |
---|---|---|
a66098da | 1 | /* |
ce9e2e1b LB |
2 | * drivers/net/wireless/mwl8k.c |
3 | * Driver for Marvell TOPDOG 802.11 Wireless cards | |
a66098da | 4 | * |
a145d575 | 5 | * Copyright (C) 2008-2009 Marvell Semiconductor Inc. |
a66098da LB |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
3d76e82c | 15 | #include <linux/sched.h> |
a66098da LB |
16 | #include <linux/spinlock.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/etherdevice.h> | |
22 | #include <net/mac80211.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/firmware.h> | |
25 | #include <linux/workqueue.h> | |
26 | ||
27 | #define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver" | |
28 | #define MWL8K_NAME KBUILD_MODNAME | |
6976b665 | 29 | #define MWL8K_VERSION "0.11" |
a66098da | 30 | |
a66098da LB |
31 | /* Register definitions */ |
32 | #define MWL8K_HIU_GEN_PTR 0x00000c10 | |
ce9e2e1b LB |
33 | #define MWL8K_MODE_STA 0x0000005a |
34 | #define MWL8K_MODE_AP 0x000000a5 | |
a66098da | 35 | #define MWL8K_HIU_INT_CODE 0x00000c14 |
ce9e2e1b LB |
36 | #define MWL8K_FWSTA_READY 0xf0f1f2f4 |
37 | #define MWL8K_FWAP_READY 0xf1f2f4a5 | |
38 | #define MWL8K_INT_CODE_CMD_FINISHED 0x00000005 | |
a66098da LB |
39 | #define MWL8K_HIU_SCRATCH 0x00000c40 |
40 | ||
41 | /* Host->device communications */ | |
42 | #define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18 | |
43 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c | |
44 | #define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20 | |
45 | #define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24 | |
46 | #define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28 | |
ce9e2e1b LB |
47 | #define MWL8K_H2A_INT_DUMMY (1 << 20) |
48 | #define MWL8K_H2A_INT_RESET (1 << 15) | |
49 | #define MWL8K_H2A_INT_DOORBELL (1 << 1) | |
50 | #define MWL8K_H2A_INT_PPA_READY (1 << 0) | |
a66098da LB |
51 | |
52 | /* Device->host communications */ | |
53 | #define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c | |
54 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30 | |
55 | #define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34 | |
56 | #define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38 | |
57 | #define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c | |
ce9e2e1b LB |
58 | #define MWL8K_A2H_INT_DUMMY (1 << 20) |
59 | #define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11) | |
60 | #define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10) | |
61 | #define MWL8K_A2H_INT_RADAR_DETECT (1 << 7) | |
62 | #define MWL8K_A2H_INT_RADIO_ON (1 << 6) | |
63 | #define MWL8K_A2H_INT_RADIO_OFF (1 << 5) | |
64 | #define MWL8K_A2H_INT_MAC_EVENT (1 << 3) | |
65 | #define MWL8K_A2H_INT_OPC_DONE (1 << 2) | |
66 | #define MWL8K_A2H_INT_RX_READY (1 << 1) | |
67 | #define MWL8K_A2H_INT_TX_DONE (1 << 0) | |
a66098da LB |
68 | |
69 | #define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \ | |
70 | MWL8K_A2H_INT_CHNL_SWITCHED | \ | |
71 | MWL8K_A2H_INT_QUEUE_EMPTY | \ | |
72 | MWL8K_A2H_INT_RADAR_DETECT | \ | |
73 | MWL8K_A2H_INT_RADIO_ON | \ | |
74 | MWL8K_A2H_INT_RADIO_OFF | \ | |
75 | MWL8K_A2H_INT_MAC_EVENT | \ | |
76 | MWL8K_A2H_INT_OPC_DONE | \ | |
77 | MWL8K_A2H_INT_RX_READY | \ | |
78 | MWL8K_A2H_INT_TX_DONE) | |
79 | ||
a66098da LB |
80 | #define MWL8K_RX_QUEUES 1 |
81 | #define MWL8K_TX_QUEUES 4 | |
82 | ||
54bc3a0d LB |
83 | struct rxd_ops { |
84 | int rxd_size; | |
85 | void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr); | |
86 | void (*rxd_refill)(void *rxd, dma_addr_t addr, int len); | |
20f09c3d LB |
87 | int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status, |
88 | __le16 *qos); | |
54bc3a0d LB |
89 | }; |
90 | ||
45a390dd | 91 | struct mwl8k_device_info { |
a74b295e LB |
92 | char *part_name; |
93 | char *helper_image; | |
94 | char *fw_image; | |
89a91f4f | 95 | struct rxd_ops *ap_rxd_ops; |
45a390dd LB |
96 | }; |
97 | ||
a66098da | 98 | struct mwl8k_rx_queue { |
45eb400d | 99 | int rxd_count; |
a66098da LB |
100 | |
101 | /* hw receives here */ | |
45eb400d | 102 | int head; |
a66098da LB |
103 | |
104 | /* refill descs here */ | |
45eb400d | 105 | int tail; |
a66098da | 106 | |
54bc3a0d | 107 | void *rxd; |
45eb400d | 108 | dma_addr_t rxd_dma; |
788838eb LB |
109 | struct { |
110 | struct sk_buff *skb; | |
111 | DECLARE_PCI_UNMAP_ADDR(dma) | |
112 | } *buf; | |
a66098da LB |
113 | }; |
114 | ||
a66098da LB |
115 | struct mwl8k_tx_queue { |
116 | /* hw transmits here */ | |
45eb400d | 117 | int head; |
a66098da LB |
118 | |
119 | /* sw appends here */ | |
45eb400d | 120 | int tail; |
a66098da | 121 | |
45eb400d LB |
122 | struct ieee80211_tx_queue_stats stats; |
123 | struct mwl8k_tx_desc *txd; | |
124 | dma_addr_t txd_dma; | |
125 | struct sk_buff **skb; | |
a66098da LB |
126 | }; |
127 | ||
a66098da | 128 | struct mwl8k_priv { |
a66098da | 129 | struct ieee80211_hw *hw; |
a66098da | 130 | struct pci_dev *pdev; |
a66098da | 131 | |
45a390dd LB |
132 | struct mwl8k_device_info *device_info; |
133 | ||
be695fc4 LB |
134 | void __iomem *sram; |
135 | void __iomem *regs; | |
136 | ||
137 | /* firmware */ | |
22be40d9 LB |
138 | struct firmware *fw_helper; |
139 | struct firmware *fw_ucode; | |
a66098da | 140 | |
be695fc4 LB |
141 | /* hardware/firmware parameters */ |
142 | bool ap_fw; | |
143 | struct rxd_ops *rxd_ops; | |
144 | ||
618952a7 LB |
145 | /* firmware access */ |
146 | struct mutex fw_mutex; | |
147 | struct task_struct *fw_mutex_owner; | |
148 | int fw_mutex_depth; | |
618952a7 LB |
149 | struct completion *hostcmd_wait; |
150 | ||
a66098da LB |
151 | /* lock held over TX and TX reap */ |
152 | spinlock_t tx_lock; | |
a66098da | 153 | |
88de754a LB |
154 | /* TX quiesce completion, protected by fw_mutex and tx_lock */ |
155 | struct completion *tx_wait; | |
156 | ||
a66098da | 157 | struct ieee80211_vif *vif; |
a66098da LB |
158 | |
159 | struct ieee80211_channel *current_channel; | |
160 | ||
161 | /* power management status cookie from firmware */ | |
162 | u32 *cookie; | |
163 | dma_addr_t cookie_dma; | |
164 | ||
165 | u16 num_mcaddrs; | |
a66098da | 166 | u8 hw_rev; |
2aa7b01f | 167 | u32 fw_rev; |
a66098da LB |
168 | |
169 | /* | |
170 | * Running count of TX packets in flight, to avoid | |
171 | * iterating over the transmit rings each time. | |
172 | */ | |
173 | int pending_tx_pkts; | |
174 | ||
175 | struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES]; | |
176 | struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES]; | |
177 | ||
178 | /* PHY parameters */ | |
179 | struct ieee80211_supported_band band; | |
180 | struct ieee80211_channel channels[14]; | |
140eb5e2 | 181 | struct ieee80211_rate rates[14]; |
a66098da | 182 | |
c46563b7 | 183 | bool radio_on; |
68ce3884 | 184 | bool radio_short_preamble; |
a43c49a8 | 185 | bool sniffer_enabled; |
0439b1f5 | 186 | bool wmm_enabled; |
a66098da | 187 | |
bbfd9128 LB |
188 | struct work_struct sta_notify_worker; |
189 | spinlock_t sta_notify_list_lock; | |
190 | struct list_head sta_notify_list; | |
191 | ||
a66098da LB |
192 | /* XXX need to convert this to handle multiple interfaces */ |
193 | bool capture_beacon; | |
d89173f2 | 194 | u8 capture_bssid[ETH_ALEN]; |
a66098da LB |
195 | struct sk_buff *beacon_skb; |
196 | ||
197 | /* | |
198 | * This FJ worker has to be global as it is scheduled from the | |
199 | * RX handler. At this point we don't know which interface it | |
200 | * belongs to until the list of bssids waiting to complete join | |
201 | * is checked. | |
202 | */ | |
203 | struct work_struct finalize_join_worker; | |
204 | ||
205 | /* Tasklet to reclaim TX descriptors and buffers after tx */ | |
206 | struct tasklet_struct tx_reclaim_task; | |
a66098da LB |
207 | }; |
208 | ||
209 | /* Per interface specific private data */ | |
210 | struct mwl8k_vif { | |
7dc6a7a7 LB |
211 | /* Local MAC address. */ |
212 | u8 mac_addr[ETH_ALEN]; | |
a66098da | 213 | |
a66098da | 214 | /* Non AMPDU sequence number assigned by driver */ |
a680400e | 215 | u16 seqno; |
a66098da | 216 | }; |
a94cc97e | 217 | #define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv)) |
a66098da | 218 | |
a680400e LB |
219 | struct mwl8k_sta { |
220 | /* Index into station database. Returned by UPDATE_STADB. */ | |
221 | u8 peer_id; | |
222 | }; | |
223 | #define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv)) | |
224 | ||
a66098da LB |
225 | static const struct ieee80211_channel mwl8k_channels[] = { |
226 | { .center_freq = 2412, .hw_value = 1, }, | |
227 | { .center_freq = 2417, .hw_value = 2, }, | |
228 | { .center_freq = 2422, .hw_value = 3, }, | |
229 | { .center_freq = 2427, .hw_value = 4, }, | |
230 | { .center_freq = 2432, .hw_value = 5, }, | |
231 | { .center_freq = 2437, .hw_value = 6, }, | |
232 | { .center_freq = 2442, .hw_value = 7, }, | |
233 | { .center_freq = 2447, .hw_value = 8, }, | |
234 | { .center_freq = 2452, .hw_value = 9, }, | |
235 | { .center_freq = 2457, .hw_value = 10, }, | |
236 | { .center_freq = 2462, .hw_value = 11, }, | |
647ca6b0 LB |
237 | { .center_freq = 2467, .hw_value = 12, }, |
238 | { .center_freq = 2472, .hw_value = 13, }, | |
239 | { .center_freq = 2484, .hw_value = 14, }, | |
a66098da LB |
240 | }; |
241 | ||
242 | static const struct ieee80211_rate mwl8k_rates[] = { | |
243 | { .bitrate = 10, .hw_value = 2, }, | |
244 | { .bitrate = 20, .hw_value = 4, }, | |
245 | { .bitrate = 55, .hw_value = 11, }, | |
5dfd3e2c LB |
246 | { .bitrate = 110, .hw_value = 22, }, |
247 | { .bitrate = 220, .hw_value = 44, }, | |
a66098da LB |
248 | { .bitrate = 60, .hw_value = 12, }, |
249 | { .bitrate = 90, .hw_value = 18, }, | |
a66098da LB |
250 | { .bitrate = 120, .hw_value = 24, }, |
251 | { .bitrate = 180, .hw_value = 36, }, | |
252 | { .bitrate = 240, .hw_value = 48, }, | |
253 | { .bitrate = 360, .hw_value = 72, }, | |
254 | { .bitrate = 480, .hw_value = 96, }, | |
255 | { .bitrate = 540, .hw_value = 108, }, | |
140eb5e2 LB |
256 | { .bitrate = 720, .hw_value = 144, }, |
257 | }; | |
258 | ||
a66098da LB |
259 | /* Set or get info from Firmware */ |
260 | #define MWL8K_CMD_SET 0x0001 | |
261 | #define MWL8K_CMD_GET 0x0000 | |
262 | ||
263 | /* Firmware command codes */ | |
264 | #define MWL8K_CMD_CODE_DNLD 0x0001 | |
265 | #define MWL8K_CMD_GET_HW_SPEC 0x0003 | |
42fba21d | 266 | #define MWL8K_CMD_SET_HW_SPEC 0x0004 |
a66098da LB |
267 | #define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010 |
268 | #define MWL8K_CMD_GET_STAT 0x0014 | |
ff45fc60 LB |
269 | #define MWL8K_CMD_RADIO_CONTROL 0x001c |
270 | #define MWL8K_CMD_RF_TX_POWER 0x001e | |
08b06347 | 271 | #define MWL8K_CMD_RF_ANTENNA 0x0020 |
a66098da LB |
272 | #define MWL8K_CMD_SET_PRE_SCAN 0x0107 |
273 | #define MWL8K_CMD_SET_POST_SCAN 0x0108 | |
ff45fc60 LB |
274 | #define MWL8K_CMD_SET_RF_CHANNEL 0x010a |
275 | #define MWL8K_CMD_SET_AID 0x010d | |
276 | #define MWL8K_CMD_SET_RATE 0x0110 | |
277 | #define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111 | |
278 | #define MWL8K_CMD_RTS_THRESHOLD 0x0113 | |
a66098da | 279 | #define MWL8K_CMD_SET_SLOT 0x0114 |
ff45fc60 LB |
280 | #define MWL8K_CMD_SET_EDCA_PARAMS 0x0115 |
281 | #define MWL8K_CMD_SET_WMM_MODE 0x0123 | |
a66098da | 282 | #define MWL8K_CMD_MIMO_CONFIG 0x0125 |
ff45fc60 | 283 | #define MWL8K_CMD_USE_FIXED_RATE 0x0126 |
a66098da | 284 | #define MWL8K_CMD_ENABLE_SNIFFER 0x0150 |
32060e1b | 285 | #define MWL8K_CMD_SET_MAC_ADDR 0x0202 |
a66098da | 286 | #define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203 |
ff45fc60 | 287 | #define MWL8K_CMD_UPDATE_STADB 0x1123 |
a66098da LB |
288 | |
289 | static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize) | |
290 | { | |
291 | #define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\ | |
292 | snprintf(buf, bufsize, "%s", #x);\ | |
293 | return buf;\ | |
294 | } while (0) | |
ce9e2e1b | 295 | switch (cmd & ~0x8000) { |
a66098da LB |
296 | MWL8K_CMDNAME(CODE_DNLD); |
297 | MWL8K_CMDNAME(GET_HW_SPEC); | |
42fba21d | 298 | MWL8K_CMDNAME(SET_HW_SPEC); |
a66098da LB |
299 | MWL8K_CMDNAME(MAC_MULTICAST_ADR); |
300 | MWL8K_CMDNAME(GET_STAT); | |
301 | MWL8K_CMDNAME(RADIO_CONTROL); | |
302 | MWL8K_CMDNAME(RF_TX_POWER); | |
08b06347 | 303 | MWL8K_CMDNAME(RF_ANTENNA); |
a66098da LB |
304 | MWL8K_CMDNAME(SET_PRE_SCAN); |
305 | MWL8K_CMDNAME(SET_POST_SCAN); | |
306 | MWL8K_CMDNAME(SET_RF_CHANNEL); | |
ff45fc60 LB |
307 | MWL8K_CMDNAME(SET_AID); |
308 | MWL8K_CMDNAME(SET_RATE); | |
309 | MWL8K_CMDNAME(SET_FINALIZE_JOIN); | |
310 | MWL8K_CMDNAME(RTS_THRESHOLD); | |
a66098da | 311 | MWL8K_CMDNAME(SET_SLOT); |
ff45fc60 LB |
312 | MWL8K_CMDNAME(SET_EDCA_PARAMS); |
313 | MWL8K_CMDNAME(SET_WMM_MODE); | |
a66098da | 314 | MWL8K_CMDNAME(MIMO_CONFIG); |
ff45fc60 | 315 | MWL8K_CMDNAME(USE_FIXED_RATE); |
a66098da | 316 | MWL8K_CMDNAME(ENABLE_SNIFFER); |
32060e1b | 317 | MWL8K_CMDNAME(SET_MAC_ADDR); |
a66098da | 318 | MWL8K_CMDNAME(SET_RATEADAPT_MODE); |
ff45fc60 | 319 | MWL8K_CMDNAME(UPDATE_STADB); |
a66098da LB |
320 | default: |
321 | snprintf(buf, bufsize, "0x%x", cmd); | |
322 | } | |
323 | #undef MWL8K_CMDNAME | |
324 | ||
325 | return buf; | |
326 | } | |
327 | ||
328 | /* Hardware and firmware reset */ | |
329 | static void mwl8k_hw_reset(struct mwl8k_priv *priv) | |
330 | { | |
331 | iowrite32(MWL8K_H2A_INT_RESET, | |
332 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
333 | iowrite32(MWL8K_H2A_INT_RESET, | |
334 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
335 | msleep(20); | |
336 | } | |
337 | ||
338 | /* Release fw image */ | |
339 | static void mwl8k_release_fw(struct firmware **fw) | |
340 | { | |
341 | if (*fw == NULL) | |
342 | return; | |
343 | release_firmware(*fw); | |
344 | *fw = NULL; | |
345 | } | |
346 | ||
347 | static void mwl8k_release_firmware(struct mwl8k_priv *priv) | |
348 | { | |
22be40d9 LB |
349 | mwl8k_release_fw(&priv->fw_ucode); |
350 | mwl8k_release_fw(&priv->fw_helper); | |
a66098da LB |
351 | } |
352 | ||
353 | /* Request fw image */ | |
354 | static int mwl8k_request_fw(struct mwl8k_priv *priv, | |
c2c357ce | 355 | const char *fname, struct firmware **fw) |
a66098da LB |
356 | { |
357 | /* release current image */ | |
358 | if (*fw != NULL) | |
359 | mwl8k_release_fw(fw); | |
360 | ||
361 | return request_firmware((const struct firmware **)fw, | |
c2c357ce | 362 | fname, &priv->pdev->dev); |
a66098da LB |
363 | } |
364 | ||
45a390dd | 365 | static int mwl8k_request_firmware(struct mwl8k_priv *priv) |
a66098da | 366 | { |
a74b295e | 367 | struct mwl8k_device_info *di = priv->device_info; |
a66098da LB |
368 | int rc; |
369 | ||
a74b295e | 370 | if (di->helper_image != NULL) { |
22be40d9 | 371 | rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper); |
a74b295e LB |
372 | if (rc) { |
373 | printk(KERN_ERR "%s: Error requesting helper " | |
374 | "firmware file %s\n", pci_name(priv->pdev), | |
375 | di->helper_image); | |
376 | return rc; | |
377 | } | |
a66098da LB |
378 | } |
379 | ||
22be40d9 | 380 | rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode); |
a66098da | 381 | if (rc) { |
c2c357ce | 382 | printk(KERN_ERR "%s: Error requesting firmware file %s\n", |
a74b295e | 383 | pci_name(priv->pdev), di->fw_image); |
22be40d9 | 384 | mwl8k_release_fw(&priv->fw_helper); |
a66098da LB |
385 | return rc; |
386 | } | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
7e75b942 BH |
391 | MODULE_FIRMWARE("mwl8k/helper_8687.fw"); |
392 | MODULE_FIRMWARE("mwl8k/fmimage_8687.fw"); | |
393 | ||
a66098da LB |
394 | struct mwl8k_cmd_pkt { |
395 | __le16 code; | |
396 | __le16 length; | |
397 | __le16 seq_num; | |
398 | __le16 result; | |
399 | char payload[0]; | |
400 | } __attribute__((packed)); | |
401 | ||
402 | /* | |
403 | * Firmware loading. | |
404 | */ | |
405 | static int | |
406 | mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length) | |
407 | { | |
408 | void __iomem *regs = priv->regs; | |
409 | dma_addr_t dma_addr; | |
a66098da LB |
410 | int loops; |
411 | ||
412 | dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE); | |
413 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
414 | return -ENOMEM; | |
415 | ||
416 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
417 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
418 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
419 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
420 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
421 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
422 | ||
a66098da LB |
423 | loops = 1000; |
424 | do { | |
425 | u32 int_code; | |
426 | ||
427 | int_code = ioread32(regs + MWL8K_HIU_INT_CODE); | |
428 | if (int_code == MWL8K_INT_CODE_CMD_FINISHED) { | |
429 | iowrite32(0, regs + MWL8K_HIU_INT_CODE); | |
a66098da LB |
430 | break; |
431 | } | |
432 | ||
3d76e82c | 433 | cond_resched(); |
a66098da LB |
434 | udelay(1); |
435 | } while (--loops); | |
436 | ||
437 | pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE); | |
438 | ||
d4b70570 | 439 | return loops ? 0 : -ETIMEDOUT; |
a66098da LB |
440 | } |
441 | ||
442 | static int mwl8k_load_fw_image(struct mwl8k_priv *priv, | |
443 | const u8 *data, size_t length) | |
444 | { | |
445 | struct mwl8k_cmd_pkt *cmd; | |
446 | int done; | |
447 | int rc = 0; | |
448 | ||
449 | cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL); | |
450 | if (cmd == NULL) | |
451 | return -ENOMEM; | |
452 | ||
453 | cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD); | |
454 | cmd->seq_num = 0; | |
455 | cmd->result = 0; | |
456 | ||
457 | done = 0; | |
458 | while (length) { | |
459 | int block_size = length > 256 ? 256 : length; | |
460 | ||
461 | memcpy(cmd->payload, data + done, block_size); | |
462 | cmd->length = cpu_to_le16(block_size); | |
463 | ||
464 | rc = mwl8k_send_fw_load_cmd(priv, cmd, | |
465 | sizeof(*cmd) + block_size); | |
466 | if (rc) | |
467 | break; | |
468 | ||
469 | done += block_size; | |
470 | length -= block_size; | |
471 | } | |
472 | ||
473 | if (!rc) { | |
474 | cmd->length = 0; | |
475 | rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd)); | |
476 | } | |
477 | ||
478 | kfree(cmd); | |
479 | ||
480 | return rc; | |
481 | } | |
482 | ||
483 | static int mwl8k_feed_fw_image(struct mwl8k_priv *priv, | |
484 | const u8 *data, size_t length) | |
485 | { | |
486 | unsigned char *buffer; | |
487 | int may_continue, rc = 0; | |
488 | u32 done, prev_block_size; | |
489 | ||
490 | buffer = kmalloc(1024, GFP_KERNEL); | |
491 | if (buffer == NULL) | |
492 | return -ENOMEM; | |
493 | ||
494 | done = 0; | |
495 | prev_block_size = 0; | |
496 | may_continue = 1000; | |
497 | while (may_continue > 0) { | |
498 | u32 block_size; | |
499 | ||
500 | block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH); | |
501 | if (block_size & 1) { | |
502 | block_size &= ~1; | |
503 | may_continue--; | |
504 | } else { | |
505 | done += prev_block_size; | |
506 | length -= prev_block_size; | |
507 | } | |
508 | ||
509 | if (block_size > 1024 || block_size > length) { | |
510 | rc = -EOVERFLOW; | |
511 | break; | |
512 | } | |
513 | ||
514 | if (length == 0) { | |
515 | rc = 0; | |
516 | break; | |
517 | } | |
518 | ||
519 | if (block_size == 0) { | |
520 | rc = -EPROTO; | |
521 | may_continue--; | |
522 | udelay(1); | |
523 | continue; | |
524 | } | |
525 | ||
526 | prev_block_size = block_size; | |
527 | memcpy(buffer, data + done, block_size); | |
528 | ||
529 | rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size); | |
530 | if (rc) | |
531 | break; | |
532 | } | |
533 | ||
534 | if (!rc && length != 0) | |
535 | rc = -EREMOTEIO; | |
536 | ||
537 | kfree(buffer); | |
538 | ||
539 | return rc; | |
540 | } | |
541 | ||
c2c357ce | 542 | static int mwl8k_load_firmware(struct ieee80211_hw *hw) |
a66098da | 543 | { |
c2c357ce | 544 | struct mwl8k_priv *priv = hw->priv; |
22be40d9 | 545 | struct firmware *fw = priv->fw_ucode; |
c2c357ce LB |
546 | int rc; |
547 | int loops; | |
548 | ||
549 | if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) { | |
22be40d9 | 550 | struct firmware *helper = priv->fw_helper; |
a66098da | 551 | |
c2c357ce LB |
552 | if (helper == NULL) { |
553 | printk(KERN_ERR "%s: helper image needed but none " | |
554 | "given\n", pci_name(priv->pdev)); | |
555 | return -EINVAL; | |
556 | } | |
a66098da | 557 | |
c2c357ce | 558 | rc = mwl8k_load_fw_image(priv, helper->data, helper->size); |
a66098da LB |
559 | if (rc) { |
560 | printk(KERN_ERR "%s: unable to load firmware " | |
c2c357ce | 561 | "helper image\n", pci_name(priv->pdev)); |
a66098da LB |
562 | return rc; |
563 | } | |
89b872e2 | 564 | msleep(5); |
a66098da | 565 | |
c2c357ce | 566 | rc = mwl8k_feed_fw_image(priv, fw->data, fw->size); |
a66098da | 567 | } else { |
c2c357ce | 568 | rc = mwl8k_load_fw_image(priv, fw->data, fw->size); |
a66098da LB |
569 | } |
570 | ||
571 | if (rc) { | |
c2c357ce LB |
572 | printk(KERN_ERR "%s: unable to load firmware image\n", |
573 | pci_name(priv->pdev)); | |
a66098da LB |
574 | return rc; |
575 | } | |
576 | ||
89a91f4f | 577 | iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR); |
a66098da | 578 | |
89b872e2 | 579 | loops = 500000; |
a66098da | 580 | do { |
eae74e65 LB |
581 | u32 ready_code; |
582 | ||
583 | ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
584 | if (ready_code == MWL8K_FWAP_READY) { | |
585 | priv->ap_fw = 1; | |
586 | break; | |
587 | } else if (ready_code == MWL8K_FWSTA_READY) { | |
588 | priv->ap_fw = 0; | |
a66098da | 589 | break; |
eae74e65 LB |
590 | } |
591 | ||
592 | cond_resched(); | |
a66098da LB |
593 | udelay(1); |
594 | } while (--loops); | |
595 | ||
596 | return loops ? 0 : -ETIMEDOUT; | |
597 | } | |
598 | ||
599 | ||
a66098da LB |
600 | /* DMA header used by firmware and hardware. */ |
601 | struct mwl8k_dma_data { | |
602 | __le16 fwlen; | |
603 | struct ieee80211_hdr wh; | |
20f09c3d | 604 | char data[0]; |
a66098da LB |
605 | } __attribute__((packed)); |
606 | ||
607 | /* Routines to add/remove DMA header from skb. */ | |
20f09c3d | 608 | static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos) |
a66098da | 609 | { |
20f09c3d LB |
610 | struct mwl8k_dma_data *tr; |
611 | int hdrlen; | |
612 | ||
613 | tr = (struct mwl8k_dma_data *)skb->data; | |
614 | hdrlen = ieee80211_hdrlen(tr->wh.frame_control); | |
615 | ||
616 | if (hdrlen != sizeof(tr->wh)) { | |
617 | if (ieee80211_is_data_qos(tr->wh.frame_control)) { | |
618 | memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2); | |
619 | *((__le16 *)(tr->data - 2)) = qos; | |
620 | } else { | |
621 | memmove(tr->data - hdrlen, &tr->wh, hdrlen); | |
622 | } | |
a66098da | 623 | } |
20f09c3d LB |
624 | |
625 | if (hdrlen != sizeof(*tr)) | |
626 | skb_pull(skb, sizeof(*tr) - hdrlen); | |
a66098da LB |
627 | } |
628 | ||
76266b2a | 629 | static inline void mwl8k_add_dma_header(struct sk_buff *skb) |
a66098da LB |
630 | { |
631 | struct ieee80211_hdr *wh; | |
ca009301 | 632 | int hdrlen; |
a66098da LB |
633 | struct mwl8k_dma_data *tr; |
634 | ||
ca009301 LB |
635 | /* |
636 | * Add a firmware DMA header; the firmware requires that we | |
637 | * present a 2-byte payload length followed by a 4-address | |
638 | * header (without QoS field), followed (optionally) by any | |
639 | * WEP/ExtIV header (but only filled in for CCMP). | |
640 | */ | |
a66098da | 641 | wh = (struct ieee80211_hdr *)skb->data; |
ca009301 | 642 | |
a66098da | 643 | hdrlen = ieee80211_hdrlen(wh->frame_control); |
ca009301 LB |
644 | if (hdrlen != sizeof(*tr)) |
645 | skb_push(skb, sizeof(*tr) - hdrlen); | |
a66098da | 646 | |
ca009301 LB |
647 | if (ieee80211_is_data_qos(wh->frame_control)) |
648 | hdrlen -= 2; | |
a66098da LB |
649 | |
650 | tr = (struct mwl8k_dma_data *)skb->data; | |
651 | if (wh != &tr->wh) | |
652 | memmove(&tr->wh, wh, hdrlen); | |
ca009301 LB |
653 | if (hdrlen != sizeof(tr->wh)) |
654 | memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen); | |
a66098da LB |
655 | |
656 | /* | |
657 | * Firmware length is the length of the fully formed "802.11 | |
658 | * payload". That is, everything except for the 802.11 header. | |
659 | * This includes all crypto material including the MIC. | |
660 | */ | |
ca009301 | 661 | tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr)); |
a66098da LB |
662 | } |
663 | ||
664 | ||
665 | /* | |
89a91f4f | 666 | * Packet reception for 88w8366 AP firmware. |
6f6d1e9a | 667 | */ |
89a91f4f | 668 | struct mwl8k_rxd_8366_ap { |
6f6d1e9a LB |
669 | __le16 pkt_len; |
670 | __u8 sq2; | |
671 | __u8 rate; | |
672 | __le32 pkt_phys_addr; | |
673 | __le32 next_rxd_phys_addr; | |
674 | __le16 qos_control; | |
675 | __le16 htsig2; | |
676 | __le32 hw_rssi_info; | |
677 | __le32 hw_noise_floor_info; | |
678 | __u8 noise_floor; | |
679 | __u8 pad0[3]; | |
680 | __u8 rssi; | |
681 | __u8 rx_status; | |
682 | __u8 channel; | |
683 | __u8 rx_ctrl; | |
684 | } __attribute__((packed)); | |
685 | ||
89a91f4f LB |
686 | #define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80 |
687 | #define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40 | |
688 | #define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f) | |
8e9f33f0 | 689 | |
89a91f4f | 690 | #define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80 |
6f6d1e9a | 691 | |
89a91f4f | 692 | static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr) |
6f6d1e9a | 693 | { |
89a91f4f | 694 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a LB |
695 | |
696 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
89a91f4f | 697 | rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST; |
6f6d1e9a LB |
698 | } |
699 | ||
89a91f4f | 700 | static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len) |
6f6d1e9a | 701 | { |
89a91f4f | 702 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a LB |
703 | |
704 | rxd->pkt_len = cpu_to_le16(len); | |
705 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
706 | wmb(); | |
707 | rxd->rx_ctrl = 0; | |
708 | } | |
709 | ||
710 | static int | |
89a91f4f LB |
711 | mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status, |
712 | __le16 *qos) | |
6f6d1e9a | 713 | { |
89a91f4f | 714 | struct mwl8k_rxd_8366_ap *rxd = _rxd; |
6f6d1e9a | 715 | |
89a91f4f | 716 | if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST)) |
6f6d1e9a LB |
717 | return -1; |
718 | rmb(); | |
719 | ||
720 | memset(status, 0, sizeof(*status)); | |
721 | ||
722 | status->signal = -rxd->rssi; | |
723 | status->noise = -rxd->noise_floor; | |
724 | ||
89a91f4f | 725 | if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) { |
6f6d1e9a | 726 | status->flag |= RX_FLAG_HT; |
89a91f4f | 727 | if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ) |
8e9f33f0 | 728 | status->flag |= RX_FLAG_40MHZ; |
89a91f4f | 729 | status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate); |
6f6d1e9a LB |
730 | } else { |
731 | int i; | |
732 | ||
733 | for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) { | |
734 | if (mwl8k_rates[i].hw_value == rxd->rate) { | |
735 | status->rate_idx = i; | |
736 | break; | |
737 | } | |
738 | } | |
739 | } | |
740 | ||
741 | status->band = IEEE80211_BAND_2GHZ; | |
742 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
743 | ||
20f09c3d LB |
744 | *qos = rxd->qos_control; |
745 | ||
6f6d1e9a LB |
746 | return le16_to_cpu(rxd->pkt_len); |
747 | } | |
748 | ||
89a91f4f LB |
749 | static struct rxd_ops rxd_8366_ap_ops = { |
750 | .rxd_size = sizeof(struct mwl8k_rxd_8366_ap), | |
751 | .rxd_init = mwl8k_rxd_8366_ap_init, | |
752 | .rxd_refill = mwl8k_rxd_8366_ap_refill, | |
753 | .rxd_process = mwl8k_rxd_8366_ap_process, | |
6f6d1e9a LB |
754 | }; |
755 | ||
756 | /* | |
89a91f4f | 757 | * Packet reception for STA firmware. |
a66098da | 758 | */ |
89a91f4f | 759 | struct mwl8k_rxd_sta { |
a66098da LB |
760 | __le16 pkt_len; |
761 | __u8 link_quality; | |
762 | __u8 noise_level; | |
763 | __le32 pkt_phys_addr; | |
45eb400d | 764 | __le32 next_rxd_phys_addr; |
a66098da LB |
765 | __le16 qos_control; |
766 | __le16 rate_info; | |
767 | __le32 pad0[4]; | |
768 | __u8 rssi; | |
769 | __u8 channel; | |
770 | __le16 pad1; | |
771 | __u8 rx_ctrl; | |
772 | __u8 rx_status; | |
773 | __u8 pad2[2]; | |
774 | } __attribute__((packed)); | |
775 | ||
89a91f4f LB |
776 | #define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000 |
777 | #define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3) | |
778 | #define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f) | |
779 | #define MWL8K_STA_RATE_INFO_40MHZ 0x0004 | |
780 | #define MWL8K_STA_RATE_INFO_SHORTGI 0x0002 | |
781 | #define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001 | |
54bc3a0d | 782 | |
89a91f4f | 783 | #define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02 |
54bc3a0d | 784 | |
89a91f4f | 785 | static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr) |
54bc3a0d | 786 | { |
89a91f4f | 787 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
788 | |
789 | rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr); | |
89a91f4f | 790 | rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST; |
54bc3a0d LB |
791 | } |
792 | ||
89a91f4f | 793 | static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len) |
54bc3a0d | 794 | { |
89a91f4f | 795 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
796 | |
797 | rxd->pkt_len = cpu_to_le16(len); | |
798 | rxd->pkt_phys_addr = cpu_to_le32(addr); | |
799 | wmb(); | |
800 | rxd->rx_ctrl = 0; | |
801 | } | |
802 | ||
803 | static int | |
89a91f4f | 804 | mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status, |
20f09c3d | 805 | __le16 *qos) |
54bc3a0d | 806 | { |
89a91f4f | 807 | struct mwl8k_rxd_sta *rxd = _rxd; |
54bc3a0d LB |
808 | u16 rate_info; |
809 | ||
89a91f4f | 810 | if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST)) |
54bc3a0d LB |
811 | return -1; |
812 | rmb(); | |
813 | ||
814 | rate_info = le16_to_cpu(rxd->rate_info); | |
815 | ||
816 | memset(status, 0, sizeof(*status)); | |
817 | ||
818 | status->signal = -rxd->rssi; | |
819 | status->noise = -rxd->noise_level; | |
89a91f4f LB |
820 | status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info); |
821 | status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info); | |
54bc3a0d | 822 | |
89a91f4f | 823 | if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE) |
54bc3a0d | 824 | status->flag |= RX_FLAG_SHORTPRE; |
89a91f4f | 825 | if (rate_info & MWL8K_STA_RATE_INFO_40MHZ) |
54bc3a0d | 826 | status->flag |= RX_FLAG_40MHZ; |
89a91f4f | 827 | if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI) |
54bc3a0d | 828 | status->flag |= RX_FLAG_SHORT_GI; |
89a91f4f | 829 | if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT) |
54bc3a0d LB |
830 | status->flag |= RX_FLAG_HT; |
831 | ||
832 | status->band = IEEE80211_BAND_2GHZ; | |
833 | status->freq = ieee80211_channel_to_frequency(rxd->channel); | |
834 | ||
20f09c3d LB |
835 | *qos = rxd->qos_control; |
836 | ||
54bc3a0d LB |
837 | return le16_to_cpu(rxd->pkt_len); |
838 | } | |
839 | ||
89a91f4f LB |
840 | static struct rxd_ops rxd_sta_ops = { |
841 | .rxd_size = sizeof(struct mwl8k_rxd_sta), | |
842 | .rxd_init = mwl8k_rxd_sta_init, | |
843 | .rxd_refill = mwl8k_rxd_sta_refill, | |
844 | .rxd_process = mwl8k_rxd_sta_process, | |
54bc3a0d LB |
845 | }; |
846 | ||
847 | ||
a66098da LB |
848 | #define MWL8K_RX_DESCS 256 |
849 | #define MWL8K_RX_MAXSZ 3800 | |
850 | ||
851 | static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index) | |
852 | { | |
853 | struct mwl8k_priv *priv = hw->priv; | |
854 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
855 | int size; | |
856 | int i; | |
857 | ||
45eb400d LB |
858 | rxq->rxd_count = 0; |
859 | rxq->head = 0; | |
860 | rxq->tail = 0; | |
a66098da | 861 | |
54bc3a0d | 862 | size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size; |
a66098da | 863 | |
45eb400d LB |
864 | rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma); |
865 | if (rxq->rxd == NULL) { | |
a66098da | 866 | printk(KERN_ERR "%s: failed to alloc RX descriptors\n", |
c2c357ce | 867 | wiphy_name(hw->wiphy)); |
a66098da LB |
868 | return -ENOMEM; |
869 | } | |
45eb400d | 870 | memset(rxq->rxd, 0, size); |
a66098da | 871 | |
788838eb LB |
872 | rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL); |
873 | if (rxq->buf == NULL) { | |
a66098da | 874 | printk(KERN_ERR "%s: failed to alloc RX skbuff list\n", |
c2c357ce | 875 | wiphy_name(hw->wiphy)); |
45eb400d | 876 | pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma); |
a66098da LB |
877 | return -ENOMEM; |
878 | } | |
788838eb | 879 | memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf)); |
a66098da LB |
880 | |
881 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
54bc3a0d LB |
882 | int desc_size; |
883 | void *rxd; | |
a66098da | 884 | int nexti; |
54bc3a0d LB |
885 | dma_addr_t next_dma_addr; |
886 | ||
887 | desc_size = priv->rxd_ops->rxd_size; | |
888 | rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size); | |
a66098da | 889 | |
54bc3a0d LB |
890 | nexti = i + 1; |
891 | if (nexti == MWL8K_RX_DESCS) | |
892 | nexti = 0; | |
893 | next_dma_addr = rxq->rxd_dma + (nexti * desc_size); | |
a66098da | 894 | |
54bc3a0d | 895 | priv->rxd_ops->rxd_init(rxd, next_dma_addr); |
a66098da LB |
896 | } |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
901 | static int rxq_refill(struct ieee80211_hw *hw, int index, int limit) | |
902 | { | |
903 | struct mwl8k_priv *priv = hw->priv; | |
904 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
905 | int refilled; | |
906 | ||
907 | refilled = 0; | |
45eb400d | 908 | while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) { |
a66098da | 909 | struct sk_buff *skb; |
788838eb | 910 | dma_addr_t addr; |
a66098da | 911 | int rx; |
54bc3a0d | 912 | void *rxd; |
a66098da LB |
913 | |
914 | skb = dev_alloc_skb(MWL8K_RX_MAXSZ); | |
915 | if (skb == NULL) | |
916 | break; | |
917 | ||
788838eb LB |
918 | addr = pci_map_single(priv->pdev, skb->data, |
919 | MWL8K_RX_MAXSZ, DMA_FROM_DEVICE); | |
a66098da | 920 | |
54bc3a0d LB |
921 | rxq->rxd_count++; |
922 | rx = rxq->tail++; | |
923 | if (rxq->tail == MWL8K_RX_DESCS) | |
924 | rxq->tail = 0; | |
788838eb LB |
925 | rxq->buf[rx].skb = skb; |
926 | pci_unmap_addr_set(&rxq->buf[rx], dma, addr); | |
54bc3a0d LB |
927 | |
928 | rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size); | |
929 | priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ); | |
a66098da LB |
930 | |
931 | refilled++; | |
932 | } | |
933 | ||
934 | return refilled; | |
935 | } | |
936 | ||
937 | /* Must be called only when the card's reception is completely halted */ | |
938 | static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index) | |
939 | { | |
940 | struct mwl8k_priv *priv = hw->priv; | |
941 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
942 | int i; | |
943 | ||
944 | for (i = 0; i < MWL8K_RX_DESCS; i++) { | |
788838eb LB |
945 | if (rxq->buf[i].skb != NULL) { |
946 | pci_unmap_single(priv->pdev, | |
947 | pci_unmap_addr(&rxq->buf[i], dma), | |
948 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
949 | pci_unmap_addr_set(&rxq->buf[i], dma, 0); | |
950 | ||
951 | kfree_skb(rxq->buf[i].skb); | |
952 | rxq->buf[i].skb = NULL; | |
a66098da LB |
953 | } |
954 | } | |
955 | ||
788838eb LB |
956 | kfree(rxq->buf); |
957 | rxq->buf = NULL; | |
a66098da LB |
958 | |
959 | pci_free_consistent(priv->pdev, | |
54bc3a0d | 960 | MWL8K_RX_DESCS * priv->rxd_ops->rxd_size, |
45eb400d LB |
961 | rxq->rxd, rxq->rxd_dma); |
962 | rxq->rxd = NULL; | |
a66098da LB |
963 | } |
964 | ||
965 | ||
966 | /* | |
967 | * Scan a list of BSSIDs to process for finalize join. | |
968 | * Allows for extension to process multiple BSSIDs. | |
969 | */ | |
970 | static inline int | |
971 | mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh) | |
972 | { | |
973 | return priv->capture_beacon && | |
974 | ieee80211_is_beacon(wh->frame_control) && | |
975 | !compare_ether_addr(wh->addr3, priv->capture_bssid); | |
976 | } | |
977 | ||
3779752d LB |
978 | static inline void mwl8k_save_beacon(struct ieee80211_hw *hw, |
979 | struct sk_buff *skb) | |
a66098da | 980 | { |
3779752d LB |
981 | struct mwl8k_priv *priv = hw->priv; |
982 | ||
a66098da | 983 | priv->capture_beacon = false; |
d89173f2 | 984 | memset(priv->capture_bssid, 0, ETH_ALEN); |
a66098da LB |
985 | |
986 | /* | |
987 | * Use GFP_ATOMIC as rxq_process is called from | |
988 | * the primary interrupt handler, memory allocation call | |
989 | * must not sleep. | |
990 | */ | |
991 | priv->beacon_skb = skb_copy(skb, GFP_ATOMIC); | |
992 | if (priv->beacon_skb != NULL) | |
3779752d | 993 | ieee80211_queue_work(hw, &priv->finalize_join_worker); |
a66098da LB |
994 | } |
995 | ||
996 | static int rxq_process(struct ieee80211_hw *hw, int index, int limit) | |
997 | { | |
998 | struct mwl8k_priv *priv = hw->priv; | |
999 | struct mwl8k_rx_queue *rxq = priv->rxq + index; | |
1000 | int processed; | |
1001 | ||
1002 | processed = 0; | |
45eb400d | 1003 | while (rxq->rxd_count && limit--) { |
a66098da | 1004 | struct sk_buff *skb; |
54bc3a0d LB |
1005 | void *rxd; |
1006 | int pkt_len; | |
a66098da | 1007 | struct ieee80211_rx_status status; |
20f09c3d | 1008 | __le16 qos; |
a66098da | 1009 | |
788838eb | 1010 | skb = rxq->buf[rxq->head].skb; |
d25f9f13 LB |
1011 | if (skb == NULL) |
1012 | break; | |
54bc3a0d LB |
1013 | |
1014 | rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size); | |
1015 | ||
20f09c3d | 1016 | pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos); |
54bc3a0d LB |
1017 | if (pkt_len < 0) |
1018 | break; | |
1019 | ||
788838eb LB |
1020 | rxq->buf[rxq->head].skb = NULL; |
1021 | ||
1022 | pci_unmap_single(priv->pdev, | |
1023 | pci_unmap_addr(&rxq->buf[rxq->head], dma), | |
1024 | MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE); | |
1025 | pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0); | |
a66098da | 1026 | |
54bc3a0d LB |
1027 | rxq->head++; |
1028 | if (rxq->head == MWL8K_RX_DESCS) | |
1029 | rxq->head = 0; | |
1030 | ||
45eb400d | 1031 | rxq->rxd_count--; |
a66098da | 1032 | |
54bc3a0d | 1033 | skb_put(skb, pkt_len); |
20f09c3d | 1034 | mwl8k_remove_dma_header(skb, qos); |
a66098da | 1035 | |
a66098da | 1036 | /* |
c2c357ce LB |
1037 | * Check for a pending join operation. Save a |
1038 | * copy of the beacon and schedule a tasklet to | |
1039 | * send a FINALIZE_JOIN command to the firmware. | |
a66098da | 1040 | */ |
54bc3a0d | 1041 | if (mwl8k_capture_bssid(priv, (void *)skb->data)) |
3779752d | 1042 | mwl8k_save_beacon(hw, skb); |
a66098da | 1043 | |
f1d58c25 JB |
1044 | memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status)); |
1045 | ieee80211_rx_irqsafe(hw, skb); | |
a66098da LB |
1046 | |
1047 | processed++; | |
1048 | } | |
1049 | ||
1050 | return processed; | |
1051 | } | |
1052 | ||
1053 | ||
1054 | /* | |
1055 | * Packet transmission. | |
1056 | */ | |
1057 | ||
a66098da LB |
1058 | #define MWL8K_TXD_STATUS_OK 0x00000001 |
1059 | #define MWL8K_TXD_STATUS_OK_RETRY 0x00000002 | |
1060 | #define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004 | |
1061 | #define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008 | |
a66098da | 1062 | #define MWL8K_TXD_STATUS_FW_OWNED 0x80000000 |
a66098da | 1063 | |
e0493a8d LB |
1064 | #define MWL8K_QOS_QLEN_UNSPEC 0xff00 |
1065 | #define MWL8K_QOS_ACK_POLICY_MASK 0x0060 | |
1066 | #define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000 | |
1067 | #define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060 | |
1068 | #define MWL8K_QOS_EOSP 0x0010 | |
1069 | ||
a66098da LB |
1070 | struct mwl8k_tx_desc { |
1071 | __le32 status; | |
1072 | __u8 data_rate; | |
1073 | __u8 tx_priority; | |
1074 | __le16 qos_control; | |
1075 | __le32 pkt_phys_addr; | |
1076 | __le16 pkt_len; | |
d89173f2 | 1077 | __u8 dest_MAC_addr[ETH_ALEN]; |
45eb400d | 1078 | __le32 next_txd_phys_addr; |
a66098da LB |
1079 | __le32 reserved; |
1080 | __le16 rate_info; | |
1081 | __u8 peer_id; | |
1082 | __u8 tx_frag_cnt; | |
1083 | } __attribute__((packed)); | |
1084 | ||
1085 | #define MWL8K_TX_DESCS 128 | |
1086 | ||
1087 | static int mwl8k_txq_init(struct ieee80211_hw *hw, int index) | |
1088 | { | |
1089 | struct mwl8k_priv *priv = hw->priv; | |
1090 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1091 | int size; | |
1092 | int i; | |
1093 | ||
45eb400d LB |
1094 | memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats)); |
1095 | txq->stats.limit = MWL8K_TX_DESCS; | |
1096 | txq->head = 0; | |
1097 | txq->tail = 0; | |
a66098da LB |
1098 | |
1099 | size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc); | |
1100 | ||
45eb400d LB |
1101 | txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma); |
1102 | if (txq->txd == NULL) { | |
a66098da | 1103 | printk(KERN_ERR "%s: failed to alloc TX descriptors\n", |
c2c357ce | 1104 | wiphy_name(hw->wiphy)); |
a66098da LB |
1105 | return -ENOMEM; |
1106 | } | |
45eb400d | 1107 | memset(txq->txd, 0, size); |
a66098da | 1108 | |
45eb400d LB |
1109 | txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL); |
1110 | if (txq->skb == NULL) { | |
a66098da | 1111 | printk(KERN_ERR "%s: failed to alloc TX skbuff list\n", |
c2c357ce | 1112 | wiphy_name(hw->wiphy)); |
45eb400d | 1113 | pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma); |
a66098da LB |
1114 | return -ENOMEM; |
1115 | } | |
45eb400d | 1116 | memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb)); |
a66098da LB |
1117 | |
1118 | for (i = 0; i < MWL8K_TX_DESCS; i++) { | |
1119 | struct mwl8k_tx_desc *tx_desc; | |
1120 | int nexti; | |
1121 | ||
45eb400d | 1122 | tx_desc = txq->txd + i; |
a66098da LB |
1123 | nexti = (i + 1) % MWL8K_TX_DESCS; |
1124 | ||
1125 | tx_desc->status = 0; | |
45eb400d LB |
1126 | tx_desc->next_txd_phys_addr = |
1127 | cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc)); | |
a66098da LB |
1128 | } |
1129 | ||
1130 | return 0; | |
1131 | } | |
1132 | ||
1133 | static inline void mwl8k_tx_start(struct mwl8k_priv *priv) | |
1134 | { | |
1135 | iowrite32(MWL8K_H2A_INT_PPA_READY, | |
1136 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1137 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1138 | priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1139 | ioread32(priv->regs + MWL8K_HIU_INT_CODE); | |
1140 | } | |
1141 | ||
7e1112d3 | 1142 | static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw) |
a66098da | 1143 | { |
7e1112d3 LB |
1144 | struct mwl8k_priv *priv = hw->priv; |
1145 | int i; | |
1146 | ||
1147 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { | |
1148 | struct mwl8k_tx_queue *txq = priv->txq + i; | |
1149 | int fw_owned = 0; | |
1150 | int drv_owned = 0; | |
1151 | int unused = 0; | |
1152 | int desc; | |
1153 | ||
a66098da | 1154 | for (desc = 0; desc < MWL8K_TX_DESCS; desc++) { |
7e1112d3 LB |
1155 | struct mwl8k_tx_desc *tx_desc = txq->txd + desc; |
1156 | u32 status; | |
a66098da | 1157 | |
7e1112d3 | 1158 | status = le32_to_cpu(tx_desc->status); |
a66098da | 1159 | if (status & MWL8K_TXD_STATUS_FW_OWNED) |
7e1112d3 | 1160 | fw_owned++; |
a66098da | 1161 | else |
7e1112d3 | 1162 | drv_owned++; |
a66098da LB |
1163 | |
1164 | if (tx_desc->pkt_len == 0) | |
7e1112d3 | 1165 | unused++; |
a66098da | 1166 | } |
a66098da | 1167 | |
7e1112d3 LB |
1168 | printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d " |
1169 | "fw_owned=%d drv_owned=%d unused=%d\n", | |
1170 | wiphy_name(hw->wiphy), i, | |
1171 | txq->stats.len, txq->head, txq->tail, | |
1172 | fw_owned, drv_owned, unused); | |
1173 | } | |
a66098da LB |
1174 | } |
1175 | ||
618952a7 | 1176 | /* |
88de754a | 1177 | * Must be called with priv->fw_mutex held and tx queues stopped. |
618952a7 | 1178 | */ |
7e1112d3 LB |
1179 | #define MWL8K_TX_WAIT_TIMEOUT_MS 1000 |
1180 | ||
950d5b01 | 1181 | static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw) |
a66098da | 1182 | { |
a66098da | 1183 | struct mwl8k_priv *priv = hw->priv; |
88de754a | 1184 | DECLARE_COMPLETION_ONSTACK(tx_wait); |
7e1112d3 LB |
1185 | int retry; |
1186 | int rc; | |
a66098da LB |
1187 | |
1188 | might_sleep(); | |
1189 | ||
7e1112d3 LB |
1190 | /* |
1191 | * The TX queues are stopped at this point, so this test | |
1192 | * doesn't need to take ->tx_lock. | |
1193 | */ | |
1194 | if (!priv->pending_tx_pkts) | |
1195 | return 0; | |
1196 | ||
1197 | retry = 0; | |
1198 | rc = 0; | |
1199 | ||
a66098da | 1200 | spin_lock_bh(&priv->tx_lock); |
7e1112d3 LB |
1201 | priv->tx_wait = &tx_wait; |
1202 | while (!rc) { | |
1203 | int oldcount; | |
1204 | unsigned long timeout; | |
a66098da | 1205 | |
7e1112d3 | 1206 | oldcount = priv->pending_tx_pkts; |
a66098da | 1207 | |
7e1112d3 | 1208 | spin_unlock_bh(&priv->tx_lock); |
88de754a | 1209 | timeout = wait_for_completion_timeout(&tx_wait, |
7e1112d3 | 1210 | msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS)); |
a66098da | 1211 | spin_lock_bh(&priv->tx_lock); |
7e1112d3 LB |
1212 | |
1213 | if (timeout) { | |
1214 | WARN_ON(priv->pending_tx_pkts); | |
1215 | if (retry) { | |
1216 | printk(KERN_NOTICE "%s: tx rings drained\n", | |
1217 | wiphy_name(hw->wiphy)); | |
1218 | } | |
1219 | break; | |
1220 | } | |
1221 | ||
1222 | if (priv->pending_tx_pkts < oldcount) { | |
9a2303b9 LB |
1223 | printk(KERN_NOTICE "%s: waiting for tx rings " |
1224 | "to drain (%d -> %d pkts)\n", | |
7e1112d3 LB |
1225 | wiphy_name(hw->wiphy), oldcount, |
1226 | priv->pending_tx_pkts); | |
1227 | retry = 1; | |
1228 | continue; | |
1229 | } | |
1230 | ||
a66098da | 1231 | priv->tx_wait = NULL; |
a66098da | 1232 | |
7e1112d3 LB |
1233 | printk(KERN_ERR "%s: tx rings stuck for %d ms\n", |
1234 | wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS); | |
1235 | mwl8k_dump_tx_rings(hw); | |
1236 | ||
1237 | rc = -ETIMEDOUT; | |
a66098da | 1238 | } |
7e1112d3 | 1239 | spin_unlock_bh(&priv->tx_lock); |
a66098da | 1240 | |
7e1112d3 | 1241 | return rc; |
a66098da LB |
1242 | } |
1243 | ||
c23b5a69 LB |
1244 | #define MWL8K_TXD_SUCCESS(status) \ |
1245 | ((status) & (MWL8K_TXD_STATUS_OK | \ | |
1246 | MWL8K_TXD_STATUS_OK_RETRY | \ | |
1247 | MWL8K_TXD_STATUS_OK_MORE_RETRY)) | |
a66098da LB |
1248 | |
1249 | static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force) | |
1250 | { | |
1251 | struct mwl8k_priv *priv = hw->priv; | |
1252 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1253 | int wake = 0; | |
1254 | ||
45eb400d | 1255 | while (txq->stats.len > 0) { |
a66098da | 1256 | int tx; |
a66098da LB |
1257 | struct mwl8k_tx_desc *tx_desc; |
1258 | unsigned long addr; | |
ce9e2e1b | 1259 | int size; |
a66098da LB |
1260 | struct sk_buff *skb; |
1261 | struct ieee80211_tx_info *info; | |
1262 | u32 status; | |
1263 | ||
45eb400d LB |
1264 | tx = txq->head; |
1265 | tx_desc = txq->txd + tx; | |
a66098da LB |
1266 | |
1267 | status = le32_to_cpu(tx_desc->status); | |
1268 | ||
1269 | if (status & MWL8K_TXD_STATUS_FW_OWNED) { | |
1270 | if (!force) | |
1271 | break; | |
1272 | tx_desc->status &= | |
1273 | ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED); | |
1274 | } | |
1275 | ||
45eb400d LB |
1276 | txq->head = (tx + 1) % MWL8K_TX_DESCS; |
1277 | BUG_ON(txq->stats.len == 0); | |
1278 | txq->stats.len--; | |
a66098da LB |
1279 | priv->pending_tx_pkts--; |
1280 | ||
1281 | addr = le32_to_cpu(tx_desc->pkt_phys_addr); | |
ce9e2e1b | 1282 | size = le16_to_cpu(tx_desc->pkt_len); |
45eb400d LB |
1283 | skb = txq->skb[tx]; |
1284 | txq->skb[tx] = NULL; | |
a66098da LB |
1285 | |
1286 | BUG_ON(skb == NULL); | |
1287 | pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE); | |
1288 | ||
20f09c3d | 1289 | mwl8k_remove_dma_header(skb, tx_desc->qos_control); |
a66098da LB |
1290 | |
1291 | /* Mark descriptor as unused */ | |
1292 | tx_desc->pkt_phys_addr = 0; | |
1293 | tx_desc->pkt_len = 0; | |
1294 | ||
a66098da LB |
1295 | info = IEEE80211_SKB_CB(skb); |
1296 | ieee80211_tx_info_clear_status(info); | |
ce9e2e1b | 1297 | if (MWL8K_TXD_SUCCESS(status)) |
a66098da | 1298 | info->flags |= IEEE80211_TX_STAT_ACK; |
a66098da LB |
1299 | |
1300 | ieee80211_tx_status_irqsafe(hw, skb); | |
1301 | ||
618952a7 | 1302 | wake = 1; |
a66098da LB |
1303 | } |
1304 | ||
618952a7 | 1305 | if (wake && priv->radio_on && !mutex_is_locked(&priv->fw_mutex)) |
a66098da LB |
1306 | ieee80211_wake_queue(hw, index); |
1307 | } | |
1308 | ||
1309 | /* must be called only when the card's transmit is completely halted */ | |
1310 | static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index) | |
1311 | { | |
1312 | struct mwl8k_priv *priv = hw->priv; | |
1313 | struct mwl8k_tx_queue *txq = priv->txq + index; | |
1314 | ||
1315 | mwl8k_txq_reclaim(hw, index, 1); | |
1316 | ||
45eb400d LB |
1317 | kfree(txq->skb); |
1318 | txq->skb = NULL; | |
a66098da LB |
1319 | |
1320 | pci_free_consistent(priv->pdev, | |
1321 | MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc), | |
45eb400d LB |
1322 | txq->txd, txq->txd_dma); |
1323 | txq->txd = NULL; | |
a66098da LB |
1324 | } |
1325 | ||
1326 | static int | |
1327 | mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb) | |
1328 | { | |
1329 | struct mwl8k_priv *priv = hw->priv; | |
1330 | struct ieee80211_tx_info *tx_info; | |
23b33906 | 1331 | struct mwl8k_vif *mwl8k_vif; |
a66098da LB |
1332 | struct ieee80211_hdr *wh; |
1333 | struct mwl8k_tx_queue *txq; | |
1334 | struct mwl8k_tx_desc *tx; | |
a66098da | 1335 | dma_addr_t dma; |
23b33906 LB |
1336 | u32 txstatus; |
1337 | u8 txdatarate; | |
1338 | u16 qos; | |
a66098da | 1339 | |
23b33906 LB |
1340 | wh = (struct ieee80211_hdr *)skb->data; |
1341 | if (ieee80211_is_data_qos(wh->frame_control)) | |
1342 | qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh))); | |
1343 | else | |
1344 | qos = 0; | |
a66098da | 1345 | |
76266b2a | 1346 | mwl8k_add_dma_header(skb); |
23b33906 | 1347 | wh = &((struct mwl8k_dma_data *)skb->data)->wh; |
a66098da LB |
1348 | |
1349 | tx_info = IEEE80211_SKB_CB(skb); | |
1350 | mwl8k_vif = MWL8K_VIF(tx_info->control.vif); | |
a66098da LB |
1351 | |
1352 | if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
1353 | u16 seqno = mwl8k_vif->seqno; | |
23b33906 | 1354 | |
a66098da LB |
1355 | wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
1356 | wh->seq_ctrl |= cpu_to_le16(seqno << 4); | |
1357 | mwl8k_vif->seqno = seqno++ % 4096; | |
1358 | } | |
1359 | ||
23b33906 LB |
1360 | /* Setup firmware control bit fields for each frame type. */ |
1361 | txstatus = 0; | |
1362 | txdatarate = 0; | |
1363 | if (ieee80211_is_mgmt(wh->frame_control) || | |
1364 | ieee80211_is_ctl(wh->frame_control)) { | |
1365 | txdatarate = 0; | |
e0493a8d | 1366 | qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP; |
23b33906 LB |
1367 | } else if (ieee80211_is_data(wh->frame_control)) { |
1368 | txdatarate = 1; | |
1369 | if (is_multicast_ether_addr(wh->addr1)) | |
1370 | txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX; | |
1371 | ||
e0493a8d | 1372 | qos &= ~MWL8K_QOS_ACK_POLICY_MASK; |
23b33906 | 1373 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) |
e0493a8d | 1374 | qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK; |
23b33906 | 1375 | else |
e0493a8d | 1376 | qos |= MWL8K_QOS_ACK_POLICY_NORMAL; |
23b33906 | 1377 | } |
a66098da LB |
1378 | |
1379 | dma = pci_map_single(priv->pdev, skb->data, | |
1380 | skb->len, PCI_DMA_TODEVICE); | |
1381 | ||
1382 | if (pci_dma_mapping_error(priv->pdev, dma)) { | |
1383 | printk(KERN_DEBUG "%s: failed to dma map skb, " | |
c2c357ce | 1384 | "dropping TX frame.\n", wiphy_name(hw->wiphy)); |
23b33906 | 1385 | dev_kfree_skb(skb); |
a66098da LB |
1386 | return NETDEV_TX_OK; |
1387 | } | |
1388 | ||
23b33906 | 1389 | spin_lock_bh(&priv->tx_lock); |
a66098da | 1390 | |
23b33906 | 1391 | txq = priv->txq + index; |
a66098da | 1392 | |
45eb400d LB |
1393 | BUG_ON(txq->skb[txq->tail] != NULL); |
1394 | txq->skb[txq->tail] = skb; | |
a66098da | 1395 | |
45eb400d | 1396 | tx = txq->txd + txq->tail; |
23b33906 LB |
1397 | tx->data_rate = txdatarate; |
1398 | tx->tx_priority = index; | |
a66098da | 1399 | tx->qos_control = cpu_to_le16(qos); |
a66098da LB |
1400 | tx->pkt_phys_addr = cpu_to_le32(dma); |
1401 | tx->pkt_len = cpu_to_le16(skb->len); | |
23b33906 | 1402 | tx->rate_info = 0; |
a680400e LB |
1403 | if (!priv->ap_fw && tx_info->control.sta != NULL) |
1404 | tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id; | |
1405 | else | |
1406 | tx->peer_id = 0; | |
a66098da | 1407 | wmb(); |
23b33906 LB |
1408 | tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus); |
1409 | ||
45eb400d LB |
1410 | txq->stats.count++; |
1411 | txq->stats.len++; | |
a66098da | 1412 | priv->pending_tx_pkts++; |
a66098da | 1413 | |
45eb400d LB |
1414 | txq->tail++; |
1415 | if (txq->tail == MWL8K_TX_DESCS) | |
1416 | txq->tail = 0; | |
23b33906 | 1417 | |
45eb400d | 1418 | if (txq->head == txq->tail) |
a66098da LB |
1419 | ieee80211_stop_queue(hw, index); |
1420 | ||
23b33906 | 1421 | mwl8k_tx_start(priv); |
a66098da LB |
1422 | |
1423 | spin_unlock_bh(&priv->tx_lock); | |
1424 | ||
1425 | return NETDEV_TX_OK; | |
1426 | } | |
1427 | ||
1428 | ||
618952a7 LB |
1429 | /* |
1430 | * Firmware access. | |
1431 | * | |
1432 | * We have the following requirements for issuing firmware commands: | |
1433 | * - Some commands require that the packet transmit path is idle when | |
1434 | * the command is issued. (For simplicity, we'll just quiesce the | |
1435 | * transmit path for every command.) | |
1436 | * - There are certain sequences of commands that need to be issued to | |
1437 | * the hardware sequentially, with no other intervening commands. | |
1438 | * | |
1439 | * This leads to an implementation of a "firmware lock" as a mutex that | |
1440 | * can be taken recursively, and which is taken by both the low-level | |
1441 | * command submission function (mwl8k_post_cmd) as well as any users of | |
1442 | * that function that require issuing of an atomic sequence of commands, | |
1443 | * and quiesces the transmit path whenever it's taken. | |
1444 | */ | |
1445 | static int mwl8k_fw_lock(struct ieee80211_hw *hw) | |
1446 | { | |
1447 | struct mwl8k_priv *priv = hw->priv; | |
1448 | ||
1449 | if (priv->fw_mutex_owner != current) { | |
1450 | int rc; | |
1451 | ||
1452 | mutex_lock(&priv->fw_mutex); | |
1453 | ieee80211_stop_queues(hw); | |
1454 | ||
1455 | rc = mwl8k_tx_wait_empty(hw); | |
1456 | if (rc) { | |
1457 | ieee80211_wake_queues(hw); | |
1458 | mutex_unlock(&priv->fw_mutex); | |
1459 | ||
1460 | return rc; | |
1461 | } | |
1462 | ||
1463 | priv->fw_mutex_owner = current; | |
1464 | } | |
1465 | ||
1466 | priv->fw_mutex_depth++; | |
1467 | ||
1468 | return 0; | |
1469 | } | |
1470 | ||
1471 | static void mwl8k_fw_unlock(struct ieee80211_hw *hw) | |
1472 | { | |
1473 | struct mwl8k_priv *priv = hw->priv; | |
1474 | ||
1475 | if (!--priv->fw_mutex_depth) { | |
1476 | ieee80211_wake_queues(hw); | |
1477 | priv->fw_mutex_owner = NULL; | |
1478 | mutex_unlock(&priv->fw_mutex); | |
1479 | } | |
1480 | } | |
1481 | ||
1482 | ||
a66098da LB |
1483 | /* |
1484 | * Command processing. | |
1485 | */ | |
1486 | ||
0c9cc640 LB |
1487 | /* Timeout firmware commands after 10s */ |
1488 | #define MWL8K_CMD_TIMEOUT_MS 10000 | |
a66098da LB |
1489 | |
1490 | static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd) | |
1491 | { | |
1492 | DECLARE_COMPLETION_ONSTACK(cmd_wait); | |
1493 | struct mwl8k_priv *priv = hw->priv; | |
1494 | void __iomem *regs = priv->regs; | |
1495 | dma_addr_t dma_addr; | |
1496 | unsigned int dma_size; | |
1497 | int rc; | |
a66098da LB |
1498 | unsigned long timeout = 0; |
1499 | u8 buf[32]; | |
1500 | ||
c2c357ce | 1501 | cmd->result = 0xffff; |
a66098da LB |
1502 | dma_size = le16_to_cpu(cmd->length); |
1503 | dma_addr = pci_map_single(priv->pdev, cmd, dma_size, | |
1504 | PCI_DMA_BIDIRECTIONAL); | |
1505 | if (pci_dma_mapping_error(priv->pdev, dma_addr)) | |
1506 | return -ENOMEM; | |
1507 | ||
618952a7 | 1508 | rc = mwl8k_fw_lock(hw); |
39a1e42e LB |
1509 | if (rc) { |
1510 | pci_unmap_single(priv->pdev, dma_addr, dma_size, | |
1511 | PCI_DMA_BIDIRECTIONAL); | |
618952a7 | 1512 | return rc; |
39a1e42e | 1513 | } |
a66098da | 1514 | |
a66098da LB |
1515 | priv->hostcmd_wait = &cmd_wait; |
1516 | iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR); | |
1517 | iowrite32(MWL8K_H2A_INT_DOORBELL, | |
1518 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
1519 | iowrite32(MWL8K_H2A_INT_DUMMY, | |
1520 | regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS); | |
a66098da LB |
1521 | |
1522 | timeout = wait_for_completion_timeout(&cmd_wait, | |
1523 | msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS)); | |
1524 | ||
618952a7 LB |
1525 | priv->hostcmd_wait = NULL; |
1526 | ||
1527 | mwl8k_fw_unlock(hw); | |
1528 | ||
37055bd4 LB |
1529 | pci_unmap_single(priv->pdev, dma_addr, dma_size, |
1530 | PCI_DMA_BIDIRECTIONAL); | |
1531 | ||
a66098da | 1532 | if (!timeout) { |
a66098da | 1533 | printk(KERN_ERR "%s: Command %s timeout after %u ms\n", |
c2c357ce | 1534 | wiphy_name(hw->wiphy), |
a66098da LB |
1535 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
1536 | MWL8K_CMD_TIMEOUT_MS); | |
1537 | rc = -ETIMEDOUT; | |
1538 | } else { | |
0c9cc640 LB |
1539 | int ms; |
1540 | ||
1541 | ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout); | |
1542 | ||
ce9e2e1b | 1543 | rc = cmd->result ? -EINVAL : 0; |
a66098da LB |
1544 | if (rc) |
1545 | printk(KERN_ERR "%s: Command %s error 0x%x\n", | |
c2c357ce | 1546 | wiphy_name(hw->wiphy), |
a66098da | 1547 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), |
76c962a2 | 1548 | le16_to_cpu(cmd->result)); |
0c9cc640 LB |
1549 | else if (ms > 2000) |
1550 | printk(KERN_NOTICE "%s: Command %s took %d ms\n", | |
1551 | wiphy_name(hw->wiphy), | |
1552 | mwl8k_cmd_name(cmd->code, buf, sizeof(buf)), | |
1553 | ms); | |
a66098da LB |
1554 | } |
1555 | ||
a66098da LB |
1556 | return rc; |
1557 | } | |
1558 | ||
1559 | /* | |
04b147b1 | 1560 | * CMD_GET_HW_SPEC (STA version). |
a66098da | 1561 | */ |
04b147b1 | 1562 | struct mwl8k_cmd_get_hw_spec_sta { |
a66098da LB |
1563 | struct mwl8k_cmd_pkt header; |
1564 | __u8 hw_rev; | |
1565 | __u8 host_interface; | |
1566 | __le16 num_mcaddrs; | |
d89173f2 | 1567 | __u8 perm_addr[ETH_ALEN]; |
a66098da LB |
1568 | __le16 region_code; |
1569 | __le32 fw_rev; | |
1570 | __le32 ps_cookie; | |
1571 | __le32 caps; | |
1572 | __u8 mcs_bitmap[16]; | |
1573 | __le32 rx_queue_ptr; | |
1574 | __le32 num_tx_queues; | |
1575 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1576 | __le32 caps2; | |
1577 | __le32 num_tx_desc_per_queue; | |
45eb400d | 1578 | __le32 total_rxd; |
a66098da LB |
1579 | } __attribute__((packed)); |
1580 | ||
04b147b1 | 1581 | static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw) |
a66098da LB |
1582 | { |
1583 | struct mwl8k_priv *priv = hw->priv; | |
04b147b1 | 1584 | struct mwl8k_cmd_get_hw_spec_sta *cmd; |
a66098da LB |
1585 | int rc; |
1586 | int i; | |
1587 | ||
1588 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1589 | if (cmd == NULL) | |
1590 | return -ENOMEM; | |
1591 | ||
1592 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1593 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1594 | ||
1595 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1596 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
45eb400d | 1597 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); |
4ff6432e | 1598 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); |
a66098da | 1599 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
45eb400d | 1600 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); |
4ff6432e | 1601 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); |
45eb400d | 1602 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); |
a66098da LB |
1603 | |
1604 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1605 | ||
1606 | if (!rc) { | |
1607 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1608 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
4ff6432e | 1609 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); |
a66098da | 1610 | priv->hw_rev = cmd->hw_rev; |
a66098da LB |
1611 | } |
1612 | ||
1613 | kfree(cmd); | |
1614 | return rc; | |
1615 | } | |
1616 | ||
42fba21d LB |
1617 | /* |
1618 | * CMD_GET_HW_SPEC (AP version). | |
1619 | */ | |
1620 | struct mwl8k_cmd_get_hw_spec_ap { | |
1621 | struct mwl8k_cmd_pkt header; | |
1622 | __u8 hw_rev; | |
1623 | __u8 host_interface; | |
1624 | __le16 num_wcb; | |
1625 | __le16 num_mcaddrs; | |
1626 | __u8 perm_addr[ETH_ALEN]; | |
1627 | __le16 region_code; | |
1628 | __le16 num_antenna; | |
1629 | __le32 fw_rev; | |
1630 | __le32 wcbbase0; | |
1631 | __le32 rxwrptr; | |
1632 | __le32 rxrdptr; | |
1633 | __le32 ps_cookie; | |
1634 | __le32 wcbbase1; | |
1635 | __le32 wcbbase2; | |
1636 | __le32 wcbbase3; | |
1637 | } __attribute__((packed)); | |
1638 | ||
1639 | static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw) | |
1640 | { | |
1641 | struct mwl8k_priv *priv = hw->priv; | |
1642 | struct mwl8k_cmd_get_hw_spec_ap *cmd; | |
1643 | int rc; | |
1644 | ||
1645 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1646 | if (cmd == NULL) | |
1647 | return -ENOMEM; | |
1648 | ||
1649 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC); | |
1650 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1651 | ||
1652 | memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr)); | |
1653 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1654 | ||
1655 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1656 | ||
1657 | if (!rc) { | |
1658 | int off; | |
1659 | ||
1660 | SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr); | |
1661 | priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs); | |
1662 | priv->fw_rev = le32_to_cpu(cmd->fw_rev); | |
1663 | priv->hw_rev = cmd->hw_rev; | |
1664 | ||
1665 | off = le32_to_cpu(cmd->wcbbase0) & 0xffff; | |
1666 | iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off); | |
1667 | ||
1668 | off = le32_to_cpu(cmd->rxwrptr) & 0xffff; | |
1669 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1670 | ||
1671 | off = le32_to_cpu(cmd->rxrdptr) & 0xffff; | |
1672 | iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off); | |
1673 | ||
1674 | off = le32_to_cpu(cmd->wcbbase1) & 0xffff; | |
1675 | iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off); | |
1676 | ||
1677 | off = le32_to_cpu(cmd->wcbbase2) & 0xffff; | |
1678 | iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off); | |
1679 | ||
1680 | off = le32_to_cpu(cmd->wcbbase3) & 0xffff; | |
1681 | iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off); | |
1682 | } | |
1683 | ||
1684 | kfree(cmd); | |
1685 | return rc; | |
1686 | } | |
1687 | ||
1688 | /* | |
1689 | * CMD_SET_HW_SPEC. | |
1690 | */ | |
1691 | struct mwl8k_cmd_set_hw_spec { | |
1692 | struct mwl8k_cmd_pkt header; | |
1693 | __u8 hw_rev; | |
1694 | __u8 host_interface; | |
1695 | __le16 num_mcaddrs; | |
1696 | __u8 perm_addr[ETH_ALEN]; | |
1697 | __le16 region_code; | |
1698 | __le32 fw_rev; | |
1699 | __le32 ps_cookie; | |
1700 | __le32 caps; | |
1701 | __le32 rx_queue_ptr; | |
1702 | __le32 num_tx_queues; | |
1703 | __le32 tx_queue_ptrs[MWL8K_TX_QUEUES]; | |
1704 | __le32 flags; | |
1705 | __le32 num_tx_desc_per_queue; | |
1706 | __le32 total_rxd; | |
1707 | } __attribute__((packed)); | |
1708 | ||
1709 | #define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080 | |
1710 | ||
1711 | static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw) | |
1712 | { | |
1713 | struct mwl8k_priv *priv = hw->priv; | |
1714 | struct mwl8k_cmd_set_hw_spec *cmd; | |
1715 | int rc; | |
1716 | int i; | |
1717 | ||
1718 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1719 | if (cmd == NULL) | |
1720 | return -ENOMEM; | |
1721 | ||
1722 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC); | |
1723 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1724 | ||
1725 | cmd->ps_cookie = cpu_to_le32(priv->cookie_dma); | |
1726 | cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma); | |
1727 | cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES); | |
1728 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
1729 | cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma); | |
1730 | cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT); | |
1731 | cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS); | |
1732 | cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS); | |
1733 | ||
1734 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1735 | kfree(cmd); | |
1736 | ||
1737 | return rc; | |
1738 | } | |
1739 | ||
a66098da LB |
1740 | /* |
1741 | * CMD_MAC_MULTICAST_ADR. | |
1742 | */ | |
1743 | struct mwl8k_cmd_mac_multicast_adr { | |
1744 | struct mwl8k_cmd_pkt header; | |
1745 | __le16 action; | |
1746 | __le16 numaddr; | |
ce9e2e1b | 1747 | __u8 addr[0][ETH_ALEN]; |
a66098da LB |
1748 | }; |
1749 | ||
d5e30845 LB |
1750 | #define MWL8K_ENABLE_RX_DIRECTED 0x0001 |
1751 | #define MWL8K_ENABLE_RX_MULTICAST 0x0002 | |
1752 | #define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004 | |
1753 | #define MWL8K_ENABLE_RX_BROADCAST 0x0008 | |
ce9e2e1b | 1754 | |
e81cd2d6 | 1755 | static struct mwl8k_cmd_pkt * |
447ced07 | 1756 | __mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti, |
e81cd2d6 | 1757 | int mc_count, struct dev_addr_list *mclist) |
a66098da | 1758 | { |
e81cd2d6 | 1759 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1760 | struct mwl8k_cmd_mac_multicast_adr *cmd; |
e81cd2d6 | 1761 | int size; |
e81cd2d6 | 1762 | |
447ced07 | 1763 | if (allmulti || mc_count > priv->num_mcaddrs) { |
d5e30845 LB |
1764 | allmulti = 1; |
1765 | mc_count = 0; | |
1766 | } | |
e81cd2d6 LB |
1767 | |
1768 | size = sizeof(*cmd) + mc_count * ETH_ALEN; | |
ce9e2e1b | 1769 | |
e81cd2d6 | 1770 | cmd = kzalloc(size, GFP_ATOMIC); |
a66098da | 1771 | if (cmd == NULL) |
e81cd2d6 | 1772 | return NULL; |
a66098da LB |
1773 | |
1774 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR); | |
1775 | cmd->header.length = cpu_to_le16(size); | |
d5e30845 LB |
1776 | cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED | |
1777 | MWL8K_ENABLE_RX_BROADCAST); | |
1778 | ||
1779 | if (allmulti) { | |
1780 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST); | |
1781 | } else if (mc_count) { | |
1782 | int i; | |
1783 | ||
1784 | cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST); | |
1785 | cmd->numaddr = cpu_to_le16(mc_count); | |
1786 | for (i = 0; i < mc_count && mclist; i++) { | |
1787 | if (mclist->da_addrlen != ETH_ALEN) { | |
1788 | kfree(cmd); | |
1789 | return NULL; | |
1790 | } | |
1791 | memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN); | |
1792 | mclist = mclist->next; | |
a66098da | 1793 | } |
a66098da LB |
1794 | } |
1795 | ||
e81cd2d6 | 1796 | return &cmd->header; |
a66098da LB |
1797 | } |
1798 | ||
1799 | /* | |
55489b6e | 1800 | * CMD_GET_STAT. |
a66098da | 1801 | */ |
55489b6e | 1802 | struct mwl8k_cmd_get_stat { |
a66098da | 1803 | struct mwl8k_cmd_pkt header; |
a66098da LB |
1804 | __le32 stats[64]; |
1805 | } __attribute__((packed)); | |
1806 | ||
1807 | #define MWL8K_STAT_ACK_FAILURE 9 | |
1808 | #define MWL8K_STAT_RTS_FAILURE 12 | |
1809 | #define MWL8K_STAT_FCS_ERROR 24 | |
1810 | #define MWL8K_STAT_RTS_SUCCESS 11 | |
1811 | ||
55489b6e LB |
1812 | static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw, |
1813 | struct ieee80211_low_level_stats *stats) | |
a66098da | 1814 | { |
55489b6e | 1815 | struct mwl8k_cmd_get_stat *cmd; |
a66098da LB |
1816 | int rc; |
1817 | ||
1818 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1819 | if (cmd == NULL) | |
1820 | return -ENOMEM; | |
1821 | ||
1822 | cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT); | |
1823 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
1824 | |
1825 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1826 | if (!rc) { | |
1827 | stats->dot11ACKFailureCount = | |
1828 | le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]); | |
1829 | stats->dot11RTSFailureCount = | |
1830 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]); | |
1831 | stats->dot11FCSErrorCount = | |
1832 | le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]); | |
1833 | stats->dot11RTSSuccessCount = | |
1834 | le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]); | |
1835 | } | |
1836 | kfree(cmd); | |
1837 | ||
1838 | return rc; | |
1839 | } | |
1840 | ||
1841 | /* | |
55489b6e | 1842 | * CMD_RADIO_CONTROL. |
a66098da | 1843 | */ |
55489b6e | 1844 | struct mwl8k_cmd_radio_control { |
a66098da LB |
1845 | struct mwl8k_cmd_pkt header; |
1846 | __le16 action; | |
1847 | __le16 control; | |
1848 | __le16 radio_on; | |
1849 | } __attribute__((packed)); | |
1850 | ||
c46563b7 | 1851 | static int |
55489b6e | 1852 | mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force) |
a66098da LB |
1853 | { |
1854 | struct mwl8k_priv *priv = hw->priv; | |
55489b6e | 1855 | struct mwl8k_cmd_radio_control *cmd; |
a66098da LB |
1856 | int rc; |
1857 | ||
c46563b7 | 1858 | if (enable == priv->radio_on && !force) |
a66098da LB |
1859 | return 0; |
1860 | ||
a66098da LB |
1861 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
1862 | if (cmd == NULL) | |
1863 | return -ENOMEM; | |
1864 | ||
1865 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL); | |
1866 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1867 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
68ce3884 | 1868 | cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1); |
a66098da LB |
1869 | cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000); |
1870 | ||
1871 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1872 | kfree(cmd); | |
1873 | ||
1874 | if (!rc) | |
c46563b7 | 1875 | priv->radio_on = enable; |
a66098da LB |
1876 | |
1877 | return rc; | |
1878 | } | |
1879 | ||
55489b6e | 1880 | static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw) |
c46563b7 | 1881 | { |
55489b6e | 1882 | return mwl8k_cmd_radio_control(hw, 0, 0); |
c46563b7 LB |
1883 | } |
1884 | ||
55489b6e | 1885 | static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw) |
c46563b7 | 1886 | { |
55489b6e | 1887 | return mwl8k_cmd_radio_control(hw, 1, 0); |
c46563b7 LB |
1888 | } |
1889 | ||
a66098da LB |
1890 | static int |
1891 | mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble) | |
1892 | { | |
99200a99 | 1893 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 1894 | |
68ce3884 | 1895 | priv->radio_short_preamble = short_preamble; |
a66098da | 1896 | |
55489b6e | 1897 | return mwl8k_cmd_radio_control(hw, 1, 1); |
a66098da LB |
1898 | } |
1899 | ||
1900 | /* | |
55489b6e | 1901 | * CMD_RF_TX_POWER. |
a66098da LB |
1902 | */ |
1903 | #define MWL8K_TX_POWER_LEVEL_TOTAL 8 | |
1904 | ||
55489b6e | 1905 | struct mwl8k_cmd_rf_tx_power { |
a66098da LB |
1906 | struct mwl8k_cmd_pkt header; |
1907 | __le16 action; | |
1908 | __le16 support_level; | |
1909 | __le16 current_level; | |
1910 | __le16 reserved; | |
1911 | __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL]; | |
1912 | } __attribute__((packed)); | |
1913 | ||
55489b6e | 1914 | static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm) |
a66098da | 1915 | { |
55489b6e | 1916 | struct mwl8k_cmd_rf_tx_power *cmd; |
a66098da LB |
1917 | int rc; |
1918 | ||
1919 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1920 | if (cmd == NULL) | |
1921 | return -ENOMEM; | |
1922 | ||
1923 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER); | |
1924 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1925 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
1926 | cmd->support_level = cpu_to_le16(dBm); | |
1927 | ||
1928 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1929 | kfree(cmd); | |
1930 | ||
1931 | return rc; | |
1932 | } | |
1933 | ||
08b06347 LB |
1934 | /* |
1935 | * CMD_RF_ANTENNA. | |
1936 | */ | |
1937 | struct mwl8k_cmd_rf_antenna { | |
1938 | struct mwl8k_cmd_pkt header; | |
1939 | __le16 antenna; | |
1940 | __le16 mode; | |
1941 | } __attribute__((packed)); | |
1942 | ||
1943 | #define MWL8K_RF_ANTENNA_RX 1 | |
1944 | #define MWL8K_RF_ANTENNA_TX 2 | |
1945 | ||
1946 | static int | |
1947 | mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask) | |
1948 | { | |
1949 | struct mwl8k_cmd_rf_antenna *cmd; | |
1950 | int rc; | |
1951 | ||
1952 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1953 | if (cmd == NULL) | |
1954 | return -ENOMEM; | |
1955 | ||
1956 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA); | |
1957 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1958 | cmd->antenna = cpu_to_le16(antenna); | |
1959 | cmd->mode = cpu_to_le16(mask); | |
1960 | ||
1961 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1962 | kfree(cmd); | |
1963 | ||
1964 | return rc; | |
1965 | } | |
1966 | ||
a66098da LB |
1967 | /* |
1968 | * CMD_SET_PRE_SCAN. | |
1969 | */ | |
1970 | struct mwl8k_cmd_set_pre_scan { | |
1971 | struct mwl8k_cmd_pkt header; | |
1972 | } __attribute__((packed)); | |
1973 | ||
1974 | static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw) | |
1975 | { | |
1976 | struct mwl8k_cmd_set_pre_scan *cmd; | |
1977 | int rc; | |
1978 | ||
1979 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
1980 | if (cmd == NULL) | |
1981 | return -ENOMEM; | |
1982 | ||
1983 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN); | |
1984 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
1985 | ||
1986 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
1987 | kfree(cmd); | |
1988 | ||
1989 | return rc; | |
1990 | } | |
1991 | ||
1992 | /* | |
1993 | * CMD_SET_POST_SCAN. | |
1994 | */ | |
1995 | struct mwl8k_cmd_set_post_scan { | |
1996 | struct mwl8k_cmd_pkt header; | |
1997 | __le32 isibss; | |
d89173f2 | 1998 | __u8 bssid[ETH_ALEN]; |
a66098da LB |
1999 | } __attribute__((packed)); |
2000 | ||
2001 | static int | |
0a11dfc3 | 2002 | mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac) |
a66098da LB |
2003 | { |
2004 | struct mwl8k_cmd_set_post_scan *cmd; | |
2005 | int rc; | |
2006 | ||
2007 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2008 | if (cmd == NULL) | |
2009 | return -ENOMEM; | |
2010 | ||
2011 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN); | |
2012 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2013 | cmd->isibss = 0; | |
d89173f2 | 2014 | memcpy(cmd->bssid, mac, ETH_ALEN); |
a66098da LB |
2015 | |
2016 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2017 | kfree(cmd); | |
2018 | ||
2019 | return rc; | |
2020 | } | |
2021 | ||
2022 | /* | |
2023 | * CMD_SET_RF_CHANNEL. | |
2024 | */ | |
2025 | struct mwl8k_cmd_set_rf_channel { | |
2026 | struct mwl8k_cmd_pkt header; | |
2027 | __le16 action; | |
2028 | __u8 current_channel; | |
2029 | __le32 channel_flags; | |
2030 | } __attribute__((packed)); | |
2031 | ||
2032 | static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw, | |
610677d2 | 2033 | struct ieee80211_conf *conf) |
a66098da | 2034 | { |
610677d2 | 2035 | struct ieee80211_channel *channel = conf->channel; |
a66098da LB |
2036 | struct mwl8k_cmd_set_rf_channel *cmd; |
2037 | int rc; | |
2038 | ||
2039 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2040 | if (cmd == NULL) | |
2041 | return -ENOMEM; | |
2042 | ||
2043 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL); | |
2044 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2045 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2046 | cmd->current_channel = channel->hw_value; | |
610677d2 | 2047 | |
a66098da | 2048 | if (channel->band == IEEE80211_BAND_2GHZ) |
610677d2 LB |
2049 | cmd->channel_flags |= cpu_to_le32(0x00000001); |
2050 | ||
2051 | if (conf->channel_type == NL80211_CHAN_NO_HT || | |
2052 | conf->channel_type == NL80211_CHAN_HT20) | |
2053 | cmd->channel_flags |= cpu_to_le32(0x00000080); | |
2054 | else if (conf->channel_type == NL80211_CHAN_HT40MINUS) | |
2055 | cmd->channel_flags |= cpu_to_le32(0x000001900); | |
2056 | else if (conf->channel_type == NL80211_CHAN_HT40PLUS) | |
2057 | cmd->channel_flags |= cpu_to_le32(0x000000900); | |
a66098da LB |
2058 | |
2059 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2060 | kfree(cmd); | |
2061 | ||
2062 | return rc; | |
2063 | } | |
2064 | ||
2065 | /* | |
55489b6e | 2066 | * CMD_SET_AID. |
a66098da | 2067 | */ |
55489b6e LB |
2068 | #define MWL8K_FRAME_PROT_DISABLED 0x00 |
2069 | #define MWL8K_FRAME_PROT_11G 0x07 | |
2070 | #define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02 | |
2071 | #define MWL8K_FRAME_PROT_11N_HT_ALL 0x06 | |
a66098da | 2072 | |
55489b6e LB |
2073 | struct mwl8k_cmd_update_set_aid { |
2074 | struct mwl8k_cmd_pkt header; | |
2075 | __le16 aid; | |
a66098da | 2076 | |
55489b6e LB |
2077 | /* AP's MAC address (BSSID) */ |
2078 | __u8 bssid[ETH_ALEN]; | |
2079 | __le16 protection_mode; | |
2080 | __u8 supp_rates[14]; | |
a66098da LB |
2081 | } __attribute__((packed)); |
2082 | ||
c6e96010 LB |
2083 | static void legacy_rate_mask_to_array(u8 *rates, u32 mask) |
2084 | { | |
2085 | int i; | |
2086 | int j; | |
2087 | ||
2088 | /* | |
2089 | * Clear nonstandard rates 4 and 13. | |
2090 | */ | |
2091 | mask &= 0x1fef; | |
2092 | ||
2093 | for (i = 0, j = 0; i < 14; i++) { | |
2094 | if (mask & (1 << i)) | |
2095 | rates[j++] = mwl8k_rates[i].hw_value; | |
2096 | } | |
2097 | } | |
2098 | ||
55489b6e | 2099 | static int |
c6e96010 LB |
2100 | mwl8k_cmd_set_aid(struct ieee80211_hw *hw, |
2101 | struct ieee80211_vif *vif, u32 legacy_rate_mask) | |
a66098da | 2102 | { |
55489b6e LB |
2103 | struct mwl8k_cmd_update_set_aid *cmd; |
2104 | u16 prot_mode; | |
a66098da LB |
2105 | int rc; |
2106 | ||
2107 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2108 | if (cmd == NULL) | |
2109 | return -ENOMEM; | |
2110 | ||
55489b6e | 2111 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID); |
a66098da | 2112 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
7dc6a7a7 | 2113 | cmd->aid = cpu_to_le16(vif->bss_conf.aid); |
0a11dfc3 | 2114 | memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN); |
a66098da | 2115 | |
7dc6a7a7 | 2116 | if (vif->bss_conf.use_cts_prot) { |
55489b6e LB |
2117 | prot_mode = MWL8K_FRAME_PROT_11G; |
2118 | } else { | |
7dc6a7a7 | 2119 | switch (vif->bss_conf.ht_operation_mode & |
55489b6e LB |
2120 | IEEE80211_HT_OP_MODE_PROTECTION) { |
2121 | case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: | |
2122 | prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY; | |
2123 | break; | |
2124 | case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: | |
2125 | prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL; | |
2126 | break; | |
2127 | default: | |
2128 | prot_mode = MWL8K_FRAME_PROT_DISABLED; | |
2129 | break; | |
2130 | } | |
2131 | } | |
2132 | cmd->protection_mode = cpu_to_le16(prot_mode); | |
a66098da | 2133 | |
c6e96010 | 2134 | legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask); |
a66098da LB |
2135 | |
2136 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2137 | kfree(cmd); | |
2138 | ||
2139 | return rc; | |
2140 | } | |
2141 | ||
32060e1b | 2142 | /* |
55489b6e | 2143 | * CMD_SET_RATE. |
32060e1b | 2144 | */ |
55489b6e LB |
2145 | struct mwl8k_cmd_set_rate { |
2146 | struct mwl8k_cmd_pkt header; | |
2147 | __u8 legacy_rates[14]; | |
2148 | ||
2149 | /* Bitmap for supported MCS codes. */ | |
2150 | __u8 mcs_set[16]; | |
2151 | __u8 reserved[16]; | |
32060e1b LB |
2152 | } __attribute__((packed)); |
2153 | ||
55489b6e | 2154 | static int |
c6e96010 | 2155 | mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
13935e2c | 2156 | u32 legacy_rate_mask, u8 *mcs_rates) |
32060e1b | 2157 | { |
55489b6e | 2158 | struct mwl8k_cmd_set_rate *cmd; |
32060e1b LB |
2159 | int rc; |
2160 | ||
2161 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2162 | if (cmd == NULL) | |
2163 | return -ENOMEM; | |
2164 | ||
55489b6e | 2165 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE); |
32060e1b | 2166 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
c6e96010 | 2167 | legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask); |
13935e2c | 2168 | memcpy(cmd->mcs_set, mcs_rates, 16); |
32060e1b LB |
2169 | |
2170 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2171 | kfree(cmd); | |
2172 | ||
2173 | return rc; | |
2174 | } | |
2175 | ||
a66098da | 2176 | /* |
55489b6e | 2177 | * CMD_FINALIZE_JOIN. |
a66098da | 2178 | */ |
55489b6e LB |
2179 | #define MWL8K_FJ_BEACON_MAXLEN 128 |
2180 | ||
2181 | struct mwl8k_cmd_finalize_join { | |
a66098da | 2182 | struct mwl8k_cmd_pkt header; |
55489b6e LB |
2183 | __le32 sleep_interval; /* Number of beacon periods to sleep */ |
2184 | __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN]; | |
a66098da LB |
2185 | } __attribute__((packed)); |
2186 | ||
55489b6e LB |
2187 | static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame, |
2188 | int framelen, int dtim) | |
a66098da | 2189 | { |
55489b6e LB |
2190 | struct mwl8k_cmd_finalize_join *cmd; |
2191 | struct ieee80211_mgmt *payload = frame; | |
2192 | int payload_len; | |
a66098da LB |
2193 | int rc; |
2194 | ||
2195 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2196 | if (cmd == NULL) | |
2197 | return -ENOMEM; | |
2198 | ||
55489b6e | 2199 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN); |
a66098da | 2200 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2201 | cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1); |
2202 | ||
2203 | payload_len = framelen - ieee80211_hdrlen(payload->frame_control); | |
2204 | if (payload_len < 0) | |
2205 | payload_len = 0; | |
2206 | else if (payload_len > MWL8K_FJ_BEACON_MAXLEN) | |
2207 | payload_len = MWL8K_FJ_BEACON_MAXLEN; | |
2208 | ||
2209 | memcpy(cmd->beacon_data, &payload->u.beacon, payload_len); | |
a66098da LB |
2210 | |
2211 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2212 | kfree(cmd); | |
2213 | ||
2214 | return rc; | |
2215 | } | |
2216 | ||
2217 | /* | |
55489b6e | 2218 | * CMD_SET_RTS_THRESHOLD. |
a66098da | 2219 | */ |
55489b6e | 2220 | struct mwl8k_cmd_set_rts_threshold { |
a66098da LB |
2221 | struct mwl8k_cmd_pkt header; |
2222 | __le16 action; | |
55489b6e | 2223 | __le16 threshold; |
a66098da LB |
2224 | } __attribute__((packed)); |
2225 | ||
55489b6e LB |
2226 | static int mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, |
2227 | u16 action, u16 threshold) | |
a66098da | 2228 | { |
55489b6e | 2229 | struct mwl8k_cmd_set_rts_threshold *cmd; |
a66098da LB |
2230 | int rc; |
2231 | ||
2232 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2233 | if (cmd == NULL) | |
2234 | return -ENOMEM; | |
2235 | ||
55489b6e | 2236 | cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD); |
a66098da | 2237 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2238 | cmd->action = cpu_to_le16(action); |
2239 | cmd->threshold = cpu_to_le16(threshold); | |
a66098da LB |
2240 | |
2241 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2242 | kfree(cmd); | |
2243 | ||
a66098da LB |
2244 | return rc; |
2245 | } | |
2246 | ||
2247 | /* | |
55489b6e | 2248 | * CMD_SET_SLOT. |
a66098da | 2249 | */ |
55489b6e | 2250 | struct mwl8k_cmd_set_slot { |
a66098da LB |
2251 | struct mwl8k_cmd_pkt header; |
2252 | __le16 action; | |
55489b6e | 2253 | __u8 short_slot; |
a66098da LB |
2254 | } __attribute__((packed)); |
2255 | ||
55489b6e | 2256 | static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time) |
a66098da | 2257 | { |
55489b6e | 2258 | struct mwl8k_cmd_set_slot *cmd; |
a66098da LB |
2259 | int rc; |
2260 | ||
2261 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2262 | if (cmd == NULL) | |
2263 | return -ENOMEM; | |
2264 | ||
55489b6e | 2265 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT); |
a66098da | 2266 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2267 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); |
2268 | cmd->short_slot = short_slot_time; | |
a66098da LB |
2269 | |
2270 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2271 | kfree(cmd); | |
2272 | ||
2273 | return rc; | |
2274 | } | |
2275 | ||
2276 | /* | |
2277 | * CMD_SET_EDCA_PARAMS. | |
2278 | */ | |
2279 | struct mwl8k_cmd_set_edca_params { | |
2280 | struct mwl8k_cmd_pkt header; | |
2281 | ||
2282 | /* See MWL8K_SET_EDCA_XXX below */ | |
2283 | __le16 action; | |
2284 | ||
2285 | /* TX opportunity in units of 32 us */ | |
2286 | __le16 txop; | |
2287 | ||
2e484c89 LB |
2288 | union { |
2289 | struct { | |
2290 | /* Log exponent of max contention period: 0...15 */ | |
2291 | __le32 log_cw_max; | |
2292 | ||
2293 | /* Log exponent of min contention period: 0...15 */ | |
2294 | __le32 log_cw_min; | |
2295 | ||
2296 | /* Adaptive interframe spacing in units of 32us */ | |
2297 | __u8 aifs; | |
2298 | ||
2299 | /* TX queue to configure */ | |
2300 | __u8 txq; | |
2301 | } ap; | |
2302 | struct { | |
2303 | /* Log exponent of max contention period: 0...15 */ | |
2304 | __u8 log_cw_max; | |
a66098da | 2305 | |
2e484c89 LB |
2306 | /* Log exponent of min contention period: 0...15 */ |
2307 | __u8 log_cw_min; | |
a66098da | 2308 | |
2e484c89 LB |
2309 | /* Adaptive interframe spacing in units of 32us */ |
2310 | __u8 aifs; | |
a66098da | 2311 | |
2e484c89 LB |
2312 | /* TX queue to configure */ |
2313 | __u8 txq; | |
2314 | } sta; | |
2315 | }; | |
a66098da LB |
2316 | } __attribute__((packed)); |
2317 | ||
a66098da LB |
2318 | #define MWL8K_SET_EDCA_CW 0x01 |
2319 | #define MWL8K_SET_EDCA_TXOP 0x02 | |
2320 | #define MWL8K_SET_EDCA_AIFS 0x04 | |
2321 | ||
2322 | #define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \ | |
2323 | MWL8K_SET_EDCA_TXOP | \ | |
2324 | MWL8K_SET_EDCA_AIFS) | |
2325 | ||
2326 | static int | |
55489b6e LB |
2327 | mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum, |
2328 | __u16 cw_min, __u16 cw_max, | |
2329 | __u8 aifs, __u16 txop) | |
a66098da | 2330 | { |
2e484c89 | 2331 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 2332 | struct mwl8k_cmd_set_edca_params *cmd; |
a66098da LB |
2333 | int rc; |
2334 | ||
2335 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2336 | if (cmd == NULL) | |
2337 | return -ENOMEM; | |
2338 | ||
22995b24 LB |
2339 | /* |
2340 | * Queues 0 (BE) and 1 (BK) are swapped in hardware for | |
2341 | * this call. | |
2342 | */ | |
2343 | qnum ^= !(qnum >> 1); | |
2344 | ||
a66098da LB |
2345 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS); |
2346 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a66098da LB |
2347 | cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL); |
2348 | cmd->txop = cpu_to_le16(txop); | |
2e484c89 LB |
2349 | if (priv->ap_fw) { |
2350 | cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1)); | |
2351 | cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1)); | |
2352 | cmd->ap.aifs = aifs; | |
2353 | cmd->ap.txq = qnum; | |
2354 | } else { | |
2355 | cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1); | |
2356 | cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1); | |
2357 | cmd->sta.aifs = aifs; | |
2358 | cmd->sta.txq = qnum; | |
2359 | } | |
a66098da LB |
2360 | |
2361 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2362 | kfree(cmd); | |
2363 | ||
2364 | return rc; | |
2365 | } | |
2366 | ||
2367 | /* | |
55489b6e | 2368 | * CMD_SET_WMM_MODE. |
a66098da | 2369 | */ |
55489b6e | 2370 | struct mwl8k_cmd_set_wmm_mode { |
a66098da | 2371 | struct mwl8k_cmd_pkt header; |
55489b6e | 2372 | __le16 action; |
a66098da LB |
2373 | } __attribute__((packed)); |
2374 | ||
55489b6e | 2375 | static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable) |
a66098da | 2376 | { |
55489b6e LB |
2377 | struct mwl8k_priv *priv = hw->priv; |
2378 | struct mwl8k_cmd_set_wmm_mode *cmd; | |
a66098da LB |
2379 | int rc; |
2380 | ||
a66098da LB |
2381 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); |
2382 | if (cmd == NULL) | |
2383 | return -ENOMEM; | |
2384 | ||
55489b6e | 2385 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE); |
a66098da | 2386 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e | 2387 | cmd->action = cpu_to_le16(!!enable); |
a66098da LB |
2388 | |
2389 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2390 | kfree(cmd); | |
16cec43d | 2391 | |
55489b6e LB |
2392 | if (!rc) |
2393 | priv->wmm_enabled = enable; | |
a66098da LB |
2394 | |
2395 | return rc; | |
2396 | } | |
2397 | ||
2398 | /* | |
55489b6e | 2399 | * CMD_MIMO_CONFIG. |
a66098da | 2400 | */ |
55489b6e LB |
2401 | struct mwl8k_cmd_mimo_config { |
2402 | struct mwl8k_cmd_pkt header; | |
2403 | __le32 action; | |
2404 | __u8 rx_antenna_map; | |
2405 | __u8 tx_antenna_map; | |
a66098da LB |
2406 | } __attribute__((packed)); |
2407 | ||
55489b6e | 2408 | static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx) |
a66098da | 2409 | { |
55489b6e | 2410 | struct mwl8k_cmd_mimo_config *cmd; |
a66098da LB |
2411 | int rc; |
2412 | ||
2413 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2414 | if (cmd == NULL) | |
2415 | return -ENOMEM; | |
2416 | ||
55489b6e | 2417 | cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG); |
a66098da | 2418 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); |
55489b6e LB |
2419 | cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET); |
2420 | cmd->rx_antenna_map = rx; | |
2421 | cmd->tx_antenna_map = tx; | |
a66098da LB |
2422 | |
2423 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2424 | kfree(cmd); | |
2425 | ||
2426 | return rc; | |
2427 | } | |
2428 | ||
2429 | /* | |
2430 | * CMD_USE_FIXED_RATE. | |
2431 | */ | |
2432 | #define MWL8K_RATE_TABLE_SIZE 8 | |
2433 | #define MWL8K_UCAST_RATE 0 | |
a66098da LB |
2434 | #define MWL8K_USE_AUTO_RATE 0x0002 |
2435 | ||
2436 | struct mwl8k_rate_entry { | |
2437 | /* Set to 1 if HT rate, 0 if legacy. */ | |
2438 | __le32 is_ht_rate; | |
2439 | ||
2440 | /* Set to 1 to use retry_count field. */ | |
2441 | __le32 enable_retry; | |
2442 | ||
2443 | /* Specified legacy rate or MCS. */ | |
2444 | __le32 rate; | |
2445 | ||
2446 | /* Number of allowed retries. */ | |
2447 | __le32 retry_count; | |
2448 | } __attribute__((packed)); | |
2449 | ||
2450 | struct mwl8k_rate_table { | |
2451 | /* 1 to allow specified rate and below */ | |
2452 | __le32 allow_rate_drop; | |
2453 | __le32 num_rates; | |
2454 | struct mwl8k_rate_entry rate_entry[MWL8K_RATE_TABLE_SIZE]; | |
2455 | } __attribute__((packed)); | |
2456 | ||
2457 | struct mwl8k_cmd_use_fixed_rate { | |
2458 | struct mwl8k_cmd_pkt header; | |
2459 | __le32 action; | |
2460 | struct mwl8k_rate_table rate_table; | |
2461 | ||
2462 | /* Unicast, Broadcast or Multicast */ | |
2463 | __le32 rate_type; | |
2464 | __le32 reserved1; | |
2465 | __le32 reserved2; | |
2466 | } __attribute__((packed)); | |
2467 | ||
2468 | static int mwl8k_cmd_use_fixed_rate(struct ieee80211_hw *hw, | |
2469 | u32 action, u32 rate_type, struct mwl8k_rate_table *rate_table) | |
2470 | { | |
2471 | struct mwl8k_cmd_use_fixed_rate *cmd; | |
2472 | int count; | |
2473 | int rc; | |
2474 | ||
2475 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2476 | if (cmd == NULL) | |
2477 | return -ENOMEM; | |
2478 | ||
2479 | cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE); | |
2480 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2481 | ||
2482 | cmd->action = cpu_to_le32(action); | |
2483 | cmd->rate_type = cpu_to_le32(rate_type); | |
2484 | ||
2485 | if (rate_table != NULL) { | |
c2c357ce LB |
2486 | /* |
2487 | * Copy over each field manually so that endian | |
2488 | * conversion can be done. | |
2489 | */ | |
a66098da LB |
2490 | cmd->rate_table.allow_rate_drop = |
2491 | cpu_to_le32(rate_table->allow_rate_drop); | |
2492 | cmd->rate_table.num_rates = | |
2493 | cpu_to_le32(rate_table->num_rates); | |
2494 | ||
2495 | for (count = 0; count < rate_table->num_rates; count++) { | |
2496 | struct mwl8k_rate_entry *dst = | |
2497 | &cmd->rate_table.rate_entry[count]; | |
2498 | struct mwl8k_rate_entry *src = | |
2499 | &rate_table->rate_entry[count]; | |
2500 | ||
2501 | dst->is_ht_rate = cpu_to_le32(src->is_ht_rate); | |
2502 | dst->enable_retry = cpu_to_le32(src->enable_retry); | |
2503 | dst->rate = cpu_to_le32(src->rate); | |
2504 | dst->retry_count = cpu_to_le32(src->retry_count); | |
2505 | } | |
2506 | } | |
2507 | ||
2508 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2509 | kfree(cmd); | |
2510 | ||
2511 | return rc; | |
2512 | } | |
2513 | ||
55489b6e LB |
2514 | /* |
2515 | * CMD_ENABLE_SNIFFER. | |
2516 | */ | |
2517 | struct mwl8k_cmd_enable_sniffer { | |
2518 | struct mwl8k_cmd_pkt header; | |
2519 | __le32 action; | |
2520 | } __attribute__((packed)); | |
2521 | ||
2522 | static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable) | |
2523 | { | |
2524 | struct mwl8k_cmd_enable_sniffer *cmd; | |
2525 | int rc; | |
2526 | ||
2527 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2528 | if (cmd == NULL) | |
2529 | return -ENOMEM; | |
2530 | ||
2531 | cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER); | |
2532 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2533 | cmd->action = cpu_to_le32(!!enable); | |
2534 | ||
2535 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2536 | kfree(cmd); | |
2537 | ||
2538 | return rc; | |
2539 | } | |
2540 | ||
2541 | /* | |
2542 | * CMD_SET_MAC_ADDR. | |
2543 | */ | |
2544 | struct mwl8k_cmd_set_mac_addr { | |
2545 | struct mwl8k_cmd_pkt header; | |
2546 | union { | |
2547 | struct { | |
2548 | __le16 mac_type; | |
2549 | __u8 mac_addr[ETH_ALEN]; | |
2550 | } mbss; | |
2551 | __u8 mac_addr[ETH_ALEN]; | |
2552 | }; | |
2553 | } __attribute__((packed)); | |
2554 | ||
2555 | static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac) | |
2556 | { | |
2557 | struct mwl8k_priv *priv = hw->priv; | |
2558 | struct mwl8k_cmd_set_mac_addr *cmd; | |
2559 | int rc; | |
2560 | ||
2561 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2562 | if (cmd == NULL) | |
2563 | return -ENOMEM; | |
2564 | ||
2565 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR); | |
2566 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2567 | if (priv->ap_fw) { | |
2568 | cmd->mbss.mac_type = 0; | |
2569 | memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN); | |
2570 | } else { | |
2571 | memcpy(cmd->mac_addr, mac, ETH_ALEN); | |
2572 | } | |
2573 | ||
2574 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2575 | kfree(cmd); | |
2576 | ||
2577 | return rc; | |
2578 | } | |
2579 | ||
2580 | /* | |
2581 | * CMD_SET_RATEADAPT_MODE. | |
2582 | */ | |
2583 | struct mwl8k_cmd_set_rate_adapt_mode { | |
2584 | struct mwl8k_cmd_pkt header; | |
2585 | __le16 action; | |
2586 | __le16 mode; | |
2587 | } __attribute__((packed)); | |
2588 | ||
2589 | static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode) | |
2590 | { | |
2591 | struct mwl8k_cmd_set_rate_adapt_mode *cmd; | |
2592 | int rc; | |
2593 | ||
2594 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2595 | if (cmd == NULL) | |
2596 | return -ENOMEM; | |
2597 | ||
2598 | cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE); | |
2599 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2600 | cmd->action = cpu_to_le16(MWL8K_CMD_SET); | |
2601 | cmd->mode = cpu_to_le16(mode); | |
2602 | ||
2603 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2604 | kfree(cmd); | |
2605 | ||
2606 | return rc; | |
2607 | } | |
2608 | ||
2609 | /* | |
2610 | * CMD_UPDATE_STADB. | |
2611 | */ | |
25d81b1e LB |
2612 | struct ewc_ht_info { |
2613 | __le16 control1; | |
2614 | __le16 control2; | |
2615 | __le16 control3; | |
2616 | } __attribute__((packed)); | |
2617 | ||
2618 | struct peer_capability_info { | |
2619 | /* Peer type - AP vs. STA. */ | |
2620 | __u8 peer_type; | |
2621 | ||
2622 | /* Basic 802.11 capabilities from assoc resp. */ | |
2623 | __le16 basic_caps; | |
2624 | ||
2625 | /* Set if peer supports 802.11n high throughput (HT). */ | |
2626 | __u8 ht_support; | |
2627 | ||
2628 | /* Valid if HT is supported. */ | |
2629 | __le16 ht_caps; | |
2630 | __u8 extended_ht_caps; | |
2631 | struct ewc_ht_info ewc_info; | |
2632 | ||
2633 | /* Legacy rate table. Intersection of our rates and peer rates. */ | |
2634 | __u8 legacy_rates[12]; | |
2635 | ||
2636 | /* HT rate table. Intersection of our rates and peer rates. */ | |
2637 | __u8 ht_rates[16]; | |
2638 | __u8 pad[16]; | |
2639 | ||
2640 | /* If set, interoperability mode, no proprietary extensions. */ | |
2641 | __u8 interop; | |
2642 | __u8 pad2; | |
2643 | __u8 station_id; | |
2644 | __le16 amsdu_enabled; | |
2645 | } __attribute__((packed)); | |
2646 | ||
55489b6e LB |
2647 | struct mwl8k_cmd_update_stadb { |
2648 | struct mwl8k_cmd_pkt header; | |
2649 | ||
2650 | /* See STADB_ACTION_TYPE */ | |
2651 | __le32 action; | |
2652 | ||
2653 | /* Peer MAC address */ | |
2654 | __u8 peer_addr[ETH_ALEN]; | |
2655 | ||
2656 | __le32 reserved; | |
2657 | ||
2658 | /* Peer info - valid during add/update. */ | |
2659 | struct peer_capability_info peer_info; | |
2660 | } __attribute__((packed)); | |
2661 | ||
a680400e LB |
2662 | #define MWL8K_STA_DB_MODIFY_ENTRY 1 |
2663 | #define MWL8K_STA_DB_DEL_ENTRY 2 | |
2664 | ||
2665 | /* Peer Entry flags - used to define the type of the peer node */ | |
2666 | #define MWL8K_PEER_TYPE_ACCESSPOINT 2 | |
2667 | ||
2668 | static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw, | |
c6e96010 | 2669 | struct ieee80211_vif *vif, |
13935e2c | 2670 | struct ieee80211_sta *sta) |
55489b6e | 2671 | { |
55489b6e | 2672 | struct mwl8k_cmd_update_stadb *cmd; |
a680400e | 2673 | struct peer_capability_info *p; |
55489b6e LB |
2674 | int rc; |
2675 | ||
2676 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2677 | if (cmd == NULL) | |
2678 | return -ENOMEM; | |
2679 | ||
2680 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
2681 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
a680400e | 2682 | cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY); |
13935e2c | 2683 | memcpy(cmd->peer_addr, sta->addr, ETH_ALEN); |
55489b6e | 2684 | |
a680400e LB |
2685 | p = &cmd->peer_info; |
2686 | p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT; | |
2687 | p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability); | |
13935e2c LB |
2688 | p->ht_support = sta->ht_cap.ht_supported; |
2689 | p->ht_caps = sta->ht_cap.cap; | |
2690 | p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) | | |
2691 | ((sta->ht_cap.ampdu_density & 7) << 2); | |
2692 | legacy_rate_mask_to_array(p->legacy_rates, | |
2693 | sta->supp_rates[IEEE80211_BAND_2GHZ]); | |
2694 | memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16); | |
a680400e LB |
2695 | p->interop = 1; |
2696 | p->amsdu_enabled = 0; | |
2697 | ||
2698 | rc = mwl8k_post_cmd(hw, &cmd->header); | |
2699 | kfree(cmd); | |
2700 | ||
2701 | return rc ? rc : p->station_id; | |
2702 | } | |
2703 | ||
2704 | static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw, | |
2705 | struct ieee80211_vif *vif, u8 *addr) | |
2706 | { | |
2707 | struct mwl8k_cmd_update_stadb *cmd; | |
2708 | int rc; | |
2709 | ||
2710 | cmd = kzalloc(sizeof(*cmd), GFP_KERNEL); | |
2711 | if (cmd == NULL) | |
2712 | return -ENOMEM; | |
2713 | ||
2714 | cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB); | |
2715 | cmd->header.length = cpu_to_le16(sizeof(*cmd)); | |
2716 | cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY); | |
bbfd9128 | 2717 | memcpy(cmd->peer_addr, addr, ETH_ALEN); |
55489b6e | 2718 | |
a680400e | 2719 | rc = mwl8k_post_cmd(hw, &cmd->header); |
55489b6e LB |
2720 | kfree(cmd); |
2721 | ||
2722 | return rc; | |
2723 | } | |
2724 | ||
a66098da LB |
2725 | |
2726 | /* | |
2727 | * Interrupt handling. | |
2728 | */ | |
2729 | static irqreturn_t mwl8k_interrupt(int irq, void *dev_id) | |
2730 | { | |
2731 | struct ieee80211_hw *hw = dev_id; | |
2732 | struct mwl8k_priv *priv = hw->priv; | |
2733 | u32 status; | |
2734 | ||
2735 | status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2736 | iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
2737 | ||
a66098da LB |
2738 | if (!status) |
2739 | return IRQ_NONE; | |
2740 | ||
2741 | if (status & MWL8K_A2H_INT_TX_DONE) | |
2742 | tasklet_schedule(&priv->tx_reclaim_task); | |
2743 | ||
2744 | if (status & MWL8K_A2H_INT_RX_READY) { | |
2745 | while (rxq_process(hw, 0, 1)) | |
2746 | rxq_refill(hw, 0, 1); | |
2747 | } | |
2748 | ||
2749 | if (status & MWL8K_A2H_INT_OPC_DONE) { | |
618952a7 | 2750 | if (priv->hostcmd_wait != NULL) |
a66098da | 2751 | complete(priv->hostcmd_wait); |
a66098da LB |
2752 | } |
2753 | ||
2754 | if (status & MWL8K_A2H_INT_QUEUE_EMPTY) { | |
618952a7 | 2755 | if (!mutex_is_locked(&priv->fw_mutex) && |
88de754a | 2756 | priv->radio_on && priv->pending_tx_pkts) |
618952a7 | 2757 | mwl8k_tx_start(priv); |
a66098da LB |
2758 | } |
2759 | ||
2760 | return IRQ_HANDLED; | |
2761 | } | |
2762 | ||
2763 | ||
2764 | /* | |
2765 | * Core driver operations. | |
2766 | */ | |
2767 | static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |
2768 | { | |
2769 | struct mwl8k_priv *priv = hw->priv; | |
2770 | int index = skb_get_queue_mapping(skb); | |
2771 | int rc; | |
2772 | ||
2773 | if (priv->current_channel == NULL) { | |
2774 | printk(KERN_DEBUG "%s: dropped TX frame since radio " | |
c2c357ce | 2775 | "disabled\n", wiphy_name(hw->wiphy)); |
a66098da LB |
2776 | dev_kfree_skb(skb); |
2777 | return NETDEV_TX_OK; | |
2778 | } | |
2779 | ||
2780 | rc = mwl8k_txq_xmit(hw, index, skb); | |
2781 | ||
2782 | return rc; | |
2783 | } | |
2784 | ||
a66098da LB |
2785 | static int mwl8k_start(struct ieee80211_hw *hw) |
2786 | { | |
a66098da LB |
2787 | struct mwl8k_priv *priv = hw->priv; |
2788 | int rc; | |
2789 | ||
a0607fd3 | 2790 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
2791 | IRQF_SHARED, MWL8K_NAME, hw); |
2792 | if (rc) { | |
2793 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 2794 | wiphy_name(hw->wiphy)); |
2ec610cb | 2795 | return -EIO; |
a66098da LB |
2796 | } |
2797 | ||
2ec610cb LB |
2798 | /* Enable tx reclaim tasklet */ |
2799 | tasklet_enable(&priv->tx_reclaim_task); | |
2800 | ||
a66098da | 2801 | /* Enable interrupts */ |
c23b5a69 | 2802 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da | 2803 | |
2ec610cb LB |
2804 | rc = mwl8k_fw_lock(hw); |
2805 | if (!rc) { | |
55489b6e | 2806 | rc = mwl8k_cmd_radio_enable(hw); |
a66098da | 2807 | |
5e4cf166 LB |
2808 | if (!priv->ap_fw) { |
2809 | if (!rc) | |
55489b6e | 2810 | rc = mwl8k_cmd_enable_sniffer(hw, 0); |
a66098da | 2811 | |
5e4cf166 LB |
2812 | if (!rc) |
2813 | rc = mwl8k_cmd_set_pre_scan(hw); | |
2814 | ||
2815 | if (!rc) | |
2816 | rc = mwl8k_cmd_set_post_scan(hw, | |
2817 | "\x00\x00\x00\x00\x00\x00"); | |
2818 | } | |
2ec610cb LB |
2819 | |
2820 | if (!rc) | |
55489b6e | 2821 | rc = mwl8k_cmd_set_rateadapt_mode(hw, 0); |
a66098da | 2822 | |
2ec610cb | 2823 | if (!rc) |
55489b6e | 2824 | rc = mwl8k_cmd_set_wmm_mode(hw, 0); |
a66098da | 2825 | |
2ec610cb LB |
2826 | mwl8k_fw_unlock(hw); |
2827 | } | |
2828 | ||
2829 | if (rc) { | |
2830 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); | |
2831 | free_irq(priv->pdev->irq, hw); | |
2832 | tasklet_disable(&priv->tx_reclaim_task); | |
2833 | } | |
a66098da LB |
2834 | |
2835 | return rc; | |
2836 | } | |
2837 | ||
a66098da LB |
2838 | static void mwl8k_stop(struct ieee80211_hw *hw) |
2839 | { | |
a66098da LB |
2840 | struct mwl8k_priv *priv = hw->priv; |
2841 | int i; | |
2842 | ||
55489b6e | 2843 | mwl8k_cmd_radio_disable(hw); |
a66098da LB |
2844 | |
2845 | ieee80211_stop_queues(hw); | |
2846 | ||
a66098da | 2847 | /* Disable interrupts */ |
a66098da | 2848 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
2849 | free_irq(priv->pdev->irq, hw); |
2850 | ||
2851 | /* Stop finalize join worker */ | |
2852 | cancel_work_sync(&priv->finalize_join_worker); | |
2853 | if (priv->beacon_skb != NULL) | |
2854 | dev_kfree_skb(priv->beacon_skb); | |
2855 | ||
2856 | /* Stop tx reclaim tasklet */ | |
2857 | tasklet_disable(&priv->tx_reclaim_task); | |
2858 | ||
a66098da LB |
2859 | /* Return all skbs to mac80211 */ |
2860 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
2861 | mwl8k_txq_reclaim(hw, i, 1); | |
2862 | } | |
2863 | ||
2864 | static int mwl8k_add_interface(struct ieee80211_hw *hw, | |
1ed32e4f | 2865 | struct ieee80211_vif *vif) |
a66098da LB |
2866 | { |
2867 | struct mwl8k_priv *priv = hw->priv; | |
2868 | struct mwl8k_vif *mwl8k_vif; | |
2869 | ||
2870 | /* | |
2871 | * We only support one active interface at a time. | |
2872 | */ | |
2873 | if (priv->vif != NULL) | |
2874 | return -EBUSY; | |
2875 | ||
2876 | /* | |
2877 | * We only support managed interfaces for now. | |
2878 | */ | |
1ed32e4f | 2879 | if (vif->type != NL80211_IFTYPE_STATION) |
a66098da LB |
2880 | return -EINVAL; |
2881 | ||
a43c49a8 LB |
2882 | /* |
2883 | * Reject interface creation if sniffer mode is active, as | |
2884 | * STA operation is mutually exclusive with hardware sniffer | |
2885 | * mode. | |
2886 | */ | |
2887 | if (priv->sniffer_enabled) { | |
2888 | printk(KERN_INFO "%s: unable to create STA " | |
2889 | "interface due to sniffer mode being enabled\n", | |
2890 | wiphy_name(hw->wiphy)); | |
2891 | return -EINVAL; | |
2892 | } | |
2893 | ||
a66098da | 2894 | /* Clean out driver private area */ |
1ed32e4f | 2895 | mwl8k_vif = MWL8K_VIF(vif); |
a66098da LB |
2896 | memset(mwl8k_vif, 0, sizeof(*mwl8k_vif)); |
2897 | ||
32060e1b | 2898 | /* Set and save the mac address */ |
1ed32e4f JB |
2899 | mwl8k_cmd_set_mac_addr(hw, vif->addr); |
2900 | memcpy(mwl8k_vif->mac_addr, vif->addr, ETH_ALEN); | |
a66098da | 2901 | |
a66098da LB |
2902 | /* Set Initial sequence number to zero */ |
2903 | mwl8k_vif->seqno = 0; | |
2904 | ||
1ed32e4f | 2905 | priv->vif = vif; |
a66098da LB |
2906 | priv->current_channel = NULL; |
2907 | ||
2908 | return 0; | |
2909 | } | |
2910 | ||
2911 | static void mwl8k_remove_interface(struct ieee80211_hw *hw, | |
1ed32e4f | 2912 | struct ieee80211_vif *vif) |
a66098da LB |
2913 | { |
2914 | struct mwl8k_priv *priv = hw->priv; | |
2915 | ||
2916 | if (priv->vif == NULL) | |
2917 | return; | |
2918 | ||
55489b6e | 2919 | mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
32060e1b | 2920 | |
a66098da LB |
2921 | priv->vif = NULL; |
2922 | } | |
2923 | ||
ee03a932 | 2924 | static int mwl8k_config(struct ieee80211_hw *hw, u32 changed) |
a66098da | 2925 | { |
a66098da LB |
2926 | struct ieee80211_conf *conf = &hw->conf; |
2927 | struct mwl8k_priv *priv = hw->priv; | |
ee03a932 | 2928 | int rc; |
a66098da | 2929 | |
7595d67a | 2930 | if (conf->flags & IEEE80211_CONF_IDLE) { |
55489b6e | 2931 | mwl8k_cmd_radio_disable(hw); |
7595d67a | 2932 | priv->current_channel = NULL; |
ee03a932 | 2933 | return 0; |
7595d67a LB |
2934 | } |
2935 | ||
ee03a932 LB |
2936 | rc = mwl8k_fw_lock(hw); |
2937 | if (rc) | |
2938 | return rc; | |
a66098da | 2939 | |
55489b6e | 2940 | rc = mwl8k_cmd_radio_enable(hw); |
ee03a932 LB |
2941 | if (rc) |
2942 | goto out; | |
a66098da | 2943 | |
610677d2 | 2944 | rc = mwl8k_cmd_set_rf_channel(hw, conf); |
ee03a932 LB |
2945 | if (rc) |
2946 | goto out; | |
2947 | ||
2948 | priv->current_channel = conf->channel; | |
a66098da LB |
2949 | |
2950 | if (conf->power_level > 18) | |
2951 | conf->power_level = 18; | |
55489b6e | 2952 | rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level); |
ee03a932 LB |
2953 | if (rc) |
2954 | goto out; | |
a66098da | 2955 | |
08b06347 LB |
2956 | if (priv->ap_fw) { |
2957 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7); | |
2958 | if (!rc) | |
2959 | rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7); | |
2960 | } else { | |
2961 | rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7); | |
2962 | } | |
a66098da | 2963 | |
ee03a932 LB |
2964 | out: |
2965 | mwl8k_fw_unlock(hw); | |
a66098da | 2966 | |
ee03a932 | 2967 | return rc; |
a66098da LB |
2968 | } |
2969 | ||
3a980d0a LB |
2970 | static void mwl8k_bss_info_changed(struct ieee80211_hw *hw, |
2971 | struct ieee80211_vif *vif, | |
2972 | struct ieee80211_bss_conf *info, | |
2973 | u32 changed) | |
a66098da | 2974 | { |
a66098da | 2975 | struct mwl8k_priv *priv = hw->priv; |
c3cbbe8a | 2976 | u32 ap_legacy_rates; |
13935e2c | 2977 | u8 ap_mcs_rates[16]; |
3a980d0a LB |
2978 | int rc; |
2979 | ||
c3cbbe8a | 2980 | if (mwl8k_fw_lock(hw)) |
3a980d0a | 2981 | return; |
a66098da | 2982 | |
c3cbbe8a LB |
2983 | /* |
2984 | * No need to capture a beacon if we're no longer associated. | |
2985 | */ | |
2986 | if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc) | |
2987 | priv->capture_beacon = false; | |
3a980d0a | 2988 | |
c3cbbe8a | 2989 | /* |
13935e2c | 2990 | * Get the AP's legacy and MCS rates. |
c3cbbe8a LB |
2991 | */ |
2992 | ap_legacy_rates = 0; | |
7dc6a7a7 | 2993 | if (vif->bss_conf.assoc) { |
c6e96010 | 2994 | struct ieee80211_sta *ap; |
c6e96010 | 2995 | rcu_read_lock(); |
c6e96010 | 2996 | |
c3cbbe8a LB |
2997 | ap = ieee80211_find_sta(vif, vif->bss_conf.bssid); |
2998 | if (ap == NULL) { | |
2999 | rcu_read_unlock(); | |
c6e96010 | 3000 | goto out; |
c3cbbe8a LB |
3001 | } |
3002 | ||
3003 | ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ]; | |
13935e2c | 3004 | memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16); |
c3cbbe8a LB |
3005 | |
3006 | rcu_read_unlock(); | |
3007 | } | |
c6e96010 | 3008 | |
c3cbbe8a | 3009 | if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) { |
13935e2c | 3010 | rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates); |
3a980d0a LB |
3011 | if (rc) |
3012 | goto out; | |
a66098da | 3013 | |
3a980d0a LB |
3014 | rc = mwl8k_cmd_use_fixed_rate(hw, MWL8K_USE_AUTO_RATE, |
3015 | MWL8K_UCAST_RATE, NULL); | |
3016 | if (rc) | |
3017 | goto out; | |
c3cbbe8a | 3018 | } |
a66098da | 3019 | |
c3cbbe8a | 3020 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
7dc6a7a7 LB |
3021 | rc = mwl8k_set_radio_preamble(hw, |
3022 | vif->bss_conf.use_short_preamble); | |
3a980d0a LB |
3023 | if (rc) |
3024 | goto out; | |
c3cbbe8a | 3025 | } |
a66098da | 3026 | |
c3cbbe8a | 3027 | if (changed & BSS_CHANGED_ERP_SLOT) { |
7dc6a7a7 | 3028 | rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot); |
3a980d0a LB |
3029 | if (rc) |
3030 | goto out; | |
c3cbbe8a | 3031 | } |
a66098da | 3032 | |
c3cbbe8a LB |
3033 | if (((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) || |
3034 | (changed & (BSS_CHANGED_ERP_CTS_PROT | BSS_CHANGED_HT))) { | |
3035 | rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates); | |
3a980d0a LB |
3036 | if (rc) |
3037 | goto out; | |
c3cbbe8a | 3038 | } |
a66098da | 3039 | |
c3cbbe8a LB |
3040 | if (vif->bss_conf.assoc && |
3041 | (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) { | |
a66098da LB |
3042 | /* |
3043 | * Finalize the join. Tell rx handler to process | |
3044 | * next beacon from our BSSID. | |
3045 | */ | |
0a11dfc3 | 3046 | memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN); |
a66098da | 3047 | priv->capture_beacon = true; |
a66098da LB |
3048 | } |
3049 | ||
3a980d0a LB |
3050 | out: |
3051 | mwl8k_fw_unlock(hw); | |
a66098da LB |
3052 | } |
3053 | ||
e81cd2d6 LB |
3054 | static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw, |
3055 | int mc_count, struct dev_addr_list *mclist) | |
3056 | { | |
3057 | struct mwl8k_cmd_pkt *cmd; | |
3058 | ||
447ced07 LB |
3059 | /* |
3060 | * Synthesize and return a command packet that programs the | |
3061 | * hardware multicast address filter. At this point we don't | |
3062 | * know whether FIF_ALLMULTI is being requested, but if it is, | |
3063 | * we'll end up throwing this packet away and creating a new | |
3064 | * one in mwl8k_configure_filter(). | |
3065 | */ | |
3066 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist); | |
e81cd2d6 LB |
3067 | |
3068 | return (unsigned long)cmd; | |
3069 | } | |
3070 | ||
a43c49a8 LB |
3071 | static int |
3072 | mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw, | |
3073 | unsigned int changed_flags, | |
3074 | unsigned int *total_flags) | |
3075 | { | |
3076 | struct mwl8k_priv *priv = hw->priv; | |
3077 | ||
3078 | /* | |
3079 | * Hardware sniffer mode is mutually exclusive with STA | |
3080 | * operation, so refuse to enable sniffer mode if a STA | |
3081 | * interface is active. | |
3082 | */ | |
3083 | if (priv->vif != NULL) { | |
3084 | if (net_ratelimit()) | |
3085 | printk(KERN_INFO "%s: not enabling sniffer " | |
3086 | "mode because STA interface is active\n", | |
3087 | wiphy_name(hw->wiphy)); | |
3088 | return 0; | |
3089 | } | |
3090 | ||
3091 | if (!priv->sniffer_enabled) { | |
55489b6e | 3092 | if (mwl8k_cmd_enable_sniffer(hw, 1)) |
a43c49a8 LB |
3093 | return 0; |
3094 | priv->sniffer_enabled = true; | |
3095 | } | |
3096 | ||
3097 | *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI | | |
3098 | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | | |
3099 | FIF_OTHER_BSS; | |
3100 | ||
3101 | return 1; | |
3102 | } | |
3103 | ||
e6935ea1 LB |
3104 | static void mwl8k_configure_filter(struct ieee80211_hw *hw, |
3105 | unsigned int changed_flags, | |
3106 | unsigned int *total_flags, | |
3107 | u64 multicast) | |
3108 | { | |
3109 | struct mwl8k_priv *priv = hw->priv; | |
a43c49a8 LB |
3110 | struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast; |
3111 | ||
c0adae2c LB |
3112 | /* |
3113 | * AP firmware doesn't allow fine-grained control over | |
3114 | * the receive filter. | |
3115 | */ | |
3116 | if (priv->ap_fw) { | |
3117 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; | |
3118 | kfree(cmd); | |
3119 | return; | |
3120 | } | |
3121 | ||
a43c49a8 LB |
3122 | /* |
3123 | * Enable hardware sniffer mode if FIF_CONTROL or | |
3124 | * FIF_OTHER_BSS is requested. | |
3125 | */ | |
3126 | if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) && | |
3127 | mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) { | |
3128 | kfree(cmd); | |
3129 | return; | |
3130 | } | |
a66098da | 3131 | |
e6935ea1 | 3132 | /* Clear unsupported feature flags */ |
447ced07 | 3133 | *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC; |
a66098da | 3134 | |
e6935ea1 LB |
3135 | if (mwl8k_fw_lock(hw)) |
3136 | return; | |
a66098da | 3137 | |
a43c49a8 | 3138 | if (priv->sniffer_enabled) { |
55489b6e | 3139 | mwl8k_cmd_enable_sniffer(hw, 0); |
a43c49a8 LB |
3140 | priv->sniffer_enabled = false; |
3141 | } | |
3142 | ||
e6935ea1 | 3143 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
77165d88 LB |
3144 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) { |
3145 | /* | |
3146 | * Disable the BSS filter. | |
3147 | */ | |
e6935ea1 | 3148 | mwl8k_cmd_set_pre_scan(hw); |
77165d88 | 3149 | } else { |
0a11dfc3 | 3150 | const u8 *bssid; |
a94cc97e | 3151 | |
77165d88 LB |
3152 | /* |
3153 | * Enable the BSS filter. | |
3154 | * | |
3155 | * If there is an active STA interface, use that | |
3156 | * interface's BSSID, otherwise use a dummy one | |
3157 | * (where the OUI part needs to be nonzero for | |
3158 | * the BSSID to be accepted by POST_SCAN). | |
3159 | */ | |
3160 | bssid = "\x01\x00\x00\x00\x00\x00"; | |
a94cc97e | 3161 | if (priv->vif != NULL) |
0a11dfc3 | 3162 | bssid = priv->vif->bss_conf.bssid; |
a94cc97e | 3163 | |
e6935ea1 | 3164 | mwl8k_cmd_set_post_scan(hw, bssid); |
a66098da LB |
3165 | } |
3166 | } | |
3167 | ||
447ced07 LB |
3168 | /* |
3169 | * If FIF_ALLMULTI is being requested, throw away the command | |
3170 | * packet that ->prepare_multicast() built and replace it with | |
3171 | * a command packet that enables reception of all multicast | |
3172 | * packets. | |
3173 | */ | |
3174 | if (*total_flags & FIF_ALLMULTI) { | |
3175 | kfree(cmd); | |
3176 | cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL); | |
3177 | } | |
3178 | ||
3179 | if (cmd != NULL) { | |
3180 | mwl8k_post_cmd(hw, cmd); | |
3181 | kfree(cmd); | |
e6935ea1 | 3182 | } |
a66098da | 3183 | |
e6935ea1 | 3184 | mwl8k_fw_unlock(hw); |
a66098da LB |
3185 | } |
3186 | ||
a66098da LB |
3187 | static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value) |
3188 | { | |
55489b6e | 3189 | return mwl8k_cmd_set_rts_threshold(hw, MWL8K_CMD_SET, value); |
a66098da LB |
3190 | } |
3191 | ||
bbfd9128 LB |
3192 | struct mwl8k_sta_notify_item |
3193 | { | |
3194 | struct list_head list; | |
3195 | struct ieee80211_vif *vif; | |
3196 | enum sta_notify_cmd cmd; | |
13935e2c | 3197 | struct ieee80211_sta sta; |
bbfd9128 LB |
3198 | }; |
3199 | ||
3200 | static void mwl8k_sta_notify_worker(struct work_struct *work) | |
3201 | { | |
3202 | struct mwl8k_priv *priv = | |
3203 | container_of(work, struct mwl8k_priv, sta_notify_worker); | |
a680400e | 3204 | struct ieee80211_hw *hw = priv->hw; |
bbfd9128 LB |
3205 | |
3206 | spin_lock_bh(&priv->sta_notify_list_lock); | |
3207 | while (!list_empty(&priv->sta_notify_list)) { | |
3208 | struct mwl8k_sta_notify_item *s; | |
bbfd9128 LB |
3209 | |
3210 | s = list_entry(priv->sta_notify_list.next, | |
3211 | struct mwl8k_sta_notify_item, list); | |
3212 | list_del(&s->list); | |
3213 | ||
3214 | spin_unlock_bh(&priv->sta_notify_list_lock); | |
3215 | ||
a680400e LB |
3216 | if (s->cmd == STA_NOTIFY_ADD) { |
3217 | int rc; | |
3218 | ||
13935e2c | 3219 | rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta); |
a680400e LB |
3220 | if (rc >= 0) { |
3221 | struct ieee80211_sta *sta; | |
3222 | ||
3223 | rcu_read_lock(); | |
13935e2c | 3224 | sta = ieee80211_find_sta(s->vif, s->sta.addr); |
a680400e LB |
3225 | if (sta != NULL) |
3226 | MWL8K_STA(sta)->peer_id = rc; | |
3227 | rcu_read_unlock(); | |
3228 | } | |
3229 | } else { | |
13935e2c | 3230 | mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr); |
a680400e | 3231 | } |
bbfd9128 LB |
3232 | |
3233 | kfree(s); | |
3234 | ||
3235 | spin_lock_bh(&priv->sta_notify_list_lock); | |
3236 | } | |
3237 | spin_unlock_bh(&priv->sta_notify_list_lock); | |
3238 | } | |
3239 | ||
3240 | static void | |
3241 | mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3242 | enum sta_notify_cmd cmd, struct ieee80211_sta *sta) | |
3243 | { | |
3244 | struct mwl8k_priv *priv = hw->priv; | |
3245 | struct mwl8k_sta_notify_item *s; | |
3246 | ||
3247 | if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE) | |
3248 | return; | |
3249 | ||
3250 | s = kmalloc(sizeof(*s), GFP_ATOMIC); | |
3251 | if (s != NULL) { | |
3252 | s->vif = vif; | |
3253 | s->cmd = cmd; | |
13935e2c | 3254 | s->sta = *sta; |
bbfd9128 LB |
3255 | |
3256 | spin_lock(&priv->sta_notify_list_lock); | |
3257 | list_add_tail(&s->list, &priv->sta_notify_list); | |
3258 | spin_unlock(&priv->sta_notify_list_lock); | |
3259 | ||
3260 | ieee80211_queue_work(hw, &priv->sta_notify_worker); | |
3261 | } | |
3262 | } | |
3263 | ||
a66098da LB |
3264 | static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
3265 | const struct ieee80211_tx_queue_params *params) | |
3266 | { | |
3e4f542c | 3267 | struct mwl8k_priv *priv = hw->priv; |
a66098da | 3268 | int rc; |
a66098da | 3269 | |
3e4f542c LB |
3270 | rc = mwl8k_fw_lock(hw); |
3271 | if (!rc) { | |
3272 | if (!priv->wmm_enabled) | |
55489b6e | 3273 | rc = mwl8k_cmd_set_wmm_mode(hw, 1); |
a66098da | 3274 | |
3e4f542c | 3275 | if (!rc) |
55489b6e LB |
3276 | rc = mwl8k_cmd_set_edca_params(hw, queue, |
3277 | params->cw_min, | |
3278 | params->cw_max, | |
3279 | params->aifs, | |
3280 | params->txop); | |
3e4f542c LB |
3281 | |
3282 | mwl8k_fw_unlock(hw); | |
a66098da | 3283 | } |
3e4f542c | 3284 | |
a66098da LB |
3285 | return rc; |
3286 | } | |
3287 | ||
3288 | static int mwl8k_get_tx_stats(struct ieee80211_hw *hw, | |
3289 | struct ieee80211_tx_queue_stats *stats) | |
3290 | { | |
3291 | struct mwl8k_priv *priv = hw->priv; | |
3292 | struct mwl8k_tx_queue *txq; | |
3293 | int index; | |
3294 | ||
3295 | spin_lock_bh(&priv->tx_lock); | |
3296 | for (index = 0; index < MWL8K_TX_QUEUES; index++) { | |
3297 | txq = priv->txq + index; | |
45eb400d | 3298 | memcpy(&stats[index], &txq->stats, |
a66098da LB |
3299 | sizeof(struct ieee80211_tx_queue_stats)); |
3300 | } | |
3301 | spin_unlock_bh(&priv->tx_lock); | |
a66098da | 3302 | |
954ef509 | 3303 | return 0; |
a66098da LB |
3304 | } |
3305 | ||
3306 | static int mwl8k_get_stats(struct ieee80211_hw *hw, | |
3307 | struct ieee80211_low_level_stats *stats) | |
3308 | { | |
55489b6e | 3309 | return mwl8k_cmd_get_stat(hw, stats); |
a66098da LB |
3310 | } |
3311 | ||
a2292d83 LB |
3312 | static int |
3313 | mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
3314 | enum ieee80211_ampdu_mlme_action action, | |
3315 | struct ieee80211_sta *sta, u16 tid, u16 *ssn) | |
3316 | { | |
3317 | switch (action) { | |
3318 | case IEEE80211_AMPDU_RX_START: | |
3319 | case IEEE80211_AMPDU_RX_STOP: | |
3320 | if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION)) | |
3321 | return -ENOTSUPP; | |
3322 | return 0; | |
3323 | default: | |
3324 | return -ENOTSUPP; | |
3325 | } | |
3326 | } | |
3327 | ||
a66098da LB |
3328 | static const struct ieee80211_ops mwl8k_ops = { |
3329 | .tx = mwl8k_tx, | |
3330 | .start = mwl8k_start, | |
3331 | .stop = mwl8k_stop, | |
3332 | .add_interface = mwl8k_add_interface, | |
3333 | .remove_interface = mwl8k_remove_interface, | |
3334 | .config = mwl8k_config, | |
a66098da | 3335 | .bss_info_changed = mwl8k_bss_info_changed, |
3ac64bee | 3336 | .prepare_multicast = mwl8k_prepare_multicast, |
a66098da LB |
3337 | .configure_filter = mwl8k_configure_filter, |
3338 | .set_rts_threshold = mwl8k_set_rts_threshold, | |
bbfd9128 | 3339 | .sta_notify = mwl8k_sta_notify, |
a66098da LB |
3340 | .conf_tx = mwl8k_conf_tx, |
3341 | .get_tx_stats = mwl8k_get_tx_stats, | |
3342 | .get_stats = mwl8k_get_stats, | |
a2292d83 | 3343 | .ampdu_action = mwl8k_ampdu_action, |
a66098da LB |
3344 | }; |
3345 | ||
3346 | static void mwl8k_tx_reclaim_handler(unsigned long data) | |
3347 | { | |
3348 | int i; | |
3349 | struct ieee80211_hw *hw = (struct ieee80211_hw *) data; | |
3350 | struct mwl8k_priv *priv = hw->priv; | |
3351 | ||
3352 | spin_lock_bh(&priv->tx_lock); | |
3353 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3354 | mwl8k_txq_reclaim(hw, i, 0); | |
3355 | ||
88de754a | 3356 | if (priv->tx_wait != NULL && !priv->pending_tx_pkts) { |
ce9e2e1b LB |
3357 | complete(priv->tx_wait); |
3358 | priv->tx_wait = NULL; | |
a66098da LB |
3359 | } |
3360 | spin_unlock_bh(&priv->tx_lock); | |
3361 | } | |
3362 | ||
3363 | static void mwl8k_finalize_join_worker(struct work_struct *work) | |
3364 | { | |
3365 | struct mwl8k_priv *priv = | |
3366 | container_of(work, struct mwl8k_priv, finalize_join_worker); | |
3367 | struct sk_buff *skb = priv->beacon_skb; | |
a66098da | 3368 | |
7dc6a7a7 LB |
3369 | mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, |
3370 | priv->vif->bss_conf.dtim_period); | |
a66098da LB |
3371 | dev_kfree_skb(skb); |
3372 | ||
3373 | priv->beacon_skb = NULL; | |
3374 | } | |
3375 | ||
bcb628d5 | 3376 | enum { |
9e1b17ea LB |
3377 | MWL8363 = 0, |
3378 | MWL8687, | |
bcb628d5 | 3379 | MWL8366, |
6f6d1e9a LB |
3380 | }; |
3381 | ||
bcb628d5 | 3382 | static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = { |
9e1b17ea LB |
3383 | [MWL8363] = { |
3384 | .part_name = "88w8363", | |
3385 | .helper_image = "mwl8k/helper_8363.fw", | |
3386 | .fw_image = "mwl8k/fmimage_8363.fw", | |
3387 | }, | |
49eb691c | 3388 | [MWL8687] = { |
bcb628d5 JL |
3389 | .part_name = "88w8687", |
3390 | .helper_image = "mwl8k/helper_8687.fw", | |
3391 | .fw_image = "mwl8k/fmimage_8687.fw", | |
bcb628d5 | 3392 | }, |
49eb691c | 3393 | [MWL8366] = { |
bcb628d5 JL |
3394 | .part_name = "88w8366", |
3395 | .helper_image = "mwl8k/helper_8366.fw", | |
3396 | .fw_image = "mwl8k/fmimage_8366.fw", | |
89a91f4f | 3397 | .ap_rxd_ops = &rxd_8366_ap_ops, |
bcb628d5 | 3398 | }, |
45a390dd LB |
3399 | }; |
3400 | ||
3401 | static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = { | |
9e1b17ea LB |
3402 | { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, }, |
3403 | { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, }, | |
bcb628d5 JL |
3404 | { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, }, |
3405 | { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, }, | |
3406 | { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, }, | |
3407 | { }, | |
45a390dd LB |
3408 | }; |
3409 | MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table); | |
3410 | ||
a66098da LB |
3411 | static int __devinit mwl8k_probe(struct pci_dev *pdev, |
3412 | const struct pci_device_id *id) | |
3413 | { | |
2aa7b01f | 3414 | static int printed_version = 0; |
a66098da LB |
3415 | struct ieee80211_hw *hw; |
3416 | struct mwl8k_priv *priv; | |
a66098da LB |
3417 | int rc; |
3418 | int i; | |
2aa7b01f LB |
3419 | |
3420 | if (!printed_version) { | |
3421 | printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION); | |
3422 | printed_version = 1; | |
3423 | } | |
a66098da | 3424 | |
be695fc4 | 3425 | |
a66098da LB |
3426 | rc = pci_enable_device(pdev); |
3427 | if (rc) { | |
3428 | printk(KERN_ERR "%s: Cannot enable new PCI device\n", | |
3429 | MWL8K_NAME); | |
3430 | return rc; | |
3431 | } | |
3432 | ||
3433 | rc = pci_request_regions(pdev, MWL8K_NAME); | |
3434 | if (rc) { | |
3435 | printk(KERN_ERR "%s: Cannot obtain PCI resources\n", | |
3436 | MWL8K_NAME); | |
3db95e50 | 3437 | goto err_disable_device; |
a66098da LB |
3438 | } |
3439 | ||
3440 | pci_set_master(pdev); | |
3441 | ||
be695fc4 | 3442 | |
a66098da LB |
3443 | hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops); |
3444 | if (hw == NULL) { | |
3445 | printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME); | |
3446 | rc = -ENOMEM; | |
3447 | goto err_free_reg; | |
3448 | } | |
3449 | ||
be695fc4 LB |
3450 | SET_IEEE80211_DEV(hw, &pdev->dev); |
3451 | pci_set_drvdata(pdev, hw); | |
3452 | ||
a66098da LB |
3453 | priv = hw->priv; |
3454 | priv->hw = hw; | |
3455 | priv->pdev = pdev; | |
bcb628d5 | 3456 | priv->device_info = &mwl8k_info_tbl[id->driver_data]; |
a66098da | 3457 | |
a66098da | 3458 | |
5b9482dd LB |
3459 | priv->sram = pci_iomap(pdev, 0, 0x10000); |
3460 | if (priv->sram == NULL) { | |
3461 | printk(KERN_ERR "%s: Cannot map device SRAM\n", | |
c2c357ce | 3462 | wiphy_name(hw->wiphy)); |
a66098da LB |
3463 | goto err_iounmap; |
3464 | } | |
3465 | ||
5b9482dd LB |
3466 | /* |
3467 | * If BAR0 is a 32 bit BAR, the register BAR will be BAR1. | |
3468 | * If BAR0 is a 64 bit BAR, the register BAR will be BAR2. | |
3469 | */ | |
3470 | priv->regs = pci_iomap(pdev, 1, 0x10000); | |
3471 | if (priv->regs == NULL) { | |
3472 | priv->regs = pci_iomap(pdev, 2, 0x10000); | |
3473 | if (priv->regs == NULL) { | |
3474 | printk(KERN_ERR "%s: Cannot map device registers\n", | |
3475 | wiphy_name(hw->wiphy)); | |
3476 | goto err_iounmap; | |
3477 | } | |
3478 | } | |
3479 | ||
be695fc4 LB |
3480 | |
3481 | /* Reset firmware and hardware */ | |
3482 | mwl8k_hw_reset(priv); | |
3483 | ||
3484 | /* Ask userland hotplug daemon for the device firmware */ | |
3485 | rc = mwl8k_request_firmware(priv); | |
3486 | if (rc) { | |
3487 | printk(KERN_ERR "%s: Firmware files not found\n", | |
3488 | wiphy_name(hw->wiphy)); | |
3489 | goto err_stop_firmware; | |
3490 | } | |
3491 | ||
3492 | /* Load firmware into hardware */ | |
3493 | rc = mwl8k_load_firmware(hw); | |
3494 | if (rc) { | |
3495 | printk(KERN_ERR "%s: Cannot start firmware\n", | |
3496 | wiphy_name(hw->wiphy)); | |
3497 | goto err_stop_firmware; | |
3498 | } | |
3499 | ||
3500 | /* Reclaim memory once firmware is successfully loaded */ | |
3501 | mwl8k_release_firmware(priv); | |
3502 | ||
3503 | ||
91942230 | 3504 | if (priv->ap_fw) { |
89a91f4f | 3505 | priv->rxd_ops = priv->device_info->ap_rxd_ops; |
91942230 LB |
3506 | if (priv->rxd_ops == NULL) { |
3507 | printk(KERN_ERR "%s: Driver does not have AP " | |
3508 | "firmware image support for this hardware\n", | |
3509 | wiphy_name(hw->wiphy)); | |
3510 | goto err_stop_firmware; | |
3511 | } | |
3512 | } else { | |
89a91f4f | 3513 | priv->rxd_ops = &rxd_sta_ops; |
91942230 | 3514 | } |
be695fc4 LB |
3515 | |
3516 | priv->sniffer_enabled = false; | |
3517 | priv->wmm_enabled = false; | |
3518 | priv->pending_tx_pkts = 0; | |
3519 | ||
3520 | ||
a66098da LB |
3521 | memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels)); |
3522 | priv->band.band = IEEE80211_BAND_2GHZ; | |
3523 | priv->band.channels = priv->channels; | |
3524 | priv->band.n_channels = ARRAY_SIZE(mwl8k_channels); | |
3525 | priv->band.bitrates = priv->rates; | |
3526 | priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates); | |
3527 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band; | |
3528 | ||
3529 | BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates)); | |
3530 | memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates)); | |
3531 | ||
3532 | /* | |
3533 | * Extra headroom is the size of the required DMA header | |
3534 | * minus the size of the smallest 802.11 frame (CTS frame). | |
3535 | */ | |
3536 | hw->extra_tx_headroom = | |
3537 | sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts); | |
3538 | ||
3539 | hw->channel_change_time = 10; | |
3540 | ||
3541 | hw->queues = MWL8K_TX_QUEUES; | |
3542 | ||
a66098da | 3543 | /* Set rssi and noise values to dBm */ |
ce9e2e1b | 3544 | hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM; |
a66098da | 3545 | hw->vif_data_size = sizeof(struct mwl8k_vif); |
a680400e | 3546 | hw->sta_data_size = sizeof(struct mwl8k_sta); |
a66098da LB |
3547 | priv->vif = NULL; |
3548 | ||
3549 | /* Set default radio state and preamble */ | |
c46563b7 | 3550 | priv->radio_on = 0; |
68ce3884 | 3551 | priv->radio_short_preamble = 0; |
a66098da | 3552 | |
bbfd9128 LB |
3553 | /* Station database handling */ |
3554 | INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker); | |
3555 | spin_lock_init(&priv->sta_notify_list_lock); | |
3556 | INIT_LIST_HEAD(&priv->sta_notify_list); | |
3557 | ||
a66098da LB |
3558 | /* Finalize join worker */ |
3559 | INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker); | |
3560 | ||
3561 | /* TX reclaim tasklet */ | |
3562 | tasklet_init(&priv->tx_reclaim_task, | |
3563 | mwl8k_tx_reclaim_handler, (unsigned long)hw); | |
3564 | tasklet_disable(&priv->tx_reclaim_task); | |
3565 | ||
a66098da LB |
3566 | /* Power management cookie */ |
3567 | priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma); | |
3568 | if (priv->cookie == NULL) | |
be695fc4 | 3569 | goto err_stop_firmware; |
a66098da LB |
3570 | |
3571 | rc = mwl8k_rxq_init(hw, 0); | |
3572 | if (rc) | |
be695fc4 | 3573 | goto err_free_cookie; |
a66098da LB |
3574 | rxq_refill(hw, 0, INT_MAX); |
3575 | ||
618952a7 LB |
3576 | mutex_init(&priv->fw_mutex); |
3577 | priv->fw_mutex_owner = NULL; | |
3578 | priv->fw_mutex_depth = 0; | |
618952a7 LB |
3579 | priv->hostcmd_wait = NULL; |
3580 | ||
a66098da LB |
3581 | spin_lock_init(&priv->tx_lock); |
3582 | ||
88de754a LB |
3583 | priv->tx_wait = NULL; |
3584 | ||
a66098da LB |
3585 | for (i = 0; i < MWL8K_TX_QUEUES; i++) { |
3586 | rc = mwl8k_txq_init(hw, i); | |
3587 | if (rc) | |
3588 | goto err_free_queues; | |
3589 | } | |
3590 | ||
3591 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS); | |
c23b5a69 | 3592 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3593 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL); |
3594 | iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK); | |
3595 | ||
a0607fd3 | 3596 | rc = request_irq(priv->pdev->irq, mwl8k_interrupt, |
a66098da LB |
3597 | IRQF_SHARED, MWL8K_NAME, hw); |
3598 | if (rc) { | |
3599 | printk(KERN_ERR "%s: failed to register IRQ handler\n", | |
c2c357ce | 3600 | wiphy_name(hw->wiphy)); |
a66098da LB |
3601 | goto err_free_queues; |
3602 | } | |
3603 | ||
a66098da LB |
3604 | /* |
3605 | * Temporarily enable interrupts. Initial firmware host | |
3606 | * commands use interrupts and avoids polling. Disable | |
3607 | * interrupts when done. | |
3608 | */ | |
c23b5a69 | 3609 | iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3610 | |
3611 | /* Get config data, mac addrs etc */ | |
42fba21d LB |
3612 | if (priv->ap_fw) { |
3613 | rc = mwl8k_cmd_get_hw_spec_ap(hw); | |
3614 | if (!rc) | |
3615 | rc = mwl8k_cmd_set_hw_spec(hw); | |
3616 | } else { | |
3617 | rc = mwl8k_cmd_get_hw_spec_sta(hw); | |
89a91f4f LB |
3618 | |
3619 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
42fba21d | 3620 | } |
a66098da | 3621 | if (rc) { |
c2c357ce LB |
3622 | printk(KERN_ERR "%s: Cannot initialise firmware\n", |
3623 | wiphy_name(hw->wiphy)); | |
be695fc4 | 3624 | goto err_free_irq; |
a66098da LB |
3625 | } |
3626 | ||
3627 | /* Turn radio off */ | |
55489b6e | 3628 | rc = mwl8k_cmd_radio_disable(hw); |
a66098da | 3629 | if (rc) { |
c2c357ce | 3630 | printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy)); |
be695fc4 | 3631 | goto err_free_irq; |
a66098da LB |
3632 | } |
3633 | ||
32060e1b | 3634 | /* Clear MAC address */ |
55489b6e | 3635 | rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00"); |
32060e1b LB |
3636 | if (rc) { |
3637 | printk(KERN_ERR "%s: Cannot clear MAC address\n", | |
3638 | wiphy_name(hw->wiphy)); | |
be695fc4 | 3639 | goto err_free_irq; |
32060e1b LB |
3640 | } |
3641 | ||
a66098da | 3642 | /* Disable interrupts */ |
a66098da | 3643 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3644 | free_irq(priv->pdev->irq, hw); |
3645 | ||
3646 | rc = ieee80211_register_hw(hw); | |
3647 | if (rc) { | |
c2c357ce LB |
3648 | printk(KERN_ERR "%s: Cannot register device\n", |
3649 | wiphy_name(hw->wiphy)); | |
153458ff | 3650 | goto err_free_queues; |
a66098da LB |
3651 | } |
3652 | ||
eae74e65 | 3653 | printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n", |
a74b295e | 3654 | wiphy_name(hw->wiphy), priv->device_info->part_name, |
45a390dd | 3655 | priv->hw_rev, hw->wiphy->perm_addr, |
eae74e65 | 3656 | priv->ap_fw ? "AP" : "STA", |
2aa7b01f LB |
3657 | (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff, |
3658 | (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff); | |
a66098da LB |
3659 | |
3660 | return 0; | |
3661 | ||
a66098da | 3662 | err_free_irq: |
a66098da | 3663 | iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK); |
a66098da LB |
3664 | free_irq(priv->pdev->irq, hw); |
3665 | ||
3666 | err_free_queues: | |
3667 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3668 | mwl8k_txq_deinit(hw, i); | |
3669 | mwl8k_rxq_deinit(hw, 0); | |
3670 | ||
be695fc4 | 3671 | err_free_cookie: |
a66098da LB |
3672 | if (priv->cookie != NULL) |
3673 | pci_free_consistent(priv->pdev, 4, | |
3674 | priv->cookie, priv->cookie_dma); | |
3675 | ||
be695fc4 LB |
3676 | err_stop_firmware: |
3677 | mwl8k_hw_reset(priv); | |
3678 | mwl8k_release_firmware(priv); | |
3679 | ||
3680 | err_iounmap: | |
a66098da LB |
3681 | if (priv->regs != NULL) |
3682 | pci_iounmap(pdev, priv->regs); | |
3683 | ||
5b9482dd LB |
3684 | if (priv->sram != NULL) |
3685 | pci_iounmap(pdev, priv->sram); | |
3686 | ||
a66098da LB |
3687 | pci_set_drvdata(pdev, NULL); |
3688 | ieee80211_free_hw(hw); | |
3689 | ||
3690 | err_free_reg: | |
3691 | pci_release_regions(pdev); | |
3db95e50 LB |
3692 | |
3693 | err_disable_device: | |
a66098da LB |
3694 | pci_disable_device(pdev); |
3695 | ||
3696 | return rc; | |
3697 | } | |
3698 | ||
230f7af0 | 3699 | static void __devexit mwl8k_shutdown(struct pci_dev *pdev) |
a66098da LB |
3700 | { |
3701 | printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__); | |
3702 | } | |
3703 | ||
230f7af0 | 3704 | static void __devexit mwl8k_remove(struct pci_dev *pdev) |
a66098da LB |
3705 | { |
3706 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
3707 | struct mwl8k_priv *priv; | |
3708 | int i; | |
3709 | ||
3710 | if (hw == NULL) | |
3711 | return; | |
3712 | priv = hw->priv; | |
3713 | ||
3714 | ieee80211_stop_queues(hw); | |
3715 | ||
60aa569f LB |
3716 | ieee80211_unregister_hw(hw); |
3717 | ||
a66098da LB |
3718 | /* Remove tx reclaim tasklet */ |
3719 | tasklet_kill(&priv->tx_reclaim_task); | |
3720 | ||
a66098da LB |
3721 | /* Stop hardware */ |
3722 | mwl8k_hw_reset(priv); | |
3723 | ||
3724 | /* Return all skbs to mac80211 */ | |
3725 | for (i = 0; i < MWL8K_TX_QUEUES; i++) | |
3726 | mwl8k_txq_reclaim(hw, i, 1); | |
3727 | ||
a66098da LB |
3728 | for (i = 0; i < MWL8K_TX_QUEUES; i++) |
3729 | mwl8k_txq_deinit(hw, i); | |
3730 | ||
3731 | mwl8k_rxq_deinit(hw, 0); | |
3732 | ||
c2c357ce | 3733 | pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma); |
a66098da LB |
3734 | |
3735 | pci_iounmap(pdev, priv->regs); | |
5b9482dd | 3736 | pci_iounmap(pdev, priv->sram); |
a66098da LB |
3737 | pci_set_drvdata(pdev, NULL); |
3738 | ieee80211_free_hw(hw); | |
3739 | pci_release_regions(pdev); | |
3740 | pci_disable_device(pdev); | |
3741 | } | |
3742 | ||
3743 | static struct pci_driver mwl8k_driver = { | |
3744 | .name = MWL8K_NAME, | |
45a390dd | 3745 | .id_table = mwl8k_pci_id_table, |
a66098da LB |
3746 | .probe = mwl8k_probe, |
3747 | .remove = __devexit_p(mwl8k_remove), | |
3748 | .shutdown = __devexit_p(mwl8k_shutdown), | |
3749 | }; | |
3750 | ||
3751 | static int __init mwl8k_init(void) | |
3752 | { | |
3753 | return pci_register_driver(&mwl8k_driver); | |
3754 | } | |
3755 | ||
3756 | static void __exit mwl8k_exit(void) | |
3757 | { | |
3758 | pci_unregister_driver(&mwl8k_driver); | |
3759 | } | |
3760 | ||
3761 | module_init(mwl8k_init); | |
3762 | module_exit(mwl8k_exit); | |
c2c357ce LB |
3763 | |
3764 | MODULE_DESCRIPTION(MWL8K_DESC); | |
3765 | MODULE_VERSION(MWL8K_VERSION); | |
3766 | MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>"); | |
3767 | MODULE_LICENSE("GPL"); |