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libertas: EHS_REMOVE_WAKEUP is not always supported
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a5fb297d 5 * Copyright (C) 2008, 2009, 2010 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
5a0e3ad6 22#include <linux/slab.h>
a66098da
LB		 23#include <net/mac80211.h>
24#include <linux/moduleparam.h>
25#include <linux/firmware.h>
26#include <linux/workqueue.h>
27
28#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
29#define MWL8K_NAME KBUILD_MODNAME
a5fb297d 30#define MWL8K_VERSION "0.12"
a66098da 31
a66098da
LB		 32/* Register definitions */
33#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 34#define MWL8K_MODE_STA 0x0000005a
35#define MWL8K_MODE_AP 0x000000a5
a66098da 36#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 37#define MWL8K_FWSTA_READY 0xf0f1f2f4
38#define MWL8K_FWAP_READY 0xf1f2f4a5
39#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 40#define MWL8K_HIU_SCRATCH 0x00000c40
41
42/* Host->device communications */
43#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
44#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
45#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
46#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
47#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 48#define MWL8K_H2A_INT_DUMMY (1 << 20)
49#define MWL8K_H2A_INT_RESET (1 << 15)
50#define MWL8K_H2A_INT_DOORBELL (1 << 1)
51#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 52
53/* Device->host communications */
54#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
55#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
56#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
57#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
58#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 59#define MWL8K_A2H_INT_DUMMY (1 << 20)
60#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
61#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
62#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
63#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
64#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
65#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
66#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
67#define MWL8K_A2H_INT_RX_READY (1 << 1)
68#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 69
70#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
71 MWL8K_A2H_INT_CHNL_SWITCHED | \
72 MWL8K_A2H_INT_QUEUE_EMPTY | \
73 MWL8K_A2H_INT_RADAR_DETECT | \
74 MWL8K_A2H_INT_RADIO_ON | \
75 MWL8K_A2H_INT_RADIO_OFF | \
76 MWL8K_A2H_INT_MAC_EVENT | \
77 MWL8K_A2H_INT_OPC_DONE | \
78 MWL8K_A2H_INT_RX_READY | \
79 MWL8K_A2H_INT_TX_DONE)
80
a66098da
LB		 81#define MWL8K_RX_QUEUES 1
82#define MWL8K_TX_QUEUES 4
83
54bc3a0d
LB		 84struct rxd_ops {
85 int rxd_size;
86 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
87 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d 88 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
0d462bbb 89 __le16 *qos, s8 *noise);
54bc3a0d
LB		 90};
91
45a390dd 92struct mwl8k_device_info {
a74b295e
LB		 93 char *part_name;
94 char *helper_image;
95 char *fw_image;
89a91f4f 96 struct rxd_ops *ap_rxd_ops;
45a390dd
LB		 97};
98
a66098da 99struct mwl8k_rx_queue {
45eb400d 100 int rxd_count;
a66098da
LB		 101
102 /* hw receives here */
45eb400d 103 int head;
a66098da
LB		 104
105 /* refill descs here */
45eb400d 106 int tail;
a66098da 107
54bc3a0d 108 void *rxd;
45eb400d 109 dma_addr_t rxd_dma;
788838eb
LB		 110 struct {
111 struct sk_buff *skb;
53b1b3e1 112 DEFINE_DMA_UNMAP_ADDR(dma);
788838eb 113 } *buf;
a66098da
LB		 114};
115
a66098da
LB		 116struct mwl8k_tx_queue {
117 /* hw transmits here */
45eb400d 118 int head;
a66098da
LB		 119
120 /* sw appends here */
45eb400d 121 int tail;
a66098da 122
8ccbc3b8 123 unsigned int len;
45eb400d
LB		 124 struct mwl8k_tx_desc *txd;
125 dma_addr_t txd_dma;
126 struct sk_buff **skb;
a66098da
LB		 127};
128
a66098da 129struct mwl8k_priv {
a66098da 130 struct ieee80211_hw *hw;
a66098da 131 struct pci_dev *pdev;
a66098da 132
45a390dd
LB		 133 struct mwl8k_device_info *device_info;
134
be695fc4
LB		 135 void __iomem *sram;
136 void __iomem *regs;
137
138 /* firmware */
22be40d9
LB		 139 struct firmware *fw_helper;
140 struct firmware *fw_ucode;
a66098da 141
be695fc4
LB		 142 /* hardware/firmware parameters */
143 bool ap_fw;
144 struct rxd_ops *rxd_ops;
777ad375
LB		 145 struct ieee80211_supported_band band_24;
146 struct ieee80211_channel channels_24[14];
147 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 148 struct ieee80211_supported_band band_50;
149 struct ieee80211_channel channels_50[4];
150 struct ieee80211_rate rates_50[9];
ee0ddf18
LB		 151 u32 ap_macids_supported;
152 u32 sta_macids_supported;
be695fc4 153
618952a7
LB		 154 /* firmware access */
155 struct mutex fw_mutex;
156 struct task_struct *fw_mutex_owner;
157 int fw_mutex_depth;
618952a7
LB		 158 struct completion *hostcmd_wait;
159
a66098da
LB		 160 /* lock held over TX and TX reap */
161 spinlock_t tx_lock;
a66098da 162
88de754a
LB		 163 /* TX quiesce completion, protected by fw_mutex and tx_lock */
164 struct completion *tx_wait;
165
f5bb87cf 166 /* List of interfaces. */
ee0ddf18 167 u32 macids_used;
f5bb87cf 168 struct list_head vif_list;
a66098da 169
a66098da
LB		 170 /* power management status cookie from firmware */
171 u32 *cookie;
172 dma_addr_t cookie_dma;
173
174 u16 num_mcaddrs;
a66098da 175 u8 hw_rev;
2aa7b01f 176 u32 fw_rev;
a66098da
LB		 177
178 /*
179 * Running count of TX packets in flight, to avoid
180 * iterating over the transmit rings each time.
181 */
182 int pending_tx_pkts;
183
184 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
185 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
186
c46563b7 187 bool radio_on;
68ce3884 188 bool radio_short_preamble;
a43c49a8 189 bool sniffer_enabled;
0439b1f5 190 bool wmm_enabled;
a66098da 191
a66098da
LB		 192 /* XXX need to convert this to handle multiple interfaces */
193 bool capture_beacon;
d89173f2 194 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 195 struct sk_buff *beacon_skb;
196
197 /*
198 * This FJ worker has to be global as it is scheduled from the
199 * RX handler. At this point we don't know which interface it
200 * belongs to until the list of bssids waiting to complete join
201 * is checked.
202 */
203 struct work_struct finalize_join_worker;
204
1e9f9de3
LB		 205 /* Tasklet to perform TX reclaim. */
206 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 207
208 /* Tasklet to perform RX. */
209 struct tasklet_struct poll_rx_task;
0d462bbb
JL		 210
211 /* Most recently reported noise in dBm */
212 s8 noise;
a66098da
LB		 213};
214
215/* Per interface specific private data */
216struct mwl8k_vif {
f5bb87cf
LB		 217 struct list_head list;
218 struct ieee80211_vif *vif;
219
f57ca9c1
LB		 220 /* Firmware macid for this vif. */
221 int macid;
222
c2c2b12a 223 /* Non AMPDU sequence number assigned by driver. */
a680400e 224 u16 seqno;
a66098da 225};
a94cc97e 226#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 227
a680400e
LB		 228struct mwl8k_sta {
229 /* Index into station database. Returned by UPDATE_STADB. */
230 u8 peer_id;
231};
232#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
233
777ad375 234static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB		 235 { .center_freq = 2412, .hw_value = 1, },
236 { .center_freq = 2417, .hw_value = 2, },
237 { .center_freq = 2422, .hw_value = 3, },
238 { .center_freq = 2427, .hw_value = 4, },
239 { .center_freq = 2432, .hw_value = 5, },
240 { .center_freq = 2437, .hw_value = 6, },
241 { .center_freq = 2442, .hw_value = 7, },
242 { .center_freq = 2447, .hw_value = 8, },
243 { .center_freq = 2452, .hw_value = 9, },
244 { .center_freq = 2457, .hw_value = 10, },
245 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 246 { .center_freq = 2467, .hw_value = 12, },
247 { .center_freq = 2472, .hw_value = 13, },
248 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 249};
250
777ad375 251static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 252 { .bitrate = 10, .hw_value = 2, },
253 { .bitrate = 20, .hw_value = 4, },
254 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 255 { .bitrate = 110, .hw_value = 22, },
256 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 257 { .bitrate = 60, .hw_value = 12, },
258 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 259 { .bitrate = 120, .hw_value = 24, },
260 { .bitrate = 180, .hw_value = 36, },
261 { .bitrate = 240, .hw_value = 48, },
262 { .bitrate = 360, .hw_value = 72, },
263 { .bitrate = 480, .hw_value = 96, },
264 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 265 { .bitrate = 720, .hw_value = 144, },
266};
267
4eae9edd
LB		 268static const struct ieee80211_channel mwl8k_channels_50[] = {
269 { .center_freq = 5180, .hw_value = 36, },
270 { .center_freq = 5200, .hw_value = 40, },
271 { .center_freq = 5220, .hw_value = 44, },
272 { .center_freq = 5240, .hw_value = 48, },
273};
274
275static const struct ieee80211_rate mwl8k_rates_50[] = {
276 { .bitrate = 60, .hw_value = 12, },
277 { .bitrate = 90, .hw_value = 18, },
278 { .bitrate = 120, .hw_value = 24, },
279 { .bitrate = 180, .hw_value = 36, },
280 { .bitrate = 240, .hw_value = 48, },
281 { .bitrate = 360, .hw_value = 72, },
282 { .bitrate = 480, .hw_value = 96, },
283 { .bitrate = 540, .hw_value = 108, },
284 { .bitrate = 720, .hw_value = 144, },
285};
286
a66098da
LB		 287/* Set or get info from Firmware */
288#define MWL8K_CMD_SET 0x0001
289#define MWL8K_CMD_GET 0x0000
290
291/* Firmware command codes */
292#define MWL8K_CMD_CODE_DNLD 0x0001
293#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 294#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 295#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
296#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 297#define MWL8K_CMD_RADIO_CONTROL 0x001c
298#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 299#define MWL8K_CMD_RF_ANTENNA 0x0020
aa21d0f6 300#define MWL8K_CMD_SET_BEACON 0x0100 /* per-vif */
a66098da
LB		 301#define MWL8K_CMD_SET_PRE_SCAN 0x0107
302#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 303#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
304#define MWL8K_CMD_SET_AID 0x010d
305#define MWL8K_CMD_SET_RATE 0x0110
306#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
307#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 308#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 309#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
310#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 311#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 312#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 313#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
aa21d0f6 314#define MWL8K_CMD_SET_MAC_ADDR 0x0202 /* per-vif */
a66098da 315#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
aa21d0f6
LB		 316#define MWL8K_CMD_BSS_START 0x1100 /* per-vif */
317#define MWL8K_CMD_SET_NEW_STN 0x1111 /* per-vif */
ff45fc60 318#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da 319
b603742f 320static const char *mwl8k_cmd_name(__le16 cmd, char *buf, int bufsize)
a66098da 321{
b603742f
JL		 322 u16 command = le16_to_cpu(cmd);
323
a66098da
LB		 324#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
325 snprintf(buf, bufsize, "%s", #x);\
326 return buf;\
327 } while (0)
b603742f 328 switch (command & ~0x8000) {
a66098da
LB		 329 MWL8K_CMDNAME(CODE_DNLD);
330 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 331 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 332 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
333 MWL8K_CMDNAME(GET_STAT);
334 MWL8K_CMDNAME(RADIO_CONTROL);
335 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 336 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 337 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 338 MWL8K_CMDNAME(SET_PRE_SCAN);
339 MWL8K_CMDNAME(SET_POST_SCAN);
340 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 341 MWL8K_CMDNAME(SET_AID);
342 MWL8K_CMDNAME(SET_RATE);
343 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
344 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 345 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 346 MWL8K_CMDNAME(SET_EDCA_PARAMS);
347 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 348 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 349 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 350 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 351 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 352 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 353 MWL8K_CMDNAME(BSS_START);
3f5610ff 354 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 355 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 356 default:
357 snprintf(buf, bufsize, "0x%x", cmd);
358 }
359#undef MWL8K_CMDNAME
360
361 return buf;
362}
363
364/* Hardware and firmware reset */
365static void mwl8k_hw_reset(struct mwl8k_priv *priv)
366{
367 iowrite32(MWL8K_H2A_INT_RESET,
368 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
369 iowrite32(MWL8K_H2A_INT_RESET,
370 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
371 msleep(20);
372}
373
374/* Release fw image */
375static void mwl8k_release_fw(struct firmware **fw)
376{
377 if (*fw == NULL)
378 return;
379 release_firmware(*fw);
380 *fw = NULL;
381}
382
383static void mwl8k_release_firmware(struct mwl8k_priv *priv)
384{
22be40d9
LB		 385 mwl8k_release_fw(&priv->fw_ucode);
386 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 387}
388
389/* Request fw image */
390static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 391 const char *fname, struct firmware **fw)
a66098da
LB		 392{
393 /* release current image */
394 if (*fw != NULL)
395 mwl8k_release_fw(fw);
396
397 return request_firmware((const struct firmware **)fw,
c2c357ce 398 fname, &priv->pdev->dev);
a66098da
LB		 399}
400
45a390dd 401static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 402{
a74b295e 403 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 404 int rc;
405
a74b295e 406 if (di->helper_image != NULL) {
22be40d9 407 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
a74b295e
LB		 408 if (rc) {
409 printk(KERN_ERR "%s: Error requesting helper "
410 "firmware file %s\n", pci_name(priv->pdev),
411 di->helper_image);
412 return rc;
413 }
a66098da
LB		 414 }
415
22be40d9 416 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 417 if (rc) {
c2c357ce 418 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 419 pci_name(priv->pdev), di->fw_image);
22be40d9 420 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 421 return rc;
422 }
423
424 return 0;
425}
426
427struct mwl8k_cmd_pkt {
428 __le16 code;
429 __le16 length;
f57ca9c1
LB		 430 __u8 seq_num;
431 __u8 macid;
a66098da
LB		 432 __le16 result;
433 char payload[0];
ba2d3587 434} __packed;
a66098da
LB		 435
436/*
437 * Firmware loading.
438 */
439static int
440mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
441{
442 void __iomem *regs = priv->regs;
443 dma_addr_t dma_addr;
a66098da
LB		 444 int loops;
445
446 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
447 if (pci_dma_mapping_error(priv->pdev, dma_addr))
448 return -ENOMEM;
449
450 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
451 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
452 iowrite32(MWL8K_H2A_INT_DOORBELL,
453 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
454 iowrite32(MWL8K_H2A_INT_DUMMY,
455 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
456
a66098da
LB		 457 loops = 1000;
458 do {
459 u32 int_code;
460
461 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
462 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
463 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 464 break;
465 }
466
3d76e82c 467 cond_resched();
a66098da
LB		 468 udelay(1);
469 } while (--loops);
470
471 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
472
d4b70570 473 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 474}
475
476static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
477 const u8 *data, size_t length)
478{
479 struct mwl8k_cmd_pkt *cmd;
480 int done;
481 int rc = 0;
482
483 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
484 if (cmd == NULL)
485 return -ENOMEM;
486
487 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
488 cmd->seq_num = 0;
f57ca9c1 489 cmd->macid = 0;
a66098da
LB		 490 cmd->result = 0;
491
492 done = 0;
493 while (length) {
494 int block_size = length > 256 ? 256 : length;
495
496 memcpy(cmd->payload, data + done, block_size);
497 cmd->length = cpu_to_le16(block_size);
498
499 rc = mwl8k_send_fw_load_cmd(priv, cmd,
500 sizeof(*cmd) + block_size);
501 if (rc)
502 break;
503
504 done += block_size;
505 length -= block_size;
506 }
507
508 if (!rc) {
509 cmd->length = 0;
510 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
511 }
512
513 kfree(cmd);
514
515 return rc;
516}
517
518static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
519 const u8 *data, size_t length)
520{
521 unsigned char *buffer;
522 int may_continue, rc = 0;
523 u32 done, prev_block_size;
524
525 buffer = kmalloc(1024, GFP_KERNEL);
526 if (buffer == NULL)
527 return -ENOMEM;
528
529 done = 0;
530 prev_block_size = 0;
531 may_continue = 1000;
532 while (may_continue > 0) {
533 u32 block_size;
534
535 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
536 if (block_size & 1) {
537 block_size &= ~1;
538 may_continue--;
539 } else {
540 done += prev_block_size;
541 length -= prev_block_size;
542 }
543
544 if (block_size > 1024 || block_size > length) {
545 rc = -EOVERFLOW;
546 break;
547 }
548
549 if (length == 0) {
550 rc = 0;
551 break;
552 }
553
554 if (block_size == 0) {
555 rc = -EPROTO;
556 may_continue--;
557 udelay(1);
558 continue;
559 }
560
561 prev_block_size = block_size;
562 memcpy(buffer, data + done, block_size);
563
564 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
565 if (rc)
566 break;
567 }
568
569 if (!rc && length != 0)
570 rc = -EREMOTEIO;
571
572 kfree(buffer);
573
574 return rc;
575}
576
c2c357ce 577static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 578{
c2c357ce 579 struct mwl8k_priv *priv = hw->priv;
22be40d9 580 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 581 int rc;
582 int loops;
583
584 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 585 struct firmware *helper = priv->fw_helper;
a66098da 586
c2c357ce
LB		 587 if (helper == NULL) {
588 printk(KERN_ERR "%s: helper image needed but none "
589 "given\n", pci_name(priv->pdev));
590 return -EINVAL;
591 }
a66098da 592
c2c357ce 593 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 594 if (rc) {
595 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 596 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 597 return rc;
598 }
89b872e2 599 msleep(5);
a66098da 600
c2c357ce 601 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 602 } else {
c2c357ce 603 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 604 }
605
606 if (rc) {
c2c357ce
LB		 607 printk(KERN_ERR "%s: unable to load firmware image\n",
608 pci_name(priv->pdev));
a66098da
LB		 609 return rc;
610 }
611
89a91f4f 612 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 613
89b872e2 614 loops = 500000;
a66098da 615 do {
eae74e65
LB		 616 u32 ready_code;
617
618 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
619 if (ready_code == MWL8K_FWAP_READY) {
620 priv->ap_fw = 1;
621 break;
622 } else if (ready_code == MWL8K_FWSTA_READY) {
623 priv->ap_fw = 0;
a66098da 624 break;
eae74e65
LB		 625 }
626
627 cond_resched();
a66098da
LB		 628 udelay(1);
629 } while (--loops);
630
631 return loops ? 0 : -ETIMEDOUT;
632}
633
634
a66098da
LB		 635/* DMA header used by firmware and hardware. */
636struct mwl8k_dma_data {
637 __le16 fwlen;
638 struct ieee80211_hdr wh;
20f09c3d 639 char data[0];
ba2d3587 640} __packed;
a66098da
LB		 641
642/* Routines to add/remove DMA header from skb. */
20f09c3d 643static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 644{
20f09c3d
LB		 645 struct mwl8k_dma_data *tr;
646 int hdrlen;
647
648 tr = (struct mwl8k_dma_data *)skb->data;
649 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
650
651 if (hdrlen != sizeof(tr->wh)) {
652 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
653 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
654 *((__le16 *)(tr->data - 2)) = qos;
655 } else {
656 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
657 }
a66098da 658 }
20f09c3d
LB		 659
660 if (hdrlen != sizeof(*tr))
661 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 662}
663
76266b2a 664static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 665{
666 struct ieee80211_hdr *wh;
ca009301 667 int hdrlen;
a66098da
LB		 668 struct mwl8k_dma_data *tr;
669
ca009301
LB		 670 /*
671 * Add a firmware DMA header; the firmware requires that we
672 * present a 2-byte payload length followed by a 4-address
673 * header (without QoS field), followed (optionally) by any
674 * WEP/ExtIV header (but only filled in for CCMP).
675 */
a66098da 676 wh = (struct ieee80211_hdr *)skb->data;
ca009301 677
a66098da 678 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 679 if (hdrlen != sizeof(*tr))
680 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 681
ca009301
LB		 682 if (ieee80211_is_data_qos(wh->frame_control))
683 hdrlen -= 2;
a66098da
LB		 684
685 tr = (struct mwl8k_dma_data *)skb->data;
686 if (wh != &tr->wh)
687 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 688 if (hdrlen != sizeof(tr->wh))
689 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 690
691 /*
692 * Firmware length is the length of the fully formed "802.11
693 * payload". That is, everything except for the 802.11 header.
694 * This includes all crypto material including the MIC.
695 */
ca009301 696 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 697}
698
699
700/*
89a91f4f 701 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 702 */
89a91f4f 703struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 704 __le16 pkt_len;
705 __u8 sq2;
706 __u8 rate;
707 __le32 pkt_phys_addr;
708 __le32 next_rxd_phys_addr;
709 __le16 qos_control;
710 __le16 htsig2;
711 __le32 hw_rssi_info;
712 __le32 hw_noise_floor_info;
713 __u8 noise_floor;
714 __u8 pad0[3];
715 __u8 rssi;
716 __u8 rx_status;
717 __u8 channel;
718 __u8 rx_ctrl;
ba2d3587 719} __packed;
6f6d1e9a 720
89a91f4f
LB		 721#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
722#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
723#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 724
89a91f4f 725#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 726
89a91f4f 727static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 728{
89a91f4f 729 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 730
731 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 732 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 733}
734
89a91f4f 735static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 736{
89a91f4f 737 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 738
739 rxd->pkt_len = cpu_to_le16(len);
740 rxd->pkt_phys_addr = cpu_to_le32(addr);
741 wmb();
742 rxd->rx_ctrl = 0;
743}
744
745static int
89a91f4f 746mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 747 __le16 *qos, s8 *noise)
6f6d1e9a 748{
89a91f4f 749 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 750
89a91f4f 751 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 752 return -1;
753 rmb();
754
755 memset(status, 0, sizeof(*status));
756
757 status->signal = -rxd->rssi;
0d462bbb 758 *noise = -rxd->noise_floor;
6f6d1e9a 759
89a91f4f 760 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 761 status->flag |= RX_FLAG_HT;
89a91f4f 762 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 763 status->flag |= RX_FLAG_40MHZ;
89a91f4f 764 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 765 } else {
766 int i;
767
777ad375
LB		 768 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
769 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 770 status->rate_idx = i;
771 break;
772 }
773 }
774 }
775
85478344
LB		 776 if (rxd->channel > 14) {
777 status->band = IEEE80211_BAND_5GHZ;
778 if (!(status->flag & RX_FLAG_HT))
779 status->rate_idx -= 5;
780 } else {
781 status->band = IEEE80211_BAND_2GHZ;
782 }
6f6d1e9a
LB		 783 status->freq = ieee80211_channel_to_frequency(rxd->channel);
784
20f09c3d
LB		 785 *qos = rxd->qos_control;
786
6f6d1e9a
LB		 787 return le16_to_cpu(rxd->pkt_len);
788}
789
89a91f4f
LB		 790static struct rxd_ops rxd_8366_ap_ops = {
791 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
792 .rxd_init = mwl8k_rxd_8366_ap_init,
793 .rxd_refill = mwl8k_rxd_8366_ap_refill,
794 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 795};
796
797/*
89a91f4f 798 * Packet reception for STA firmware.
a66098da 799 */
89a91f4f 800struct mwl8k_rxd_sta {
a66098da
LB		 801 __le16 pkt_len;
802 __u8 link_quality;
803 __u8 noise_level;
804 __le32 pkt_phys_addr;
45eb400d 805 __le32 next_rxd_phys_addr;
a66098da
LB		 806 __le16 qos_control;
807 __le16 rate_info;
808 __le32 pad0[4];
809 __u8 rssi;
810 __u8 channel;
811 __le16 pad1;
812 __u8 rx_ctrl;
813 __u8 rx_status;
814 __u8 pad2[2];
ba2d3587 815} __packed;
a66098da 816
89a91f4f
LB		 817#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
818#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
819#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
820#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
821#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
822#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 823
89a91f4f 824#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 825
89a91f4f 826static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 827{
89a91f4f 828 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 829
830 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 831 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 832}
833
89a91f4f 834static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 835{
89a91f4f 836 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 837
838 rxd->pkt_len = cpu_to_le16(len);
839 rxd->pkt_phys_addr = cpu_to_le32(addr);
840 wmb();
841 rxd->rx_ctrl = 0;
842}
843
844static int
89a91f4f 845mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
0d462bbb 846 __le16 *qos, s8 *noise)
54bc3a0d 847{
89a91f4f 848 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 849 u16 rate_info;
850
89a91f4f 851 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 852 return -1;
853 rmb();
854
855 rate_info = le16_to_cpu(rxd->rate_info);
856
857 memset(status, 0, sizeof(*status));
858
859 status->signal = -rxd->rssi;
0d462bbb 860 *noise = -rxd->noise_level;
89a91f4f
LB		 861 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
862 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 863
89a91f4f 864 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 865 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 866 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 867 status->flag |= RX_FLAG_40MHZ;
89a91f4f 868 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 869 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 870 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 871 status->flag |= RX_FLAG_HT;
872
85478344
LB		 873 if (rxd->channel > 14) {
874 status->band = IEEE80211_BAND_5GHZ;
875 if (!(status->flag & RX_FLAG_HT))
876 status->rate_idx -= 5;
877 } else {
878 status->band = IEEE80211_BAND_2GHZ;
879 }
54bc3a0d
LB		 880 status->freq = ieee80211_channel_to_frequency(rxd->channel);
881
20f09c3d
LB		 882 *qos = rxd->qos_control;
883
54bc3a0d
LB		 884 return le16_to_cpu(rxd->pkt_len);
885}
886
89a91f4f
LB		 887static struct rxd_ops rxd_sta_ops = {
888 .rxd_size = sizeof(struct mwl8k_rxd_sta),
889 .rxd_init = mwl8k_rxd_sta_init,
890 .rxd_refill = mwl8k_rxd_sta_refill,
891 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 892};
893
894
a66098da
LB		 895#define MWL8K_RX_DESCS 256
896#define MWL8K_RX_MAXSZ 3800
897
898static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
899{
900 struct mwl8k_priv *priv = hw->priv;
901 struct mwl8k_rx_queue *rxq = priv->rxq + index;
902 int size;
903 int i;
904
45eb400d
LB		 905 rxq->rxd_count = 0;
906 rxq->head = 0;
907 rxq->tail = 0;
a66098da 908
54bc3a0d 909 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 910
45eb400d
LB		 911 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
912 if (rxq->rxd == NULL) {
5db55844 913 wiphy_err(hw->wiphy, "failed to alloc RX descriptors\n");
a66098da
LB		 914 return -ENOMEM;
915 }
45eb400d 916 memset(rxq->rxd, 0, size);
a66098da 917
788838eb
LB		 918 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
919 if (rxq->buf == NULL) {
5db55844 920 wiphy_err(hw->wiphy, "failed to alloc RX skbuff list\n");
45eb400d 921 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 922 return -ENOMEM;
923 }
788838eb 924 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 925
926 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 927 int desc_size;
928 void *rxd;
a66098da 929 int nexti;
54bc3a0d
LB		 930 dma_addr_t next_dma_addr;
931
932 desc_size = priv->rxd_ops->rxd_size;
933 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 934
54bc3a0d
LB		 935 nexti = i + 1;
936 if (nexti == MWL8K_RX_DESCS)
937 nexti = 0;
938 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 939
54bc3a0d 940 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 941 }
942
943 return 0;
944}
945
946static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
947{
948 struct mwl8k_priv *priv = hw->priv;
949 struct mwl8k_rx_queue *rxq = priv->rxq + index;
950 int refilled;
951
952 refilled = 0;
45eb400d 953 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 954 struct sk_buff *skb;
788838eb 955 dma_addr_t addr;
a66098da 956 int rx;
54bc3a0d 957 void *rxd;
a66098da
LB		 958
959 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
960 if (skb == NULL)
961 break;
962
788838eb
LB		 963 addr = pci_map_single(priv->pdev, skb->data,
964 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 965
54bc3a0d
LB		 966 rxq->rxd_count++;
967 rx = rxq->tail++;
968 if (rxq->tail == MWL8K_RX_DESCS)
969 rxq->tail = 0;
788838eb 970 rxq->buf[rx].skb = skb;
53b1b3e1 971 dma_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 972
973 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
974 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 975
976 refilled++;
977 }
978
979 return refilled;
980}
981
982/* Must be called only when the card's reception is completely halted */
983static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
984{
985 struct mwl8k_priv *priv = hw->priv;
986 struct mwl8k_rx_queue *rxq = priv->rxq + index;
987 int i;
988
989 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 990 if (rxq->buf[i].skb != NULL) {
991 pci_unmap_single(priv->pdev,
53b1b3e1 992 dma_unmap_addr(&rxq->buf[i], dma),
788838eb 993 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 994 dma_unmap_addr_set(&rxq->buf[i], dma, 0);
788838eb
LB		 995
996 kfree_skb(rxq->buf[i].skb);
997 rxq->buf[i].skb = NULL;
a66098da
LB		 998 }
999 }
1000
788838eb
LB		 1001 kfree(rxq->buf);
1002 rxq->buf = NULL;
a66098da
LB		 1003
1004 pci_free_consistent(priv->pdev,
54bc3a0d 1005 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1006 rxq->rxd, rxq->rxd_dma);
1007 rxq->rxd = NULL;
a66098da
LB		 1008}
1009
1010
1011/*
1012 * Scan a list of BSSIDs to process for finalize join.
1013 * Allows for extension to process multiple BSSIDs.
1014 */
1015static inline int
1016mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1017{
1018 return priv->capture_beacon &&
1019 ieee80211_is_beacon(wh->frame_control) &&
1020 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1021}
1022
3779752d
LB		 1023static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1024 struct sk_buff *skb)
a66098da 1025{
3779752d
LB		 1026 struct mwl8k_priv *priv = hw->priv;
1027
a66098da 1028 priv->capture_beacon = false;
d89173f2 1029 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1030
1031 /*
1032 * Use GFP_ATOMIC as rxq_process is called from
1033 * the primary interrupt handler, memory allocation call
1034 * must not sleep.
1035 */
1036 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1037 if (priv->beacon_skb != NULL)
3779752d 1038 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1039}
1040
1041static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1042{
1043 struct mwl8k_priv *priv = hw->priv;
1044 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1045 int processed;
1046
1047 processed = 0;
45eb400d 1048 while (rxq->rxd_count && limit--) {
a66098da 1049 struct sk_buff *skb;
54bc3a0d
LB		 1050 void *rxd;
1051 int pkt_len;
a66098da 1052 struct ieee80211_rx_status status;
20f09c3d 1053 __le16 qos;
a66098da 1054
788838eb 1055 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1056 if (skb == NULL)
1057 break;
54bc3a0d
LB		 1058
1059 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1060
0d462bbb
JL		 1061 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos,
1062 &priv->noise);
54bc3a0d
LB		 1063 if (pkt_len < 0)
1064 break;
1065
788838eb
LB		 1066 rxq->buf[rxq->head].skb = NULL;
1067
1068 pci_unmap_single(priv->pdev,
53b1b3e1 1069 dma_unmap_addr(&rxq->buf[rxq->head], dma),
788838eb 1070 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
53b1b3e1 1071 dma_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1072
54bc3a0d
LB		 1073 rxq->head++;
1074 if (rxq->head == MWL8K_RX_DESCS)
1075 rxq->head = 0;
1076
45eb400d 1077 rxq->rxd_count--;
a66098da 1078
54bc3a0d 1079 skb_put(skb, pkt_len);
20f09c3d 1080 mwl8k_remove_dma_header(skb, qos);
a66098da 1081
a66098da 1082 /*
c2c357ce
LB		 1083 * Check for a pending join operation. Save a
1084 * copy of the beacon and schedule a tasklet to
1085 * send a FINALIZE_JOIN command to the firmware.
a66098da 1086 */
54bc3a0d 1087 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1088 mwl8k_save_beacon(hw, skb);
a66098da 1089
f1d58c25
JB		 1090 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1091 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1092
1093 processed++;
1094 }
1095
1096 return processed;
1097}
1098
1099
1100/*
1101 * Packet transmission.
1102 */
1103
a66098da
LB		 1104#define MWL8K_TXD_STATUS_OK 0x00000001
1105#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1106#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1107#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1108#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1109
e0493a8d
LB		 1110#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1111#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1112#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1113#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1114#define MWL8K_QOS_EOSP 0x0010
1115
a66098da
LB		 1116struct mwl8k_tx_desc {
1117 __le32 status;
1118 __u8 data_rate;
1119 __u8 tx_priority;
1120 __le16 qos_control;
1121 __le32 pkt_phys_addr;
1122 __le16 pkt_len;
d89173f2 1123 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1124 __le32 next_txd_phys_addr;
a66098da
LB		 1125 __le32 reserved;
1126 __le16 rate_info;
1127 __u8 peer_id;
c0bf9ca9 1128 __u8 xmitcontrol;
ba2d3587 1129} __packed;
a66098da
LB		 1130
1131#define MWL8K_TX_DESCS 128
c0bf9ca9
NS		 1132#define MWL8K_XMITCONTROL_NON_AMPDU 0x04
1133
a66098da
LB		 1134
1135static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1136{
1137 struct mwl8k_priv *priv = hw->priv;
1138 struct mwl8k_tx_queue *txq = priv->txq + index;
1139 int size;
1140 int i;
1141
8ccbc3b8 1142 txq->len = 0;
45eb400d
LB		 1143 txq->head = 0;
1144 txq->tail = 0;
a66098da
LB		 1145
1146 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1147
45eb400d
LB		 1148 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1149 if (txq->txd == NULL) {
5db55844 1150 wiphy_err(hw->wiphy, "failed to alloc TX descriptors\n");
a66098da
LB		 1151 return -ENOMEM;
1152 }
45eb400d 1153 memset(txq->txd, 0, size);
a66098da 1154
45eb400d
LB		 1155 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1156 if (txq->skb == NULL) {
5db55844 1157 wiphy_err(hw->wiphy, "failed to alloc TX skbuff list\n");
45eb400d 1158 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1159 return -ENOMEM;
1160 }
45eb400d 1161 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1162
1163 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1164 struct mwl8k_tx_desc *tx_desc;
1165 int nexti;
1166
45eb400d 1167 tx_desc = txq->txd + i;
a66098da
LB		 1168 nexti = (i + 1) % MWL8K_TX_DESCS;
1169
1170 tx_desc->status = 0;
45eb400d
LB		 1171 tx_desc->next_txd_phys_addr =
1172 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1173 }
1174
1175 return 0;
1176}
1177
1178static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1179{
1180 iowrite32(MWL8K_H2A_INT_PPA_READY,
1181 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1182 iowrite32(MWL8K_H2A_INT_DUMMY,
1183 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1184 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1185}
1186
7e1112d3 1187static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1188{
7e1112d3
LB		 1189 struct mwl8k_priv *priv = hw->priv;
1190 int i;
1191
1192 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1193 struct mwl8k_tx_queue *txq = priv->txq + i;
1194 int fw_owned = 0;
1195 int drv_owned = 0;
1196 int unused = 0;
1197 int desc;
1198
a66098da 1199 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1200 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1201 u32 status;
a66098da 1202
7e1112d3 1203 status = le32_to_cpu(tx_desc->status);
a66098da 1204 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1205 fw_owned++;
a66098da 1206 else
7e1112d3 1207 drv_owned++;
a66098da
LB		 1208
1209 if (tx_desc->pkt_len == 0)
7e1112d3 1210 unused++;
a66098da 1211 }
a66098da 1212
c96c31e4
JP		 1213 wiphy_err(hw->wiphy,
1214 "txq[%d] len=%d head=%d tail=%d "
1215 "fw_owned=%d drv_owned=%d unused=%d\n",
1216 i,
1217 txq->len, txq->head, txq->tail,
1218 fw_owned, drv_owned, unused);
7e1112d3 1219 }
a66098da
LB		 1220}
1221
618952a7 1222/*
88de754a 1223 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1224 */
62abd3cf 1225#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1226
950d5b01 1227static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1228{
a66098da 1229 struct mwl8k_priv *priv = hw->priv;
88de754a 1230 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1231 int retry;
1232 int rc;
a66098da
LB		 1233
1234 might_sleep();
1235
7e1112d3
LB		 1236 /*
1237 * The TX queues are stopped at this point, so this test
1238 * doesn't need to take ->tx_lock.
1239 */
1240 if (!priv->pending_tx_pkts)
1241 return 0;
1242
1243 retry = 0;
1244 rc = 0;
1245
a66098da 1246 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1247 priv->tx_wait = &tx_wait;
1248 while (!rc) {
1249 int oldcount;
1250 unsigned long timeout;
a66098da 1251
7e1112d3 1252 oldcount = priv->pending_tx_pkts;
a66098da 1253
7e1112d3 1254 spin_unlock_bh(&priv->tx_lock);
88de754a 1255 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1256 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1257 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1258
1259 if (timeout) {
1260 WARN_ON(priv->pending_tx_pkts);
1261 if (retry) {
c96c31e4 1262 wiphy_notice(hw->wiphy, "tx rings drained\n");
7e1112d3
LB		 1263 }
1264 break;
1265 }
1266
1267 if (priv->pending_tx_pkts < oldcount) {
c96c31e4
JP		 1268 wiphy_notice(hw->wiphy,
1269 "waiting for tx rings to drain (%d -> %d pkts)\n",
1270 oldcount, priv->pending_tx_pkts);
7e1112d3
LB		 1271 retry = 1;
1272 continue;
1273 }
1274
a66098da 1275 priv->tx_wait = NULL;
a66098da 1276
c96c31e4
JP		 1277 wiphy_err(hw->wiphy, "tx rings stuck for %d ms\n",
1278 MWL8K_TX_WAIT_TIMEOUT_MS);
7e1112d3
LB		 1279 mwl8k_dump_tx_rings(hw);
1280
1281 rc = -ETIMEDOUT;
a66098da 1282 }
7e1112d3 1283 spin_unlock_bh(&priv->tx_lock);
a66098da 1284
7e1112d3 1285 return rc;
a66098da
LB		 1286}
1287
c23b5a69
LB		 1288#define MWL8K_TXD_SUCCESS(status) \
1289 ((status) & (MWL8K_TXD_STATUS_OK | \
1290 MWL8K_TXD_STATUS_OK_RETRY | \
1291 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1292
efb7c49a
LB		 1293static int
1294mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1295{
1296 struct mwl8k_priv *priv = hw->priv;
1297 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1298 int processed;
a66098da 1299
efb7c49a 1300 processed = 0;
8ccbc3b8 1301 while (txq->len > 0 && limit--) {
a66098da 1302 int tx;
a66098da
LB		 1303 struct mwl8k_tx_desc *tx_desc;
1304 unsigned long addr;
ce9e2e1b 1305 int size;
a66098da
LB		 1306 struct sk_buff *skb;
1307 struct ieee80211_tx_info *info;
1308 u32 status;
1309
45eb400d
LB		 1310 tx = txq->head;
1311 tx_desc = txq->txd + tx;
a66098da
LB		 1312
1313 status = le32_to_cpu(tx_desc->status);
1314
1315 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1316 if (!force)
1317 break;
1318 tx_desc->status &=
1319 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1320 }
1321
45eb400d 1322 txq->head = (tx + 1) % MWL8K_TX_DESCS;
8ccbc3b8
KV		 1323 BUG_ON(txq->len == 0);
1324 txq->len--;
a66098da
LB		 1325 priv->pending_tx_pkts--;
1326
1327 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1328 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1329 skb = txq->skb[tx];
1330 txq->skb[tx] = NULL;
a66098da
LB		 1331
1332 BUG_ON(skb == NULL);
1333 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1334
20f09c3d 1335 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1336
1337 /* Mark descriptor as unused */
1338 tx_desc->pkt_phys_addr = 0;
1339 tx_desc->pkt_len = 0;
1340
a66098da
LB		 1341 info = IEEE80211_SKB_CB(skb);
1342 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1343 if (MWL8K_TXD_SUCCESS(status))
a66098da 1344 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1345
1346 ieee80211_tx_status_irqsafe(hw, skb);
1347
efb7c49a 1348 processed++;
a66098da
LB		 1349 }
1350
efb7c49a 1351 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1352 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1353
1354 return processed;
a66098da
LB		 1355}
1356
1357/* must be called only when the card's transmit is completely halted */
1358static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1359{
1360 struct mwl8k_priv *priv = hw->priv;
1361 struct mwl8k_tx_queue *txq = priv->txq + index;
1362
efb7c49a 1363 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1364
45eb400d
LB		 1365 kfree(txq->skb);
1366 txq->skb = NULL;
a66098da
LB		 1367
1368 pci_free_consistent(priv->pdev,
1369 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1370 txq->txd, txq->txd_dma);
1371 txq->txd = NULL;
a66098da
LB		 1372}
1373
1374static int
1375mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1376{
1377 struct mwl8k_priv *priv = hw->priv;
1378 struct ieee80211_tx_info *tx_info;
23b33906 1379 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1380 struct ieee80211_hdr *wh;
1381 struct mwl8k_tx_queue *txq;
1382 struct mwl8k_tx_desc *tx;
a66098da 1383 dma_addr_t dma;
23b33906
LB		 1384 u32 txstatus;
1385 u8 txdatarate;
1386 u16 qos;
a66098da 1387
23b33906
LB		 1388 wh = (struct ieee80211_hdr *)skb->data;
1389 if (ieee80211_is_data_qos(wh->frame_control))
1390 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1391 else
1392 qos = 0;
a66098da 1393
76266b2a 1394 mwl8k_add_dma_header(skb);
23b33906 1395 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1396
1397 tx_info = IEEE80211_SKB_CB(skb);
1398 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1399
1400 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1401 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1402 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1403 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1404 }
1405
23b33906
LB		 1406 /* Setup firmware control bit fields for each frame type. */
1407 txstatus = 0;
1408 txdatarate = 0;
1409 if (ieee80211_is_mgmt(wh->frame_control) ||
1410 ieee80211_is_ctl(wh->frame_control)) {
1411 txdatarate = 0;
e0493a8d 1412 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1413 } else if (ieee80211_is_data(wh->frame_control)) {
1414 txdatarate = 1;
1415 if (is_multicast_ether_addr(wh->addr1))
1416 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1417
e0493a8d 1418 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1419 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1420 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1421 else
e0493a8d 1422 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1423 }
a66098da
LB		 1424
1425 dma = pci_map_single(priv->pdev, skb->data,
1426 skb->len, PCI_DMA_TODEVICE);
1427
1428 if (pci_dma_mapping_error(priv->pdev, dma)) {
c96c31e4
JP		 1429 wiphy_debug(hw->wiphy,
1430 "failed to dma map skb, dropping TX frame.\n");
23b33906 1431 dev_kfree_skb(skb);
a66098da
LB		 1432 return NETDEV_TX_OK;
1433 }
1434
23b33906 1435 spin_lock_bh(&priv->tx_lock);
a66098da 1436
23b33906 1437 txq = priv->txq + index;
a66098da 1438
45eb400d
LB		 1439 BUG_ON(txq->skb[txq->tail] != NULL);
1440 txq->skb[txq->tail] = skb;
a66098da 1441
45eb400d 1442 tx = txq->txd + txq->tail;
23b33906
LB		 1443 tx->data_rate = txdatarate;
1444 tx->tx_priority = index;
a66098da 1445 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1446 tx->pkt_phys_addr = cpu_to_le32(dma);
1447 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1448 tx->rate_info = 0;
a680400e
LB		 1449 if (!priv->ap_fw && tx_info->control.sta != NULL)
1450 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1451 else
1452 tx->peer_id = 0;
c0bf9ca9
NS		 1453
1454 if (priv->ap_fw)
1455 tx->xmitcontrol = MWL8K_XMITCONTROL_NON_AMPDU;
a66098da 1456 wmb();
23b33906
LB		 1457 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1458
8ccbc3b8 1459 txq->len++;
a66098da 1460 priv->pending_tx_pkts++;
a66098da 1461
45eb400d
LB		 1462 txq->tail++;
1463 if (txq->tail == MWL8K_TX_DESCS)
1464 txq->tail = 0;
23b33906 1465
45eb400d 1466 if (txq->head == txq->tail)
a66098da
LB		 1467 ieee80211_stop_queue(hw, index);
1468
23b33906 1469 mwl8k_tx_start(priv);
a66098da
LB		 1470
1471 spin_unlock_bh(&priv->tx_lock);
1472
1473 return NETDEV_TX_OK;
1474}
1475
1476
618952a7
LB		 1477/*
1478 * Firmware access.
1479 *
1480 * We have the following requirements for issuing firmware commands:
1481 * - Some commands require that the packet transmit path is idle when
1482 * the command is issued. (For simplicity, we'll just quiesce the
1483 * transmit path for every command.)
1484 * - There are certain sequences of commands that need to be issued to
1485 * the hardware sequentially, with no other intervening commands.
1486 *
1487 * This leads to an implementation of a "firmware lock" as a mutex that
1488 * can be taken recursively, and which is taken by both the low-level
1489 * command submission function (mwl8k_post_cmd) as well as any users of
1490 * that function that require issuing of an atomic sequence of commands,
1491 * and quiesces the transmit path whenever it's taken.
1492 */
1493static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1494{
1495 struct mwl8k_priv *priv = hw->priv;
1496
1497 if (priv->fw_mutex_owner != current) {
1498 int rc;
1499
1500 mutex_lock(&priv->fw_mutex);
1501 ieee80211_stop_queues(hw);
1502
1503 rc = mwl8k_tx_wait_empty(hw);
1504 if (rc) {
1505 ieee80211_wake_queues(hw);
1506 mutex_unlock(&priv->fw_mutex);
1507
1508 return rc;
1509 }
1510
1511 priv->fw_mutex_owner = current;
1512 }
1513
1514 priv->fw_mutex_depth++;
1515
1516 return 0;
1517}
1518
1519static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1520{
1521 struct mwl8k_priv *priv = hw->priv;
1522
1523 if (!--priv->fw_mutex_depth) {
1524 ieee80211_wake_queues(hw);
1525 priv->fw_mutex_owner = NULL;
1526 mutex_unlock(&priv->fw_mutex);
1527 }
1528}
1529
1530
a66098da
LB		 1531/*
1532 * Command processing.
1533 */
1534
0c9cc640
LB		 1535/* Timeout firmware commands after 10s */
1536#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1537
1538static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1539{
1540 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1541 struct mwl8k_priv *priv = hw->priv;
1542 void __iomem *regs = priv->regs;
1543 dma_addr_t dma_addr;
1544 unsigned int dma_size;
1545 int rc;
a66098da
LB		 1546 unsigned long timeout = 0;
1547 u8 buf[32];
1548
b603742f 1549 cmd->result = (__force __le16) 0xffff;
a66098da
LB		 1550 dma_size = le16_to_cpu(cmd->length);
1551 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1552 PCI_DMA_BIDIRECTIONAL);
1553 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1554 return -ENOMEM;
1555
618952a7 1556 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1557 if (rc) {
1558 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1559 PCI_DMA_BIDIRECTIONAL);
618952a7 1560 return rc;
39a1e42e 1561 }
a66098da 1562
a66098da
LB		 1563 priv->hostcmd_wait = &cmd_wait;
1564 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1565 iowrite32(MWL8K_H2A_INT_DOORBELL,
1566 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1567 iowrite32(MWL8K_H2A_INT_DUMMY,
1568 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1569
1570 timeout = wait_for_completion_timeout(&cmd_wait,
1571 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1572
618952a7
LB		 1573 priv->hostcmd_wait = NULL;
1574
1575 mwl8k_fw_unlock(hw);
1576
37055bd4
LB		 1577 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1578 PCI_DMA_BIDIRECTIONAL);
1579
a66098da 1580 if (!timeout) {
5db55844 1581 wiphy_err(hw->wiphy, "Command %s timeout after %u ms\n",
c96c31e4
JP		 1582 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1583 MWL8K_CMD_TIMEOUT_MS);
a66098da
LB		 1584 rc = -ETIMEDOUT;
1585 } else {
0c9cc640
LB		 1586 int ms;
1587
1588 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1589
ce9e2e1b 1590 rc = cmd->result ? -EINVAL : 0;
a66098da 1591 if (rc)
5db55844 1592 wiphy_err(hw->wiphy, "Command %s error 0x%x\n",
c96c31e4
JP		 1593 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1594 le16_to_cpu(cmd->result));
0c9cc640 1595 else if (ms > 2000)
5db55844 1596 wiphy_notice(hw->wiphy, "Command %s took %d ms\n",
c96c31e4
JP		 1597 mwl8k_cmd_name(cmd->code,
1598 buf, sizeof(buf)),
1599 ms);
a66098da
LB		 1600 }
1601
a66098da
LB		 1602 return rc;
1603}
1604
f57ca9c1
LB		 1605static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
1606 struct ieee80211_vif *vif,
1607 struct mwl8k_cmd_pkt *cmd)
1608{
1609 if (vif != NULL)
1610 cmd->macid = MWL8K_VIF(vif)->macid;
1611 return mwl8k_post_cmd(hw, cmd);
1612}
1613
1349ad2f
LB		 1614/*
1615 * Setup code shared between STA and AP firmware images.
1616 */
1617static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
1618{
1619 struct mwl8k_priv *priv = hw->priv;
1620
1621 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
1622 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
1623
1624 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
1625 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
1626
1627 priv->band_24.band = IEEE80211_BAND_2GHZ;
1628 priv->band_24.channels = priv->channels_24;
1629 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
1630 priv->band_24.bitrates = priv->rates_24;
1631 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
1632
1633 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
1634}
1635
4eae9edd
LB		 1636static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
1637{
1638 struct mwl8k_priv *priv = hw->priv;
1639
1640 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
1641 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
1642
1643 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
1644 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
1645
1646 priv->band_50.band = IEEE80211_BAND_5GHZ;
1647 priv->band_50.channels = priv->channels_50;
1648 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
1649 priv->band_50.bitrates = priv->rates_50;
1650 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
1651
1652 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
1653}
1654
a66098da 1655/*
04b147b1 1656 * CMD_GET_HW_SPEC (STA version).
a66098da 1657 */
04b147b1 1658struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1659 struct mwl8k_cmd_pkt header;
1660 __u8 hw_rev;
1661 __u8 host_interface;
1662 __le16 num_mcaddrs;
d89173f2 1663 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1664 __le16 region_code;
1665 __le32 fw_rev;
1666 __le32 ps_cookie;
1667 __le32 caps;
1668 __u8 mcs_bitmap[16];
1669 __le32 rx_queue_ptr;
1670 __le32 num_tx_queues;
1671 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1672 __le32 caps2;
1673 __le32 num_tx_desc_per_queue;
45eb400d 1674 __le32 total_rxd;
ba2d3587 1675} __packed;
a66098da 1676
341c9791
LB		 1677#define MWL8K_CAP_MAX_AMSDU 0x20000000
1678#define MWL8K_CAP_GREENFIELD 0x08000000
1679#define MWL8K_CAP_AMPDU 0x04000000
1680#define MWL8K_CAP_RX_STBC 0x01000000
1681#define MWL8K_CAP_TX_STBC 0x00800000
1682#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1683#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1684#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1685#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1686#define MWL8K_CAP_DELAY_BA 0x00003000
1687#define MWL8K_CAP_MIMO 0x00000200
1688#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 1689#define MWL8K_CAP_BAND_MASK 0x00000007
1690#define MWL8K_CAP_5GHZ 0x00000004
1691#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 1692
06953235
LB		 1693static void
1694mwl8k_set_ht_caps(struct ieee80211_hw *hw,
1695 struct ieee80211_supported_band *band, u32 cap)
341c9791 1696{
341c9791
LB		 1697 int rx_streams;
1698 int tx_streams;
1699
777ad375 1700 band->ht_cap.ht_supported = 1;
341c9791
LB		 1701
1702 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 1703 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 1704 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 1705 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 1706 if (cap & MWL8K_CAP_AMPDU) {
1707 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 1708 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1709 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 1710 }
1711 if (cap & MWL8K_CAP_RX_STBC)
777ad375 1712 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 1713 if (cap & MWL8K_CAP_TX_STBC)
777ad375 1714 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 1715 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 1716 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 1717 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 1718 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 1719 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 1720 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 1721 if (cap & MWL8K_CAP_40MHZ)
777ad375 1722 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 1723
1724 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1725 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1726
777ad375 1727 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 1728 if (rx_streams >= 2)
777ad375 1729 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 1730 if (rx_streams >= 3)
777ad375
LB		 1731 band->ht_cap.mcs.rx_mask[2] = 0xff;
1732 band->ht_cap.mcs.rx_mask[4] = 0x01;
1733 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 1734
1735 if (rx_streams != tx_streams) {
777ad375
LB		 1736 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1737 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 1738 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1739 }
1740}
1741
06953235
LB		 1742static void
1743mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
1744{
1745 struct mwl8k_priv *priv = hw->priv;
1746
1747 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
1748 mwl8k_setup_2ghz_band(hw);
1749 if (caps & MWL8K_CAP_MIMO)
1750 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
1751 }
1752
1753 if (caps & MWL8K_CAP_5GHZ) {
1754 mwl8k_setup_5ghz_band(hw);
1755 if (caps & MWL8K_CAP_MIMO)
1756 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
1757 }
1758}
1759
04b147b1 1760static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1761{
1762 struct mwl8k_priv *priv = hw->priv;
04b147b1 1763 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1764 int rc;
1765 int i;
1766
1767 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1768 if (cmd == NULL)
1769 return -ENOMEM;
1770
1771 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1772 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1773
1774 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1775 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1776 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1777 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1778 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1779 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1780 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1781 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1782
1783 rc = mwl8k_post_cmd(hw, &cmd->header);
1784
1785 if (!rc) {
1786 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1787 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1788 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1789 priv->hw_rev = cmd->hw_rev;
06953235 1790 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
ee0ddf18
LB		 1791 priv->ap_macids_supported = 0x00000000;
1792 priv->sta_macids_supported = 0x00000001;
a66098da
LB		 1793 }
1794
1795 kfree(cmd);
1796 return rc;
1797}
1798
42fba21d
LB		 1799/*
1800 * CMD_GET_HW_SPEC (AP version).
1801 */
1802struct mwl8k_cmd_get_hw_spec_ap {
1803 struct mwl8k_cmd_pkt header;
1804 __u8 hw_rev;
1805 __u8 host_interface;
1806 __le16 num_wcb;
1807 __le16 num_mcaddrs;
1808 __u8 perm_addr[ETH_ALEN];
1809 __le16 region_code;
1810 __le16 num_antenna;
1811 __le32 fw_rev;
1812 __le32 wcbbase0;
1813 __le32 rxwrptr;
1814 __le32 rxrdptr;
1815 __le32 ps_cookie;
1816 __le32 wcbbase1;
1817 __le32 wcbbase2;
1818 __le32 wcbbase3;
ba2d3587 1819} __packed;
42fba21d
LB		 1820
1821static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1822{
1823 struct mwl8k_priv *priv = hw->priv;
1824 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1825 int rc;
1826
1827 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1828 if (cmd == NULL)
1829 return -ENOMEM;
1830
1831 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1832 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1833
1834 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1835 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1836
1837 rc = mwl8k_post_cmd(hw, &cmd->header);
1838
1839 if (!rc) {
1840 int off;
1841
1842 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1843 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1844 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1845 priv->hw_rev = cmd->hw_rev;
1349ad2f 1846 mwl8k_setup_2ghz_band(hw);
ee0ddf18
LB		 1847 priv->ap_macids_supported = 0x000000ff;
1848 priv->sta_macids_supported = 0x00000000;
42fba21d
LB		 1849
1850 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
b603742f 1851 iowrite32(priv->txq[0].txd_dma, priv->sram + off);
42fba21d
LB		 1852
1853 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
b603742f 1854 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 1855
1856 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
b603742f 1857 iowrite32(priv->rxq[0].rxd_dma, priv->sram + off);
42fba21d
LB		 1858
1859 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
b603742f 1860 iowrite32(priv->txq[1].txd_dma, priv->sram + off);
42fba21d
LB		 1861
1862 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
b603742f 1863 iowrite32(priv->txq[2].txd_dma, priv->sram + off);
42fba21d
LB		 1864
1865 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
b603742f 1866 iowrite32(priv->txq[3].txd_dma, priv->sram + off);
42fba21d
LB		 1867 }
1868
1869 kfree(cmd);
1870 return rc;
1871}
1872
1873/*
1874 * CMD_SET_HW_SPEC.
1875 */
1876struct mwl8k_cmd_set_hw_spec {
1877 struct mwl8k_cmd_pkt header;
1878 __u8 hw_rev;
1879 __u8 host_interface;
1880 __le16 num_mcaddrs;
1881 __u8 perm_addr[ETH_ALEN];
1882 __le16 region_code;
1883 __le32 fw_rev;
1884 __le32 ps_cookie;
1885 __le32 caps;
1886 __le32 rx_queue_ptr;
1887 __le32 num_tx_queues;
1888 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1889 __le32 flags;
1890 __le32 num_tx_desc_per_queue;
1891 __le32 total_rxd;
ba2d3587 1892} __packed;
42fba21d 1893
b64fe619
LB		 1894#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1895#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
1896#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 1897
1898static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1899{
1900 struct mwl8k_priv *priv = hw->priv;
1901 struct mwl8k_cmd_set_hw_spec *cmd;
1902 int rc;
1903 int i;
1904
1905 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1906 if (cmd == NULL)
1907 return -ENOMEM;
1908
1909 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1910 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1911
1912 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1913 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1914 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1915 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1916 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB		 1917 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
1918 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
1919 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 1920 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1921 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1922
1923 rc = mwl8k_post_cmd(hw, &cmd->header);
1924 kfree(cmd);
1925
1926 return rc;
1927}
1928
a66098da
LB		 1929/*
1930 * CMD_MAC_MULTICAST_ADR.
1931 */
1932struct mwl8k_cmd_mac_multicast_adr {
1933 struct mwl8k_cmd_pkt header;
1934 __le16 action;
1935 __le16 numaddr;
ce9e2e1b 1936 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1937};
1938
d5e30845
LB		 1939#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1940#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1941#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1942#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1943
e81cd2d6 1944static struct mwl8k_cmd_pkt *
447ced07 1945__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
22bedad3 1946 struct netdev_hw_addr_list *mc_list)
a66098da 1947{
e81cd2d6 1948 struct mwl8k_priv *priv = hw->priv;
a66098da 1949 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1950 int size;
22bedad3
JP		 1951 int mc_count = 0;
1952
1953 if (mc_list)
1954 mc_count = netdev_hw_addr_list_count(mc_list);
e81cd2d6 1955
447ced07 1956 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1957 allmulti = 1;
1958 mc_count = 0;
1959 }
e81cd2d6
LB		 1960
1961 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1962
e81cd2d6 1963 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1964 if (cmd == NULL)
e81cd2d6 1965 return NULL;
a66098da
LB		 1966
1967 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1968 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1969 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1970 MWL8K_ENABLE_RX_BROADCAST);
1971
1972 if (allmulti) {
1973 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1974 } else if (mc_count) {
22bedad3
JP		 1975 struct netdev_hw_addr *ha;
1976 int i = 0;
d5e30845
LB		 1977
1978 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1979 cmd->numaddr = cpu_to_le16(mc_count);
22bedad3
JP		 1980 netdev_hw_addr_list_for_each(ha, mc_list) {
1981 memcpy(cmd->addr[i], ha->addr, ETH_ALEN);
a66098da 1982 }
a66098da
LB		 1983 }
1984
e81cd2d6 1985 return &cmd->header;
a66098da
LB		 1986}
1987
1988/*
55489b6e 1989 * CMD_GET_STAT.
a66098da 1990 */
55489b6e 1991struct mwl8k_cmd_get_stat {
a66098da 1992 struct mwl8k_cmd_pkt header;
a66098da 1993 __le32 stats[64];
ba2d3587 1994} __packed;
a66098da
LB		 1995
1996#define MWL8K_STAT_ACK_FAILURE 9
1997#define MWL8K_STAT_RTS_FAILURE 12
1998#define MWL8K_STAT_FCS_ERROR 24
1999#define MWL8K_STAT_RTS_SUCCESS 11
2000
55489b6e
LB		 2001static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
2002 struct ieee80211_low_level_stats *stats)
a66098da 2003{
55489b6e 2004 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 2005 int rc;
2006
2007 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2008 if (cmd == NULL)
2009 return -ENOMEM;
2010
2011 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2012 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2013
2014 rc = mwl8k_post_cmd(hw, &cmd->header);
2015 if (!rc) {
2016 stats->dot11ACKFailureCount =
2017 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2018 stats->dot11RTSFailureCount =
2019 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2020 stats->dot11FCSErrorCount =
2021 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2022 stats->dot11RTSSuccessCount =
2023 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2024 }
2025 kfree(cmd);
2026
2027 return rc;
2028}
2029
2030/*
55489b6e 2031 * CMD_RADIO_CONTROL.
a66098da 2032 */
55489b6e 2033struct mwl8k_cmd_radio_control {
a66098da
LB		 2034 struct mwl8k_cmd_pkt header;
2035 __le16 action;
2036 __le16 control;
2037 __le16 radio_on;
ba2d3587 2038} __packed;
a66098da 2039
c46563b7 2040static int
55489b6e 2041mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2042{
2043 struct mwl8k_priv *priv = hw->priv;
55489b6e 2044 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2045 int rc;
2046
c46563b7 2047 if (enable == priv->radio_on && !force)
a66098da
LB		 2048 return 0;
2049
a66098da
LB		 2050 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2051 if (cmd == NULL)
2052 return -ENOMEM;
2053
2054 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2055 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2056 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2057 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2058 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2059
2060 rc = mwl8k_post_cmd(hw, &cmd->header);
2061 kfree(cmd);
2062
2063 if (!rc)
c46563b7 2064 priv->radio_on = enable;
a66098da
LB		 2065
2066 return rc;
2067}
2068
55489b6e 2069static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2070{
55489b6e 2071 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2072}
2073
55489b6e 2074static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2075{
55489b6e 2076 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2077}
2078
a66098da
LB		 2079static int
2080mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2081{
99200a99 2082 struct mwl8k_priv *priv = hw->priv;
a66098da 2083
68ce3884 2084 priv->radio_short_preamble = short_preamble;
a66098da 2085
55489b6e 2086 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2087}
2088
2089/*
55489b6e 2090 * CMD_RF_TX_POWER.
a66098da
LB		 2091 */
2092#define MWL8K_TX_POWER_LEVEL_TOTAL 8
2093
55489b6e 2094struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2095 struct mwl8k_cmd_pkt header;
2096 __le16 action;
2097 __le16 support_level;
2098 __le16 current_level;
2099 __le16 reserved;
2100 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
ba2d3587 2101} __packed;
a66098da 2102
55489b6e 2103static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2104{
55489b6e 2105 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2106 int rc;
2107
2108 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2109 if (cmd == NULL)
2110 return -ENOMEM;
2111
2112 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2113 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2114 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2115 cmd->support_level = cpu_to_le16(dBm);
2116
2117 rc = mwl8k_post_cmd(hw, &cmd->header);
2118 kfree(cmd);
2119
2120 return rc;
2121}
2122
08b06347
LB		 2123/*
2124 * CMD_RF_ANTENNA.
2125 */
2126struct mwl8k_cmd_rf_antenna {
2127 struct mwl8k_cmd_pkt header;
2128 __le16 antenna;
2129 __le16 mode;
ba2d3587 2130} __packed;
08b06347
LB		 2131
2132#define MWL8K_RF_ANTENNA_RX 1
2133#define MWL8K_RF_ANTENNA_TX 2
2134
2135static int
2136mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2137{
2138 struct mwl8k_cmd_rf_antenna *cmd;
2139 int rc;
2140
2141 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2142 if (cmd == NULL)
2143 return -ENOMEM;
2144
2145 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2146 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2147 cmd->antenna = cpu_to_le16(antenna);
2148 cmd->mode = cpu_to_le16(mask);
2149
2150 rc = mwl8k_post_cmd(hw, &cmd->header);
2151 kfree(cmd);
2152
2153 return rc;
2154}
2155
b64fe619
LB		 2156/*
2157 * CMD_SET_BEACON.
2158 */
2159struct mwl8k_cmd_set_beacon {
2160 struct mwl8k_cmd_pkt header;
2161 __le16 beacon_len;
2162 __u8 beacon[0];
2163};
2164
aa21d0f6
LB		 2165static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw,
2166 struct ieee80211_vif *vif, u8 *beacon, int len)
b64fe619
LB		 2167{
2168 struct mwl8k_cmd_set_beacon *cmd;
2169 int rc;
2170
2171 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2172 if (cmd == NULL)
2173 return -ENOMEM;
2174
2175 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2176 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2177 cmd->beacon_len = cpu_to_le16(len);
2178 memcpy(cmd->beacon, beacon, len);
2179
aa21d0f6 2180 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2181 kfree(cmd);
2182
2183 return rc;
2184}
2185
a66098da
LB		 2186/*
2187 * CMD_SET_PRE_SCAN.
2188 */
2189struct mwl8k_cmd_set_pre_scan {
2190 struct mwl8k_cmd_pkt header;
ba2d3587 2191} __packed;
a66098da
LB		 2192
2193static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2194{
2195 struct mwl8k_cmd_set_pre_scan *cmd;
2196 int rc;
2197
2198 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2199 if (cmd == NULL)
2200 return -ENOMEM;
2201
2202 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2203 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2204
2205 rc = mwl8k_post_cmd(hw, &cmd->header);
2206 kfree(cmd);
2207
2208 return rc;
2209}
2210
2211/*
2212 * CMD_SET_POST_SCAN.
2213 */
2214struct mwl8k_cmd_set_post_scan {
2215 struct mwl8k_cmd_pkt header;
2216 __le32 isibss;
d89173f2 2217 __u8 bssid[ETH_ALEN];
ba2d3587 2218} __packed;
a66098da
LB		 2219
2220static int
0a11dfc3 2221mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2222{
2223 struct mwl8k_cmd_set_post_scan *cmd;
2224 int rc;
2225
2226 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2227 if (cmd == NULL)
2228 return -ENOMEM;
2229
2230 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2231 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2232 cmd->isibss = 0;
d89173f2 2233 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2234
2235 rc = mwl8k_post_cmd(hw, &cmd->header);
2236 kfree(cmd);
2237
2238 return rc;
2239}
2240
2241/*
2242 * CMD_SET_RF_CHANNEL.
2243 */
2244struct mwl8k_cmd_set_rf_channel {
2245 struct mwl8k_cmd_pkt header;
2246 __le16 action;
2247 __u8 current_channel;
2248 __le32 channel_flags;
ba2d3587 2249} __packed;
a66098da
LB		 2250
2251static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2252 struct ieee80211_conf *conf)
a66098da 2253{
610677d2 2254 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2255 struct mwl8k_cmd_set_rf_channel *cmd;
2256 int rc;
2257
2258 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2259 if (cmd == NULL)
2260 return -ENOMEM;
2261
2262 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2263 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2264 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2265 cmd->current_channel = channel->hw_value;
610677d2 2266
a66098da 2267 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 2268 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 2269 else if (channel->band == IEEE80211_BAND_5GHZ)
2270 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB		 2271
2272 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2273 conf->channel_type == NL80211_CHAN_HT20)
2274 cmd->channel_flags |= cpu_to_le32(0x00000080);
2275 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2276 cmd->channel_flags |= cpu_to_le32(0x000001900);
2277 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2278 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2279
2280 rc = mwl8k_post_cmd(hw, &cmd->header);
2281 kfree(cmd);
2282
2283 return rc;
2284}
2285
2286/*
55489b6e 2287 * CMD_SET_AID.
a66098da 2288 */
55489b6e
LB		 2289#define MWL8K_FRAME_PROT_DISABLED 0x00
2290#define MWL8K_FRAME_PROT_11G 0x07
2291#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2292#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2293
55489b6e
LB		 2294struct mwl8k_cmd_update_set_aid {
2295 struct mwl8k_cmd_pkt header;
2296 __le16 aid;
a66098da 2297
55489b6e
LB		 2298 /* AP's MAC address (BSSID) */
2299 __u8 bssid[ETH_ALEN];
2300 __le16 protection_mode;
2301 __u8 supp_rates[14];
ba2d3587 2302} __packed;
a66098da 2303
c6e96010
LB		 2304static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2305{
2306 int i;
2307 int j;
2308
2309 /*
2310 * Clear nonstandard rates 4 and 13.
2311 */
2312 mask &= 0x1fef;
2313
2314 for (i = 0, j = 0; i < 14; i++) {
2315 if (mask & (1 << i))
777ad375 2316 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 2317 }
2318}
2319
55489b6e 2320static int
c6e96010
LB		 2321mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2322 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2323{
55489b6e
LB		 2324 struct mwl8k_cmd_update_set_aid *cmd;
2325 u16 prot_mode;
a66098da
LB		 2326 int rc;
2327
2328 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2329 if (cmd == NULL)
2330 return -ENOMEM;
2331
55489b6e 2332 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2333 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2334 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2335 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2336
7dc6a7a7 2337 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2338 prot_mode = MWL8K_FRAME_PROT_11G;
2339 } else {
7dc6a7a7 2340 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2341 IEEE80211_HT_OP_MODE_PROTECTION) {
2342 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2343 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2344 break;
2345 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2346 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2347 break;
2348 default:
2349 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2350 break;
2351 }
2352 }
2353 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2354
c6e96010 2355 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2356
2357 rc = mwl8k_post_cmd(hw, &cmd->header);
2358 kfree(cmd);
2359
2360 return rc;
2361}
2362
32060e1b 2363/*
55489b6e 2364 * CMD_SET_RATE.
32060e1b 2365 */
55489b6e
LB		 2366struct mwl8k_cmd_set_rate {
2367 struct mwl8k_cmd_pkt header;
2368 __u8 legacy_rates[14];
2369
2370 /* Bitmap for supported MCS codes. */
2371 __u8 mcs_set[16];
2372 __u8 reserved[16];
ba2d3587 2373} __packed;
32060e1b 2374
55489b6e 2375static int
c6e96010 2376mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2377 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2378{
55489b6e 2379 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2380 int rc;
2381
2382 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2383 if (cmd == NULL)
2384 return -ENOMEM;
2385
55489b6e 2386 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2387 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2388 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2389 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2390
2391 rc = mwl8k_post_cmd(hw, &cmd->header);
2392 kfree(cmd);
2393
2394 return rc;
2395}
2396
a66098da 2397/*
55489b6e 2398 * CMD_FINALIZE_JOIN.
a66098da 2399 */
55489b6e
LB		 2400#define MWL8K_FJ_BEACON_MAXLEN 128
2401
2402struct mwl8k_cmd_finalize_join {
a66098da 2403 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2404 __le32 sleep_interval; /* Number of beacon periods to sleep */
2405 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
ba2d3587 2406} __packed;
a66098da 2407
55489b6e
LB		 2408static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2409 int framelen, int dtim)
a66098da 2410{
55489b6e
LB		 2411 struct mwl8k_cmd_finalize_join *cmd;
2412 struct ieee80211_mgmt *payload = frame;
2413 int payload_len;
a66098da
LB		 2414 int rc;
2415
2416 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2417 if (cmd == NULL)
2418 return -ENOMEM;
2419
55489b6e 2420 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2421 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2422 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2423
2424 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2425 if (payload_len < 0)
2426 payload_len = 0;
2427 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2428 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2429
2430 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2431
2432 rc = mwl8k_post_cmd(hw, &cmd->header);
2433 kfree(cmd);
2434
2435 return rc;
2436}
2437
2438/*
55489b6e 2439 * CMD_SET_RTS_THRESHOLD.
a66098da 2440 */
55489b6e 2441struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2442 struct mwl8k_cmd_pkt header;
2443 __le16 action;
55489b6e 2444 __le16 threshold;
ba2d3587 2445} __packed;
a66098da 2446
c2c2b12a
LB		 2447static int
2448mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2449{
55489b6e 2450 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2451 int rc;
2452
2453 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2454 if (cmd == NULL)
2455 return -ENOMEM;
2456
55489b6e 2457 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2458 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 2459 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2460 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 2461
2462 rc = mwl8k_post_cmd(hw, &cmd->header);
2463 kfree(cmd);
2464
a66098da
LB		 2465 return rc;
2466}
2467
2468/*
55489b6e 2469 * CMD_SET_SLOT.
a66098da 2470 */
55489b6e 2471struct mwl8k_cmd_set_slot {
a66098da
LB		 2472 struct mwl8k_cmd_pkt header;
2473 __le16 action;
55489b6e 2474 __u8 short_slot;
ba2d3587 2475} __packed;
a66098da 2476
55489b6e 2477static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2478{
55489b6e 2479 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2480 int rc;
2481
2482 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2483 if (cmd == NULL)
2484 return -ENOMEM;
2485
55489b6e 2486 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2487 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2488 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2489 cmd->short_slot = short_slot_time;
a66098da
LB		 2490
2491 rc = mwl8k_post_cmd(hw, &cmd->header);
2492 kfree(cmd);
2493
2494 return rc;
2495}
2496
2497/*
2498 * CMD_SET_EDCA_PARAMS.
2499 */
2500struct mwl8k_cmd_set_edca_params {
2501 struct mwl8k_cmd_pkt header;
2502
2503 /* See MWL8K_SET_EDCA_XXX below */
2504 __le16 action;
2505
2506 /* TX opportunity in units of 32 us */
2507 __le16 txop;
2508
2e484c89
LB		 2509 union {
2510 struct {
2511 /* Log exponent of max contention period: 0...15 */
2512 __le32 log_cw_max;
2513
2514 /* Log exponent of min contention period: 0...15 */
2515 __le32 log_cw_min;
2516
2517 /* Adaptive interframe spacing in units of 32us */
2518 __u8 aifs;
2519
2520 /* TX queue to configure */
2521 __u8 txq;
2522 } ap;
2523 struct {
2524 /* Log exponent of max contention period: 0...15 */
2525 __u8 log_cw_max;
a66098da 2526
2e484c89
LB		 2527 /* Log exponent of min contention period: 0...15 */
2528 __u8 log_cw_min;
a66098da 2529
2e484c89
LB		 2530 /* Adaptive interframe spacing in units of 32us */
2531 __u8 aifs;
a66098da 2532
2e484c89
LB		 2533 /* TX queue to configure */
2534 __u8 txq;
2535 } sta;
2536 };
ba2d3587 2537} __packed;
a66098da 2538
a66098da
LB		 2539#define MWL8K_SET_EDCA_CW 0x01
2540#define MWL8K_SET_EDCA_TXOP 0x02
2541#define MWL8K_SET_EDCA_AIFS 0x04
2542
2543#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2544 MWL8K_SET_EDCA_TXOP | \
2545 MWL8K_SET_EDCA_AIFS)
2546
2547static int
55489b6e
LB		 2548mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2549 __u16 cw_min, __u16 cw_max,
2550 __u8 aifs, __u16 txop)
a66098da 2551{
2e484c89 2552 struct mwl8k_priv *priv = hw->priv;
a66098da 2553 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2554 int rc;
2555
2556 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2557 if (cmd == NULL)
2558 return -ENOMEM;
2559
a66098da
LB		 2560 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2561 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2562 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2563 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2564 if (priv->ap_fw) {
2565 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2566 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2567 cmd->ap.aifs = aifs;
2568 cmd->ap.txq = qnum;
2569 } else {
2570 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2571 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2572 cmd->sta.aifs = aifs;
2573 cmd->sta.txq = qnum;
2574 }
a66098da
LB		 2575
2576 rc = mwl8k_post_cmd(hw, &cmd->header);
2577 kfree(cmd);
2578
2579 return rc;
2580}
2581
2582/*
55489b6e 2583 * CMD_SET_WMM_MODE.
a66098da 2584 */
55489b6e 2585struct mwl8k_cmd_set_wmm_mode {
a66098da 2586 struct mwl8k_cmd_pkt header;
55489b6e 2587 __le16 action;
ba2d3587 2588} __packed;
a66098da 2589
55489b6e 2590static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2591{
55489b6e
LB		 2592 struct mwl8k_priv *priv = hw->priv;
2593 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2594 int rc;
2595
a66098da
LB		 2596 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2597 if (cmd == NULL)
2598 return -ENOMEM;
2599
55489b6e 2600 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2601 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2602 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2603
2604 rc = mwl8k_post_cmd(hw, &cmd->header);
2605 kfree(cmd);
16cec43d 2606
55489b6e
LB		 2607 if (!rc)
2608 priv->wmm_enabled = enable;
a66098da
LB		 2609
2610 return rc;
2611}
2612
2613/*
55489b6e 2614 * CMD_MIMO_CONFIG.
a66098da 2615 */
55489b6e
LB		 2616struct mwl8k_cmd_mimo_config {
2617 struct mwl8k_cmd_pkt header;
2618 __le32 action;
2619 __u8 rx_antenna_map;
2620 __u8 tx_antenna_map;
ba2d3587 2621} __packed;
a66098da 2622
55489b6e 2623static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2624{
55489b6e 2625 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2626 int rc;
2627
2628 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2629 if (cmd == NULL)
2630 return -ENOMEM;
2631
55489b6e 2632 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2633 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2634 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2635 cmd->rx_antenna_map = rx;
2636 cmd->tx_antenna_map = tx;
a66098da
LB		 2637
2638 rc = mwl8k_post_cmd(hw, &cmd->header);
2639 kfree(cmd);
2640
2641 return rc;
2642}
2643
2644/*
b71ed2c6 2645 * CMD_USE_FIXED_RATE (STA version).
a66098da 2646 */
b71ed2c6
LB		 2647struct mwl8k_cmd_use_fixed_rate_sta {
2648 struct mwl8k_cmd_pkt header;
2649 __le32 action;
2650 __le32 allow_rate_drop;
2651 __le32 num_rates;
2652 struct {
2653 __le32 is_ht_rate;
2654 __le32 enable_retry;
2655 __le32 rate;
2656 __le32 retry_count;
2657 } rate_entry[8];
2658 __le32 rate_type;
2659 __le32 reserved1;
2660 __le32 reserved2;
ba2d3587 2661} __packed;
a66098da 2662
b71ed2c6
LB		 2663#define MWL8K_USE_AUTO_RATE 0x0002
2664#define MWL8K_UCAST_RATE 0
a66098da 2665
b71ed2c6 2666static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2667{
b71ed2c6 2668 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 2669 int rc;
2670
2671 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2672 if (cmd == NULL)
2673 return -ENOMEM;
2674
2675 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2676 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 2677 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2678 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 2679
2680 rc = mwl8k_post_cmd(hw, &cmd->header);
2681 kfree(cmd);
2682
2683 return rc;
2684}
2685
088aab8b
LB		 2686/*
2687 * CMD_USE_FIXED_RATE (AP version).
2688 */
2689struct mwl8k_cmd_use_fixed_rate_ap {
2690 struct mwl8k_cmd_pkt header;
2691 __le32 action;
2692 __le32 allow_rate_drop;
2693 __le32 num_rates;
2694 struct mwl8k_rate_entry_ap {
2695 __le32 is_ht_rate;
2696 __le32 enable_retry;
2697 __le32 rate;
2698 __le32 retry_count;
2699 } rate_entry[4];
2700 u8 multicast_rate;
2701 u8 multicast_rate_type;
2702 u8 management_rate;
ba2d3587 2703} __packed;
088aab8b
LB		 2704
2705static int
2706mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2707{
2708 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2709 int rc;
2710
2711 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2712 if (cmd == NULL)
2713 return -ENOMEM;
2714
2715 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2716 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2717 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2718 cmd->multicast_rate = mcast;
2719 cmd->management_rate = mgmt;
2720
2721 rc = mwl8k_post_cmd(hw, &cmd->header);
2722 kfree(cmd);
2723
2724 return rc;
2725}
2726
55489b6e
LB		 2727/*
2728 * CMD_ENABLE_SNIFFER.
2729 */
2730struct mwl8k_cmd_enable_sniffer {
2731 struct mwl8k_cmd_pkt header;
2732 __le32 action;
ba2d3587 2733} __packed;
55489b6e
LB		 2734
2735static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2736{
2737 struct mwl8k_cmd_enable_sniffer *cmd;
2738 int rc;
2739
2740 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2741 if (cmd == NULL)
2742 return -ENOMEM;
2743
2744 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2745 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2746 cmd->action = cpu_to_le32(!!enable);
2747
2748 rc = mwl8k_post_cmd(hw, &cmd->header);
2749 kfree(cmd);
2750
2751 return rc;
2752}
2753
2754/*
2755 * CMD_SET_MAC_ADDR.
2756 */
2757struct mwl8k_cmd_set_mac_addr {
2758 struct mwl8k_cmd_pkt header;
2759 union {
2760 struct {
2761 __le16 mac_type;
2762 __u8 mac_addr[ETH_ALEN];
2763 } mbss;
2764 __u8 mac_addr[ETH_ALEN];
2765 };
ba2d3587 2766} __packed;
55489b6e 2767
ee0ddf18
LB		 2768#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
2769#define MWL8K_MAC_TYPE_SECONDARY_CLIENT 1
2770#define MWL8K_MAC_TYPE_PRIMARY_AP 2
2771#define MWL8K_MAC_TYPE_SECONDARY_AP 3
a9e00b15 2772
aa21d0f6
LB		 2773static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw,
2774 struct ieee80211_vif *vif, u8 *mac)
55489b6e
LB		 2775{
2776 struct mwl8k_priv *priv = hw->priv;
ee0ddf18 2777 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
55489b6e 2778 struct mwl8k_cmd_set_mac_addr *cmd;
ee0ddf18 2779 int mac_type;
55489b6e
LB		 2780 int rc;
2781
ee0ddf18
LB		 2782 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
2783 if (vif != NULL && vif->type == NL80211_IFTYPE_STATION) {
2784 if (mwl8k_vif->macid + 1 == ffs(priv->sta_macids_supported))
2785 mac_type = MWL8K_MAC_TYPE_PRIMARY_CLIENT;
2786 else
2787 mac_type = MWL8K_MAC_TYPE_SECONDARY_CLIENT;
2788 } else if (vif != NULL && vif->type == NL80211_IFTYPE_AP) {
2789 if (mwl8k_vif->macid + 1 == ffs(priv->ap_macids_supported))
2790 mac_type = MWL8K_MAC_TYPE_PRIMARY_AP;
2791 else
2792 mac_type = MWL8K_MAC_TYPE_SECONDARY_AP;
2793 }
2794
55489b6e
LB		 2795 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2796 if (cmd == NULL)
2797 return -ENOMEM;
2798
2799 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2800 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2801 if (priv->ap_fw) {
ee0ddf18 2802 cmd->mbss.mac_type = cpu_to_le16(mac_type);
55489b6e
LB		 2803 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2804 } else {
2805 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2806 }
2807
aa21d0f6 2808 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
55489b6e
LB		 2809 kfree(cmd);
2810
2811 return rc;
2812}
2813
2814/*
2815 * CMD_SET_RATEADAPT_MODE.
2816 */
2817struct mwl8k_cmd_set_rate_adapt_mode {
2818 struct mwl8k_cmd_pkt header;
2819 __le16 action;
2820 __le16 mode;
ba2d3587 2821} __packed;
55489b6e
LB		 2822
2823static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2824{
2825 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2826 int rc;
2827
2828 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2829 if (cmd == NULL)
2830 return -ENOMEM;
2831
2832 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2833 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2834 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2835 cmd->mode = cpu_to_le16(mode);
2836
2837 rc = mwl8k_post_cmd(hw, &cmd->header);
2838 kfree(cmd);
2839
2840 return rc;
2841}
2842
b64fe619
LB		 2843/*
2844 * CMD_BSS_START.
2845 */
2846struct mwl8k_cmd_bss_start {
2847 struct mwl8k_cmd_pkt header;
2848 __le32 enable;
ba2d3587 2849} __packed;
b64fe619 2850
aa21d0f6
LB		 2851static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw,
2852 struct ieee80211_vif *vif, int enable)
b64fe619
LB		 2853{
2854 struct mwl8k_cmd_bss_start *cmd;
2855 int rc;
2856
2857 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2858 if (cmd == NULL)
2859 return -ENOMEM;
2860
2861 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
2862 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2863 cmd->enable = cpu_to_le32(enable);
2864
aa21d0f6 2865 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2866 kfree(cmd);
2867
2868 return rc;
2869}
2870
3f5610ff
LB		 2871/*
2872 * CMD_SET_NEW_STN.
2873 */
2874struct mwl8k_cmd_set_new_stn {
2875 struct mwl8k_cmd_pkt header;
2876 __le16 aid;
2877 __u8 mac_addr[6];
2878 __le16 stn_id;
2879 __le16 action;
2880 __le16 rsvd;
2881 __le32 legacy_rates;
2882 __u8 ht_rates[4];
2883 __le16 cap_info;
2884 __le16 ht_capabilities_info;
2885 __u8 mac_ht_param_info;
2886 __u8 rev;
2887 __u8 control_channel;
2888 __u8 add_channel;
2889 __le16 op_mode;
2890 __le16 stbc;
2891 __u8 add_qos_info;
2892 __u8 is_qos_sta;
2893 __le32 fw_sta_ptr;
ba2d3587 2894} __packed;
3f5610ff
LB		 2895
2896#define MWL8K_STA_ACTION_ADD 0
2897#define MWL8K_STA_ACTION_REMOVE 2
2898
2899static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
2900 struct ieee80211_vif *vif,
2901 struct ieee80211_sta *sta)
2902{
2903 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 2904 u32 rates;
3f5610ff
LB		 2905 int rc;
2906
2907 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2908 if (cmd == NULL)
2909 return -ENOMEM;
2910
2911 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2912 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2913 cmd->aid = cpu_to_le16(sta->aid);
2914 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
2915 cmd->stn_id = cpu_to_le16(sta->aid);
2916 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 2917 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
2918 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
2919 else
2920 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
2921 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 2922 if (sta->ht_cap.ht_supported) {
2923 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
2924 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
2925 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
2926 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
2927 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
2928 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
2929 ((sta->ht_cap.ampdu_density & 7) << 2);
2930 cmd->is_qos_sta = 1;
2931 }
2932
aa21d0f6 2933 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 2934 kfree(cmd);
2935
2936 return rc;
2937}
2938
b64fe619
LB		 2939static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
2940 struct ieee80211_vif *vif)
2941{
2942 struct mwl8k_cmd_set_new_stn *cmd;
2943 int rc;
2944
2945 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2946 if (cmd == NULL)
2947 return -ENOMEM;
2948
2949 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2950 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2951 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
2952
aa21d0f6 2953 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
b64fe619
LB		 2954 kfree(cmd);
2955
2956 return rc;
2957}
2958
3f5610ff
LB		 2959static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
2960 struct ieee80211_vif *vif, u8 *addr)
2961{
2962 struct mwl8k_cmd_set_new_stn *cmd;
2963 int rc;
2964
2965 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2966 if (cmd == NULL)
2967 return -ENOMEM;
2968
2969 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2970 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2971 memcpy(cmd->mac_addr, addr, ETH_ALEN);
2972 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
2973
aa21d0f6 2974 rc = mwl8k_post_pervif_cmd(hw, vif, &cmd->header);
3f5610ff
LB		 2975 kfree(cmd);
2976
2977 return rc;
2978}
2979
55489b6e
LB		 2980/*
2981 * CMD_UPDATE_STADB.
2982 */
25d81b1e
LB		 2983struct ewc_ht_info {
2984 __le16 control1;
2985 __le16 control2;
2986 __le16 control3;
ba2d3587 2987} __packed;
25d81b1e
LB		 2988
2989struct peer_capability_info {
2990 /* Peer type - AP vs. STA. */
2991 __u8 peer_type;
2992
2993 /* Basic 802.11 capabilities from assoc resp. */
2994 __le16 basic_caps;
2995
2996 /* Set if peer supports 802.11n high throughput (HT). */
2997 __u8 ht_support;
2998
2999 /* Valid if HT is supported. */
3000 __le16 ht_caps;
3001 __u8 extended_ht_caps;
3002 struct ewc_ht_info ewc_info;
3003
3004 /* Legacy rate table. Intersection of our rates and peer rates. */
3005 __u8 legacy_rates[12];
3006
3007 /* HT rate table. Intersection of our rates and peer rates. */
3008 __u8 ht_rates[16];
3009 __u8 pad[16];
3010
3011 /* If set, interoperability mode, no proprietary extensions. */
3012 __u8 interop;
3013 __u8 pad2;
3014 __u8 station_id;
3015 __le16 amsdu_enabled;
ba2d3587 3016} __packed;
25d81b1e 3017
55489b6e
LB		 3018struct mwl8k_cmd_update_stadb {
3019 struct mwl8k_cmd_pkt header;
3020
3021 /* See STADB_ACTION_TYPE */
3022 __le32 action;
3023
3024 /* Peer MAC address */
3025 __u8 peer_addr[ETH_ALEN];
3026
3027 __le32 reserved;
3028
3029 /* Peer info - valid during add/update. */
3030 struct peer_capability_info peer_info;
ba2d3587 3031} __packed;
55489b6e 3032
a680400e
LB		 3033#define MWL8K_STA_DB_MODIFY_ENTRY 1
3034#define MWL8K_STA_DB_DEL_ENTRY 2
3035
3036/* Peer Entry flags - used to define the type of the peer node */
3037#define MWL8K_PEER_TYPE_ACCESSPOINT 2
3038
3039static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 3040 struct ieee80211_vif *vif,
13935e2c 3041 struct ieee80211_sta *sta)
55489b6e 3042{
55489b6e 3043 struct mwl8k_cmd_update_stadb *cmd;
a680400e 3044 struct peer_capability_info *p;
8707d026 3045 u32 rates;
55489b6e
LB		 3046 int rc;
3047
3048 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3049 if (cmd == NULL)
3050 return -ENOMEM;
3051
3052 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3053 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 3054 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 3055 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 3056
a680400e
LB		 3057 p = &cmd->peer_info;
3058 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
3059 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c 3060 p->ht_support = sta->ht_cap.ht_supported;
b603742f 3061 p->ht_caps = cpu_to_le16(sta->ht_cap.cap);
13935e2c
LB		 3062 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
3063 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 3064 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3065 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3066 else
3067 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3068 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 3069 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 3070 p->interop = 1;
3071 p->amsdu_enabled = 0;
3072
3073 rc = mwl8k_post_cmd(hw, &cmd->header);
3074 kfree(cmd);
3075
3076 return rc ? rc : p->station_id;
3077}
3078
3079static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
3080 struct ieee80211_vif *vif, u8 *addr)
3081{
3082 struct mwl8k_cmd_update_stadb *cmd;
3083 int rc;
3084
3085 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3086 if (cmd == NULL)
3087 return -ENOMEM;
3088
3089 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3090 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3091 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 3092 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 3093
a680400e 3094 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 3095 kfree(cmd);
3096
3097 return rc;
3098}
3099
a66098da
LB		 3100
3101/*
3102 * Interrupt handling.
3103 */
3104static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
3105{
3106 struct ieee80211_hw *hw = dev_id;
3107 struct mwl8k_priv *priv = hw->priv;
3108 u32 status;
3109
3110 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 3111 if (!status)
3112 return IRQ_NONE;
3113
1e9f9de3
LB		 3114 if (status & MWL8K_A2H_INT_TX_DONE) {
3115 status &= ~MWL8K_A2H_INT_TX_DONE;
3116 tasklet_schedule(&priv->poll_tx_task);
3117 }
3118
a66098da 3119 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 3120 status &= ~MWL8K_A2H_INT_RX_READY;
3121 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 3122 }
3123
67e2eb27
LB		 3124 if (status)
3125 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3126
a66098da 3127 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 3128 if (priv->hostcmd_wait != NULL)
a66098da 3129 complete(priv->hostcmd_wait);
a66098da
LB		 3130 }
3131
3132 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 3133 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 3134 priv->radio_on && priv->pending_tx_pkts)
618952a7 3135 mwl8k_tx_start(priv);
a66098da
LB		 3136 }
3137
3138 return IRQ_HANDLED;
3139}
3140
1e9f9de3
LB		 3141static void mwl8k_tx_poll(unsigned long data)
3142{
3143 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3144 struct mwl8k_priv *priv = hw->priv;
3145 int limit;
3146 int i;
3147
3148 limit = 32;
3149
3150 spin_lock_bh(&priv->tx_lock);
3151
3152 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3153 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3154
3155 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3156 complete(priv->tx_wait);
3157 priv->tx_wait = NULL;
3158 }
3159
3160 spin_unlock_bh(&priv->tx_lock);
3161
3162 if (limit) {
3163 writel(~MWL8K_A2H_INT_TX_DONE,
3164 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3165 } else {
3166 tasklet_schedule(&priv->poll_tx_task);
3167 }
3168}
3169
67e2eb27
LB		 3170static void mwl8k_rx_poll(unsigned long data)
3171{
3172 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3173 struct mwl8k_priv *priv = hw->priv;
3174 int limit;
3175
3176 limit = 32;
3177 limit -= rxq_process(hw, 0, limit);
3178 limit -= rxq_refill(hw, 0, limit);
3179
3180 if (limit) {
3181 writel(~MWL8K_A2H_INT_RX_READY,
3182 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3183 } else {
3184 tasklet_schedule(&priv->poll_rx_task);
3185 }
3186}
3187
a66098da
LB		 3188
3189/*
3190 * Core driver operations.
3191 */
3192static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3193{
3194 struct mwl8k_priv *priv = hw->priv;
3195 int index = skb_get_queue_mapping(skb);
3196 int rc;
3197
9189c100 3198 if (!priv->radio_on) {
c96c31e4
JP		 3199 wiphy_debug(hw->wiphy,
3200 "dropped TX frame since radio disabled\n");
a66098da
LB		 3201 dev_kfree_skb(skb);
3202 return NETDEV_TX_OK;
3203 }
3204
3205 rc = mwl8k_txq_xmit(hw, index, skb);
3206
3207 return rc;
3208}
3209
a66098da
LB		 3210static int mwl8k_start(struct ieee80211_hw *hw)
3211{
a66098da
LB		 3212 struct mwl8k_priv *priv = hw->priv;
3213 int rc;
3214
a0607fd3 3215 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3216 IRQF_SHARED, MWL8K_NAME, hw);
3217 if (rc) {
5db55844 3218 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
2ec610cb 3219 return -EIO;
a66098da
LB		 3220 }
3221
67e2eb27 3222 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3223 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3224 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3225
a66098da 3226 /* Enable interrupts */
c23b5a69 3227 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3228
2ec610cb
LB		 3229 rc = mwl8k_fw_lock(hw);
3230 if (!rc) {
55489b6e 3231 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3232
5e4cf166
LB		 3233 if (!priv->ap_fw) {
3234 if (!rc)
55489b6e 3235 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3236
5e4cf166
LB		 3237 if (!rc)
3238 rc = mwl8k_cmd_set_pre_scan(hw);
3239
3240 if (!rc)
3241 rc = mwl8k_cmd_set_post_scan(hw,
3242 "\x00\x00\x00\x00\x00\x00");
3243 }
2ec610cb
LB		 3244
3245 if (!rc)
55489b6e 3246 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3247
2ec610cb 3248 if (!rc)
55489b6e 3249 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3250
2ec610cb
LB		 3251 mwl8k_fw_unlock(hw);
3252 }
3253
3254 if (rc) {
3255 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3256 free_irq(priv->pdev->irq, hw);
1e9f9de3 3257 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3258 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3259 }
a66098da
LB		 3260
3261 return rc;
3262}
3263
a66098da
LB		 3264static void mwl8k_stop(struct ieee80211_hw *hw)
3265{
a66098da
LB		 3266 struct mwl8k_priv *priv = hw->priv;
3267 int i;
3268
55489b6e 3269 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 3270
3271 ieee80211_stop_queues(hw);
3272
a66098da 3273 /* Disable interrupts */
a66098da 3274 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3275 free_irq(priv->pdev->irq, hw);
3276
3277 /* Stop finalize join worker */
3278 cancel_work_sync(&priv->finalize_join_worker);
3279 if (priv->beacon_skb != NULL)
3280 dev_kfree_skb(priv->beacon_skb);
3281
67e2eb27 3282 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3283 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3284 tasklet_disable(&priv->poll_rx_task);
a66098da 3285
a66098da
LB		 3286 /* Return all skbs to mac80211 */
3287 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3288 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 3289}
3290
3291static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 3292 struct ieee80211_vif *vif)
a66098da
LB		 3293{
3294 struct mwl8k_priv *priv = hw->priv;
3295 struct mwl8k_vif *mwl8k_vif;
ee0ddf18
LB		 3296 u32 macids_supported;
3297 int macid;
a66098da 3298
a43c49a8
LB		 3299 /*
3300 * Reject interface creation if sniffer mode is active, as
3301 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3302 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 3303 */
3304 if (priv->sniffer_enabled) {
c96c31e4
JP		 3305 wiphy_info(hw->wiphy,
3306 "unable to create STA interface because sniffer mode is enabled\n");
a43c49a8
LB		 3307 return -EINVAL;
3308 }
3309
ee0ddf18
LB		 3310
3311 switch (vif->type) {
3312 case NL80211_IFTYPE_AP:
3313 macids_supported = priv->ap_macids_supported;
3314 break;
3315 case NL80211_IFTYPE_STATION:
3316 macids_supported = priv->sta_macids_supported;
3317 break;
3318 default:
3319 return -EINVAL;
3320 }
3321
3322 macid = ffs(macids_supported & ~priv->macids_used);
3323 if (!macid--)
3324 return -EBUSY;
3325
f5bb87cf 3326 /* Setup driver private area. */
1ed32e4f 3327 mwl8k_vif = MWL8K_VIF(vif);
a66098da 3328 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 3329 mwl8k_vif->vif = vif;
ee0ddf18 3330 mwl8k_vif->macid = macid;
a66098da
LB		 3331 mwl8k_vif->seqno = 0;
3332
aa21d0f6
LB		 3333 /* Set the mac address. */
3334 mwl8k_cmd_set_mac_addr(hw, vif, vif->addr);
3335
3336 if (priv->ap_fw)
3337 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3338
ee0ddf18 3339 priv->macids_used |= 1 << mwl8k_vif->macid;
f5bb87cf 3340 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 3341
3342 return 0;
3343}
3344
3345static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3346 struct ieee80211_vif *vif)
a66098da
LB		 3347{
3348 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 3349 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 3350
b64fe619
LB		 3351 if (priv->ap_fw)
3352 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3353
aa21d0f6 3354 mwl8k_cmd_set_mac_addr(hw, vif, "\x00\x00\x00\x00\x00\x00");
32060e1b 3355
ee0ddf18 3356 priv->macids_used &= ~(1 << mwl8k_vif->macid);
f5bb87cf 3357 list_del(&mwl8k_vif->list);
a66098da
LB		 3358}
3359
ee03a932 3360static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3361{
a66098da
LB		 3362 struct ieee80211_conf *conf = &hw->conf;
3363 struct mwl8k_priv *priv = hw->priv;
ee03a932 3364 int rc;
a66098da 3365
7595d67a 3366 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3367 mwl8k_cmd_radio_disable(hw);
ee03a932 3368 return 0;
7595d67a
LB		 3369 }
3370
ee03a932
LB		 3371 rc = mwl8k_fw_lock(hw);
3372 if (rc)
3373 return rc;
a66098da 3374
55489b6e 3375 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 3376 if (rc)
3377 goto out;
a66098da 3378
610677d2 3379 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 3380 if (rc)
3381 goto out;
3382
a66098da
LB		 3383 if (conf->power_level > 18)
3384 conf->power_level = 18;
55489b6e 3385 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB		 3386 if (rc)
3387 goto out;
a66098da 3388
08b06347
LB		 3389 if (priv->ap_fw) {
3390 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3391 if (!rc)
3392 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3393 } else {
3394 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3395 }
a66098da 3396
ee03a932
LB		 3397out:
3398 mwl8k_fw_unlock(hw);
a66098da 3399
ee03a932 3400 return rc;
a66098da
LB		 3401}
3402
b64fe619
LB		 3403static void
3404mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3405 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3406{
a66098da 3407 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3408 u32 ap_legacy_rates;
13935e2c 3409 u8 ap_mcs_rates[16];
3a980d0a
LB		 3410 int rc;
3411
c3cbbe8a 3412 if (mwl8k_fw_lock(hw))
3a980d0a 3413 return;
a66098da 3414
c3cbbe8a
LB		 3415 /*
3416 * No need to capture a beacon if we're no longer associated.
3417 */
3418 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3419 priv->capture_beacon = false;
3a980d0a 3420
c3cbbe8a 3421 /*
13935e2c 3422 * Get the AP's legacy and MCS rates.
c3cbbe8a 3423 */
7dc6a7a7 3424 if (vif->bss_conf.assoc) {
c6e96010 3425 struct ieee80211_sta *ap;
c97470dd 3426
c6e96010 3427 rcu_read_lock();
c6e96010 3428
c3cbbe8a
LB		 3429 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3430 if (ap == NULL) {
3431 rcu_read_unlock();
c6e96010 3432 goto out;
c3cbbe8a
LB		 3433 }
3434
8707d026
LB		 3435 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
3436 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
3437 } else {
3438 ap_legacy_rates =
3439 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3440 }
13935e2c 3441 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 3442
3443 rcu_read_unlock();
3444 }
c6e96010 3445
c3cbbe8a 3446 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3447 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 3448 if (rc)
3449 goto out;
a66098da 3450
b71ed2c6 3451 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 3452 if (rc)
3453 goto out;
c3cbbe8a 3454 }
a66098da 3455
c3cbbe8a 3456 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 3457 rc = mwl8k_set_radio_preamble(hw,
3458 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 3459 if (rc)
3460 goto out;
c3cbbe8a 3461 }
a66098da 3462
c3cbbe8a 3463 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3464 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 3465 if (rc)
3466 goto out;
c3cbbe8a 3467 }
a66098da 3468
c97470dd
LB		 3469 if (vif->bss_conf.assoc &&
3470 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
3471 BSS_CHANGED_HT))) {
c3cbbe8a 3472 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 3473 if (rc)
3474 goto out;
c3cbbe8a 3475 }
a66098da 3476
c3cbbe8a
LB		 3477 if (vif->bss_conf.assoc &&
3478 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 3479 /*
3480 * Finalize the join. Tell rx handler to process
3481 * next beacon from our BSSID.
3482 */
0a11dfc3 3483 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3484 priv->capture_beacon = true;
a66098da
LB		 3485 }
3486
3a980d0a
LB		 3487out:
3488 mwl8k_fw_unlock(hw);
a66098da
LB		 3489}
3490
b64fe619
LB		 3491static void
3492mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3493 struct ieee80211_bss_conf *info, u32 changed)
3494{
3495 int rc;
3496
3497 if (mwl8k_fw_lock(hw))
3498 return;
3499
3500 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3501 rc = mwl8k_set_radio_preamble(hw,
3502 vif->bss_conf.use_short_preamble);
3503 if (rc)
3504 goto out;
3505 }
3506
3507 if (changed & BSS_CHANGED_BASIC_RATES) {
3508 int idx;
3509 int rate;
3510
3511 /*
3512 * Use lowest supported basic rate for multicasts
3513 * and management frames (such as probe responses --
3514 * beacons will always go out at 1 Mb/s).
3515 */
3516 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 3517 if (idx)
3518 idx--;
3519
3520 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3521 rate = mwl8k_rates_24[idx].hw_value;
3522 else
3523 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 3524
3525 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3526 }
3527
3528 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3529 struct sk_buff *skb;
3530
3531 skb = ieee80211_beacon_get(hw, vif);
3532 if (skb != NULL) {
aa21d0f6 3533 mwl8k_cmd_set_beacon(hw, vif, skb->data, skb->len);
b64fe619
LB		 3534 kfree_skb(skb);
3535 }
3536 }
3537
3538 if (changed & BSS_CHANGED_BEACON_ENABLED)
aa21d0f6 3539 mwl8k_cmd_bss_start(hw, vif, info->enable_beacon);
b64fe619
LB		 3540
3541out:
3542 mwl8k_fw_unlock(hw);
3543}
3544
3545static void
3546mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3547 struct ieee80211_bss_conf *info, u32 changed)
3548{
3549 struct mwl8k_priv *priv = hw->priv;
3550
3551 if (!priv->ap_fw)
3552 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3553 else
3554 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3555}
3556
e81cd2d6 3557static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 3558 struct netdev_hw_addr_list *mc_list)
e81cd2d6
LB		 3559{
3560 struct mwl8k_cmd_pkt *cmd;
3561
447ced07
LB		 3562 /*
3563 * Synthesize and return a command packet that programs the
3564 * hardware multicast address filter. At this point we don't
3565 * know whether FIF_ALLMULTI is being requested, but if it is,
3566 * we'll end up throwing this packet away and creating a new
3567 * one in mwl8k_configure_filter().
3568 */
22bedad3 3569 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_list);
e81cd2d6
LB		 3570
3571 return (unsigned long)cmd;
3572}
3573
a43c49a8
LB		 3574static int
3575mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3576 unsigned int changed_flags,
3577 unsigned int *total_flags)
3578{
3579 struct mwl8k_priv *priv = hw->priv;
3580
3581 /*
3582 * Hardware sniffer mode is mutually exclusive with STA
3583 * operation, so refuse to enable sniffer mode if a STA
3584 * interface is active.
3585 */
f5bb87cf 3586 if (!list_empty(&priv->vif_list)) {
a43c49a8 3587 if (net_ratelimit())
c96c31e4
JP		 3588 wiphy_info(hw->wiphy,
3589 "not enabling sniffer mode because STA interface is active\n");
a43c49a8
LB		 3590 return 0;
3591 }
3592
3593 if (!priv->sniffer_enabled) {
55489b6e 3594 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3595 return 0;
3596 priv->sniffer_enabled = true;
3597 }
3598
3599 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3600 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3601 FIF_OTHER_BSS;
3602
3603 return 1;
3604}
3605
f5bb87cf
LB		 3606static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
3607{
3608 if (!list_empty(&priv->vif_list))
3609 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
3610
3611 return NULL;
3612}
3613
e6935ea1
LB		 3614static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3615 unsigned int changed_flags,
3616 unsigned int *total_flags,
3617 u64 multicast)
3618{
3619 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3620 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3621
c0adae2c
LB		 3622 /*
3623 * AP firmware doesn't allow fine-grained control over
3624 * the receive filter.
3625 */
3626 if (priv->ap_fw) {
3627 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3628 kfree(cmd);
3629 return;
3630 }
3631
a43c49a8
LB		 3632 /*
3633 * Enable hardware sniffer mode if FIF_CONTROL or
3634 * FIF_OTHER_BSS is requested.
3635 */
3636 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3637 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3638 kfree(cmd);
3639 return;
3640 }
a66098da 3641
e6935ea1 3642 /* Clear unsupported feature flags */
447ced07 3643 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3644
90852f7a
LB		 3645 if (mwl8k_fw_lock(hw)) {
3646 kfree(cmd);
e6935ea1 3647 return;
90852f7a 3648 }
a66098da 3649
a43c49a8 3650 if (priv->sniffer_enabled) {
55489b6e 3651 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3652 priv->sniffer_enabled = false;
3653 }
3654
e6935ea1 3655 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3656 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3657 /*
3658 * Disable the BSS filter.
3659 */
e6935ea1 3660 mwl8k_cmd_set_pre_scan(hw);
77165d88 3661 } else {
f5bb87cf 3662 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 3663 const u8 *bssid;
a94cc97e 3664
77165d88
LB		 3665 /*
3666 * Enable the BSS filter.
3667 *
3668 * If there is an active STA interface, use that
3669 * interface's BSSID, otherwise use a dummy one
3670 * (where the OUI part needs to be nonzero for
3671 * the BSSID to be accepted by POST_SCAN).
3672 */
f5bb87cf
LB		 3673 mwl8k_vif = mwl8k_first_vif(priv);
3674 if (mwl8k_vif != NULL)
3675 bssid = mwl8k_vif->vif->bss_conf.bssid;
3676 else
3677 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3678
e6935ea1 3679 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3680 }
3681 }
3682
447ced07
LB		 3683 /*
3684 * If FIF_ALLMULTI is being requested, throw away the command
3685 * packet that ->prepare_multicast() built and replace it with
3686 * a command packet that enables reception of all multicast
3687 * packets.
3688 */
3689 if (*total_flags & FIF_ALLMULTI) {
3690 kfree(cmd);
22bedad3 3691 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, NULL);
447ced07
LB		 3692 }
3693
3694 if (cmd != NULL) {
3695 mwl8k_post_cmd(hw, cmd);
3696 kfree(cmd);
e6935ea1 3697 }
a66098da 3698
e6935ea1 3699 mwl8k_fw_unlock(hw);
a66098da
LB		 3700}
3701
a66098da
LB		 3702static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3703{
c2c2b12a 3704 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 3705}
3706
4a6967b8
JB		 3707static int mwl8k_sta_remove(struct ieee80211_hw *hw,
3708 struct ieee80211_vif *vif,
3709 struct ieee80211_sta *sta)
3f5610ff
LB		 3710{
3711 struct mwl8k_priv *priv = hw->priv;
3712
4a6967b8
JB		 3713 if (priv->ap_fw)
3714 return mwl8k_cmd_set_new_stn_del(hw, vif, sta->addr);
3715 else
3716 return mwl8k_cmd_update_stadb_del(hw, vif, sta->addr);
bbfd9128
LB		 3717}
3718
4a6967b8
JB		 3719static int mwl8k_sta_add(struct ieee80211_hw *hw,
3720 struct ieee80211_vif *vif,
3721 struct ieee80211_sta *sta)
bbfd9128
LB		 3722{
3723 struct mwl8k_priv *priv = hw->priv;
4a6967b8 3724 int ret;
bbfd9128 3725
4a6967b8
JB		 3726 if (!priv->ap_fw) {
3727 ret = mwl8k_cmd_update_stadb_add(hw, vif, sta);
3728 if (ret >= 0) {
3729 MWL8K_STA(sta)->peer_id = ret;
3730 return 0;
3731 }
bbfd9128 3732
4a6967b8 3733 return ret;
bbfd9128 3734 }
4a6967b8
JB		 3735
3736 return mwl8k_cmd_set_new_stn_add(hw, vif, sta);
bbfd9128
LB		 3737}
3738
a66098da
LB		 3739static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3740 const struct ieee80211_tx_queue_params *params)
3741{
3e4f542c 3742 struct mwl8k_priv *priv = hw->priv;
a66098da 3743 int rc;
a66098da 3744
3e4f542c
LB		 3745 rc = mwl8k_fw_lock(hw);
3746 if (!rc) {
3747 if (!priv->wmm_enabled)
55489b6e 3748 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3749
3e4f542c 3750 if (!rc)
55489b6e
LB		 3751 rc = mwl8k_cmd_set_edca_params(hw, queue,
3752 params->cw_min,
3753 params->cw_max,
3754 params->aifs,
3755 params->txop);
3e4f542c
LB		 3756
3757 mwl8k_fw_unlock(hw);
a66098da 3758 }
3e4f542c 3759
a66098da
LB		 3760 return rc;
3761}
3762
a66098da
LB		 3763static int mwl8k_get_stats(struct ieee80211_hw *hw,
3764 struct ieee80211_low_level_stats *stats)
3765{
55489b6e 3766 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 3767}
3768
0d462bbb
JL		 3769static int mwl8k_get_survey(struct ieee80211_hw *hw, int idx,
3770 struct survey_info *survey)
3771{
3772 struct mwl8k_priv *priv = hw->priv;
3773 struct ieee80211_conf *conf = &hw->conf;
3774
3775 if (idx != 0)
3776 return -ENOENT;
3777
3778 survey->channel = conf->channel;
3779 survey->filled = SURVEY_INFO_NOISE_DBM;
3780 survey->noise = priv->noise;
3781
3782 return 0;
3783}
3784
a2292d83
LB		 3785static int
3786mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3787 enum ieee80211_ampdu_mlme_action action,
3788 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3789{
3790 switch (action) {
3791 case IEEE80211_AMPDU_RX_START:
3792 case IEEE80211_AMPDU_RX_STOP:
3793 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
3794 return -ENOTSUPP;
3795 return 0;
3796 default:
3797 return -ENOTSUPP;
3798 }
3799}
3800
a66098da
LB		 3801static const struct ieee80211_ops mwl8k_ops = {
3802 .tx = mwl8k_tx,
3803 .start = mwl8k_start,
3804 .stop = mwl8k_stop,
3805 .add_interface = mwl8k_add_interface,
3806 .remove_interface = mwl8k_remove_interface,
3807 .config = mwl8k_config,
a66098da 3808 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3809 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3810 .configure_filter = mwl8k_configure_filter,
3811 .set_rts_threshold = mwl8k_set_rts_threshold,
4a6967b8
JB		 3812 .sta_add = mwl8k_sta_add,
3813 .sta_remove = mwl8k_sta_remove,
a66098da 3814 .conf_tx = mwl8k_conf_tx,
a66098da 3815 .get_stats = mwl8k_get_stats,
0d462bbb 3816 .get_survey = mwl8k_get_survey,
a2292d83 3817 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 3818};
3819
a66098da
LB		 3820static void mwl8k_finalize_join_worker(struct work_struct *work)
3821{
3822 struct mwl8k_priv *priv =
3823 container_of(work, struct mwl8k_priv, finalize_join_worker);
3824 struct sk_buff *skb = priv->beacon_skb;
56007a02
JB		 3825 struct ieee80211_mgmt *mgmt = (void *)skb->data;
3826 int len = skb->len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
3827 const u8 *tim = cfg80211_find_ie(WLAN_EID_TIM,
3828 mgmt->u.beacon.variable, len);
3829 int dtim_period = 1;
3830
3831 if (tim && tim[1] >= 2)
3832 dtim_period = tim[3];
a66098da 3833
56007a02 3834 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len, dtim_period);
a66098da 3835
f5bb87cf 3836 dev_kfree_skb(skb);
a66098da
LB		 3837 priv->beacon_skb = NULL;
3838}
3839
bcb628d5 3840enum {
9e1b17ea
LB		 3841 MWL8363 = 0,
3842 MWL8687,
bcb628d5 3843 MWL8366,
6f6d1e9a
LB		 3844};
3845
bcb628d5 3846static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 3847 [MWL8363] = {
3848 .part_name = "88w8363",
3849 .helper_image = "mwl8k/helper_8363.fw",
3850 .fw_image = "mwl8k/fmimage_8363.fw",
3851 },
49eb691c 3852 [MWL8687] = {
bcb628d5
JL		 3853 .part_name = "88w8687",
3854 .helper_image = "mwl8k/helper_8687.fw",
3855 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3856 },
49eb691c 3857 [MWL8366] = {
bcb628d5
JL		 3858 .part_name = "88w8366",
3859 .helper_image = "mwl8k/helper_8366.fw",
3860 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3861 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3862 },
45a390dd
LB		 3863};
3864
c92d4ede
LB		 3865MODULE_FIRMWARE("mwl8k/helper_8363.fw");
3866MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
3867MODULE_FIRMWARE("mwl8k/helper_8687.fw");
3868MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
3869MODULE_FIRMWARE("mwl8k/helper_8366.fw");
3870MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
3871
45a390dd 3872static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
e5868ba1 3873 { PCI_VDEVICE(MARVELL, 0x2a0a), .driver_data = MWL8363, },
9e1b17ea
LB		 3874 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
3875 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 3876 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3877 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3878 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 3879 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 3880 { },
45a390dd
LB		 3881};
3882MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3883
a66098da
LB		 3884static int __devinit mwl8k_probe(struct pci_dev *pdev,
3885 const struct pci_device_id *id)
3886{
2aa7b01f 3887 static int printed_version = 0;
a66098da
LB		 3888 struct ieee80211_hw *hw;
3889 struct mwl8k_priv *priv;
a66098da
LB		 3890 int rc;
3891 int i;
2aa7b01f
LB		 3892
3893 if (!printed_version) {
3894 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3895 printed_version = 1;
3896 }
a66098da 3897
be695fc4 3898
a66098da
LB		 3899 rc = pci_enable_device(pdev);
3900 if (rc) {
3901 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3902 MWL8K_NAME);
3903 return rc;
3904 }
3905
3906 rc = pci_request_regions(pdev, MWL8K_NAME);
3907 if (rc) {
3908 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3909 MWL8K_NAME);
3db95e50 3910 goto err_disable_device;
a66098da
LB		 3911 }
3912
3913 pci_set_master(pdev);
3914
be695fc4 3915
a66098da
LB		 3916 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3917 if (hw == NULL) {
3918 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3919 rc = -ENOMEM;
3920 goto err_free_reg;
3921 }
3922
be695fc4
LB		 3923 SET_IEEE80211_DEV(hw, &pdev->dev);
3924 pci_set_drvdata(pdev, hw);
3925
a66098da
LB		 3926 priv = hw->priv;
3927 priv->hw = hw;
3928 priv->pdev = pdev;
bcb628d5 3929 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3930
a66098da 3931
5b9482dd
LB		 3932 priv->sram = pci_iomap(pdev, 0, 0x10000);
3933 if (priv->sram == NULL) {
5db55844 3934 wiphy_err(hw->wiphy, "Cannot map device SRAM\n");
a66098da
LB		 3935 goto err_iounmap;
3936 }
3937
5b9482dd
LB		 3938 /*
3939 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3940 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3941 */
3942 priv->regs = pci_iomap(pdev, 1, 0x10000);
3943 if (priv->regs == NULL) {
3944 priv->regs = pci_iomap(pdev, 2, 0x10000);
3945 if (priv->regs == NULL) {
5db55844 3946 wiphy_err(hw->wiphy, "Cannot map device registers\n");
5b9482dd
LB		 3947 goto err_iounmap;
3948 }
3949 }
3950
be695fc4
LB		 3951
3952 /* Reset firmware and hardware */
3953 mwl8k_hw_reset(priv);
3954
3955 /* Ask userland hotplug daemon for the device firmware */
3956 rc = mwl8k_request_firmware(priv);
3957 if (rc) {
5db55844 3958 wiphy_err(hw->wiphy, "Firmware files not found\n");
be695fc4
LB		 3959 goto err_stop_firmware;
3960 }
3961
3962 /* Load firmware into hardware */
3963 rc = mwl8k_load_firmware(hw);
3964 if (rc) {
5db55844 3965 wiphy_err(hw->wiphy, "Cannot start firmware\n");
be695fc4
LB		 3966 goto err_stop_firmware;
3967 }
3968
3969 /* Reclaim memory once firmware is successfully loaded */
3970 mwl8k_release_firmware(priv);
3971
3972
91942230 3973 if (priv->ap_fw) {
89a91f4f 3974 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230 3975 if (priv->rxd_ops == NULL) {
c96c31e4
JP		 3976 wiphy_err(hw->wiphy,
3977 "Driver does not have AP firmware image support for this hardware\n");
91942230
LB		 3978 goto err_stop_firmware;
3979 }
3980 } else {
89a91f4f 3981 priv->rxd_ops = &rxd_sta_ops;
91942230 3982 }
be695fc4
LB		 3983
3984 priv->sniffer_enabled = false;
3985 priv->wmm_enabled = false;
3986 priv->pending_tx_pkts = 0;
3987
3988
a66098da
LB		 3989 /*
3990 * Extra headroom is the size of the required DMA header
3991 * minus the size of the smallest 802.11 frame (CTS frame).
3992 */
3993 hw->extra_tx_headroom =
3994 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3995
3996 hw->channel_change_time = 10;
3997
3998 hw->queues = MWL8K_TX_QUEUES;
3999
f5c044e5
JL		 4000 /* Set rssi values to dBm */
4001 hw->flags |= IEEE80211_HW_SIGNAL_DBM;
a66098da 4002 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 4003 hw->sta_data_size = sizeof(struct mwl8k_sta);
f5bb87cf 4004
ee0ddf18 4005 priv->macids_used = 0;
f5bb87cf 4006 INIT_LIST_HEAD(&priv->vif_list);
a66098da
LB		 4007
4008 /* Set default radio state and preamble */
c46563b7 4009 priv->radio_on = 0;
68ce3884 4010 priv->radio_short_preamble = 0;
a66098da
LB		 4011
4012 /* Finalize join worker */
4013 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
4014
67e2eb27 4015 /* TX reclaim and RX tasklets. */
1e9f9de3
LB		 4016 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
4017 tasklet_disable(&priv->poll_tx_task);
67e2eb27
LB		 4018 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
4019 tasklet_disable(&priv->poll_rx_task);
a66098da 4020
a66098da
LB		 4021 /* Power management cookie */
4022 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
4023 if (priv->cookie == NULL)
be695fc4 4024 goto err_stop_firmware;
a66098da
LB		 4025
4026 rc = mwl8k_rxq_init(hw, 0);
4027 if (rc)
be695fc4 4028 goto err_free_cookie;
a66098da
LB		 4029 rxq_refill(hw, 0, INT_MAX);
4030
618952a7
LB		 4031 mutex_init(&priv->fw_mutex);
4032 priv->fw_mutex_owner = NULL;
4033 priv->fw_mutex_depth = 0;
618952a7
LB		 4034 priv->hostcmd_wait = NULL;
4035
a66098da
LB		 4036 spin_lock_init(&priv->tx_lock);
4037
88de754a
LB		 4038 priv->tx_wait = NULL;
4039
a66098da
LB		 4040 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
4041 rc = mwl8k_txq_init(hw, i);
4042 if (rc)
4043 goto err_free_queues;
4044 }
4045
4046 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 4047 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 4048 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 4049 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 4050 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4051
a0607fd3 4052 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4053 IRQF_SHARED, MWL8K_NAME, hw);
4054 if (rc) {
5db55844 4055 wiphy_err(hw->wiphy, "failed to register IRQ handler\n");
a66098da
LB		 4056 goto err_free_queues;
4057 }
4058
a66098da
LB		 4059 /*
4060 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 4061 * commands use interrupts and avoid polling. Disable
a66098da
LB		 4062 * interrupts when done.
4063 */
c23b5a69 4064 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4065
4066 /* Get config data, mac addrs etc */
42fba21d
LB		 4067 if (priv->ap_fw) {
4068 rc = mwl8k_cmd_get_hw_spec_ap(hw);
4069 if (!rc)
4070 rc = mwl8k_cmd_set_hw_spec(hw);
4071 } else {
4072 rc = mwl8k_cmd_get_hw_spec_sta(hw);
4073 }
a66098da 4074 if (rc) {
5db55844 4075 wiphy_err(hw->wiphy, "Cannot initialise firmware\n");
be695fc4 4076 goto err_free_irq;
a66098da
LB		 4077 }
4078
ee0ddf18
LB		 4079 hw->wiphy->interface_modes = 0;
4080 if (priv->ap_macids_supported)
4081 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
4082 if (priv->sta_macids_supported)
4083 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_STATION);
4084
4085
a66098da 4086 /* Turn radio off */
55489b6e 4087 rc = mwl8k_cmd_radio_disable(hw);
a66098da 4088 if (rc) {
5db55844 4089 wiphy_err(hw->wiphy, "Cannot disable\n");
be695fc4 4090 goto err_free_irq;
a66098da
LB		 4091 }
4092
32060e1b 4093 /* Clear MAC address */
aa21d0f6 4094 rc = mwl8k_cmd_set_mac_addr(hw, NULL, "\x00\x00\x00\x00\x00\x00");
32060e1b 4095 if (rc) {
5db55844 4096 wiphy_err(hw->wiphy, "Cannot clear MAC address\n");
be695fc4 4097 goto err_free_irq;
32060e1b
LB		 4098 }
4099
a66098da 4100 /* Disable interrupts */
a66098da 4101 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4102 free_irq(priv->pdev->irq, hw);
4103
4104 rc = ieee80211_register_hw(hw);
4105 if (rc) {
5db55844 4106 wiphy_err(hw->wiphy, "Cannot register device\n");
153458ff 4107 goto err_free_queues;
a66098da
LB		 4108 }
4109
c96c31e4
JP		 4110 wiphy_info(hw->wiphy, "%s v%d, %pm, %s firmware %u.%u.%u.%u\n",
4111 priv->device_info->part_name,
4112 priv->hw_rev, hw->wiphy->perm_addr,
4113 priv->ap_fw ? "AP" : "STA",
4114 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
4115 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 4116
4117 return 0;
4118
a66098da 4119err_free_irq:
a66098da 4120 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4121 free_irq(priv->pdev->irq, hw);
4122
4123err_free_queues:
4124 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4125 mwl8k_txq_deinit(hw, i);
4126 mwl8k_rxq_deinit(hw, 0);
4127
be695fc4 4128err_free_cookie:
a66098da
LB		 4129 if (priv->cookie != NULL)
4130 pci_free_consistent(priv->pdev, 4,
4131 priv->cookie, priv->cookie_dma);
4132
be695fc4
LB		 4133err_stop_firmware:
4134 mwl8k_hw_reset(priv);
4135 mwl8k_release_firmware(priv);
4136
4137err_iounmap:
a66098da
LB		 4138 if (priv->regs != NULL)
4139 pci_iounmap(pdev, priv->regs);
4140
5b9482dd
LB		 4141 if (priv->sram != NULL)
4142 pci_iounmap(pdev, priv->sram);
4143
a66098da
LB		 4144 pci_set_drvdata(pdev, NULL);
4145 ieee80211_free_hw(hw);
4146
4147err_free_reg:
4148 pci_release_regions(pdev);
3db95e50
LB		 4149
4150err_disable_device:
a66098da
LB		 4151 pci_disable_device(pdev);
4152
4153 return rc;
4154}
4155
230f7af0 4156static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 4157{
4158 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4159}
4160
230f7af0 4161static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 4162{
4163 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4164 struct mwl8k_priv *priv;
4165 int i;
4166
4167 if (hw == NULL)
4168 return;
4169 priv = hw->priv;
4170
4171 ieee80211_stop_queues(hw);
4172
60aa569f
LB		 4173 ieee80211_unregister_hw(hw);
4174
67e2eb27 4175 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4176 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4177 tasklet_kill(&priv->poll_rx_task);
a66098da 4178
a66098da
LB		 4179 /* Stop hardware */
4180 mwl8k_hw_reset(priv);
4181
4182 /* Return all skbs to mac80211 */
4183 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4184 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4185
a66098da
LB		 4186 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4187 mwl8k_txq_deinit(hw, i);
4188
4189 mwl8k_rxq_deinit(hw, 0);
4190
c2c357ce 4191 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 4192
4193 pci_iounmap(pdev, priv->regs);
5b9482dd 4194 pci_iounmap(pdev, priv->sram);
a66098da
LB		 4195 pci_set_drvdata(pdev, NULL);
4196 ieee80211_free_hw(hw);
4197 pci_release_regions(pdev);
4198 pci_disable_device(pdev);
4199}
4200
4201static struct pci_driver mwl8k_driver = {
4202 .name = MWL8K_NAME,
45a390dd 4203 .id_table = mwl8k_pci_id_table,
a66098da
LB		 4204 .probe = mwl8k_probe,
4205 .remove = __devexit_p(mwl8k_remove),
4206 .shutdown = __devexit_p(mwl8k_shutdown),
4207};
4208
4209static int __init mwl8k_init(void)
4210{
4211 return pci_register_driver(&mwl8k_driver);
4212}
4213
4214static void __exit mwl8k_exit(void)
4215{
4216 pci_unregister_driver(&mwl8k_driver);
4217}
4218
4219module_init(mwl8k_init);
4220module_exit(mwl8k_exit);
c2c357ce
LB		 4221
4222MODULE_DESCRIPTION(MWL8K_DESC);
4223MODULE_VERSION(MWL8K_VERSION);
4224MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4225MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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