mwl8k: don't call SET_AID if we're not associated
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
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2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
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6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
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16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
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31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
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33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
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36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
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39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
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47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
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51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
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58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
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68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
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80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
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83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
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87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
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89};
90
45a390dd 91struct mwl8k_device_info {
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92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
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96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
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100
101 /* hw receives here */
45eb400d 102 int head;
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103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
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109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
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113};
114
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115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
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118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
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122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
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126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
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132 struct mwl8k_device_info *device_info;
133
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134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
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138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
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141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
144
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145 /* firmware access */
146 struct mutex fw_mutex;
147 struct task_struct *fw_mutex_owner;
148 int fw_mutex_depth;
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149 struct completion *hostcmd_wait;
150
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151 /* lock held over TX and TX reap */
152 spinlock_t tx_lock;
a66098da 153
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154 /* TX quiesce completion, protected by fw_mutex and tx_lock */
155 struct completion *tx_wait;
156
a66098da 157 struct ieee80211_vif *vif;
a66098da 158
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159 /* power management status cookie from firmware */
160 u32 *cookie;
161 dma_addr_t cookie_dma;
162
163 u16 num_mcaddrs;
a66098da 164 u8 hw_rev;
2aa7b01f 165 u32 fw_rev;
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166
167 /*
168 * Running count of TX packets in flight, to avoid
169 * iterating over the transmit rings each time.
170 */
171 int pending_tx_pkts;
172
173 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
174 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
175
176 /* PHY parameters */
177 struct ieee80211_supported_band band;
178 struct ieee80211_channel channels[14];
140eb5e2 179 struct ieee80211_rate rates[14];
a66098da 180
c46563b7 181 bool radio_on;
68ce3884 182 bool radio_short_preamble;
a43c49a8 183 bool sniffer_enabled;
0439b1f5 184 bool wmm_enabled;
a66098da 185
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186 struct work_struct sta_notify_worker;
187 spinlock_t sta_notify_list_lock;
188 struct list_head sta_notify_list;
189
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190 /* XXX need to convert this to handle multiple interfaces */
191 bool capture_beacon;
d89173f2 192 u8 capture_bssid[ETH_ALEN];
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193 struct sk_buff *beacon_skb;
194
195 /*
196 * This FJ worker has to be global as it is scheduled from the
197 * RX handler. At this point we don't know which interface it
198 * belongs to until the list of bssids waiting to complete join
199 * is checked.
200 */
201 struct work_struct finalize_join_worker;
202
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203 /* Tasklet to perform TX reclaim. */
204 struct tasklet_struct poll_tx_task;
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205
206 /* Tasklet to perform RX. */
207 struct tasklet_struct poll_rx_task;
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208};
209
210/* Per interface specific private data */
211struct mwl8k_vif {
c2c2b12a 212 /* Non AMPDU sequence number assigned by driver. */
a680400e 213 u16 seqno;
a66098da 214};
a94cc97e 215#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 216
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217struct mwl8k_sta {
218 /* Index into station database. Returned by UPDATE_STADB. */
219 u8 peer_id;
220};
221#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
222
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223static const struct ieee80211_channel mwl8k_channels[] = {
224 { .center_freq = 2412, .hw_value = 1, },
225 { .center_freq = 2417, .hw_value = 2, },
226 { .center_freq = 2422, .hw_value = 3, },
227 { .center_freq = 2427, .hw_value = 4, },
228 { .center_freq = 2432, .hw_value = 5, },
229 { .center_freq = 2437, .hw_value = 6, },
230 { .center_freq = 2442, .hw_value = 7, },
231 { .center_freq = 2447, .hw_value = 8, },
232 { .center_freq = 2452, .hw_value = 9, },
233 { .center_freq = 2457, .hw_value = 10, },
234 { .center_freq = 2462, .hw_value = 11, },
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235 { .center_freq = 2467, .hw_value = 12, },
236 { .center_freq = 2472, .hw_value = 13, },
237 { .center_freq = 2484, .hw_value = 14, },
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238};
239
240static const struct ieee80211_rate mwl8k_rates[] = {
241 { .bitrate = 10, .hw_value = 2, },
242 { .bitrate = 20, .hw_value = 4, },
243 { .bitrate = 55, .hw_value = 11, },
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244 { .bitrate = 110, .hw_value = 22, },
245 { .bitrate = 220, .hw_value = 44, },
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246 { .bitrate = 60, .hw_value = 12, },
247 { .bitrate = 90, .hw_value = 18, },
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248 { .bitrate = 120, .hw_value = 24, },
249 { .bitrate = 180, .hw_value = 36, },
250 { .bitrate = 240, .hw_value = 48, },
251 { .bitrate = 360, .hw_value = 72, },
252 { .bitrate = 480, .hw_value = 96, },
253 { .bitrate = 540, .hw_value = 108, },
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254 { .bitrate = 720, .hw_value = 144, },
255};
256
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257/* Set or get info from Firmware */
258#define MWL8K_CMD_SET 0x0001
259#define MWL8K_CMD_GET 0x0000
260
261/* Firmware command codes */
262#define MWL8K_CMD_CODE_DNLD 0x0001
263#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 264#define MWL8K_CMD_SET_HW_SPEC 0x0004
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265#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
266#define MWL8K_CMD_GET_STAT 0x0014
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267#define MWL8K_CMD_RADIO_CONTROL 0x001c
268#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 269#define MWL8K_CMD_RF_ANTENNA 0x0020
b64fe619 270#define MWL8K_CMD_SET_BEACON 0x0100
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271#define MWL8K_CMD_SET_PRE_SCAN 0x0107
272#define MWL8K_CMD_SET_POST_SCAN 0x0108
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273#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
274#define MWL8K_CMD_SET_AID 0x010d
275#define MWL8K_CMD_SET_RATE 0x0110
276#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
277#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 278#define MWL8K_CMD_SET_SLOT 0x0114
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279#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
280#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 281#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 282#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 283#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 284#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 285#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
b64fe619 286#define MWL8K_CMD_BSS_START 0x1100
3f5610ff 287#define MWL8K_CMD_SET_NEW_STN 0x1111
ff45fc60 288#define MWL8K_CMD_UPDATE_STADB 0x1123
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289
290static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
291{
292#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
293 snprintf(buf, bufsize, "%s", #x);\
294 return buf;\
295 } while (0)
ce9e2e1b 296 switch (cmd & ~0x8000) {
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297 MWL8K_CMDNAME(CODE_DNLD);
298 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 299 MWL8K_CMDNAME(SET_HW_SPEC);
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300 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
301 MWL8K_CMDNAME(GET_STAT);
302 MWL8K_CMDNAME(RADIO_CONTROL);
303 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 304 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 305 MWL8K_CMDNAME(SET_BEACON);
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306 MWL8K_CMDNAME(SET_PRE_SCAN);
307 MWL8K_CMDNAME(SET_POST_SCAN);
308 MWL8K_CMDNAME(SET_RF_CHANNEL);
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309 MWL8K_CMDNAME(SET_AID);
310 MWL8K_CMDNAME(SET_RATE);
311 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
312 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 313 MWL8K_CMDNAME(SET_SLOT);
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314 MWL8K_CMDNAME(SET_EDCA_PARAMS);
315 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 316 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 317 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 318 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 319 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 320 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 321 MWL8K_CMDNAME(BSS_START);
3f5610ff 322 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 323 MWL8K_CMDNAME(UPDATE_STADB);
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324 default:
325 snprintf(buf, bufsize, "0x%x", cmd);
326 }
327#undef MWL8K_CMDNAME
328
329 return buf;
330}
331
332/* Hardware and firmware reset */
333static void mwl8k_hw_reset(struct mwl8k_priv *priv)
334{
335 iowrite32(MWL8K_H2A_INT_RESET,
336 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
337 iowrite32(MWL8K_H2A_INT_RESET,
338 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
339 msleep(20);
340}
341
342/* Release fw image */
343static void mwl8k_release_fw(struct firmware **fw)
344{
345 if (*fw == NULL)
346 return;
347 release_firmware(*fw);
348 *fw = NULL;
349}
350
351static void mwl8k_release_firmware(struct mwl8k_priv *priv)
352{
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353 mwl8k_release_fw(&priv->fw_ucode);
354 mwl8k_release_fw(&priv->fw_helper);
a66098da
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355}
356
357/* Request fw image */
358static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 359 const char *fname, struct firmware **fw)
a66098da
LB
360{
361 /* release current image */
362 if (*fw != NULL)
363 mwl8k_release_fw(fw);
364
365 return request_firmware((const struct firmware **)fw,
c2c357ce 366 fname, &priv->pdev->dev);
a66098da
LB
367}
368
45a390dd 369static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 370{
a74b295e 371 struct mwl8k_device_info *di = priv->device_info;
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LB
372 int rc;
373
a74b295e 374 if (di->helper_image != NULL) {
22be40d9 375 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
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376 if (rc) {
377 printk(KERN_ERR "%s: Error requesting helper "
378 "firmware file %s\n", pci_name(priv->pdev),
379 di->helper_image);
380 return rc;
381 }
a66098da
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382 }
383
22be40d9 384 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 385 if (rc) {
c2c357ce 386 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 387 pci_name(priv->pdev), di->fw_image);
22be40d9 388 mwl8k_release_fw(&priv->fw_helper);
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389 return rc;
390 }
391
392 return 0;
393}
394
395struct mwl8k_cmd_pkt {
396 __le16 code;
397 __le16 length;
398 __le16 seq_num;
399 __le16 result;
400 char payload[0];
401} __attribute__((packed));
402
403/*
404 * Firmware loading.
405 */
406static int
407mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
408{
409 void __iomem *regs = priv->regs;
410 dma_addr_t dma_addr;
a66098da
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411 int loops;
412
413 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
414 if (pci_dma_mapping_error(priv->pdev, dma_addr))
415 return -ENOMEM;
416
417 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
418 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
419 iowrite32(MWL8K_H2A_INT_DOORBELL,
420 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
421 iowrite32(MWL8K_H2A_INT_DUMMY,
422 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
423
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424 loops = 1000;
425 do {
426 u32 int_code;
427
428 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
429 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
430 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
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431 break;
432 }
433
3d76e82c 434 cond_resched();
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435 udelay(1);
436 } while (--loops);
437
438 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
439
d4b70570 440 return loops ? 0 : -ETIMEDOUT;
a66098da
LB
441}
442
443static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
444 const u8 *data, size_t length)
445{
446 struct mwl8k_cmd_pkt *cmd;
447 int done;
448 int rc = 0;
449
450 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
451 if (cmd == NULL)
452 return -ENOMEM;
453
454 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
455 cmd->seq_num = 0;
456 cmd->result = 0;
457
458 done = 0;
459 while (length) {
460 int block_size = length > 256 ? 256 : length;
461
462 memcpy(cmd->payload, data + done, block_size);
463 cmd->length = cpu_to_le16(block_size);
464
465 rc = mwl8k_send_fw_load_cmd(priv, cmd,
466 sizeof(*cmd) + block_size);
467 if (rc)
468 break;
469
470 done += block_size;
471 length -= block_size;
472 }
473
474 if (!rc) {
475 cmd->length = 0;
476 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
477 }
478
479 kfree(cmd);
480
481 return rc;
482}
483
484static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
485 const u8 *data, size_t length)
486{
487 unsigned char *buffer;
488 int may_continue, rc = 0;
489 u32 done, prev_block_size;
490
491 buffer = kmalloc(1024, GFP_KERNEL);
492 if (buffer == NULL)
493 return -ENOMEM;
494
495 done = 0;
496 prev_block_size = 0;
497 may_continue = 1000;
498 while (may_continue > 0) {
499 u32 block_size;
500
501 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
502 if (block_size & 1) {
503 block_size &= ~1;
504 may_continue--;
505 } else {
506 done += prev_block_size;
507 length -= prev_block_size;
508 }
509
510 if (block_size > 1024 || block_size > length) {
511 rc = -EOVERFLOW;
512 break;
513 }
514
515 if (length == 0) {
516 rc = 0;
517 break;
518 }
519
520 if (block_size == 0) {
521 rc = -EPROTO;
522 may_continue--;
523 udelay(1);
524 continue;
525 }
526
527 prev_block_size = block_size;
528 memcpy(buffer, data + done, block_size);
529
530 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
531 if (rc)
532 break;
533 }
534
535 if (!rc && length != 0)
536 rc = -EREMOTEIO;
537
538 kfree(buffer);
539
540 return rc;
541}
542
c2c357ce 543static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 544{
c2c357ce 545 struct mwl8k_priv *priv = hw->priv;
22be40d9 546 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB
547 int rc;
548 int loops;
549
550 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 551 struct firmware *helper = priv->fw_helper;
a66098da 552
c2c357ce
LB
553 if (helper == NULL) {
554 printk(KERN_ERR "%s: helper image needed but none "
555 "given\n", pci_name(priv->pdev));
556 return -EINVAL;
557 }
a66098da 558
c2c357ce 559 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB
560 if (rc) {
561 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 562 "helper image\n", pci_name(priv->pdev));
a66098da
LB
563 return rc;
564 }
89b872e2 565 msleep(5);
a66098da 566
c2c357ce 567 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 568 } else {
c2c357ce 569 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB
570 }
571
572 if (rc) {
c2c357ce
LB
573 printk(KERN_ERR "%s: unable to load firmware image\n",
574 pci_name(priv->pdev));
a66098da
LB
575 return rc;
576 }
577
89a91f4f 578 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 579
89b872e2 580 loops = 500000;
a66098da 581 do {
eae74e65
LB
582 u32 ready_code;
583
584 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
585 if (ready_code == MWL8K_FWAP_READY) {
586 priv->ap_fw = 1;
587 break;
588 } else if (ready_code == MWL8K_FWSTA_READY) {
589 priv->ap_fw = 0;
a66098da 590 break;
eae74e65
LB
591 }
592
593 cond_resched();
a66098da
LB
594 udelay(1);
595 } while (--loops);
596
597 return loops ? 0 : -ETIMEDOUT;
598}
599
600
a66098da
LB
601/* DMA header used by firmware and hardware. */
602struct mwl8k_dma_data {
603 __le16 fwlen;
604 struct ieee80211_hdr wh;
20f09c3d 605 char data[0];
a66098da
LB
606} __attribute__((packed));
607
608/* Routines to add/remove DMA header from skb. */
20f09c3d 609static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 610{
20f09c3d
LB
611 struct mwl8k_dma_data *tr;
612 int hdrlen;
613
614 tr = (struct mwl8k_dma_data *)skb->data;
615 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
616
617 if (hdrlen != sizeof(tr->wh)) {
618 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
619 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
620 *((__le16 *)(tr->data - 2)) = qos;
621 } else {
622 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
623 }
a66098da 624 }
20f09c3d
LB
625
626 if (hdrlen != sizeof(*tr))
627 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB
628}
629
76266b2a 630static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB
631{
632 struct ieee80211_hdr *wh;
ca009301 633 int hdrlen;
a66098da
LB
634 struct mwl8k_dma_data *tr;
635
ca009301
LB
636 /*
637 * Add a firmware DMA header; the firmware requires that we
638 * present a 2-byte payload length followed by a 4-address
639 * header (without QoS field), followed (optionally) by any
640 * WEP/ExtIV header (but only filled in for CCMP).
641 */
a66098da 642 wh = (struct ieee80211_hdr *)skb->data;
ca009301 643
a66098da 644 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB
645 if (hdrlen != sizeof(*tr))
646 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 647
ca009301
LB
648 if (ieee80211_is_data_qos(wh->frame_control))
649 hdrlen -= 2;
a66098da
LB
650
651 tr = (struct mwl8k_dma_data *)skb->data;
652 if (wh != &tr->wh)
653 memmove(&tr->wh, wh, hdrlen);
ca009301
LB
654 if (hdrlen != sizeof(tr->wh))
655 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB
656
657 /*
658 * Firmware length is the length of the fully formed "802.11
659 * payload". That is, everything except for the 802.11 header.
660 * This includes all crypto material including the MIC.
661 */
ca009301 662 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB
663}
664
665
666/*
89a91f4f 667 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 668 */
89a91f4f 669struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB
670 __le16 pkt_len;
671 __u8 sq2;
672 __u8 rate;
673 __le32 pkt_phys_addr;
674 __le32 next_rxd_phys_addr;
675 __le16 qos_control;
676 __le16 htsig2;
677 __le32 hw_rssi_info;
678 __le32 hw_noise_floor_info;
679 __u8 noise_floor;
680 __u8 pad0[3];
681 __u8 rssi;
682 __u8 rx_status;
683 __u8 channel;
684 __u8 rx_ctrl;
685} __attribute__((packed));
686
89a91f4f
LB
687#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
688#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
689#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 690
89a91f4f 691#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 692
89a91f4f 693static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 694{
89a91f4f 695 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB
696
697 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 698 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB
699}
700
89a91f4f 701static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 702{
89a91f4f 703 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB
704
705 rxd->pkt_len = cpu_to_le16(len);
706 rxd->pkt_phys_addr = cpu_to_le32(addr);
707 wmb();
708 rxd->rx_ctrl = 0;
709}
710
711static int
89a91f4f
LB
712mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
713 __le16 *qos)
6f6d1e9a 714{
89a91f4f 715 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 716
89a91f4f 717 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB
718 return -1;
719 rmb();
720
721 memset(status, 0, sizeof(*status));
722
723 status->signal = -rxd->rssi;
724 status->noise = -rxd->noise_floor;
725
89a91f4f 726 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 727 status->flag |= RX_FLAG_HT;
89a91f4f 728 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 729 status->flag |= RX_FLAG_40MHZ;
89a91f4f 730 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB
731 } else {
732 int i;
733
734 for (i = 0; i < ARRAY_SIZE(mwl8k_rates); i++) {
735 if (mwl8k_rates[i].hw_value == rxd->rate) {
736 status->rate_idx = i;
737 break;
738 }
739 }
740 }
741
742 status->band = IEEE80211_BAND_2GHZ;
743 status->freq = ieee80211_channel_to_frequency(rxd->channel);
744
20f09c3d
LB
745 *qos = rxd->qos_control;
746
6f6d1e9a
LB
747 return le16_to_cpu(rxd->pkt_len);
748}
749
89a91f4f
LB
750static struct rxd_ops rxd_8366_ap_ops = {
751 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
752 .rxd_init = mwl8k_rxd_8366_ap_init,
753 .rxd_refill = mwl8k_rxd_8366_ap_refill,
754 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB
755};
756
757/*
89a91f4f 758 * Packet reception for STA firmware.
a66098da 759 */
89a91f4f 760struct mwl8k_rxd_sta {
a66098da
LB
761 __le16 pkt_len;
762 __u8 link_quality;
763 __u8 noise_level;
764 __le32 pkt_phys_addr;
45eb400d 765 __le32 next_rxd_phys_addr;
a66098da
LB
766 __le16 qos_control;
767 __le16 rate_info;
768 __le32 pad0[4];
769 __u8 rssi;
770 __u8 channel;
771 __le16 pad1;
772 __u8 rx_ctrl;
773 __u8 rx_status;
774 __u8 pad2[2];
775} __attribute__((packed));
776
89a91f4f
LB
777#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
778#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
779#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
780#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
781#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
782#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 783
89a91f4f 784#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 785
89a91f4f 786static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 787{
89a91f4f 788 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
789
790 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 791 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB
792}
793
89a91f4f 794static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 795{
89a91f4f 796 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
797
798 rxd->pkt_len = cpu_to_le16(len);
799 rxd->pkt_phys_addr = cpu_to_le32(addr);
800 wmb();
801 rxd->rx_ctrl = 0;
802}
803
804static int
89a91f4f 805mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 806 __le16 *qos)
54bc3a0d 807{
89a91f4f 808 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB
809 u16 rate_info;
810
89a91f4f 811 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB
812 return -1;
813 rmb();
814
815 rate_info = le16_to_cpu(rxd->rate_info);
816
817 memset(status, 0, sizeof(*status));
818
819 status->signal = -rxd->rssi;
820 status->noise = -rxd->noise_level;
89a91f4f
LB
821 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
822 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 823
89a91f4f 824 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 825 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 826 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 827 status->flag |= RX_FLAG_40MHZ;
89a91f4f 828 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 829 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 830 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB
831 status->flag |= RX_FLAG_HT;
832
833 status->band = IEEE80211_BAND_2GHZ;
834 status->freq = ieee80211_channel_to_frequency(rxd->channel);
835
20f09c3d
LB
836 *qos = rxd->qos_control;
837
54bc3a0d
LB
838 return le16_to_cpu(rxd->pkt_len);
839}
840
89a91f4f
LB
841static struct rxd_ops rxd_sta_ops = {
842 .rxd_size = sizeof(struct mwl8k_rxd_sta),
843 .rxd_init = mwl8k_rxd_sta_init,
844 .rxd_refill = mwl8k_rxd_sta_refill,
845 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB
846};
847
848
a66098da
LB
849#define MWL8K_RX_DESCS 256
850#define MWL8K_RX_MAXSZ 3800
851
852static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
853{
854 struct mwl8k_priv *priv = hw->priv;
855 struct mwl8k_rx_queue *rxq = priv->rxq + index;
856 int size;
857 int i;
858
45eb400d
LB
859 rxq->rxd_count = 0;
860 rxq->head = 0;
861 rxq->tail = 0;
a66098da 862
54bc3a0d 863 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 864
45eb400d
LB
865 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
866 if (rxq->rxd == NULL) {
a66098da 867 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 868 wiphy_name(hw->wiphy));
a66098da
LB
869 return -ENOMEM;
870 }
45eb400d 871 memset(rxq->rxd, 0, size);
a66098da 872
788838eb
LB
873 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
874 if (rxq->buf == NULL) {
a66098da 875 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 876 wiphy_name(hw->wiphy));
45eb400d 877 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB
878 return -ENOMEM;
879 }
788838eb 880 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB
881
882 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB
883 int desc_size;
884 void *rxd;
a66098da 885 int nexti;
54bc3a0d
LB
886 dma_addr_t next_dma_addr;
887
888 desc_size = priv->rxd_ops->rxd_size;
889 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 890
54bc3a0d
LB
891 nexti = i + 1;
892 if (nexti == MWL8K_RX_DESCS)
893 nexti = 0;
894 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 895
54bc3a0d 896 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB
897 }
898
899 return 0;
900}
901
902static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
903{
904 struct mwl8k_priv *priv = hw->priv;
905 struct mwl8k_rx_queue *rxq = priv->rxq + index;
906 int refilled;
907
908 refilled = 0;
45eb400d 909 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 910 struct sk_buff *skb;
788838eb 911 dma_addr_t addr;
a66098da 912 int rx;
54bc3a0d 913 void *rxd;
a66098da
LB
914
915 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
916 if (skb == NULL)
917 break;
918
788838eb
LB
919 addr = pci_map_single(priv->pdev, skb->data,
920 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 921
54bc3a0d
LB
922 rxq->rxd_count++;
923 rx = rxq->tail++;
924 if (rxq->tail == MWL8K_RX_DESCS)
925 rxq->tail = 0;
788838eb
LB
926 rxq->buf[rx].skb = skb;
927 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB
928
929 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
930 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB
931
932 refilled++;
933 }
934
935 return refilled;
936}
937
938/* Must be called only when the card's reception is completely halted */
939static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
940{
941 struct mwl8k_priv *priv = hw->priv;
942 struct mwl8k_rx_queue *rxq = priv->rxq + index;
943 int i;
944
945 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB
946 if (rxq->buf[i].skb != NULL) {
947 pci_unmap_single(priv->pdev,
948 pci_unmap_addr(&rxq->buf[i], dma),
949 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
950 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
951
952 kfree_skb(rxq->buf[i].skb);
953 rxq->buf[i].skb = NULL;
a66098da
LB
954 }
955 }
956
788838eb
LB
957 kfree(rxq->buf);
958 rxq->buf = NULL;
a66098da
LB
959
960 pci_free_consistent(priv->pdev,
54bc3a0d 961 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB
962 rxq->rxd, rxq->rxd_dma);
963 rxq->rxd = NULL;
a66098da
LB
964}
965
966
967/*
968 * Scan a list of BSSIDs to process for finalize join.
969 * Allows for extension to process multiple BSSIDs.
970 */
971static inline int
972mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
973{
974 return priv->capture_beacon &&
975 ieee80211_is_beacon(wh->frame_control) &&
976 !compare_ether_addr(wh->addr3, priv->capture_bssid);
977}
978
3779752d
LB
979static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
980 struct sk_buff *skb)
a66098da 981{
3779752d
LB
982 struct mwl8k_priv *priv = hw->priv;
983
a66098da 984 priv->capture_beacon = false;
d89173f2 985 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB
986
987 /*
988 * Use GFP_ATOMIC as rxq_process is called from
989 * the primary interrupt handler, memory allocation call
990 * must not sleep.
991 */
992 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
993 if (priv->beacon_skb != NULL)
3779752d 994 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB
995}
996
997static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
998{
999 struct mwl8k_priv *priv = hw->priv;
1000 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1001 int processed;
1002
1003 processed = 0;
45eb400d 1004 while (rxq->rxd_count && limit--) {
a66098da 1005 struct sk_buff *skb;
54bc3a0d
LB
1006 void *rxd;
1007 int pkt_len;
a66098da 1008 struct ieee80211_rx_status status;
20f09c3d 1009 __le16 qos;
a66098da 1010
788838eb 1011 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB
1012 if (skb == NULL)
1013 break;
54bc3a0d
LB
1014
1015 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1016
20f09c3d 1017 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB
1018 if (pkt_len < 0)
1019 break;
1020
788838eb
LB
1021 rxq->buf[rxq->head].skb = NULL;
1022
1023 pci_unmap_single(priv->pdev,
1024 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1025 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1026 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1027
54bc3a0d
LB
1028 rxq->head++;
1029 if (rxq->head == MWL8K_RX_DESCS)
1030 rxq->head = 0;
1031
45eb400d 1032 rxq->rxd_count--;
a66098da 1033
54bc3a0d 1034 skb_put(skb, pkt_len);
20f09c3d 1035 mwl8k_remove_dma_header(skb, qos);
a66098da 1036
a66098da 1037 /*
c2c357ce
LB
1038 * Check for a pending join operation. Save a
1039 * copy of the beacon and schedule a tasklet to
1040 * send a FINALIZE_JOIN command to the firmware.
a66098da 1041 */
54bc3a0d 1042 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1043 mwl8k_save_beacon(hw, skb);
a66098da 1044
f1d58c25
JB
1045 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1046 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB
1047
1048 processed++;
1049 }
1050
1051 return processed;
1052}
1053
1054
1055/*
1056 * Packet transmission.
1057 */
1058
a66098da
LB
1059#define MWL8K_TXD_STATUS_OK 0x00000001
1060#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1061#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1062#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1063#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1064
e0493a8d
LB
1065#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1066#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1067#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1068#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1069#define MWL8K_QOS_EOSP 0x0010
1070
a66098da
LB
1071struct mwl8k_tx_desc {
1072 __le32 status;
1073 __u8 data_rate;
1074 __u8 tx_priority;
1075 __le16 qos_control;
1076 __le32 pkt_phys_addr;
1077 __le16 pkt_len;
d89173f2 1078 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1079 __le32 next_txd_phys_addr;
a66098da
LB
1080 __le32 reserved;
1081 __le16 rate_info;
1082 __u8 peer_id;
1083 __u8 tx_frag_cnt;
1084} __attribute__((packed));
1085
1086#define MWL8K_TX_DESCS 128
1087
1088static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1089{
1090 struct mwl8k_priv *priv = hw->priv;
1091 struct mwl8k_tx_queue *txq = priv->txq + index;
1092 int size;
1093 int i;
1094
45eb400d
LB
1095 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1096 txq->stats.limit = MWL8K_TX_DESCS;
1097 txq->head = 0;
1098 txq->tail = 0;
a66098da
LB
1099
1100 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1101
45eb400d
LB
1102 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1103 if (txq->txd == NULL) {
a66098da 1104 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1105 wiphy_name(hw->wiphy));
a66098da
LB
1106 return -ENOMEM;
1107 }
45eb400d 1108 memset(txq->txd, 0, size);
a66098da 1109
45eb400d
LB
1110 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1111 if (txq->skb == NULL) {
a66098da 1112 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1113 wiphy_name(hw->wiphy));
45eb400d 1114 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB
1115 return -ENOMEM;
1116 }
45eb400d 1117 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB
1118
1119 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1120 struct mwl8k_tx_desc *tx_desc;
1121 int nexti;
1122
45eb400d 1123 tx_desc = txq->txd + i;
a66098da
LB
1124 nexti = (i + 1) % MWL8K_TX_DESCS;
1125
1126 tx_desc->status = 0;
45eb400d
LB
1127 tx_desc->next_txd_phys_addr =
1128 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB
1129 }
1130
1131 return 0;
1132}
1133
1134static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1135{
1136 iowrite32(MWL8K_H2A_INT_PPA_READY,
1137 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1138 iowrite32(MWL8K_H2A_INT_DUMMY,
1139 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1140 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1141}
1142
7e1112d3 1143static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1144{
7e1112d3
LB
1145 struct mwl8k_priv *priv = hw->priv;
1146 int i;
1147
1148 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1149 struct mwl8k_tx_queue *txq = priv->txq + i;
1150 int fw_owned = 0;
1151 int drv_owned = 0;
1152 int unused = 0;
1153 int desc;
1154
a66098da 1155 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB
1156 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1157 u32 status;
a66098da 1158
7e1112d3 1159 status = le32_to_cpu(tx_desc->status);
a66098da 1160 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1161 fw_owned++;
a66098da 1162 else
7e1112d3 1163 drv_owned++;
a66098da
LB
1164
1165 if (tx_desc->pkt_len == 0)
7e1112d3 1166 unused++;
a66098da 1167 }
a66098da 1168
7e1112d3
LB
1169 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1170 "fw_owned=%d drv_owned=%d unused=%d\n",
1171 wiphy_name(hw->wiphy), i,
1172 txq->stats.len, txq->head, txq->tail,
1173 fw_owned, drv_owned, unused);
1174 }
a66098da
LB
1175}
1176
618952a7 1177/*
88de754a 1178 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1179 */
62abd3cf 1180#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1181
950d5b01 1182static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1183{
a66098da 1184 struct mwl8k_priv *priv = hw->priv;
88de754a 1185 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB
1186 int retry;
1187 int rc;
a66098da
LB
1188
1189 might_sleep();
1190
7e1112d3
LB
1191 /*
1192 * The TX queues are stopped at this point, so this test
1193 * doesn't need to take ->tx_lock.
1194 */
1195 if (!priv->pending_tx_pkts)
1196 return 0;
1197
1198 retry = 0;
1199 rc = 0;
1200
a66098da 1201 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB
1202 priv->tx_wait = &tx_wait;
1203 while (!rc) {
1204 int oldcount;
1205 unsigned long timeout;
a66098da 1206
7e1112d3 1207 oldcount = priv->pending_tx_pkts;
a66098da 1208
7e1112d3 1209 spin_unlock_bh(&priv->tx_lock);
88de754a 1210 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1211 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1212 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB
1213
1214 if (timeout) {
1215 WARN_ON(priv->pending_tx_pkts);
1216 if (retry) {
1217 printk(KERN_NOTICE "%s: tx rings drained\n",
1218 wiphy_name(hw->wiphy));
1219 }
1220 break;
1221 }
1222
1223 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB
1224 printk(KERN_NOTICE "%s: waiting for tx rings "
1225 "to drain (%d -> %d pkts)\n",
7e1112d3
LB
1226 wiphy_name(hw->wiphy), oldcount,
1227 priv->pending_tx_pkts);
1228 retry = 1;
1229 continue;
1230 }
1231
a66098da 1232 priv->tx_wait = NULL;
a66098da 1233
7e1112d3
LB
1234 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1235 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1236 mwl8k_dump_tx_rings(hw);
1237
1238 rc = -ETIMEDOUT;
a66098da 1239 }
7e1112d3 1240 spin_unlock_bh(&priv->tx_lock);
a66098da 1241
7e1112d3 1242 return rc;
a66098da
LB
1243}
1244
c23b5a69
LB
1245#define MWL8K_TXD_SUCCESS(status) \
1246 ((status) & (MWL8K_TXD_STATUS_OK | \
1247 MWL8K_TXD_STATUS_OK_RETRY | \
1248 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1249
efb7c49a
LB
1250static int
1251mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB
1252{
1253 struct mwl8k_priv *priv = hw->priv;
1254 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1255 int processed;
a66098da 1256
efb7c49a
LB
1257 processed = 0;
1258 while (txq->stats.len > 0 && limit--) {
a66098da 1259 int tx;
a66098da
LB
1260 struct mwl8k_tx_desc *tx_desc;
1261 unsigned long addr;
ce9e2e1b 1262 int size;
a66098da
LB
1263 struct sk_buff *skb;
1264 struct ieee80211_tx_info *info;
1265 u32 status;
1266
45eb400d
LB
1267 tx = txq->head;
1268 tx_desc = txq->txd + tx;
a66098da
LB
1269
1270 status = le32_to_cpu(tx_desc->status);
1271
1272 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1273 if (!force)
1274 break;
1275 tx_desc->status &=
1276 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1277 }
1278
45eb400d
LB
1279 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1280 BUG_ON(txq->stats.len == 0);
1281 txq->stats.len--;
a66098da
LB
1282 priv->pending_tx_pkts--;
1283
1284 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1285 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB
1286 skb = txq->skb[tx];
1287 txq->skb[tx] = NULL;
a66098da
LB
1288
1289 BUG_ON(skb == NULL);
1290 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1291
20f09c3d 1292 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB
1293
1294 /* Mark descriptor as unused */
1295 tx_desc->pkt_phys_addr = 0;
1296 tx_desc->pkt_len = 0;
1297
a66098da
LB
1298 info = IEEE80211_SKB_CB(skb);
1299 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1300 if (MWL8K_TXD_SUCCESS(status))
a66098da 1301 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB
1302
1303 ieee80211_tx_status_irqsafe(hw, skb);
1304
efb7c49a 1305 processed++;
a66098da
LB
1306 }
1307
efb7c49a 1308 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1309 ieee80211_wake_queue(hw, index);
efb7c49a
LB
1310
1311 return processed;
a66098da
LB
1312}
1313
1314/* must be called only when the card's transmit is completely halted */
1315static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1316{
1317 struct mwl8k_priv *priv = hw->priv;
1318 struct mwl8k_tx_queue *txq = priv->txq + index;
1319
efb7c49a 1320 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1321
45eb400d
LB
1322 kfree(txq->skb);
1323 txq->skb = NULL;
a66098da
LB
1324
1325 pci_free_consistent(priv->pdev,
1326 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB
1327 txq->txd, txq->txd_dma);
1328 txq->txd = NULL;
a66098da
LB
1329}
1330
1331static int
1332mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1333{
1334 struct mwl8k_priv *priv = hw->priv;
1335 struct ieee80211_tx_info *tx_info;
23b33906 1336 struct mwl8k_vif *mwl8k_vif;
a66098da
LB
1337 struct ieee80211_hdr *wh;
1338 struct mwl8k_tx_queue *txq;
1339 struct mwl8k_tx_desc *tx;
a66098da 1340 dma_addr_t dma;
23b33906
LB
1341 u32 txstatus;
1342 u8 txdatarate;
1343 u16 qos;
a66098da 1344
23b33906
LB
1345 wh = (struct ieee80211_hdr *)skb->data;
1346 if (ieee80211_is_data_qos(wh->frame_control))
1347 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1348 else
1349 qos = 0;
a66098da 1350
76266b2a 1351 mwl8k_add_dma_header(skb);
23b33906 1352 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB
1353
1354 tx_info = IEEE80211_SKB_CB(skb);
1355 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB
1356
1357 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1358 u16 seqno = mwl8k_vif->seqno;
23b33906 1359
a66098da
LB
1360 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1361 wh->seq_ctrl |= cpu_to_le16(seqno << 4);
1362 mwl8k_vif->seqno = seqno++ % 4096;
1363 }
1364
23b33906
LB
1365 /* Setup firmware control bit fields for each frame type. */
1366 txstatus = 0;
1367 txdatarate = 0;
1368 if (ieee80211_is_mgmt(wh->frame_control) ||
1369 ieee80211_is_ctl(wh->frame_control)) {
1370 txdatarate = 0;
e0493a8d 1371 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB
1372 } else if (ieee80211_is_data(wh->frame_control)) {
1373 txdatarate = 1;
1374 if (is_multicast_ether_addr(wh->addr1))
1375 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1376
e0493a8d 1377 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1378 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1379 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1380 else
e0493a8d 1381 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1382 }
a66098da
LB
1383
1384 dma = pci_map_single(priv->pdev, skb->data,
1385 skb->len, PCI_DMA_TODEVICE);
1386
1387 if (pci_dma_mapping_error(priv->pdev, dma)) {
1388 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1389 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1390 dev_kfree_skb(skb);
a66098da
LB
1391 return NETDEV_TX_OK;
1392 }
1393
23b33906 1394 spin_lock_bh(&priv->tx_lock);
a66098da 1395
23b33906 1396 txq = priv->txq + index;
a66098da 1397
45eb400d
LB
1398 BUG_ON(txq->skb[txq->tail] != NULL);
1399 txq->skb[txq->tail] = skb;
a66098da 1400
45eb400d 1401 tx = txq->txd + txq->tail;
23b33906
LB
1402 tx->data_rate = txdatarate;
1403 tx->tx_priority = index;
a66098da 1404 tx->qos_control = cpu_to_le16(qos);
a66098da
LB
1405 tx->pkt_phys_addr = cpu_to_le32(dma);
1406 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1407 tx->rate_info = 0;
a680400e
LB
1408 if (!priv->ap_fw && tx_info->control.sta != NULL)
1409 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1410 else
1411 tx->peer_id = 0;
a66098da 1412 wmb();
23b33906
LB
1413 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1414
45eb400d
LB
1415 txq->stats.count++;
1416 txq->stats.len++;
a66098da 1417 priv->pending_tx_pkts++;
a66098da 1418
45eb400d
LB
1419 txq->tail++;
1420 if (txq->tail == MWL8K_TX_DESCS)
1421 txq->tail = 0;
23b33906 1422
45eb400d 1423 if (txq->head == txq->tail)
a66098da
LB
1424 ieee80211_stop_queue(hw, index);
1425
23b33906 1426 mwl8k_tx_start(priv);
a66098da
LB
1427
1428 spin_unlock_bh(&priv->tx_lock);
1429
1430 return NETDEV_TX_OK;
1431}
1432
1433
618952a7
LB
1434/*
1435 * Firmware access.
1436 *
1437 * We have the following requirements for issuing firmware commands:
1438 * - Some commands require that the packet transmit path is idle when
1439 * the command is issued. (For simplicity, we'll just quiesce the
1440 * transmit path for every command.)
1441 * - There are certain sequences of commands that need to be issued to
1442 * the hardware sequentially, with no other intervening commands.
1443 *
1444 * This leads to an implementation of a "firmware lock" as a mutex that
1445 * can be taken recursively, and which is taken by both the low-level
1446 * command submission function (mwl8k_post_cmd) as well as any users of
1447 * that function that require issuing of an atomic sequence of commands,
1448 * and quiesces the transmit path whenever it's taken.
1449 */
1450static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1451{
1452 struct mwl8k_priv *priv = hw->priv;
1453
1454 if (priv->fw_mutex_owner != current) {
1455 int rc;
1456
1457 mutex_lock(&priv->fw_mutex);
1458 ieee80211_stop_queues(hw);
1459
1460 rc = mwl8k_tx_wait_empty(hw);
1461 if (rc) {
1462 ieee80211_wake_queues(hw);
1463 mutex_unlock(&priv->fw_mutex);
1464
1465 return rc;
1466 }
1467
1468 priv->fw_mutex_owner = current;
1469 }
1470
1471 priv->fw_mutex_depth++;
1472
1473 return 0;
1474}
1475
1476static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1477{
1478 struct mwl8k_priv *priv = hw->priv;
1479
1480 if (!--priv->fw_mutex_depth) {
1481 ieee80211_wake_queues(hw);
1482 priv->fw_mutex_owner = NULL;
1483 mutex_unlock(&priv->fw_mutex);
1484 }
1485}
1486
1487
a66098da
LB
1488/*
1489 * Command processing.
1490 */
1491
0c9cc640
LB
1492/* Timeout firmware commands after 10s */
1493#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB
1494
1495static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1496{
1497 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1498 struct mwl8k_priv *priv = hw->priv;
1499 void __iomem *regs = priv->regs;
1500 dma_addr_t dma_addr;
1501 unsigned int dma_size;
1502 int rc;
a66098da
LB
1503 unsigned long timeout = 0;
1504 u8 buf[32];
1505
c2c357ce 1506 cmd->result = 0xffff;
a66098da
LB
1507 dma_size = le16_to_cpu(cmd->length);
1508 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1509 PCI_DMA_BIDIRECTIONAL);
1510 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1511 return -ENOMEM;
1512
618952a7 1513 rc = mwl8k_fw_lock(hw);
39a1e42e
LB
1514 if (rc) {
1515 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1516 PCI_DMA_BIDIRECTIONAL);
618952a7 1517 return rc;
39a1e42e 1518 }
a66098da 1519
a66098da
LB
1520 priv->hostcmd_wait = &cmd_wait;
1521 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1522 iowrite32(MWL8K_H2A_INT_DOORBELL,
1523 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1524 iowrite32(MWL8K_H2A_INT_DUMMY,
1525 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB
1526
1527 timeout = wait_for_completion_timeout(&cmd_wait,
1528 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1529
618952a7
LB
1530 priv->hostcmd_wait = NULL;
1531
1532 mwl8k_fw_unlock(hw);
1533
37055bd4
LB
1534 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1535 PCI_DMA_BIDIRECTIONAL);
1536
a66098da 1537 if (!timeout) {
a66098da 1538 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1539 wiphy_name(hw->wiphy),
a66098da
LB
1540 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1541 MWL8K_CMD_TIMEOUT_MS);
1542 rc = -ETIMEDOUT;
1543 } else {
0c9cc640
LB
1544 int ms;
1545
1546 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1547
ce9e2e1b 1548 rc = cmd->result ? -EINVAL : 0;
a66098da
LB
1549 if (rc)
1550 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1551 wiphy_name(hw->wiphy),
a66098da 1552 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1553 le16_to_cpu(cmd->result));
0c9cc640
LB
1554 else if (ms > 2000)
1555 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1556 wiphy_name(hw->wiphy),
1557 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1558 ms);
a66098da
LB
1559 }
1560
a66098da
LB
1561 return rc;
1562}
1563
1564/*
04b147b1 1565 * CMD_GET_HW_SPEC (STA version).
a66098da 1566 */
04b147b1 1567struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB
1568 struct mwl8k_cmd_pkt header;
1569 __u8 hw_rev;
1570 __u8 host_interface;
1571 __le16 num_mcaddrs;
d89173f2 1572 __u8 perm_addr[ETH_ALEN];
a66098da
LB
1573 __le16 region_code;
1574 __le32 fw_rev;
1575 __le32 ps_cookie;
1576 __le32 caps;
1577 __u8 mcs_bitmap[16];
1578 __le32 rx_queue_ptr;
1579 __le32 num_tx_queues;
1580 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1581 __le32 caps2;
1582 __le32 num_tx_desc_per_queue;
45eb400d 1583 __le32 total_rxd;
a66098da
LB
1584} __attribute__((packed));
1585
341c9791
LB
1586#define MWL8K_CAP_MAX_AMSDU 0x20000000
1587#define MWL8K_CAP_GREENFIELD 0x08000000
1588#define MWL8K_CAP_AMPDU 0x04000000
1589#define MWL8K_CAP_RX_STBC 0x01000000
1590#define MWL8K_CAP_TX_STBC 0x00800000
1591#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1592#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1593#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1594#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1595#define MWL8K_CAP_DELAY_BA 0x00003000
1596#define MWL8K_CAP_MIMO 0x00000200
1597#define MWL8K_CAP_40MHZ 0x00000100
1598
1599static void mwl8k_set_ht_caps(struct ieee80211_hw *hw, u32 cap)
1600{
1601 struct mwl8k_priv *priv = hw->priv;
1602 int rx_streams;
1603 int tx_streams;
1604
1605 priv->band.ht_cap.ht_supported = 1;
1606
1607 if (cap & MWL8K_CAP_MAX_AMSDU)
1608 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
1609 if (cap & MWL8K_CAP_GREENFIELD)
1610 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
1611 if (cap & MWL8K_CAP_AMPDU) {
1612 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
1613 priv->band.ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1614 priv->band.ht_cap.ampdu_density =
1615 IEEE80211_HT_MPDU_DENSITY_NONE;
1616 }
1617 if (cap & MWL8K_CAP_RX_STBC)
1618 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
1619 if (cap & MWL8K_CAP_TX_STBC)
1620 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
1621 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
1622 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
1623 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
1624 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
1625 if (cap & MWL8K_CAP_DELAY_BA)
1626 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
1627 if (cap & MWL8K_CAP_40MHZ)
1628 priv->band.ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
1629
1630 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1631 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1632
1633 priv->band.ht_cap.mcs.rx_mask[0] = 0xff;
1634 if (rx_streams >= 2)
1635 priv->band.ht_cap.mcs.rx_mask[1] = 0xff;
1636 if (rx_streams >= 3)
1637 priv->band.ht_cap.mcs.rx_mask[2] = 0xff;
1638 priv->band.ht_cap.mcs.rx_mask[4] = 0x01;
1639 priv->band.ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
1640
1641 if (rx_streams != tx_streams) {
1642 priv->band.ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1643 priv->band.ht_cap.mcs.tx_params |= (tx_streams - 1) <<
1644 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1645 }
1646}
1647
04b147b1 1648static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB
1649{
1650 struct mwl8k_priv *priv = hw->priv;
04b147b1 1651 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB
1652 int rc;
1653 int i;
1654
1655 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1656 if (cmd == NULL)
1657 return -ENOMEM;
1658
1659 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1660 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1661
1662 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1663 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1664 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1665 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1666 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1667 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1668 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1669 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB
1670
1671 rc = mwl8k_post_cmd(hw, &cmd->header);
1672
1673 if (!rc) {
1674 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1675 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1676 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1677 priv->hw_rev = cmd->hw_rev;
341c9791
LB
1678 if (cmd->caps & cpu_to_le32(MWL8K_CAP_MIMO))
1679 mwl8k_set_ht_caps(hw, le32_to_cpu(cmd->caps));
a66098da
LB
1680 }
1681
1682 kfree(cmd);
1683 return rc;
1684}
1685
42fba21d
LB
1686/*
1687 * CMD_GET_HW_SPEC (AP version).
1688 */
1689struct mwl8k_cmd_get_hw_spec_ap {
1690 struct mwl8k_cmd_pkt header;
1691 __u8 hw_rev;
1692 __u8 host_interface;
1693 __le16 num_wcb;
1694 __le16 num_mcaddrs;
1695 __u8 perm_addr[ETH_ALEN];
1696 __le16 region_code;
1697 __le16 num_antenna;
1698 __le32 fw_rev;
1699 __le32 wcbbase0;
1700 __le32 rxwrptr;
1701 __le32 rxrdptr;
1702 __le32 ps_cookie;
1703 __le32 wcbbase1;
1704 __le32 wcbbase2;
1705 __le32 wcbbase3;
1706} __attribute__((packed));
1707
1708static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1709{
1710 struct mwl8k_priv *priv = hw->priv;
1711 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1712 int rc;
1713
1714 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1715 if (cmd == NULL)
1716 return -ENOMEM;
1717
1718 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1719 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1720
1721 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1722 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1723
1724 rc = mwl8k_post_cmd(hw, &cmd->header);
1725
1726 if (!rc) {
1727 int off;
1728
1729 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1730 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1731 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1732 priv->hw_rev = cmd->hw_rev;
1733
1734 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1735 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1736
1737 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1738 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1739
1740 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1741 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1742
1743 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1744 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1745
1746 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1747 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1748
1749 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1750 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1751 }
1752
1753 kfree(cmd);
1754 return rc;
1755}
1756
1757/*
1758 * CMD_SET_HW_SPEC.
1759 */
1760struct mwl8k_cmd_set_hw_spec {
1761 struct mwl8k_cmd_pkt header;
1762 __u8 hw_rev;
1763 __u8 host_interface;
1764 __le16 num_mcaddrs;
1765 __u8 perm_addr[ETH_ALEN];
1766 __le16 region_code;
1767 __le32 fw_rev;
1768 __le32 ps_cookie;
1769 __le32 caps;
1770 __le32 rx_queue_ptr;
1771 __le32 num_tx_queues;
1772 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1773 __le32 flags;
1774 __le32 num_tx_desc_per_queue;
1775 __le32 total_rxd;
1776} __attribute__((packed));
1777
b64fe619
LB
1778#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1779#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
1780#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB
1781
1782static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1783{
1784 struct mwl8k_priv *priv = hw->priv;
1785 struct mwl8k_cmd_set_hw_spec *cmd;
1786 int rc;
1787 int i;
1788
1789 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1790 if (cmd == NULL)
1791 return -ENOMEM;
1792
1793 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1794 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1795
1796 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1797 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1798 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1799 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1800 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB
1801 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
1802 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
1803 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB
1804 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1805 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1806
1807 rc = mwl8k_post_cmd(hw, &cmd->header);
1808 kfree(cmd);
1809
1810 return rc;
1811}
1812
a66098da
LB
1813/*
1814 * CMD_MAC_MULTICAST_ADR.
1815 */
1816struct mwl8k_cmd_mac_multicast_adr {
1817 struct mwl8k_cmd_pkt header;
1818 __le16 action;
1819 __le16 numaddr;
ce9e2e1b 1820 __u8 addr[0][ETH_ALEN];
a66098da
LB
1821};
1822
d5e30845
LB
1823#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1824#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1825#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1826#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1827
e81cd2d6 1828static struct mwl8k_cmd_pkt *
447ced07 1829__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1830 int mc_count, struct dev_addr_list *mclist)
a66098da 1831{
e81cd2d6 1832 struct mwl8k_priv *priv = hw->priv;
a66098da 1833 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1834 int size;
e81cd2d6 1835
447ced07 1836 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB
1837 allmulti = 1;
1838 mc_count = 0;
1839 }
e81cd2d6
LB
1840
1841 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1842
e81cd2d6 1843 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1844 if (cmd == NULL)
e81cd2d6 1845 return NULL;
a66098da
LB
1846
1847 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1848 cmd->header.length = cpu_to_le16(size);
d5e30845
LB
1849 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1850 MWL8K_ENABLE_RX_BROADCAST);
1851
1852 if (allmulti) {
1853 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1854 } else if (mc_count) {
1855 int i;
1856
1857 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1858 cmd->numaddr = cpu_to_le16(mc_count);
1859 for (i = 0; i < mc_count && mclist; i++) {
1860 if (mclist->da_addrlen != ETH_ALEN) {
1861 kfree(cmd);
1862 return NULL;
1863 }
1864 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1865 mclist = mclist->next;
a66098da 1866 }
a66098da
LB
1867 }
1868
e81cd2d6 1869 return &cmd->header;
a66098da
LB
1870}
1871
1872/*
55489b6e 1873 * CMD_GET_STAT.
a66098da 1874 */
55489b6e 1875struct mwl8k_cmd_get_stat {
a66098da 1876 struct mwl8k_cmd_pkt header;
a66098da
LB
1877 __le32 stats[64];
1878} __attribute__((packed));
1879
1880#define MWL8K_STAT_ACK_FAILURE 9
1881#define MWL8K_STAT_RTS_FAILURE 12
1882#define MWL8K_STAT_FCS_ERROR 24
1883#define MWL8K_STAT_RTS_SUCCESS 11
1884
55489b6e
LB
1885static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1886 struct ieee80211_low_level_stats *stats)
a66098da 1887{
55489b6e 1888 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB
1889 int rc;
1890
1891 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1892 if (cmd == NULL)
1893 return -ENOMEM;
1894
1895 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
1896 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB
1897
1898 rc = mwl8k_post_cmd(hw, &cmd->header);
1899 if (!rc) {
1900 stats->dot11ACKFailureCount =
1901 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
1902 stats->dot11RTSFailureCount =
1903 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
1904 stats->dot11FCSErrorCount =
1905 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
1906 stats->dot11RTSSuccessCount =
1907 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
1908 }
1909 kfree(cmd);
1910
1911 return rc;
1912}
1913
1914/*
55489b6e 1915 * CMD_RADIO_CONTROL.
a66098da 1916 */
55489b6e 1917struct mwl8k_cmd_radio_control {
a66098da
LB
1918 struct mwl8k_cmd_pkt header;
1919 __le16 action;
1920 __le16 control;
1921 __le16 radio_on;
1922} __attribute__((packed));
1923
c46563b7 1924static int
55489b6e 1925mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB
1926{
1927 struct mwl8k_priv *priv = hw->priv;
55489b6e 1928 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB
1929 int rc;
1930
c46563b7 1931 if (enable == priv->radio_on && !force)
a66098da
LB
1932 return 0;
1933
a66098da
LB
1934 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1935 if (cmd == NULL)
1936 return -ENOMEM;
1937
1938 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
1939 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1940 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 1941 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB
1942 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
1943
1944 rc = mwl8k_post_cmd(hw, &cmd->header);
1945 kfree(cmd);
1946
1947 if (!rc)
c46563b7 1948 priv->radio_on = enable;
a66098da
LB
1949
1950 return rc;
1951}
1952
55489b6e 1953static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 1954{
55489b6e 1955 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB
1956}
1957
55489b6e 1958static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 1959{
55489b6e 1960 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB
1961}
1962
a66098da
LB
1963static int
1964mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
1965{
99200a99 1966 struct mwl8k_priv *priv = hw->priv;
a66098da 1967
68ce3884 1968 priv->radio_short_preamble = short_preamble;
a66098da 1969
55489b6e 1970 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB
1971}
1972
1973/*
55489b6e 1974 * CMD_RF_TX_POWER.
a66098da
LB
1975 */
1976#define MWL8K_TX_POWER_LEVEL_TOTAL 8
1977
55489b6e 1978struct mwl8k_cmd_rf_tx_power {
a66098da
LB
1979 struct mwl8k_cmd_pkt header;
1980 __le16 action;
1981 __le16 support_level;
1982 __le16 current_level;
1983 __le16 reserved;
1984 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
1985} __attribute__((packed));
1986
55489b6e 1987static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 1988{
55489b6e 1989 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB
1990 int rc;
1991
1992 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1993 if (cmd == NULL)
1994 return -ENOMEM;
1995
1996 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
1997 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1998 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
1999 cmd->support_level = cpu_to_le16(dBm);
2000
2001 rc = mwl8k_post_cmd(hw, &cmd->header);
2002 kfree(cmd);
2003
2004 return rc;
2005}
2006
08b06347
LB
2007/*
2008 * CMD_RF_ANTENNA.
2009 */
2010struct mwl8k_cmd_rf_antenna {
2011 struct mwl8k_cmd_pkt header;
2012 __le16 antenna;
2013 __le16 mode;
2014} __attribute__((packed));
2015
2016#define MWL8K_RF_ANTENNA_RX 1
2017#define MWL8K_RF_ANTENNA_TX 2
2018
2019static int
2020mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2021{
2022 struct mwl8k_cmd_rf_antenna *cmd;
2023 int rc;
2024
2025 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2026 if (cmd == NULL)
2027 return -ENOMEM;
2028
2029 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2030 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2031 cmd->antenna = cpu_to_le16(antenna);
2032 cmd->mode = cpu_to_le16(mask);
2033
2034 rc = mwl8k_post_cmd(hw, &cmd->header);
2035 kfree(cmd);
2036
2037 return rc;
2038}
2039
b64fe619
LB
2040/*
2041 * CMD_SET_BEACON.
2042 */
2043struct mwl8k_cmd_set_beacon {
2044 struct mwl8k_cmd_pkt header;
2045 __le16 beacon_len;
2046 __u8 beacon[0];
2047};
2048
2049static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
2050{
2051 struct mwl8k_cmd_set_beacon *cmd;
2052 int rc;
2053
2054 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2055 if (cmd == NULL)
2056 return -ENOMEM;
2057
2058 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2059 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2060 cmd->beacon_len = cpu_to_le16(len);
2061 memcpy(cmd->beacon, beacon, len);
2062
2063 rc = mwl8k_post_cmd(hw, &cmd->header);
2064 kfree(cmd);
2065
2066 return rc;
2067}
2068
a66098da
LB
2069/*
2070 * CMD_SET_PRE_SCAN.
2071 */
2072struct mwl8k_cmd_set_pre_scan {
2073 struct mwl8k_cmd_pkt header;
2074} __attribute__((packed));
2075
2076static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2077{
2078 struct mwl8k_cmd_set_pre_scan *cmd;
2079 int rc;
2080
2081 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2082 if (cmd == NULL)
2083 return -ENOMEM;
2084
2085 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2086 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2087
2088 rc = mwl8k_post_cmd(hw, &cmd->header);
2089 kfree(cmd);
2090
2091 return rc;
2092}
2093
2094/*
2095 * CMD_SET_POST_SCAN.
2096 */
2097struct mwl8k_cmd_set_post_scan {
2098 struct mwl8k_cmd_pkt header;
2099 __le32 isibss;
d89173f2 2100 __u8 bssid[ETH_ALEN];
a66098da
LB
2101} __attribute__((packed));
2102
2103static int
0a11dfc3 2104mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB
2105{
2106 struct mwl8k_cmd_set_post_scan *cmd;
2107 int rc;
2108
2109 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2110 if (cmd == NULL)
2111 return -ENOMEM;
2112
2113 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2114 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2115 cmd->isibss = 0;
d89173f2 2116 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB
2117
2118 rc = mwl8k_post_cmd(hw, &cmd->header);
2119 kfree(cmd);
2120
2121 return rc;
2122}
2123
2124/*
2125 * CMD_SET_RF_CHANNEL.
2126 */
2127struct mwl8k_cmd_set_rf_channel {
2128 struct mwl8k_cmd_pkt header;
2129 __le16 action;
2130 __u8 current_channel;
2131 __le32 channel_flags;
2132} __attribute__((packed));
2133
2134static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2135 struct ieee80211_conf *conf)
a66098da 2136{
610677d2 2137 struct ieee80211_channel *channel = conf->channel;
a66098da
LB
2138 struct mwl8k_cmd_set_rf_channel *cmd;
2139 int rc;
2140
2141 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2142 if (cmd == NULL)
2143 return -ENOMEM;
2144
2145 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2146 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2147 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2148 cmd->current_channel = channel->hw_value;
610677d2 2149
a66098da 2150 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2
LB
2151 cmd->channel_flags |= cpu_to_le32(0x00000001);
2152
2153 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2154 conf->channel_type == NL80211_CHAN_HT20)
2155 cmd->channel_flags |= cpu_to_le32(0x00000080);
2156 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2157 cmd->channel_flags |= cpu_to_le32(0x000001900);
2158 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2159 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB
2160
2161 rc = mwl8k_post_cmd(hw, &cmd->header);
2162 kfree(cmd);
2163
2164 return rc;
2165}
2166
2167/*
55489b6e 2168 * CMD_SET_AID.
a66098da 2169 */
55489b6e
LB
2170#define MWL8K_FRAME_PROT_DISABLED 0x00
2171#define MWL8K_FRAME_PROT_11G 0x07
2172#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2173#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2174
55489b6e
LB
2175struct mwl8k_cmd_update_set_aid {
2176 struct mwl8k_cmd_pkt header;
2177 __le16 aid;
a66098da 2178
55489b6e
LB
2179 /* AP's MAC address (BSSID) */
2180 __u8 bssid[ETH_ALEN];
2181 __le16 protection_mode;
2182 __u8 supp_rates[14];
a66098da
LB
2183} __attribute__((packed));
2184
c6e96010
LB
2185static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2186{
2187 int i;
2188 int j;
2189
2190 /*
2191 * Clear nonstandard rates 4 and 13.
2192 */
2193 mask &= 0x1fef;
2194
2195 for (i = 0, j = 0; i < 14; i++) {
2196 if (mask & (1 << i))
2197 rates[j++] = mwl8k_rates[i].hw_value;
2198 }
2199}
2200
55489b6e 2201static int
c6e96010
LB
2202mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2203 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2204{
55489b6e
LB
2205 struct mwl8k_cmd_update_set_aid *cmd;
2206 u16 prot_mode;
a66098da
LB
2207 int rc;
2208
2209 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2210 if (cmd == NULL)
2211 return -ENOMEM;
2212
55489b6e 2213 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2214 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2215 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2216 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2217
7dc6a7a7 2218 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB
2219 prot_mode = MWL8K_FRAME_PROT_11G;
2220 } else {
7dc6a7a7 2221 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB
2222 IEEE80211_HT_OP_MODE_PROTECTION) {
2223 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2224 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2225 break;
2226 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2227 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2228 break;
2229 default:
2230 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2231 break;
2232 }
2233 }
2234 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2235
c6e96010 2236 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB
2237
2238 rc = mwl8k_post_cmd(hw, &cmd->header);
2239 kfree(cmd);
2240
2241 return rc;
2242}
2243
32060e1b 2244/*
55489b6e 2245 * CMD_SET_RATE.
32060e1b 2246 */
55489b6e
LB
2247struct mwl8k_cmd_set_rate {
2248 struct mwl8k_cmd_pkt header;
2249 __u8 legacy_rates[14];
2250
2251 /* Bitmap for supported MCS codes. */
2252 __u8 mcs_set[16];
2253 __u8 reserved[16];
32060e1b
LB
2254} __attribute__((packed));
2255
55489b6e 2256static int
c6e96010 2257mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2258 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2259{
55489b6e 2260 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB
2261 int rc;
2262
2263 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2264 if (cmd == NULL)
2265 return -ENOMEM;
2266
55489b6e 2267 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2268 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2269 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2270 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB
2271
2272 rc = mwl8k_post_cmd(hw, &cmd->header);
2273 kfree(cmd);
2274
2275 return rc;
2276}
2277
a66098da 2278/*
55489b6e 2279 * CMD_FINALIZE_JOIN.
a66098da 2280 */
55489b6e
LB
2281#define MWL8K_FJ_BEACON_MAXLEN 128
2282
2283struct mwl8k_cmd_finalize_join {
a66098da 2284 struct mwl8k_cmd_pkt header;
55489b6e
LB
2285 __le32 sleep_interval; /* Number of beacon periods to sleep */
2286 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB
2287} __attribute__((packed));
2288
55489b6e
LB
2289static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2290 int framelen, int dtim)
a66098da 2291{
55489b6e
LB
2292 struct mwl8k_cmd_finalize_join *cmd;
2293 struct ieee80211_mgmt *payload = frame;
2294 int payload_len;
a66098da
LB
2295 int rc;
2296
2297 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2298 if (cmd == NULL)
2299 return -ENOMEM;
2300
55489b6e 2301 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2302 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
2303 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2304
2305 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2306 if (payload_len < 0)
2307 payload_len = 0;
2308 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2309 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2310
2311 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB
2312
2313 rc = mwl8k_post_cmd(hw, &cmd->header);
2314 kfree(cmd);
2315
2316 return rc;
2317}
2318
2319/*
55489b6e 2320 * CMD_SET_RTS_THRESHOLD.
a66098da 2321 */
55489b6e 2322struct mwl8k_cmd_set_rts_threshold {
a66098da
LB
2323 struct mwl8k_cmd_pkt header;
2324 __le16 action;
55489b6e 2325 __le16 threshold;
a66098da
LB
2326} __attribute__((packed));
2327
c2c2b12a
LB
2328static int
2329mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2330{
55489b6e 2331 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB
2332 int rc;
2333
2334 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2335 if (cmd == NULL)
2336 return -ENOMEM;
2337
55489b6e 2338 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2339 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB
2340 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2341 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB
2342
2343 rc = mwl8k_post_cmd(hw, &cmd->header);
2344 kfree(cmd);
2345
a66098da
LB
2346 return rc;
2347}
2348
2349/*
55489b6e 2350 * CMD_SET_SLOT.
a66098da 2351 */
55489b6e 2352struct mwl8k_cmd_set_slot {
a66098da
LB
2353 struct mwl8k_cmd_pkt header;
2354 __le16 action;
55489b6e 2355 __u8 short_slot;
a66098da
LB
2356} __attribute__((packed));
2357
55489b6e 2358static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2359{
55489b6e 2360 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB
2361 int rc;
2362
2363 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2364 if (cmd == NULL)
2365 return -ENOMEM;
2366
55489b6e 2367 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2368 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
2369 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2370 cmd->short_slot = short_slot_time;
a66098da
LB
2371
2372 rc = mwl8k_post_cmd(hw, &cmd->header);
2373 kfree(cmd);
2374
2375 return rc;
2376}
2377
2378/*
2379 * CMD_SET_EDCA_PARAMS.
2380 */
2381struct mwl8k_cmd_set_edca_params {
2382 struct mwl8k_cmd_pkt header;
2383
2384 /* See MWL8K_SET_EDCA_XXX below */
2385 __le16 action;
2386
2387 /* TX opportunity in units of 32 us */
2388 __le16 txop;
2389
2e484c89
LB
2390 union {
2391 struct {
2392 /* Log exponent of max contention period: 0...15 */
2393 __le32 log_cw_max;
2394
2395 /* Log exponent of min contention period: 0...15 */
2396 __le32 log_cw_min;
2397
2398 /* Adaptive interframe spacing in units of 32us */
2399 __u8 aifs;
2400
2401 /* TX queue to configure */
2402 __u8 txq;
2403 } ap;
2404 struct {
2405 /* Log exponent of max contention period: 0...15 */
2406 __u8 log_cw_max;
a66098da 2407
2e484c89
LB
2408 /* Log exponent of min contention period: 0...15 */
2409 __u8 log_cw_min;
a66098da 2410
2e484c89
LB
2411 /* Adaptive interframe spacing in units of 32us */
2412 __u8 aifs;
a66098da 2413
2e484c89
LB
2414 /* TX queue to configure */
2415 __u8 txq;
2416 } sta;
2417 };
a66098da
LB
2418} __attribute__((packed));
2419
a66098da
LB
2420#define MWL8K_SET_EDCA_CW 0x01
2421#define MWL8K_SET_EDCA_TXOP 0x02
2422#define MWL8K_SET_EDCA_AIFS 0x04
2423
2424#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2425 MWL8K_SET_EDCA_TXOP | \
2426 MWL8K_SET_EDCA_AIFS)
2427
2428static int
55489b6e
LB
2429mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2430 __u16 cw_min, __u16 cw_max,
2431 __u8 aifs, __u16 txop)
a66098da 2432{
2e484c89 2433 struct mwl8k_priv *priv = hw->priv;
a66098da 2434 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB
2435 int rc;
2436
2437 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2438 if (cmd == NULL)
2439 return -ENOMEM;
2440
a66098da
LB
2441 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2442 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB
2443 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2444 cmd->txop = cpu_to_le16(txop);
2e484c89
LB
2445 if (priv->ap_fw) {
2446 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2447 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2448 cmd->ap.aifs = aifs;
2449 cmd->ap.txq = qnum;
2450 } else {
2451 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2452 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2453 cmd->sta.aifs = aifs;
2454 cmd->sta.txq = qnum;
2455 }
a66098da
LB
2456
2457 rc = mwl8k_post_cmd(hw, &cmd->header);
2458 kfree(cmd);
2459
2460 return rc;
2461}
2462
2463/*
55489b6e 2464 * CMD_SET_WMM_MODE.
a66098da 2465 */
55489b6e 2466struct mwl8k_cmd_set_wmm_mode {
a66098da 2467 struct mwl8k_cmd_pkt header;
55489b6e 2468 __le16 action;
a66098da
LB
2469} __attribute__((packed));
2470
55489b6e 2471static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2472{
55489b6e
LB
2473 struct mwl8k_priv *priv = hw->priv;
2474 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB
2475 int rc;
2476
a66098da
LB
2477 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2478 if (cmd == NULL)
2479 return -ENOMEM;
2480
55489b6e 2481 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2482 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2483 cmd->action = cpu_to_le16(!!enable);
a66098da
LB
2484
2485 rc = mwl8k_post_cmd(hw, &cmd->header);
2486 kfree(cmd);
16cec43d 2487
55489b6e
LB
2488 if (!rc)
2489 priv->wmm_enabled = enable;
a66098da
LB
2490
2491 return rc;
2492}
2493
2494/*
55489b6e 2495 * CMD_MIMO_CONFIG.
a66098da 2496 */
55489b6e
LB
2497struct mwl8k_cmd_mimo_config {
2498 struct mwl8k_cmd_pkt header;
2499 __le32 action;
2500 __u8 rx_antenna_map;
2501 __u8 tx_antenna_map;
a66098da
LB
2502} __attribute__((packed));
2503
55489b6e 2504static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2505{
55489b6e 2506 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB
2507 int rc;
2508
2509 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2510 if (cmd == NULL)
2511 return -ENOMEM;
2512
55489b6e 2513 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2514 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB
2515 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2516 cmd->rx_antenna_map = rx;
2517 cmd->tx_antenna_map = tx;
a66098da
LB
2518
2519 rc = mwl8k_post_cmd(hw, &cmd->header);
2520 kfree(cmd);
2521
2522 return rc;
2523}
2524
2525/*
b71ed2c6 2526 * CMD_USE_FIXED_RATE (STA version).
a66098da 2527 */
b71ed2c6
LB
2528struct mwl8k_cmd_use_fixed_rate_sta {
2529 struct mwl8k_cmd_pkt header;
2530 __le32 action;
2531 __le32 allow_rate_drop;
2532 __le32 num_rates;
2533 struct {
2534 __le32 is_ht_rate;
2535 __le32 enable_retry;
2536 __le32 rate;
2537 __le32 retry_count;
2538 } rate_entry[8];
2539 __le32 rate_type;
2540 __le32 reserved1;
2541 __le32 reserved2;
a66098da
LB
2542} __attribute__((packed));
2543
b71ed2c6
LB
2544#define MWL8K_USE_AUTO_RATE 0x0002
2545#define MWL8K_UCAST_RATE 0
a66098da 2546
b71ed2c6 2547static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2548{
b71ed2c6 2549 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB
2550 int rc;
2551
2552 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2553 if (cmd == NULL)
2554 return -ENOMEM;
2555
2556 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2557 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB
2558 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2559 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB
2560
2561 rc = mwl8k_post_cmd(hw, &cmd->header);
2562 kfree(cmd);
2563
2564 return rc;
2565}
2566
088aab8b
LB
2567/*
2568 * CMD_USE_FIXED_RATE (AP version).
2569 */
2570struct mwl8k_cmd_use_fixed_rate_ap {
2571 struct mwl8k_cmd_pkt header;
2572 __le32 action;
2573 __le32 allow_rate_drop;
2574 __le32 num_rates;
2575 struct mwl8k_rate_entry_ap {
2576 __le32 is_ht_rate;
2577 __le32 enable_retry;
2578 __le32 rate;
2579 __le32 retry_count;
2580 } rate_entry[4];
2581 u8 multicast_rate;
2582 u8 multicast_rate_type;
2583 u8 management_rate;
2584} __attribute__((packed));
2585
2586static int
2587mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2588{
2589 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2590 int rc;
2591
2592 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2593 if (cmd == NULL)
2594 return -ENOMEM;
2595
2596 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2597 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2598 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2599 cmd->multicast_rate = mcast;
2600 cmd->management_rate = mgmt;
2601
2602 rc = mwl8k_post_cmd(hw, &cmd->header);
2603 kfree(cmd);
2604
2605 return rc;
2606}
2607
55489b6e
LB
2608/*
2609 * CMD_ENABLE_SNIFFER.
2610 */
2611struct mwl8k_cmd_enable_sniffer {
2612 struct mwl8k_cmd_pkt header;
2613 __le32 action;
2614} __attribute__((packed));
2615
2616static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2617{
2618 struct mwl8k_cmd_enable_sniffer *cmd;
2619 int rc;
2620
2621 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2622 if (cmd == NULL)
2623 return -ENOMEM;
2624
2625 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2626 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2627 cmd->action = cpu_to_le32(!!enable);
2628
2629 rc = mwl8k_post_cmd(hw, &cmd->header);
2630 kfree(cmd);
2631
2632 return rc;
2633}
2634
2635/*
2636 * CMD_SET_MAC_ADDR.
2637 */
2638struct mwl8k_cmd_set_mac_addr {
2639 struct mwl8k_cmd_pkt header;
2640 union {
2641 struct {
2642 __le16 mac_type;
2643 __u8 mac_addr[ETH_ALEN];
2644 } mbss;
2645 __u8 mac_addr[ETH_ALEN];
2646 };
2647} __attribute__((packed));
2648
a9e00b15
LB
2649#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
2650#define MWL8K_MAC_TYPE_PRIMARY_AP 2
2651
55489b6e
LB
2652static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2653{
2654 struct mwl8k_priv *priv = hw->priv;
2655 struct mwl8k_cmd_set_mac_addr *cmd;
2656 int rc;
2657
2658 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2659 if (cmd == NULL)
2660 return -ENOMEM;
2661
2662 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2663 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2664 if (priv->ap_fw) {
a9e00b15 2665 cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
55489b6e
LB
2666 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2667 } else {
2668 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2669 }
2670
2671 rc = mwl8k_post_cmd(hw, &cmd->header);
2672 kfree(cmd);
2673
2674 return rc;
2675}
2676
2677/*
2678 * CMD_SET_RATEADAPT_MODE.
2679 */
2680struct mwl8k_cmd_set_rate_adapt_mode {
2681 struct mwl8k_cmd_pkt header;
2682 __le16 action;
2683 __le16 mode;
2684} __attribute__((packed));
2685
2686static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2687{
2688 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2689 int rc;
2690
2691 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2692 if (cmd == NULL)
2693 return -ENOMEM;
2694
2695 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2696 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2697 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2698 cmd->mode = cpu_to_le16(mode);
2699
2700 rc = mwl8k_post_cmd(hw, &cmd->header);
2701 kfree(cmd);
2702
2703 return rc;
2704}
2705
b64fe619
LB
2706/*
2707 * CMD_BSS_START.
2708 */
2709struct mwl8k_cmd_bss_start {
2710 struct mwl8k_cmd_pkt header;
2711 __le32 enable;
2712} __attribute__((packed));
2713
2714static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
2715{
2716 struct mwl8k_cmd_bss_start *cmd;
2717 int rc;
2718
2719 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2720 if (cmd == NULL)
2721 return -ENOMEM;
2722
2723 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
2724 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2725 cmd->enable = cpu_to_le32(enable);
2726
2727 rc = mwl8k_post_cmd(hw, &cmd->header);
2728 kfree(cmd);
2729
2730 return rc;
2731}
2732
3f5610ff
LB
2733/*
2734 * CMD_SET_NEW_STN.
2735 */
2736struct mwl8k_cmd_set_new_stn {
2737 struct mwl8k_cmd_pkt header;
2738 __le16 aid;
2739 __u8 mac_addr[6];
2740 __le16 stn_id;
2741 __le16 action;
2742 __le16 rsvd;
2743 __le32 legacy_rates;
2744 __u8 ht_rates[4];
2745 __le16 cap_info;
2746 __le16 ht_capabilities_info;
2747 __u8 mac_ht_param_info;
2748 __u8 rev;
2749 __u8 control_channel;
2750 __u8 add_channel;
2751 __le16 op_mode;
2752 __le16 stbc;
2753 __u8 add_qos_info;
2754 __u8 is_qos_sta;
2755 __le32 fw_sta_ptr;
2756} __attribute__((packed));
2757
2758#define MWL8K_STA_ACTION_ADD 0
2759#define MWL8K_STA_ACTION_REMOVE 2
2760
2761static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
2762 struct ieee80211_vif *vif,
2763 struct ieee80211_sta *sta)
2764{
2765 struct mwl8k_cmd_set_new_stn *cmd;
2766 int rc;
2767
2768 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2769 if (cmd == NULL)
2770 return -ENOMEM;
2771
2772 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2773 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2774 cmd->aid = cpu_to_le16(sta->aid);
2775 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
2776 cmd->stn_id = cpu_to_le16(sta->aid);
2777 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
2778 cmd->legacy_rates = cpu_to_le32(sta->supp_rates[IEEE80211_BAND_2GHZ]);
2779 if (sta->ht_cap.ht_supported) {
2780 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
2781 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
2782 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
2783 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
2784 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
2785 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
2786 ((sta->ht_cap.ampdu_density & 7) << 2);
2787 cmd->is_qos_sta = 1;
2788 }
2789
2790 rc = mwl8k_post_cmd(hw, &cmd->header);
2791 kfree(cmd);
2792
2793 return rc;
2794}
2795
b64fe619
LB
2796static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
2797 struct ieee80211_vif *vif)
2798{
2799 struct mwl8k_cmd_set_new_stn *cmd;
2800 int rc;
2801
2802 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2803 if (cmd == NULL)
2804 return -ENOMEM;
2805
2806 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2807 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2808 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
2809
2810 rc = mwl8k_post_cmd(hw, &cmd->header);
2811 kfree(cmd);
2812
2813 return rc;
2814}
2815
3f5610ff
LB
2816static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
2817 struct ieee80211_vif *vif, u8 *addr)
2818{
2819 struct mwl8k_cmd_set_new_stn *cmd;
2820 int rc;
2821
2822 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2823 if (cmd == NULL)
2824 return -ENOMEM;
2825
2826 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2827 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2828 memcpy(cmd->mac_addr, addr, ETH_ALEN);
2829 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
2830
2831 rc = mwl8k_post_cmd(hw, &cmd->header);
2832 kfree(cmd);
2833
2834 return rc;
2835}
2836
55489b6e
LB
2837/*
2838 * CMD_UPDATE_STADB.
2839 */
25d81b1e
LB
2840struct ewc_ht_info {
2841 __le16 control1;
2842 __le16 control2;
2843 __le16 control3;
2844} __attribute__((packed));
2845
2846struct peer_capability_info {
2847 /* Peer type - AP vs. STA. */
2848 __u8 peer_type;
2849
2850 /* Basic 802.11 capabilities from assoc resp. */
2851 __le16 basic_caps;
2852
2853 /* Set if peer supports 802.11n high throughput (HT). */
2854 __u8 ht_support;
2855
2856 /* Valid if HT is supported. */
2857 __le16 ht_caps;
2858 __u8 extended_ht_caps;
2859 struct ewc_ht_info ewc_info;
2860
2861 /* Legacy rate table. Intersection of our rates and peer rates. */
2862 __u8 legacy_rates[12];
2863
2864 /* HT rate table. Intersection of our rates and peer rates. */
2865 __u8 ht_rates[16];
2866 __u8 pad[16];
2867
2868 /* If set, interoperability mode, no proprietary extensions. */
2869 __u8 interop;
2870 __u8 pad2;
2871 __u8 station_id;
2872 __le16 amsdu_enabled;
2873} __attribute__((packed));
2874
55489b6e
LB
2875struct mwl8k_cmd_update_stadb {
2876 struct mwl8k_cmd_pkt header;
2877
2878 /* See STADB_ACTION_TYPE */
2879 __le32 action;
2880
2881 /* Peer MAC address */
2882 __u8 peer_addr[ETH_ALEN];
2883
2884 __le32 reserved;
2885
2886 /* Peer info - valid during add/update. */
2887 struct peer_capability_info peer_info;
2888} __attribute__((packed));
2889
a680400e
LB
2890#define MWL8K_STA_DB_MODIFY_ENTRY 1
2891#define MWL8K_STA_DB_DEL_ENTRY 2
2892
2893/* Peer Entry flags - used to define the type of the peer node */
2894#define MWL8K_PEER_TYPE_ACCESSPOINT 2
2895
2896static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 2897 struct ieee80211_vif *vif,
13935e2c 2898 struct ieee80211_sta *sta)
55489b6e 2899{
55489b6e 2900 struct mwl8k_cmd_update_stadb *cmd;
a680400e 2901 struct peer_capability_info *p;
55489b6e
LB
2902 int rc;
2903
2904 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2905 if (cmd == NULL)
2906 return -ENOMEM;
2907
2908 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2909 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 2910 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 2911 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 2912
a680400e
LB
2913 p = &cmd->peer_info;
2914 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
2915 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c
LB
2916 p->ht_support = sta->ht_cap.ht_supported;
2917 p->ht_caps = sta->ht_cap.cap;
2918 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
2919 ((sta->ht_cap.ampdu_density & 7) << 2);
2920 legacy_rate_mask_to_array(p->legacy_rates,
2921 sta->supp_rates[IEEE80211_BAND_2GHZ]);
2922 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB
2923 p->interop = 1;
2924 p->amsdu_enabled = 0;
2925
2926 rc = mwl8k_post_cmd(hw, &cmd->header);
2927 kfree(cmd);
2928
2929 return rc ? rc : p->station_id;
2930}
2931
2932static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
2933 struct ieee80211_vif *vif, u8 *addr)
2934{
2935 struct mwl8k_cmd_update_stadb *cmd;
2936 int rc;
2937
2938 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2939 if (cmd == NULL)
2940 return -ENOMEM;
2941
2942 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
2943 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2944 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 2945 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 2946
a680400e 2947 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB
2948 kfree(cmd);
2949
2950 return rc;
2951}
2952
a66098da
LB
2953
2954/*
2955 * Interrupt handling.
2956 */
2957static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
2958{
2959 struct ieee80211_hw *hw = dev_id;
2960 struct mwl8k_priv *priv = hw->priv;
2961 u32 status;
2962
2963 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB
2964 if (!status)
2965 return IRQ_NONE;
2966
1e9f9de3
LB
2967 if (status & MWL8K_A2H_INT_TX_DONE) {
2968 status &= ~MWL8K_A2H_INT_TX_DONE;
2969 tasklet_schedule(&priv->poll_tx_task);
2970 }
2971
a66098da 2972 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB
2973 status &= ~MWL8K_A2H_INT_RX_READY;
2974 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB
2975 }
2976
67e2eb27
LB
2977 if (status)
2978 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
2979
a66098da 2980 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 2981 if (priv->hostcmd_wait != NULL)
a66098da 2982 complete(priv->hostcmd_wait);
a66098da
LB
2983 }
2984
2985 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 2986 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 2987 priv->radio_on && priv->pending_tx_pkts)
618952a7 2988 mwl8k_tx_start(priv);
a66098da
LB
2989 }
2990
2991 return IRQ_HANDLED;
2992}
2993
1e9f9de3
LB
2994static void mwl8k_tx_poll(unsigned long data)
2995{
2996 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
2997 struct mwl8k_priv *priv = hw->priv;
2998 int limit;
2999 int i;
3000
3001 limit = 32;
3002
3003 spin_lock_bh(&priv->tx_lock);
3004
3005 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3006 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3007
3008 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3009 complete(priv->tx_wait);
3010 priv->tx_wait = NULL;
3011 }
3012
3013 spin_unlock_bh(&priv->tx_lock);
3014
3015 if (limit) {
3016 writel(~MWL8K_A2H_INT_TX_DONE,
3017 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3018 } else {
3019 tasklet_schedule(&priv->poll_tx_task);
3020 }
3021}
3022
67e2eb27
LB
3023static void mwl8k_rx_poll(unsigned long data)
3024{
3025 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3026 struct mwl8k_priv *priv = hw->priv;
3027 int limit;
3028
3029 limit = 32;
3030 limit -= rxq_process(hw, 0, limit);
3031 limit -= rxq_refill(hw, 0, limit);
3032
3033 if (limit) {
3034 writel(~MWL8K_A2H_INT_RX_READY,
3035 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3036 } else {
3037 tasklet_schedule(&priv->poll_rx_task);
3038 }
3039}
3040
a66098da
LB
3041
3042/*
3043 * Core driver operations.
3044 */
3045static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3046{
3047 struct mwl8k_priv *priv = hw->priv;
3048 int index = skb_get_queue_mapping(skb);
3049 int rc;
3050
9189c100 3051 if (!priv->radio_on) {
a66098da 3052 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 3053 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB
3054 dev_kfree_skb(skb);
3055 return NETDEV_TX_OK;
3056 }
3057
3058 rc = mwl8k_txq_xmit(hw, index, skb);
3059
3060 return rc;
3061}
3062
a66098da
LB
3063static int mwl8k_start(struct ieee80211_hw *hw)
3064{
a66098da
LB
3065 struct mwl8k_priv *priv = hw->priv;
3066 int rc;
3067
a0607fd3 3068 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB
3069 IRQF_SHARED, MWL8K_NAME, hw);
3070 if (rc) {
3071 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3072 wiphy_name(hw->wiphy));
2ec610cb 3073 return -EIO;
a66098da
LB
3074 }
3075
67e2eb27 3076 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3077 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3078 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3079
a66098da 3080 /* Enable interrupts */
c23b5a69 3081 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3082
2ec610cb
LB
3083 rc = mwl8k_fw_lock(hw);
3084 if (!rc) {
55489b6e 3085 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3086
5e4cf166
LB
3087 if (!priv->ap_fw) {
3088 if (!rc)
55489b6e 3089 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3090
5e4cf166
LB
3091 if (!rc)
3092 rc = mwl8k_cmd_set_pre_scan(hw);
3093
3094 if (!rc)
3095 rc = mwl8k_cmd_set_post_scan(hw,
3096 "\x00\x00\x00\x00\x00\x00");
3097 }
2ec610cb
LB
3098
3099 if (!rc)
55489b6e 3100 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3101
2ec610cb 3102 if (!rc)
55489b6e 3103 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3104
2ec610cb
LB
3105 mwl8k_fw_unlock(hw);
3106 }
3107
3108 if (rc) {
3109 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3110 free_irq(priv->pdev->irq, hw);
1e9f9de3 3111 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3112 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3113 }
a66098da
LB
3114
3115 return rc;
3116}
3117
a66098da
LB
3118static void mwl8k_stop(struct ieee80211_hw *hw)
3119{
a66098da
LB
3120 struct mwl8k_priv *priv = hw->priv;
3121 int i;
3122
55489b6e 3123 mwl8k_cmd_radio_disable(hw);
a66098da
LB
3124
3125 ieee80211_stop_queues(hw);
3126
a66098da 3127 /* Disable interrupts */
a66098da 3128 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
3129 free_irq(priv->pdev->irq, hw);
3130
3131 /* Stop finalize join worker */
3132 cancel_work_sync(&priv->finalize_join_worker);
3133 if (priv->beacon_skb != NULL)
3134 dev_kfree_skb(priv->beacon_skb);
3135
67e2eb27 3136 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3137 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3138 tasklet_disable(&priv->poll_rx_task);
a66098da 3139
a66098da
LB
3140 /* Return all skbs to mac80211 */
3141 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3142 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB
3143}
3144
3145static int mwl8k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3146 struct ieee80211_vif *vif)
a66098da
LB
3147{
3148 struct mwl8k_priv *priv = hw->priv;
3149 struct mwl8k_vif *mwl8k_vif;
3150
3151 /*
3152 * We only support one active interface at a time.
3153 */
3154 if (priv->vif != NULL)
3155 return -EBUSY;
3156
a43c49a8
LB
3157 /*
3158 * Reject interface creation if sniffer mode is active, as
3159 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3160 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB
3161 */
3162 if (priv->sniffer_enabled) {
3163 printk(KERN_INFO "%s: unable to create STA "
3164 "interface due to sniffer mode being enabled\n",
3165 wiphy_name(hw->wiphy));
3166 return -EINVAL;
3167 }
3168
c2c2b12a
LB
3169 /* Set the mac address. */
3170 mwl8k_cmd_set_mac_addr(hw, vif->addr);
3171
b64fe619
LB
3172 if (priv->ap_fw)
3173 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3174
a66098da 3175 /* Clean out driver private area */
1ed32e4f 3176 mwl8k_vif = MWL8K_VIF(vif);
a66098da
LB
3177 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
3178
a66098da
LB
3179 /* Set Initial sequence number to zero */
3180 mwl8k_vif->seqno = 0;
3181
1ed32e4f 3182 priv->vif = vif;
a66098da
LB
3183
3184 return 0;
3185}
3186
3187static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3188 struct ieee80211_vif *vif)
a66098da
LB
3189{
3190 struct mwl8k_priv *priv = hw->priv;
3191
b64fe619
LB
3192 if (priv->ap_fw)
3193 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3194
55489b6e 3195 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 3196
a66098da
LB
3197 priv->vif = NULL;
3198}
3199
ee03a932 3200static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3201{
a66098da
LB
3202 struct ieee80211_conf *conf = &hw->conf;
3203 struct mwl8k_priv *priv = hw->priv;
ee03a932 3204 int rc;
a66098da 3205
7595d67a 3206 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3207 mwl8k_cmd_radio_disable(hw);
ee03a932 3208 return 0;
7595d67a
LB
3209 }
3210
ee03a932
LB
3211 rc = mwl8k_fw_lock(hw);
3212 if (rc)
3213 return rc;
a66098da 3214
55489b6e 3215 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB
3216 if (rc)
3217 goto out;
a66098da 3218
610677d2 3219 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB
3220 if (rc)
3221 goto out;
3222
a66098da
LB
3223 if (conf->power_level > 18)
3224 conf->power_level = 18;
55489b6e 3225 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB
3226 if (rc)
3227 goto out;
a66098da 3228
08b06347
LB
3229 if (priv->ap_fw) {
3230 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3231 if (!rc)
3232 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3233 } else {
3234 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3235 }
a66098da 3236
ee03a932
LB
3237out:
3238 mwl8k_fw_unlock(hw);
a66098da 3239
ee03a932 3240 return rc;
a66098da
LB
3241}
3242
b64fe619
LB
3243static void
3244mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3245 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3246{
a66098da 3247 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3248 u32 ap_legacy_rates;
13935e2c 3249 u8 ap_mcs_rates[16];
3a980d0a
LB
3250 int rc;
3251
c3cbbe8a 3252 if (mwl8k_fw_lock(hw))
3a980d0a 3253 return;
a66098da 3254
c3cbbe8a
LB
3255 /*
3256 * No need to capture a beacon if we're no longer associated.
3257 */
3258 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3259 priv->capture_beacon = false;
3a980d0a 3260
c3cbbe8a 3261 /*
13935e2c 3262 * Get the AP's legacy and MCS rates.
c3cbbe8a 3263 */
7dc6a7a7 3264 if (vif->bss_conf.assoc) {
c6e96010 3265 struct ieee80211_sta *ap;
c97470dd 3266
c6e96010 3267 rcu_read_lock();
c6e96010 3268
c3cbbe8a
LB
3269 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3270 if (ap == NULL) {
3271 rcu_read_unlock();
c6e96010 3272 goto out;
c3cbbe8a
LB
3273 }
3274
3275 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
13935e2c 3276 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB
3277
3278 rcu_read_unlock();
3279 }
c6e96010 3280
c3cbbe8a 3281 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3282 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB
3283 if (rc)
3284 goto out;
a66098da 3285
b71ed2c6 3286 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB
3287 if (rc)
3288 goto out;
c3cbbe8a 3289 }
a66098da 3290
c3cbbe8a 3291 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB
3292 rc = mwl8k_set_radio_preamble(hw,
3293 vif->bss_conf.use_short_preamble);
3a980d0a
LB
3294 if (rc)
3295 goto out;
c3cbbe8a 3296 }
a66098da 3297
c3cbbe8a 3298 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3299 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB
3300 if (rc)
3301 goto out;
c3cbbe8a 3302 }
a66098da 3303
c97470dd
LB
3304 if (vif->bss_conf.assoc &&
3305 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
3306 BSS_CHANGED_HT))) {
c3cbbe8a 3307 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB
3308 if (rc)
3309 goto out;
c3cbbe8a 3310 }
a66098da 3311
c3cbbe8a
LB
3312 if (vif->bss_conf.assoc &&
3313 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB
3314 /*
3315 * Finalize the join. Tell rx handler to process
3316 * next beacon from our BSSID.
3317 */
0a11dfc3 3318 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3319 priv->capture_beacon = true;
a66098da
LB
3320 }
3321
3a980d0a
LB
3322out:
3323 mwl8k_fw_unlock(hw);
a66098da
LB
3324}
3325
b64fe619
LB
3326static void
3327mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3328 struct ieee80211_bss_conf *info, u32 changed)
3329{
3330 int rc;
3331
3332 if (mwl8k_fw_lock(hw))
3333 return;
3334
3335 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3336 rc = mwl8k_set_radio_preamble(hw,
3337 vif->bss_conf.use_short_preamble);
3338 if (rc)
3339 goto out;
3340 }
3341
3342 if (changed & BSS_CHANGED_BASIC_RATES) {
3343 int idx;
3344 int rate;
3345
3346 /*
3347 * Use lowest supported basic rate for multicasts
3348 * and management frames (such as probe responses --
3349 * beacons will always go out at 1 Mb/s).
3350 */
3351 idx = ffs(vif->bss_conf.basic_rates);
3352 rate = idx ? mwl8k_rates[idx - 1].hw_value : 2;
3353
3354 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3355 }
3356
3357 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3358 struct sk_buff *skb;
3359
3360 skb = ieee80211_beacon_get(hw, vif);
3361 if (skb != NULL) {
3362 mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
3363 kfree_skb(skb);
3364 }
3365 }
3366
3367 if (changed & BSS_CHANGED_BEACON_ENABLED)
3368 mwl8k_cmd_bss_start(hw, info->enable_beacon);
3369
3370out:
3371 mwl8k_fw_unlock(hw);
3372}
3373
3374static void
3375mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3376 struct ieee80211_bss_conf *info, u32 changed)
3377{
3378 struct mwl8k_priv *priv = hw->priv;
3379
3380 if (!priv->ap_fw)
3381 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3382 else
3383 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3384}
3385
e81cd2d6
LB
3386static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3387 int mc_count, struct dev_addr_list *mclist)
3388{
3389 struct mwl8k_cmd_pkt *cmd;
3390
447ced07
LB
3391 /*
3392 * Synthesize and return a command packet that programs the
3393 * hardware multicast address filter. At this point we don't
3394 * know whether FIF_ALLMULTI is being requested, but if it is,
3395 * we'll end up throwing this packet away and creating a new
3396 * one in mwl8k_configure_filter().
3397 */
3398 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB
3399
3400 return (unsigned long)cmd;
3401}
3402
a43c49a8
LB
3403static int
3404mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3405 unsigned int changed_flags,
3406 unsigned int *total_flags)
3407{
3408 struct mwl8k_priv *priv = hw->priv;
3409
3410 /*
3411 * Hardware sniffer mode is mutually exclusive with STA
3412 * operation, so refuse to enable sniffer mode if a STA
3413 * interface is active.
3414 */
3415 if (priv->vif != NULL) {
3416 if (net_ratelimit())
3417 printk(KERN_INFO "%s: not enabling sniffer "
3418 "mode because STA interface is active\n",
3419 wiphy_name(hw->wiphy));
3420 return 0;
3421 }
3422
3423 if (!priv->sniffer_enabled) {
55489b6e 3424 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB
3425 return 0;
3426 priv->sniffer_enabled = true;
3427 }
3428
3429 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3430 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3431 FIF_OTHER_BSS;
3432
3433 return 1;
3434}
3435
e6935ea1
LB
3436static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3437 unsigned int changed_flags,
3438 unsigned int *total_flags,
3439 u64 multicast)
3440{
3441 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB
3442 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3443
c0adae2c
LB
3444 /*
3445 * AP firmware doesn't allow fine-grained control over
3446 * the receive filter.
3447 */
3448 if (priv->ap_fw) {
3449 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3450 kfree(cmd);
3451 return;
3452 }
3453
a43c49a8
LB
3454 /*
3455 * Enable hardware sniffer mode if FIF_CONTROL or
3456 * FIF_OTHER_BSS is requested.
3457 */
3458 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3459 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3460 kfree(cmd);
3461 return;
3462 }
a66098da 3463
e6935ea1 3464 /* Clear unsupported feature flags */
447ced07 3465 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3466
90852f7a
LB
3467 if (mwl8k_fw_lock(hw)) {
3468 kfree(cmd);
e6935ea1 3469 return;
90852f7a 3470 }
a66098da 3471
a43c49a8 3472 if (priv->sniffer_enabled) {
55489b6e 3473 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB
3474 priv->sniffer_enabled = false;
3475 }
3476
e6935ea1 3477 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB
3478 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3479 /*
3480 * Disable the BSS filter.
3481 */
e6935ea1 3482 mwl8k_cmd_set_pre_scan(hw);
77165d88 3483 } else {
0a11dfc3 3484 const u8 *bssid;
a94cc97e 3485
77165d88
LB
3486 /*
3487 * Enable the BSS filter.
3488 *
3489 * If there is an active STA interface, use that
3490 * interface's BSSID, otherwise use a dummy one
3491 * (where the OUI part needs to be nonzero for
3492 * the BSSID to be accepted by POST_SCAN).
3493 */
3494 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3495 if (priv->vif != NULL)
0a11dfc3 3496 bssid = priv->vif->bss_conf.bssid;
a94cc97e 3497
e6935ea1 3498 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB
3499 }
3500 }
3501
447ced07
LB
3502 /*
3503 * If FIF_ALLMULTI is being requested, throw away the command
3504 * packet that ->prepare_multicast() built and replace it with
3505 * a command packet that enables reception of all multicast
3506 * packets.
3507 */
3508 if (*total_flags & FIF_ALLMULTI) {
3509 kfree(cmd);
3510 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3511 }
3512
3513 if (cmd != NULL) {
3514 mwl8k_post_cmd(hw, cmd);
3515 kfree(cmd);
e6935ea1 3516 }
a66098da 3517
e6935ea1 3518 mwl8k_fw_unlock(hw);
a66098da
LB
3519}
3520
a66098da
LB
3521static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3522{
c2c2b12a 3523 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB
3524}
3525
bbfd9128
LB
3526struct mwl8k_sta_notify_item
3527{
3528 struct list_head list;
3529 struct ieee80211_vif *vif;
3530 enum sta_notify_cmd cmd;
13935e2c 3531 struct ieee80211_sta sta;
bbfd9128
LB
3532};
3533
3f5610ff
LB
3534static void
3535mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
3536{
3537 struct mwl8k_priv *priv = hw->priv;
3538
3539 /*
3540 * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
3541 */
3542 if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3543 int rc;
3544
3545 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
3546 if (rc >= 0) {
3547 struct ieee80211_sta *sta;
3548
3549 rcu_read_lock();
3550 sta = ieee80211_find_sta(s->vif, s->sta.addr);
3551 if (sta != NULL)
3552 MWL8K_STA(sta)->peer_id = rc;
3553 rcu_read_unlock();
3554 }
3555 } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3556 mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
3557 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3558 mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
3559 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3560 mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
3561 }
3562}
3563
bbfd9128
LB
3564static void mwl8k_sta_notify_worker(struct work_struct *work)
3565{
3566 struct mwl8k_priv *priv =
3567 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3568 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB
3569
3570 spin_lock_bh(&priv->sta_notify_list_lock);
3571 while (!list_empty(&priv->sta_notify_list)) {
3572 struct mwl8k_sta_notify_item *s;
bbfd9128
LB
3573
3574 s = list_entry(priv->sta_notify_list.next,
3575 struct mwl8k_sta_notify_item, list);
3576 list_del(&s->list);
3577
3578 spin_unlock_bh(&priv->sta_notify_list_lock);
3579
3f5610ff 3580 mwl8k_do_sta_notify(hw, s);
bbfd9128
LB
3581 kfree(s);
3582
3583 spin_lock_bh(&priv->sta_notify_list_lock);
3584 }
3585 spin_unlock_bh(&priv->sta_notify_list_lock);
3586}
3587
3588static void
3589mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3590 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3591{
3592 struct mwl8k_priv *priv = hw->priv;
3593 struct mwl8k_sta_notify_item *s;
3594
3595 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3596 return;
3597
3598 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3599 if (s != NULL) {
3600 s->vif = vif;
3601 s->cmd = cmd;
13935e2c 3602 s->sta = *sta;
bbfd9128
LB
3603
3604 spin_lock(&priv->sta_notify_list_lock);
3605 list_add_tail(&s->list, &priv->sta_notify_list);
3606 spin_unlock(&priv->sta_notify_list_lock);
3607
3608 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3609 }
3610}
3611
a66098da
LB
3612static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3613 const struct ieee80211_tx_queue_params *params)
3614{
3e4f542c 3615 struct mwl8k_priv *priv = hw->priv;
a66098da 3616 int rc;
a66098da 3617
3e4f542c
LB
3618 rc = mwl8k_fw_lock(hw);
3619 if (!rc) {
3620 if (!priv->wmm_enabled)
55489b6e 3621 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3622
3e4f542c 3623 if (!rc)
55489b6e
LB
3624 rc = mwl8k_cmd_set_edca_params(hw, queue,
3625 params->cw_min,
3626 params->cw_max,
3627 params->aifs,
3628 params->txop);
3e4f542c
LB
3629
3630 mwl8k_fw_unlock(hw);
a66098da 3631 }
3e4f542c 3632
a66098da
LB
3633 return rc;
3634}
3635
3636static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3637 struct ieee80211_tx_queue_stats *stats)
3638{
3639 struct mwl8k_priv *priv = hw->priv;
3640 struct mwl8k_tx_queue *txq;
3641 int index;
3642
3643 spin_lock_bh(&priv->tx_lock);
3644 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3645 txq = priv->txq + index;
45eb400d 3646 memcpy(&stats[index], &txq->stats,
a66098da
LB
3647 sizeof(struct ieee80211_tx_queue_stats));
3648 }
3649 spin_unlock_bh(&priv->tx_lock);
a66098da 3650
954ef509 3651 return 0;
a66098da
LB
3652}
3653
3654static int mwl8k_get_stats(struct ieee80211_hw *hw,
3655 struct ieee80211_low_level_stats *stats)
3656{
55489b6e 3657 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB
3658}
3659
a2292d83
LB
3660static int
3661mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3662 enum ieee80211_ampdu_mlme_action action,
3663 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3664{
3665 switch (action) {
3666 case IEEE80211_AMPDU_RX_START:
3667 case IEEE80211_AMPDU_RX_STOP:
3668 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
3669 return -ENOTSUPP;
3670 return 0;
3671 default:
3672 return -ENOTSUPP;
3673 }
3674}
3675
a66098da
LB
3676static const struct ieee80211_ops mwl8k_ops = {
3677 .tx = mwl8k_tx,
3678 .start = mwl8k_start,
3679 .stop = mwl8k_stop,
3680 .add_interface = mwl8k_add_interface,
3681 .remove_interface = mwl8k_remove_interface,
3682 .config = mwl8k_config,
a66098da 3683 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3684 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB
3685 .configure_filter = mwl8k_configure_filter,
3686 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3687 .sta_notify = mwl8k_sta_notify,
a66098da
LB
3688 .conf_tx = mwl8k_conf_tx,
3689 .get_tx_stats = mwl8k_get_tx_stats,
3690 .get_stats = mwl8k_get_stats,
a2292d83 3691 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB
3692};
3693
a66098da
LB
3694static void mwl8k_finalize_join_worker(struct work_struct *work)
3695{
3696 struct mwl8k_priv *priv =
3697 container_of(work, struct mwl8k_priv, finalize_join_worker);
3698 struct sk_buff *skb = priv->beacon_skb;
a66098da 3699
7dc6a7a7
LB
3700 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3701 priv->vif->bss_conf.dtim_period);
a66098da
LB
3702 dev_kfree_skb(skb);
3703
3704 priv->beacon_skb = NULL;
3705}
3706
bcb628d5 3707enum {
9e1b17ea
LB
3708 MWL8363 = 0,
3709 MWL8687,
bcb628d5 3710 MWL8366,
6f6d1e9a
LB
3711};
3712
bcb628d5 3713static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB
3714 [MWL8363] = {
3715 .part_name = "88w8363",
3716 .helper_image = "mwl8k/helper_8363.fw",
3717 .fw_image = "mwl8k/fmimage_8363.fw",
3718 },
49eb691c 3719 [MWL8687] = {
bcb628d5
JL
3720 .part_name = "88w8687",
3721 .helper_image = "mwl8k/helper_8687.fw",
3722 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3723 },
49eb691c 3724 [MWL8366] = {
bcb628d5
JL
3725 .part_name = "88w8366",
3726 .helper_image = "mwl8k/helper_8366.fw",
3727 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3728 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3729 },
45a390dd
LB
3730};
3731
c92d4ede
LB
3732MODULE_FIRMWARE("mwl8k/helper_8363.fw");
3733MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
3734MODULE_FIRMWARE("mwl8k/helper_8687.fw");
3735MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
3736MODULE_FIRMWARE("mwl8k/helper_8366.fw");
3737MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
3738
45a390dd 3739static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
9e1b17ea
LB
3740 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
3741 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL
3742 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3743 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3744 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
3745 { },
45a390dd
LB
3746};
3747MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3748
a66098da
LB
3749static int __devinit mwl8k_probe(struct pci_dev *pdev,
3750 const struct pci_device_id *id)
3751{
2aa7b01f 3752 static int printed_version = 0;
a66098da
LB
3753 struct ieee80211_hw *hw;
3754 struct mwl8k_priv *priv;
a66098da
LB
3755 int rc;
3756 int i;
2aa7b01f
LB
3757
3758 if (!printed_version) {
3759 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3760 printed_version = 1;
3761 }
a66098da 3762
be695fc4 3763
a66098da
LB
3764 rc = pci_enable_device(pdev);
3765 if (rc) {
3766 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3767 MWL8K_NAME);
3768 return rc;
3769 }
3770
3771 rc = pci_request_regions(pdev, MWL8K_NAME);
3772 if (rc) {
3773 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3774 MWL8K_NAME);
3db95e50 3775 goto err_disable_device;
a66098da
LB
3776 }
3777
3778 pci_set_master(pdev);
3779
be695fc4 3780
a66098da
LB
3781 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3782 if (hw == NULL) {
3783 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3784 rc = -ENOMEM;
3785 goto err_free_reg;
3786 }
3787
be695fc4
LB
3788 SET_IEEE80211_DEV(hw, &pdev->dev);
3789 pci_set_drvdata(pdev, hw);
3790
a66098da
LB
3791 priv = hw->priv;
3792 priv->hw = hw;
3793 priv->pdev = pdev;
bcb628d5 3794 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3795
a66098da 3796
5b9482dd
LB
3797 priv->sram = pci_iomap(pdev, 0, 0x10000);
3798 if (priv->sram == NULL) {
3799 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3800 wiphy_name(hw->wiphy));
a66098da
LB
3801 goto err_iounmap;
3802 }
3803
5b9482dd
LB
3804 /*
3805 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3806 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3807 */
3808 priv->regs = pci_iomap(pdev, 1, 0x10000);
3809 if (priv->regs == NULL) {
3810 priv->regs = pci_iomap(pdev, 2, 0x10000);
3811 if (priv->regs == NULL) {
3812 printk(KERN_ERR "%s: Cannot map device registers\n",
3813 wiphy_name(hw->wiphy));
3814 goto err_iounmap;
3815 }
3816 }
3817
be695fc4
LB
3818
3819 /* Reset firmware and hardware */
3820 mwl8k_hw_reset(priv);
3821
3822 /* Ask userland hotplug daemon for the device firmware */
3823 rc = mwl8k_request_firmware(priv);
3824 if (rc) {
3825 printk(KERN_ERR "%s: Firmware files not found\n",
3826 wiphy_name(hw->wiphy));
3827 goto err_stop_firmware;
3828 }
3829
3830 /* Load firmware into hardware */
3831 rc = mwl8k_load_firmware(hw);
3832 if (rc) {
3833 printk(KERN_ERR "%s: Cannot start firmware\n",
3834 wiphy_name(hw->wiphy));
3835 goto err_stop_firmware;
3836 }
3837
3838 /* Reclaim memory once firmware is successfully loaded */
3839 mwl8k_release_firmware(priv);
3840
3841
91942230 3842 if (priv->ap_fw) {
89a91f4f 3843 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB
3844 if (priv->rxd_ops == NULL) {
3845 printk(KERN_ERR "%s: Driver does not have AP "
3846 "firmware image support for this hardware\n",
3847 wiphy_name(hw->wiphy));
3848 goto err_stop_firmware;
3849 }
3850 } else {
89a91f4f 3851 priv->rxd_ops = &rxd_sta_ops;
91942230 3852 }
be695fc4
LB
3853
3854 priv->sniffer_enabled = false;
3855 priv->wmm_enabled = false;
3856 priv->pending_tx_pkts = 0;
3857
3858
a66098da
LB
3859 memcpy(priv->channels, mwl8k_channels, sizeof(mwl8k_channels));
3860 priv->band.band = IEEE80211_BAND_2GHZ;
3861 priv->band.channels = priv->channels;
3862 priv->band.n_channels = ARRAY_SIZE(mwl8k_channels);
3863 priv->band.bitrates = priv->rates;
3864 priv->band.n_bitrates = ARRAY_SIZE(mwl8k_rates);
3865 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
3866
3867 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(mwl8k_rates));
3868 memcpy(priv->rates, mwl8k_rates, sizeof(mwl8k_rates));
3869
3870 /*
3871 * Extra headroom is the size of the required DMA header
3872 * minus the size of the smallest 802.11 frame (CTS frame).
3873 */
3874 hw->extra_tx_headroom =
3875 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
3876
3877 hw->channel_change_time = 10;
3878
3879 hw->queues = MWL8K_TX_QUEUES;
3880
a66098da 3881 /* Set rssi and noise values to dBm */
ce9e2e1b 3882 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 3883 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 3884 hw->sta_data_size = sizeof(struct mwl8k_sta);
a66098da
LB
3885 priv->vif = NULL;
3886
3887 /* Set default radio state and preamble */
c46563b7 3888 priv->radio_on = 0;
68ce3884 3889 priv->radio_short_preamble = 0;
a66098da 3890
bbfd9128
LB
3891 /* Station database handling */
3892 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
3893 spin_lock_init(&priv->sta_notify_list_lock);
3894 INIT_LIST_HEAD(&priv->sta_notify_list);
3895
a66098da
LB
3896 /* Finalize join worker */
3897 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
3898
67e2eb27 3899 /* TX reclaim and RX tasklets. */
1e9f9de3
LB
3900 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
3901 tasklet_disable(&priv->poll_tx_task);
67e2eb27
LB
3902 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
3903 tasklet_disable(&priv->poll_rx_task);
a66098da 3904
a66098da
LB
3905 /* Power management cookie */
3906 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
3907 if (priv->cookie == NULL)
be695fc4 3908 goto err_stop_firmware;
a66098da
LB
3909
3910 rc = mwl8k_rxq_init(hw, 0);
3911 if (rc)
be695fc4 3912 goto err_free_cookie;
a66098da
LB
3913 rxq_refill(hw, 0, INT_MAX);
3914
618952a7
LB
3915 mutex_init(&priv->fw_mutex);
3916 priv->fw_mutex_owner = NULL;
3917 priv->fw_mutex_depth = 0;
618952a7
LB
3918 priv->hostcmd_wait = NULL;
3919
a66098da
LB
3920 spin_lock_init(&priv->tx_lock);
3921
88de754a
LB
3922 priv->tx_wait = NULL;
3923
a66098da
LB
3924 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
3925 rc = mwl8k_txq_init(hw, i);
3926 if (rc)
3927 goto err_free_queues;
3928 }
3929
3930 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 3931 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 3932 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 3933 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB
3934 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
3935
a0607fd3 3936 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB
3937 IRQF_SHARED, MWL8K_NAME, hw);
3938 if (rc) {
3939 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3940 wiphy_name(hw->wiphy));
a66098da
LB
3941 goto err_free_queues;
3942 }
3943
a66098da
LB
3944 /*
3945 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 3946 * commands use interrupts and avoid polling. Disable
a66098da
LB
3947 * interrupts when done.
3948 */
c23b5a69 3949 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
3950
3951 /* Get config data, mac addrs etc */
42fba21d
LB
3952 if (priv->ap_fw) {
3953 rc = mwl8k_cmd_get_hw_spec_ap(hw);
3954 if (!rc)
3955 rc = mwl8k_cmd_set_hw_spec(hw);
b64fe619
LB
3956
3957 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
42fba21d
LB
3958 } else {
3959 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB
3960
3961 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 3962 }
a66098da 3963 if (rc) {
c2c357ce
LB
3964 printk(KERN_ERR "%s: Cannot initialise firmware\n",
3965 wiphy_name(hw->wiphy));
be695fc4 3966 goto err_free_irq;
a66098da
LB
3967 }
3968
3969 /* Turn radio off */
55489b6e 3970 rc = mwl8k_cmd_radio_disable(hw);
a66098da 3971 if (rc) {
c2c357ce 3972 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 3973 goto err_free_irq;
a66098da
LB
3974 }
3975
32060e1b 3976 /* Clear MAC address */
55489b6e 3977 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB
3978 if (rc) {
3979 printk(KERN_ERR "%s: Cannot clear MAC address\n",
3980 wiphy_name(hw->wiphy));
be695fc4 3981 goto err_free_irq;
32060e1b
LB
3982 }
3983
a66098da 3984 /* Disable interrupts */
a66098da 3985 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
3986 free_irq(priv->pdev->irq, hw);
3987
3988 rc = ieee80211_register_hw(hw);
3989 if (rc) {
c2c357ce
LB
3990 printk(KERN_ERR "%s: Cannot register device\n",
3991 wiphy_name(hw->wiphy));
153458ff 3992 goto err_free_queues;
a66098da
LB
3993 }
3994
eae74e65 3995 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 3996 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 3997 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 3998 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB
3999 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
4000 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB
4001
4002 return 0;
4003
a66098da 4004err_free_irq:
a66098da 4005 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB
4006 free_irq(priv->pdev->irq, hw);
4007
4008err_free_queues:
4009 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4010 mwl8k_txq_deinit(hw, i);
4011 mwl8k_rxq_deinit(hw, 0);
4012
be695fc4 4013err_free_cookie:
a66098da
LB
4014 if (priv->cookie != NULL)
4015 pci_free_consistent(priv->pdev, 4,
4016 priv->cookie, priv->cookie_dma);
4017
be695fc4
LB
4018err_stop_firmware:
4019 mwl8k_hw_reset(priv);
4020 mwl8k_release_firmware(priv);
4021
4022err_iounmap:
a66098da
LB
4023 if (priv->regs != NULL)
4024 pci_iounmap(pdev, priv->regs);
4025
5b9482dd
LB
4026 if (priv->sram != NULL)
4027 pci_iounmap(pdev, priv->sram);
4028
a66098da
LB
4029 pci_set_drvdata(pdev, NULL);
4030 ieee80211_free_hw(hw);
4031
4032err_free_reg:
4033 pci_release_regions(pdev);
3db95e50
LB
4034
4035err_disable_device:
a66098da
LB
4036 pci_disable_device(pdev);
4037
4038 return rc;
4039}
4040
230f7af0 4041static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB
4042{
4043 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4044}
4045
230f7af0 4046static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB
4047{
4048 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4049 struct mwl8k_priv *priv;
4050 int i;
4051
4052 if (hw == NULL)
4053 return;
4054 priv = hw->priv;
4055
4056 ieee80211_stop_queues(hw);
4057
60aa569f
LB
4058 ieee80211_unregister_hw(hw);
4059
67e2eb27 4060 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4061 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4062 tasklet_kill(&priv->poll_rx_task);
a66098da 4063
a66098da
LB
4064 /* Stop hardware */
4065 mwl8k_hw_reset(priv);
4066
4067 /* Return all skbs to mac80211 */
4068 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4069 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4070
a66098da
LB
4071 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4072 mwl8k_txq_deinit(hw, i);
4073
4074 mwl8k_rxq_deinit(hw, 0);
4075
c2c357ce 4076 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB
4077
4078 pci_iounmap(pdev, priv->regs);
5b9482dd 4079 pci_iounmap(pdev, priv->sram);
a66098da
LB
4080 pci_set_drvdata(pdev, NULL);
4081 ieee80211_free_hw(hw);
4082 pci_release_regions(pdev);
4083 pci_disable_device(pdev);
4084}
4085
4086static struct pci_driver mwl8k_driver = {
4087 .name = MWL8K_NAME,
45a390dd 4088 .id_table = mwl8k_pci_id_table,
a66098da
LB
4089 .probe = mwl8k_probe,
4090 .remove = __devexit_p(mwl8k_remove),
4091 .shutdown = __devexit_p(mwl8k_shutdown),
4092};
4093
4094static int __init mwl8k_init(void)
4095{
4096 return pci_register_driver(&mwl8k_driver);
4097}
4098
4099static void __exit mwl8k_exit(void)
4100{
4101 pci_unregister_driver(&mwl8k_driver);
4102}
4103
4104module_init(mwl8k_init);
4105module_exit(mwl8k_exit);
c2c357ce
LB
4106
4107MODULE_DESCRIPTION(MWL8K_DESC);
4108MODULE_VERSION(MWL8K_VERSION);
4109MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4110MODULE_LICENSE("GPL");
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