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mwl8k: prepare for posting per-vif firmware commands
[deliverable/linux.git] / drivers / net / wireless / mwl8k.c
CommitLineData
a66098da 1/*
ce9e2e1b
LB		 2 * drivers/net/wireless/mwl8k.c
3 * Driver for Marvell TOPDOG 802.11 Wireless cards
a66098da 4 *
a145d575 5 * Copyright (C) 2008-2009 Marvell Semiconductor Inc.
a66098da
LB		 6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
3d76e82c 15#include <linux/sched.h>
a66098da
LB		 16#include <linux/spinlock.h>
17#include <linux/list.h>
18#include <linux/pci.h>
19#include <linux/delay.h>
20#include <linux/completion.h>
21#include <linux/etherdevice.h>
22#include <net/mac80211.h>
23#include <linux/moduleparam.h>
24#include <linux/firmware.h>
25#include <linux/workqueue.h>
26
27#define MWL8K_DESC "Marvell TOPDOG(R) 802.11 Wireless Network Driver"
28#define MWL8K_NAME KBUILD_MODNAME
6976b665 29#define MWL8K_VERSION "0.11"
a66098da 30
a66098da
LB		 31/* Register definitions */
32#define MWL8K_HIU_GEN_PTR 0x00000c10
ce9e2e1b
LB		 33#define MWL8K_MODE_STA 0x0000005a
34#define MWL8K_MODE_AP 0x000000a5
a66098da 35#define MWL8K_HIU_INT_CODE 0x00000c14
ce9e2e1b
LB		 36#define MWL8K_FWSTA_READY 0xf0f1f2f4
37#define MWL8K_FWAP_READY 0xf1f2f4a5
38#define MWL8K_INT_CODE_CMD_FINISHED 0x00000005
a66098da
LB		 39#define MWL8K_HIU_SCRATCH 0x00000c40
40
41/* Host->device communications */
42#define MWL8K_HIU_H2A_INTERRUPT_EVENTS 0x00000c18
43#define MWL8K_HIU_H2A_INTERRUPT_STATUS 0x00000c1c
44#define MWL8K_HIU_H2A_INTERRUPT_MASK 0x00000c20
45#define MWL8K_HIU_H2A_INTERRUPT_CLEAR_SEL 0x00000c24
46#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
ce9e2e1b
LB		 47#define MWL8K_H2A_INT_DUMMY (1 << 20)
48#define MWL8K_H2A_INT_RESET (1 << 15)
49#define MWL8K_H2A_INT_DOORBELL (1 << 1)
50#define MWL8K_H2A_INT_PPA_READY (1 << 0)
a66098da
LB		 51
52/* Device->host communications */
53#define MWL8K_HIU_A2H_INTERRUPT_EVENTS 0x00000c2c
54#define MWL8K_HIU_A2H_INTERRUPT_STATUS 0x00000c30
55#define MWL8K_HIU_A2H_INTERRUPT_MASK 0x00000c34
56#define MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL 0x00000c38
57#define MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK 0x00000c3c
ce9e2e1b
LB		 58#define MWL8K_A2H_INT_DUMMY (1 << 20)
59#define MWL8K_A2H_INT_CHNL_SWITCHED (1 << 11)
60#define MWL8K_A2H_INT_QUEUE_EMPTY (1 << 10)
61#define MWL8K_A2H_INT_RADAR_DETECT (1 << 7)
62#define MWL8K_A2H_INT_RADIO_ON (1 << 6)
63#define MWL8K_A2H_INT_RADIO_OFF (1 << 5)
64#define MWL8K_A2H_INT_MAC_EVENT (1 << 3)
65#define MWL8K_A2H_INT_OPC_DONE (1 << 2)
66#define MWL8K_A2H_INT_RX_READY (1 << 1)
67#define MWL8K_A2H_INT_TX_DONE (1 << 0)
a66098da
LB		 68
69#define MWL8K_A2H_EVENTS (MWL8K_A2H_INT_DUMMY | \
70 MWL8K_A2H_INT_CHNL_SWITCHED | \
71 MWL8K_A2H_INT_QUEUE_EMPTY | \
72 MWL8K_A2H_INT_RADAR_DETECT | \
73 MWL8K_A2H_INT_RADIO_ON | \
74 MWL8K_A2H_INT_RADIO_OFF | \
75 MWL8K_A2H_INT_MAC_EVENT | \
76 MWL8K_A2H_INT_OPC_DONE | \
77 MWL8K_A2H_INT_RX_READY | \
78 MWL8K_A2H_INT_TX_DONE)
79
a66098da
LB		 80#define MWL8K_RX_QUEUES 1
81#define MWL8K_TX_QUEUES 4
82
54bc3a0d
LB		 83struct rxd_ops {
84 int rxd_size;
85 void (*rxd_init)(void *rxd, dma_addr_t next_dma_addr);
86 void (*rxd_refill)(void *rxd, dma_addr_t addr, int len);
20f09c3d
LB		 87 int (*rxd_process)(void *rxd, struct ieee80211_rx_status *status,
88 __le16 *qos);
54bc3a0d
LB		 89};
90
45a390dd 91struct mwl8k_device_info {
a74b295e
LB		 92 char *part_name;
93 char *helper_image;
94 char *fw_image;
89a91f4f 95 struct rxd_ops *ap_rxd_ops;
45a390dd
LB		 96};
97
a66098da 98struct mwl8k_rx_queue {
45eb400d 99 int rxd_count;
a66098da
LB		 100
101 /* hw receives here */
45eb400d 102 int head;
a66098da
LB		 103
104 /* refill descs here */
45eb400d 105 int tail;
a66098da 106
54bc3a0d 107 void *rxd;
45eb400d 108 dma_addr_t rxd_dma;
788838eb
LB		 109 struct {
110 struct sk_buff *skb;
111 DECLARE_PCI_UNMAP_ADDR(dma)
112 } *buf;
a66098da
LB		 113};
114
a66098da
LB		 115struct mwl8k_tx_queue {
116 /* hw transmits here */
45eb400d 117 int head;
a66098da
LB		 118
119 /* sw appends here */
45eb400d 120 int tail;
a66098da 121
45eb400d
LB		 122 struct ieee80211_tx_queue_stats stats;
123 struct mwl8k_tx_desc *txd;
124 dma_addr_t txd_dma;
125 struct sk_buff **skb;
a66098da
LB		 126};
127
a66098da 128struct mwl8k_priv {
a66098da 129 struct ieee80211_hw *hw;
a66098da 130 struct pci_dev *pdev;
a66098da 131
45a390dd
LB		 132 struct mwl8k_device_info *device_info;
133
be695fc4
LB		 134 void __iomem *sram;
135 void __iomem *regs;
136
137 /* firmware */
22be40d9
LB		 138 struct firmware *fw_helper;
139 struct firmware *fw_ucode;
a66098da 140
be695fc4
LB		 141 /* hardware/firmware parameters */
142 bool ap_fw;
143 struct rxd_ops *rxd_ops;
777ad375
LB		 144 struct ieee80211_supported_band band_24;
145 struct ieee80211_channel channels_24[14];
146 struct ieee80211_rate rates_24[14];
4eae9edd
LB		 147 struct ieee80211_supported_band band_50;
148 struct ieee80211_channel channels_50[4];
149 struct ieee80211_rate rates_50[9];
be695fc4 150
618952a7
LB		 151 /* firmware access */
152 struct mutex fw_mutex;
153 struct task_struct *fw_mutex_owner;
154 int fw_mutex_depth;
618952a7
LB		 155 struct completion *hostcmd_wait;
156
a66098da
LB		 157 /* lock held over TX and TX reap */
158 spinlock_t tx_lock;
a66098da 159
88de754a
LB		 160 /* TX quiesce completion, protected by fw_mutex and tx_lock */
161 struct completion *tx_wait;
162
f5bb87cf
LB		 163 /* List of interfaces. */
164 struct list_head vif_list;
a66098da 165
a66098da
LB		 166 /* power management status cookie from firmware */
167 u32 *cookie;
168 dma_addr_t cookie_dma;
169
170 u16 num_mcaddrs;
a66098da 171 u8 hw_rev;
2aa7b01f 172 u32 fw_rev;
a66098da
LB		 173
174 /*
175 * Running count of TX packets in flight, to avoid
176 * iterating over the transmit rings each time.
177 */
178 int pending_tx_pkts;
179
180 struct mwl8k_rx_queue rxq[MWL8K_RX_QUEUES];
181 struct mwl8k_tx_queue txq[MWL8K_TX_QUEUES];
182
c46563b7 183 bool radio_on;
68ce3884 184 bool radio_short_preamble;
a43c49a8 185 bool sniffer_enabled;
0439b1f5 186 bool wmm_enabled;
a66098da 187
bbfd9128
LB		 188 struct work_struct sta_notify_worker;
189 spinlock_t sta_notify_list_lock;
190 struct list_head sta_notify_list;
191
a66098da
LB		 192 /* XXX need to convert this to handle multiple interfaces */
193 bool capture_beacon;
d89173f2 194 u8 capture_bssid[ETH_ALEN];
a66098da
LB		 195 struct sk_buff *beacon_skb;
196
197 /*
198 * This FJ worker has to be global as it is scheduled from the
199 * RX handler. At this point we don't know which interface it
200 * belongs to until the list of bssids waiting to complete join
201 * is checked.
202 */
203 struct work_struct finalize_join_worker;
204
1e9f9de3
LB		 205 /* Tasklet to perform TX reclaim. */
206 struct tasklet_struct poll_tx_task;
67e2eb27
LB		 207
208 /* Tasklet to perform RX. */
209 struct tasklet_struct poll_rx_task;
a66098da
LB		 210};
211
212/* Per interface specific private data */
213struct mwl8k_vif {
f5bb87cf
LB		 214 struct list_head list;
215 struct ieee80211_vif *vif;
216
f57ca9c1
LB		 217 /* Firmware macid for this vif. */
218 int macid;
219
c2c2b12a 220 /* Non AMPDU sequence number assigned by driver. */
a680400e 221 u16 seqno;
a66098da 222};
a94cc97e 223#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
a66098da 224
a680400e
LB		 225struct mwl8k_sta {
226 /* Index into station database. Returned by UPDATE_STADB. */
227 u8 peer_id;
228};
229#define MWL8K_STA(_sta) ((struct mwl8k_sta *)&((_sta)->drv_priv))
230
777ad375 231static const struct ieee80211_channel mwl8k_channels_24[] = {
a66098da
LB		 232 { .center_freq = 2412, .hw_value = 1, },
233 { .center_freq = 2417, .hw_value = 2, },
234 { .center_freq = 2422, .hw_value = 3, },
235 { .center_freq = 2427, .hw_value = 4, },
236 { .center_freq = 2432, .hw_value = 5, },
237 { .center_freq = 2437, .hw_value = 6, },
238 { .center_freq = 2442, .hw_value = 7, },
239 { .center_freq = 2447, .hw_value = 8, },
240 { .center_freq = 2452, .hw_value = 9, },
241 { .center_freq = 2457, .hw_value = 10, },
242 { .center_freq = 2462, .hw_value = 11, },
647ca6b0
LB		 243 { .center_freq = 2467, .hw_value = 12, },
244 { .center_freq = 2472, .hw_value = 13, },
245 { .center_freq = 2484, .hw_value = 14, },
a66098da
LB		 246};
247
777ad375 248static const struct ieee80211_rate mwl8k_rates_24[] = {
a66098da
LB		 249 { .bitrate = 10, .hw_value = 2, },
250 { .bitrate = 20, .hw_value = 4, },
251 { .bitrate = 55, .hw_value = 11, },
5dfd3e2c
LB		 252 { .bitrate = 110, .hw_value = 22, },
253 { .bitrate = 220, .hw_value = 44, },
a66098da
LB		 254 { .bitrate = 60, .hw_value = 12, },
255 { .bitrate = 90, .hw_value = 18, },
a66098da
LB		 256 { .bitrate = 120, .hw_value = 24, },
257 { .bitrate = 180, .hw_value = 36, },
258 { .bitrate = 240, .hw_value = 48, },
259 { .bitrate = 360, .hw_value = 72, },
260 { .bitrate = 480, .hw_value = 96, },
261 { .bitrate = 540, .hw_value = 108, },
140eb5e2
LB		 262 { .bitrate = 720, .hw_value = 144, },
263};
264
4eae9edd
LB		 265static const struct ieee80211_channel mwl8k_channels_50[] = {
266 { .center_freq = 5180, .hw_value = 36, },
267 { .center_freq = 5200, .hw_value = 40, },
268 { .center_freq = 5220, .hw_value = 44, },
269 { .center_freq = 5240, .hw_value = 48, },
270};
271
272static const struct ieee80211_rate mwl8k_rates_50[] = {
273 { .bitrate = 60, .hw_value = 12, },
274 { .bitrate = 90, .hw_value = 18, },
275 { .bitrate = 120, .hw_value = 24, },
276 { .bitrate = 180, .hw_value = 36, },
277 { .bitrate = 240, .hw_value = 48, },
278 { .bitrate = 360, .hw_value = 72, },
279 { .bitrate = 480, .hw_value = 96, },
280 { .bitrate = 540, .hw_value = 108, },
281 { .bitrate = 720, .hw_value = 144, },
282};
283
a66098da
LB		 284/* Set or get info from Firmware */
285#define MWL8K_CMD_SET 0x0001
286#define MWL8K_CMD_GET 0x0000
287
288/* Firmware command codes */
289#define MWL8K_CMD_CODE_DNLD 0x0001
290#define MWL8K_CMD_GET_HW_SPEC 0x0003
42fba21d 291#define MWL8K_CMD_SET_HW_SPEC 0x0004
a66098da
LB		 292#define MWL8K_CMD_MAC_MULTICAST_ADR 0x0010
293#define MWL8K_CMD_GET_STAT 0x0014
ff45fc60
LB		 294#define MWL8K_CMD_RADIO_CONTROL 0x001c
295#define MWL8K_CMD_RF_TX_POWER 0x001e
08b06347 296#define MWL8K_CMD_RF_ANTENNA 0x0020
b64fe619 297#define MWL8K_CMD_SET_BEACON 0x0100
a66098da
LB		 298#define MWL8K_CMD_SET_PRE_SCAN 0x0107
299#define MWL8K_CMD_SET_POST_SCAN 0x0108
ff45fc60
LB		 300#define MWL8K_CMD_SET_RF_CHANNEL 0x010a
301#define MWL8K_CMD_SET_AID 0x010d
302#define MWL8K_CMD_SET_RATE 0x0110
303#define MWL8K_CMD_SET_FINALIZE_JOIN 0x0111
304#define MWL8K_CMD_RTS_THRESHOLD 0x0113
a66098da 305#define MWL8K_CMD_SET_SLOT 0x0114
ff45fc60
LB		 306#define MWL8K_CMD_SET_EDCA_PARAMS 0x0115
307#define MWL8K_CMD_SET_WMM_MODE 0x0123
a66098da 308#define MWL8K_CMD_MIMO_CONFIG 0x0125
ff45fc60 309#define MWL8K_CMD_USE_FIXED_RATE 0x0126
a66098da 310#define MWL8K_CMD_ENABLE_SNIFFER 0x0150
32060e1b 311#define MWL8K_CMD_SET_MAC_ADDR 0x0202
a66098da 312#define MWL8K_CMD_SET_RATEADAPT_MODE 0x0203
b64fe619 313#define MWL8K_CMD_BSS_START 0x1100
3f5610ff 314#define MWL8K_CMD_SET_NEW_STN 0x1111
ff45fc60 315#define MWL8K_CMD_UPDATE_STADB 0x1123
a66098da
LB		 316
317static const char *mwl8k_cmd_name(u16 cmd, char *buf, int bufsize)
318{
319#define MWL8K_CMDNAME(x) case MWL8K_CMD_##x: do {\
320 snprintf(buf, bufsize, "%s", #x);\
321 return buf;\
322 } while (0)
ce9e2e1b 323 switch (cmd & ~0x8000) {
a66098da
LB		 324 MWL8K_CMDNAME(CODE_DNLD);
325 MWL8K_CMDNAME(GET_HW_SPEC);
42fba21d 326 MWL8K_CMDNAME(SET_HW_SPEC);
a66098da
LB		 327 MWL8K_CMDNAME(MAC_MULTICAST_ADR);
328 MWL8K_CMDNAME(GET_STAT);
329 MWL8K_CMDNAME(RADIO_CONTROL);
330 MWL8K_CMDNAME(RF_TX_POWER);
08b06347 331 MWL8K_CMDNAME(RF_ANTENNA);
b64fe619 332 MWL8K_CMDNAME(SET_BEACON);
a66098da
LB		 333 MWL8K_CMDNAME(SET_PRE_SCAN);
334 MWL8K_CMDNAME(SET_POST_SCAN);
335 MWL8K_CMDNAME(SET_RF_CHANNEL);
ff45fc60
LB		 336 MWL8K_CMDNAME(SET_AID);
337 MWL8K_CMDNAME(SET_RATE);
338 MWL8K_CMDNAME(SET_FINALIZE_JOIN);
339 MWL8K_CMDNAME(RTS_THRESHOLD);
a66098da 340 MWL8K_CMDNAME(SET_SLOT);
ff45fc60
LB		 341 MWL8K_CMDNAME(SET_EDCA_PARAMS);
342 MWL8K_CMDNAME(SET_WMM_MODE);
a66098da 343 MWL8K_CMDNAME(MIMO_CONFIG);
ff45fc60 344 MWL8K_CMDNAME(USE_FIXED_RATE);
a66098da 345 MWL8K_CMDNAME(ENABLE_SNIFFER);
32060e1b 346 MWL8K_CMDNAME(SET_MAC_ADDR);
a66098da 347 MWL8K_CMDNAME(SET_RATEADAPT_MODE);
b64fe619 348 MWL8K_CMDNAME(BSS_START);
3f5610ff 349 MWL8K_CMDNAME(SET_NEW_STN);
ff45fc60 350 MWL8K_CMDNAME(UPDATE_STADB);
a66098da
LB		 351 default:
352 snprintf(buf, bufsize, "0x%x", cmd);
353 }
354#undef MWL8K_CMDNAME
355
356 return buf;
357}
358
359/* Hardware and firmware reset */
360static void mwl8k_hw_reset(struct mwl8k_priv *priv)
361{
362 iowrite32(MWL8K_H2A_INT_RESET,
363 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
364 iowrite32(MWL8K_H2A_INT_RESET,
365 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
366 msleep(20);
367}
368
369/* Release fw image */
370static void mwl8k_release_fw(struct firmware **fw)
371{
372 if (*fw == NULL)
373 return;
374 release_firmware(*fw);
375 *fw = NULL;
376}
377
378static void mwl8k_release_firmware(struct mwl8k_priv *priv)
379{
22be40d9
LB		 380 mwl8k_release_fw(&priv->fw_ucode);
381 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 382}
383
384/* Request fw image */
385static int mwl8k_request_fw(struct mwl8k_priv *priv,
c2c357ce 386 const char *fname, struct firmware **fw)
a66098da
LB		 387{
388 /* release current image */
389 if (*fw != NULL)
390 mwl8k_release_fw(fw);
391
392 return request_firmware((const struct firmware **)fw,
c2c357ce 393 fname, &priv->pdev->dev);
a66098da
LB		 394}
395
45a390dd 396static int mwl8k_request_firmware(struct mwl8k_priv *priv)
a66098da 397{
a74b295e 398 struct mwl8k_device_info *di = priv->device_info;
a66098da
LB		 399 int rc;
400
a74b295e 401 if (di->helper_image != NULL) {
22be40d9 402 rc = mwl8k_request_fw(priv, di->helper_image, &priv->fw_helper);
a74b295e
LB		 403 if (rc) {
404 printk(KERN_ERR "%s: Error requesting helper "
405 "firmware file %s\n", pci_name(priv->pdev),
406 di->helper_image);
407 return rc;
408 }
a66098da
LB		 409 }
410
22be40d9 411 rc = mwl8k_request_fw(priv, di->fw_image, &priv->fw_ucode);
a66098da 412 if (rc) {
c2c357ce 413 printk(KERN_ERR "%s: Error requesting firmware file %s\n",
a74b295e 414 pci_name(priv->pdev), di->fw_image);
22be40d9 415 mwl8k_release_fw(&priv->fw_helper);
a66098da
LB		 416 return rc;
417 }
418
419 return 0;
420}
421
422struct mwl8k_cmd_pkt {
423 __le16 code;
424 __le16 length;
f57ca9c1
LB		 425 __u8 seq_num;
426 __u8 macid;
a66098da
LB		 427 __le16 result;
428 char payload[0];
429} __attribute__((packed));
430
431/*
432 * Firmware loading.
433 */
434static int
435mwl8k_send_fw_load_cmd(struct mwl8k_priv *priv, void *data, int length)
436{
437 void __iomem *regs = priv->regs;
438 dma_addr_t dma_addr;
a66098da
LB		 439 int loops;
440
441 dma_addr = pci_map_single(priv->pdev, data, length, PCI_DMA_TODEVICE);
442 if (pci_dma_mapping_error(priv->pdev, dma_addr))
443 return -ENOMEM;
444
445 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
446 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
447 iowrite32(MWL8K_H2A_INT_DOORBELL,
448 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
449 iowrite32(MWL8K_H2A_INT_DUMMY,
450 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
451
a66098da
LB		 452 loops = 1000;
453 do {
454 u32 int_code;
455
456 int_code = ioread32(regs + MWL8K_HIU_INT_CODE);
457 if (int_code == MWL8K_INT_CODE_CMD_FINISHED) {
458 iowrite32(0, regs + MWL8K_HIU_INT_CODE);
a66098da
LB		 459 break;
460 }
461
3d76e82c 462 cond_resched();
a66098da
LB		 463 udelay(1);
464 } while (--loops);
465
466 pci_unmap_single(priv->pdev, dma_addr, length, PCI_DMA_TODEVICE);
467
d4b70570 468 return loops ? 0 : -ETIMEDOUT;
a66098da
LB		 469}
470
471static int mwl8k_load_fw_image(struct mwl8k_priv *priv,
472 const u8 *data, size_t length)
473{
474 struct mwl8k_cmd_pkt *cmd;
475 int done;
476 int rc = 0;
477
478 cmd = kmalloc(sizeof(*cmd) + 256, GFP_KERNEL);
479 if (cmd == NULL)
480 return -ENOMEM;
481
482 cmd->code = cpu_to_le16(MWL8K_CMD_CODE_DNLD);
483 cmd->seq_num = 0;
f57ca9c1 484 cmd->macid = 0;
a66098da
LB		 485 cmd->result = 0;
486
487 done = 0;
488 while (length) {
489 int block_size = length > 256 ? 256 : length;
490
491 memcpy(cmd->payload, data + done, block_size);
492 cmd->length = cpu_to_le16(block_size);
493
494 rc = mwl8k_send_fw_load_cmd(priv, cmd,
495 sizeof(*cmd) + block_size);
496 if (rc)
497 break;
498
499 done += block_size;
500 length -= block_size;
501 }
502
503 if (!rc) {
504 cmd->length = 0;
505 rc = mwl8k_send_fw_load_cmd(priv, cmd, sizeof(*cmd));
506 }
507
508 kfree(cmd);
509
510 return rc;
511}
512
513static int mwl8k_feed_fw_image(struct mwl8k_priv *priv,
514 const u8 *data, size_t length)
515{
516 unsigned char *buffer;
517 int may_continue, rc = 0;
518 u32 done, prev_block_size;
519
520 buffer = kmalloc(1024, GFP_KERNEL);
521 if (buffer == NULL)
522 return -ENOMEM;
523
524 done = 0;
525 prev_block_size = 0;
526 may_continue = 1000;
527 while (may_continue > 0) {
528 u32 block_size;
529
530 block_size = ioread32(priv->regs + MWL8K_HIU_SCRATCH);
531 if (block_size & 1) {
532 block_size &= ~1;
533 may_continue--;
534 } else {
535 done += prev_block_size;
536 length -= prev_block_size;
537 }
538
539 if (block_size > 1024 || block_size > length) {
540 rc = -EOVERFLOW;
541 break;
542 }
543
544 if (length == 0) {
545 rc = 0;
546 break;
547 }
548
549 if (block_size == 0) {
550 rc = -EPROTO;
551 may_continue--;
552 udelay(1);
553 continue;
554 }
555
556 prev_block_size = block_size;
557 memcpy(buffer, data + done, block_size);
558
559 rc = mwl8k_send_fw_load_cmd(priv, buffer, block_size);
560 if (rc)
561 break;
562 }
563
564 if (!rc && length != 0)
565 rc = -EREMOTEIO;
566
567 kfree(buffer);
568
569 return rc;
570}
571
c2c357ce 572static int mwl8k_load_firmware(struct ieee80211_hw *hw)
a66098da 573{
c2c357ce 574 struct mwl8k_priv *priv = hw->priv;
22be40d9 575 struct firmware *fw = priv->fw_ucode;
c2c357ce
LB		 576 int rc;
577 int loops;
578
579 if (!memcmp(fw->data, "\x01\x00\x00\x00", 4)) {
22be40d9 580 struct firmware *helper = priv->fw_helper;
a66098da 581
c2c357ce
LB		 582 if (helper == NULL) {
583 printk(KERN_ERR "%s: helper image needed but none "
584 "given\n", pci_name(priv->pdev));
585 return -EINVAL;
586 }
a66098da 587
c2c357ce 588 rc = mwl8k_load_fw_image(priv, helper->data, helper->size);
a66098da
LB		 589 if (rc) {
590 printk(KERN_ERR "%s: unable to load firmware "
c2c357ce 591 "helper image\n", pci_name(priv->pdev));
a66098da
LB		 592 return rc;
593 }
89b872e2 594 msleep(5);
a66098da 595
c2c357ce 596 rc = mwl8k_feed_fw_image(priv, fw->data, fw->size);
a66098da 597 } else {
c2c357ce 598 rc = mwl8k_load_fw_image(priv, fw->data, fw->size);
a66098da
LB		 599 }
600
601 if (rc) {
c2c357ce
LB		 602 printk(KERN_ERR "%s: unable to load firmware image\n",
603 pci_name(priv->pdev));
a66098da
LB		 604 return rc;
605 }
606
89a91f4f 607 iowrite32(MWL8K_MODE_STA, priv->regs + MWL8K_HIU_GEN_PTR);
a66098da 608
89b872e2 609 loops = 500000;
a66098da 610 do {
eae74e65
LB		 611 u32 ready_code;
612
613 ready_code = ioread32(priv->regs + MWL8K_HIU_INT_CODE);
614 if (ready_code == MWL8K_FWAP_READY) {
615 priv->ap_fw = 1;
616 break;
617 } else if (ready_code == MWL8K_FWSTA_READY) {
618 priv->ap_fw = 0;
a66098da 619 break;
eae74e65
LB		 620 }
621
622 cond_resched();
a66098da
LB		 623 udelay(1);
624 } while (--loops);
625
626 return loops ? 0 : -ETIMEDOUT;
627}
628
629
a66098da
LB		 630/* DMA header used by firmware and hardware. */
631struct mwl8k_dma_data {
632 __le16 fwlen;
633 struct ieee80211_hdr wh;
20f09c3d 634 char data[0];
a66098da
LB		 635} __attribute__((packed));
636
637/* Routines to add/remove DMA header from skb. */
20f09c3d 638static inline void mwl8k_remove_dma_header(struct sk_buff *skb, __le16 qos)
a66098da 639{
20f09c3d
LB		 640 struct mwl8k_dma_data *tr;
641 int hdrlen;
642
643 tr = (struct mwl8k_dma_data *)skb->data;
644 hdrlen = ieee80211_hdrlen(tr->wh.frame_control);
645
646 if (hdrlen != sizeof(tr->wh)) {
647 if (ieee80211_is_data_qos(tr->wh.frame_control)) {
648 memmove(tr->data - hdrlen, &tr->wh, hdrlen - 2);
649 *((__le16 *)(tr->data - 2)) = qos;
650 } else {
651 memmove(tr->data - hdrlen, &tr->wh, hdrlen);
652 }
a66098da 653 }
20f09c3d
LB		 654
655 if (hdrlen != sizeof(*tr))
656 skb_pull(skb, sizeof(*tr) - hdrlen);
a66098da
LB		 657}
658
76266b2a 659static inline void mwl8k_add_dma_header(struct sk_buff *skb)
a66098da
LB		 660{
661 struct ieee80211_hdr *wh;
ca009301 662 int hdrlen;
a66098da
LB		 663 struct mwl8k_dma_data *tr;
664
ca009301
LB		 665 /*
666 * Add a firmware DMA header; the firmware requires that we
667 * present a 2-byte payload length followed by a 4-address
668 * header (without QoS field), followed (optionally) by any
669 * WEP/ExtIV header (but only filled in for CCMP).
670 */
a66098da 671 wh = (struct ieee80211_hdr *)skb->data;
ca009301 672
a66098da 673 hdrlen = ieee80211_hdrlen(wh->frame_control);
ca009301
LB		 674 if (hdrlen != sizeof(*tr))
675 skb_push(skb, sizeof(*tr) - hdrlen);
a66098da 676
ca009301
LB		 677 if (ieee80211_is_data_qos(wh->frame_control))
678 hdrlen -= 2;
a66098da
LB		 679
680 tr = (struct mwl8k_dma_data *)skb->data;
681 if (wh != &tr->wh)
682 memmove(&tr->wh, wh, hdrlen);
ca009301
LB		 683 if (hdrlen != sizeof(tr->wh))
684 memset(((void *)&tr->wh) + hdrlen, 0, sizeof(tr->wh) - hdrlen);
a66098da
LB		 685
686 /*
687 * Firmware length is the length of the fully formed "802.11
688 * payload". That is, everything except for the 802.11 header.
689 * This includes all crypto material including the MIC.
690 */
ca009301 691 tr->fwlen = cpu_to_le16(skb->len - sizeof(*tr));
a66098da
LB		 692}
693
694
695/*
89a91f4f 696 * Packet reception for 88w8366 AP firmware.
6f6d1e9a 697 */
89a91f4f 698struct mwl8k_rxd_8366_ap {
6f6d1e9a
LB		 699 __le16 pkt_len;
700 __u8 sq2;
701 __u8 rate;
702 __le32 pkt_phys_addr;
703 __le32 next_rxd_phys_addr;
704 __le16 qos_control;
705 __le16 htsig2;
706 __le32 hw_rssi_info;
707 __le32 hw_noise_floor_info;
708 __u8 noise_floor;
709 __u8 pad0[3];
710 __u8 rssi;
711 __u8 rx_status;
712 __u8 channel;
713 __u8 rx_ctrl;
714} __attribute__((packed));
715
89a91f4f
LB		 716#define MWL8K_8366_AP_RATE_INFO_MCS_FORMAT 0x80
717#define MWL8K_8366_AP_RATE_INFO_40MHZ 0x40
718#define MWL8K_8366_AP_RATE_INFO_RATEID(x) ((x) & 0x3f)
8e9f33f0 719
89a91f4f 720#define MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST 0x80
6f6d1e9a 721
89a91f4f 722static void mwl8k_rxd_8366_ap_init(void *_rxd, dma_addr_t next_dma_addr)
6f6d1e9a 723{
89a91f4f 724 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 725
726 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 727 rxd->rx_ctrl = MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST;
6f6d1e9a
LB		 728}
729
89a91f4f 730static void mwl8k_rxd_8366_ap_refill(void *_rxd, dma_addr_t addr, int len)
6f6d1e9a 731{
89a91f4f 732 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a
LB		 733
734 rxd->pkt_len = cpu_to_le16(len);
735 rxd->pkt_phys_addr = cpu_to_le32(addr);
736 wmb();
737 rxd->rx_ctrl = 0;
738}
739
740static int
89a91f4f
LB		 741mwl8k_rxd_8366_ap_process(void *_rxd, struct ieee80211_rx_status *status,
742 __le16 *qos)
6f6d1e9a 743{
89a91f4f 744 struct mwl8k_rxd_8366_ap *rxd = _rxd;
6f6d1e9a 745
89a91f4f 746 if (!(rxd->rx_ctrl & MWL8K_8366_AP_RX_CTRL_OWNED_BY_HOST))
6f6d1e9a
LB		 747 return -1;
748 rmb();
749
750 memset(status, 0, sizeof(*status));
751
752 status->signal = -rxd->rssi;
753 status->noise = -rxd->noise_floor;
754
89a91f4f 755 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_MCS_FORMAT) {
6f6d1e9a 756 status->flag |= RX_FLAG_HT;
89a91f4f 757 if (rxd->rate & MWL8K_8366_AP_RATE_INFO_40MHZ)
8e9f33f0 758 status->flag |= RX_FLAG_40MHZ;
89a91f4f 759 status->rate_idx = MWL8K_8366_AP_RATE_INFO_RATEID(rxd->rate);
6f6d1e9a
LB		 760 } else {
761 int i;
762
777ad375
LB		 763 for (i = 0; i < ARRAY_SIZE(mwl8k_rates_24); i++) {
764 if (mwl8k_rates_24[i].hw_value == rxd->rate) {
6f6d1e9a
LB		 765 status->rate_idx = i;
766 break;
767 }
768 }
769 }
770
85478344
LB		 771 if (rxd->channel > 14) {
772 status->band = IEEE80211_BAND_5GHZ;
773 if (!(status->flag & RX_FLAG_HT))
774 status->rate_idx -= 5;
775 } else {
776 status->band = IEEE80211_BAND_2GHZ;
777 }
6f6d1e9a
LB		 778 status->freq = ieee80211_channel_to_frequency(rxd->channel);
779
20f09c3d
LB		 780 *qos = rxd->qos_control;
781
6f6d1e9a
LB		 782 return le16_to_cpu(rxd->pkt_len);
783}
784
89a91f4f
LB		 785static struct rxd_ops rxd_8366_ap_ops = {
786 .rxd_size = sizeof(struct mwl8k_rxd_8366_ap),
787 .rxd_init = mwl8k_rxd_8366_ap_init,
788 .rxd_refill = mwl8k_rxd_8366_ap_refill,
789 .rxd_process = mwl8k_rxd_8366_ap_process,
6f6d1e9a
LB		 790};
791
792/*
89a91f4f 793 * Packet reception for STA firmware.
a66098da 794 */
89a91f4f 795struct mwl8k_rxd_sta {
a66098da
LB		 796 __le16 pkt_len;
797 __u8 link_quality;
798 __u8 noise_level;
799 __le32 pkt_phys_addr;
45eb400d 800 __le32 next_rxd_phys_addr;
a66098da
LB		 801 __le16 qos_control;
802 __le16 rate_info;
803 __le32 pad0[4];
804 __u8 rssi;
805 __u8 channel;
806 __le16 pad1;
807 __u8 rx_ctrl;
808 __u8 rx_status;
809 __u8 pad2[2];
810} __attribute__((packed));
811
89a91f4f
LB		 812#define MWL8K_STA_RATE_INFO_SHORTPRE 0x8000
813#define MWL8K_STA_RATE_INFO_ANTSELECT(x) (((x) >> 11) & 0x3)
814#define MWL8K_STA_RATE_INFO_RATEID(x) (((x) >> 3) & 0x3f)
815#define MWL8K_STA_RATE_INFO_40MHZ 0x0004
816#define MWL8K_STA_RATE_INFO_SHORTGI 0x0002
817#define MWL8K_STA_RATE_INFO_MCS_FORMAT 0x0001
54bc3a0d 818
89a91f4f 819#define MWL8K_STA_RX_CTRL_OWNED_BY_HOST 0x02
54bc3a0d 820
89a91f4f 821static void mwl8k_rxd_sta_init(void *_rxd, dma_addr_t next_dma_addr)
54bc3a0d 822{
89a91f4f 823 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 824
825 rxd->next_rxd_phys_addr = cpu_to_le32(next_dma_addr);
89a91f4f 826 rxd->rx_ctrl = MWL8K_STA_RX_CTRL_OWNED_BY_HOST;
54bc3a0d
LB		 827}
828
89a91f4f 829static void mwl8k_rxd_sta_refill(void *_rxd, dma_addr_t addr, int len)
54bc3a0d 830{
89a91f4f 831 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 832
833 rxd->pkt_len = cpu_to_le16(len);
834 rxd->pkt_phys_addr = cpu_to_le32(addr);
835 wmb();
836 rxd->rx_ctrl = 0;
837}
838
839static int
89a91f4f 840mwl8k_rxd_sta_process(void *_rxd, struct ieee80211_rx_status *status,
20f09c3d 841 __le16 *qos)
54bc3a0d 842{
89a91f4f 843 struct mwl8k_rxd_sta *rxd = _rxd;
54bc3a0d
LB		 844 u16 rate_info;
845
89a91f4f 846 if (!(rxd->rx_ctrl & MWL8K_STA_RX_CTRL_OWNED_BY_HOST))
54bc3a0d
LB		 847 return -1;
848 rmb();
849
850 rate_info = le16_to_cpu(rxd->rate_info);
851
852 memset(status, 0, sizeof(*status));
853
854 status->signal = -rxd->rssi;
855 status->noise = -rxd->noise_level;
89a91f4f
LB		 856 status->antenna = MWL8K_STA_RATE_INFO_ANTSELECT(rate_info);
857 status->rate_idx = MWL8K_STA_RATE_INFO_RATEID(rate_info);
54bc3a0d 858
89a91f4f 859 if (rate_info & MWL8K_STA_RATE_INFO_SHORTPRE)
54bc3a0d 860 status->flag |= RX_FLAG_SHORTPRE;
89a91f4f 861 if (rate_info & MWL8K_STA_RATE_INFO_40MHZ)
54bc3a0d 862 status->flag |= RX_FLAG_40MHZ;
89a91f4f 863 if (rate_info & MWL8K_STA_RATE_INFO_SHORTGI)
54bc3a0d 864 status->flag |= RX_FLAG_SHORT_GI;
89a91f4f 865 if (rate_info & MWL8K_STA_RATE_INFO_MCS_FORMAT)
54bc3a0d
LB		 866 status->flag |= RX_FLAG_HT;
867
85478344
LB		 868 if (rxd->channel > 14) {
869 status->band = IEEE80211_BAND_5GHZ;
870 if (!(status->flag & RX_FLAG_HT))
871 status->rate_idx -= 5;
872 } else {
873 status->band = IEEE80211_BAND_2GHZ;
874 }
54bc3a0d
LB		 875 status->freq = ieee80211_channel_to_frequency(rxd->channel);
876
20f09c3d
LB		 877 *qos = rxd->qos_control;
878
54bc3a0d
LB		 879 return le16_to_cpu(rxd->pkt_len);
880}
881
89a91f4f
LB		 882static struct rxd_ops rxd_sta_ops = {
883 .rxd_size = sizeof(struct mwl8k_rxd_sta),
884 .rxd_init = mwl8k_rxd_sta_init,
885 .rxd_refill = mwl8k_rxd_sta_refill,
886 .rxd_process = mwl8k_rxd_sta_process,
54bc3a0d
LB		 887};
888
889
a66098da
LB		 890#define MWL8K_RX_DESCS 256
891#define MWL8K_RX_MAXSZ 3800
892
893static int mwl8k_rxq_init(struct ieee80211_hw *hw, int index)
894{
895 struct mwl8k_priv *priv = hw->priv;
896 struct mwl8k_rx_queue *rxq = priv->rxq + index;
897 int size;
898 int i;
899
45eb400d
LB		 900 rxq->rxd_count = 0;
901 rxq->head = 0;
902 rxq->tail = 0;
a66098da 903
54bc3a0d 904 size = MWL8K_RX_DESCS * priv->rxd_ops->rxd_size;
a66098da 905
45eb400d
LB		 906 rxq->rxd = pci_alloc_consistent(priv->pdev, size, &rxq->rxd_dma);
907 if (rxq->rxd == NULL) {
a66098da 908 printk(KERN_ERR "%s: failed to alloc RX descriptors\n",
c2c357ce 909 wiphy_name(hw->wiphy));
a66098da
LB		 910 return -ENOMEM;
911 }
45eb400d 912 memset(rxq->rxd, 0, size);
a66098da 913
788838eb
LB		 914 rxq->buf = kmalloc(MWL8K_RX_DESCS * sizeof(*rxq->buf), GFP_KERNEL);
915 if (rxq->buf == NULL) {
a66098da 916 printk(KERN_ERR "%s: failed to alloc RX skbuff list\n",
c2c357ce 917 wiphy_name(hw->wiphy));
45eb400d 918 pci_free_consistent(priv->pdev, size, rxq->rxd, rxq->rxd_dma);
a66098da
LB		 919 return -ENOMEM;
920 }
788838eb 921 memset(rxq->buf, 0, MWL8K_RX_DESCS * sizeof(*rxq->buf));
a66098da
LB		 922
923 for (i = 0; i < MWL8K_RX_DESCS; i++) {
54bc3a0d
LB		 924 int desc_size;
925 void *rxd;
a66098da 926 int nexti;
54bc3a0d
LB		 927 dma_addr_t next_dma_addr;
928
929 desc_size = priv->rxd_ops->rxd_size;
930 rxd = rxq->rxd + (i * priv->rxd_ops->rxd_size);
a66098da 931
54bc3a0d
LB		 932 nexti = i + 1;
933 if (nexti == MWL8K_RX_DESCS)
934 nexti = 0;
935 next_dma_addr = rxq->rxd_dma + (nexti * desc_size);
a66098da 936
54bc3a0d 937 priv->rxd_ops->rxd_init(rxd, next_dma_addr);
a66098da
LB		 938 }
939
940 return 0;
941}
942
943static int rxq_refill(struct ieee80211_hw *hw, int index, int limit)
944{
945 struct mwl8k_priv *priv = hw->priv;
946 struct mwl8k_rx_queue *rxq = priv->rxq + index;
947 int refilled;
948
949 refilled = 0;
45eb400d 950 while (rxq->rxd_count < MWL8K_RX_DESCS && limit--) {
a66098da 951 struct sk_buff *skb;
788838eb 952 dma_addr_t addr;
a66098da 953 int rx;
54bc3a0d 954 void *rxd;
a66098da
LB		 955
956 skb = dev_alloc_skb(MWL8K_RX_MAXSZ);
957 if (skb == NULL)
958 break;
959
788838eb
LB		 960 addr = pci_map_single(priv->pdev, skb->data,
961 MWL8K_RX_MAXSZ, DMA_FROM_DEVICE);
a66098da 962
54bc3a0d
LB		 963 rxq->rxd_count++;
964 rx = rxq->tail++;
965 if (rxq->tail == MWL8K_RX_DESCS)
966 rxq->tail = 0;
788838eb
LB		 967 rxq->buf[rx].skb = skb;
968 pci_unmap_addr_set(&rxq->buf[rx], dma, addr);
54bc3a0d
LB		 969
970 rxd = rxq->rxd + (rx * priv->rxd_ops->rxd_size);
971 priv->rxd_ops->rxd_refill(rxd, addr, MWL8K_RX_MAXSZ);
a66098da
LB		 972
973 refilled++;
974 }
975
976 return refilled;
977}
978
979/* Must be called only when the card's reception is completely halted */
980static void mwl8k_rxq_deinit(struct ieee80211_hw *hw, int index)
981{
982 struct mwl8k_priv *priv = hw->priv;
983 struct mwl8k_rx_queue *rxq = priv->rxq + index;
984 int i;
985
986 for (i = 0; i < MWL8K_RX_DESCS; i++) {
788838eb
LB		 987 if (rxq->buf[i].skb != NULL) {
988 pci_unmap_single(priv->pdev,
989 pci_unmap_addr(&rxq->buf[i], dma),
990 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
991 pci_unmap_addr_set(&rxq->buf[i], dma, 0);
992
993 kfree_skb(rxq->buf[i].skb);
994 rxq->buf[i].skb = NULL;
a66098da
LB		 995 }
996 }
997
788838eb
LB		 998 kfree(rxq->buf);
999 rxq->buf = NULL;
a66098da
LB		 1000
1001 pci_free_consistent(priv->pdev,
54bc3a0d 1002 MWL8K_RX_DESCS * priv->rxd_ops->rxd_size,
45eb400d
LB		 1003 rxq->rxd, rxq->rxd_dma);
1004 rxq->rxd = NULL;
a66098da
LB		 1005}
1006
1007
1008/*
1009 * Scan a list of BSSIDs to process for finalize join.
1010 * Allows for extension to process multiple BSSIDs.
1011 */
1012static inline int
1013mwl8k_capture_bssid(struct mwl8k_priv *priv, struct ieee80211_hdr *wh)
1014{
1015 return priv->capture_beacon &&
1016 ieee80211_is_beacon(wh->frame_control) &&
1017 !compare_ether_addr(wh->addr3, priv->capture_bssid);
1018}
1019
3779752d
LB		 1020static inline void mwl8k_save_beacon(struct ieee80211_hw *hw,
1021 struct sk_buff *skb)
a66098da 1022{
3779752d
LB		 1023 struct mwl8k_priv *priv = hw->priv;
1024
a66098da 1025 priv->capture_beacon = false;
d89173f2 1026 memset(priv->capture_bssid, 0, ETH_ALEN);
a66098da
LB		 1027
1028 /*
1029 * Use GFP_ATOMIC as rxq_process is called from
1030 * the primary interrupt handler, memory allocation call
1031 * must not sleep.
1032 */
1033 priv->beacon_skb = skb_copy(skb, GFP_ATOMIC);
1034 if (priv->beacon_skb != NULL)
3779752d 1035 ieee80211_queue_work(hw, &priv->finalize_join_worker);
a66098da
LB		 1036}
1037
1038static int rxq_process(struct ieee80211_hw *hw, int index, int limit)
1039{
1040 struct mwl8k_priv *priv = hw->priv;
1041 struct mwl8k_rx_queue *rxq = priv->rxq + index;
1042 int processed;
1043
1044 processed = 0;
45eb400d 1045 while (rxq->rxd_count && limit--) {
a66098da 1046 struct sk_buff *skb;
54bc3a0d
LB		 1047 void *rxd;
1048 int pkt_len;
a66098da 1049 struct ieee80211_rx_status status;
20f09c3d 1050 __le16 qos;
a66098da 1051
788838eb 1052 skb = rxq->buf[rxq->head].skb;
d25f9f13
LB		 1053 if (skb == NULL)
1054 break;
54bc3a0d
LB		 1055
1056 rxd = rxq->rxd + (rxq->head * priv->rxd_ops->rxd_size);
1057
20f09c3d 1058 pkt_len = priv->rxd_ops->rxd_process(rxd, &status, &qos);
54bc3a0d
LB		 1059 if (pkt_len < 0)
1060 break;
1061
788838eb
LB		 1062 rxq->buf[rxq->head].skb = NULL;
1063
1064 pci_unmap_single(priv->pdev,
1065 pci_unmap_addr(&rxq->buf[rxq->head], dma),
1066 MWL8K_RX_MAXSZ, PCI_DMA_FROMDEVICE);
1067 pci_unmap_addr_set(&rxq->buf[rxq->head], dma, 0);
a66098da 1068
54bc3a0d
LB		 1069 rxq->head++;
1070 if (rxq->head == MWL8K_RX_DESCS)
1071 rxq->head = 0;
1072
45eb400d 1073 rxq->rxd_count--;
a66098da 1074
54bc3a0d 1075 skb_put(skb, pkt_len);
20f09c3d 1076 mwl8k_remove_dma_header(skb, qos);
a66098da 1077
a66098da 1078 /*
c2c357ce
LB		 1079 * Check for a pending join operation. Save a
1080 * copy of the beacon and schedule a tasklet to
1081 * send a FINALIZE_JOIN command to the firmware.
a66098da 1082 */
54bc3a0d 1083 if (mwl8k_capture_bssid(priv, (void *)skb->data))
3779752d 1084 mwl8k_save_beacon(hw, skb);
a66098da 1085
f1d58c25
JB		 1086 memcpy(IEEE80211_SKB_RXCB(skb), &status, sizeof(status));
1087 ieee80211_rx_irqsafe(hw, skb);
a66098da
LB		 1088
1089 processed++;
1090 }
1091
1092 return processed;
1093}
1094
1095
1096/*
1097 * Packet transmission.
1098 */
1099
a66098da
LB		 1100#define MWL8K_TXD_STATUS_OK 0x00000001
1101#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
1102#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
1103#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
a66098da 1104#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
a66098da 1105
e0493a8d
LB		 1106#define MWL8K_QOS_QLEN_UNSPEC 0xff00
1107#define MWL8K_QOS_ACK_POLICY_MASK 0x0060
1108#define MWL8K_QOS_ACK_POLICY_NORMAL 0x0000
1109#define MWL8K_QOS_ACK_POLICY_BLOCKACK 0x0060
1110#define MWL8K_QOS_EOSP 0x0010
1111
a66098da
LB		 1112struct mwl8k_tx_desc {
1113 __le32 status;
1114 __u8 data_rate;
1115 __u8 tx_priority;
1116 __le16 qos_control;
1117 __le32 pkt_phys_addr;
1118 __le16 pkt_len;
d89173f2 1119 __u8 dest_MAC_addr[ETH_ALEN];
45eb400d 1120 __le32 next_txd_phys_addr;
a66098da
LB		 1121 __le32 reserved;
1122 __le16 rate_info;
1123 __u8 peer_id;
1124 __u8 tx_frag_cnt;
1125} __attribute__((packed));
1126
1127#define MWL8K_TX_DESCS 128
1128
1129static int mwl8k_txq_init(struct ieee80211_hw *hw, int index)
1130{
1131 struct mwl8k_priv *priv = hw->priv;
1132 struct mwl8k_tx_queue *txq = priv->txq + index;
1133 int size;
1134 int i;
1135
45eb400d
LB		 1136 memset(&txq->stats, 0, sizeof(struct ieee80211_tx_queue_stats));
1137 txq->stats.limit = MWL8K_TX_DESCS;
1138 txq->head = 0;
1139 txq->tail = 0;
a66098da
LB		 1140
1141 size = MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc);
1142
45eb400d
LB		 1143 txq->txd = pci_alloc_consistent(priv->pdev, size, &txq->txd_dma);
1144 if (txq->txd == NULL) {
a66098da 1145 printk(KERN_ERR "%s: failed to alloc TX descriptors\n",
c2c357ce 1146 wiphy_name(hw->wiphy));
a66098da
LB		 1147 return -ENOMEM;
1148 }
45eb400d 1149 memset(txq->txd, 0, size);
a66098da 1150
45eb400d
LB		 1151 txq->skb = kmalloc(MWL8K_TX_DESCS * sizeof(*txq->skb), GFP_KERNEL);
1152 if (txq->skb == NULL) {
a66098da 1153 printk(KERN_ERR "%s: failed to alloc TX skbuff list\n",
c2c357ce 1154 wiphy_name(hw->wiphy));
45eb400d 1155 pci_free_consistent(priv->pdev, size, txq->txd, txq->txd_dma);
a66098da
LB		 1156 return -ENOMEM;
1157 }
45eb400d 1158 memset(txq->skb, 0, MWL8K_TX_DESCS * sizeof(*txq->skb));
a66098da
LB		 1159
1160 for (i = 0; i < MWL8K_TX_DESCS; i++) {
1161 struct mwl8k_tx_desc *tx_desc;
1162 int nexti;
1163
45eb400d 1164 tx_desc = txq->txd + i;
a66098da
LB		 1165 nexti = (i + 1) % MWL8K_TX_DESCS;
1166
1167 tx_desc->status = 0;
45eb400d
LB		 1168 tx_desc->next_txd_phys_addr =
1169 cpu_to_le32(txq->txd_dma + nexti * sizeof(*tx_desc));
a66098da
LB		 1170 }
1171
1172 return 0;
1173}
1174
1175static inline void mwl8k_tx_start(struct mwl8k_priv *priv)
1176{
1177 iowrite32(MWL8K_H2A_INT_PPA_READY,
1178 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1179 iowrite32(MWL8K_H2A_INT_DUMMY,
1180 priv->regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1181 ioread32(priv->regs + MWL8K_HIU_INT_CODE);
1182}
1183
7e1112d3 1184static void mwl8k_dump_tx_rings(struct ieee80211_hw *hw)
a66098da 1185{
7e1112d3
LB		 1186 struct mwl8k_priv *priv = hw->priv;
1187 int i;
1188
1189 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
1190 struct mwl8k_tx_queue *txq = priv->txq + i;
1191 int fw_owned = 0;
1192 int drv_owned = 0;
1193 int unused = 0;
1194 int desc;
1195
a66098da 1196 for (desc = 0; desc < MWL8K_TX_DESCS; desc++) {
7e1112d3
LB		 1197 struct mwl8k_tx_desc *tx_desc = txq->txd + desc;
1198 u32 status;
a66098da 1199
7e1112d3 1200 status = le32_to_cpu(tx_desc->status);
a66098da 1201 if (status & MWL8K_TXD_STATUS_FW_OWNED)
7e1112d3 1202 fw_owned++;
a66098da 1203 else
7e1112d3 1204 drv_owned++;
a66098da
LB		 1205
1206 if (tx_desc->pkt_len == 0)
7e1112d3 1207 unused++;
a66098da 1208 }
a66098da 1209
7e1112d3
LB		 1210 printk(KERN_ERR "%s: txq[%d] len=%d head=%d tail=%d "
1211 "fw_owned=%d drv_owned=%d unused=%d\n",
1212 wiphy_name(hw->wiphy), i,
1213 txq->stats.len, txq->head, txq->tail,
1214 fw_owned, drv_owned, unused);
1215 }
a66098da
LB		 1216}
1217
618952a7 1218/*
88de754a 1219 * Must be called with priv->fw_mutex held and tx queues stopped.
618952a7 1220 */
62abd3cf 1221#define MWL8K_TX_WAIT_TIMEOUT_MS 5000
7e1112d3 1222
950d5b01 1223static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw)
a66098da 1224{
a66098da 1225 struct mwl8k_priv *priv = hw->priv;
88de754a 1226 DECLARE_COMPLETION_ONSTACK(tx_wait);
7e1112d3
LB		 1227 int retry;
1228 int rc;
a66098da
LB		 1229
1230 might_sleep();
1231
7e1112d3
LB		 1232 /*
1233 * The TX queues are stopped at this point, so this test
1234 * doesn't need to take ->tx_lock.
1235 */
1236 if (!priv->pending_tx_pkts)
1237 return 0;
1238
1239 retry = 0;
1240 rc = 0;
1241
a66098da 1242 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1243 priv->tx_wait = &tx_wait;
1244 while (!rc) {
1245 int oldcount;
1246 unsigned long timeout;
a66098da 1247
7e1112d3 1248 oldcount = priv->pending_tx_pkts;
a66098da 1249
7e1112d3 1250 spin_unlock_bh(&priv->tx_lock);
88de754a 1251 timeout = wait_for_completion_timeout(&tx_wait,
7e1112d3 1252 msecs_to_jiffies(MWL8K_TX_WAIT_TIMEOUT_MS));
a66098da 1253 spin_lock_bh(&priv->tx_lock);
7e1112d3
LB		 1254
1255 if (timeout) {
1256 WARN_ON(priv->pending_tx_pkts);
1257 if (retry) {
1258 printk(KERN_NOTICE "%s: tx rings drained\n",
1259 wiphy_name(hw->wiphy));
1260 }
1261 break;
1262 }
1263
1264 if (priv->pending_tx_pkts < oldcount) {
9a2303b9
LB		 1265 printk(KERN_NOTICE "%s: waiting for tx rings "
1266 "to drain (%d -> %d pkts)\n",
7e1112d3
LB		 1267 wiphy_name(hw->wiphy), oldcount,
1268 priv->pending_tx_pkts);
1269 retry = 1;
1270 continue;
1271 }
1272
a66098da 1273 priv->tx_wait = NULL;
a66098da 1274
7e1112d3
LB		 1275 printk(KERN_ERR "%s: tx rings stuck for %d ms\n",
1276 wiphy_name(hw->wiphy), MWL8K_TX_WAIT_TIMEOUT_MS);
1277 mwl8k_dump_tx_rings(hw);
1278
1279 rc = -ETIMEDOUT;
a66098da 1280 }
7e1112d3 1281 spin_unlock_bh(&priv->tx_lock);
a66098da 1282
7e1112d3 1283 return rc;
a66098da
LB		 1284}
1285
c23b5a69
LB		 1286#define MWL8K_TXD_SUCCESS(status) \
1287 ((status) & (MWL8K_TXD_STATUS_OK | \
1288 MWL8K_TXD_STATUS_OK_RETRY | \
1289 MWL8K_TXD_STATUS_OK_MORE_RETRY))
a66098da 1290
efb7c49a
LB		 1291static int
1292mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int limit, int force)
a66098da
LB		 1293{
1294 struct mwl8k_priv *priv = hw->priv;
1295 struct mwl8k_tx_queue *txq = priv->txq + index;
efb7c49a 1296 int processed;
a66098da 1297
efb7c49a
LB		 1298 processed = 0;
1299 while (txq->stats.len > 0 && limit--) {
a66098da 1300 int tx;
a66098da
LB		 1301 struct mwl8k_tx_desc *tx_desc;
1302 unsigned long addr;
ce9e2e1b 1303 int size;
a66098da
LB		 1304 struct sk_buff *skb;
1305 struct ieee80211_tx_info *info;
1306 u32 status;
1307
45eb400d
LB		 1308 tx = txq->head;
1309 tx_desc = txq->txd + tx;
a66098da
LB		 1310
1311 status = le32_to_cpu(tx_desc->status);
1312
1313 if (status & MWL8K_TXD_STATUS_FW_OWNED) {
1314 if (!force)
1315 break;
1316 tx_desc->status &=
1317 ~cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED);
1318 }
1319
45eb400d
LB		 1320 txq->head = (tx + 1) % MWL8K_TX_DESCS;
1321 BUG_ON(txq->stats.len == 0);
1322 txq->stats.len--;
a66098da
LB		 1323 priv->pending_tx_pkts--;
1324
1325 addr = le32_to_cpu(tx_desc->pkt_phys_addr);
ce9e2e1b 1326 size = le16_to_cpu(tx_desc->pkt_len);
45eb400d
LB		 1327 skb = txq->skb[tx];
1328 txq->skb[tx] = NULL;
a66098da
LB		 1329
1330 BUG_ON(skb == NULL);
1331 pci_unmap_single(priv->pdev, addr, size, PCI_DMA_TODEVICE);
1332
20f09c3d 1333 mwl8k_remove_dma_header(skb, tx_desc->qos_control);
a66098da
LB		 1334
1335 /* Mark descriptor as unused */
1336 tx_desc->pkt_phys_addr = 0;
1337 tx_desc->pkt_len = 0;
1338
a66098da
LB		 1339 info = IEEE80211_SKB_CB(skb);
1340 ieee80211_tx_info_clear_status(info);
ce9e2e1b 1341 if (MWL8K_TXD_SUCCESS(status))
a66098da 1342 info->flags |= IEEE80211_TX_STAT_ACK;
a66098da
LB		 1343
1344 ieee80211_tx_status_irqsafe(hw, skb);
1345
efb7c49a 1346 processed++;
a66098da
LB		 1347 }
1348
efb7c49a 1349 if (processed && priv->radio_on && !mutex_is_locked(&priv->fw_mutex))
a66098da 1350 ieee80211_wake_queue(hw, index);
efb7c49a
LB		 1351
1352 return processed;
a66098da
LB		 1353}
1354
1355/* must be called only when the card's transmit is completely halted */
1356static void mwl8k_txq_deinit(struct ieee80211_hw *hw, int index)
1357{
1358 struct mwl8k_priv *priv = hw->priv;
1359 struct mwl8k_tx_queue *txq = priv->txq + index;
1360
efb7c49a 1361 mwl8k_txq_reclaim(hw, index, INT_MAX, 1);
a66098da 1362
45eb400d
LB		 1363 kfree(txq->skb);
1364 txq->skb = NULL;
a66098da
LB		 1365
1366 pci_free_consistent(priv->pdev,
1367 MWL8K_TX_DESCS * sizeof(struct mwl8k_tx_desc),
45eb400d
LB		 1368 txq->txd, txq->txd_dma);
1369 txq->txd = NULL;
a66098da
LB		 1370}
1371
1372static int
1373mwl8k_txq_xmit(struct ieee80211_hw *hw, int index, struct sk_buff *skb)
1374{
1375 struct mwl8k_priv *priv = hw->priv;
1376 struct ieee80211_tx_info *tx_info;
23b33906 1377 struct mwl8k_vif *mwl8k_vif;
a66098da
LB		 1378 struct ieee80211_hdr *wh;
1379 struct mwl8k_tx_queue *txq;
1380 struct mwl8k_tx_desc *tx;
a66098da 1381 dma_addr_t dma;
23b33906
LB		 1382 u32 txstatus;
1383 u8 txdatarate;
1384 u16 qos;
a66098da 1385
23b33906
LB		 1386 wh = (struct ieee80211_hdr *)skb->data;
1387 if (ieee80211_is_data_qos(wh->frame_control))
1388 qos = le16_to_cpu(*((__le16 *)ieee80211_get_qos_ctl(wh)));
1389 else
1390 qos = 0;
a66098da 1391
76266b2a 1392 mwl8k_add_dma_header(skb);
23b33906 1393 wh = &((struct mwl8k_dma_data *)skb->data)->wh;
a66098da
LB		 1394
1395 tx_info = IEEE80211_SKB_CB(skb);
1396 mwl8k_vif = MWL8K_VIF(tx_info->control.vif);
a66098da
LB		 1397
1398 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
a66098da 1399 wh->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
657232b6
LB		 1400 wh->seq_ctrl |= cpu_to_le16(mwl8k_vif->seqno);
1401 mwl8k_vif->seqno += 0x10;
a66098da
LB		 1402 }
1403
23b33906
LB		 1404 /* Setup firmware control bit fields for each frame type. */
1405 txstatus = 0;
1406 txdatarate = 0;
1407 if (ieee80211_is_mgmt(wh->frame_control) ||
1408 ieee80211_is_ctl(wh->frame_control)) {
1409 txdatarate = 0;
e0493a8d 1410 qos |= MWL8K_QOS_QLEN_UNSPEC | MWL8K_QOS_EOSP;
23b33906
LB		 1411 } else if (ieee80211_is_data(wh->frame_control)) {
1412 txdatarate = 1;
1413 if (is_multicast_ether_addr(wh->addr1))
1414 txstatus |= MWL8K_TXD_STATUS_MULTICAST_TX;
1415
e0493a8d 1416 qos &= ~MWL8K_QOS_ACK_POLICY_MASK;
23b33906 1417 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
e0493a8d 1418 qos |= MWL8K_QOS_ACK_POLICY_BLOCKACK;
23b33906 1419 else
e0493a8d 1420 qos |= MWL8K_QOS_ACK_POLICY_NORMAL;
23b33906 1421 }
a66098da
LB		 1422
1423 dma = pci_map_single(priv->pdev, skb->data,
1424 skb->len, PCI_DMA_TODEVICE);
1425
1426 if (pci_dma_mapping_error(priv->pdev, dma)) {
1427 printk(KERN_DEBUG "%s: failed to dma map skb, "
c2c357ce 1428 "dropping TX frame.\n", wiphy_name(hw->wiphy));
23b33906 1429 dev_kfree_skb(skb);
a66098da
LB		 1430 return NETDEV_TX_OK;
1431 }
1432
23b33906 1433 spin_lock_bh(&priv->tx_lock);
a66098da 1434
23b33906 1435 txq = priv->txq + index;
a66098da 1436
45eb400d
LB		 1437 BUG_ON(txq->skb[txq->tail] != NULL);
1438 txq->skb[txq->tail] = skb;
a66098da 1439
45eb400d 1440 tx = txq->txd + txq->tail;
23b33906
LB		 1441 tx->data_rate = txdatarate;
1442 tx->tx_priority = index;
a66098da 1443 tx->qos_control = cpu_to_le16(qos);
a66098da
LB		 1444 tx->pkt_phys_addr = cpu_to_le32(dma);
1445 tx->pkt_len = cpu_to_le16(skb->len);
23b33906 1446 tx->rate_info = 0;
a680400e
LB		 1447 if (!priv->ap_fw && tx_info->control.sta != NULL)
1448 tx->peer_id = MWL8K_STA(tx_info->control.sta)->peer_id;
1449 else
1450 tx->peer_id = 0;
a66098da 1451 wmb();
23b33906
LB		 1452 tx->status = cpu_to_le32(MWL8K_TXD_STATUS_FW_OWNED | txstatus);
1453
45eb400d
LB		 1454 txq->stats.count++;
1455 txq->stats.len++;
a66098da 1456 priv->pending_tx_pkts++;
a66098da 1457
45eb400d
LB		 1458 txq->tail++;
1459 if (txq->tail == MWL8K_TX_DESCS)
1460 txq->tail = 0;
23b33906 1461
45eb400d 1462 if (txq->head == txq->tail)
a66098da
LB		 1463 ieee80211_stop_queue(hw, index);
1464
23b33906 1465 mwl8k_tx_start(priv);
a66098da
LB		 1466
1467 spin_unlock_bh(&priv->tx_lock);
1468
1469 return NETDEV_TX_OK;
1470}
1471
1472
618952a7
LB		 1473/*
1474 * Firmware access.
1475 *
1476 * We have the following requirements for issuing firmware commands:
1477 * - Some commands require that the packet transmit path is idle when
1478 * the command is issued. (For simplicity, we'll just quiesce the
1479 * transmit path for every command.)
1480 * - There are certain sequences of commands that need to be issued to
1481 * the hardware sequentially, with no other intervening commands.
1482 *
1483 * This leads to an implementation of a "firmware lock" as a mutex that
1484 * can be taken recursively, and which is taken by both the low-level
1485 * command submission function (mwl8k_post_cmd) as well as any users of
1486 * that function that require issuing of an atomic sequence of commands,
1487 * and quiesces the transmit path whenever it's taken.
1488 */
1489static int mwl8k_fw_lock(struct ieee80211_hw *hw)
1490{
1491 struct mwl8k_priv *priv = hw->priv;
1492
1493 if (priv->fw_mutex_owner != current) {
1494 int rc;
1495
1496 mutex_lock(&priv->fw_mutex);
1497 ieee80211_stop_queues(hw);
1498
1499 rc = mwl8k_tx_wait_empty(hw);
1500 if (rc) {
1501 ieee80211_wake_queues(hw);
1502 mutex_unlock(&priv->fw_mutex);
1503
1504 return rc;
1505 }
1506
1507 priv->fw_mutex_owner = current;
1508 }
1509
1510 priv->fw_mutex_depth++;
1511
1512 return 0;
1513}
1514
1515static void mwl8k_fw_unlock(struct ieee80211_hw *hw)
1516{
1517 struct mwl8k_priv *priv = hw->priv;
1518
1519 if (!--priv->fw_mutex_depth) {
1520 ieee80211_wake_queues(hw);
1521 priv->fw_mutex_owner = NULL;
1522 mutex_unlock(&priv->fw_mutex);
1523 }
1524}
1525
1526
a66098da
LB		 1527/*
1528 * Command processing.
1529 */
1530
0c9cc640
LB		 1531/* Timeout firmware commands after 10s */
1532#define MWL8K_CMD_TIMEOUT_MS 10000
a66098da
LB		 1533
1534static int mwl8k_post_cmd(struct ieee80211_hw *hw, struct mwl8k_cmd_pkt *cmd)
1535{
1536 DECLARE_COMPLETION_ONSTACK(cmd_wait);
1537 struct mwl8k_priv *priv = hw->priv;
1538 void __iomem *regs = priv->regs;
1539 dma_addr_t dma_addr;
1540 unsigned int dma_size;
1541 int rc;
a66098da
LB		 1542 unsigned long timeout = 0;
1543 u8 buf[32];
1544
c2c357ce 1545 cmd->result = 0xffff;
a66098da
LB		 1546 dma_size = le16_to_cpu(cmd->length);
1547 dma_addr = pci_map_single(priv->pdev, cmd, dma_size,
1548 PCI_DMA_BIDIRECTIONAL);
1549 if (pci_dma_mapping_error(priv->pdev, dma_addr))
1550 return -ENOMEM;
1551
618952a7 1552 rc = mwl8k_fw_lock(hw);
39a1e42e
LB		 1553 if (rc) {
1554 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1555 PCI_DMA_BIDIRECTIONAL);
618952a7 1556 return rc;
39a1e42e 1557 }
a66098da 1558
a66098da
LB		 1559 priv->hostcmd_wait = &cmd_wait;
1560 iowrite32(dma_addr, regs + MWL8K_HIU_GEN_PTR);
1561 iowrite32(MWL8K_H2A_INT_DOORBELL,
1562 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
1563 iowrite32(MWL8K_H2A_INT_DUMMY,
1564 regs + MWL8K_HIU_H2A_INTERRUPT_EVENTS);
a66098da
LB		 1565
1566 timeout = wait_for_completion_timeout(&cmd_wait,
1567 msecs_to_jiffies(MWL8K_CMD_TIMEOUT_MS));
1568
618952a7
LB		 1569 priv->hostcmd_wait = NULL;
1570
1571 mwl8k_fw_unlock(hw);
1572
37055bd4
LB		 1573 pci_unmap_single(priv->pdev, dma_addr, dma_size,
1574 PCI_DMA_BIDIRECTIONAL);
1575
a66098da 1576 if (!timeout) {
a66098da 1577 printk(KERN_ERR "%s: Command %s timeout after %u ms\n",
c2c357ce 1578 wiphy_name(hw->wiphy),
a66098da
LB		 1579 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1580 MWL8K_CMD_TIMEOUT_MS);
1581 rc = -ETIMEDOUT;
1582 } else {
0c9cc640
LB		 1583 int ms;
1584
1585 ms = MWL8K_CMD_TIMEOUT_MS - jiffies_to_msecs(timeout);
1586
ce9e2e1b 1587 rc = cmd->result ? -EINVAL : 0;
a66098da
LB		 1588 if (rc)
1589 printk(KERN_ERR "%s: Command %s error 0x%x\n",
c2c357ce 1590 wiphy_name(hw->wiphy),
a66098da 1591 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
76c962a2 1592 le16_to_cpu(cmd->result));
0c9cc640
LB		 1593 else if (ms > 2000)
1594 printk(KERN_NOTICE "%s: Command %s took %d ms\n",
1595 wiphy_name(hw->wiphy),
1596 mwl8k_cmd_name(cmd->code, buf, sizeof(buf)),
1597 ms);
a66098da
LB		 1598 }
1599
a66098da
LB		 1600 return rc;
1601}
1602
f57ca9c1
LB		 1603static int mwl8k_post_pervif_cmd(struct ieee80211_hw *hw,
1604 struct ieee80211_vif *vif,
1605 struct mwl8k_cmd_pkt *cmd)
1606{
1607 if (vif != NULL)
1608 cmd->macid = MWL8K_VIF(vif)->macid;
1609 return mwl8k_post_cmd(hw, cmd);
1610}
1611
1349ad2f
LB		 1612/*
1613 * Setup code shared between STA and AP firmware images.
1614 */
1615static void mwl8k_setup_2ghz_band(struct ieee80211_hw *hw)
1616{
1617 struct mwl8k_priv *priv = hw->priv;
1618
1619 BUILD_BUG_ON(sizeof(priv->channels_24) != sizeof(mwl8k_channels_24));
1620 memcpy(priv->channels_24, mwl8k_channels_24, sizeof(mwl8k_channels_24));
1621
1622 BUILD_BUG_ON(sizeof(priv->rates_24) != sizeof(mwl8k_rates_24));
1623 memcpy(priv->rates_24, mwl8k_rates_24, sizeof(mwl8k_rates_24));
1624
1625 priv->band_24.band = IEEE80211_BAND_2GHZ;
1626 priv->band_24.channels = priv->channels_24;
1627 priv->band_24.n_channels = ARRAY_SIZE(mwl8k_channels_24);
1628 priv->band_24.bitrates = priv->rates_24;
1629 priv->band_24.n_bitrates = ARRAY_SIZE(mwl8k_rates_24);
1630
1631 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band_24;
1632}
1633
4eae9edd
LB		 1634static void mwl8k_setup_5ghz_band(struct ieee80211_hw *hw)
1635{
1636 struct mwl8k_priv *priv = hw->priv;
1637
1638 BUILD_BUG_ON(sizeof(priv->channels_50) != sizeof(mwl8k_channels_50));
1639 memcpy(priv->channels_50, mwl8k_channels_50, sizeof(mwl8k_channels_50));
1640
1641 BUILD_BUG_ON(sizeof(priv->rates_50) != sizeof(mwl8k_rates_50));
1642 memcpy(priv->rates_50, mwl8k_rates_50, sizeof(mwl8k_rates_50));
1643
1644 priv->band_50.band = IEEE80211_BAND_5GHZ;
1645 priv->band_50.channels = priv->channels_50;
1646 priv->band_50.n_channels = ARRAY_SIZE(mwl8k_channels_50);
1647 priv->band_50.bitrates = priv->rates_50;
1648 priv->band_50.n_bitrates = ARRAY_SIZE(mwl8k_rates_50);
1649
1650 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &priv->band_50;
1651}
1652
a66098da 1653/*
04b147b1 1654 * CMD_GET_HW_SPEC (STA version).
a66098da 1655 */
04b147b1 1656struct mwl8k_cmd_get_hw_spec_sta {
a66098da
LB		 1657 struct mwl8k_cmd_pkt header;
1658 __u8 hw_rev;
1659 __u8 host_interface;
1660 __le16 num_mcaddrs;
d89173f2 1661 __u8 perm_addr[ETH_ALEN];
a66098da
LB		 1662 __le16 region_code;
1663 __le32 fw_rev;
1664 __le32 ps_cookie;
1665 __le32 caps;
1666 __u8 mcs_bitmap[16];
1667 __le32 rx_queue_ptr;
1668 __le32 num_tx_queues;
1669 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1670 __le32 caps2;
1671 __le32 num_tx_desc_per_queue;
45eb400d 1672 __le32 total_rxd;
a66098da
LB		 1673} __attribute__((packed));
1674
341c9791
LB		 1675#define MWL8K_CAP_MAX_AMSDU 0x20000000
1676#define MWL8K_CAP_GREENFIELD 0x08000000
1677#define MWL8K_CAP_AMPDU 0x04000000
1678#define MWL8K_CAP_RX_STBC 0x01000000
1679#define MWL8K_CAP_TX_STBC 0x00800000
1680#define MWL8K_CAP_SHORTGI_40MHZ 0x00400000
1681#define MWL8K_CAP_SHORTGI_20MHZ 0x00200000
1682#define MWL8K_CAP_RX_ANTENNA_MASK 0x000e0000
1683#define MWL8K_CAP_TX_ANTENNA_MASK 0x0001c000
1684#define MWL8K_CAP_DELAY_BA 0x00003000
1685#define MWL8K_CAP_MIMO 0x00000200
1686#define MWL8K_CAP_40MHZ 0x00000100
06953235
LB		 1687#define MWL8K_CAP_BAND_MASK 0x00000007
1688#define MWL8K_CAP_5GHZ 0x00000004
1689#define MWL8K_CAP_2GHZ4 0x00000001
341c9791 1690
06953235
LB		 1691static void
1692mwl8k_set_ht_caps(struct ieee80211_hw *hw,
1693 struct ieee80211_supported_band *band, u32 cap)
341c9791 1694{
341c9791
LB		 1695 int rx_streams;
1696 int tx_streams;
1697
777ad375 1698 band->ht_cap.ht_supported = 1;
341c9791
LB		 1699
1700 if (cap & MWL8K_CAP_MAX_AMSDU)
777ad375 1701 band->ht_cap.cap |= IEEE80211_HT_CAP_MAX_AMSDU;
341c9791 1702 if (cap & MWL8K_CAP_GREENFIELD)
777ad375 1703 band->ht_cap.cap |= IEEE80211_HT_CAP_GRN_FLD;
341c9791
LB		 1704 if (cap & MWL8K_CAP_AMPDU) {
1705 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
777ad375
LB		 1706 band->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
1707 band->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
341c9791
LB		 1708 }
1709 if (cap & MWL8K_CAP_RX_STBC)
777ad375 1710 band->ht_cap.cap |= IEEE80211_HT_CAP_RX_STBC;
341c9791 1711 if (cap & MWL8K_CAP_TX_STBC)
777ad375 1712 band->ht_cap.cap |= IEEE80211_HT_CAP_TX_STBC;
341c9791 1713 if (cap & MWL8K_CAP_SHORTGI_40MHZ)
777ad375 1714 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
341c9791 1715 if (cap & MWL8K_CAP_SHORTGI_20MHZ)
777ad375 1716 band->ht_cap.cap |= IEEE80211_HT_CAP_SGI_20;
341c9791 1717 if (cap & MWL8K_CAP_DELAY_BA)
777ad375 1718 band->ht_cap.cap |= IEEE80211_HT_CAP_DELAY_BA;
341c9791 1719 if (cap & MWL8K_CAP_40MHZ)
777ad375 1720 band->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
341c9791
LB		 1721
1722 rx_streams = hweight32(cap & MWL8K_CAP_RX_ANTENNA_MASK);
1723 tx_streams = hweight32(cap & MWL8K_CAP_TX_ANTENNA_MASK);
1724
777ad375 1725 band->ht_cap.mcs.rx_mask[0] = 0xff;
341c9791 1726 if (rx_streams >= 2)
777ad375 1727 band->ht_cap.mcs.rx_mask[1] = 0xff;
341c9791 1728 if (rx_streams >= 3)
777ad375
LB		 1729 band->ht_cap.mcs.rx_mask[2] = 0xff;
1730 band->ht_cap.mcs.rx_mask[4] = 0x01;
1731 band->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
341c9791
LB		 1732
1733 if (rx_streams != tx_streams) {
777ad375
LB		 1734 band->ht_cap.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
1735 band->ht_cap.mcs.tx_params |= (tx_streams - 1) <<
341c9791
LB		 1736 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
1737 }
1738}
1739
06953235
LB		 1740static void
1741mwl8k_set_caps(struct ieee80211_hw *hw, u32 caps)
1742{
1743 struct mwl8k_priv *priv = hw->priv;
1744
1745 if ((caps & MWL8K_CAP_2GHZ4) || !(caps & MWL8K_CAP_BAND_MASK)) {
1746 mwl8k_setup_2ghz_band(hw);
1747 if (caps & MWL8K_CAP_MIMO)
1748 mwl8k_set_ht_caps(hw, &priv->band_24, caps);
1749 }
1750
1751 if (caps & MWL8K_CAP_5GHZ) {
1752 mwl8k_setup_5ghz_band(hw);
1753 if (caps & MWL8K_CAP_MIMO)
1754 mwl8k_set_ht_caps(hw, &priv->band_50, caps);
1755 }
1756}
1757
04b147b1 1758static int mwl8k_cmd_get_hw_spec_sta(struct ieee80211_hw *hw)
a66098da
LB		 1759{
1760 struct mwl8k_priv *priv = hw->priv;
04b147b1 1761 struct mwl8k_cmd_get_hw_spec_sta *cmd;
a66098da
LB		 1762 int rc;
1763 int i;
1764
1765 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1766 if (cmd == NULL)
1767 return -ENOMEM;
1768
1769 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1770 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1771
1772 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1773 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
45eb400d 1774 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
4ff6432e 1775 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
a66098da 1776 for (i = 0; i < MWL8K_TX_QUEUES; i++)
45eb400d 1777 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
4ff6432e 1778 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
45eb400d 1779 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
a66098da
LB		 1780
1781 rc = mwl8k_post_cmd(hw, &cmd->header);
1782
1783 if (!rc) {
1784 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1785 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
4ff6432e 1786 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
a66098da 1787 priv->hw_rev = cmd->hw_rev;
06953235 1788 mwl8k_set_caps(hw, le32_to_cpu(cmd->caps));
a66098da
LB		 1789 }
1790
1791 kfree(cmd);
1792 return rc;
1793}
1794
42fba21d
LB		 1795/*
1796 * CMD_GET_HW_SPEC (AP version).
1797 */
1798struct mwl8k_cmd_get_hw_spec_ap {
1799 struct mwl8k_cmd_pkt header;
1800 __u8 hw_rev;
1801 __u8 host_interface;
1802 __le16 num_wcb;
1803 __le16 num_mcaddrs;
1804 __u8 perm_addr[ETH_ALEN];
1805 __le16 region_code;
1806 __le16 num_antenna;
1807 __le32 fw_rev;
1808 __le32 wcbbase0;
1809 __le32 rxwrptr;
1810 __le32 rxrdptr;
1811 __le32 ps_cookie;
1812 __le32 wcbbase1;
1813 __le32 wcbbase2;
1814 __le32 wcbbase3;
1815} __attribute__((packed));
1816
1817static int mwl8k_cmd_get_hw_spec_ap(struct ieee80211_hw *hw)
1818{
1819 struct mwl8k_priv *priv = hw->priv;
1820 struct mwl8k_cmd_get_hw_spec_ap *cmd;
1821 int rc;
1822
1823 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1824 if (cmd == NULL)
1825 return -ENOMEM;
1826
1827 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_HW_SPEC);
1828 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1829
1830 memset(cmd->perm_addr, 0xff, sizeof(cmd->perm_addr));
1831 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1832
1833 rc = mwl8k_post_cmd(hw, &cmd->header);
1834
1835 if (!rc) {
1836 int off;
1837
1838 SET_IEEE80211_PERM_ADDR(hw, cmd->perm_addr);
1839 priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
1840 priv->fw_rev = le32_to_cpu(cmd->fw_rev);
1841 priv->hw_rev = cmd->hw_rev;
1349ad2f 1842 mwl8k_setup_2ghz_band(hw);
42fba21d
LB		 1843
1844 off = le32_to_cpu(cmd->wcbbase0) & 0xffff;
1845 iowrite32(cpu_to_le32(priv->txq[0].txd_dma), priv->sram + off);
1846
1847 off = le32_to_cpu(cmd->rxwrptr) & 0xffff;
1848 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1849
1850 off = le32_to_cpu(cmd->rxrdptr) & 0xffff;
1851 iowrite32(cpu_to_le32(priv->rxq[0].rxd_dma), priv->sram + off);
1852
1853 off = le32_to_cpu(cmd->wcbbase1) & 0xffff;
1854 iowrite32(cpu_to_le32(priv->txq[1].txd_dma), priv->sram + off);
1855
1856 off = le32_to_cpu(cmd->wcbbase2) & 0xffff;
1857 iowrite32(cpu_to_le32(priv->txq[2].txd_dma), priv->sram + off);
1858
1859 off = le32_to_cpu(cmd->wcbbase3) & 0xffff;
1860 iowrite32(cpu_to_le32(priv->txq[3].txd_dma), priv->sram + off);
1861 }
1862
1863 kfree(cmd);
1864 return rc;
1865}
1866
1867/*
1868 * CMD_SET_HW_SPEC.
1869 */
1870struct mwl8k_cmd_set_hw_spec {
1871 struct mwl8k_cmd_pkt header;
1872 __u8 hw_rev;
1873 __u8 host_interface;
1874 __le16 num_mcaddrs;
1875 __u8 perm_addr[ETH_ALEN];
1876 __le16 region_code;
1877 __le32 fw_rev;
1878 __le32 ps_cookie;
1879 __le32 caps;
1880 __le32 rx_queue_ptr;
1881 __le32 num_tx_queues;
1882 __le32 tx_queue_ptrs[MWL8K_TX_QUEUES];
1883 __le32 flags;
1884 __le32 num_tx_desc_per_queue;
1885 __le32 total_rxd;
1886} __attribute__((packed));
1887
b64fe619
LB		 1888#define MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT 0x00000080
1889#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP 0x00000020
1890#define MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON 0x00000010
42fba21d
LB		 1891
1892static int mwl8k_cmd_set_hw_spec(struct ieee80211_hw *hw)
1893{
1894 struct mwl8k_priv *priv = hw->priv;
1895 struct mwl8k_cmd_set_hw_spec *cmd;
1896 int rc;
1897 int i;
1898
1899 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
1900 if (cmd == NULL)
1901 return -ENOMEM;
1902
1903 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_HW_SPEC);
1904 cmd->header.length = cpu_to_le16(sizeof(*cmd));
1905
1906 cmd->ps_cookie = cpu_to_le32(priv->cookie_dma);
1907 cmd->rx_queue_ptr = cpu_to_le32(priv->rxq[0].rxd_dma);
1908 cmd->num_tx_queues = cpu_to_le32(MWL8K_TX_QUEUES);
1909 for (i = 0; i < MWL8K_TX_QUEUES; i++)
1910 cmd->tx_queue_ptrs[i] = cpu_to_le32(priv->txq[i].txd_dma);
b64fe619
LB		 1911 cmd->flags = cpu_to_le32(MWL8K_SET_HW_SPEC_FLAG_HOST_DECR_MGMT |
1912 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_PROBERESP |
1913 MWL8K_SET_HW_SPEC_FLAG_HOSTFORM_BEACON);
42fba21d
LB		 1914 cmd->num_tx_desc_per_queue = cpu_to_le32(MWL8K_TX_DESCS);
1915 cmd->total_rxd = cpu_to_le32(MWL8K_RX_DESCS);
1916
1917 rc = mwl8k_post_cmd(hw, &cmd->header);
1918 kfree(cmd);
1919
1920 return rc;
1921}
1922
a66098da
LB		 1923/*
1924 * CMD_MAC_MULTICAST_ADR.
1925 */
1926struct mwl8k_cmd_mac_multicast_adr {
1927 struct mwl8k_cmd_pkt header;
1928 __le16 action;
1929 __le16 numaddr;
ce9e2e1b 1930 __u8 addr[0][ETH_ALEN];
a66098da
LB		 1931};
1932
d5e30845
LB		 1933#define MWL8K_ENABLE_RX_DIRECTED 0x0001
1934#define MWL8K_ENABLE_RX_MULTICAST 0x0002
1935#define MWL8K_ENABLE_RX_ALL_MULTICAST 0x0004
1936#define MWL8K_ENABLE_RX_BROADCAST 0x0008
ce9e2e1b 1937
e81cd2d6 1938static struct mwl8k_cmd_pkt *
447ced07 1939__mwl8k_cmd_mac_multicast_adr(struct ieee80211_hw *hw, int allmulti,
e81cd2d6 1940 int mc_count, struct dev_addr_list *mclist)
a66098da 1941{
e81cd2d6 1942 struct mwl8k_priv *priv = hw->priv;
a66098da 1943 struct mwl8k_cmd_mac_multicast_adr *cmd;
e81cd2d6 1944 int size;
e81cd2d6 1945
447ced07 1946 if (allmulti || mc_count > priv->num_mcaddrs) {
d5e30845
LB		 1947 allmulti = 1;
1948 mc_count = 0;
1949 }
e81cd2d6
LB		 1950
1951 size = sizeof(*cmd) + mc_count * ETH_ALEN;
ce9e2e1b 1952
e81cd2d6 1953 cmd = kzalloc(size, GFP_ATOMIC);
a66098da 1954 if (cmd == NULL)
e81cd2d6 1955 return NULL;
a66098da
LB		 1956
1957 cmd->header.code = cpu_to_le16(MWL8K_CMD_MAC_MULTICAST_ADR);
1958 cmd->header.length = cpu_to_le16(size);
d5e30845
LB		 1959 cmd->action = cpu_to_le16(MWL8K_ENABLE_RX_DIRECTED |
1960 MWL8K_ENABLE_RX_BROADCAST);
1961
1962 if (allmulti) {
1963 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_ALL_MULTICAST);
1964 } else if (mc_count) {
1965 int i;
1966
1967 cmd->action |= cpu_to_le16(MWL8K_ENABLE_RX_MULTICAST);
1968 cmd->numaddr = cpu_to_le16(mc_count);
1969 for (i = 0; i < mc_count && mclist; i++) {
1970 if (mclist->da_addrlen != ETH_ALEN) {
1971 kfree(cmd);
1972 return NULL;
1973 }
1974 memcpy(cmd->addr[i], mclist->da_addr, ETH_ALEN);
1975 mclist = mclist->next;
a66098da 1976 }
a66098da
LB		 1977 }
1978
e81cd2d6 1979 return &cmd->header;
a66098da
LB		 1980}
1981
1982/*
55489b6e 1983 * CMD_GET_STAT.
a66098da 1984 */
55489b6e 1985struct mwl8k_cmd_get_stat {
a66098da 1986 struct mwl8k_cmd_pkt header;
a66098da
LB		 1987 __le32 stats[64];
1988} __attribute__((packed));
1989
1990#define MWL8K_STAT_ACK_FAILURE 9
1991#define MWL8K_STAT_RTS_FAILURE 12
1992#define MWL8K_STAT_FCS_ERROR 24
1993#define MWL8K_STAT_RTS_SUCCESS 11
1994
55489b6e
LB		 1995static int mwl8k_cmd_get_stat(struct ieee80211_hw *hw,
1996 struct ieee80211_low_level_stats *stats)
a66098da 1997{
55489b6e 1998 struct mwl8k_cmd_get_stat *cmd;
a66098da
LB		 1999 int rc;
2000
2001 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2002 if (cmd == NULL)
2003 return -ENOMEM;
2004
2005 cmd->header.code = cpu_to_le16(MWL8K_CMD_GET_STAT);
2006 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2007
2008 rc = mwl8k_post_cmd(hw, &cmd->header);
2009 if (!rc) {
2010 stats->dot11ACKFailureCount =
2011 le32_to_cpu(cmd->stats[MWL8K_STAT_ACK_FAILURE]);
2012 stats->dot11RTSFailureCount =
2013 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_FAILURE]);
2014 stats->dot11FCSErrorCount =
2015 le32_to_cpu(cmd->stats[MWL8K_STAT_FCS_ERROR]);
2016 stats->dot11RTSSuccessCount =
2017 le32_to_cpu(cmd->stats[MWL8K_STAT_RTS_SUCCESS]);
2018 }
2019 kfree(cmd);
2020
2021 return rc;
2022}
2023
2024/*
55489b6e 2025 * CMD_RADIO_CONTROL.
a66098da 2026 */
55489b6e 2027struct mwl8k_cmd_radio_control {
a66098da
LB		 2028 struct mwl8k_cmd_pkt header;
2029 __le16 action;
2030 __le16 control;
2031 __le16 radio_on;
2032} __attribute__((packed));
2033
c46563b7 2034static int
55489b6e 2035mwl8k_cmd_radio_control(struct ieee80211_hw *hw, bool enable, bool force)
a66098da
LB		 2036{
2037 struct mwl8k_priv *priv = hw->priv;
55489b6e 2038 struct mwl8k_cmd_radio_control *cmd;
a66098da
LB		 2039 int rc;
2040
c46563b7 2041 if (enable == priv->radio_on && !force)
a66098da
LB		 2042 return 0;
2043
a66098da
LB		 2044 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2045 if (cmd == NULL)
2046 return -ENOMEM;
2047
2048 cmd->header.code = cpu_to_le16(MWL8K_CMD_RADIO_CONTROL);
2049 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2050 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
68ce3884 2051 cmd->control = cpu_to_le16(priv->radio_short_preamble ? 3 : 1);
a66098da
LB		 2052 cmd->radio_on = cpu_to_le16(enable ? 0x0001 : 0x0000);
2053
2054 rc = mwl8k_post_cmd(hw, &cmd->header);
2055 kfree(cmd);
2056
2057 if (!rc)
c46563b7 2058 priv->radio_on = enable;
a66098da
LB		 2059
2060 return rc;
2061}
2062
55489b6e 2063static int mwl8k_cmd_radio_disable(struct ieee80211_hw *hw)
c46563b7 2064{
55489b6e 2065 return mwl8k_cmd_radio_control(hw, 0, 0);
c46563b7
LB		 2066}
2067
55489b6e 2068static int mwl8k_cmd_radio_enable(struct ieee80211_hw *hw)
c46563b7 2069{
55489b6e 2070 return mwl8k_cmd_radio_control(hw, 1, 0);
c46563b7
LB		 2071}
2072
a66098da
LB		 2073static int
2074mwl8k_set_radio_preamble(struct ieee80211_hw *hw, bool short_preamble)
2075{
99200a99 2076 struct mwl8k_priv *priv = hw->priv;
a66098da 2077
68ce3884 2078 priv->radio_short_preamble = short_preamble;
a66098da 2079
55489b6e 2080 return mwl8k_cmd_radio_control(hw, 1, 1);
a66098da
LB		 2081}
2082
2083/*
55489b6e 2084 * CMD_RF_TX_POWER.
a66098da
LB		 2085 */
2086#define MWL8K_TX_POWER_LEVEL_TOTAL 8
2087
55489b6e 2088struct mwl8k_cmd_rf_tx_power {
a66098da
LB		 2089 struct mwl8k_cmd_pkt header;
2090 __le16 action;
2091 __le16 support_level;
2092 __le16 current_level;
2093 __le16 reserved;
2094 __le16 power_level_list[MWL8K_TX_POWER_LEVEL_TOTAL];
2095} __attribute__((packed));
2096
55489b6e 2097static int mwl8k_cmd_rf_tx_power(struct ieee80211_hw *hw, int dBm)
a66098da 2098{
55489b6e 2099 struct mwl8k_cmd_rf_tx_power *cmd;
a66098da
LB		 2100 int rc;
2101
2102 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2103 if (cmd == NULL)
2104 return -ENOMEM;
2105
2106 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_TX_POWER);
2107 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2108 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2109 cmd->support_level = cpu_to_le16(dBm);
2110
2111 rc = mwl8k_post_cmd(hw, &cmd->header);
2112 kfree(cmd);
2113
2114 return rc;
2115}
2116
08b06347
LB		 2117/*
2118 * CMD_RF_ANTENNA.
2119 */
2120struct mwl8k_cmd_rf_antenna {
2121 struct mwl8k_cmd_pkt header;
2122 __le16 antenna;
2123 __le16 mode;
2124} __attribute__((packed));
2125
2126#define MWL8K_RF_ANTENNA_RX 1
2127#define MWL8K_RF_ANTENNA_TX 2
2128
2129static int
2130mwl8k_cmd_rf_antenna(struct ieee80211_hw *hw, int antenna, int mask)
2131{
2132 struct mwl8k_cmd_rf_antenna *cmd;
2133 int rc;
2134
2135 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2136 if (cmd == NULL)
2137 return -ENOMEM;
2138
2139 cmd->header.code = cpu_to_le16(MWL8K_CMD_RF_ANTENNA);
2140 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2141 cmd->antenna = cpu_to_le16(antenna);
2142 cmd->mode = cpu_to_le16(mask);
2143
2144 rc = mwl8k_post_cmd(hw, &cmd->header);
2145 kfree(cmd);
2146
2147 return rc;
2148}
2149
b64fe619
LB		 2150/*
2151 * CMD_SET_BEACON.
2152 */
2153struct mwl8k_cmd_set_beacon {
2154 struct mwl8k_cmd_pkt header;
2155 __le16 beacon_len;
2156 __u8 beacon[0];
2157};
2158
2159static int mwl8k_cmd_set_beacon(struct ieee80211_hw *hw, u8 *beacon, int len)
2160{
2161 struct mwl8k_cmd_set_beacon *cmd;
2162 int rc;
2163
2164 cmd = kzalloc(sizeof(*cmd) + len, GFP_KERNEL);
2165 if (cmd == NULL)
2166 return -ENOMEM;
2167
2168 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_BEACON);
2169 cmd->header.length = cpu_to_le16(sizeof(*cmd) + len);
2170 cmd->beacon_len = cpu_to_le16(len);
2171 memcpy(cmd->beacon, beacon, len);
2172
2173 rc = mwl8k_post_cmd(hw, &cmd->header);
2174 kfree(cmd);
2175
2176 return rc;
2177}
2178
a66098da
LB		 2179/*
2180 * CMD_SET_PRE_SCAN.
2181 */
2182struct mwl8k_cmd_set_pre_scan {
2183 struct mwl8k_cmd_pkt header;
2184} __attribute__((packed));
2185
2186static int mwl8k_cmd_set_pre_scan(struct ieee80211_hw *hw)
2187{
2188 struct mwl8k_cmd_set_pre_scan *cmd;
2189 int rc;
2190
2191 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2192 if (cmd == NULL)
2193 return -ENOMEM;
2194
2195 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_PRE_SCAN);
2196 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2197
2198 rc = mwl8k_post_cmd(hw, &cmd->header);
2199 kfree(cmd);
2200
2201 return rc;
2202}
2203
2204/*
2205 * CMD_SET_POST_SCAN.
2206 */
2207struct mwl8k_cmd_set_post_scan {
2208 struct mwl8k_cmd_pkt header;
2209 __le32 isibss;
d89173f2 2210 __u8 bssid[ETH_ALEN];
a66098da
LB		 2211} __attribute__((packed));
2212
2213static int
0a11dfc3 2214mwl8k_cmd_set_post_scan(struct ieee80211_hw *hw, const __u8 *mac)
a66098da
LB		 2215{
2216 struct mwl8k_cmd_set_post_scan *cmd;
2217 int rc;
2218
2219 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2220 if (cmd == NULL)
2221 return -ENOMEM;
2222
2223 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_POST_SCAN);
2224 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2225 cmd->isibss = 0;
d89173f2 2226 memcpy(cmd->bssid, mac, ETH_ALEN);
a66098da
LB		 2227
2228 rc = mwl8k_post_cmd(hw, &cmd->header);
2229 kfree(cmd);
2230
2231 return rc;
2232}
2233
2234/*
2235 * CMD_SET_RF_CHANNEL.
2236 */
2237struct mwl8k_cmd_set_rf_channel {
2238 struct mwl8k_cmd_pkt header;
2239 __le16 action;
2240 __u8 current_channel;
2241 __le32 channel_flags;
2242} __attribute__((packed));
2243
2244static int mwl8k_cmd_set_rf_channel(struct ieee80211_hw *hw,
610677d2 2245 struct ieee80211_conf *conf)
a66098da 2246{
610677d2 2247 struct ieee80211_channel *channel = conf->channel;
a66098da
LB		 2248 struct mwl8k_cmd_set_rf_channel *cmd;
2249 int rc;
2250
2251 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2252 if (cmd == NULL)
2253 return -ENOMEM;
2254
2255 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RF_CHANNEL);
2256 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2257 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2258 cmd->current_channel = channel->hw_value;
610677d2 2259
a66098da 2260 if (channel->band == IEEE80211_BAND_2GHZ)
610677d2 2261 cmd->channel_flags |= cpu_to_le32(0x00000001);
42574ea2
LB		 2262 else if (channel->band == IEEE80211_BAND_5GHZ)
2263 cmd->channel_flags |= cpu_to_le32(0x00000004);
610677d2
LB		 2264
2265 if (conf->channel_type == NL80211_CHAN_NO_HT ||
2266 conf->channel_type == NL80211_CHAN_HT20)
2267 cmd->channel_flags |= cpu_to_le32(0x00000080);
2268 else if (conf->channel_type == NL80211_CHAN_HT40MINUS)
2269 cmd->channel_flags |= cpu_to_le32(0x000001900);
2270 else if (conf->channel_type == NL80211_CHAN_HT40PLUS)
2271 cmd->channel_flags |= cpu_to_le32(0x000000900);
a66098da
LB		 2272
2273 rc = mwl8k_post_cmd(hw, &cmd->header);
2274 kfree(cmd);
2275
2276 return rc;
2277}
2278
2279/*
55489b6e 2280 * CMD_SET_AID.
a66098da 2281 */
55489b6e
LB		 2282#define MWL8K_FRAME_PROT_DISABLED 0x00
2283#define MWL8K_FRAME_PROT_11G 0x07
2284#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
2285#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
a66098da 2286
55489b6e
LB		 2287struct mwl8k_cmd_update_set_aid {
2288 struct mwl8k_cmd_pkt header;
2289 __le16 aid;
a66098da 2290
55489b6e
LB		 2291 /* AP's MAC address (BSSID) */
2292 __u8 bssid[ETH_ALEN];
2293 __le16 protection_mode;
2294 __u8 supp_rates[14];
a66098da
LB		 2295} __attribute__((packed));
2296
c6e96010
LB		 2297static void legacy_rate_mask_to_array(u8 *rates, u32 mask)
2298{
2299 int i;
2300 int j;
2301
2302 /*
2303 * Clear nonstandard rates 4 and 13.
2304 */
2305 mask &= 0x1fef;
2306
2307 for (i = 0, j = 0; i < 14; i++) {
2308 if (mask & (1 << i))
777ad375 2309 rates[j++] = mwl8k_rates_24[i].hw_value;
c6e96010
LB		 2310 }
2311}
2312
55489b6e 2313static int
c6e96010
LB		 2314mwl8k_cmd_set_aid(struct ieee80211_hw *hw,
2315 struct ieee80211_vif *vif, u32 legacy_rate_mask)
a66098da 2316{
55489b6e
LB		 2317 struct mwl8k_cmd_update_set_aid *cmd;
2318 u16 prot_mode;
a66098da
LB		 2319 int rc;
2320
2321 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2322 if (cmd == NULL)
2323 return -ENOMEM;
2324
55489b6e 2325 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_AID);
a66098da 2326 cmd->header.length = cpu_to_le16(sizeof(*cmd));
7dc6a7a7 2327 cmd->aid = cpu_to_le16(vif->bss_conf.aid);
0a11dfc3 2328 memcpy(cmd->bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 2329
7dc6a7a7 2330 if (vif->bss_conf.use_cts_prot) {
55489b6e
LB		 2331 prot_mode = MWL8K_FRAME_PROT_11G;
2332 } else {
7dc6a7a7 2333 switch (vif->bss_conf.ht_operation_mode &
55489b6e
LB		 2334 IEEE80211_HT_OP_MODE_PROTECTION) {
2335 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
2336 prot_mode = MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY;
2337 break;
2338 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
2339 prot_mode = MWL8K_FRAME_PROT_11N_HT_ALL;
2340 break;
2341 default:
2342 prot_mode = MWL8K_FRAME_PROT_DISABLED;
2343 break;
2344 }
2345 }
2346 cmd->protection_mode = cpu_to_le16(prot_mode);
a66098da 2347
c6e96010 2348 legacy_rate_mask_to_array(cmd->supp_rates, legacy_rate_mask);
a66098da
LB		 2349
2350 rc = mwl8k_post_cmd(hw, &cmd->header);
2351 kfree(cmd);
2352
2353 return rc;
2354}
2355
32060e1b 2356/*
55489b6e 2357 * CMD_SET_RATE.
32060e1b 2358 */
55489b6e
LB		 2359struct mwl8k_cmd_set_rate {
2360 struct mwl8k_cmd_pkt header;
2361 __u8 legacy_rates[14];
2362
2363 /* Bitmap for supported MCS codes. */
2364 __u8 mcs_set[16];
2365 __u8 reserved[16];
32060e1b
LB		 2366} __attribute__((packed));
2367
55489b6e 2368static int
c6e96010 2369mwl8k_cmd_set_rate(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
13935e2c 2370 u32 legacy_rate_mask, u8 *mcs_rates)
32060e1b 2371{
55489b6e 2372 struct mwl8k_cmd_set_rate *cmd;
32060e1b
LB		 2373 int rc;
2374
2375 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2376 if (cmd == NULL)
2377 return -ENOMEM;
2378
55489b6e 2379 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATE);
32060e1b 2380 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c6e96010 2381 legacy_rate_mask_to_array(cmd->legacy_rates, legacy_rate_mask);
13935e2c 2382 memcpy(cmd->mcs_set, mcs_rates, 16);
32060e1b
LB		 2383
2384 rc = mwl8k_post_cmd(hw, &cmd->header);
2385 kfree(cmd);
2386
2387 return rc;
2388}
2389
a66098da 2390/*
55489b6e 2391 * CMD_FINALIZE_JOIN.
a66098da 2392 */
55489b6e
LB		 2393#define MWL8K_FJ_BEACON_MAXLEN 128
2394
2395struct mwl8k_cmd_finalize_join {
a66098da 2396 struct mwl8k_cmd_pkt header;
55489b6e
LB		 2397 __le32 sleep_interval; /* Number of beacon periods to sleep */
2398 __u8 beacon_data[MWL8K_FJ_BEACON_MAXLEN];
a66098da
LB		 2399} __attribute__((packed));
2400
55489b6e
LB		 2401static int mwl8k_cmd_finalize_join(struct ieee80211_hw *hw, void *frame,
2402 int framelen, int dtim)
a66098da 2403{
55489b6e
LB		 2404 struct mwl8k_cmd_finalize_join *cmd;
2405 struct ieee80211_mgmt *payload = frame;
2406 int payload_len;
a66098da
LB		 2407 int rc;
2408
2409 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2410 if (cmd == NULL)
2411 return -ENOMEM;
2412
55489b6e 2413 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_FINALIZE_JOIN);
a66098da 2414 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2415 cmd->sleep_interval = cpu_to_le32(dtim ? dtim : 1);
2416
2417 payload_len = framelen - ieee80211_hdrlen(payload->frame_control);
2418 if (payload_len < 0)
2419 payload_len = 0;
2420 else if (payload_len > MWL8K_FJ_BEACON_MAXLEN)
2421 payload_len = MWL8K_FJ_BEACON_MAXLEN;
2422
2423 memcpy(cmd->beacon_data, &payload->u.beacon, payload_len);
a66098da
LB		 2424
2425 rc = mwl8k_post_cmd(hw, &cmd->header);
2426 kfree(cmd);
2427
2428 return rc;
2429}
2430
2431/*
55489b6e 2432 * CMD_SET_RTS_THRESHOLD.
a66098da 2433 */
55489b6e 2434struct mwl8k_cmd_set_rts_threshold {
a66098da
LB		 2435 struct mwl8k_cmd_pkt header;
2436 __le16 action;
55489b6e 2437 __le16 threshold;
a66098da
LB		 2438} __attribute__((packed));
2439
c2c2b12a
LB		 2440static int
2441mwl8k_cmd_set_rts_threshold(struct ieee80211_hw *hw, int rts_thresh)
a66098da 2442{
55489b6e 2443 struct mwl8k_cmd_set_rts_threshold *cmd;
a66098da
LB		 2444 int rc;
2445
2446 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2447 if (cmd == NULL)
2448 return -ENOMEM;
2449
55489b6e 2450 cmd->header.code = cpu_to_le16(MWL8K_CMD_RTS_THRESHOLD);
a66098da 2451 cmd->header.length = cpu_to_le16(sizeof(*cmd));
c2c2b12a
LB		 2452 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2453 cmd->threshold = cpu_to_le16(rts_thresh);
a66098da
LB		 2454
2455 rc = mwl8k_post_cmd(hw, &cmd->header);
2456 kfree(cmd);
2457
a66098da
LB		 2458 return rc;
2459}
2460
2461/*
55489b6e 2462 * CMD_SET_SLOT.
a66098da 2463 */
55489b6e 2464struct mwl8k_cmd_set_slot {
a66098da
LB		 2465 struct mwl8k_cmd_pkt header;
2466 __le16 action;
55489b6e 2467 __u8 short_slot;
a66098da
LB		 2468} __attribute__((packed));
2469
55489b6e 2470static int mwl8k_cmd_set_slot(struct ieee80211_hw *hw, bool short_slot_time)
a66098da 2471{
55489b6e 2472 struct mwl8k_cmd_set_slot *cmd;
a66098da
LB		 2473 int rc;
2474
2475 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2476 if (cmd == NULL)
2477 return -ENOMEM;
2478
55489b6e 2479 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_SLOT);
a66098da 2480 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2481 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2482 cmd->short_slot = short_slot_time;
a66098da
LB		 2483
2484 rc = mwl8k_post_cmd(hw, &cmd->header);
2485 kfree(cmd);
2486
2487 return rc;
2488}
2489
2490/*
2491 * CMD_SET_EDCA_PARAMS.
2492 */
2493struct mwl8k_cmd_set_edca_params {
2494 struct mwl8k_cmd_pkt header;
2495
2496 /* See MWL8K_SET_EDCA_XXX below */
2497 __le16 action;
2498
2499 /* TX opportunity in units of 32 us */
2500 __le16 txop;
2501
2e484c89
LB		 2502 union {
2503 struct {
2504 /* Log exponent of max contention period: 0...15 */
2505 __le32 log_cw_max;
2506
2507 /* Log exponent of min contention period: 0...15 */
2508 __le32 log_cw_min;
2509
2510 /* Adaptive interframe spacing in units of 32us */
2511 __u8 aifs;
2512
2513 /* TX queue to configure */
2514 __u8 txq;
2515 } ap;
2516 struct {
2517 /* Log exponent of max contention period: 0...15 */
2518 __u8 log_cw_max;
a66098da 2519
2e484c89
LB		 2520 /* Log exponent of min contention period: 0...15 */
2521 __u8 log_cw_min;
a66098da 2522
2e484c89
LB		 2523 /* Adaptive interframe spacing in units of 32us */
2524 __u8 aifs;
a66098da 2525
2e484c89
LB		 2526 /* TX queue to configure */
2527 __u8 txq;
2528 } sta;
2529 };
a66098da
LB		 2530} __attribute__((packed));
2531
a66098da
LB		 2532#define MWL8K_SET_EDCA_CW 0x01
2533#define MWL8K_SET_EDCA_TXOP 0x02
2534#define MWL8K_SET_EDCA_AIFS 0x04
2535
2536#define MWL8K_SET_EDCA_ALL (MWL8K_SET_EDCA_CW | \
2537 MWL8K_SET_EDCA_TXOP | \
2538 MWL8K_SET_EDCA_AIFS)
2539
2540static int
55489b6e
LB		 2541mwl8k_cmd_set_edca_params(struct ieee80211_hw *hw, __u8 qnum,
2542 __u16 cw_min, __u16 cw_max,
2543 __u8 aifs, __u16 txop)
a66098da 2544{
2e484c89 2545 struct mwl8k_priv *priv = hw->priv;
a66098da 2546 struct mwl8k_cmd_set_edca_params *cmd;
a66098da
LB		 2547 int rc;
2548
2549 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2550 if (cmd == NULL)
2551 return -ENOMEM;
2552
a66098da
LB		 2553 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_EDCA_PARAMS);
2554 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a66098da
LB		 2555 cmd->action = cpu_to_le16(MWL8K_SET_EDCA_ALL);
2556 cmd->txop = cpu_to_le16(txop);
2e484c89
LB		 2557 if (priv->ap_fw) {
2558 cmd->ap.log_cw_max = cpu_to_le32(ilog2(cw_max + 1));
2559 cmd->ap.log_cw_min = cpu_to_le32(ilog2(cw_min + 1));
2560 cmd->ap.aifs = aifs;
2561 cmd->ap.txq = qnum;
2562 } else {
2563 cmd->sta.log_cw_max = (u8)ilog2(cw_max + 1);
2564 cmd->sta.log_cw_min = (u8)ilog2(cw_min + 1);
2565 cmd->sta.aifs = aifs;
2566 cmd->sta.txq = qnum;
2567 }
a66098da
LB		 2568
2569 rc = mwl8k_post_cmd(hw, &cmd->header);
2570 kfree(cmd);
2571
2572 return rc;
2573}
2574
2575/*
55489b6e 2576 * CMD_SET_WMM_MODE.
a66098da 2577 */
55489b6e 2578struct mwl8k_cmd_set_wmm_mode {
a66098da 2579 struct mwl8k_cmd_pkt header;
55489b6e 2580 __le16 action;
a66098da
LB		 2581} __attribute__((packed));
2582
55489b6e 2583static int mwl8k_cmd_set_wmm_mode(struct ieee80211_hw *hw, bool enable)
a66098da 2584{
55489b6e
LB		 2585 struct mwl8k_priv *priv = hw->priv;
2586 struct mwl8k_cmd_set_wmm_mode *cmd;
a66098da
LB		 2587 int rc;
2588
a66098da
LB		 2589 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2590 if (cmd == NULL)
2591 return -ENOMEM;
2592
55489b6e 2593 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_WMM_MODE);
a66098da 2594 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e 2595 cmd->action = cpu_to_le16(!!enable);
a66098da
LB		 2596
2597 rc = mwl8k_post_cmd(hw, &cmd->header);
2598 kfree(cmd);
16cec43d 2599
55489b6e
LB		 2600 if (!rc)
2601 priv->wmm_enabled = enable;
a66098da
LB		 2602
2603 return rc;
2604}
2605
2606/*
55489b6e 2607 * CMD_MIMO_CONFIG.
a66098da 2608 */
55489b6e
LB		 2609struct mwl8k_cmd_mimo_config {
2610 struct mwl8k_cmd_pkt header;
2611 __le32 action;
2612 __u8 rx_antenna_map;
2613 __u8 tx_antenna_map;
a66098da
LB		 2614} __attribute__((packed));
2615
55489b6e 2616static int mwl8k_cmd_mimo_config(struct ieee80211_hw *hw, __u8 rx, __u8 tx)
a66098da 2617{
55489b6e 2618 struct mwl8k_cmd_mimo_config *cmd;
a66098da
LB		 2619 int rc;
2620
2621 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2622 if (cmd == NULL)
2623 return -ENOMEM;
2624
55489b6e 2625 cmd->header.code = cpu_to_le16(MWL8K_CMD_MIMO_CONFIG);
a66098da 2626 cmd->header.length = cpu_to_le16(sizeof(*cmd));
55489b6e
LB		 2627 cmd->action = cpu_to_le32((u32)MWL8K_CMD_SET);
2628 cmd->rx_antenna_map = rx;
2629 cmd->tx_antenna_map = tx;
a66098da
LB		 2630
2631 rc = mwl8k_post_cmd(hw, &cmd->header);
2632 kfree(cmd);
2633
2634 return rc;
2635}
2636
2637/*
b71ed2c6 2638 * CMD_USE_FIXED_RATE (STA version).
a66098da 2639 */
b71ed2c6
LB		 2640struct mwl8k_cmd_use_fixed_rate_sta {
2641 struct mwl8k_cmd_pkt header;
2642 __le32 action;
2643 __le32 allow_rate_drop;
2644 __le32 num_rates;
2645 struct {
2646 __le32 is_ht_rate;
2647 __le32 enable_retry;
2648 __le32 rate;
2649 __le32 retry_count;
2650 } rate_entry[8];
2651 __le32 rate_type;
2652 __le32 reserved1;
2653 __le32 reserved2;
a66098da
LB		 2654} __attribute__((packed));
2655
b71ed2c6
LB		 2656#define MWL8K_USE_AUTO_RATE 0x0002
2657#define MWL8K_UCAST_RATE 0
a66098da 2658
b71ed2c6 2659static int mwl8k_cmd_use_fixed_rate_sta(struct ieee80211_hw *hw)
a66098da 2660{
b71ed2c6 2661 struct mwl8k_cmd_use_fixed_rate_sta *cmd;
a66098da
LB		 2662 int rc;
2663
2664 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2665 if (cmd == NULL)
2666 return -ENOMEM;
2667
2668 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2669 cmd->header.length = cpu_to_le16(sizeof(*cmd));
b71ed2c6
LB		 2670 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2671 cmd->rate_type = cpu_to_le32(MWL8K_UCAST_RATE);
a66098da
LB		 2672
2673 rc = mwl8k_post_cmd(hw, &cmd->header);
2674 kfree(cmd);
2675
2676 return rc;
2677}
2678
088aab8b
LB		 2679/*
2680 * CMD_USE_FIXED_RATE (AP version).
2681 */
2682struct mwl8k_cmd_use_fixed_rate_ap {
2683 struct mwl8k_cmd_pkt header;
2684 __le32 action;
2685 __le32 allow_rate_drop;
2686 __le32 num_rates;
2687 struct mwl8k_rate_entry_ap {
2688 __le32 is_ht_rate;
2689 __le32 enable_retry;
2690 __le32 rate;
2691 __le32 retry_count;
2692 } rate_entry[4];
2693 u8 multicast_rate;
2694 u8 multicast_rate_type;
2695 u8 management_rate;
2696} __attribute__((packed));
2697
2698static int
2699mwl8k_cmd_use_fixed_rate_ap(struct ieee80211_hw *hw, int mcast, int mgmt)
2700{
2701 struct mwl8k_cmd_use_fixed_rate_ap *cmd;
2702 int rc;
2703
2704 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2705 if (cmd == NULL)
2706 return -ENOMEM;
2707
2708 cmd->header.code = cpu_to_le16(MWL8K_CMD_USE_FIXED_RATE);
2709 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2710 cmd->action = cpu_to_le32(MWL8K_USE_AUTO_RATE);
2711 cmd->multicast_rate = mcast;
2712 cmd->management_rate = mgmt;
2713
2714 rc = mwl8k_post_cmd(hw, &cmd->header);
2715 kfree(cmd);
2716
2717 return rc;
2718}
2719
55489b6e
LB		 2720/*
2721 * CMD_ENABLE_SNIFFER.
2722 */
2723struct mwl8k_cmd_enable_sniffer {
2724 struct mwl8k_cmd_pkt header;
2725 __le32 action;
2726} __attribute__((packed));
2727
2728static int mwl8k_cmd_enable_sniffer(struct ieee80211_hw *hw, bool enable)
2729{
2730 struct mwl8k_cmd_enable_sniffer *cmd;
2731 int rc;
2732
2733 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2734 if (cmd == NULL)
2735 return -ENOMEM;
2736
2737 cmd->header.code = cpu_to_le16(MWL8K_CMD_ENABLE_SNIFFER);
2738 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2739 cmd->action = cpu_to_le32(!!enable);
2740
2741 rc = mwl8k_post_cmd(hw, &cmd->header);
2742 kfree(cmd);
2743
2744 return rc;
2745}
2746
2747/*
2748 * CMD_SET_MAC_ADDR.
2749 */
2750struct mwl8k_cmd_set_mac_addr {
2751 struct mwl8k_cmd_pkt header;
2752 union {
2753 struct {
2754 __le16 mac_type;
2755 __u8 mac_addr[ETH_ALEN];
2756 } mbss;
2757 __u8 mac_addr[ETH_ALEN];
2758 };
2759} __attribute__((packed));
2760
a9e00b15
LB		 2761#define MWL8K_MAC_TYPE_PRIMARY_CLIENT 0
2762#define MWL8K_MAC_TYPE_PRIMARY_AP 2
2763
55489b6e
LB		 2764static int mwl8k_cmd_set_mac_addr(struct ieee80211_hw *hw, u8 *mac)
2765{
2766 struct mwl8k_priv *priv = hw->priv;
2767 struct mwl8k_cmd_set_mac_addr *cmd;
2768 int rc;
2769
2770 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2771 if (cmd == NULL)
2772 return -ENOMEM;
2773
2774 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_MAC_ADDR);
2775 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2776 if (priv->ap_fw) {
a9e00b15 2777 cmd->mbss.mac_type = cpu_to_le16(MWL8K_MAC_TYPE_PRIMARY_AP);
55489b6e
LB		 2778 memcpy(cmd->mbss.mac_addr, mac, ETH_ALEN);
2779 } else {
2780 memcpy(cmd->mac_addr, mac, ETH_ALEN);
2781 }
2782
2783 rc = mwl8k_post_cmd(hw, &cmd->header);
2784 kfree(cmd);
2785
2786 return rc;
2787}
2788
2789/*
2790 * CMD_SET_RATEADAPT_MODE.
2791 */
2792struct mwl8k_cmd_set_rate_adapt_mode {
2793 struct mwl8k_cmd_pkt header;
2794 __le16 action;
2795 __le16 mode;
2796} __attribute__((packed));
2797
2798static int mwl8k_cmd_set_rateadapt_mode(struct ieee80211_hw *hw, __u16 mode)
2799{
2800 struct mwl8k_cmd_set_rate_adapt_mode *cmd;
2801 int rc;
2802
2803 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2804 if (cmd == NULL)
2805 return -ENOMEM;
2806
2807 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_RATEADAPT_MODE);
2808 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2809 cmd->action = cpu_to_le16(MWL8K_CMD_SET);
2810 cmd->mode = cpu_to_le16(mode);
2811
2812 rc = mwl8k_post_cmd(hw, &cmd->header);
2813 kfree(cmd);
2814
2815 return rc;
2816}
2817
b64fe619
LB		 2818/*
2819 * CMD_BSS_START.
2820 */
2821struct mwl8k_cmd_bss_start {
2822 struct mwl8k_cmd_pkt header;
2823 __le32 enable;
2824} __attribute__((packed));
2825
2826static int mwl8k_cmd_bss_start(struct ieee80211_hw *hw, int enable)
2827{
2828 struct mwl8k_cmd_bss_start *cmd;
2829 int rc;
2830
2831 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2832 if (cmd == NULL)
2833 return -ENOMEM;
2834
2835 cmd->header.code = cpu_to_le16(MWL8K_CMD_BSS_START);
2836 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2837 cmd->enable = cpu_to_le32(enable);
2838
2839 rc = mwl8k_post_cmd(hw, &cmd->header);
2840 kfree(cmd);
2841
2842 return rc;
2843}
2844
3f5610ff
LB		 2845/*
2846 * CMD_SET_NEW_STN.
2847 */
2848struct mwl8k_cmd_set_new_stn {
2849 struct mwl8k_cmd_pkt header;
2850 __le16 aid;
2851 __u8 mac_addr[6];
2852 __le16 stn_id;
2853 __le16 action;
2854 __le16 rsvd;
2855 __le32 legacy_rates;
2856 __u8 ht_rates[4];
2857 __le16 cap_info;
2858 __le16 ht_capabilities_info;
2859 __u8 mac_ht_param_info;
2860 __u8 rev;
2861 __u8 control_channel;
2862 __u8 add_channel;
2863 __le16 op_mode;
2864 __le16 stbc;
2865 __u8 add_qos_info;
2866 __u8 is_qos_sta;
2867 __le32 fw_sta_ptr;
2868} __attribute__((packed));
2869
2870#define MWL8K_STA_ACTION_ADD 0
2871#define MWL8K_STA_ACTION_REMOVE 2
2872
2873static int mwl8k_cmd_set_new_stn_add(struct ieee80211_hw *hw,
2874 struct ieee80211_vif *vif,
2875 struct ieee80211_sta *sta)
2876{
2877 struct mwl8k_cmd_set_new_stn *cmd;
8707d026 2878 u32 rates;
3f5610ff
LB		 2879 int rc;
2880
2881 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2882 if (cmd == NULL)
2883 return -ENOMEM;
2884
2885 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2886 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2887 cmd->aid = cpu_to_le16(sta->aid);
2888 memcpy(cmd->mac_addr, sta->addr, ETH_ALEN);
2889 cmd->stn_id = cpu_to_le16(sta->aid);
2890 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_ADD);
8707d026
LB		 2891 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
2892 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
2893 else
2894 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
2895 cmd->legacy_rates = cpu_to_le32(rates);
3f5610ff
LB		 2896 if (sta->ht_cap.ht_supported) {
2897 cmd->ht_rates[0] = sta->ht_cap.mcs.rx_mask[0];
2898 cmd->ht_rates[1] = sta->ht_cap.mcs.rx_mask[1];
2899 cmd->ht_rates[2] = sta->ht_cap.mcs.rx_mask[2];
2900 cmd->ht_rates[3] = sta->ht_cap.mcs.rx_mask[3];
2901 cmd->ht_capabilities_info = cpu_to_le16(sta->ht_cap.cap);
2902 cmd->mac_ht_param_info = (sta->ht_cap.ampdu_factor & 3) |
2903 ((sta->ht_cap.ampdu_density & 7) << 2);
2904 cmd->is_qos_sta = 1;
2905 }
2906
2907 rc = mwl8k_post_cmd(hw, &cmd->header);
2908 kfree(cmd);
2909
2910 return rc;
2911}
2912
b64fe619
LB		 2913static int mwl8k_cmd_set_new_stn_add_self(struct ieee80211_hw *hw,
2914 struct ieee80211_vif *vif)
2915{
2916 struct mwl8k_cmd_set_new_stn *cmd;
2917 int rc;
2918
2919 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2920 if (cmd == NULL)
2921 return -ENOMEM;
2922
2923 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2924 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2925 memcpy(cmd->mac_addr, vif->addr, ETH_ALEN);
2926
2927 rc = mwl8k_post_cmd(hw, &cmd->header);
2928 kfree(cmd);
2929
2930 return rc;
2931}
2932
3f5610ff
LB		 2933static int mwl8k_cmd_set_new_stn_del(struct ieee80211_hw *hw,
2934 struct ieee80211_vif *vif, u8 *addr)
2935{
2936 struct mwl8k_cmd_set_new_stn *cmd;
2937 int rc;
2938
2939 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
2940 if (cmd == NULL)
2941 return -ENOMEM;
2942
2943 cmd->header.code = cpu_to_le16(MWL8K_CMD_SET_NEW_STN);
2944 cmd->header.length = cpu_to_le16(sizeof(*cmd));
2945 memcpy(cmd->mac_addr, addr, ETH_ALEN);
2946 cmd->action = cpu_to_le16(MWL8K_STA_ACTION_REMOVE);
2947
2948 rc = mwl8k_post_cmd(hw, &cmd->header);
2949 kfree(cmd);
2950
2951 return rc;
2952}
2953
55489b6e
LB		 2954/*
2955 * CMD_UPDATE_STADB.
2956 */
25d81b1e
LB		 2957struct ewc_ht_info {
2958 __le16 control1;
2959 __le16 control2;
2960 __le16 control3;
2961} __attribute__((packed));
2962
2963struct peer_capability_info {
2964 /* Peer type - AP vs. STA. */
2965 __u8 peer_type;
2966
2967 /* Basic 802.11 capabilities from assoc resp. */
2968 __le16 basic_caps;
2969
2970 /* Set if peer supports 802.11n high throughput (HT). */
2971 __u8 ht_support;
2972
2973 /* Valid if HT is supported. */
2974 __le16 ht_caps;
2975 __u8 extended_ht_caps;
2976 struct ewc_ht_info ewc_info;
2977
2978 /* Legacy rate table. Intersection of our rates and peer rates. */
2979 __u8 legacy_rates[12];
2980
2981 /* HT rate table. Intersection of our rates and peer rates. */
2982 __u8 ht_rates[16];
2983 __u8 pad[16];
2984
2985 /* If set, interoperability mode, no proprietary extensions. */
2986 __u8 interop;
2987 __u8 pad2;
2988 __u8 station_id;
2989 __le16 amsdu_enabled;
2990} __attribute__((packed));
2991
55489b6e
LB		 2992struct mwl8k_cmd_update_stadb {
2993 struct mwl8k_cmd_pkt header;
2994
2995 /* See STADB_ACTION_TYPE */
2996 __le32 action;
2997
2998 /* Peer MAC address */
2999 __u8 peer_addr[ETH_ALEN];
3000
3001 __le32 reserved;
3002
3003 /* Peer info - valid during add/update. */
3004 struct peer_capability_info peer_info;
3005} __attribute__((packed));
3006
a680400e
LB		 3007#define MWL8K_STA_DB_MODIFY_ENTRY 1
3008#define MWL8K_STA_DB_DEL_ENTRY 2
3009
3010/* Peer Entry flags - used to define the type of the peer node */
3011#define MWL8K_PEER_TYPE_ACCESSPOINT 2
3012
3013static int mwl8k_cmd_update_stadb_add(struct ieee80211_hw *hw,
c6e96010 3014 struct ieee80211_vif *vif,
13935e2c 3015 struct ieee80211_sta *sta)
55489b6e 3016{
55489b6e 3017 struct mwl8k_cmd_update_stadb *cmd;
a680400e 3018 struct peer_capability_info *p;
8707d026 3019 u32 rates;
55489b6e
LB		 3020 int rc;
3021
3022 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3023 if (cmd == NULL)
3024 return -ENOMEM;
3025
3026 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3027 cmd->header.length = cpu_to_le16(sizeof(*cmd));
a680400e 3028 cmd->action = cpu_to_le32(MWL8K_STA_DB_MODIFY_ENTRY);
13935e2c 3029 memcpy(cmd->peer_addr, sta->addr, ETH_ALEN);
55489b6e 3030
a680400e
LB		 3031 p = &cmd->peer_info;
3032 p->peer_type = MWL8K_PEER_TYPE_ACCESSPOINT;
3033 p->basic_caps = cpu_to_le16(vif->bss_conf.assoc_capability);
13935e2c
LB		 3034 p->ht_support = sta->ht_cap.ht_supported;
3035 p->ht_caps = sta->ht_cap.cap;
3036 p->extended_ht_caps = (sta->ht_cap.ampdu_factor & 3) |
3037 ((sta->ht_cap.ampdu_density & 7) << 2);
8707d026
LB		 3038 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3039 rates = sta->supp_rates[IEEE80211_BAND_2GHZ];
3040 else
3041 rates = sta->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3042 legacy_rate_mask_to_array(p->legacy_rates, rates);
13935e2c 3043 memcpy(p->ht_rates, sta->ht_cap.mcs.rx_mask, 16);
a680400e
LB		 3044 p->interop = 1;
3045 p->amsdu_enabled = 0;
3046
3047 rc = mwl8k_post_cmd(hw, &cmd->header);
3048 kfree(cmd);
3049
3050 return rc ? rc : p->station_id;
3051}
3052
3053static int mwl8k_cmd_update_stadb_del(struct ieee80211_hw *hw,
3054 struct ieee80211_vif *vif, u8 *addr)
3055{
3056 struct mwl8k_cmd_update_stadb *cmd;
3057 int rc;
3058
3059 cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
3060 if (cmd == NULL)
3061 return -ENOMEM;
3062
3063 cmd->header.code = cpu_to_le16(MWL8K_CMD_UPDATE_STADB);
3064 cmd->header.length = cpu_to_le16(sizeof(*cmd));
3065 cmd->action = cpu_to_le32(MWL8K_STA_DB_DEL_ENTRY);
bbfd9128 3066 memcpy(cmd->peer_addr, addr, ETH_ALEN);
55489b6e 3067
a680400e 3068 rc = mwl8k_post_cmd(hw, &cmd->header);
55489b6e
LB		 3069 kfree(cmd);
3070
3071 return rc;
3072}
3073
a66098da
LB		 3074
3075/*
3076 * Interrupt handling.
3077 */
3078static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
3079{
3080 struct ieee80211_hw *hw = dev_id;
3081 struct mwl8k_priv *priv = hw->priv;
3082 u32 status;
3083
3084 status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
a66098da
LB		 3085 if (!status)
3086 return IRQ_NONE;
3087
1e9f9de3
LB		 3088 if (status & MWL8K_A2H_INT_TX_DONE) {
3089 status &= ~MWL8K_A2H_INT_TX_DONE;
3090 tasklet_schedule(&priv->poll_tx_task);
3091 }
3092
a66098da 3093 if (status & MWL8K_A2H_INT_RX_READY) {
67e2eb27
LB		 3094 status &= ~MWL8K_A2H_INT_RX_READY;
3095 tasklet_schedule(&priv->poll_rx_task);
a66098da
LB		 3096 }
3097
67e2eb27
LB		 3098 if (status)
3099 iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3100
a66098da 3101 if (status & MWL8K_A2H_INT_OPC_DONE) {
618952a7 3102 if (priv->hostcmd_wait != NULL)
a66098da 3103 complete(priv->hostcmd_wait);
a66098da
LB		 3104 }
3105
3106 if (status & MWL8K_A2H_INT_QUEUE_EMPTY) {
618952a7 3107 if (!mutex_is_locked(&priv->fw_mutex) &&
88de754a 3108 priv->radio_on && priv->pending_tx_pkts)
618952a7 3109 mwl8k_tx_start(priv);
a66098da
LB		 3110 }
3111
3112 return IRQ_HANDLED;
3113}
3114
1e9f9de3
LB		 3115static void mwl8k_tx_poll(unsigned long data)
3116{
3117 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3118 struct mwl8k_priv *priv = hw->priv;
3119 int limit;
3120 int i;
3121
3122 limit = 32;
3123
3124 spin_lock_bh(&priv->tx_lock);
3125
3126 for (i = 0; i < MWL8K_TX_QUEUES; i++)
3127 limit -= mwl8k_txq_reclaim(hw, i, limit, 0);
3128
3129 if (!priv->pending_tx_pkts && priv->tx_wait != NULL) {
3130 complete(priv->tx_wait);
3131 priv->tx_wait = NULL;
3132 }
3133
3134 spin_unlock_bh(&priv->tx_lock);
3135
3136 if (limit) {
3137 writel(~MWL8K_A2H_INT_TX_DONE,
3138 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3139 } else {
3140 tasklet_schedule(&priv->poll_tx_task);
3141 }
3142}
3143
67e2eb27
LB		 3144static void mwl8k_rx_poll(unsigned long data)
3145{
3146 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
3147 struct mwl8k_priv *priv = hw->priv;
3148 int limit;
3149
3150 limit = 32;
3151 limit -= rxq_process(hw, 0, limit);
3152 limit -= rxq_refill(hw, 0, limit);
3153
3154 if (limit) {
3155 writel(~MWL8K_A2H_INT_RX_READY,
3156 priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
3157 } else {
3158 tasklet_schedule(&priv->poll_rx_task);
3159 }
3160}
3161
a66098da
LB		 3162
3163/*
3164 * Core driver operations.
3165 */
3166static int mwl8k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3167{
3168 struct mwl8k_priv *priv = hw->priv;
3169 int index = skb_get_queue_mapping(skb);
3170 int rc;
3171
9189c100 3172 if (!priv->radio_on) {
a66098da 3173 printk(KERN_DEBUG "%s: dropped TX frame since radio "
c2c357ce 3174 "disabled\n", wiphy_name(hw->wiphy));
a66098da
LB		 3175 dev_kfree_skb(skb);
3176 return NETDEV_TX_OK;
3177 }
3178
3179 rc = mwl8k_txq_xmit(hw, index, skb);
3180
3181 return rc;
3182}
3183
a66098da
LB		 3184static int mwl8k_start(struct ieee80211_hw *hw)
3185{
a66098da
LB		 3186 struct mwl8k_priv *priv = hw->priv;
3187 int rc;
3188
a0607fd3 3189 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 3190 IRQF_SHARED, MWL8K_NAME, hw);
3191 if (rc) {
3192 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 3193 wiphy_name(hw->wiphy));
2ec610cb 3194 return -EIO;
a66098da
LB		 3195 }
3196
67e2eb27 3197 /* Enable TX reclaim and RX tasklets. */
1e9f9de3 3198 tasklet_enable(&priv->poll_tx_task);
67e2eb27 3199 tasklet_enable(&priv->poll_rx_task);
2ec610cb 3200
a66098da 3201 /* Enable interrupts */
c23b5a69 3202 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da 3203
2ec610cb
LB		 3204 rc = mwl8k_fw_lock(hw);
3205 if (!rc) {
55489b6e 3206 rc = mwl8k_cmd_radio_enable(hw);
a66098da 3207
5e4cf166
LB		 3208 if (!priv->ap_fw) {
3209 if (!rc)
55489b6e 3210 rc = mwl8k_cmd_enable_sniffer(hw, 0);
a66098da 3211
5e4cf166
LB		 3212 if (!rc)
3213 rc = mwl8k_cmd_set_pre_scan(hw);
3214
3215 if (!rc)
3216 rc = mwl8k_cmd_set_post_scan(hw,
3217 "\x00\x00\x00\x00\x00\x00");
3218 }
2ec610cb
LB		 3219
3220 if (!rc)
55489b6e 3221 rc = mwl8k_cmd_set_rateadapt_mode(hw, 0);
a66098da 3222
2ec610cb 3223 if (!rc)
55489b6e 3224 rc = mwl8k_cmd_set_wmm_mode(hw, 0);
a66098da 3225
2ec610cb
LB		 3226 mwl8k_fw_unlock(hw);
3227 }
3228
3229 if (rc) {
3230 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
3231 free_irq(priv->pdev->irq, hw);
1e9f9de3 3232 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3233 tasklet_disable(&priv->poll_rx_task);
2ec610cb 3234 }
a66098da
LB		 3235
3236 return rc;
3237}
3238
a66098da
LB		 3239static void mwl8k_stop(struct ieee80211_hw *hw)
3240{
a66098da
LB		 3241 struct mwl8k_priv *priv = hw->priv;
3242 int i;
3243
55489b6e 3244 mwl8k_cmd_radio_disable(hw);
a66098da
LB		 3245
3246 ieee80211_stop_queues(hw);
3247
a66098da 3248 /* Disable interrupts */
a66098da 3249 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 3250 free_irq(priv->pdev->irq, hw);
3251
3252 /* Stop finalize join worker */
3253 cancel_work_sync(&priv->finalize_join_worker);
3254 if (priv->beacon_skb != NULL)
3255 dev_kfree_skb(priv->beacon_skb);
3256
67e2eb27 3257 /* Stop TX reclaim and RX tasklets. */
1e9f9de3 3258 tasklet_disable(&priv->poll_tx_task);
67e2eb27 3259 tasklet_disable(&priv->poll_rx_task);
a66098da 3260
a66098da
LB		 3261 /* Return all skbs to mac80211 */
3262 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 3263 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da
LB		 3264}
3265
3266static int mwl8k_add_interface(struct ieee80211_hw *hw,
f5bb87cf 3267 struct ieee80211_vif *vif)
a66098da
LB		 3268{
3269 struct mwl8k_priv *priv = hw->priv;
3270 struct mwl8k_vif *mwl8k_vif;
3271
3272 /*
3273 * We only support one active interface at a time.
3274 */
f5bb87cf 3275 if (!list_empty(&priv->vif_list))
a66098da
LB		 3276 return -EBUSY;
3277
a43c49a8
LB		 3278 /*
3279 * Reject interface creation if sniffer mode is active, as
3280 * STA operation is mutually exclusive with hardware sniffer
b64fe619 3281 * mode. (Sniffer mode is only used on STA firmware.)
a43c49a8
LB		 3282 */
3283 if (priv->sniffer_enabled) {
3284 printk(KERN_INFO "%s: unable to create STA "
3285 "interface due to sniffer mode being enabled\n",
3286 wiphy_name(hw->wiphy));
3287 return -EINVAL;
3288 }
3289
c2c2b12a
LB		 3290 /* Set the mac address. */
3291 mwl8k_cmd_set_mac_addr(hw, vif->addr);
3292
b64fe619
LB		 3293 if (priv->ap_fw)
3294 mwl8k_cmd_set_new_stn_add_self(hw, vif);
3295
f5bb87cf 3296 /* Setup driver private area. */
1ed32e4f 3297 mwl8k_vif = MWL8K_VIF(vif);
a66098da 3298 memset(mwl8k_vif, 0, sizeof(*mwl8k_vif));
f5bb87cf 3299 mwl8k_vif->vif = vif;
f57ca9c1 3300 mwl8k_vif->macid = 0;
a66098da
LB		 3301 mwl8k_vif->seqno = 0;
3302
f5bb87cf 3303 list_add_tail(&mwl8k_vif->list, &priv->vif_list);
a66098da
LB		 3304
3305 return 0;
3306}
3307
3308static void mwl8k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3309 struct ieee80211_vif *vif)
a66098da
LB		 3310{
3311 struct mwl8k_priv *priv = hw->priv;
f5bb87cf 3312 struct mwl8k_vif *mwl8k_vif = MWL8K_VIF(vif);
a66098da 3313
b64fe619
LB		 3314 if (priv->ap_fw)
3315 mwl8k_cmd_set_new_stn_del(hw, vif, vif->addr);
3316
55489b6e 3317 mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b 3318
f5bb87cf 3319 list_del(&mwl8k_vif->list);
a66098da
LB		 3320}
3321
ee03a932 3322static int mwl8k_config(struct ieee80211_hw *hw, u32 changed)
a66098da 3323{
a66098da
LB		 3324 struct ieee80211_conf *conf = &hw->conf;
3325 struct mwl8k_priv *priv = hw->priv;
ee03a932 3326 int rc;
a66098da 3327
7595d67a 3328 if (conf->flags & IEEE80211_CONF_IDLE) {
55489b6e 3329 mwl8k_cmd_radio_disable(hw);
ee03a932 3330 return 0;
7595d67a
LB		 3331 }
3332
ee03a932
LB		 3333 rc = mwl8k_fw_lock(hw);
3334 if (rc)
3335 return rc;
a66098da 3336
55489b6e 3337 rc = mwl8k_cmd_radio_enable(hw);
ee03a932
LB		 3338 if (rc)
3339 goto out;
a66098da 3340
610677d2 3341 rc = mwl8k_cmd_set_rf_channel(hw, conf);
ee03a932
LB		 3342 if (rc)
3343 goto out;
3344
a66098da
LB		 3345 if (conf->power_level > 18)
3346 conf->power_level = 18;
55489b6e 3347 rc = mwl8k_cmd_rf_tx_power(hw, conf->power_level);
ee03a932
LB		 3348 if (rc)
3349 goto out;
a66098da 3350
08b06347
LB		 3351 if (priv->ap_fw) {
3352 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_RX, 0x7);
3353 if (!rc)
3354 rc = mwl8k_cmd_rf_antenna(hw, MWL8K_RF_ANTENNA_TX, 0x7);
3355 } else {
3356 rc = mwl8k_cmd_mimo_config(hw, 0x7, 0x7);
3357 }
a66098da 3358
ee03a932
LB		 3359out:
3360 mwl8k_fw_unlock(hw);
a66098da 3361
ee03a932 3362 return rc;
a66098da
LB		 3363}
3364
b64fe619
LB		 3365static void
3366mwl8k_bss_info_changed_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3367 struct ieee80211_bss_conf *info, u32 changed)
a66098da 3368{
a66098da 3369 struct mwl8k_priv *priv = hw->priv;
c3cbbe8a 3370 u32 ap_legacy_rates;
13935e2c 3371 u8 ap_mcs_rates[16];
3a980d0a
LB		 3372 int rc;
3373
c3cbbe8a 3374 if (mwl8k_fw_lock(hw))
3a980d0a 3375 return;
a66098da 3376
c3cbbe8a
LB		 3377 /*
3378 * No need to capture a beacon if we're no longer associated.
3379 */
3380 if ((changed & BSS_CHANGED_ASSOC) && !vif->bss_conf.assoc)
3381 priv->capture_beacon = false;
3a980d0a 3382
c3cbbe8a 3383 /*
13935e2c 3384 * Get the AP's legacy and MCS rates.
c3cbbe8a 3385 */
7dc6a7a7 3386 if (vif->bss_conf.assoc) {
c6e96010 3387 struct ieee80211_sta *ap;
c97470dd 3388
c6e96010 3389 rcu_read_lock();
c6e96010 3390
c3cbbe8a
LB		 3391 ap = ieee80211_find_sta(vif, vif->bss_conf.bssid);
3392 if (ap == NULL) {
3393 rcu_read_unlock();
c6e96010 3394 goto out;
c3cbbe8a
LB		 3395 }
3396
8707d026
LB		 3397 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
3398 ap_legacy_rates = ap->supp_rates[IEEE80211_BAND_2GHZ];
3399 } else {
3400 ap_legacy_rates =
3401 ap->supp_rates[IEEE80211_BAND_5GHZ] << 5;
3402 }
13935e2c 3403 memcpy(ap_mcs_rates, ap->ht_cap.mcs.rx_mask, 16);
c3cbbe8a
LB		 3404
3405 rcu_read_unlock();
3406 }
c6e96010 3407
c3cbbe8a 3408 if ((changed & BSS_CHANGED_ASSOC) && vif->bss_conf.assoc) {
13935e2c 3409 rc = mwl8k_cmd_set_rate(hw, vif, ap_legacy_rates, ap_mcs_rates);
3a980d0a
LB		 3410 if (rc)
3411 goto out;
a66098da 3412
b71ed2c6 3413 rc = mwl8k_cmd_use_fixed_rate_sta(hw);
3a980d0a
LB		 3414 if (rc)
3415 goto out;
c3cbbe8a 3416 }
a66098da 3417
c3cbbe8a 3418 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
7dc6a7a7
LB		 3419 rc = mwl8k_set_radio_preamble(hw,
3420 vif->bss_conf.use_short_preamble);
3a980d0a
LB		 3421 if (rc)
3422 goto out;
c3cbbe8a 3423 }
a66098da 3424
c3cbbe8a 3425 if (changed & BSS_CHANGED_ERP_SLOT) {
7dc6a7a7 3426 rc = mwl8k_cmd_set_slot(hw, vif->bss_conf.use_short_slot);
3a980d0a
LB		 3427 if (rc)
3428 goto out;
c3cbbe8a 3429 }
a66098da 3430
c97470dd
LB		 3431 if (vif->bss_conf.assoc &&
3432 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_ERP_CTS_PROT |
3433 BSS_CHANGED_HT))) {
c3cbbe8a 3434 rc = mwl8k_cmd_set_aid(hw, vif, ap_legacy_rates);
3a980d0a
LB		 3435 if (rc)
3436 goto out;
c3cbbe8a 3437 }
a66098da 3438
c3cbbe8a
LB		 3439 if (vif->bss_conf.assoc &&
3440 (changed & (BSS_CHANGED_ASSOC | BSS_CHANGED_BEACON_INT))) {
a66098da
LB		 3441 /*
3442 * Finalize the join. Tell rx handler to process
3443 * next beacon from our BSSID.
3444 */
0a11dfc3 3445 memcpy(priv->capture_bssid, vif->bss_conf.bssid, ETH_ALEN);
a66098da 3446 priv->capture_beacon = true;
a66098da
LB		 3447 }
3448
3a980d0a
LB		 3449out:
3450 mwl8k_fw_unlock(hw);
a66098da
LB		 3451}
3452
b64fe619
LB		 3453static void
3454mwl8k_bss_info_changed_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3455 struct ieee80211_bss_conf *info, u32 changed)
3456{
3457 int rc;
3458
3459 if (mwl8k_fw_lock(hw))
3460 return;
3461
3462 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3463 rc = mwl8k_set_radio_preamble(hw,
3464 vif->bss_conf.use_short_preamble);
3465 if (rc)
3466 goto out;
3467 }
3468
3469 if (changed & BSS_CHANGED_BASIC_RATES) {
3470 int idx;
3471 int rate;
3472
3473 /*
3474 * Use lowest supported basic rate for multicasts
3475 * and management frames (such as probe responses --
3476 * beacons will always go out at 1 Mb/s).
3477 */
3478 idx = ffs(vif->bss_conf.basic_rates);
8707d026
LB		 3479 if (idx)
3480 idx--;
3481
3482 if (hw->conf.channel->band == IEEE80211_BAND_2GHZ)
3483 rate = mwl8k_rates_24[idx].hw_value;
3484 else
3485 rate = mwl8k_rates_50[idx].hw_value;
b64fe619
LB		 3486
3487 mwl8k_cmd_use_fixed_rate_ap(hw, rate, rate);
3488 }
3489
3490 if (changed & (BSS_CHANGED_BEACON_INT | BSS_CHANGED_BEACON)) {
3491 struct sk_buff *skb;
3492
3493 skb = ieee80211_beacon_get(hw, vif);
3494 if (skb != NULL) {
3495 mwl8k_cmd_set_beacon(hw, skb->data, skb->len);
3496 kfree_skb(skb);
3497 }
3498 }
3499
3500 if (changed & BSS_CHANGED_BEACON_ENABLED)
3501 mwl8k_cmd_bss_start(hw, info->enable_beacon);
3502
3503out:
3504 mwl8k_fw_unlock(hw);
3505}
3506
3507static void
3508mwl8k_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3509 struct ieee80211_bss_conf *info, u32 changed)
3510{
3511 struct mwl8k_priv *priv = hw->priv;
3512
3513 if (!priv->ap_fw)
3514 mwl8k_bss_info_changed_sta(hw, vif, info, changed);
3515 else
3516 mwl8k_bss_info_changed_ap(hw, vif, info, changed);
3517}
3518
e81cd2d6
LB		 3519static u64 mwl8k_prepare_multicast(struct ieee80211_hw *hw,
3520 int mc_count, struct dev_addr_list *mclist)
3521{
3522 struct mwl8k_cmd_pkt *cmd;
3523
447ced07
LB		 3524 /*
3525 * Synthesize and return a command packet that programs the
3526 * hardware multicast address filter. At this point we don't
3527 * know whether FIF_ALLMULTI is being requested, but if it is,
3528 * we'll end up throwing this packet away and creating a new
3529 * one in mwl8k_configure_filter().
3530 */
3531 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 0, mc_count, mclist);
e81cd2d6
LB		 3532
3533 return (unsigned long)cmd;
3534}
3535
a43c49a8
LB		 3536static int
3537mwl8k_configure_filter_sniffer(struct ieee80211_hw *hw,
3538 unsigned int changed_flags,
3539 unsigned int *total_flags)
3540{
3541 struct mwl8k_priv *priv = hw->priv;
3542
3543 /*
3544 * Hardware sniffer mode is mutually exclusive with STA
3545 * operation, so refuse to enable sniffer mode if a STA
3546 * interface is active.
3547 */
f5bb87cf 3548 if (!list_empty(&priv->vif_list)) {
a43c49a8
LB		 3549 if (net_ratelimit())
3550 printk(KERN_INFO "%s: not enabling sniffer "
3551 "mode because STA interface is active\n",
3552 wiphy_name(hw->wiphy));
3553 return 0;
3554 }
3555
3556 if (!priv->sniffer_enabled) {
55489b6e 3557 if (mwl8k_cmd_enable_sniffer(hw, 1))
a43c49a8
LB		 3558 return 0;
3559 priv->sniffer_enabled = true;
3560 }
3561
3562 *total_flags &= FIF_PROMISC_IN_BSS | FIF_ALLMULTI |
3563 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL |
3564 FIF_OTHER_BSS;
3565
3566 return 1;
3567}
3568
f5bb87cf
LB		 3569static struct mwl8k_vif *mwl8k_first_vif(struct mwl8k_priv *priv)
3570{
3571 if (!list_empty(&priv->vif_list))
3572 return list_entry(priv->vif_list.next, struct mwl8k_vif, list);
3573
3574 return NULL;
3575}
3576
e6935ea1
LB		 3577static void mwl8k_configure_filter(struct ieee80211_hw *hw,
3578 unsigned int changed_flags,
3579 unsigned int *total_flags,
3580 u64 multicast)
3581{
3582 struct mwl8k_priv *priv = hw->priv;
a43c49a8
LB		 3583 struct mwl8k_cmd_pkt *cmd = (void *)(unsigned long)multicast;
3584
c0adae2c
LB		 3585 /*
3586 * AP firmware doesn't allow fine-grained control over
3587 * the receive filter.
3588 */
3589 if (priv->ap_fw) {
3590 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
3591 kfree(cmd);
3592 return;
3593 }
3594
a43c49a8
LB		 3595 /*
3596 * Enable hardware sniffer mode if FIF_CONTROL or
3597 * FIF_OTHER_BSS is requested.
3598 */
3599 if (*total_flags & (FIF_CONTROL | FIF_OTHER_BSS) &&
3600 mwl8k_configure_filter_sniffer(hw, changed_flags, total_flags)) {
3601 kfree(cmd);
3602 return;
3603 }
a66098da 3604
e6935ea1 3605 /* Clear unsupported feature flags */
447ced07 3606 *total_flags &= FIF_ALLMULTI | FIF_BCN_PRBRESP_PROMISC;
a66098da 3607
90852f7a
LB		 3608 if (mwl8k_fw_lock(hw)) {
3609 kfree(cmd);
e6935ea1 3610 return;
90852f7a 3611 }
a66098da 3612
a43c49a8 3613 if (priv->sniffer_enabled) {
55489b6e 3614 mwl8k_cmd_enable_sniffer(hw, 0);
a43c49a8
LB		 3615 priv->sniffer_enabled = false;
3616 }
3617
e6935ea1 3618 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
77165d88
LB		 3619 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
3620 /*
3621 * Disable the BSS filter.
3622 */
e6935ea1 3623 mwl8k_cmd_set_pre_scan(hw);
77165d88 3624 } else {
f5bb87cf 3625 struct mwl8k_vif *mwl8k_vif;
0a11dfc3 3626 const u8 *bssid;
a94cc97e 3627
77165d88
LB		 3628 /*
3629 * Enable the BSS filter.
3630 *
3631 * If there is an active STA interface, use that
3632 * interface's BSSID, otherwise use a dummy one
3633 * (where the OUI part needs to be nonzero for
3634 * the BSSID to be accepted by POST_SCAN).
3635 */
f5bb87cf
LB		 3636 mwl8k_vif = mwl8k_first_vif(priv);
3637 if (mwl8k_vif != NULL)
3638 bssid = mwl8k_vif->vif->bss_conf.bssid;
3639 else
3640 bssid = "\x01\x00\x00\x00\x00\x00";
a94cc97e 3641
e6935ea1 3642 mwl8k_cmd_set_post_scan(hw, bssid);
a66098da
LB		 3643 }
3644 }
3645
447ced07
LB		 3646 /*
3647 * If FIF_ALLMULTI is being requested, throw away the command
3648 * packet that ->prepare_multicast() built and replace it with
3649 * a command packet that enables reception of all multicast
3650 * packets.
3651 */
3652 if (*total_flags & FIF_ALLMULTI) {
3653 kfree(cmd);
3654 cmd = __mwl8k_cmd_mac_multicast_adr(hw, 1, 0, NULL);
3655 }
3656
3657 if (cmd != NULL) {
3658 mwl8k_post_cmd(hw, cmd);
3659 kfree(cmd);
e6935ea1 3660 }
a66098da 3661
e6935ea1 3662 mwl8k_fw_unlock(hw);
a66098da
LB		 3663}
3664
a66098da
LB		 3665static int mwl8k_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3666{
c2c2b12a 3667 return mwl8k_cmd_set_rts_threshold(hw, value);
a66098da
LB		 3668}
3669
bbfd9128
LB		 3670struct mwl8k_sta_notify_item
3671{
3672 struct list_head list;
3673 struct ieee80211_vif *vif;
3674 enum sta_notify_cmd cmd;
13935e2c 3675 struct ieee80211_sta sta;
bbfd9128
LB		 3676};
3677
3f5610ff
LB		 3678static void
3679mwl8k_do_sta_notify(struct ieee80211_hw *hw, struct mwl8k_sta_notify_item *s)
3680{
3681 struct mwl8k_priv *priv = hw->priv;
3682
3683 /*
3684 * STA firmware uses UPDATE_STADB, AP firmware uses SET_NEW_STN.
3685 */
3686 if (!priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3687 int rc;
3688
3689 rc = mwl8k_cmd_update_stadb_add(hw, s->vif, &s->sta);
3690 if (rc >= 0) {
3691 struct ieee80211_sta *sta;
3692
3693 rcu_read_lock();
3694 sta = ieee80211_find_sta(s->vif, s->sta.addr);
3695 if (sta != NULL)
3696 MWL8K_STA(sta)->peer_id = rc;
3697 rcu_read_unlock();
3698 }
3699 } else if (!priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3700 mwl8k_cmd_update_stadb_del(hw, s->vif, s->sta.addr);
3701 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_ADD) {
3702 mwl8k_cmd_set_new_stn_add(hw, s->vif, &s->sta);
3703 } else if (priv->ap_fw && s->cmd == STA_NOTIFY_REMOVE) {
3704 mwl8k_cmd_set_new_stn_del(hw, s->vif, s->sta.addr);
3705 }
3706}
3707
bbfd9128
LB		 3708static void mwl8k_sta_notify_worker(struct work_struct *work)
3709{
3710 struct mwl8k_priv *priv =
3711 container_of(work, struct mwl8k_priv, sta_notify_worker);
a680400e 3712 struct ieee80211_hw *hw = priv->hw;
bbfd9128
LB		 3713
3714 spin_lock_bh(&priv->sta_notify_list_lock);
3715 while (!list_empty(&priv->sta_notify_list)) {
3716 struct mwl8k_sta_notify_item *s;
bbfd9128
LB		 3717
3718 s = list_entry(priv->sta_notify_list.next,
3719 struct mwl8k_sta_notify_item, list);
3720 list_del(&s->list);
3721
3722 spin_unlock_bh(&priv->sta_notify_list_lock);
3723
3f5610ff 3724 mwl8k_do_sta_notify(hw, s);
bbfd9128
LB		 3725 kfree(s);
3726
3727 spin_lock_bh(&priv->sta_notify_list_lock);
3728 }
3729 spin_unlock_bh(&priv->sta_notify_list_lock);
3730}
3731
3732static void
3733mwl8k_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3734 enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
3735{
3736 struct mwl8k_priv *priv = hw->priv;
3737 struct mwl8k_sta_notify_item *s;
3738
3739 if (cmd != STA_NOTIFY_ADD && cmd != STA_NOTIFY_REMOVE)
3740 return;
3741
3742 s = kmalloc(sizeof(*s), GFP_ATOMIC);
3743 if (s != NULL) {
3744 s->vif = vif;
3745 s->cmd = cmd;
13935e2c 3746 s->sta = *sta;
bbfd9128
LB		 3747
3748 spin_lock(&priv->sta_notify_list_lock);
3749 list_add_tail(&s->list, &priv->sta_notify_list);
3750 spin_unlock(&priv->sta_notify_list_lock);
3751
3752 ieee80211_queue_work(hw, &priv->sta_notify_worker);
3753 }
3754}
3755
a66098da
LB		 3756static int mwl8k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3757 const struct ieee80211_tx_queue_params *params)
3758{
3e4f542c 3759 struct mwl8k_priv *priv = hw->priv;
a66098da 3760 int rc;
a66098da 3761
3e4f542c
LB		 3762 rc = mwl8k_fw_lock(hw);
3763 if (!rc) {
3764 if (!priv->wmm_enabled)
55489b6e 3765 rc = mwl8k_cmd_set_wmm_mode(hw, 1);
a66098da 3766
3e4f542c 3767 if (!rc)
55489b6e
LB		 3768 rc = mwl8k_cmd_set_edca_params(hw, queue,
3769 params->cw_min,
3770 params->cw_max,
3771 params->aifs,
3772 params->txop);
3e4f542c
LB		 3773
3774 mwl8k_fw_unlock(hw);
a66098da 3775 }
3e4f542c 3776
a66098da
LB		 3777 return rc;
3778}
3779
3780static int mwl8k_get_tx_stats(struct ieee80211_hw *hw,
3781 struct ieee80211_tx_queue_stats *stats)
3782{
3783 struct mwl8k_priv *priv = hw->priv;
3784 struct mwl8k_tx_queue *txq;
3785 int index;
3786
3787 spin_lock_bh(&priv->tx_lock);
3788 for (index = 0; index < MWL8K_TX_QUEUES; index++) {
3789 txq = priv->txq + index;
45eb400d 3790 memcpy(&stats[index], &txq->stats,
a66098da
LB		 3791 sizeof(struct ieee80211_tx_queue_stats));
3792 }
3793 spin_unlock_bh(&priv->tx_lock);
a66098da 3794
954ef509 3795 return 0;
a66098da
LB		 3796}
3797
3798static int mwl8k_get_stats(struct ieee80211_hw *hw,
3799 struct ieee80211_low_level_stats *stats)
3800{
55489b6e 3801 return mwl8k_cmd_get_stat(hw, stats);
a66098da
LB		 3802}
3803
a2292d83
LB		 3804static int
3805mwl8k_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
3806 enum ieee80211_ampdu_mlme_action action,
3807 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
3808{
3809 switch (action) {
3810 case IEEE80211_AMPDU_RX_START:
3811 case IEEE80211_AMPDU_RX_STOP:
3812 if (!(hw->flags & IEEE80211_HW_AMPDU_AGGREGATION))
3813 return -ENOTSUPP;
3814 return 0;
3815 default:
3816 return -ENOTSUPP;
3817 }
3818}
3819
a66098da
LB		 3820static const struct ieee80211_ops mwl8k_ops = {
3821 .tx = mwl8k_tx,
3822 .start = mwl8k_start,
3823 .stop = mwl8k_stop,
3824 .add_interface = mwl8k_add_interface,
3825 .remove_interface = mwl8k_remove_interface,
3826 .config = mwl8k_config,
a66098da 3827 .bss_info_changed = mwl8k_bss_info_changed,
3ac64bee 3828 .prepare_multicast = mwl8k_prepare_multicast,
a66098da
LB		 3829 .configure_filter = mwl8k_configure_filter,
3830 .set_rts_threshold = mwl8k_set_rts_threshold,
bbfd9128 3831 .sta_notify = mwl8k_sta_notify,
a66098da
LB		 3832 .conf_tx = mwl8k_conf_tx,
3833 .get_tx_stats = mwl8k_get_tx_stats,
3834 .get_stats = mwl8k_get_stats,
a2292d83 3835 .ampdu_action = mwl8k_ampdu_action,
a66098da
LB		 3836};
3837
a66098da
LB		 3838static void mwl8k_finalize_join_worker(struct work_struct *work)
3839{
3840 struct mwl8k_priv *priv =
3841 container_of(work, struct mwl8k_priv, finalize_join_worker);
3842 struct sk_buff *skb = priv->beacon_skb;
f5bb87cf 3843 struct mwl8k_vif *mwl8k_vif;
a66098da 3844
f5bb87cf
LB		 3845 mwl8k_vif = mwl8k_first_vif(priv);
3846 if (mwl8k_vif != NULL)
3847 mwl8k_cmd_finalize_join(priv->hw, skb->data, skb->len,
3848 mwl8k_vif->vif->bss_conf.dtim_period);
a66098da 3849
f5bb87cf 3850 dev_kfree_skb(skb);
a66098da
LB		 3851 priv->beacon_skb = NULL;
3852}
3853
bcb628d5 3854enum {
9e1b17ea
LB		 3855 MWL8363 = 0,
3856 MWL8687,
bcb628d5 3857 MWL8366,
6f6d1e9a
LB		 3858};
3859
bcb628d5 3860static struct mwl8k_device_info mwl8k_info_tbl[] __devinitdata = {
9e1b17ea
LB		 3861 [MWL8363] = {
3862 .part_name = "88w8363",
3863 .helper_image = "mwl8k/helper_8363.fw",
3864 .fw_image = "mwl8k/fmimage_8363.fw",
3865 },
49eb691c 3866 [MWL8687] = {
bcb628d5
JL		 3867 .part_name = "88w8687",
3868 .helper_image = "mwl8k/helper_8687.fw",
3869 .fw_image = "mwl8k/fmimage_8687.fw",
bcb628d5 3870 },
49eb691c 3871 [MWL8366] = {
bcb628d5
JL		 3872 .part_name = "88w8366",
3873 .helper_image = "mwl8k/helper_8366.fw",
3874 .fw_image = "mwl8k/fmimage_8366.fw",
89a91f4f 3875 .ap_rxd_ops = &rxd_8366_ap_ops,
bcb628d5 3876 },
45a390dd
LB		 3877};
3878
c92d4ede
LB		 3879MODULE_FIRMWARE("mwl8k/helper_8363.fw");
3880MODULE_FIRMWARE("mwl8k/fmimage_8363.fw");
3881MODULE_FIRMWARE("mwl8k/helper_8687.fw");
3882MODULE_FIRMWARE("mwl8k/fmimage_8687.fw");
3883MODULE_FIRMWARE("mwl8k/helper_8366.fw");
3884MODULE_FIRMWARE("mwl8k/fmimage_8366.fw");
3885
45a390dd 3886static DEFINE_PCI_DEVICE_TABLE(mwl8k_pci_id_table) = {
9e1b17ea
LB		 3887 { PCI_VDEVICE(MARVELL, 0x2a0c), .driver_data = MWL8363, },
3888 { PCI_VDEVICE(MARVELL, 0x2a24), .driver_data = MWL8363, },
bcb628d5
JL		 3889 { PCI_VDEVICE(MARVELL, 0x2a2b), .driver_data = MWL8687, },
3890 { PCI_VDEVICE(MARVELL, 0x2a30), .driver_data = MWL8687, },
3891 { PCI_VDEVICE(MARVELL, 0x2a40), .driver_data = MWL8366, },
ca66527c 3892 { PCI_VDEVICE(MARVELL, 0x2a43), .driver_data = MWL8366, },
bcb628d5 3893 { },
45a390dd
LB		 3894};
3895MODULE_DEVICE_TABLE(pci, mwl8k_pci_id_table);
3896
a66098da
LB		 3897static int __devinit mwl8k_probe(struct pci_dev *pdev,
3898 const struct pci_device_id *id)
3899{
2aa7b01f 3900 static int printed_version = 0;
a66098da
LB		 3901 struct ieee80211_hw *hw;
3902 struct mwl8k_priv *priv;
a66098da
LB		 3903 int rc;
3904 int i;
2aa7b01f
LB		 3905
3906 if (!printed_version) {
3907 printk(KERN_INFO "%s version %s\n", MWL8K_DESC, MWL8K_VERSION);
3908 printed_version = 1;
3909 }
a66098da 3910
be695fc4 3911
a66098da
LB		 3912 rc = pci_enable_device(pdev);
3913 if (rc) {
3914 printk(KERN_ERR "%s: Cannot enable new PCI device\n",
3915 MWL8K_NAME);
3916 return rc;
3917 }
3918
3919 rc = pci_request_regions(pdev, MWL8K_NAME);
3920 if (rc) {
3921 printk(KERN_ERR "%s: Cannot obtain PCI resources\n",
3922 MWL8K_NAME);
3db95e50 3923 goto err_disable_device;
a66098da
LB		 3924 }
3925
3926 pci_set_master(pdev);
3927
be695fc4 3928
a66098da
LB		 3929 hw = ieee80211_alloc_hw(sizeof(*priv), &mwl8k_ops);
3930 if (hw == NULL) {
3931 printk(KERN_ERR "%s: ieee80211 alloc failed\n", MWL8K_NAME);
3932 rc = -ENOMEM;
3933 goto err_free_reg;
3934 }
3935
be695fc4
LB		 3936 SET_IEEE80211_DEV(hw, &pdev->dev);
3937 pci_set_drvdata(pdev, hw);
3938
a66098da
LB		 3939 priv = hw->priv;
3940 priv->hw = hw;
3941 priv->pdev = pdev;
bcb628d5 3942 priv->device_info = &mwl8k_info_tbl[id->driver_data];
a66098da 3943
a66098da 3944
5b9482dd
LB		 3945 priv->sram = pci_iomap(pdev, 0, 0x10000);
3946 if (priv->sram == NULL) {
3947 printk(KERN_ERR "%s: Cannot map device SRAM\n",
c2c357ce 3948 wiphy_name(hw->wiphy));
a66098da
LB		 3949 goto err_iounmap;
3950 }
3951
5b9482dd
LB		 3952 /*
3953 * If BAR0 is a 32 bit BAR, the register BAR will be BAR1.
3954 * If BAR0 is a 64 bit BAR, the register BAR will be BAR2.
3955 */
3956 priv->regs = pci_iomap(pdev, 1, 0x10000);
3957 if (priv->regs == NULL) {
3958 priv->regs = pci_iomap(pdev, 2, 0x10000);
3959 if (priv->regs == NULL) {
3960 printk(KERN_ERR "%s: Cannot map device registers\n",
3961 wiphy_name(hw->wiphy));
3962 goto err_iounmap;
3963 }
3964 }
3965
be695fc4
LB		 3966
3967 /* Reset firmware and hardware */
3968 mwl8k_hw_reset(priv);
3969
3970 /* Ask userland hotplug daemon for the device firmware */
3971 rc = mwl8k_request_firmware(priv);
3972 if (rc) {
3973 printk(KERN_ERR "%s: Firmware files not found\n",
3974 wiphy_name(hw->wiphy));
3975 goto err_stop_firmware;
3976 }
3977
3978 /* Load firmware into hardware */
3979 rc = mwl8k_load_firmware(hw);
3980 if (rc) {
3981 printk(KERN_ERR "%s: Cannot start firmware\n",
3982 wiphy_name(hw->wiphy));
3983 goto err_stop_firmware;
3984 }
3985
3986 /* Reclaim memory once firmware is successfully loaded */
3987 mwl8k_release_firmware(priv);
3988
3989
91942230 3990 if (priv->ap_fw) {
89a91f4f 3991 priv->rxd_ops = priv->device_info->ap_rxd_ops;
91942230
LB		 3992 if (priv->rxd_ops == NULL) {
3993 printk(KERN_ERR "%s: Driver does not have AP "
3994 "firmware image support for this hardware\n",
3995 wiphy_name(hw->wiphy));
3996 goto err_stop_firmware;
3997 }
3998 } else {
89a91f4f 3999 priv->rxd_ops = &rxd_sta_ops;
91942230 4000 }
be695fc4
LB		 4001
4002 priv->sniffer_enabled = false;
4003 priv->wmm_enabled = false;
4004 priv->pending_tx_pkts = 0;
4005
4006
a66098da
LB		 4007 /*
4008 * Extra headroom is the size of the required DMA header
4009 * minus the size of the smallest 802.11 frame (CTS frame).
4010 */
4011 hw->extra_tx_headroom =
4012 sizeof(struct mwl8k_dma_data) - sizeof(struct ieee80211_cts);
4013
4014 hw->channel_change_time = 10;
4015
4016 hw->queues = MWL8K_TX_QUEUES;
4017
a66098da 4018 /* Set rssi and noise values to dBm */
ce9e2e1b 4019 hw->flags |= IEEE80211_HW_SIGNAL_DBM | IEEE80211_HW_NOISE_DBM;
a66098da 4020 hw->vif_data_size = sizeof(struct mwl8k_vif);
a680400e 4021 hw->sta_data_size = sizeof(struct mwl8k_sta);
f5bb87cf
LB		 4022
4023 INIT_LIST_HEAD(&priv->vif_list);
a66098da
LB		 4024
4025 /* Set default radio state and preamble */
c46563b7 4026 priv->radio_on = 0;
68ce3884 4027 priv->radio_short_preamble = 0;
a66098da 4028
bbfd9128
LB		 4029 /* Station database handling */
4030 INIT_WORK(&priv->sta_notify_worker, mwl8k_sta_notify_worker);
4031 spin_lock_init(&priv->sta_notify_list_lock);
4032 INIT_LIST_HEAD(&priv->sta_notify_list);
4033
a66098da
LB		 4034 /* Finalize join worker */
4035 INIT_WORK(&priv->finalize_join_worker, mwl8k_finalize_join_worker);
4036
67e2eb27 4037 /* TX reclaim and RX tasklets. */
1e9f9de3
LB		 4038 tasklet_init(&priv->poll_tx_task, mwl8k_tx_poll, (unsigned long)hw);
4039 tasklet_disable(&priv->poll_tx_task);
67e2eb27
LB		 4040 tasklet_init(&priv->poll_rx_task, mwl8k_rx_poll, (unsigned long)hw);
4041 tasklet_disable(&priv->poll_rx_task);
a66098da 4042
a66098da
LB		 4043 /* Power management cookie */
4044 priv->cookie = pci_alloc_consistent(priv->pdev, 4, &priv->cookie_dma);
4045 if (priv->cookie == NULL)
be695fc4 4046 goto err_stop_firmware;
a66098da
LB		 4047
4048 rc = mwl8k_rxq_init(hw, 0);
4049 if (rc)
be695fc4 4050 goto err_free_cookie;
a66098da
LB		 4051 rxq_refill(hw, 0, INT_MAX);
4052
618952a7
LB		 4053 mutex_init(&priv->fw_mutex);
4054 priv->fw_mutex_owner = NULL;
4055 priv->fw_mutex_depth = 0;
618952a7
LB		 4056 priv->hostcmd_wait = NULL;
4057
a66098da
LB		 4058 spin_lock_init(&priv->tx_lock);
4059
88de754a
LB		 4060 priv->tx_wait = NULL;
4061
a66098da
LB		 4062 for (i = 0; i < MWL8K_TX_QUEUES; i++) {
4063 rc = mwl8k_txq_init(hw, i);
4064 if (rc)
4065 goto err_free_queues;
4066 }
4067
4068 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
c23b5a69 4069 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
67e2eb27 4070 iowrite32(MWL8K_A2H_INT_TX_DONE | MWL8K_A2H_INT_RX_READY,
1e9f9de3 4071 priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
a66098da
LB		 4072 iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
4073
a0607fd3 4074 rc = request_irq(priv->pdev->irq, mwl8k_interrupt,
a66098da
LB		 4075 IRQF_SHARED, MWL8K_NAME, hw);
4076 if (rc) {
4077 printk(KERN_ERR "%s: failed to register IRQ handler\n",
c2c357ce 4078 wiphy_name(hw->wiphy));
a66098da
LB		 4079 goto err_free_queues;
4080 }
4081
a66098da
LB		 4082 /*
4083 * Temporarily enable interrupts. Initial firmware host
c2c2b12a 4084 * commands use interrupts and avoid polling. Disable
a66098da
LB		 4085 * interrupts when done.
4086 */
c23b5a69 4087 iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4088
4089 /* Get config data, mac addrs etc */
42fba21d
LB		 4090 if (priv->ap_fw) {
4091 rc = mwl8k_cmd_get_hw_spec_ap(hw);
4092 if (!rc)
4093 rc = mwl8k_cmd_set_hw_spec(hw);
b64fe619
LB		 4094
4095 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_AP);
42fba21d
LB		 4096 } else {
4097 rc = mwl8k_cmd_get_hw_spec_sta(hw);
89a91f4f
LB		 4098
4099 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
42fba21d 4100 }
a66098da 4101 if (rc) {
c2c357ce
LB		 4102 printk(KERN_ERR "%s: Cannot initialise firmware\n",
4103 wiphy_name(hw->wiphy));
be695fc4 4104 goto err_free_irq;
a66098da
LB		 4105 }
4106
4107 /* Turn radio off */
55489b6e 4108 rc = mwl8k_cmd_radio_disable(hw);
a66098da 4109 if (rc) {
c2c357ce 4110 printk(KERN_ERR "%s: Cannot disable\n", wiphy_name(hw->wiphy));
be695fc4 4111 goto err_free_irq;
a66098da
LB		 4112 }
4113
32060e1b 4114 /* Clear MAC address */
55489b6e 4115 rc = mwl8k_cmd_set_mac_addr(hw, "\x00\x00\x00\x00\x00\x00");
32060e1b
LB		 4116 if (rc) {
4117 printk(KERN_ERR "%s: Cannot clear MAC address\n",
4118 wiphy_name(hw->wiphy));
be695fc4 4119 goto err_free_irq;
32060e1b
LB		 4120 }
4121
a66098da 4122 /* Disable interrupts */
a66098da 4123 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4124 free_irq(priv->pdev->irq, hw);
4125
4126 rc = ieee80211_register_hw(hw);
4127 if (rc) {
c2c357ce
LB		 4128 printk(KERN_ERR "%s: Cannot register device\n",
4129 wiphy_name(hw->wiphy));
153458ff 4130 goto err_free_queues;
a66098da
LB		 4131 }
4132
eae74e65 4133 printk(KERN_INFO "%s: %s v%d, %pM, %s firmware %u.%u.%u.%u\n",
a74b295e 4134 wiphy_name(hw->wiphy), priv->device_info->part_name,
45a390dd 4135 priv->hw_rev, hw->wiphy->perm_addr,
eae74e65 4136 priv->ap_fw ? "AP" : "STA",
2aa7b01f
LB		 4137 (priv->fw_rev >> 24) & 0xff, (priv->fw_rev >> 16) & 0xff,
4138 (priv->fw_rev >> 8) & 0xff, priv->fw_rev & 0xff);
a66098da
LB		 4139
4140 return 0;
4141
a66098da 4142err_free_irq:
a66098da 4143 iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
a66098da
LB		 4144 free_irq(priv->pdev->irq, hw);
4145
4146err_free_queues:
4147 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4148 mwl8k_txq_deinit(hw, i);
4149 mwl8k_rxq_deinit(hw, 0);
4150
be695fc4 4151err_free_cookie:
a66098da
LB		 4152 if (priv->cookie != NULL)
4153 pci_free_consistent(priv->pdev, 4,
4154 priv->cookie, priv->cookie_dma);
4155
be695fc4
LB		 4156err_stop_firmware:
4157 mwl8k_hw_reset(priv);
4158 mwl8k_release_firmware(priv);
4159
4160err_iounmap:
a66098da
LB		 4161 if (priv->regs != NULL)
4162 pci_iounmap(pdev, priv->regs);
4163
5b9482dd
LB		 4164 if (priv->sram != NULL)
4165 pci_iounmap(pdev, priv->sram);
4166
a66098da
LB		 4167 pci_set_drvdata(pdev, NULL);
4168 ieee80211_free_hw(hw);
4169
4170err_free_reg:
4171 pci_release_regions(pdev);
3db95e50
LB		 4172
4173err_disable_device:
a66098da
LB		 4174 pci_disable_device(pdev);
4175
4176 return rc;
4177}
4178
230f7af0 4179static void __devexit mwl8k_shutdown(struct pci_dev *pdev)
a66098da
LB		 4180{
4181 printk(KERN_ERR "===>%s(%u)\n", __func__, __LINE__);
4182}
4183
230f7af0 4184static void __devexit mwl8k_remove(struct pci_dev *pdev)
a66098da
LB		 4185{
4186 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
4187 struct mwl8k_priv *priv;
4188 int i;
4189
4190 if (hw == NULL)
4191 return;
4192 priv = hw->priv;
4193
4194 ieee80211_stop_queues(hw);
4195
60aa569f
LB		 4196 ieee80211_unregister_hw(hw);
4197
67e2eb27 4198 /* Remove TX reclaim and RX tasklets. */
1e9f9de3 4199 tasklet_kill(&priv->poll_tx_task);
67e2eb27 4200 tasklet_kill(&priv->poll_rx_task);
a66098da 4201
a66098da
LB		 4202 /* Stop hardware */
4203 mwl8k_hw_reset(priv);
4204
4205 /* Return all skbs to mac80211 */
4206 for (i = 0; i < MWL8K_TX_QUEUES; i++)
efb7c49a 4207 mwl8k_txq_reclaim(hw, i, INT_MAX, 1);
a66098da 4208
a66098da
LB		 4209 for (i = 0; i < MWL8K_TX_QUEUES; i++)
4210 mwl8k_txq_deinit(hw, i);
4211
4212 mwl8k_rxq_deinit(hw, 0);
4213
c2c357ce 4214 pci_free_consistent(priv->pdev, 4, priv->cookie, priv->cookie_dma);
a66098da
LB		 4215
4216 pci_iounmap(pdev, priv->regs);
5b9482dd 4217 pci_iounmap(pdev, priv->sram);
a66098da
LB		 4218 pci_set_drvdata(pdev, NULL);
4219 ieee80211_free_hw(hw);
4220 pci_release_regions(pdev);
4221 pci_disable_device(pdev);
4222}
4223
4224static struct pci_driver mwl8k_driver = {
4225 .name = MWL8K_NAME,
45a390dd 4226 .id_table = mwl8k_pci_id_table,
a66098da
LB		 4227 .probe = mwl8k_probe,
4228 .remove = __devexit_p(mwl8k_remove),
4229 .shutdown = __devexit_p(mwl8k_shutdown),
4230};
4231
4232static int __init mwl8k_init(void)
4233{
4234 return pci_register_driver(&mwl8k_driver);
4235}
4236
4237static void __exit mwl8k_exit(void)
4238{
4239 pci_unregister_driver(&mwl8k_driver);
4240}
4241
4242module_init(mwl8k_init);
4243module_exit(mwl8k_exit);
c2c357ce
LB		 4244
4245MODULE_DESCRIPTION(MWL8K_DESC);
4246MODULE_VERSION(MWL8K_VERSION);
4247MODULE_AUTHOR("Lennert Buytenhek <buytenh@marvell.com>");
4248MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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