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p54: fix rssi auto calibration
[deliverable/linux.git] / drivers / net / wireless / p54 / p54common.c
CommitLineData
eff1a59c
MW		 1
2/*
3 * Common code for mac80211 Prism54 drivers
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/firmware.h>
18#include <linux/etherdevice.h>
19
20#include <net/mac80211.h>
21
22#include "p54.h"
23#include "p54common.h"
24
25MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
26MODULE_DESCRIPTION("Softmac Prism54 common code");
27MODULE_LICENSE("GPL");
28MODULE_ALIAS("prism54common");
29
8318d78a
JB		 30static struct ieee80211_rate p54_rates[] = {
31 { .bitrate = 10, .hw_value = 0, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
32 { .bitrate = 20, .hw_value = 1, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
33 { .bitrate = 55, .hw_value = 2, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
34 { .bitrate = 110, .hw_value = 3, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
35 { .bitrate = 60, .hw_value = 4, },
36 { .bitrate = 90, .hw_value = 5, },
37 { .bitrate = 120, .hw_value = 6, },
38 { .bitrate = 180, .hw_value = 7, },
39 { .bitrate = 240, .hw_value = 8, },
40 { .bitrate = 360, .hw_value = 9, },
41 { .bitrate = 480, .hw_value = 10, },
42 { .bitrate = 540, .hw_value = 11, },
43};
44
45static struct ieee80211_channel p54_channels[] = {
46 { .center_freq = 2412, .hw_value = 1, },
47 { .center_freq = 2417, .hw_value = 2, },
48 { .center_freq = 2422, .hw_value = 3, },
49 { .center_freq = 2427, .hw_value = 4, },
50 { .center_freq = 2432, .hw_value = 5, },
51 { .center_freq = 2437, .hw_value = 6, },
52 { .center_freq = 2442, .hw_value = 7, },
53 { .center_freq = 2447, .hw_value = 8, },
54 { .center_freq = 2452, .hw_value = 9, },
55 { .center_freq = 2457, .hw_value = 10, },
56 { .center_freq = 2462, .hw_value = 11, },
57 { .center_freq = 2467, .hw_value = 12, },
58 { .center_freq = 2472, .hw_value = 13, },
59 { .center_freq = 2484, .hw_value = 14, },
60};
61
c2976ab0 62static struct ieee80211_supported_band band_2GHz = {
8318d78a
JB		 63 .channels = p54_channels,
64 .n_channels = ARRAY_SIZE(p54_channels),
65 .bitrates = p54_rates,
66 .n_bitrates = ARRAY_SIZE(p54_rates),
67};
68
69
eff1a59c
MW		 70void p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
71{
72 struct p54_common *priv = dev->priv;
73 struct bootrec_exp_if *exp_if;
74 struct bootrec *bootrec;
75 u32 *data = (u32 *)fw->data;
76 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
77 u8 *fw_version = NULL;
78 size_t len;
79 int i;
80
81 if (priv->rx_start)
82 return;
83
84 while (data < end_data && *data)
85 data++;
86
87 while (data < end_data && !*data)
88 data++;
89
90 bootrec = (struct bootrec *) data;
91
92 while (bootrec->data <= end_data &&
93 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
94 u32 code = le32_to_cpu(bootrec->code);
95 switch (code) {
96 case BR_CODE_COMPONENT_ID:
dc73c623 97 switch (be32_to_cpu(*(__be32 *)bootrec->data)) {
eff1a59c
MW		 98 case FW_FMAC:
99 printk(KERN_INFO "p54: FreeMAC firmware\n");
100 break;
101 case FW_LM20:
102 printk(KERN_INFO "p54: LM20 firmware\n");
103 break;
104 case FW_LM86:
105 printk(KERN_INFO "p54: LM86 firmware\n");
106 break;
107 case FW_LM87:
108 printk(KERN_INFO "p54: LM87 firmware - not supported yet!\n");
109 break;
110 default:
111 printk(KERN_INFO "p54: unknown firmware\n");
112 break;
113 }
114 break;
115 case BR_CODE_COMPONENT_VERSION:
116 /* 24 bytes should be enough for all firmwares */
117 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
118 fw_version = (unsigned char*)bootrec->data;
119 break;
120 case BR_CODE_DESCR:
dc73c623 121 priv->rx_start = le32_to_cpu(((__le32 *)bootrec->data)[1]);
eff1a59c 122 /* FIXME add sanity checking */
dc73c623 123 priv->rx_end = le32_to_cpu(((__le32 *)bootrec->data)[2]) - 0x3500;
eff1a59c
MW		 124 break;
125 case BR_CODE_EXPOSED_IF:
126 exp_if = (struct bootrec_exp_if *) bootrec->data;
127 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 128 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW		 129 priv->fw_var = le16_to_cpu(exp_if[i].variant);
130 break;
131 case BR_CODE_DEPENDENT_IF:
132 break;
133 case BR_CODE_END_OF_BRA:
134 case LEGACY_BR_CODE_END_OF_BRA:
135 end_data = NULL;
136 break;
137 default:
138 break;
139 }
140 bootrec = (struct bootrec *)&bootrec->data[len];
141 }
142
143 if (fw_version)
144 printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
145 fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
146
147 if (priv->fw_var >= 0x300) {
148 /* Firmware supports QoS, use it! */
57ffc589
JB		 149 priv->tx_stats[0].limit = 3;
150 priv->tx_stats[1].limit = 4;
151 priv->tx_stats[2].limit = 3;
152 priv->tx_stats[3].limit = 1;
eff1a59c
MW		 153 dev->queues = 4;
154 }
155}
156EXPORT_SYMBOL_GPL(p54_parse_firmware);
157
154e3af1
CL		 158static int p54_convert_rev0(struct ieee80211_hw *dev,
159 struct pda_pa_curve_data *curve_data)
eff1a59c
MW		 160{
161 struct p54_common *priv = dev->priv;
154e3af1
CL		 162 struct p54_pa_curve_data_sample *dst;
163 struct pda_pa_curve_data_sample_rev0 *src;
eff1a59c 164 size_t cd_len = sizeof(*curve_data) +
154e3af1 165 (curve_data->points_per_channel*sizeof(*dst) + 2) *
eff1a59c
MW		 166 curve_data->channels;
167 unsigned int i, j;
168 void *source, *target;
169
170 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
171 if (!priv->curve_data)
172 return -ENOMEM;
173
174 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
175 source = curve_data->data;
176 target = priv->curve_data->data;
177 for (i = 0; i < curve_data->channels; i++) {
178 __le16 *freq = source;
179 source += sizeof(__le16);
180 *((__le16 *)target) = *freq;
181 target += sizeof(__le16);
182 for (j = 0; j < curve_data->points_per_channel; j++) {
154e3af1
CL		 183 dst = target;
184 src = source;
eff1a59c 185
154e3af1
CL		 186 dst->rf_power = src->rf_power;
187 dst->pa_detector = src->pa_detector;
188 dst->data_64qam = src->pcv;
eff1a59c
MW		 189 /* "invent" the points for the other modulations */
190#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
154e3af1
CL		 191 dst->data_16qam = SUB(src->pcv, 12);
192 dst->data_qpsk = SUB(dst->data_16qam, 12);
193 dst->data_bpsk = SUB(dst->data_qpsk, 12);
194 dst->data_barker = SUB(dst->data_bpsk, 14);
eff1a59c 195#undef SUB
154e3af1
CL		 196 target += sizeof(*dst);
197 source += sizeof(*src);
eff1a59c
MW		 198 }
199 }
200
201 return 0;
202}
203
154e3af1
CL		 204static int p54_convert_rev1(struct ieee80211_hw *dev,
205 struct pda_pa_curve_data *curve_data)
206{
207 struct p54_common *priv = dev->priv;
208 struct p54_pa_curve_data_sample *dst;
209 struct pda_pa_curve_data_sample_rev1 *src;
210 size_t cd_len = sizeof(*curve_data) +
211 (curve_data->points_per_channel*sizeof(*dst) + 2) *
212 curve_data->channels;
213 unsigned int i, j;
214 void *source, *target;
215
216 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
217 if (!priv->curve_data)
218 return -ENOMEM;
219
220 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
221 source = curve_data->data;
222 target = priv->curve_data->data;
223 for (i = 0; i < curve_data->channels; i++) {
224 __le16 *freq = source;
225 source += sizeof(__le16);
226 *((__le16 *)target) = *freq;
227 target += sizeof(__le16);
228 for (j = 0; j < curve_data->points_per_channel; j++) {
229 memcpy(target, source, sizeof(*src));
230
231 target += sizeof(*dst);
232 source += sizeof(*src);
233 }
234 source++;
235 }
236
237 return 0;
238}
239
eff1a59c
MW		 240int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
241{
242 struct p54_common *priv = dev->priv;
243 struct eeprom_pda_wrap *wrap = NULL;
244 struct pda_entry *entry;
eff1a59c
MW		 245 unsigned int data_len, entry_len;
246 void *tmp;
247 int err;
c2f2d3a0 248 u8 *end = (u8 *)eeprom + len;
eff1a59c
MW		 249
250 wrap = (struct eeprom_pda_wrap *) eeprom;
8c28293f 251 entry = (void *)wrap->data + le16_to_cpu(wrap->len);
c2f2d3a0
JB		 252
253 /* verify that at least the entry length/code fits */
254 while ((u8 *)entry <= end - sizeof(*entry)) {
eff1a59c
MW		 255 entry_len = le16_to_cpu(entry->len);
256 data_len = ((entry_len - 1) << 1);
c2f2d3a0
JB		 257
258 /* abort if entry exceeds whole structure */
259 if ((u8 *)entry + sizeof(*entry) + data_len > end)
260 break;
261
eff1a59c
MW		 262 switch (le16_to_cpu(entry->code)) {
263 case PDR_MAC_ADDRESS:
264 SET_IEEE80211_PERM_ADDR(dev, entry->data);
265 break;
266 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
267 if (data_len < 2) {
268 err = -EINVAL;
269 goto err;
270 }
271
272 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
273 err = -EINVAL;
274 goto err;
275 }
276
277 priv->output_limit = kmalloc(entry->data[1] *
278 sizeof(*priv->output_limit), GFP_KERNEL);
279
280 if (!priv->output_limit) {
281 err = -ENOMEM;
282 goto err;
283 }
284
285 memcpy(priv->output_limit, &entry->data[2],
286 entry->data[1]*sizeof(*priv->output_limit));
287 priv->output_limit_len = entry->data[1];
288 break;
154e3af1
CL		 289 case PDR_PRISM_PA_CAL_CURVE_DATA: {
290 struct pda_pa_curve_data *curve_data =
291 (struct pda_pa_curve_data *)entry->data;
292 if (data_len < sizeof(*curve_data)) {
eff1a59c
MW		 293 err = -EINVAL;
294 goto err;
295 }
296
154e3af1
CL		 297 switch (curve_data->cal_method_rev) {
298 case 0:
299 err = p54_convert_rev0(dev, curve_data);
300 break;
301 case 1:
302 err = p54_convert_rev1(dev, curve_data);
303 break;
304 default:
305 printk(KERN_ERR "p54: unknown curve data "
306 "revision %d\n",
307 curve_data->cal_method_rev);
308 err = -ENODEV;
309 break;
eff1a59c 310 }
154e3af1
CL		 311 if (err)
312 goto err;
eff1a59c 313
154e3af1 314 }
eff1a59c
MW		 315 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
316 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
317 if (!priv->iq_autocal) {
318 err = -ENOMEM;
319 goto err;
320 }
321
322 memcpy(priv->iq_autocal, entry->data, data_len);
323 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
324 break;
325 case PDR_INTERFACE_LIST:
326 tmp = entry->data;
327 while ((u8 *)tmp < entry->data + data_len) {
328 struct bootrec_exp_if *exp_if = tmp;
329 if (le16_to_cpu(exp_if->if_id) == 0xF)
330 priv->rxhw = exp_if->variant & cpu_to_le16(0x07);
331 tmp += sizeof(struct bootrec_exp_if);
332 }
333 break;
334 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
335 priv->version = *(u8 *)(entry->data + 1);
336 break;
337 case PDR_END:
c2f2d3a0
JB		 338 /* make it overrun */
339 entry_len = len;
eff1a59c 340 break;
58e30739
FF		 341 default:
342 printk(KERN_INFO "p54: unknown eeprom code : 0x%x\n",
343 le16_to_cpu(entry->code));
344 break;
eff1a59c
MW		 345 }
346
347 entry = (void *)entry + (entry_len + 1)*2;
eff1a59c
MW		 348 }
349
350 if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) {
351 printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
352 err = -EINVAL;
353 goto err;
354 }
355
356 return 0;
357
358 err:
359 if (priv->iq_autocal) {
360 kfree(priv->iq_autocal);
361 priv->iq_autocal = NULL;
362 }
363
364 if (priv->output_limit) {
365 kfree(priv->output_limit);
366 priv->output_limit = NULL;
367 }
368
369 if (priv->curve_data) {
370 kfree(priv->curve_data);
371 priv->curve_data = NULL;
372 }
373
374 printk(KERN_ERR "p54: eeprom parse failed!\n");
375 return err;
376}
377EXPORT_SYMBOL_GPL(p54_parse_eeprom);
378
379void p54_fill_eeprom_readback(struct p54_control_hdr *hdr)
380{
381 struct p54_eeprom_lm86 *eeprom_hdr;
382
383 hdr->magic1 = cpu_to_le16(0x8000);
384 hdr->len = cpu_to_le16(sizeof(*eeprom_hdr) + 0x2000);
385 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK);
386 hdr->retry1 = hdr->retry2 = 0;
387 eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data;
388 eeprom_hdr->offset = 0x0;
389 eeprom_hdr->len = cpu_to_le16(0x2000);
390}
391EXPORT_SYMBOL_GPL(p54_fill_eeprom_readback);
392
393static void p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
394{
395 struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data;
396 struct ieee80211_rx_status rx_status = {0};
397 u16 freq = le16_to_cpu(hdr->freq);
398
566bfe5a 399 rx_status.signal = hdr->rssi;
8318d78a 400 /* XX correct? */
18d72605 401 rx_status.qual = (100 * hdr->rssi) / 127;
8318d78a 402 rx_status.rate_idx = hdr->rate & 0xf;
eff1a59c 403 rx_status.freq = freq;
8318d78a 404 rx_status.band = IEEE80211_BAND_2GHZ;
eff1a59c
MW		 405 rx_status.antenna = hdr->antenna;
406 rx_status.mactime = le64_to_cpu(hdr->timestamp);
03bffc13 407 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c
MW		 408
409 skb_pull(skb, sizeof(*hdr));
410 skb_trim(skb, le16_to_cpu(hdr->len));
411
412 ieee80211_rx_irqsafe(dev, skb, &rx_status);
413}
414
415static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
416{
417 struct p54_common *priv = dev->priv;
418 int i;
419
eff1a59c 420 for (i = 0; i < dev->queues; i++)
57ffc589 421 if (priv->tx_stats[i].len < priv->tx_stats[i].limit)
eff1a59c
MW		 422 ieee80211_wake_queue(dev, i);
423}
424
425static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
426{
427 struct p54_common *priv = dev->priv;
428 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
429 struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data;
430 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
431 u32 addr = le32_to_cpu(hdr->req_id) - 0x70;
432 struct memrecord *range = NULL;
433 u32 freed = 0;
434 u32 last_addr = priv->rx_start;
435
436 while (entry != (struct sk_buff *)&priv->tx_queue) {
552fe53f
JB		 437 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
438 range = (void *)info->driver_data;
eff1a59c 439 if (range->start_addr == addr) {
eff1a59c
MW		 440 struct p54_control_hdr *entry_hdr;
441 struct p54_tx_control_allocdata *entry_data;
442 int pad = 0;
443
552fe53f
JB		 444 if (entry->next != (struct sk_buff *)&priv->tx_queue) {
445 struct ieee80211_tx_info *ni;
446 struct memrecord *mr;
447
448 ni = IEEE80211_SKB_CB(entry->next);
449 mr = (struct memrecord *)ni->driver_data;
450 freed = mr->start_addr - last_addr;
451 } else
eff1a59c
MW		 452 freed = priv->rx_end - last_addr;
453
454 last_addr = range->end_addr;
455 __skb_unlink(entry, &priv->tx_queue);
e039fa4a 456 memset(&info->status, 0, sizeof(info->status));
eff1a59c
MW		 457 entry_hdr = (struct p54_control_hdr *) entry->data;
458 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
459 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
460 pad = entry_data->align[0];
461
aaa15535 462 priv->tx_stats[entry_data->hw_queue - 4].len--;
e039fa4a 463 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
eff1a59c 464 if (!(payload->status & 0x01))
e039fa4a 465 info->flags |= IEEE80211_TX_STAT_ACK;
eff1a59c 466 else
e039fa4a 467 info->status.excessive_retries = 1;
eff1a59c 468 }
e039fa4a
JB		 469 info->status.retry_count = payload->retries - 1;
470 info->status.ack_signal = le16_to_cpu(payload->ack_rssi);
eff1a59c 471 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
e039fa4a 472 ieee80211_tx_status_irqsafe(dev, entry);
eff1a59c
MW		 473 break;
474 } else
475 last_addr = range->end_addr;
476 entry = entry->next;
477 }
478
479 if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
480 sizeof(struct p54_control_hdr))
481 p54_wake_free_queues(dev);
482}
483
484static void p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
485{
486 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
487
488 switch (le16_to_cpu(hdr->type)) {
489 case P54_CONTROL_TYPE_TXDONE:
490 p54_rx_frame_sent(dev, skb);
491 break;
492 case P54_CONTROL_TYPE_BBP:
493 break;
494 default:
495 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
496 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
497 break;
498 }
499}
500
501/* returns zero if skb can be reused */
502int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
503{
504 u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8;
505 switch (type) {
506 case 0x00:
507 case 0x01:
508 p54_rx_data(dev, skb);
509 return -1;
510 case 0x4d:
511 /* TODO: do something better... but then again, I've never seen this happen */
512 printk(KERN_ERR "%s: Received fault. Probably need to restart hardware now..\n",
513 wiphy_name(dev->wiphy));
514 break;
515 case 0x80:
516 p54_rx_control(dev, skb);
517 break;
518 default:
519 printk(KERN_ERR "%s: unknown frame RXed (0x%02x)\n",
520 wiphy_name(dev->wiphy), type);
521 break;
522 }
523 return 0;
524}
525EXPORT_SYMBOL_GPL(p54_rx);
526
527/*
528 * So, the firmware is somewhat stupid and doesn't know what places in its
529 * memory incoming data should go to. By poking around in the firmware, we
530 * can find some unused memory to upload our packets to. However, data that we
531 * want the card to TX needs to stay intact until the card has told us that
532 * it is done with it. This function finds empty places we can upload to and
533 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
534 * allocated areas.
535 */
536static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
e039fa4a 537 struct p54_control_hdr *data, u32 len)
eff1a59c
MW		 538{
539 struct p54_common *priv = dev->priv;
540 struct sk_buff *entry = priv->tx_queue.next;
541 struct sk_buff *target_skb = NULL;
eff1a59c
MW		 542 u32 last_addr = priv->rx_start;
543 u32 largest_hole = 0;
544 u32 target_addr = priv->rx_start;
545 unsigned long flags;
546 unsigned int left;
547 len = (len + 0x170 + 3) & ~0x3; /* 0x70 headroom, 0x100 tailroom */
548
549 spin_lock_irqsave(&priv->tx_queue.lock, flags);
550 left = skb_queue_len(&priv->tx_queue);
551 while (left--) {
552 u32 hole_size;
e039fa4a
JB		 553 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry);
554 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 555 hole_size = range->start_addr - last_addr;
556 if (!target_skb && hole_size >= len) {
557 target_skb = entry->prev;
558 hole_size -= len;
559 target_addr = last_addr;
560 }
561 largest_hole = max(largest_hole, hole_size);
562 last_addr = range->end_addr;
563 entry = entry->next;
564 }
565 if (!target_skb && priv->rx_end - last_addr >= len) {
566 target_skb = priv->tx_queue.prev;
567 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
568 if (!skb_queue_empty(&priv->tx_queue)) {
e039fa4a
JB		 569 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(target_skb);
570 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 571 target_addr = range->end_addr;
572 }
573 } else
574 largest_hole = max(largest_hole, priv->rx_end - last_addr);
575
576 if (skb) {
e039fa4a
JB		 577 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
578 struct memrecord *range = (void *)info->driver_data;
eff1a59c
MW		 579 range->start_addr = target_addr;
580 range->end_addr = target_addr + len;
eff1a59c
MW		 581 __skb_queue_after(&priv->tx_queue, target_skb, skb);
582 if (largest_hole < IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
583 sizeof(struct p54_control_hdr))
584 ieee80211_stop_queues(dev);
585 }
586 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
587
588 data->req_id = cpu_to_le32(target_addr + 0x70);
589}
590
e039fa4a 591static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
eff1a59c 592{
e039fa4a 593 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
57ffc589 594 struct ieee80211_tx_queue_stats *current_queue;
eff1a59c
MW		 595 struct p54_common *priv = dev->priv;
596 struct p54_control_hdr *hdr;
eda0c003 597 struct ieee80211_hdr *ieee80211hdr = (struct ieee80211_hdr *)skb->data;
eff1a59c 598 struct p54_tx_control_allocdata *txhdr;
eff1a59c
MW		 599 size_t padding, len;
600 u8 rate;
aaa15535 601 u8 cts_rate = 0x20;
eff1a59c 602
e2530083 603 current_queue = &priv->tx_stats[skb_get_queue_mapping(skb)];
eff1a59c
MW		 604 if (unlikely(current_queue->len > current_queue->limit))
605 return NETDEV_TX_BUSY;
606 current_queue->len++;
607 current_queue->count++;
608 if (current_queue->len == current_queue->limit)
e2530083 609 ieee80211_stop_queue(dev, skb_get_queue_mapping(skb));
eff1a59c
MW		 610
611 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
612 len = skb->len;
613
eff1a59c
MW		 614 txhdr = (struct p54_tx_control_allocdata *)
615 skb_push(skb, sizeof(*txhdr) + padding);
616 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
617
618 if (padding)
619 hdr->magic1 = cpu_to_le16(0x4010);
620 else
621 hdr->magic1 = cpu_to_le16(0x0010);
622 hdr->len = cpu_to_le16(len);
e039fa4a
JB		 623 hdr->type = (info->flags & IEEE80211_TX_CTL_NO_ACK) ? 0 : cpu_to_le16(1);
624 hdr->retry1 = hdr->retry2 = info->control.retry_limit;
eff1a59c 625
eff1a59c 626 /* TODO: add support for alternate retry TX rates */
e039fa4a 627 rate = ieee80211_get_tx_rate(dev, info)->hw_value;
aaa15535 628 if (info->flags & IEEE80211_TX_CTL_SHORT_PREAMBLE) {
8318d78a 629 rate |= 0x10;
aaa15535
CL		 630 cts_rate |= 0x10;
631 }
632 if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
eff1a59c 633 rate |= 0x40;
aaa15535
CL		 634 cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value;
635 } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
eff1a59c 636 rate |= 0x20;
aaa15535
CL		 637 cts_rate |= ieee80211_get_rts_cts_rate(dev, info)->hw_value;
638 }
eff1a59c 639 memset(txhdr->rateset, rate, 8);
aaa15535
CL		 640 txhdr->key_type = 0;
641 txhdr->key_len = 0;
642 txhdr->hw_queue = skb_get_queue_mapping(skb) + 4;
643 txhdr->tx_antenna = (info->antenna_sel_tx == 0) ?
e039fa4a 644 2 : info->antenna_sel_tx - 1;
eff1a59c 645 txhdr->output_power = 0x7f; // HW Maximum
aaa15535
CL		 646 txhdr->cts_rate = (info->flags & IEEE80211_TX_CTL_NO_ACK) ?
647 0 : cts_rate;
eff1a59c
MW		 648 if (padding)
649 txhdr->align[0] = padding;
650
eda0c003
LF		 651 /* FIXME: The sequence that follows is needed for this driver to
652 * work with mac80211 since "mac80211: fix TX sequence numbers".
653 * As with the temporary code in rt2x00, changes will be needed
654 * to get proper sequence numbers on beacons. In addition, this
655 * patch places the sequence number in the hardware state, which
656 * limits us to a single virtual state.
657 */
658 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
659 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
660 priv->seqno += 0x10;
661 ieee80211hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
662 ieee80211hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
663 }
e039fa4a
JB		 664 /* modifies skb->cb and with it info, so must be last! */
665 p54_assign_address(dev, skb, hdr, skb->len);
666
eff1a59c
MW		 667 priv->tx(dev, hdr, skb->len, 0);
668 return 0;
669}
670
671static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
672 const u8 *dst, const u8 *src, u8 antenna,
673 u32 magic3, u32 magic8, u32 magic9)
674{
675 struct p54_common *priv = dev->priv;
676 struct p54_control_hdr *hdr;
677 struct p54_tx_control_filter *filter;
678
679 hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) +
ba8007ce 680 priv->tx_hdr_len, GFP_ATOMIC);
eff1a59c
MW		 681 if (!hdr)
682 return -ENOMEM;
683
684 hdr = (void *)hdr + priv->tx_hdr_len;
685
686 filter = (struct p54_tx_control_filter *) hdr->data;
687 hdr->magic1 = cpu_to_le16(0x8001);
688 hdr->len = cpu_to_le16(sizeof(*filter));
e039fa4a 689 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter));
eff1a59c
MW		 690 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
691
692 filter->filter_type = cpu_to_le16(filter_type);
693 memcpy(filter->dst, dst, ETH_ALEN);
694 if (!src)
695 memset(filter->src, ~0, ETH_ALEN);
696 else
697 memcpy(filter->src, src, ETH_ALEN);
698 filter->antenna = antenna;
699 filter->magic3 = cpu_to_le32(magic3);
700 filter->rx_addr = cpu_to_le32(priv->rx_end);
701 filter->max_rx = cpu_to_le16(0x0620); /* FIXME: for usb ver 1.. maybe */
702 filter->rxhw = priv->rxhw;
703 filter->magic8 = cpu_to_le16(magic8);
704 filter->magic9 = cpu_to_le16(magic9);
705
706 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*filter), 1);
707 return 0;
708}
709
710static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
711{
712 struct p54_common *priv = dev->priv;
713 struct p54_control_hdr *hdr;
714 struct p54_tx_control_channel *chan;
715 unsigned int i;
eff1a59c
MW		 716 void *entry;
717
154e3af1 718 hdr = kzalloc(sizeof(*hdr) + sizeof(*chan) +
eff1a59c
MW		 719 priv->tx_hdr_len, GFP_KERNEL);
720 if (!hdr)
721 return -ENOMEM;
722
723 hdr = (void *)hdr + priv->tx_hdr_len;
724
725 chan = (struct p54_tx_control_channel *) hdr->data;
726
727 hdr->magic1 = cpu_to_le16(0x8001);
728 hdr->len = cpu_to_le16(sizeof(*chan));
729 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
154e3af1 730 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*chan));
eff1a59c 731
154e3af1
CL		 732 chan->flags = cpu_to_le16(0x1);
733 chan->dwell = cpu_to_le16(0x0);
eff1a59c
MW		 734
735 for (i = 0; i < priv->iq_autocal_len; i++) {
736 if (priv->iq_autocal[i].freq != freq)
737 continue;
738
739 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
740 sizeof(*priv->iq_autocal));
741 break;
742 }
743 if (i == priv->iq_autocal_len)
744 goto err;
745
746 for (i = 0; i < priv->output_limit_len; i++) {
747 if (priv->output_limit[i].freq != freq)
748 continue;
749
750 chan->val_barker = 0x38;
154e3af1
CL		 751 chan->val_bpsk = chan->dup_bpsk =
752 priv->output_limit[i].val_bpsk;
753 chan->val_qpsk = chan->dup_qpsk =
754 priv->output_limit[i].val_qpsk;
755 chan->val_16qam = chan->dup_16qam =
756 priv->output_limit[i].val_16qam;
757 chan->val_64qam = chan->dup_64qam =
758 priv->output_limit[i].val_64qam;
eff1a59c
MW		 759 break;
760 }
761 if (i == priv->output_limit_len)
762 goto err;
763
eff1a59c
MW		 764 entry = priv->curve_data->data;
765 for (i = 0; i < priv->curve_data->channels; i++) {
766 if (*((__le16 *)entry) != freq) {
767 entry += sizeof(__le16);
154e3af1
CL		 768 entry += sizeof(struct p54_pa_curve_data_sample) *
769 priv->curve_data->points_per_channel;
eff1a59c
MW		 770 continue;
771 }
772
773 entry += sizeof(__le16);
154e3af1
CL		 774 chan->pa_points_per_curve =
775 min(priv->curve_data->points_per_channel, (u8) 8);
776
eff1a59c
MW		 777 memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
778 chan->pa_points_per_curve);
779 break;
780 }
781
154e3af1
CL		 782 chan->rssical_mul = cpu_to_le16(130);
783 chan->rssical_add = cpu_to_le16(0xfe70); /* -400 */
eff1a59c 784
154e3af1 785 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*chan), 1);
eff1a59c
MW		 786 return 0;
787
788 err:
789 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
790 kfree(hdr);
791 return -EINVAL;
792}
793
794static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
795{
796 struct p54_common *priv = dev->priv;
797 struct p54_control_hdr *hdr;
798 struct p54_tx_control_led *led;
799
800 hdr = kzalloc(sizeof(*hdr) + sizeof(*led) +
801 priv->tx_hdr_len, GFP_KERNEL);
802 if (!hdr)
803 return -ENOMEM;
804
805 hdr = (void *)hdr + priv->tx_hdr_len;
806 hdr->magic1 = cpu_to_le16(0x8001);
807 hdr->len = cpu_to_le16(sizeof(*led));
808 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
e039fa4a 809 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led));
eff1a59c
MW		 810
811 led = (struct p54_tx_control_led *) hdr->data;
812 led->mode = cpu_to_le16(mode);
813 led->led_permanent = cpu_to_le16(link);
814 led->led_temporary = cpu_to_le16(act);
815 led->duration = cpu_to_le16(1000);
816
817 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1);
818
819 return 0;
820}
821
3330d7be 822#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, _txop) \
eff1a59c
MW		 823do { \
824 queue.aifs = cpu_to_le16(ai_fs); \
825 queue.cwmin = cpu_to_le16(cw_min); \
826 queue.cwmax = cpu_to_le16(cw_max); \
3330d7be 827 queue.txop = cpu_to_le16(_txop); \
eff1a59c
MW		 828} while(0)
829
830static void p54_init_vdcf(struct ieee80211_hw *dev)
831{
832 struct p54_common *priv = dev->priv;
833 struct p54_control_hdr *hdr;
834 struct p54_tx_control_vdcf *vdcf;
835
836 /* all USB V1 adapters need a extra headroom */
837 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
838 hdr->magic1 = cpu_to_le16(0x8001);
839 hdr->len = cpu_to_le16(sizeof(*vdcf));
840 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT);
841 hdr->req_id = cpu_to_le32(priv->rx_start);
842
843 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
844
3330d7be
JB		 845 P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 47);
846 P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 94);
5200e8cd 847 P54_SET_QUEUE(vdcf->queue[2], 0x0003, 0x000f, 0x03ff, 0);
3330d7be 848 P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0);
eff1a59c
MW		 849}
850
851static void p54_set_vdcf(struct ieee80211_hw *dev)
852{
853 struct p54_common *priv = dev->priv;
854 struct p54_control_hdr *hdr;
855 struct p54_tx_control_vdcf *vdcf;
856
857 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
858
e039fa4a 859 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf));
eff1a59c
MW		 860
861 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
862
863 if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
864 vdcf->slottime = 9;
5423b2ed
CL		 865 vdcf->magic1 = 0x10;
866 vdcf->magic2 = 0x00;
eff1a59c
MW		 867 } else {
868 vdcf->slottime = 20;
869 vdcf->magic1 = 0x0a;
870 vdcf->magic2 = 0x06;
871 }
872
873 /* (see prism54/isl_oid.h for further details) */
874 vdcf->frameburst = cpu_to_le16(0);
875
876 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0);
877}
878
4150c572
JB		 879static int p54_start(struct ieee80211_hw *dev)
880{
881 struct p54_common *priv = dev->priv;
882 int err;
883
69bbc7dc
CL		 884 if (!priv->cached_vdcf) {
885 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf)+
886 priv->tx_hdr_len + sizeof(struct p54_control_hdr),
887 GFP_KERNEL);
888
889 if (!priv->cached_vdcf)
890 return -ENOMEM;
891 }
892
4150c572
JB		 893 err = priv->open(dev);
894 if (!err)
895 priv->mode = IEEE80211_IF_TYPE_MNTR;
896
69bbc7dc
CL		 897 p54_init_vdcf(dev);
898
4150c572
JB		 899 return err;
900}
901
902static void p54_stop(struct ieee80211_hw *dev)
903{
904 struct p54_common *priv = dev->priv;
905 struct sk_buff *skb;
e039fa4a 906 while ((skb = skb_dequeue(&priv->tx_queue)))
4150c572 907 kfree_skb(skb);
4150c572 908 priv->stop(dev);
a2897552 909 priv->mode = IEEE80211_IF_TYPE_INVALID;
4150c572
JB		 910}
911
eff1a59c
MW		 912static int p54_add_interface(struct ieee80211_hw *dev,
913 struct ieee80211_if_init_conf *conf)
914{
915 struct p54_common *priv = dev->priv;
eff1a59c 916
4150c572
JB		 917 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
918 return -EOPNOTSUPP;
eff1a59c
MW		 919
920 switch (conf->type) {
921 case IEEE80211_IF_TYPE_STA:
922 priv->mode = conf->type;
923 break;
924 default:
925 return -EOPNOTSUPP;
926 }
927
4150c572 928 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
eff1a59c
MW		 929
930 p54_set_filter(dev, 0, priv->mac_addr, NULL, 0, 1, 0, 0xF642);
931 p54_set_filter(dev, 0, priv->mac_addr, NULL, 1, 0, 0, 0xF642);
eff1a59c
MW		 932
933 switch (conf->type) {
934 case IEEE80211_IF_TYPE_STA:
935 p54_set_filter(dev, 1, priv->mac_addr, NULL, 0, 0x15F, 0x1F4, 0);
936 break;
4150c572
JB		 937 default:
938 BUG(); /* impossible */
939 break;
eff1a59c
MW		 940 }
941
942 p54_set_leds(dev, 1, 0, 0);
943
944 return 0;
945}
946
947static void p54_remove_interface(struct ieee80211_hw *dev,
948 struct ieee80211_if_init_conf *conf)
949{
950 struct p54_common *priv = dev->priv;
4150c572
JB		 951 priv->mode = IEEE80211_IF_TYPE_MNTR;
952 memset(priv->mac_addr, 0, ETH_ALEN);
953 p54_set_filter(dev, 0, priv->mac_addr, NULL, 2, 0, 0, 0);
eff1a59c
MW		 954}
955
956static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
957{
958 int ret;
6041e2a0 959 struct p54_common *priv = dev->priv;
eff1a59c 960
6041e2a0 961 mutex_lock(&priv->conf_mutex);
8318d78a 962 ret = p54_set_freq(dev, cpu_to_le16(conf->channel->center_freq));
eff1a59c 963 p54_set_vdcf(dev);
6041e2a0 964 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 965 return ret;
966}
967
32bfd35d
JB		 968static int p54_config_interface(struct ieee80211_hw *dev,
969 struct ieee80211_vif *vif,
eff1a59c
MW		 970 struct ieee80211_if_conf *conf)
971{
972 struct p54_common *priv = dev->priv;
973
6041e2a0 974 mutex_lock(&priv->conf_mutex);
eff1a59c
MW		 975 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642);
976 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0);
977 p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
4150c572 978 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
6041e2a0 979 mutex_unlock(&priv->conf_mutex);
eff1a59c
MW		 980 return 0;
981}
982
4150c572
JB		 983static void p54_configure_filter(struct ieee80211_hw *dev,
984 unsigned int changed_flags,
985 unsigned int *total_flags,
986 int mc_count, struct dev_mc_list *mclist)
987{
988 struct p54_common *priv = dev->priv;
989
990 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
991
992 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
993 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
994 p54_set_filter(dev, 0, priv->mac_addr,
995 NULL, 2, 0, 0, 0);
996 else
997 p54_set_filter(dev, 0, priv->mac_addr,
998 priv->bssid, 2, 0, 0, 0);
999 }
1000}
1001
e100bb64 1002static int p54_conf_tx(struct ieee80211_hw *dev, u16 queue,
eff1a59c
MW		 1003 const struct ieee80211_tx_queue_params *params)
1004{
1005 struct p54_common *priv = dev->priv;
1006 struct p54_tx_control_vdcf *vdcf;
1007
1008 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
1009 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
1010
3df5ee60 1011 if ((params) && !(queue > 4)) {
eff1a59c 1012 P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
3330d7be 1013 params->cw_min, params->cw_max, params->txop);
eff1a59c
MW		 1014 } else
1015 return -EINVAL;
1016
1017 p54_set_vdcf(dev);
1018
1019 return 0;
1020}
1021
1022static int p54_get_stats(struct ieee80211_hw *dev,
1023 struct ieee80211_low_level_stats *stats)
1024{
1025 /* TODO */
1026 return 0;
1027}
1028
1029static int p54_get_tx_stats(struct ieee80211_hw *dev,
1030 struct ieee80211_tx_queue_stats *stats)
1031{
1032 struct p54_common *priv = dev->priv;
eff1a59c 1033
57ffc589 1034 memcpy(stats, &priv->tx_stats, sizeof(stats[0]) * dev->queues);
eff1a59c
MW		 1035
1036 return 0;
1037}
1038
1039static const struct ieee80211_ops p54_ops = {
1040 .tx = p54_tx,
4150c572
JB		 1041 .start = p54_start,
1042 .stop = p54_stop,
eff1a59c
MW		 1043 .add_interface = p54_add_interface,
1044 .remove_interface = p54_remove_interface,
1045 .config = p54_config,
1046 .config_interface = p54_config_interface,
4150c572 1047 .configure_filter = p54_configure_filter,
eff1a59c
MW		 1048 .conf_tx = p54_conf_tx,
1049 .get_stats = p54_get_stats,
1050 .get_tx_stats = p54_get_tx_stats
1051};
1052
1053struct ieee80211_hw *p54_init_common(size_t priv_data_len)
1054{
1055 struct ieee80211_hw *dev;
1056 struct p54_common *priv;
eff1a59c
MW		 1057
1058 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
1059 if (!dev)
1060 return NULL;
1061
1062 priv = dev->priv;
a2897552 1063 priv->mode = IEEE80211_IF_TYPE_INVALID;
eff1a59c 1064 skb_queue_head_init(&priv->tx_queue);
8318d78a 1065 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &band_2GHz;
eff1a59c 1066 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
566bfe5a
BR		 1067 IEEE80211_HW_RX_INCLUDES_FCS |
1068 IEEE80211_HW_SIGNAL_UNSPEC;
eff1a59c 1069 dev->channel_change_time = 1000; /* TODO: find actual value */
566bfe5a 1070 dev->max_signal = 127;
eff1a59c 1071
57ffc589 1072 priv->tx_stats[0].limit = 5;
eff1a59c
MW		 1073 dev->queues = 1;
1074
1075 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
1076 sizeof(struct p54_tx_control_allocdata);
1077
6041e2a0 1078 mutex_init(&priv->conf_mutex);
eff1a59c 1079
eff1a59c
MW		 1080 return dev;
1081}
1082EXPORT_SYMBOL_GPL(p54_init_common);
1083
1084void p54_free_common(struct ieee80211_hw *dev)
1085{
1086 struct p54_common *priv = dev->priv;
1087 kfree(priv->iq_autocal);
1088 kfree(priv->output_limit);
1089 kfree(priv->curve_data);
1090 kfree(priv->cached_vdcf);
1091}
1092EXPORT_SYMBOL_GPL(p54_free_common);
1093
1094static int __init p54_init(void)
1095{
1096 return 0;
1097}
1098
1099static void __exit p54_exit(void)
1100{
1101}
1102
1103module_init(p54_init);
1104module_exit(p54_exit);
Linux kernel - Deliverables
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