Commit | Line | Data |
---|---|---|
eff1a59c MW |
1 | |
2 | /* | |
3 | * Linux device driver for PCI based Prism54 | |
4 | * | |
5 | * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net> | |
7262d593 | 6 | * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de> |
eff1a59c MW |
7 | * |
8 | * Based on the islsm (softmac prism54) driver, which is: | |
9 | * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/pci.h> | |
18 | #include <linux/firmware.h> | |
19 | #include <linux/etherdevice.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/completion.h> | |
22 | #include <net/mac80211.h> | |
23 | ||
24 | #include "p54.h" | |
25 | #include "p54pci.h" | |
26 | ||
27 | MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>"); | |
28 | MODULE_DESCRIPTION("Prism54 PCI wireless driver"); | |
29 | MODULE_LICENSE("GPL"); | |
30 | MODULE_ALIAS("prism54pci"); | |
9a8675d7 | 31 | MODULE_FIRMWARE("isl3886pci"); |
eff1a59c MW |
32 | |
33 | static struct pci_device_id p54p_table[] __devinitdata = { | |
34 | /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */ | |
35 | { PCI_DEVICE(0x1260, 0x3890) }, | |
36 | /* 3COM 3CRWE154G72 Wireless LAN adapter */ | |
37 | { PCI_DEVICE(0x10b7, 0x6001) }, | |
38 | /* Intersil PRISM Indigo Wireless LAN adapter */ | |
39 | { PCI_DEVICE(0x1260, 0x3877) }, | |
40 | /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */ | |
41 | { PCI_DEVICE(0x1260, 0x3886) }, | |
90f4dd0f | 42 | { }, |
eff1a59c MW |
43 | }; |
44 | ||
45 | MODULE_DEVICE_TABLE(pci, p54p_table); | |
46 | ||
47 | static int p54p_upload_firmware(struct ieee80211_hw *dev) | |
48 | { | |
49 | struct p54p_priv *priv = dev->priv; | |
eff1a59c MW |
50 | __le32 reg; |
51 | int err; | |
8160c031 | 52 | __le32 *data; |
eff1a59c MW |
53 | u32 remains, left, device_addr; |
54 | ||
8160c031 | 55 | P54P_WRITE(int_enable, cpu_to_le32(0)); |
eff1a59c MW |
56 | P54P_READ(int_enable); |
57 | udelay(10); | |
58 | ||
59 | reg = P54P_READ(ctrl_stat); | |
60 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); | |
61 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT); | |
62 | P54P_WRITE(ctrl_stat, reg); | |
63 | P54P_READ(ctrl_stat); | |
64 | udelay(10); | |
65 | ||
66 | reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET); | |
67 | P54P_WRITE(ctrl_stat, reg); | |
68 | wmb(); | |
69 | udelay(10); | |
70 | ||
71 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); | |
72 | P54P_WRITE(ctrl_stat, reg); | |
73 | wmb(); | |
74 | ||
40db0b22 CL |
75 | /* wait for the firmware to reset properly */ |
76 | mdelay(10); | |
eff1a59c | 77 | |
40db0b22 CL |
78 | err = p54_parse_firmware(dev, priv->firmware); |
79 | if (err) | |
4e416a6f | 80 | return err; |
eff1a59c | 81 | |
e365f160 CL |
82 | if (priv->common.fw_interface != FW_LM86) { |
83 | dev_err(&priv->pdev->dev, "wrong firmware, " | |
84 | "please get a LM86(PCI) firmware a try again.\n"); | |
85 | return -EINVAL; | |
86 | } | |
87 | ||
40db0b22 CL |
88 | data = (__le32 *) priv->firmware->data; |
89 | remains = priv->firmware->size; | |
eff1a59c MW |
90 | device_addr = ISL38XX_DEV_FIRMWARE_ADDR; |
91 | while (remains) { | |
92 | u32 i = 0; | |
93 | left = min((u32)0x1000, remains); | |
94 | P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr)); | |
95 | P54P_READ(int_enable); | |
96 | ||
97 | device_addr += 0x1000; | |
98 | while (i < left) { | |
99 | P54P_WRITE(direct_mem_win[i], *data++); | |
100 | i += sizeof(u32); | |
101 | } | |
102 | ||
103 | remains -= left; | |
104 | P54P_READ(int_enable); | |
105 | } | |
106 | ||
eff1a59c MW |
107 | reg = P54P_READ(ctrl_stat); |
108 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN); | |
109 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); | |
110 | reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT); | |
111 | P54P_WRITE(ctrl_stat, reg); | |
112 | P54P_READ(ctrl_stat); | |
113 | udelay(10); | |
114 | ||
115 | reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET); | |
116 | P54P_WRITE(ctrl_stat, reg); | |
117 | wmb(); | |
118 | udelay(10); | |
119 | ||
120 | reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET); | |
121 | P54P_WRITE(ctrl_stat, reg); | |
122 | wmb(); | |
123 | udelay(10); | |
124 | ||
7cb77072 | 125 | /* wait for the firmware to boot properly */ |
eff1a59c | 126 | mdelay(100); |
eff1a59c | 127 | |
7cb77072 | 128 | return 0; |
eff1a59c MW |
129 | } |
130 | ||
7262d593 CL |
131 | static void p54p_refill_rx_ring(struct ieee80211_hw *dev, |
132 | int ring_index, struct p54p_desc *ring, u32 ring_limit, | |
133 | struct sk_buff **rx_buf) | |
eff1a59c MW |
134 | { |
135 | struct p54p_priv *priv = dev->priv; | |
eb76bf29 | 136 | struct p54p_ring_control *ring_control = priv->ring_control; |
7262d593 | 137 | u32 limit, idx, i; |
eff1a59c | 138 | |
7262d593 CL |
139 | idx = le32_to_cpu(ring_control->host_idx[ring_index]); |
140 | limit = idx; | |
141 | limit -= le32_to_cpu(ring_control->device_idx[ring_index]); | |
142 | limit = ring_limit - limit; | |
eff1a59c | 143 | |
7262d593 | 144 | i = idx % ring_limit; |
eff1a59c | 145 | while (limit-- > 1) { |
7262d593 | 146 | struct p54p_desc *desc = &ring[i]; |
eff1a59c MW |
147 | |
148 | if (!desc->host_addr) { | |
149 | struct sk_buff *skb; | |
150 | dma_addr_t mapping; | |
4e416a6f | 151 | skb = dev_alloc_skb(priv->common.rx_mtu + 32); |
eff1a59c MW |
152 | if (!skb) |
153 | break; | |
154 | ||
155 | mapping = pci_map_single(priv->pdev, | |
156 | skb_tail_pointer(skb), | |
4e416a6f | 157 | priv->common.rx_mtu + 32, |
eff1a59c MW |
158 | PCI_DMA_FROMDEVICE); |
159 | desc->host_addr = cpu_to_le32(mapping); | |
160 | desc->device_addr = 0; // FIXME: necessary? | |
4e416a6f | 161 | desc->len = cpu_to_le16(priv->common.rx_mtu + 32); |
eff1a59c | 162 | desc->flags = 0; |
7262d593 | 163 | rx_buf[i] = skb; |
eff1a59c MW |
164 | } |
165 | ||
7262d593 | 166 | i++; |
eff1a59c | 167 | idx++; |
7262d593 | 168 | i %= ring_limit; |
eff1a59c MW |
169 | } |
170 | ||
171 | wmb(); | |
7262d593 CL |
172 | ring_control->host_idx[ring_index] = cpu_to_le32(idx); |
173 | } | |
174 | ||
175 | static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index, | |
176 | int ring_index, struct p54p_desc *ring, u32 ring_limit, | |
177 | struct sk_buff **rx_buf) | |
178 | { | |
179 | struct p54p_priv *priv = dev->priv; | |
180 | struct p54p_ring_control *ring_control = priv->ring_control; | |
181 | struct p54p_desc *desc; | |
182 | u32 idx, i; | |
183 | ||
184 | i = (*index) % ring_limit; | |
185 | (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]); | |
186 | idx %= ring_limit; | |
187 | while (i != idx) { | |
188 | u16 len; | |
189 | struct sk_buff *skb; | |
190 | desc = &ring[i]; | |
191 | len = le16_to_cpu(desc->len); | |
192 | skb = rx_buf[i]; | |
193 | ||
0c25970d CL |
194 | if (!skb) { |
195 | i++; | |
196 | i %= ring_limit; | |
7262d593 | 197 | continue; |
0c25970d | 198 | } |
7262d593 CL |
199 | skb_put(skb, len); |
200 | ||
201 | if (p54_rx(dev, skb)) { | |
202 | pci_unmap_single(priv->pdev, | |
203 | le32_to_cpu(desc->host_addr), | |
4e416a6f CL |
204 | priv->common.rx_mtu + 32, |
205 | PCI_DMA_FROMDEVICE); | |
7262d593 CL |
206 | rx_buf[i] = NULL; |
207 | desc->host_addr = 0; | |
208 | } else { | |
209 | skb_trim(skb, 0); | |
4e416a6f | 210 | desc->len = cpu_to_le16(priv->common.rx_mtu + 32); |
7262d593 CL |
211 | } |
212 | ||
213 | i++; | |
214 | i %= ring_limit; | |
215 | } | |
216 | ||
217 | p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf); | |
218 | } | |
219 | ||
220 | /* caller must hold priv->lock */ | |
221 | static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index, | |
222 | int ring_index, struct p54p_desc *ring, u32 ring_limit, | |
223 | void **tx_buf) | |
224 | { | |
225 | struct p54p_priv *priv = dev->priv; | |
226 | struct p54p_ring_control *ring_control = priv->ring_control; | |
227 | struct p54p_desc *desc; | |
228 | u32 idx, i; | |
229 | ||
230 | i = (*index) % ring_limit; | |
231 | (*index) = idx = le32_to_cpu(ring_control->device_idx[1]); | |
232 | idx %= ring_limit; | |
233 | ||
234 | while (i != idx) { | |
235 | desc = &ring[i]; | |
0a5ec96a CL |
236 | if (tx_buf[i]) |
237 | if (FREE_AFTER_TX((struct sk_buff *) tx_buf[i])) | |
238 | p54_free_skb(dev, tx_buf[i]); | |
7262d593 CL |
239 | tx_buf[i] = NULL; |
240 | ||
241 | pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr), | |
242 | le16_to_cpu(desc->len), PCI_DMA_TODEVICE); | |
243 | ||
244 | desc->host_addr = 0; | |
245 | desc->device_addr = 0; | |
246 | desc->len = 0; | |
247 | desc->flags = 0; | |
248 | ||
249 | i++; | |
250 | i %= ring_limit; | |
251 | } | |
252 | } | |
253 | ||
254 | static void p54p_rx_tasklet(unsigned long dev_id) | |
255 | { | |
256 | struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id; | |
257 | struct p54p_priv *priv = dev->priv; | |
258 | struct p54p_ring_control *ring_control = priv->ring_control; | |
259 | ||
260 | p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt, | |
261 | ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt); | |
262 | ||
263 | p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data, | |
264 | ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data); | |
265 | ||
266 | wmb(); | |
267 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); | |
eff1a59c MW |
268 | } |
269 | ||
270 | static irqreturn_t p54p_interrupt(int irq, void *dev_id) | |
271 | { | |
272 | struct ieee80211_hw *dev = dev_id; | |
273 | struct p54p_priv *priv = dev->priv; | |
eb76bf29 | 274 | struct p54p_ring_control *ring_control = priv->ring_control; |
eff1a59c MW |
275 | __le32 reg; |
276 | ||
277 | spin_lock(&priv->lock); | |
278 | reg = P54P_READ(int_ident); | |
8160c031 | 279 | if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) { |
eff1a59c MW |
280 | spin_unlock(&priv->lock); |
281 | return IRQ_HANDLED; | |
282 | } | |
283 | ||
284 | P54P_WRITE(int_ack, reg); | |
285 | ||
286 | reg &= P54P_READ(int_enable); | |
287 | ||
288 | if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)) { | |
7262d593 CL |
289 | p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, |
290 | 3, ring_control->tx_mgmt, | |
291 | ARRAY_SIZE(ring_control->tx_mgmt), | |
292 | priv->tx_buf_mgmt); | |
eff1a59c | 293 | |
7262d593 CL |
294 | p54p_check_tx_ring(dev, &priv->tx_idx_data, |
295 | 1, ring_control->tx_data, | |
296 | ARRAY_SIZE(ring_control->tx_data), | |
297 | priv->tx_buf_data); | |
eff1a59c | 298 | |
7262d593 | 299 | tasklet_schedule(&priv->rx_tasklet); |
eff1a59c | 300 | |
eff1a59c MW |
301 | } else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT)) |
302 | complete(&priv->boot_comp); | |
303 | ||
304 | spin_unlock(&priv->lock); | |
305 | ||
306 | return reg ? IRQ_HANDLED : IRQ_NONE; | |
307 | } | |
308 | ||
0a5ec96a | 309 | static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb) |
eff1a59c MW |
310 | { |
311 | struct p54p_priv *priv = dev->priv; | |
eb76bf29 | 312 | struct p54p_ring_control *ring_control = priv->ring_control; |
eff1a59c MW |
313 | unsigned long flags; |
314 | struct p54p_desc *desc; | |
315 | dma_addr_t mapping; | |
316 | u32 device_idx, idx, i; | |
317 | ||
318 | spin_lock_irqsave(&priv->lock, flags); | |
319 | ||
eb76bf29 DT |
320 | device_idx = le32_to_cpu(ring_control->device_idx[1]); |
321 | idx = le32_to_cpu(ring_control->host_idx[1]); | |
322 | i = idx % ARRAY_SIZE(ring_control->tx_data); | |
eff1a59c | 323 | |
0a5ec96a | 324 | priv->tx_buf_data[i] = skb; |
b92f30d6 CL |
325 | mapping = pci_map_single(priv->pdev, skb->data, skb->len, |
326 | PCI_DMA_TODEVICE); | |
eb76bf29 | 327 | desc = &ring_control->tx_data[i]; |
eff1a59c | 328 | desc->host_addr = cpu_to_le32(mapping); |
27df605e | 329 | desc->device_addr = ((struct p54_hdr *)skb->data)->req_id; |
b92f30d6 | 330 | desc->len = cpu_to_le16(skb->len); |
eff1a59c MW |
331 | desc->flags = 0; |
332 | ||
333 | wmb(); | |
eb76bf29 | 334 | ring_control->host_idx[1] = cpu_to_le32(idx + 1); |
eff1a59c MW |
335 | spin_unlock_irqrestore(&priv->lock, flags); |
336 | ||
337 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); | |
338 | P54P_READ(dev_int); | |
eff1a59c MW |
339 | } |
340 | ||
eff1a59c MW |
341 | static void p54p_stop(struct ieee80211_hw *dev) |
342 | { | |
343 | struct p54p_priv *priv = dev->priv; | |
eb76bf29 | 344 | struct p54p_ring_control *ring_control = priv->ring_control; |
eff1a59c MW |
345 | unsigned int i; |
346 | struct p54p_desc *desc; | |
347 | ||
7262d593 CL |
348 | tasklet_kill(&priv->rx_tasklet); |
349 | ||
8160c031 | 350 | P54P_WRITE(int_enable, cpu_to_le32(0)); |
eff1a59c MW |
351 | P54P_READ(int_enable); |
352 | udelay(10); | |
353 | ||
354 | free_irq(priv->pdev->irq, dev); | |
355 | ||
356 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET)); | |
357 | ||
7262d593 | 358 | for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) { |
eb76bf29 | 359 | desc = &ring_control->rx_data[i]; |
eff1a59c | 360 | if (desc->host_addr) |
7262d593 CL |
361 | pci_unmap_single(priv->pdev, |
362 | le32_to_cpu(desc->host_addr), | |
4e416a6f CL |
363 | priv->common.rx_mtu + 32, |
364 | PCI_DMA_FROMDEVICE); | |
7262d593 CL |
365 | kfree_skb(priv->rx_buf_data[i]); |
366 | priv->rx_buf_data[i] = NULL; | |
eff1a59c MW |
367 | } |
368 | ||
7262d593 CL |
369 | for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) { |
370 | desc = &ring_control->rx_mgmt[i]; | |
371 | if (desc->host_addr) | |
372 | pci_unmap_single(priv->pdev, | |
373 | le32_to_cpu(desc->host_addr), | |
4e416a6f CL |
374 | priv->common.rx_mtu + 32, |
375 | PCI_DMA_FROMDEVICE); | |
7262d593 CL |
376 | kfree_skb(priv->rx_buf_mgmt[i]); |
377 | priv->rx_buf_mgmt[i] = NULL; | |
378 | } | |
379 | ||
380 | for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) { | |
eb76bf29 | 381 | desc = &ring_control->tx_data[i]; |
eff1a59c | 382 | if (desc->host_addr) |
7262d593 CL |
383 | pci_unmap_single(priv->pdev, |
384 | le32_to_cpu(desc->host_addr), | |
385 | le16_to_cpu(desc->len), | |
386 | PCI_DMA_TODEVICE); | |
387 | ||
b92f30d6 | 388 | p54_free_skb(dev, priv->tx_buf_data[i]); |
7262d593 CL |
389 | priv->tx_buf_data[i] = NULL; |
390 | } | |
391 | ||
392 | for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) { | |
393 | desc = &ring_control->tx_mgmt[i]; | |
394 | if (desc->host_addr) | |
395 | pci_unmap_single(priv->pdev, | |
396 | le32_to_cpu(desc->host_addr), | |
397 | le16_to_cpu(desc->len), | |
398 | PCI_DMA_TODEVICE); | |
eff1a59c | 399 | |
b92f30d6 | 400 | p54_free_skb(dev, priv->tx_buf_mgmt[i]); |
7262d593 | 401 | priv->tx_buf_mgmt[i] = NULL; |
eff1a59c MW |
402 | } |
403 | ||
7262d593 | 404 | memset(ring_control, 0, sizeof(*ring_control)); |
eff1a59c MW |
405 | } |
406 | ||
35961627 CL |
407 | static int p54p_open(struct ieee80211_hw *dev) |
408 | { | |
409 | struct p54p_priv *priv = dev->priv; | |
410 | int err; | |
411 | ||
412 | init_completion(&priv->boot_comp); | |
413 | err = request_irq(priv->pdev->irq, &p54p_interrupt, | |
414 | IRQF_SHARED, "p54pci", dev); | |
415 | if (err) { | |
ad5e72ee | 416 | dev_err(&priv->pdev->dev, "failed to register IRQ handler\n"); |
35961627 CL |
417 | return err; |
418 | } | |
419 | ||
420 | memset(priv->ring_control, 0, sizeof(*priv->ring_control)); | |
421 | err = p54p_upload_firmware(dev); | |
422 | if (err) { | |
423 | free_irq(priv->pdev->irq, dev); | |
424 | return err; | |
425 | } | |
426 | priv->rx_idx_data = priv->tx_idx_data = 0; | |
427 | priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0; | |
428 | ||
429 | p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data, | |
430 | ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data); | |
431 | ||
432 | p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt, | |
433 | ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt); | |
434 | ||
435 | P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma)); | |
436 | P54P_READ(ring_control_base); | |
437 | wmb(); | |
438 | udelay(10); | |
439 | ||
440 | P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT)); | |
441 | P54P_READ(int_enable); | |
442 | wmb(); | |
443 | udelay(10); | |
444 | ||
445 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET)); | |
446 | P54P_READ(dev_int); | |
447 | ||
448 | if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) { | |
449 | printk(KERN_ERR "%s: Cannot boot firmware!\n", | |
450 | wiphy_name(dev->wiphy)); | |
451 | p54p_stop(dev); | |
452 | return -ETIMEDOUT; | |
453 | } | |
454 | ||
455 | P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE)); | |
456 | P54P_READ(int_enable); | |
457 | wmb(); | |
458 | udelay(10); | |
459 | ||
460 | P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE)); | |
461 | P54P_READ(dev_int); | |
462 | wmb(); | |
463 | udelay(10); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
eff1a59c MW |
468 | static int __devinit p54p_probe(struct pci_dev *pdev, |
469 | const struct pci_device_id *id) | |
470 | { | |
471 | struct p54p_priv *priv; | |
472 | struct ieee80211_hw *dev; | |
473 | unsigned long mem_addr, mem_len; | |
474 | int err; | |
eff1a59c MW |
475 | |
476 | err = pci_enable_device(pdev); | |
477 | if (err) { | |
ad5e72ee | 478 | dev_err(&pdev->dev, "Cannot enable new PCI device\n"); |
eff1a59c MW |
479 | return err; |
480 | } | |
481 | ||
482 | mem_addr = pci_resource_start(pdev, 0); | |
483 | mem_len = pci_resource_len(pdev, 0); | |
484 | if (mem_len < sizeof(struct p54p_csr)) { | |
ad5e72ee | 485 | dev_err(&pdev->dev, "Too short PCI resources\n"); |
40db0b22 | 486 | goto err_disable_dev; |
eff1a59c MW |
487 | } |
488 | ||
32ddf071 | 489 | err = pci_request_regions(pdev, "p54pci"); |
eff1a59c | 490 | if (err) { |
ad5e72ee | 491 | dev_err(&pdev->dev, "Cannot obtain PCI resources\n"); |
40db0b22 | 492 | goto err_disable_dev; |
eff1a59c MW |
493 | } |
494 | ||
e930438c YH |
495 | if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) || |
496 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
ad5e72ee | 497 | dev_err(&pdev->dev, "No suitable DMA available\n"); |
eff1a59c MW |
498 | goto err_free_reg; |
499 | } | |
500 | ||
501 | pci_set_master(pdev); | |
502 | pci_try_set_mwi(pdev); | |
503 | ||
504 | pci_write_config_byte(pdev, 0x40, 0); | |
505 | pci_write_config_byte(pdev, 0x41, 0); | |
506 | ||
507 | dev = p54_init_common(sizeof(*priv)); | |
508 | if (!dev) { | |
ad5e72ee | 509 | dev_err(&pdev->dev, "ieee80211 alloc failed\n"); |
eff1a59c MW |
510 | err = -ENOMEM; |
511 | goto err_free_reg; | |
512 | } | |
513 | ||
514 | priv = dev->priv; | |
515 | priv->pdev = pdev; | |
516 | ||
517 | SET_IEEE80211_DEV(dev, &pdev->dev); | |
518 | pci_set_drvdata(pdev, dev); | |
519 | ||
520 | priv->map = ioremap(mem_addr, mem_len); | |
521 | if (!priv->map) { | |
ad5e72ee CL |
522 | dev_err(&pdev->dev, "Cannot map device memory\n"); |
523 | err = -ENOMEM; | |
eff1a59c MW |
524 | goto err_free_dev; |
525 | } | |
526 | ||
527 | priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control), | |
528 | &priv->ring_control_dma); | |
529 | if (!priv->ring_control) { | |
ad5e72ee | 530 | dev_err(&pdev->dev, "Cannot allocate rings\n"); |
eff1a59c MW |
531 | err = -ENOMEM; |
532 | goto err_iounmap; | |
533 | } | |
eff1a59c MW |
534 | priv->common.open = p54p_open; |
535 | priv->common.stop = p54p_stop; | |
536 | priv->common.tx = p54p_tx; | |
537 | ||
538 | spin_lock_init(&priv->lock); | |
7262d593 | 539 | tasklet_init(&priv->rx_tasklet, p54p_rx_tasklet, (unsigned long)dev); |
eff1a59c | 540 | |
40db0b22 CL |
541 | err = request_firmware(&priv->firmware, "isl3886pci", |
542 | &priv->pdev->dev); | |
543 | if (err) { | |
ad5e72ee | 544 | dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n"); |
40db0b22 CL |
545 | err = request_firmware(&priv->firmware, "isl3886", |
546 | &priv->pdev->dev); | |
547 | if (err) | |
548 | goto err_free_common; | |
549 | } | |
550 | ||
35961627 CL |
551 | err = p54p_open(dev); |
552 | if (err) | |
553 | goto err_free_common; | |
7cb77072 CL |
554 | err = p54_read_eeprom(dev); |
555 | p54p_stop(dev); | |
556 | if (err) | |
35961627 | 557 | goto err_free_common; |
7cb77072 | 558 | |
2ac71072 CL |
559 | err = p54_register_common(dev, &pdev->dev); |
560 | if (err) | |
eff1a59c | 561 | goto err_free_common; |
eff1a59c | 562 | |
eff1a59c MW |
563 | return 0; |
564 | ||
565 | err_free_common: | |
40db0b22 | 566 | release_firmware(priv->firmware); |
eff1a59c | 567 | p54_free_common(dev); |
eff1a59c MW |
568 | pci_free_consistent(pdev, sizeof(*priv->ring_control), |
569 | priv->ring_control, priv->ring_control_dma); | |
570 | ||
571 | err_iounmap: | |
572 | iounmap(priv->map); | |
573 | ||
574 | err_free_dev: | |
575 | pci_set_drvdata(pdev, NULL); | |
576 | ieee80211_free_hw(dev); | |
577 | ||
578 | err_free_reg: | |
579 | pci_release_regions(pdev); | |
40db0b22 | 580 | err_disable_dev: |
eff1a59c MW |
581 | pci_disable_device(pdev); |
582 | return err; | |
583 | } | |
584 | ||
585 | static void __devexit p54p_remove(struct pci_dev *pdev) | |
586 | { | |
587 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
588 | struct p54p_priv *priv; | |
589 | ||
590 | if (!dev) | |
591 | return; | |
592 | ||
593 | ieee80211_unregister_hw(dev); | |
594 | priv = dev->priv; | |
40db0b22 | 595 | release_firmware(priv->firmware); |
eff1a59c MW |
596 | pci_free_consistent(pdev, sizeof(*priv->ring_control), |
597 | priv->ring_control, priv->ring_control_dma); | |
598 | p54_free_common(dev); | |
599 | iounmap(priv->map); | |
600 | pci_release_regions(pdev); | |
601 | pci_disable_device(pdev); | |
602 | ieee80211_free_hw(dev); | |
603 | } | |
604 | ||
605 | #ifdef CONFIG_PM | |
606 | static int p54p_suspend(struct pci_dev *pdev, pm_message_t state) | |
607 | { | |
608 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
609 | struct p54p_priv *priv = dev->priv; | |
610 | ||
05c914fe | 611 | if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) { |
eff1a59c MW |
612 | ieee80211_stop_queues(dev); |
613 | p54p_stop(dev); | |
614 | } | |
615 | ||
616 | pci_save_state(pdev); | |
617 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
618 | return 0; | |
619 | } | |
620 | ||
621 | static int p54p_resume(struct pci_dev *pdev) | |
622 | { | |
623 | struct ieee80211_hw *dev = pci_get_drvdata(pdev); | |
624 | struct p54p_priv *priv = dev->priv; | |
625 | ||
626 | pci_set_power_state(pdev, PCI_D0); | |
627 | pci_restore_state(pdev); | |
628 | ||
05c914fe | 629 | if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) { |
eff1a59c | 630 | p54p_open(dev); |
36d6825b | 631 | ieee80211_wake_queues(dev); |
eff1a59c MW |
632 | } |
633 | ||
634 | return 0; | |
635 | } | |
636 | #endif /* CONFIG_PM */ | |
637 | ||
638 | static struct pci_driver p54p_driver = { | |
32ddf071 | 639 | .name = "p54pci", |
eff1a59c MW |
640 | .id_table = p54p_table, |
641 | .probe = p54p_probe, | |
642 | .remove = __devexit_p(p54p_remove), | |
643 | #ifdef CONFIG_PM | |
644 | .suspend = p54p_suspend, | |
645 | .resume = p54p_resume, | |
646 | #endif /* CONFIG_PM */ | |
647 | }; | |
648 | ||
649 | static int __init p54p_init(void) | |
650 | { | |
651 | return pci_register_driver(&p54p_driver); | |
652 | } | |
653 | ||
654 | static void __exit p54p_exit(void) | |
655 | { | |
656 | pci_unregister_driver(&p54p_driver); | |
657 | } | |
658 | ||
659 | module_init(p54p_init); | |
660 | module_exit(p54p_exit); |