[deliverable/linux.git] / drivers / net / wireless / p54 / p54spi.c

/*
 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
 * Copyright 2008       Johannes Berg <johannes@sipsolutions.net>
 *
 * This driver is a port from stlc45xx:
 *	Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 */

#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/firmware.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/spi/spi.h>
#include <linux/etherdevice.h>
#include <linux/gpio.h>
#include <linux/slab.h>

#include "p54spi.h"
#include "p54.h"

#include "lmac.h"

#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
#include "p54spi_eeprom.h"
#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */

MODULE_FIRMWARE("3826.arm");

/* gpios should be handled in board files and provided via platform data,
 * but because it's currently impossible for p54spi to have a header file
 * in include/linux, let's use module paramaters for now
 */

static int p54spi_gpio_power = 97;
module_param(p54spi_gpio_power, int, 0444);
MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");

static int p54spi_gpio_irq = 87;
module_param(p54spi_gpio_irq, int, 0444);
MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");

static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
			      void *buf, size_t len)
{
	struct spi_transfer t[2];
	struct spi_message m;
	__le16 addr;

	/* We first push the address */
	addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = &addr;
	t[0].len = sizeof(addr);
	spi_message_add_tail(&t[0], &m);

	t[1].rx_buf = buf;
	t[1].len = len;
	spi_message_add_tail(&t[1], &m);

	spi_sync(priv->spi, &m);
}


static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
			     const void *buf, size_t len)
{
	struct spi_transfer t[3];
	struct spi_message m;
	__le16 addr;

	/* We first push the address */
	addr = cpu_to_le16(address << 8);

	spi_message_init(&m);
	memset(t, 0, sizeof(t));

	t[0].tx_buf = &addr;
	t[0].len = sizeof(addr);
	spi_message_add_tail(&t[0], &m);

	t[1].tx_buf = buf;
	t[1].len = len & ~1;
	spi_message_add_tail(&t[1], &m);

	if (len % 2) {
		__le16 last_word;
		last_word = cpu_to_le16(((u8 *)buf)[len - 1]);

		t[2].tx_buf = &last_word;
		t[2].len = sizeof(last_word);
		spi_message_add_tail(&t[2], &m);
	}

	spi_sync(priv->spi, &m);
}

static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
{
	__le32 val;

	p54spi_spi_read(priv, addr, &val, sizeof(val));

	return le32_to_cpu(val);
}

static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
{
	p54spi_spi_write(priv, addr, &val, sizeof(val));
}

static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
{
	p54spi_spi_write(priv, addr, &val, sizeof(val));
}

static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
{
	int i;

	for (i = 0; i < 2000; i++) {
		u32 buffer = p54spi_read32(priv, reg);
		if ((buffer & bits) == bits)
			return 1;
	}
	return 0;
}

static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
				const void *buf, size_t len)
{
	if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
		dev_err(&priv->spi->dev, "spi_write_dma not allowed "
			"to DMA write.\n");
		return -EAGAIN;
	}

	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
		       cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));

	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
	p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
	p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
	return 0;
}

static int p54spi_request_firmware(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	int ret;

	/* FIXME: should driver use it's own struct device? */
	ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);

	if (ret < 0) {
		dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
		return ret;
	}

	ret = p54_parse_firmware(dev, priv->firmware);
	if (ret) {
		release_firmware(priv->firmware);
		return ret;
	}

	return 0;
}

static int p54spi_request_eeprom(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	const struct firmware *eeprom;
	int ret;

	/* allow users to customize their eeprom.
	 */

	ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
	if (ret < 0) {
#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
		dev_info(&priv->spi->dev, "loading default eeprom...\n");
		ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
				       sizeof(p54spi_eeprom));
#else
		dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
	} else {
		dev_info(&priv->spi->dev, "loading user eeprom...\n");
		ret = p54_parse_eeprom(dev, (void *) eeprom->data,
				       (int)eeprom->size);
		release_firmware(eeprom);
	}
	return ret;
}

static int p54spi_upload_firmware(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long fw_len, _fw_len;
	unsigned int offset = 0;
	int err = 0;
	u8 *fw;

	fw_len = priv->firmware->size;
	fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
	if (!fw)
		return -ENOMEM;

	/* stop the device */
	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
		       SPI_CTRL_STAT_START_HALTED));

	msleep(TARGET_BOOT_SLEEP);

	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE |
		       SPI_CTRL_STAT_START_HALTED));

	msleep(TARGET_BOOT_SLEEP);

	while (fw_len > 0) {
		_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);

		err = p54spi_spi_write_dma(priv, cpu_to_le32(
					   ISL38XX_DEV_FIRMWARE_ADDR + offset),
					   (fw + offset), _fw_len);
		if (err < 0)
			goto out;

		fw_len -= _fw_len;
		offset += _fw_len;
	}

	BUG_ON(fw_len != 0);

	/* enable host interrupts */
	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
		       cpu_to_le32(SPI_HOST_INTS_DEFAULT));

	/* boot the device */
	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
		       SPI_CTRL_STAT_RAM_BOOT));

	msleep(TARGET_BOOT_SLEEP);

	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
		       SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
	msleep(TARGET_BOOT_SLEEP);

out:
	kfree(fw);
	return err;
}

static void p54spi_power_off(struct p54s_priv *priv)
{
	disable_irq(gpio_to_irq(p54spi_gpio_irq));
	gpio_set_value(p54spi_gpio_power, 0);
}

static void p54spi_power_on(struct p54s_priv *priv)
{
	gpio_set_value(p54spi_gpio_power, 1);
	enable_irq(gpio_to_irq(p54spi_gpio_irq));

	/* need to wait a while before device can be accessed, the length
	 * is just a guess
	 */
	msleep(10);
}

static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
{
	p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
}

static int p54spi_wakeup(struct p54s_priv *priv)
{
	/* wake the chip */
	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
		       cpu_to_le32(SPI_TARGET_INT_WAKEUP));

	/* And wait for the READY interrupt */
	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
			     SPI_HOST_INT_READY)) {
		dev_err(&priv->spi->dev, "INT_READY timeout\n");
		return -EBUSY;
	}

	p54spi_int_ack(priv, SPI_HOST_INT_READY);
	return 0;
}

static inline void p54spi_sleep(struct p54s_priv *priv)
{
	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
		       cpu_to_le32(SPI_TARGET_INT_SLEEP));
}

static void p54spi_int_ready(struct p54s_priv *priv)
{
	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
		       SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));

	switch (priv->fw_state) {
	case FW_STATE_BOOTING:
		priv->fw_state = FW_STATE_READY;
		complete(&priv->fw_comp);
		break;
	case FW_STATE_RESETTING:
		priv->fw_state = FW_STATE_READY;
		/* TODO: reinitialize state */
		break;
	default:
		break;
	}
}

static int p54spi_rx(struct p54s_priv *priv)
{
	struct sk_buff *skb;
	u16 len;
	u16 rx_head[2];
#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))

	if (p54spi_wakeup(priv) < 0)
		return -EBUSY;

	/* Read data size and first data word in one SPI transaction
	 * This is workaround for firmware/DMA bug,
	 * when first data word gets lost under high load.
	 */
	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
	len = rx_head[0];

	if (len == 0) {
		p54spi_sleep(priv);
		dev_err(&priv->spi->dev, "rx request of zero bytes\n");
		return 0;
	}

	/* Firmware may insert up to 4 padding bytes after the lmac header,
	 * but it does not amend the size of SPI data transfer.
	 * Such packets has correct data size in header, thus referencing
	 * past the end of allocated skb. Reserve extra 4 bytes for this case
	 */
	skb = dev_alloc_skb(len + 4);
	if (!skb) {
		p54spi_sleep(priv);
		dev_err(&priv->spi->dev, "could not alloc skb");
		return -ENOMEM;
	}

	if (len <= READAHEAD_SZ) {
		memcpy(skb_put(skb, len), rx_head + 1, len);
	} else {
		memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
		p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
				skb_put(skb, len - READAHEAD_SZ),
				len - READAHEAD_SZ);
	}
	p54spi_sleep(priv);
	/* Put additional bytes to compensate for the possible
	 * alignment-caused truncation
	 */
	skb_put(skb, 4);

	if (p54_rx(priv->hw, skb) == 0)
		dev_kfree_skb(skb);

	return 0;
}


static irqreturn_t p54spi_interrupt(int irq, void *config)
{
	struct spi_device *spi = config;
	struct p54s_priv *priv = spi_get_drvdata(spi);

	ieee80211_queue_work(priv->hw, &priv->work);

	return IRQ_HANDLED;
}

static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
{
	struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
	int ret = 0;

	if (p54spi_wakeup(priv) < 0)
		return -EBUSY;

	ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
	if (ret < 0)
		goto out;

	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
			     SPI_HOST_INT_WR_READY)) {
		dev_err(&priv->spi->dev, "WR_READY timeout\n");
		ret = -EAGAIN;
		goto out;
	}

	p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);

	if (FREE_AFTER_TX(skb))
		p54_free_skb(priv->hw, skb);
out:
	p54spi_sleep(priv);
	return ret;
}

static int p54spi_wq_tx(struct p54s_priv *priv)
{
	struct p54s_tx_info *entry;
	struct sk_buff *skb;
	struct ieee80211_tx_info *info;
	struct p54_tx_info *minfo;
	struct p54s_tx_info *dinfo;
	unsigned long flags;
	int ret = 0;

	spin_lock_irqsave(&priv->tx_lock, flags);

	while (!list_empty(&priv->tx_pending)) {
		entry = list_entry(priv->tx_pending.next,
				   struct p54s_tx_info, tx_list);

		list_del_init(&entry->tx_list);

		spin_unlock_irqrestore(&priv->tx_lock, flags);

		dinfo = container_of((void *) entry, struct p54s_tx_info,
				     tx_list);
		minfo = container_of((void *) dinfo, struct p54_tx_info,
				     data);
		info = container_of((void *) minfo, struct ieee80211_tx_info,
				    rate_driver_data);
		skb = container_of((void *) info, struct sk_buff, cb);

		ret = p54spi_tx_frame(priv, skb);

		if (ret < 0) {
			p54_free_skb(priv->hw, skb);
			return ret;
		}

		spin_lock_irqsave(&priv->tx_lock, flags);
	}
	spin_unlock_irqrestore(&priv->tx_lock, flags);
	return ret;
}

static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
{
	struct p54s_priv *priv = dev->priv;
	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
	struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
	struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
	unsigned long flags;

	BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));

	spin_lock_irqsave(&priv->tx_lock, flags);
	list_add_tail(&di->tx_list, &priv->tx_pending);
	spin_unlock_irqrestore(&priv->tx_lock, flags);

	ieee80211_queue_work(priv->hw, &priv->work);
}

static void p54spi_work(struct work_struct *work)
{
	struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
	u32 ints;
	int ret;

	mutex_lock(&priv->mutex);

	if (priv->fw_state == FW_STATE_OFF)
		goto out;

	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);

	if (ints & SPI_HOST_INT_READY) {
		p54spi_int_ready(priv);
		p54spi_int_ack(priv, SPI_HOST_INT_READY);
	}

	if (priv->fw_state != FW_STATE_READY)
		goto out;

	if (ints & SPI_HOST_INT_UPDATE) {
		p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
		ret = p54spi_rx(priv);
		if (ret < 0)
			goto out;
	}
	if (ints & SPI_HOST_INT_SW_UPDATE) {
		p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
		ret = p54spi_rx(priv);
		if (ret < 0)
			goto out;
	}

	ret = p54spi_wq_tx(priv);
out:
	mutex_unlock(&priv->mutex);
}

static int p54spi_op_start(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long timeout;
	int ret = 0;

	if (mutex_lock_interruptible(&priv->mutex)) {
		ret = -EINTR;
		goto out;
	}

	priv->fw_state = FW_STATE_BOOTING;

	p54spi_power_on(priv);

	ret = p54spi_upload_firmware(dev);
	if (ret < 0) {
		p54spi_power_off(priv);
		goto out_unlock;
	}

	mutex_unlock(&priv->mutex);

	timeout = msecs_to_jiffies(2000);
	timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
							    timeout);
	if (!timeout) {
		dev_err(&priv->spi->dev, "firmware boot failed");
		p54spi_power_off(priv);
		ret = -1;
		goto out;
	}

	if (mutex_lock_interruptible(&priv->mutex)) {
		ret = -EINTR;
		p54spi_power_off(priv);
		goto out;
	}

	WARN_ON(priv->fw_state != FW_STATE_READY);

out_unlock:
	mutex_unlock(&priv->mutex);

out:
	return ret;
}

static void p54spi_op_stop(struct ieee80211_hw *dev)
{
	struct p54s_priv *priv = dev->priv;
	unsigned long flags;

	mutex_lock(&priv->mutex);
	WARN_ON(priv->fw_state != FW_STATE_READY);

	p54spi_power_off(priv);
	spin_lock_irqsave(&priv->tx_lock, flags);
	INIT_LIST_HEAD(&priv->tx_pending);
	spin_unlock_irqrestore(&priv->tx_lock, flags);

	priv->fw_state = FW_STATE_OFF;
	mutex_unlock(&priv->mutex);

	cancel_work_sync(&priv->work);
}

static int p54spi_probe(struct spi_device *spi)
{
	struct p54s_priv *priv = NULL;
	struct ieee80211_hw *hw;
	int ret = -EINVAL;

	hw = p54_init_common(sizeof(*priv));
	if (!hw) {
		dev_err(&spi->dev, "could not alloc ieee80211_hw");
		return -ENOMEM;
	}

	priv = hw->priv;
	priv->hw = hw;
	spi_set_drvdata(spi, priv);
	priv->spi = spi;

	spi->bits_per_word = 16;
	spi->max_speed_hz = 24000000;

	ret = spi_setup(spi);
	if (ret < 0) {
		dev_err(&priv->spi->dev, "spi_setup failed");
		goto err_free;
	}

	ret = gpio_request(p54spi_gpio_power, "p54spi power");
	if (ret < 0) {
		dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
		goto err_free;
	}

	ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
	if (ret < 0) {
		dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
		goto err_free_gpio_power;
	}

	gpio_direction_output(p54spi_gpio_power, 0);
	gpio_direction_input(p54spi_gpio_irq);

	ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
			  p54spi_interrupt, IRQF_DISABLED, "p54spi",
			  priv->spi);
	if (ret < 0) {
		dev_err(&priv->spi->dev, "request_irq() failed");
		goto err_free_gpio_irq;
	}

	irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);

	disable_irq(gpio_to_irq(p54spi_gpio_irq));

	INIT_WORK(&priv->work, p54spi_work);
	init_completion(&priv->fw_comp);
	INIT_LIST_HEAD(&priv->tx_pending);
	mutex_init(&priv->mutex);
	spin_lock_init(&priv->tx_lock);
	SET_IEEE80211_DEV(hw, &spi->dev);
	priv->common.open = p54spi_op_start;
	priv->common.stop = p54spi_op_stop;
	priv->common.tx = p54spi_op_tx;

	ret = p54spi_request_firmware(hw);
	if (ret < 0)
		goto err_free_common;

	ret = p54spi_request_eeprom(hw);
	if (ret)
		goto err_free_common;

	ret = p54_register_common(hw, &priv->spi->dev);
	if (ret)
		goto err_free_common;

	return 0;

err_free_common:
	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
err_free_gpio_irq:
	gpio_free(p54spi_gpio_irq);
err_free_gpio_power:
	gpio_free(p54spi_gpio_power);
err_free:
	p54_free_common(priv->hw);
	return ret;
}

static int p54spi_remove(struct spi_device *spi)
{
	struct p54s_priv *priv = spi_get_drvdata(spi);

	p54_unregister_common(priv->hw);

	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);

	gpio_free(p54spi_gpio_power);
	gpio_free(p54spi_gpio_irq);
	release_firmware(priv->firmware);

	mutex_destroy(&priv->mutex);

	p54_free_common(priv->hw);

	return 0;
}


static struct spi_driver p54spi_driver = {
	.driver = {
		.name		= "p54spi",
		.owner		= THIS_MODULE,
	},

	.probe		= p54spi_probe,
	.remove		= p54spi_remove,
};

module_spi_driver(p54spi_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
MODULE_ALIAS("spi:cx3110x");
MODULE_ALIAS("spi:p54spi");
MODULE_ALIAS("spi:stlc45xx");
Commit	Line	Data
cd8d3d32 CL	1	/*
	2	* Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
	3	* Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
	4	*
	5	* This driver is a port from stlc45xx:
	6	* Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License
	10	* version 2 as published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but
	13	* WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	20	* 02110-1301 USA
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/interrupt.h>
	26	#include <linux/firmware.h>
	27	#include <linux/delay.h>
	28	#include <linux/irq.h>
	29	#include <linux/spi/spi.h>
	30	#include <linux/etherdevice.h>
	31	#include <linux/gpio.h>
5a0e3ad6	32	#include <linux/slab.h>
cd8d3d32 CL	33
cd8d3d32 CL	34	#include "p54spi.h"
cd8d3d32 CL	35	#include "p54.h"
cd8d3d32 CL	36
d8c92107	37	#include "lmac.h"
cd8d3d32	38
d7065c30 CL	39	#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
	40	#include "p54spi_eeprom.h"
	41	#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
	42
cd8d3d32	43	MODULE_FIRMWARE("3826.arm");
cd8d3d32	44
acba7bb3	45	/* gpios should be handled in board files and provided via platform data,
a2116993 CL	46	* but because it's currently impossible for p54spi to have a header file
	47	* in include/linux, let's use module paramaters for now
	48	*/
	49
	50	static int p54spi_gpio_power = 97;
	51	module_param(p54spi_gpio_power, int, 0444);
	52	MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
	53
	54	static int p54spi_gpio_irq = 87;
	55	module_param(p54spi_gpio_irq, int, 0444);
	56	MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
	57
cd8d3d32 CL	58	static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
	59	void *buf, size_t len)
	60	{
	61	struct spi_transfer t[2];
	62	struct spi_message m;
	63	__le16 addr;
	64
	65	/* We first push the address */
	66	addr = cpu_to_le16(address << 8 \| SPI_ADRS_READ_BIT_15);
	67
	68	spi_message_init(&m);
	69	memset(t, 0, sizeof(t));
	70
	71	t[0].tx_buf = &addr;
	72	t[0].len = sizeof(addr);
	73	spi_message_add_tail(&t[0], &m);
	74
	75	t[1].rx_buf = buf;
	76	t[1].len = len;
	77	spi_message_add_tail(&t[1], &m);
	78
	79	spi_sync(priv->spi, &m);
	80	}
	81
	82
	83	static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
	84	const void *buf, size_t len)
	85	{
	86	struct spi_transfer t[3];
	87	struct spi_message m;
	88	__le16 addr;
	89
	90	/* We first push the address */
	91	addr = cpu_to_le16(address << 8);
	92
	93	spi_message_init(&m);
	94	memset(t, 0, sizeof(t));
	95
	96	t[0].tx_buf = &addr;
	97	t[0].len = sizeof(addr);
	98	spi_message_add_tail(&t[0], &m);
	99
	100	t[1].tx_buf = buf;
69712e92	101	t[1].len = len & ~1;
cd8d3d32 CL	102	spi_message_add_tail(&t[1], &m);
	103
	104	if (len % 2) {
	105	__le16 last_word;
	106	last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
	107
	108	t[2].tx_buf = &last_word;
	109	t[2].len = sizeof(last_word);
	110	spi_message_add_tail(&t[2], &m);
	111	}
	112
	113	spi_sync(priv->spi, &m);
	114	}
	115
cd8d3d32 CL	116	static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
	117	{
	118	__le32 val;
	119
	120	p54spi_spi_read(priv, addr, &val, sizeof(val));
	121
	122	return le32_to_cpu(val);
	123	}
	124
	125	static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
	126	{
	127	p54spi_spi_write(priv, addr, &val, sizeof(val));
	128	}
	129
	130	static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
	131	{
	132	p54spi_spi_write(priv, addr, &val, sizeof(val));
	133	}
	134
a7eee06b	135	static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
cd8d3d32 CL	136	{
cd8d3d32 CL	137	int i;
cd8d3d32 CL	138
cd8d3d32 CL	139	for (i = 0; i < 2000; i++) {
a7eee06b	140	u32 buffer = p54spi_read32(priv, reg);
f74d0f5c	141	if ((buffer & bits) == bits)
cd8d3d32	142	return 1;
cd8d3d32 CL	143	}
	144	return 0;
	145	}
	146
4f5cab96 MF	147	static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
	148	const void *buf, size_t len)
	149	{
a7eee06b	150	if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
4f5cab96	151	dev_err(&priv->spi->dev, "spi_write_dma not allowed "
87cbfd06	152	"to DMA write.\n");
4f5cab96 MF	153	return -EAGAIN;
	154	}
	155
210dd1bb MF	156	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
	157	cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
	158
4f5cab96 MF	159	p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
	160	p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
	161	p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
	162	return 0;
	163	}
	164
cd8d3d32 CL	165	static int p54spi_request_firmware(struct ieee80211_hw *dev)
	166	{
	167	struct p54s_priv *priv = dev->priv;
	168	int ret;
	169
	170	/* FIXME: should driver use it's own struct device? */
	171	ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
	172
	173	if (ret < 0) {
	174	dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
	175	return ret;
	176	}
	177
	178	ret = p54_parse_firmware(dev, priv->firmware);
	179	if (ret) {
	180	release_firmware(priv->firmware);
	181	return ret;
	182	}
	183
	184	return 0;
	185	}
	186
	187	static int p54spi_request_eeprom(struct ieee80211_hw *dev)
	188	{
	189	struct p54s_priv *priv = dev->priv;
	190	const struct firmware *eeprom;
	191	int ret;
	192
acba7bb3	193	/* allow users to customize their eeprom.
cd8d3d32 CL	194	*/
	195
	196	ret = request_firmware(&eeprom, "3826.eeprom", &priv->spi->dev);
	197	if (ret < 0) {
d7065c30	198	#ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
cd8d3d32 CL	199	dev_info(&priv->spi->dev, "loading default eeprom...\n");
	200	ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
	201	sizeof(p54spi_eeprom));
f4bbf922 MB	202	#else
f4bbf922 MB	203	dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
d7065c30	204	#endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
cd8d3d32 CL	205	} else {
	206	dev_info(&priv->spi->dev, "loading user eeprom...\n");
	207	ret = p54_parse_eeprom(dev, (void *) eeprom->data,
	208	(int)eeprom->size);
	209	release_firmware(eeprom);
	210	}
	211	return ret;
	212	}
	213
	214	static int p54spi_upload_firmware(struct ieee80211_hw *dev)
	215	{
	216	struct p54s_priv *priv = dev->priv;
5e3af1d2 MF	217	unsigned long fw_len, _fw_len;
	218	unsigned int offset = 0;
	219	int err = 0;
	220	u8 *fw;
	221
	222	fw_len = priv->firmware->size;
	223	fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
	224	if (!fw)
	225	return -ENOMEM;
cd8d3d32 CL	226
	227	/* stop the device */
	228	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	229	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_HOST_RESET \|
	230	SPI_CTRL_STAT_START_HALTED));
	231
	232	msleep(TARGET_BOOT_SLEEP);
	233
	234	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	235	SPI_CTRL_STAT_HOST_OVERRIDE \|
	236	SPI_CTRL_STAT_START_HALTED));
	237
	238	msleep(TARGET_BOOT_SLEEP);
	239
cd8d3d32 CL	240	while (fw_len > 0) {
	241	_fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
	242
4f5cab96 MF	243	err = p54spi_spi_write_dma(priv, cpu_to_le32(
	244	ISL38XX_DEV_FIRMWARE_ADDR + offset),
	245	(fw + offset), _fw_len);
	246	if (err < 0)
5e3af1d2	247	goto out;
cd8d3d32 CL	248
cd8d3d32 CL	249	fw_len -= _fw_len;
5e3af1d2	250	offset += _fw_len;
cd8d3d32 CL	251	}
	252
	253	BUG_ON(fw_len != 0);
	254
	255	/* enable host interrupts */
	256	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
	257	cpu_to_le32(SPI_HOST_INTS_DEFAULT));
	258
	259	/* boot the device */
	260	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	261	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_HOST_RESET \|
	262	SPI_CTRL_STAT_RAM_BOOT));
	263
	264	msleep(TARGET_BOOT_SLEEP);
	265
	266	p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
	267	SPI_CTRL_STAT_HOST_OVERRIDE \| SPI_CTRL_STAT_RAM_BOOT));
	268	msleep(TARGET_BOOT_SLEEP);
5e3af1d2 MF	269
	270	out:
	271	kfree(fw);
	272	return err;
cd8d3d32 CL	273	}
	274
	275	static void p54spi_power_off(struct p54s_priv *priv)
	276	{
a2116993 CL	277	disable_irq(gpio_to_irq(p54spi_gpio_irq));
a2116993 CL	278	gpio_set_value(p54spi_gpio_power, 0);
cd8d3d32 CL	279	}
	280
	281	static void p54spi_power_on(struct p54s_priv *priv)
	282	{
a2116993 CL	283	gpio_set_value(p54spi_gpio_power, 1);
a2116993 CL	284	enable_irq(gpio_to_irq(p54spi_gpio_irq));
cd8d3d32	285
acba7bb3	286	/* need to wait a while before device can be accessed, the length
cd8d3d32 CL	287	* is just a guess
	288	*/
	289	msleep(10);
	290	}
	291
	292	static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
	293	{
	294	p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
	295	}
	296
465b6353	297	static int p54spi_wakeup(struct p54s_priv *priv)
cd8d3d32	298	{
cd8d3d32 CL	299	/* wake the chip */
	300	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
	301	cpu_to_le32(SPI_TARGET_INT_WAKEUP));
	302
	303	/* And wait for the READY interrupt */
87cbfd06	304	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
a7eee06b	305	SPI_HOST_INT_READY)) {
87cbfd06	306	dev_err(&priv->spi->dev, "INT_READY timeout\n");
465b6353	307	return -EBUSY;
cd8d3d32 CL	308	}
	309
	310	p54spi_int_ack(priv, SPI_HOST_INT_READY);
465b6353	311	return 0;
cd8d3d32 CL	312	}
	313
	314	static inline void p54spi_sleep(struct p54s_priv *priv)
	315	{
	316	p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
	317	cpu_to_le32(SPI_TARGET_INT_SLEEP));
	318	}
	319
	320	static void p54spi_int_ready(struct p54s_priv *priv)
	321	{
	322	p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
	323	SPI_HOST_INT_UPDATE \| SPI_HOST_INT_SW_UPDATE));
	324
	325	switch (priv->fw_state) {
	326	case FW_STATE_BOOTING:
	327	priv->fw_state = FW_STATE_READY;
	328	complete(&priv->fw_comp);
	329	break;
	330	case FW_STATE_RESETTING:
	331	priv->fw_state = FW_STATE_READY;
	332	/* TODO: reinitialize state */
	333	break;
	334	default:
	335	break;
	336	}
	337	}
	338
	339	static int p54spi_rx(struct p54s_priv *priv)
	340	{
	341	struct sk_buff *skb;
	342	u16 len;
ff561ac8 MF	343	u16 rx_head[2];
ff561ac8 MF	344	#define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
cd8d3d32	345
465b6353 MF	346	if (p54spi_wakeup(priv) < 0)
465b6353 MF	347	return -EBUSY;
cd8d3d32	348
ff561ac8 MF	349	/* Read data size and first data word in one SPI transaction
	350	* This is workaround for firmware/DMA bug,
	351	* when first data word gets lost under high load.
	352	*/
	353	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
	354	len = rx_head[0];
cd8d3d32 CL	355
cd8d3d32 CL	356	if (len == 0) {
ff561ac8 MF	357	p54spi_sleep(priv);
ff561ac8 MF	358	dev_err(&priv->spi->dev, "rx request of zero bytes\n");
cd8d3d32 CL	359	return 0;
	360	}
	361
9f201a87 MF	362	/* Firmware may insert up to 4 padding bytes after the lmac header,
	363	* but it does not amend the size of SPI data transfer.
	364	* Such packets has correct data size in header, thus referencing
acba7bb3 SK	365	* past the end of allocated skb. Reserve extra 4 bytes for this case
acba7bb3 SK	366	*/
9f201a87	367	skb = dev_alloc_skb(len + 4);
cd8d3d32	368	if (!skb) {
ff561ac8	369	p54spi_sleep(priv);
cd8d3d32	370	dev_err(&priv->spi->dev, "could not alloc skb");
ff561ac8	371	return -ENOMEM;
cd8d3d32 CL	372	}
cd8d3d32 CL	373
ff561ac8 MF	374	if (len <= READAHEAD_SZ) {
	375	memcpy(skb_put(skb, len), rx_head + 1, len);
	376	} else {
	377	memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
	378	p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
	379	skb_put(skb, len - READAHEAD_SZ),
	380	len - READAHEAD_SZ);
	381	}
cd8d3d32	382	p54spi_sleep(priv);
9f201a87	383	/* Put additional bytes to compensate for the possible
acba7bb3 SK	384	* alignment-caused truncation
acba7bb3 SK	385	*/
9f201a87	386	skb_put(skb, 4);
cd8d3d32 CL	387
	388	if (p54_rx(priv->hw, skb) == 0)
	389	dev_kfree_skb(skb);
	390
	391	return 0;
	392	}
	393
	394
	395	static irqreturn_t p54spi_interrupt(int irq, void *config)
	396	{
	397	struct spi_device *spi = config;
d60c5d20	398	struct p54s_priv *priv = spi_get_drvdata(spi);
cd8d3d32	399
42935eca	400	ieee80211_queue_work(priv->hw, &priv->work);
cd8d3d32 CL	401
	402	return IRQ_HANDLED;
	403	}
	404
	405	static int p54spi_tx_frame(struct p54s_priv priv, struct sk_buff skb)
	406	{
	407	struct p54_hdr hdr = (struct p54_hdr ) skb->data;
cd8d3d32	408	int ret = 0;
cd8d3d32	409
465b6353 MF	410	if (p54spi_wakeup(priv) < 0)
465b6353 MF	411	return -EBUSY;
cd8d3d32	412
4f5cab96 MF	413	ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
	414	if (ret < 0)
	415	goto out;
cd8d3d32	416
87cbfd06	417	if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
a7eee06b	418	SPI_HOST_INT_WR_READY)) {
87cbfd06	419	dev_err(&priv->spi->dev, "WR_READY timeout\n");
6edf534a	420	ret = -EAGAIN;
87cbfd06	421	goto out;
cd8d3d32 CL	422	}
	423
	424	p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
cd8d3d32	425
cd8d3d32 CL	426	if (FREE_AFTER_TX(skb))
cd8d3d32 CL	427	p54_free_skb(priv->hw, skb);
4f5cab96	428	out:
6edf534a	429	p54spi_sleep(priv);
cd8d3d32 CL	430	return ret;
	431	}
	432
	433	static int p54spi_wq_tx(struct p54s_priv *priv)
	434	{
	435	struct p54s_tx_info *entry;
	436	struct sk_buff *skb;
	437	struct ieee80211_tx_info *info;
	438	struct p54_tx_info *minfo;
	439	struct p54s_tx_info *dinfo;
731c6531	440	unsigned long flags;
cd8d3d32 CL	441	int ret = 0;
cd8d3d32 CL	442
731c6531	443	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32 CL	444
	445	while (!list_empty(&priv->tx_pending)) {
	446	entry = list_entry(priv->tx_pending.next,
	447	struct p54s_tx_info, tx_list);
	448
	449	list_del_init(&entry->tx_list);
	450
731c6531	451	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	452
	453	dinfo = container_of((void *) entry, struct p54s_tx_info,
	454	tx_list);
	455	minfo = container_of((void *) dinfo, struct p54_tx_info,
	456	data);
	457	info = container_of((void *) minfo, struct ieee80211_tx_info,
	458	rate_driver_data);
	459	skb = container_of((void *) info, struct sk_buff, cb);
	460
	461	ret = p54spi_tx_frame(priv, skb);
	462
cd8d3d32 CL	463	if (ret < 0) {
cd8d3d32 CL	464	p54_free_skb(priv->hw, skb);
731c6531	465	return ret;
cd8d3d32	466	}
cd8d3d32	467
731c6531 CL	468	spin_lock_irqsave(&priv->tx_lock, flags);
	469	}
	470	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	471	return ret;
	472	}
	473
	474	static void p54spi_op_tx(struct ieee80211_hw dev, struct sk_buff skb)
	475	{
	476	struct p54s_priv *priv = dev->priv;
	477	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
	478	struct p54_tx_info mi = (struct p54_tx_info ) info->rate_driver_data;
	479	struct p54s_tx_info di = (struct p54s_tx_info ) mi->data;
731c6531	480	unsigned long flags;
cd8d3d32 CL	481
	482	BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
	483
731c6531	484	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32	485	list_add_tail(&di->tx_list, &priv->tx_pending);
731c6531	486	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32	487
42935eca	488	ieee80211_queue_work(priv->hw, &priv->work);
cd8d3d32 CL	489	}
	490
	491	static void p54spi_work(struct work_struct *work)
	492	{
	493	struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
	494	u32 ints;
	495	int ret;
	496
	497	mutex_lock(&priv->mutex);
	498
4de2dc74	499	if (priv->fw_state == FW_STATE_OFF)
cd8d3d32 CL	500	goto out;
	501
	502	ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
	503
	504	if (ints & SPI_HOST_INT_READY) {
	505	p54spi_int_ready(priv);
	506	p54spi_int_ack(priv, SPI_HOST_INT_READY);
	507	}
	508
	509	if (priv->fw_state != FW_STATE_READY)
	510	goto out;
	511
	512	if (ints & SPI_HOST_INT_UPDATE) {
	513	p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
	514	ret = p54spi_rx(priv);
	515	if (ret < 0)
	516	goto out;
	517	}
	518	if (ints & SPI_HOST_INT_SW_UPDATE) {
	519	p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
	520	ret = p54spi_rx(priv);
	521	if (ret < 0)
	522	goto out;
	523	}
	524
	525	ret = p54spi_wq_tx(priv);
cd8d3d32 CL	526	out:
	527	mutex_unlock(&priv->mutex);
	528	}
	529
	530	static int p54spi_op_start(struct ieee80211_hw *dev)
	531	{
	532	struct p54s_priv *priv = dev->priv;
	533	unsigned long timeout;
	534	int ret = 0;
	535
	536	if (mutex_lock_interruptible(&priv->mutex)) {
	537	ret = -EINTR;
	538	goto out;
	539	}
	540
	541	priv->fw_state = FW_STATE_BOOTING;
	542
	543	p54spi_power_on(priv);
	544
	545	ret = p54spi_upload_firmware(dev);
	546	if (ret < 0) {
	547	p54spi_power_off(priv);
	548	goto out_unlock;
	549	}
	550
	551	mutex_unlock(&priv->mutex);
	552
	553	timeout = msecs_to_jiffies(2000);
	554	timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
	555	timeout);
	556	if (!timeout) {
	557	dev_err(&priv->spi->dev, "firmware boot failed");
	558	p54spi_power_off(priv);
	559	ret = -1;
	560	goto out;
	561	}
	562
	563	if (mutex_lock_interruptible(&priv->mutex)) {
	564	ret = -EINTR;
	565	p54spi_power_off(priv);
	566	goto out;
	567	}
	568
	569	WARN_ON(priv->fw_state != FW_STATE_READY);
	570
	571	out_unlock:
	572	mutex_unlock(&priv->mutex);
	573
	574	out:
	575	return ret;
	576	}
	577
	578	static void p54spi_op_stop(struct ieee80211_hw *dev)
	579	{
	580	struct p54s_priv *priv = dev->priv;
731c6531	581	unsigned long flags;
cd8d3d32	582
7adb92fa	583	mutex_lock(&priv->mutex);
cd8d3d32 CL	584	WARN_ON(priv->fw_state != FW_STATE_READY);
cd8d3d32 CL	585
cd8d3d32	586	p54spi_power_off(priv);
731c6531	587	spin_lock_irqsave(&priv->tx_lock, flags);
cd8d3d32	588	INIT_LIST_HEAD(&priv->tx_pending);
731c6531	589	spin_unlock_irqrestore(&priv->tx_lock, flags);
cd8d3d32 CL	590
	591	priv->fw_state = FW_STATE_OFF;
	592	mutex_unlock(&priv->mutex);
2d161817 MB	593
2d161817 MB	594	cancel_work_sync(&priv->work);
cd8d3d32 CL	595	}
cd8d3d32 CL	596
337b563f	597	static int p54spi_probe(struct spi_device *spi)
cd8d3d32 CL	598	{
	599	struct p54s_priv *priv = NULL;
	600	struct ieee80211_hw *hw;
	601	int ret = -EINVAL;
	602
	603	hw = p54_init_common(sizeof(*priv));
	604	if (!hw) {
bfa99bfd	605	dev_err(&spi->dev, "could not alloc ieee80211_hw");
cd8d3d32 CL	606	return -ENOMEM;
	607	}
	608
	609	priv = hw->priv;
	610	priv->hw = hw;
d60c5d20	611	spi_set_drvdata(spi, priv);
cd8d3d32 CL	612	priv->spi = spi;
cd8d3d32 CL	613
cd8d3d32 CL	614	spi->bits_per_word = 16;
	615	spi->max_speed_hz = 24000000;
	616
	617	ret = spi_setup(spi);
	618	if (ret < 0) {
	619	dev_err(&priv->spi->dev, "spi_setup failed");
62ebeed8	620	goto err_free;
cd8d3d32 CL	621	}
cd8d3d32 CL	622
a2116993	623	ret = gpio_request(p54spi_gpio_power, "p54spi power");
cd8d3d32 CL	624	if (ret < 0) {
cd8d3d32 CL	625	dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
62ebeed8	626	goto err_free;
cd8d3d32 CL	627	}
cd8d3d32 CL	628
a2116993	629	ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
cd8d3d32 CL	630	if (ret < 0) {
cd8d3d32 CL	631	dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
62ebeed8	632	goto err_free_gpio_power;
cd8d3d32 CL	633	}
cd8d3d32 CL	634
a2116993 CL	635	gpio_direction_output(p54spi_gpio_power, 0);
a2116993 CL	636	gpio_direction_input(p54spi_gpio_irq);
cd8d3d32	637
a2116993	638	ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
cd8d3d32 CL	639	p54spi_interrupt, IRQF_DISABLED, "p54spi",
	640	priv->spi);
	641	if (ret < 0) {
	642	dev_err(&priv->spi->dev, "request_irq() failed");
62ebeed8	643	goto err_free_gpio_irq;
cd8d3d32 CL	644	}
cd8d3d32 CL	645
dced35ae	646	irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);
cd8d3d32	647
a2116993	648	disable_irq(gpio_to_irq(p54spi_gpio_irq));
cd8d3d32 CL	649
	650	INIT_WORK(&priv->work, p54spi_work);
	651	init_completion(&priv->fw_comp);
	652	INIT_LIST_HEAD(&priv->tx_pending);
	653	mutex_init(&priv->mutex);
32d3a392	654	spin_lock_init(&priv->tx_lock);
cd8d3d32 CL	655	SET_IEEE80211_DEV(hw, &spi->dev);
	656	priv->common.open = p54spi_op_start;
	657	priv->common.stop = p54spi_op_stop;
	658	priv->common.tx = p54spi_op_tx;
	659
	660	ret = p54spi_request_firmware(hw);
	661	if (ret < 0)
	662	goto err_free_common;
	663
	664	ret = p54spi_request_eeprom(hw);
	665	if (ret)
	666	goto err_free_common;
	667
2ac71072 CL	668	ret = p54_register_common(hw, &priv->spi->dev);
2ac71072 CL	669	if (ret)
cd8d3d32	670	goto err_free_common;
cd8d3d32	671
cd8d3d32 CL	672	return 0;
	673
	674	err_free_common:
62ebeed8 MF	675	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
	676	err_free_gpio_irq:
	677	gpio_free(p54spi_gpio_irq);
	678	err_free_gpio_power:
	679	gpio_free(p54spi_gpio_power);
	680	err_free:
cd8d3d32 CL	681	p54_free_common(priv->hw);
	682	return ret;
	683	}
	684
337b563f	685	static int p54spi_remove(struct spi_device *spi)
cd8d3d32	686	{
d60c5d20	687	struct p54s_priv *priv = spi_get_drvdata(spi);
cd8d3d32	688
d8c92107	689	p54_unregister_common(priv->hw);
cd8d3d32	690
a2116993	691	free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
cd8d3d32	692
a2116993 CL	693	gpio_free(p54spi_gpio_power);
a2116993 CL	694	gpio_free(p54spi_gpio_irq);
cd8d3d32 CL	695	release_firmware(priv->firmware);
	696
	697	mutex_destroy(&priv->mutex);
	698
	699	p54_free_common(priv->hw);
cd8d3d32 CL	700
	701	return 0;
	702	}
	703
	704
	705	static struct spi_driver p54spi_driver = {
	706	.driver = {
5f1e83db	707	.name = "p54spi",
cd8d3d32 CL	708	.owner = THIS_MODULE,
	709	},
	710
	711	.probe = p54spi_probe,
337b563f	712	.remove = p54spi_remove,
cd8d3d32 CL	713	};
cd8d3d32 CL	714
b6c32f88	715	module_spi_driver(p54spi_driver);
cd8d3d32 CL	716
	717	MODULE_LICENSE("GPL");
	718	MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
e0626e38	719	MODULE_ALIAS("spi:cx3110x");
5f1e83db	720	MODULE_ALIAS("spi:p54spi");
1eb85d63	721	MODULE_ALIAS("spi:stlc45xx");