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mac80211: dont use interface indices in drivers
[deliverable/linux.git] / drivers / net / wireless / p54common.c
CommitLineData
eff1a59c
MW		 1
2/*
3 * Common code for mac80211 Prism54 drivers
4 *
5 * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
6 * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
7 *
8 * Based on the islsm (softmac prism54) driver, which is:
9 * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/firmware.h>
18#include <linux/etherdevice.h>
19
20#include <net/mac80211.h>
21
22#include "p54.h"
23#include "p54common.h"
24
25MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
26MODULE_DESCRIPTION("Softmac Prism54 common code");
27MODULE_LICENSE("GPL");
28MODULE_ALIAS("prism54common");
29
30void p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
31{
32 struct p54_common *priv = dev->priv;
33 struct bootrec_exp_if *exp_if;
34 struct bootrec *bootrec;
35 u32 *data = (u32 *)fw->data;
36 u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
37 u8 *fw_version = NULL;
38 size_t len;
39 int i;
40
41 if (priv->rx_start)
42 return;
43
44 while (data < end_data && *data)
45 data++;
46
47 while (data < end_data && !*data)
48 data++;
49
50 bootrec = (struct bootrec *) data;
51
52 while (bootrec->data <= end_data &&
53 (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
54 u32 code = le32_to_cpu(bootrec->code);
55 switch (code) {
56 case BR_CODE_COMPONENT_ID:
dc73c623 57 switch (be32_to_cpu(*(__be32 *)bootrec->data)) {
eff1a59c
MW		 58 case FW_FMAC:
59 printk(KERN_INFO "p54: FreeMAC firmware\n");
60 break;
61 case FW_LM20:
62 printk(KERN_INFO "p54: LM20 firmware\n");
63 break;
64 case FW_LM86:
65 printk(KERN_INFO "p54: LM86 firmware\n");
66 break;
67 case FW_LM87:
68 printk(KERN_INFO "p54: LM87 firmware - not supported yet!\n");
69 break;
70 default:
71 printk(KERN_INFO "p54: unknown firmware\n");
72 break;
73 }
74 break;
75 case BR_CODE_COMPONENT_VERSION:
76 /* 24 bytes should be enough for all firmwares */
77 if (strnlen((unsigned char*)bootrec->data, 24) < 24)
78 fw_version = (unsigned char*)bootrec->data;
79 break;
80 case BR_CODE_DESCR:
dc73c623 81 priv->rx_start = le32_to_cpu(((__le32 *)bootrec->data)[1]);
eff1a59c 82 /* FIXME add sanity checking */
dc73c623 83 priv->rx_end = le32_to_cpu(((__le32 *)bootrec->data)[2]) - 0x3500;
eff1a59c
MW		 84 break;
85 case BR_CODE_EXPOSED_IF:
86 exp_if = (struct bootrec_exp_if *) bootrec->data;
87 for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
dc73c623 88 if (exp_if[i].if_id == cpu_to_le16(0x1a))
eff1a59c
MW		 89 priv->fw_var = le16_to_cpu(exp_if[i].variant);
90 break;
91 case BR_CODE_DEPENDENT_IF:
92 break;
93 case BR_CODE_END_OF_BRA:
94 case LEGACY_BR_CODE_END_OF_BRA:
95 end_data = NULL;
96 break;
97 default:
98 break;
99 }
100 bootrec = (struct bootrec *)&bootrec->data[len];
101 }
102
103 if (fw_version)
104 printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
105 fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
106
107 if (priv->fw_var >= 0x300) {
108 /* Firmware supports QoS, use it! */
109 priv->tx_stats.data[0].limit = 3;
110 priv->tx_stats.data[1].limit = 4;
111 priv->tx_stats.data[2].limit = 3;
112 priv->tx_stats.data[3].limit = 1;
113 dev->queues = 4;
114 }
115}
116EXPORT_SYMBOL_GPL(p54_parse_firmware);
117
118static int p54_convert_rev0_to_rev1(struct ieee80211_hw *dev,
119 struct pda_pa_curve_data *curve_data)
120{
121 struct p54_common *priv = dev->priv;
122 struct pda_pa_curve_data_sample_rev1 *rev1;
123 struct pda_pa_curve_data_sample_rev0 *rev0;
124 size_t cd_len = sizeof(*curve_data) +
125 (curve_data->points_per_channel*sizeof(*rev1) + 2) *
126 curve_data->channels;
127 unsigned int i, j;
128 void *source, *target;
129
130 priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
131 if (!priv->curve_data)
132 return -ENOMEM;
133
134 memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
135 source = curve_data->data;
136 target = priv->curve_data->data;
137 for (i = 0; i < curve_data->channels; i++) {
138 __le16 *freq = source;
139 source += sizeof(__le16);
140 *((__le16 *)target) = *freq;
141 target += sizeof(__le16);
142 for (j = 0; j < curve_data->points_per_channel; j++) {
143 rev1 = target;
144 rev0 = source;
145
146 rev1->rf_power = rev0->rf_power;
147 rev1->pa_detector = rev0->pa_detector;
148 rev1->data_64qam = rev0->pcv;
149 /* "invent" the points for the other modulations */
150#define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
151 rev1->data_16qam = SUB(rev0->pcv, 12);
152 rev1->data_qpsk = SUB(rev1->data_16qam, 12);
153 rev1->data_bpsk = SUB(rev1->data_qpsk, 12);
154 rev1->data_barker= SUB(rev1->data_bpsk, 14);
155#undef SUB
156 target += sizeof(*rev1);
157 source += sizeof(*rev0);
158 }
159 }
160
161 return 0;
162}
163
164int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
165{
166 struct p54_common *priv = dev->priv;
167 struct eeprom_pda_wrap *wrap = NULL;
168 struct pda_entry *entry;
169 int i = 0;
170 unsigned int data_len, entry_len;
171 void *tmp;
172 int err;
173
174 wrap = (struct eeprom_pda_wrap *) eeprom;
175 entry = (void *)wrap->data + wrap->len;
176 i += 2;
177 i += le16_to_cpu(entry->len)*2;
178 while (i < len) {
179 entry_len = le16_to_cpu(entry->len);
180 data_len = ((entry_len - 1) << 1);
181 switch (le16_to_cpu(entry->code)) {
182 case PDR_MAC_ADDRESS:
183 SET_IEEE80211_PERM_ADDR(dev, entry->data);
184 break;
185 case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
186 if (data_len < 2) {
187 err = -EINVAL;
188 goto err;
189 }
190
191 if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
192 err = -EINVAL;
193 goto err;
194 }
195
196 priv->output_limit = kmalloc(entry->data[1] *
197 sizeof(*priv->output_limit), GFP_KERNEL);
198
199 if (!priv->output_limit) {
200 err = -ENOMEM;
201 goto err;
202 }
203
204 memcpy(priv->output_limit, &entry->data[2],
205 entry->data[1]*sizeof(*priv->output_limit));
206 priv->output_limit_len = entry->data[1];
207 break;
208 case PDR_PRISM_PA_CAL_CURVE_DATA:
209 if (data_len < sizeof(struct pda_pa_curve_data)) {
210 err = -EINVAL;
211 goto err;
212 }
213
214 if (((struct pda_pa_curve_data *)entry->data)->cal_method_rev) {
215 priv->curve_data = kmalloc(data_len, GFP_KERNEL);
216 if (!priv->curve_data) {
217 err = -ENOMEM;
218 goto err;
219 }
220
221 memcpy(priv->curve_data, entry->data, data_len);
222 } else {
223 err = p54_convert_rev0_to_rev1(dev, (struct pda_pa_curve_data *)entry->data);
224 if (err)
225 goto err;
226 }
227
228 break;
229 case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
230 priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
231 if (!priv->iq_autocal) {
232 err = -ENOMEM;
233 goto err;
234 }
235
236 memcpy(priv->iq_autocal, entry->data, data_len);
237 priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
238 break;
239 case PDR_INTERFACE_LIST:
240 tmp = entry->data;
241 while ((u8 *)tmp < entry->data + data_len) {
242 struct bootrec_exp_if *exp_if = tmp;
243 if (le16_to_cpu(exp_if->if_id) == 0xF)
244 priv->rxhw = exp_if->variant & cpu_to_le16(0x07);
245 tmp += sizeof(struct bootrec_exp_if);
246 }
247 break;
248 case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
249 priv->version = *(u8 *)(entry->data + 1);
250 break;
251 case PDR_END:
252 i = len;
253 break;
254 }
255
256 entry = (void *)entry + (entry_len + 1)*2;
257 i += 2;
258 i += entry_len*2;
259 }
260
261 if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) {
262 printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
263 err = -EINVAL;
264 goto err;
265 }
266
267 return 0;
268
269 err:
270 if (priv->iq_autocal) {
271 kfree(priv->iq_autocal);
272 priv->iq_autocal = NULL;
273 }
274
275 if (priv->output_limit) {
276 kfree(priv->output_limit);
277 priv->output_limit = NULL;
278 }
279
280 if (priv->curve_data) {
281 kfree(priv->curve_data);
282 priv->curve_data = NULL;
283 }
284
285 printk(KERN_ERR "p54: eeprom parse failed!\n");
286 return err;
287}
288EXPORT_SYMBOL_GPL(p54_parse_eeprom);
289
290void p54_fill_eeprom_readback(struct p54_control_hdr *hdr)
291{
292 struct p54_eeprom_lm86 *eeprom_hdr;
293
294 hdr->magic1 = cpu_to_le16(0x8000);
295 hdr->len = cpu_to_le16(sizeof(*eeprom_hdr) + 0x2000);
296 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK);
297 hdr->retry1 = hdr->retry2 = 0;
298 eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data;
299 eeprom_hdr->offset = 0x0;
300 eeprom_hdr->len = cpu_to_le16(0x2000);
301}
302EXPORT_SYMBOL_GPL(p54_fill_eeprom_readback);
303
304static void p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
305{
306 struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data;
307 struct ieee80211_rx_status rx_status = {0};
308 u16 freq = le16_to_cpu(hdr->freq);
309
310 rx_status.ssi = hdr->rssi;
311 rx_status.rate = hdr->rate & 0x1f; /* report short preambles & CCK too */
312 rx_status.channel = freq == 2484 ? 14 : (freq - 2407)/5;
313 rx_status.freq = freq;
314 rx_status.phymode = MODE_IEEE80211G;
315 rx_status.antenna = hdr->antenna;
316 rx_status.mactime = le64_to_cpu(hdr->timestamp);
03bffc13 317 rx_status.flag |= RX_FLAG_TSFT;
eff1a59c
MW		 318
319 skb_pull(skb, sizeof(*hdr));
320 skb_trim(skb, le16_to_cpu(hdr->len));
321
322 ieee80211_rx_irqsafe(dev, skb, &rx_status);
323}
324
325static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
326{
327 struct p54_common *priv = dev->priv;
328 int i;
329
330 /* ieee80211_start_queues is great if all queues are really empty.
331 * But, what if some are full? */
332
333 for (i = 0; i < dev->queues; i++)
334 if (priv->tx_stats.data[i].len < priv->tx_stats.data[i].limit)
335 ieee80211_wake_queue(dev, i);
336}
337
338static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
339{
340 struct p54_common *priv = dev->priv;
341 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
342 struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data;
343 struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
344 u32 addr = le32_to_cpu(hdr->req_id) - 0x70;
345 struct memrecord *range = NULL;
346 u32 freed = 0;
347 u32 last_addr = priv->rx_start;
348
349 while (entry != (struct sk_buff *)&priv->tx_queue) {
350 range = (struct memrecord *)&entry->cb;
351 if (range->start_addr == addr) {
352 struct ieee80211_tx_status status = {{0}};
353 struct p54_control_hdr *entry_hdr;
354 struct p54_tx_control_allocdata *entry_data;
355 int pad = 0;
356
357 if (entry->next != (struct sk_buff *)&priv->tx_queue)
358 freed = ((struct memrecord *)&entry->next->cb)->start_addr - last_addr;
359 else
360 freed = priv->rx_end - last_addr;
361
362 last_addr = range->end_addr;
363 __skb_unlink(entry, &priv->tx_queue);
364 if (!range->control) {
365 kfree_skb(entry);
366 break;
367 }
368 memcpy(&status.control, range->control,
369 sizeof(status.control));
370 kfree(range->control);
371 priv->tx_stats.data[status.control.queue].len--;
372
373 entry_hdr = (struct p54_control_hdr *) entry->data;
374 entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
375 if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
376 pad = entry_data->align[0];
377
f59d9782 378 if (!(status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
eff1a59c
MW		 379 if (!(payload->status & 0x01))
380 status.flags |= IEEE80211_TX_STATUS_ACK;
381 else
382 status.excessive_retries = 1;
383 }
384 status.retry_count = payload->retries - 1;
385 status.ack_signal = le16_to_cpu(payload->ack_rssi);
386 skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
387 ieee80211_tx_status_irqsafe(dev, entry, &status);
388 break;
389 } else
390 last_addr = range->end_addr;
391 entry = entry->next;
392 }
393
394 if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
395 sizeof(struct p54_control_hdr))
396 p54_wake_free_queues(dev);
397}
398
399static void p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
400{
401 struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
402
403 switch (le16_to_cpu(hdr->type)) {
404 case P54_CONTROL_TYPE_TXDONE:
405 p54_rx_frame_sent(dev, skb);
406 break;
407 case P54_CONTROL_TYPE_BBP:
408 break;
409 default:
410 printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
411 wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
412 break;
413 }
414}
415
416/* returns zero if skb can be reused */
417int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
418{
419 u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8;
420 switch (type) {
421 case 0x00:
422 case 0x01:
423 p54_rx_data(dev, skb);
424 return -1;
425 case 0x4d:
426 /* TODO: do something better... but then again, I've never seen this happen */
427 printk(KERN_ERR "%s: Received fault. Probably need to restart hardware now..\n",
428 wiphy_name(dev->wiphy));
429 break;
430 case 0x80:
431 p54_rx_control(dev, skb);
432 break;
433 default:
434 printk(KERN_ERR "%s: unknown frame RXed (0x%02x)\n",
435 wiphy_name(dev->wiphy), type);
436 break;
437 }
438 return 0;
439}
440EXPORT_SYMBOL_GPL(p54_rx);
441
442/*
443 * So, the firmware is somewhat stupid and doesn't know what places in its
444 * memory incoming data should go to. By poking around in the firmware, we
445 * can find some unused memory to upload our packets to. However, data that we
446 * want the card to TX needs to stay intact until the card has told us that
447 * it is done with it. This function finds empty places we can upload to and
448 * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
449 * allocated areas.
450 */
451static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
452 struct p54_control_hdr *data, u32 len,
453 struct ieee80211_tx_control *control)
454{
455 struct p54_common *priv = dev->priv;
456 struct sk_buff *entry = priv->tx_queue.next;
457 struct sk_buff *target_skb = NULL;
458 struct memrecord *range;
459 u32 last_addr = priv->rx_start;
460 u32 largest_hole = 0;
461 u32 target_addr = priv->rx_start;
462 unsigned long flags;
463 unsigned int left;
464 len = (len + 0x170 + 3) & ~0x3; /* 0x70 headroom, 0x100 tailroom */
465
466 spin_lock_irqsave(&priv->tx_queue.lock, flags);
467 left = skb_queue_len(&priv->tx_queue);
468 while (left--) {
469 u32 hole_size;
470 range = (struct memrecord *)&entry->cb;
471 hole_size = range->start_addr - last_addr;
472 if (!target_skb && hole_size >= len) {
473 target_skb = entry->prev;
474 hole_size -= len;
475 target_addr = last_addr;
476 }
477 largest_hole = max(largest_hole, hole_size);
478 last_addr = range->end_addr;
479 entry = entry->next;
480 }
481 if (!target_skb && priv->rx_end - last_addr >= len) {
482 target_skb = priv->tx_queue.prev;
483 largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
484 if (!skb_queue_empty(&priv->tx_queue)) {
485 range = (struct memrecord *)&target_skb->cb;
486 target_addr = range->end_addr;
487 }
488 } else
489 largest_hole = max(largest_hole, priv->rx_end - last_addr);
490
491 if (skb) {
492 range = (struct memrecord *)&skb->cb;
493 range->start_addr = target_addr;
494 range->end_addr = target_addr + len;
495 range->control = control;
496 __skb_queue_after(&priv->tx_queue, target_skb, skb);
497 if (largest_hole < IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
498 sizeof(struct p54_control_hdr))
499 ieee80211_stop_queues(dev);
500 }
501 spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
502
503 data->req_id = cpu_to_le32(target_addr + 0x70);
504}
505
506static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
507 struct ieee80211_tx_control *control)
508{
509 struct ieee80211_tx_queue_stats_data *current_queue;
510 struct p54_common *priv = dev->priv;
511 struct p54_control_hdr *hdr;
512 struct p54_tx_control_allocdata *txhdr;
513 struct ieee80211_tx_control *control_copy;
514 size_t padding, len;
515 u8 rate;
516
517 current_queue = &priv->tx_stats.data[control->queue];
518 if (unlikely(current_queue->len > current_queue->limit))
519 return NETDEV_TX_BUSY;
520 current_queue->len++;
521 current_queue->count++;
522 if (current_queue->len == current_queue->limit)
523 ieee80211_stop_queue(dev, control->queue);
524
525 padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
526 len = skb->len;
527
528 control_copy = kmalloc(sizeof(*control), GFP_ATOMIC);
529 if (control_copy)
530 memcpy(control_copy, control, sizeof(*control));
531
532 txhdr = (struct p54_tx_control_allocdata *)
533 skb_push(skb, sizeof(*txhdr) + padding);
534 hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
535
536 if (padding)
537 hdr->magic1 = cpu_to_le16(0x4010);
538 else
539 hdr->magic1 = cpu_to_le16(0x0010);
540 hdr->len = cpu_to_le16(len);
541 hdr->type = (control->flags & IEEE80211_TXCTL_NO_ACK) ? 0 : cpu_to_le16(1);
542 hdr->retry1 = hdr->retry2 = control->retry_limit;
543 p54_assign_address(dev, skb, hdr, skb->len, control_copy);
544
545 memset(txhdr->wep_key, 0x0, 16);
546 txhdr->padding = 0;
547 txhdr->padding2 = 0;
548
549 /* TODO: add support for alternate retry TX rates */
550 rate = control->tx_rate;
551 if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
552 rate |= 0x40;
553 else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
554 rate |= 0x20;
555 memset(txhdr->rateset, rate, 8);
556 txhdr->wep_key_present = 0;
557 txhdr->wep_key_len = 0;
558 txhdr->frame_type = cpu_to_le32(control->queue + 4);
559 txhdr->magic4 = 0;
560 txhdr->antenna = (control->antenna_sel_tx == 0) ?
561 2 : control->antenna_sel_tx - 1;
562 txhdr->output_power = 0x7f; // HW Maximum
563 txhdr->magic5 = (control->flags & IEEE80211_TXCTL_NO_ACK) ?
564 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23));
565 if (padding)
566 txhdr->align[0] = padding;
567
568 priv->tx(dev, hdr, skb->len, 0);
569 return 0;
570}
571
572static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
573 const u8 *dst, const u8 *src, u8 antenna,
574 u32 magic3, u32 magic8, u32 magic9)
575{
576 struct p54_common *priv = dev->priv;
577 struct p54_control_hdr *hdr;
578 struct p54_tx_control_filter *filter;
579
580 hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) +
ba8007ce 581 priv->tx_hdr_len, GFP_ATOMIC);
eff1a59c
MW		 582 if (!hdr)
583 return -ENOMEM;
584
585 hdr = (void *)hdr + priv->tx_hdr_len;
586
587 filter = (struct p54_tx_control_filter *) hdr->data;
588 hdr->magic1 = cpu_to_le16(0x8001);
589 hdr->len = cpu_to_le16(sizeof(*filter));
590 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter), NULL);
591 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
592
593 filter->filter_type = cpu_to_le16(filter_type);
594 memcpy(filter->dst, dst, ETH_ALEN);
595 if (!src)
596 memset(filter->src, ~0, ETH_ALEN);
597 else
598 memcpy(filter->src, src, ETH_ALEN);
599 filter->antenna = antenna;
600 filter->magic3 = cpu_to_le32(magic3);
601 filter->rx_addr = cpu_to_le32(priv->rx_end);
602 filter->max_rx = cpu_to_le16(0x0620); /* FIXME: for usb ver 1.. maybe */
603 filter->rxhw = priv->rxhw;
604 filter->magic8 = cpu_to_le16(magic8);
605 filter->magic9 = cpu_to_le16(magic9);
606
607 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*filter), 1);
608 return 0;
609}
610
611static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
612{
613 struct p54_common *priv = dev->priv;
614 struct p54_control_hdr *hdr;
615 struct p54_tx_control_channel *chan;
616 unsigned int i;
617 size_t payload_len = sizeof(*chan) + sizeof(u32)*2 +
618 sizeof(*chan->curve_data) *
619 priv->curve_data->points_per_channel;
620 void *entry;
621
622 hdr = kzalloc(sizeof(*hdr) + payload_len +
623 priv->tx_hdr_len, GFP_KERNEL);
624 if (!hdr)
625 return -ENOMEM;
626
627 hdr = (void *)hdr + priv->tx_hdr_len;
628
629 chan = (struct p54_tx_control_channel *) hdr->data;
630
631 hdr->magic1 = cpu_to_le16(0x8001);
632 hdr->len = cpu_to_le16(sizeof(*chan));
633 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
634 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + payload_len, NULL);
635
636 chan->magic1 = cpu_to_le16(0x1);
637 chan->magic2 = cpu_to_le16(0x0);
638
639 for (i = 0; i < priv->iq_autocal_len; i++) {
640 if (priv->iq_autocal[i].freq != freq)
641 continue;
642
643 memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
644 sizeof(*priv->iq_autocal));
645 break;
646 }
647 if (i == priv->iq_autocal_len)
648 goto err;
649
650 for (i = 0; i < priv->output_limit_len; i++) {
651 if (priv->output_limit[i].freq != freq)
652 continue;
653
654 chan->val_barker = 0x38;
655 chan->val_bpsk = priv->output_limit[i].val_bpsk;
656 chan->val_qpsk = priv->output_limit[i].val_qpsk;
657 chan->val_16qam = priv->output_limit[i].val_16qam;
658 chan->val_64qam = priv->output_limit[i].val_64qam;
659 break;
660 }
661 if (i == priv->output_limit_len)
662 goto err;
663
664 chan->pa_points_per_curve = priv->curve_data->points_per_channel;
665
666 entry = priv->curve_data->data;
667 for (i = 0; i < priv->curve_data->channels; i++) {
668 if (*((__le16 *)entry) != freq) {
669 entry += sizeof(__le16);
670 entry += sizeof(struct pda_pa_curve_data_sample_rev1) *
671 chan->pa_points_per_curve;
672 continue;
673 }
674
675 entry += sizeof(__le16);
676 memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
677 chan->pa_points_per_curve);
678 break;
679 }
680
681 memcpy(hdr->data + payload_len - 4, &chan->val_bpsk, 4);
682
683 priv->tx(dev, hdr, sizeof(*hdr) + payload_len, 1);
684 return 0;
685
686 err:
687 printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
688 kfree(hdr);
689 return -EINVAL;
690}
691
692static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
693{
694 struct p54_common *priv = dev->priv;
695 struct p54_control_hdr *hdr;
696 struct p54_tx_control_led *led;
697
698 hdr = kzalloc(sizeof(*hdr) + sizeof(*led) +
699 priv->tx_hdr_len, GFP_KERNEL);
700 if (!hdr)
701 return -ENOMEM;
702
703 hdr = (void *)hdr + priv->tx_hdr_len;
704 hdr->magic1 = cpu_to_le16(0x8001);
705 hdr->len = cpu_to_le16(sizeof(*led));
706 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
707 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led), NULL);
708
709 led = (struct p54_tx_control_led *) hdr->data;
710 led->mode = cpu_to_le16(mode);
711 led->led_permanent = cpu_to_le16(link);
712 led->led_temporary = cpu_to_le16(act);
713 led->duration = cpu_to_le16(1000);
714
715 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1);
716
717 return 0;
718}
719
720#define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, burst) \
721do { \
722 queue.aifs = cpu_to_le16(ai_fs); \
723 queue.cwmin = cpu_to_le16(cw_min); \
724 queue.cwmax = cpu_to_le16(cw_max); \
725 queue.txop = (burst == 0) ? \
726 0 : cpu_to_le16((burst * 100) / 32 + 1); \
727} while(0)
728
729static void p54_init_vdcf(struct ieee80211_hw *dev)
730{
731 struct p54_common *priv = dev->priv;
732 struct p54_control_hdr *hdr;
733 struct p54_tx_control_vdcf *vdcf;
734
735 /* all USB V1 adapters need a extra headroom */
736 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
737 hdr->magic1 = cpu_to_le16(0x8001);
738 hdr->len = cpu_to_le16(sizeof(*vdcf));
739 hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT);
740 hdr->req_id = cpu_to_le32(priv->rx_start);
741
742 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
743
744 P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 0x000f);
745 P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 0x001e);
746 P54_SET_QUEUE(vdcf->queue[2], 0x0002, 0x000f, 0x03ff, 0x0014);
747 P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0x0000);
748}
749
750static void p54_set_vdcf(struct ieee80211_hw *dev)
751{
752 struct p54_common *priv = dev->priv;
753 struct p54_control_hdr *hdr;
754 struct p54_tx_control_vdcf *vdcf;
755
756 hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
757
758 p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf), NULL);
759
760 vdcf = (struct p54_tx_control_vdcf *) hdr->data;
761
762 if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
763 vdcf->slottime = 9;
764 vdcf->magic1 = 0x00;
765 vdcf->magic2 = 0x10;
766 } else {
767 vdcf->slottime = 20;
768 vdcf->magic1 = 0x0a;
769 vdcf->magic2 = 0x06;
770 }
771
772 /* (see prism54/isl_oid.h for further details) */
773 vdcf->frameburst = cpu_to_le16(0);
774
775 priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0);
776}
777
4150c572
JB		 778static int p54_start(struct ieee80211_hw *dev)
779{
780 struct p54_common *priv = dev->priv;
781 int err;
782
783 err = priv->open(dev);
784 if (!err)
785 priv->mode = IEEE80211_IF_TYPE_MNTR;
786
787 return err;
788}
789
790static void p54_stop(struct ieee80211_hw *dev)
791{
792 struct p54_common *priv = dev->priv;
793 struct sk_buff *skb;
794 while ((skb = skb_dequeue(&priv->tx_queue))) {
795 struct memrecord *range = (struct memrecord *)&skb->cb;
796 if (range->control)
797 kfree(range->control);
798 kfree_skb(skb);
799 }
800 priv->stop(dev);
a2897552 801 priv->mode = IEEE80211_IF_TYPE_INVALID;
4150c572
JB		 802}
803
eff1a59c
MW		 804static int p54_add_interface(struct ieee80211_hw *dev,
805 struct ieee80211_if_init_conf *conf)
806{
807 struct p54_common *priv = dev->priv;
eff1a59c 808
4150c572
JB		 809 if (priv->mode != IEEE80211_IF_TYPE_MNTR)
810 return -EOPNOTSUPP;
eff1a59c
MW		 811
812 switch (conf->type) {
813 case IEEE80211_IF_TYPE_STA:
814 priv->mode = conf->type;
815 break;
816 default:
817 return -EOPNOTSUPP;
818 }
819
4150c572 820 memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
eff1a59c
MW		 821
822 p54_set_filter(dev, 0, priv->mac_addr, NULL, 0, 1, 0, 0xF642);
823 p54_set_filter(dev, 0, priv->mac_addr, NULL, 1, 0, 0, 0xF642);
eff1a59c
MW		 824
825 switch (conf->type) {
826 case IEEE80211_IF_TYPE_STA:
827 p54_set_filter(dev, 1, priv->mac_addr, NULL, 0, 0x15F, 0x1F4, 0);
828 break;
4150c572
JB		 829 default:
830 BUG(); /* impossible */
831 break;
eff1a59c
MW		 832 }
833
834 p54_set_leds(dev, 1, 0, 0);
835
836 return 0;
837}
838
839static void p54_remove_interface(struct ieee80211_hw *dev,
840 struct ieee80211_if_init_conf *conf)
841{
842 struct p54_common *priv = dev->priv;
4150c572
JB		 843 priv->mode = IEEE80211_IF_TYPE_MNTR;
844 memset(priv->mac_addr, 0, ETH_ALEN);
845 p54_set_filter(dev, 0, priv->mac_addr, NULL, 2, 0, 0, 0);
eff1a59c
MW		 846}
847
848static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
849{
850 int ret;
851
852 ret = p54_set_freq(dev, cpu_to_le16(conf->freq));
853 p54_set_vdcf(dev);
854 return ret;
855}
856
32bfd35d
JB		 857static int p54_config_interface(struct ieee80211_hw *dev,
858 struct ieee80211_vif *vif,
eff1a59c
MW		 859 struct ieee80211_if_conf *conf)
860{
861 struct p54_common *priv = dev->priv;
862
863 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642);
864 p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0);
865 p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
4150c572 866 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
eff1a59c
MW		 867 return 0;
868}
869
4150c572
JB		 870static void p54_configure_filter(struct ieee80211_hw *dev,
871 unsigned int changed_flags,
872 unsigned int *total_flags,
873 int mc_count, struct dev_mc_list *mclist)
874{
875 struct p54_common *priv = dev->priv;
876
877 *total_flags &= FIF_BCN_PRBRESP_PROMISC;
878
879 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
880 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
881 p54_set_filter(dev, 0, priv->mac_addr,
882 NULL, 2, 0, 0, 0);
883 else
884 p54_set_filter(dev, 0, priv->mac_addr,
885 priv->bssid, 2, 0, 0, 0);
886 }
887}
888
eff1a59c
MW		 889static int p54_conf_tx(struct ieee80211_hw *dev, int queue,
890 const struct ieee80211_tx_queue_params *params)
891{
892 struct p54_common *priv = dev->priv;
893 struct p54_tx_control_vdcf *vdcf;
894
895 vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
896 ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
897
898 if ((params) && !((queue < 0) || (queue > 4))) {
899 P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
900 params->cw_min, params->cw_max, params->burst_time);
901 } else
902 return -EINVAL;
903
904 p54_set_vdcf(dev);
905
906 return 0;
907}
908
909static int p54_get_stats(struct ieee80211_hw *dev,
910 struct ieee80211_low_level_stats *stats)
911{
912 /* TODO */
913 return 0;
914}
915
916static int p54_get_tx_stats(struct ieee80211_hw *dev,
917 struct ieee80211_tx_queue_stats *stats)
918{
919 struct p54_common *priv = dev->priv;
920 unsigned int i;
921
922 for (i = 0; i < dev->queues; i++)
923 memcpy(&stats->data[i], &priv->tx_stats.data[i],
924 sizeof(stats->data[i]));
925
926 return 0;
927}
928
929static const struct ieee80211_ops p54_ops = {
930 .tx = p54_tx,
4150c572
JB		 931 .start = p54_start,
932 .stop = p54_stop,
eff1a59c
MW		 933 .add_interface = p54_add_interface,
934 .remove_interface = p54_remove_interface,
935 .config = p54_config,
936 .config_interface = p54_config_interface,
4150c572 937 .configure_filter = p54_configure_filter,
eff1a59c
MW		 938 .conf_tx = p54_conf_tx,
939 .get_stats = p54_get_stats,
940 .get_tx_stats = p54_get_tx_stats
941};
942
943struct ieee80211_hw *p54_init_common(size_t priv_data_len)
944{
945 struct ieee80211_hw *dev;
946 struct p54_common *priv;
947 int i;
948
949 dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
950 if (!dev)
951 return NULL;
952
953 priv = dev->priv;
a2897552 954 priv->mode = IEEE80211_IF_TYPE_INVALID;
eff1a59c
MW		 955 skb_queue_head_init(&priv->tx_queue);
956 memcpy(priv->channels, p54_channels, sizeof(p54_channels));
957 memcpy(priv->rates, p54_rates, sizeof(p54_rates));
958 priv->modes[1].mode = MODE_IEEE80211B;
959 priv->modes[1].num_rates = 4;
960 priv->modes[1].rates = priv->rates;
961 priv->modes[1].num_channels = ARRAY_SIZE(p54_channels);
962 priv->modes[1].channels = priv->channels;
963 priv->modes[0].mode = MODE_IEEE80211G;
964 priv->modes[0].num_rates = ARRAY_SIZE(p54_rates);
965 priv->modes[0].rates = priv->rates;
966 priv->modes[0].num_channels = ARRAY_SIZE(p54_channels);
967 priv->modes[0].channels = priv->channels;
968 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
969 IEEE80211_HW_RX_INCLUDES_FCS;
970 dev->channel_change_time = 1000; /* TODO: find actual value */
971 dev->max_rssi = 127;
972
973 priv->tx_stats.data[0].limit = 5;
974 dev->queues = 1;
975
976 dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
977 sizeof(struct p54_tx_control_allocdata);
978
979 priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf) +
980 priv->tx_hdr_len + sizeof(struct p54_control_hdr), GFP_KERNEL);
981
982 if (!priv->cached_vdcf) {
983 ieee80211_free_hw(dev);
984 return NULL;
985 }
986
987 p54_init_vdcf(dev);
988
989 for (i = 0; i < 2; i++) {
990 if (ieee80211_register_hwmode(dev, &priv->modes[i])) {
991 kfree(priv->cached_vdcf);
992 ieee80211_free_hw(dev);
993 return NULL;
994 }
995 }
996
997 return dev;
998}
999EXPORT_SYMBOL_GPL(p54_init_common);
1000
1001void p54_free_common(struct ieee80211_hw *dev)
1002{
1003 struct p54_common *priv = dev->priv;
1004 kfree(priv->iq_autocal);
1005 kfree(priv->output_limit);
1006 kfree(priv->curve_data);
1007 kfree(priv->cached_vdcf);
1008}
1009EXPORT_SYMBOL_GPL(p54_free_common);
1010
1011static int __init p54_init(void)
1012{
1013 return 0;
1014}
1015
1016static void __exit p54_exit(void)
1017{
1018}
1019
1020module_init(p54_init);
1021module_exit(p54_exit);
Linux kernel - Deliverables
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