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rtl8xxxu: Rename rtl8723au_iqk_phy_iq_bb_reg
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
CommitLineData
26f1fad2
JS		 1/*
2 * RTL8XXXU mac80211 USB driver
3 *
eb188062 4 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
26f1fad2
JS		 5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
3307d840 45static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
b001e086 57MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
35a741fe
JS		 58MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
26f1fad2
JS		 60
61module_param_named(debug, rtl8xxxu_debug, int, 0600);
62MODULE_PARM_DESC(debug, "Set debug mask");
63module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66#define USB_VENDOR_ID_REALTEK 0x0bda
67/* Minimum IEEE80211_MAX_FRAME_LEN */
68#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69#define RTL8XXXU_RX_URBS 32
70#define RTL8XXXU_RX_URB_PENDING_WATER 8
71#define RTL8XXXU_TX_URBS 64
72#define RTL8XXXU_TX_URB_LOW_WATER 25
73#define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91};
92
93static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
57fbcce3 94 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
26f1fad2 95 .hw_value = 1, .max_power = 30 },
57fbcce3 96 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
26f1fad2 97 .hw_value = 2, .max_power = 30 },
57fbcce3 98 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
26f1fad2 99 .hw_value = 3, .max_power = 30 },
57fbcce3 100 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
26f1fad2 101 .hw_value = 4, .max_power = 30 },
57fbcce3 102 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
26f1fad2 103 .hw_value = 5, .max_power = 30 },
57fbcce3 104 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
26f1fad2 105 .hw_value = 6, .max_power = 30 },
57fbcce3 106 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
26f1fad2 107 .hw_value = 7, .max_power = 30 },
57fbcce3 108 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
26f1fad2 109 .hw_value = 8, .max_power = 30 },
57fbcce3 110 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
26f1fad2 111 .hw_value = 9, .max_power = 30 },
57fbcce3 112 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
26f1fad2 113 .hw_value = 10, .max_power = 30 },
57fbcce3 114 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
26f1fad2 115 .hw_value = 11, .max_power = 30 },
57fbcce3 116 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
26f1fad2 117 .hw_value = 12, .max_power = 30 },
57fbcce3 118 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
26f1fad2 119 .hw_value = 13, .max_power = 30 },
57fbcce3 120 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
26f1fad2
JS		 121 .hw_value = 14, .max_power = 30 }
122};
123
124static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129};
130
8db71451 131static struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
26f1fad2
JS		 132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154};
155
b7dd8ff9
JS		 156static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185};
186
c606e662
JS		 187static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
188 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
189 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
190 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
191 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
192 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
193 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
194 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
195 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
196 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
197 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
198 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
199 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
200 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
201 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
202 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
203 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
204 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
205 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
206 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
207 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
208 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
209 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
210 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
211 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
212 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
213 {0x70b, 0x87},
214 {0xffff, 0xff},
215};
216
06d05463 217#ifdef CONFIG_RTL8XXXU_UNTESTED
2fc0b8e5
JS		 218static struct rtl8xxxu_power_base rtl8188r_power_base = {
219 .reg_0e00 = 0x06080808,
220 .reg_0e04 = 0x00040406,
221 .reg_0e08 = 0x00000000,
222 .reg_086c = 0x00000000,
223
224 .reg_0e10 = 0x04060608,
225 .reg_0e14 = 0x00020204,
226 .reg_0e18 = 0x04060608,
227 .reg_0e1c = 0x00020204,
228
229 .reg_0830 = 0x06080808,
230 .reg_0834 = 0x00040406,
231 .reg_0838 = 0x00000000,
232 .reg_086c_2 = 0x00000000,
233
234 .reg_083c = 0x04060608,
235 .reg_0848 = 0x00020204,
236 .reg_084c = 0x04060608,
237 .reg_0868 = 0x00020204,
238};
239
240static struct rtl8xxxu_power_base rtl8192c_power_base = {
241 .reg_0e00 = 0x07090c0c,
242 .reg_0e04 = 0x01020405,
243 .reg_0e08 = 0x00000000,
244 .reg_086c = 0x00000000,
245
246 .reg_0e10 = 0x0b0c0c0e,
247 .reg_0e14 = 0x01030506,
248 .reg_0e18 = 0x0b0c0d0e,
249 .reg_0e1c = 0x01030509,
250
251 .reg_0830 = 0x07090c0c,
252 .reg_0834 = 0x01020405,
253 .reg_0838 = 0x00000000,
254 .reg_086c_2 = 0x00000000,
255
256 .reg_083c = 0x0b0c0d0e,
257 .reg_0848 = 0x01030509,
258 .reg_084c = 0x0b0c0d0e,
259 .reg_0868 = 0x01030509,
260};
06d05463 261#endif
2fc0b8e5
JS		 262
263static struct rtl8xxxu_power_base rtl8723a_power_base = {
264 .reg_0e00 = 0x0a0c0c0c,
265 .reg_0e04 = 0x02040608,
266 .reg_0e08 = 0x00000000,
267 .reg_086c = 0x00000000,
268
269 .reg_0e10 = 0x0a0c0d0e,
270 .reg_0e14 = 0x02040608,
271 .reg_0e18 = 0x0a0c0d0e,
272 .reg_0e1c = 0x02040608,
273
274 .reg_0830 = 0x0a0c0c0c,
275 .reg_0834 = 0x02040608,
276 .reg_0838 = 0x00000000,
277 .reg_086c_2 = 0x00000000,
278
279 .reg_083c = 0x0a0c0d0e,
280 .reg_0848 = 0x02040608,
281 .reg_084c = 0x0a0c0d0e,
282 .reg_0868 = 0x02040608,
283};
284
26f1fad2
JS		 285static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00390004},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
298 {0x860, 0x66f60110}, {0x864, 0x061f0130},
299 {0x868, 0x00000000}, {0x86c, 0x32323200},
300 {0x870, 0x07000760}, {0x874, 0x22004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xc0083070}, {0x884, 0x000004d5},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
309 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
310 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
311 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
312 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
313 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
314 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
315 {0xa78, 0x00000900},
316 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
317 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
318 {0xc10, 0x08800000}, {0xc14, 0x40000100},
319 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
320 {0xc20, 0x00000000}, {0xc24, 0x00000000},
321 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
322 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
323 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
324 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
325 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
326 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
327 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
328 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
329 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
330 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
331 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
332 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
333 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
334 {0xc90, 0x00121820}, {0xc94, 0x00000000},
335 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
336 {0xca0, 0x00000000}, {0xca4, 0x00000080},
337 {0xca8, 0x00000000}, {0xcac, 0x00000000},
338 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
339 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
340 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
341 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
342 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
343 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
344 {0xce0, 0x00222222}, {0xce4, 0x00000000},
345 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
346 {0xd00, 0x00080740}, {0xd04, 0x00020401},
347 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
348 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
349 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
350 {0xd30, 0x00000000}, {0xd34, 0x80608000},
351 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
352 {0xd40, 0x00000000}, {0xd44, 0x00000000},
353 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
354 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
355 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
356 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
357 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
358 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
359 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
360 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
361 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
362 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
363 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
364 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
365 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
366 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
367 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
368 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
369 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
370 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
371 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
372 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
373 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
374 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
375 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
376 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
377 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
378 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
379 {0xf00, 0x00000300},
380 {0xffff, 0xffffffff},
381};
382
36c32588
JS		 383static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
384 {0x800, 0x80040000}, {0x804, 0x00000003},
385 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
386 {0x810, 0x10001331}, {0x814, 0x020c3d10},
387 {0x818, 0x02200385}, {0x81c, 0x00000000},
388 {0x820, 0x01000100}, {0x824, 0x00190204},
389 {0x828, 0x00000000}, {0x82c, 0x00000000},
390 {0x830, 0x00000000}, {0x834, 0x00000000},
391 {0x838, 0x00000000}, {0x83c, 0x00000000},
392 {0x840, 0x00010000}, {0x844, 0x00000000},
393 {0x848, 0x00000000}, {0x84c, 0x00000000},
394 {0x850, 0x00000000}, {0x854, 0x00000000},
395 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
396 {0x860, 0x66f60110}, {0x864, 0x061f0649},
397 {0x868, 0x00000000}, {0x86c, 0x27272700},
398 {0x870, 0x07000760}, {0x874, 0x25004000},
399 {0x878, 0x00000808}, {0x87c, 0x00000000},
400 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
401 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
402 {0x890, 0x00000800}, {0x894, 0xfffffffe},
403 {0x898, 0x40302010}, {0x89c, 0x00706050},
404 {0x900, 0x00000000}, {0x904, 0x00000023},
405 {0x908, 0x00000000}, {0x90c, 0x81121111},
406 {0x910, 0x00000002}, {0x914, 0x00000201},
407 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
408 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
409 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
410 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
411 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
412 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
413 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
414 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
415 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
416 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
417 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
418 {0xc10, 0x08800000}, {0xc14, 0x40000100},
419 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
420 {0xc20, 0x00000000}, {0xc24, 0x00000000},
421 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
422 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
423 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
424 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
425 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
426 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
427 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
428 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
429 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
430 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
431 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
432 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
433 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
434 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
435 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
436 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
437 {0xca8, 0x00000000}, {0xcac, 0x00000000},
438 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
439 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
440 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
441 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
442 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
443 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
444 {0xce0, 0x00222222}, {0xce4, 0x00000000},
445 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
446 {0xd00, 0x00000740}, {0xd04, 0x40020401},
447 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
448 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
449 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
450 {0xd30, 0x00000000}, {0xd34, 0x80608000},
451 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
452 {0xd40, 0x00000000}, {0xd44, 0x00000000},
453 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
454 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
455 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
456 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
457 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
458 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
459 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
460 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
461 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
462 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
463 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
464 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
465 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
466 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
467 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
468 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
469 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
470 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
471 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
472 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
473 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
474 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
475 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
476 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
477 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
478 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
479 {0xf00, 0x00000300},
480 {0x820, 0x01000100}, {0x800, 0x83040000},
481 {0xffff, 0xffffffff},
482};
483
26f1fad2
JS		 484static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x800, 0x80040002}, {0x804, 0x00000003},
487 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
488 {0x810, 0x10000330}, {0x814, 0x020c3d10},
489 {0x818, 0x02200385}, {0x81c, 0x00000000},
490 {0x820, 0x01000100}, {0x824, 0x00390004},
491 {0x828, 0x01000100}, {0x82c, 0x00390004},
492 {0x830, 0x27272727}, {0x834, 0x27272727},
493 {0x838, 0x27272727}, {0x83c, 0x27272727},
494 {0x840, 0x00010000}, {0x844, 0x00010000},
495 {0x848, 0x27272727}, {0x84c, 0x27272727},
496 {0x850, 0x00000000}, {0x854, 0x00000000},
497 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
498 {0x860, 0x66e60230}, {0x864, 0x061f0130},
499 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
500 {0x870, 0x07000700}, {0x874, 0x22184000},
501 {0x878, 0x08080808}, {0x87c, 0x00000000},
502 {0x880, 0xc0083070}, {0x884, 0x000004d5},
503 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
504 {0x890, 0x00000800}, {0x894, 0xfffffffe},
505 {0x898, 0x40302010}, {0x89c, 0x00706050},
506 {0x900, 0x00000000}, {0x904, 0x00000023},
507 {0x908, 0x00000000}, {0x90c, 0x81121313},
508 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
509 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
510 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
511 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
512 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
513 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
514 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
515 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
516 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
517 {0xc10, 0x08800000}, {0xc14, 0x40000100},
518 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
519 {0xc20, 0x00000000}, {0xc24, 0x00000000},
520 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
521 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
522 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
523 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
524 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
525 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
526 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
527 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
528 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
529 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
530 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
531 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
532 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
533 {0xc90, 0x00121820}, {0xc94, 0x00000000},
534 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
535 {0xca0, 0x00000000}, {0xca4, 0x00000080},
536 {0xca8, 0x00000000}, {0xcac, 0x00000000},
537 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
538 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
539 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
540 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
541 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
542 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
543 {0xce0, 0x00222222}, {0xce4, 0x00000000},
544 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
545 {0xd00, 0x00080740}, {0xd04, 0x00020403},
546 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
547 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
548 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
549 {0xd30, 0x00000000}, {0xd34, 0x80608000},
550 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
551 {0xd40, 0x00000000}, {0xd44, 0x00000000},
552 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
553 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
554 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
555 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
556 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
557 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
558 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
559 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
560 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
561 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
562 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
563 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
564 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
565 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
566 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
567 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
568 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
569 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
570 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
571 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
572 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
573 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
574 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
575 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
576 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
577 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
578 {0xf00, 0x00000300},
579 {0xffff, 0xffffffff},
580};
581
582static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
583 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
584 {0x040, 0x000c0004}, {0x800, 0x80040000},
585 {0x804, 0x00000001}, {0x808, 0x0000fc00},
586 {0x80c, 0x0000000a}, {0x810, 0x10005388},
587 {0x814, 0x020c3d10}, {0x818, 0x02200385},
588 {0x81c, 0x00000000}, {0x820, 0x01000100},
589 {0x824, 0x00390204}, {0x828, 0x00000000},
590 {0x82c, 0x00000000}, {0x830, 0x00000000},
591 {0x834, 0x00000000}, {0x838, 0x00000000},
592 {0x83c, 0x00000000}, {0x840, 0x00010000},
593 {0x844, 0x00000000}, {0x848, 0x00000000},
594 {0x84c, 0x00000000}, {0x850, 0x00000000},
595 {0x854, 0x00000000}, {0x858, 0x569a569a},
596 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
597 {0x864, 0x061f0130}, {0x868, 0x00000000},
598 {0x86c, 0x20202000}, {0x870, 0x03000300},
599 {0x874, 0x22004000}, {0x878, 0x00000808},
600 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
601 {0x884, 0x000004d5}, {0x888, 0x00000000},
602 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
603 {0x894, 0xfffffffe}, {0x898, 0x40302010},
604 {0x89c, 0x00706050}, {0x900, 0x00000000},
605 {0x904, 0x00000023}, {0x908, 0x00000000},
606 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
607 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
608 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
609 {0xa14, 0x11144028}, {0xa18, 0x00881117},
610 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
611 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
612 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
613 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
614 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
615 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
616 {0xc14, 0x40000100}, {0xc18, 0x08800000},
617 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
618 {0xc24, 0x00000000}, {0xc28, 0x00000000},
619 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
620 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
621 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
622 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
623 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
624 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
625 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
626 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
627 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
628 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
629 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
630 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
631 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
632 {0xc94, 0x00000000}, {0xc98, 0x00121820},
633 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
634 {0xca4, 0x00000080}, {0xca8, 0x00000000},
635 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
636 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
637 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
638 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
639 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
640 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
641 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
642 {0xce4, 0x00000000}, {0xce8, 0x37644302},
643 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
644 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
645 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
646 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
647 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
648 {0xd34, 0x80608000}, {0xd38, 0x00000000},
649 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
650 {0xd44, 0x00000000}, {0xd48, 0x00000000},
651 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
652 {0xd54, 0x00000000}, {0xd58, 0x00000000},
653 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
654 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
655 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
656 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
657 {0xe00, 0x24242424}, {0xe04, 0x24242424},
658 {0xe08, 0x03902024}, {0xe10, 0x24242424},
659 {0xe14, 0x24242424}, {0xe18, 0x24242424},
660 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
661 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
662 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
663 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
664 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
665 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
666 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
667 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
668 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
669 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
670 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
671 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
672 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
673 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
674 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
675 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
676 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
677 {0xf00, 0x00000300},
678 {0xffff, 0xffffffff},
679};
680
ae14c5d2
JS		 681static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
682 {0x800, 0x80040000}, {0x804, 0x00000003},
683 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
684 {0x810, 0x10001331}, {0x814, 0x020c3d10},
685 {0x818, 0x02220385}, {0x81c, 0x00000000},
686 {0x820, 0x01000100}, {0x824, 0x00390204},
687 {0x828, 0x01000100}, {0x82c, 0x00390204},
688 {0x830, 0x32323232}, {0x834, 0x30303030},
689 {0x838, 0x30303030}, {0x83c, 0x30303030},
690 {0x840, 0x00010000}, {0x844, 0x00010000},
691 {0x848, 0x28282828}, {0x84c, 0x28282828},
692 {0x850, 0x00000000}, {0x854, 0x00000000},
693 {0x858, 0x009a009a}, {0x85c, 0x01000014},
694 {0x860, 0x66f60000}, {0x864, 0x061f0000},
695 {0x868, 0x30303030}, {0x86c, 0x30303030},
696 {0x870, 0x00000000}, {0x874, 0x55004200},
697 {0x878, 0x08080808}, {0x87c, 0x00000000},
698 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
699 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
700 {0x890, 0x00000800}, {0x894, 0xfffffffe},
701 {0x898, 0x40302010}, {0x900, 0x00000000},
702 {0x904, 0x00000023}, {0x908, 0x00000000},
703 {0x90c, 0x81121313}, {0x910, 0x806c0001},
704 {0x914, 0x00000001}, {0x918, 0x00000000},
705 {0x91c, 0x00010000}, {0x924, 0x00000001},
706 {0x928, 0x00000000}, {0x92c, 0x00000000},
707 {0x930, 0x00000000}, {0x934, 0x00000000},
708 {0x938, 0x00000000}, {0x93c, 0x00000000},
709 {0x940, 0x00000000}, {0x944, 0x00000000},
710 {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
711 {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
712 {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
713 {0xa14, 0x1114d028}, {0xa18, 0x00881117},
714 {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
715 {0xa24, 0x090e1317}, {0xa28, 0x00000204},
716 {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
717 {0xa74, 0x00000007}, {0xa78, 0x00000900},
718 {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
719 {0xb38, 0x00000000}, {0xc00, 0x48071d40},
720 {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
721 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
722 {0xc14, 0x40000100}, {0xc18, 0x08800000},
723 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
724 {0xc24, 0x00000000}, {0xc28, 0x00000000},
725 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
726 {0xc34, 0x469652af}, {0xc38, 0x49795994},
727 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
728 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
729 {0xc4c, 0x007f037f},
730#ifdef EXT_PA_8192EU
731 /* External PA or external LNA */
732 {0xc50, 0x00340220},
733#else
734 {0xc50, 0x00340020},
735#endif
736 {0xc54, 0x0080801f},
737#ifdef EXT_PA_8192EU
738 /* External PA or external LNA */
739 {0xc58, 0x00000220},
740#else
741 {0xc58, 0x00000020},
742#endif
743 {0xc5c, 0x00248492}, {0xc60, 0x00000000},
744 {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
745 {0xc6c, 0x00000036}, {0xc70, 0x00000600},
746 {0xc74, 0x02013169}, {0xc78, 0x0000001f},
747 {0xc7c, 0x00b91612},
748#ifdef EXT_PA_8192EU
749 /* External PA or external LNA */
750 {0xc80, 0x2d4000b5},
751#else
752 {0xc80, 0x40000100},
753#endif
754 {0xc84, 0x21f60000},
755#ifdef EXT_PA_8192EU
756 /* External PA or external LNA */
757 {0xc88, 0x2d4000b5},
758#else
759 {0xc88, 0x40000100},
760#endif
761 {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
762 {0xc94, 0x00000000}, {0xc98, 0x00121820},
763 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
764 {0xca4, 0x000300a0}, {0xca8, 0x00000000},
765 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
766 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
767 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
768 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
769 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
770 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
771 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
772 {0xce4, 0x00040000}, {0xce8, 0x77644302},
773 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
774 {0xd04, 0x00020403}, {0xd08, 0x0000907f},
775 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
776 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
777 {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
778 {0xd30, 0x00000000}, {0xd34, 0x80608000},
779 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
780 {0xd40, 0x00000000}, {0xd44, 0x00000000},
781 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
782 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
783 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
784 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
785 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
786 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
787 {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
788 {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
789 {0xe00, 0x30303030}, {0xe04, 0x30303030},
790 {0xe08, 0x03903030}, {0xe10, 0x30303030},
791 {0xe14, 0x30303030}, {0xe18, 0x30303030},
792 {0xe1c, 0x30303030}, {0xe28, 0x00000000},
793 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
794 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
795 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
796 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
797 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
798 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
799 {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
800 {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
801 {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
802 {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
803 {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
804 {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
805 {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
806 {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
807 {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
808 {0xee8, 0x00000001}, {0xf14, 0x00000003},
809 {0xf4c, 0x00000000}, {0xf00, 0x00000300},
810 {0xffff, 0xffffffff},
811};
812
26f1fad2
JS		 813static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
814 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
815 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
816 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
817 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
818 {0xc78, 0x78080001}, {0xc78, 0x77090001},
819 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
820 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
821 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
822 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
823 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
824 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
825 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
826 {0xc78, 0x68180001}, {0xc78, 0x67190001},
827 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
828 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
829 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
830 {0xc78, 0x60200001}, {0xc78, 0x49210001},
831 {0xc78, 0x48220001}, {0xc78, 0x47230001},
832 {0xc78, 0x46240001}, {0xc78, 0x45250001},
833 {0xc78, 0x44260001}, {0xc78, 0x43270001},
834 {0xc78, 0x42280001}, {0xc78, 0x41290001},
835 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
836 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
837 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
838 {0xc78, 0x21300001}, {0xc78, 0x20310001},
839 {0xc78, 0x06320001}, {0xc78, 0x05330001},
840 {0xc78, 0x04340001}, {0xc78, 0x03350001},
841 {0xc78, 0x02360001}, {0xc78, 0x01370001},
842 {0xc78, 0x00380001}, {0xc78, 0x00390001},
843 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
844 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
845 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
846 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
847 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
848 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
849 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
850 {0xc78, 0x78480001}, {0xc78, 0x77490001},
851 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
852 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
853 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
854 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
855 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
856 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
857 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
858 {0xc78, 0x68580001}, {0xc78, 0x67590001},
859 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
860 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
861 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
862 {0xc78, 0x60600001}, {0xc78, 0x49610001},
863 {0xc78, 0x48620001}, {0xc78, 0x47630001},
864 {0xc78, 0x46640001}, {0xc78, 0x45650001},
865 {0xc78, 0x44660001}, {0xc78, 0x43670001},
866 {0xc78, 0x42680001}, {0xc78, 0x41690001},
867 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
868 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
869 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
870 {0xc78, 0x21700001}, {0xc78, 0x20710001},
871 {0xc78, 0x06720001}, {0xc78, 0x05730001},
872 {0xc78, 0x04740001}, {0xc78, 0x03750001},
873 {0xc78, 0x02760001}, {0xc78, 0x01770001},
874 {0xc78, 0x00780001}, {0xc78, 0x00790001},
875 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
876 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
877 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
878 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
879 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
880 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
881 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
882 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
883 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
884 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
885 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
886 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
887 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
888 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
889 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
890 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
891 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
892 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
893 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
894 {0xffff, 0xffffffff}
895};
896
897static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
898 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
899 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
900 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
901 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
902 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
903 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
904 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
905 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
906 {0xc78, 0x73100001}, {0xc78, 0x72110001},
907 {0xc78, 0x71120001}, {0xc78, 0x70130001},
908 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
909 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
910 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
911 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
912 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
913 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
914 {0xc78, 0x63200001}, {0xc78, 0x62210001},
915 {0xc78, 0x61220001}, {0xc78, 0x60230001},
916 {0xc78, 0x46240001}, {0xc78, 0x45250001},
917 {0xc78, 0x44260001}, {0xc78, 0x43270001},
918 {0xc78, 0x42280001}, {0xc78, 0x41290001},
919 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
920 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
921 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
922 {0xc78, 0x21300001}, {0xc78, 0x20310001},
923 {0xc78, 0x06320001}, {0xc78, 0x05330001},
924 {0xc78, 0x04340001}, {0xc78, 0x03350001},
925 {0xc78, 0x02360001}, {0xc78, 0x01370001},
926 {0xc78, 0x00380001}, {0xc78, 0x00390001},
927 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
928 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
929 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
930 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
931 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
932 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
933 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
934 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
935 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
936 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
937 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
938 {0xc78, 0x73500001}, {0xc78, 0x72510001},
939 {0xc78, 0x71520001}, {0xc78, 0x70530001},
940 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
941 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
942 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
943 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
944 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
945 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
946 {0xc78, 0x63600001}, {0xc78, 0x62610001},
947 {0xc78, 0x61620001}, {0xc78, 0x60630001},
948 {0xc78, 0x46640001}, {0xc78, 0x45650001},
949 {0xc78, 0x44660001}, {0xc78, 0x43670001},
950 {0xc78, 0x42680001}, {0xc78, 0x41690001},
951 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
952 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
953 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
954 {0xc78, 0x21700001}, {0xc78, 0x20710001},
955 {0xc78, 0x06720001}, {0xc78, 0x05730001},
956 {0xc78, 0x04740001}, {0xc78, 0x03750001},
957 {0xc78, 0x02760001}, {0xc78, 0x01770001},
958 {0xc78, 0x00780001}, {0xc78, 0x00790001},
959 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
960 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
961 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
962 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
963 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
964 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
965 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
966 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
967 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
968 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
969 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
970 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
971 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
972 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
973 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
974 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
975 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
976 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
977 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
978 {0xffff, 0xffffffff}
979};
980
b9f498e1
JS		 981static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
982 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
983 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
984 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
985 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
986 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
987 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
988 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
989 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
990 {0xc78, 0xed100001}, {0xc78, 0xec110001},
991 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
992 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
993 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
994 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
995 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
996 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
997 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
998 {0xc78, 0x65200001}, {0xc78, 0x64210001},
999 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
1000 {0xc78, 0x49240001}, {0xc78, 0x48250001},
1001 {0xc78, 0x47260001}, {0xc78, 0x46270001},
1002 {0xc78, 0x45280001}, {0xc78, 0x44290001},
1003 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
1004 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
1005 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
1006 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
1007 {0xc78, 0x08320001}, {0xc78, 0x07330001},
1008 {0xc78, 0x06340001}, {0xc78, 0x05350001},
1009 {0xc78, 0x04360001}, {0xc78, 0x03370001},
1010 {0xc78, 0x02380001}, {0xc78, 0x01390001},
1011 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
1012 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
1013 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
1014 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
1015 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
1016 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
1017 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
1018 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
1019 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
1020 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
1021 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
1022 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
1023 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
1024 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
1025 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
1026 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
1027 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
1028 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
1029 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
1030 {0xc78, 0x65600001}, {0xc78, 0x64610001},
1031 {0xc78, 0x63620001}, {0xc78, 0x62630001},
1032 {0xc78, 0x61640001}, {0xc78, 0x48650001},
1033 {0xc78, 0x47660001}, {0xc78, 0x46670001},
1034 {0xc78, 0x45680001}, {0xc78, 0x44690001},
1035 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
1036 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
1037 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
1038 {0xc78, 0x24700001}, {0xc78, 0x09710001},
1039 {0xc78, 0x08720001}, {0xc78, 0x07730001},
1040 {0xc78, 0x06740001}, {0xc78, 0x05750001},
1041 {0xc78, 0x04760001}, {0xc78, 0x03770001},
1042 {0xc78, 0x02780001}, {0xc78, 0x01790001},
1043 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
1044 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
1045 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
1046 {0xc50, 0x69553422},
1047 {0xc50, 0x69553420},
1048 {0x824, 0x00390204},
1049 {0xffff, 0xffffffff}
1050};
1051
e293278d
JS		 1052static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
1053 {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
1054 {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
1055 {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
1056 {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
1057 {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
1058 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
1059 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
1060 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
1061 {0xc78, 0xf0100001}, {0xc78, 0xef110001},
1062 {0xc78, 0xee120001}, {0xc78, 0xed130001},
1063 {0xc78, 0xec140001}, {0xc78, 0xeb150001},
1064 {0xc78, 0xea160001}, {0xc78, 0xe9170001},
1065 {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
1066 {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
1067 {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
1068 {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
1069 {0xc78, 0x04200001}, {0xc78, 0x03210001},
1070 {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
1071 {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
1072 {0xc78, 0xa6260001}, {0xc78, 0x85270001},
1073 {0xc78, 0x84280001}, {0xc78, 0x83290001},
1074 {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
1075 {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
1076 {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
1077 {0xc78, 0x65300001}, {0xc78, 0x64310001},
1078 {0xc78, 0x63320001}, {0xc78, 0x62330001},
1079 {0xc78, 0x61340001}, {0xc78, 0x45350001},
1080 {0xc78, 0x44360001}, {0xc78, 0x43370001},
1081 {0xc78, 0x42380001}, {0xc78, 0x41390001},
1082 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
1083 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
1084 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
1085 {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
1086 {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
1087 {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
1088 {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
1089 {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
1090 {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
1091 {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
1092 {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
1093 {0xc78, 0xf0500001}, {0xc78, 0xef510001},
1094 {0xc78, 0xee520001}, {0xc78, 0xed530001},
1095 {0xc78, 0xec540001}, {0xc78, 0xeb550001},
1096 {0xc78, 0xea560001}, {0xc78, 0xe9570001},
1097 {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
1098 {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
1099 {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
1100 {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
1101 {0xc78, 0x8a600001}, {0xc78, 0x89610001},
1102 {0xc78, 0x88620001}, {0xc78, 0x87630001},
1103 {0xc78, 0x86640001}, {0xc78, 0x85650001},
1104 {0xc78, 0x84660001}, {0xc78, 0x83670001},
1105 {0xc78, 0x82680001}, {0xc78, 0x6b690001},
1106 {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
1107 {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
1108 {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
1109 {0xc78, 0x64700001}, {0xc78, 0x63710001},
1110 {0xc78, 0x62720001}, {0xc78, 0x61730001},
1111 {0xc78, 0x49740001}, {0xc78, 0x48750001},
1112 {0xc78, 0x47760001}, {0xc78, 0x46770001},
1113 {0xc78, 0x45780001}, {0xc78, 0x44790001},
1114 {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
1115 {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
1116 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
1117 {0xc50, 0x00040022}, {0xc50, 0x00040020},
1118 {0xffff, 0xffffffff}
1119};
1120
1121static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
1122 {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
1123 {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
1124 {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
1125 {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
1126 {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
1127 {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
1128 {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
1129 {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
1130 {0xc78, 0xea100001}, {0xc78, 0xe9110001},
1131 {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
1132 {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
1133 {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
1134 {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
1135 {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
1136 {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
1137 {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
1138 {0xc78, 0x84200001}, {0xc78, 0x83210001},
1139 {0xc78, 0x82220001}, {0xc78, 0x6a230001},
1140 {0xc78, 0x69240001}, {0xc78, 0x68250001},
1141 {0xc78, 0x67260001}, {0xc78, 0x66270001},
1142 {0xc78, 0x65280001}, {0xc78, 0x64290001},
1143 {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
1144 {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
1145 {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
1146 {0xc78, 0x45300001}, {0xc78, 0x44310001},
1147 {0xc78, 0x43320001}, {0xc78, 0x42330001},
1148 {0xc78, 0x41340001}, {0xc78, 0x40350001},
1149 {0xc78, 0x40360001}, {0xc78, 0x40370001},
1150 {0xc78, 0x40380001}, {0xc78, 0x40390001},
1151 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
1152 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
1153 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
1154 {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
1155 {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
1156 {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
1157 {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
1158 {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
1159 {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
1160 {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
1161 {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
1162 {0xc78, 0xea500001}, {0xc78, 0xe9510001},
1163 {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
1164 {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
1165 {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
1166 {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
1167 {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
1168 {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
1169 {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
1170 {0xc78, 0x84600001}, {0xc78, 0x83610001},
1171 {0xc78, 0x82620001}, {0xc78, 0x6a630001},
1172 {0xc78, 0x69640001}, {0xc78, 0x68650001},
1173 {0xc78, 0x67660001}, {0xc78, 0x66670001},
1174 {0xc78, 0x65680001}, {0xc78, 0x64690001},
1175 {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
1176 {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
1177 {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
1178 {0xc78, 0x45700001}, {0xc78, 0x44710001},
1179 {0xc78, 0x43720001}, {0xc78, 0x42730001},
1180 {0xc78, 0x41740001}, {0xc78, 0x40750001},
1181 {0xc78, 0x40760001}, {0xc78, 0x40770001},
1182 {0xc78, 0x40780001}, {0xc78, 0x40790001},
1183 {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
1184 {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
1185 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
1186 {0xc50, 0x00040222}, {0xc50, 0x00040220},
1187 {0xffff, 0xffffffff}
1188};
1189
26f1fad2
JS		 1190static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
1191 {0x00, 0x00030159}, {0x01, 0x00031284},
1192 {0x02, 0x00098000}, {0x03, 0x00039c63},
1193 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1194 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
1195 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
1196 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1197 {0x19, 0x00000000}, {0x1a, 0x00030355},
1198 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1199 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
1200 {0x1f, 0x00000000}, {0x20, 0x0000b614},
1201 {0x21, 0x0006c000}, {0x22, 0x00000000},
1202 {0x23, 0x00001558}, {0x24, 0x00000060},
1203 {0x25, 0x00000483}, {0x26, 0x0004f000},
1204 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
1205 {0x29, 0x00004783}, {0x2a, 0x00000001},
1206 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1207 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1208 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1209 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1210 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1211 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1212 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1213 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1214 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1215 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1216 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1217 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1218 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1219 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1220 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1221 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1222 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1223 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1224 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1225 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1226 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1227 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1228 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1229 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1230 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1231 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1232 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1233 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1234 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1235 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1236 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1237 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1238 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1239 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1240 {0x10, 0x00000000}, {0x11, 0x00000000},
1241 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1242 {0x10, 0x0009000f}, {0x11, 0x00023100},
1243 {0x12, 0x00032000}, {0x12, 0x00071000},
1244 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1245 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1246 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1247 {0x13, 0x00018493}, {0x13, 0x0001429b},
1248 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1249 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1250 {0x13, 0x00000020}, {0x14, 0x0001944c},
1251 {0x14, 0x00059444}, {0x14, 0x0009944c},
1252 {0x14, 0x000d9444}, {0x15, 0x0000f474},
1253 {0x15, 0x0004f477}, {0x15, 0x0008f455},
1254 {0x15, 0x000cf455}, {0x16, 0x00000339},
1255 {0x16, 0x00040339}, {0x16, 0x00080339},
1256 {0x16, 0x000c0366}, {0x00, 0x00010159},
1257 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1258 {0xfe, 0x00000000}, {0x1f, 0x00000003},
1259 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1260 {0x1e, 0x00000247}, {0x1f, 0x00000000},
1261 {0x00, 0x00030159},
1262 {0xff, 0xffffffff}
1263};
1264
22a31d45
JS		 1265static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
1266 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
1267 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1268 {0xfe, 0x00000000}, {0xb1, 0x00000018},
1269 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1270 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
1271 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
1272 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
1273 {0x5c, 0x00000002}, {0x7c, 0x00000002},
1274 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
1275 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
1276 {0x1e, 0x00000000}, {0xdf, 0x00000780},
1277 {0x50, 0x00067435},
1278 /*
1279 * The 8723bu vendor driver indicates that bit 8 should be set in
1280 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
1281 * they never actually check the package type - and just default
1282 * to not setting it.
1283 */
1284 {0x51, 0x0006b04e},
1285 {0x52, 0x000007d2}, {0x53, 0x00000000},
1286 {0x54, 0x00050400}, {0x55, 0x0004026e},
1287 {0xdd, 0x0000004c}, {0x70, 0x00067435},
1288 /*
1289 * 0x71 has same package type condition as for register 0x51
1290 */
1291 {0x71, 0x0006b04e},
1292 {0x72, 0x000007d2}, {0x73, 0x00000000},
1293 {0x74, 0x00050400}, {0x75, 0x0004026e},
1294 {0xef, 0x00000100}, {0x34, 0x0000add7},
1295 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
1296 {0x35, 0x00005000}, {0x34, 0x00008dd1},
1297 {0x35, 0x00004400}, {0x34, 0x00007dce},
1298 {0x35, 0x00003800}, {0x34, 0x00006cd1},
1299 {0x35, 0x00004400}, {0x34, 0x00005cce},
1300 {0x35, 0x00003800}, {0x34, 0x000048ce},
1301 {0x35, 0x00004400}, {0x34, 0x000034ce},
1302 {0x35, 0x00003800}, {0x34, 0x00002451},
1303 {0x35, 0x00004400}, {0x34, 0x0000144e},
1304 {0x35, 0x00003800}, {0x34, 0x00000051},
1305 {0x35, 0x00004400}, {0xef, 0x00000000},
1306 {0xef, 0x00000100}, {0xed, 0x00000010},
1307 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
1308 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
1309 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
1310 {0x44, 0x000044d1}, {0x44, 0x000034ce},
1311 {0x44, 0x00002451}, {0x44, 0x0000144e},
1312 {0x44, 0x00000051}, {0xef, 0x00000000},
1313 {0xed, 0x00000000}, {0x7f, 0x00020080},
1314 {0xef, 0x00002000}, {0x3b, 0x000380ef},
1315 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
1316 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
1317 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
1318 {0x3b, 0x00000900}, {0xef, 0x00000000},
1319 {0xed, 0x00000001}, {0x40, 0x000380ef},
1320 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
1321 {0x40, 0x000200bc}, {0x40, 0x000188a5},
1322 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
1323 {0x40, 0x00000900}, {0xed, 0x00000000},
1324 {0x82, 0x00080000}, {0x83, 0x00008000},
1325 {0x84, 0x00048d80}, {0x85, 0x00068000},
1326 {0xa2, 0x00080000}, {0xa3, 0x00008000},
1327 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
1328 {0xed, 0x00000002}, {0xef, 0x00000002},
1329 {0x56, 0x00000032}, {0x76, 0x00000032},
1330 {0x01, 0x00000780},
1331 {0xff, 0xffffffff}
1332};
1333
06d05463 1334#ifdef CONFIG_RTL8XXXU_UNTESTED
26f1fad2
JS		 1335static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
1336 {0x00, 0x00030159}, {0x01, 0x00031284},
1337 {0x02, 0x00098000}, {0x03, 0x00018c63},
1338 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1339 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1340 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1341 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1342 {0x19, 0x00000000}, {0x1a, 0x00010255},
1343 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1344 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1345 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1346 {0x21, 0x0006c000}, {0x22, 0x00000000},
1347 {0x23, 0x00001558}, {0x24, 0x00000060},
1348 {0x25, 0x00000483}, {0x26, 0x0004f000},
1349 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1350 {0x29, 0x00004783}, {0x2a, 0x00000001},
1351 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1352 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1353 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1354 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1355 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1356 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1357 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1358 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1359 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1360 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1361 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1362 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1363 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1364 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1365 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1366 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1367 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1368 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1369 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1370 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1371 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1372 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1373 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1374 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1375 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1376 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1377 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1378 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1379 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1380 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1381 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1382 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1383 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1384 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1385 {0x10, 0x00000000}, {0x11, 0x00000000},
1386 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1387 {0x10, 0x0009000f}, {0x11, 0x00023100},
1388 {0x12, 0x00032000}, {0x12, 0x00071000},
1389 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1390 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1391 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1392 {0x13, 0x00018493}, {0x13, 0x0001429b},
1393 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1394 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1395 {0x13, 0x00000020}, {0x14, 0x0001944c},
1396 {0x14, 0x00059444}, {0x14, 0x0009944c},
1397 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1398 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1399 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1400 {0x16, 0x000a0330}, {0x16, 0x00060330},
1401 {0x16, 0x00020330}, {0x00, 0x00010159},
1402 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1403 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1404 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1405 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1406 {0x00, 0x00030159},
1407 {0xff, 0xffffffff}
1408};
1409
1410static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1411 {0x00, 0x00030159}, {0x01, 0x00031284},
1412 {0x02, 0x00098000}, {0x03, 0x00018c63},
1413 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1414 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1415 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1416 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1417 {0x12, 0x00032000}, {0x12, 0x00071000},
1418 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1419 {0x13, 0x000287af}, {0x13, 0x000244b7},
1420 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1421 {0x13, 0x00018493}, {0x13, 0x00014297},
1422 {0x13, 0x00010295}, {0x13, 0x0000c298},
1423 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1424 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1425 {0x14, 0x00059444}, {0x14, 0x0009944c},
1426 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1427 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1428 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1429 {0x16, 0x000a0330}, {0x16, 0x00060330},
1430 {0x16, 0x00020330},
1431 {0xff, 0xffffffff}
1432};
1433
1434static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1435 {0x00, 0x00030159}, {0x01, 0x00031284},
1436 {0x02, 0x00098000}, {0x03, 0x00018c63},
1437 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1438 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1439 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1440 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1441 {0x19, 0x00000000}, {0x1a, 0x00010255},
1442 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1443 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1444 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1445 {0x21, 0x0006c000}, {0x22, 0x00000000},
1446 {0x23, 0x00001558}, {0x24, 0x00000060},
1447 {0x25, 0x00000483}, {0x26, 0x0004f000},
1448 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1449 {0x29, 0x00004783}, {0x2a, 0x00000001},
1450 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1451 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1452 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1453 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1454 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1455 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1456 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1457 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1458 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1459 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1460 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1461 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1462 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1463 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1464 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1465 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1466 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1467 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1468 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1469 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1470 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1471 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1472 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1473 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1474 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1475 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1476 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1477 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1478 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1479 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1480 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1481 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1482 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1483 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1484 {0x10, 0x00000000}, {0x11, 0x00000000},
1485 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1486 {0x10, 0x0009000f}, {0x11, 0x00023100},
1487 {0x12, 0x00032000}, {0x12, 0x00071000},
1488 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1489 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1490 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1491 {0x13, 0x00018493}, {0x13, 0x0001429b},
1492 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1493 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1494 {0x13, 0x00000020}, {0x14, 0x0001944c},
1495 {0x14, 0x00059444}, {0x14, 0x0009944c},
1496 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1497 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1498 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1499 {0x16, 0x000a0330}, {0x16, 0x00060330},
1500 {0x16, 0x00020330}, {0x00, 0x00010159},
1501 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1502 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1503 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1504 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1505 {0x00, 0x00030159},
1506 {0xff, 0xffffffff}
1507};
1508
1509static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1510 {0x00, 0x00030159}, {0x01, 0x00031284},
1511 {0x02, 0x00098000}, {0x03, 0x00018c63},
1512 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1513 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1514 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1515 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1516 {0x19, 0x00000000}, {0x1a, 0x00000255},
1517 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1518 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1519 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1520 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1521 {0x23, 0x00001558}, {0x24, 0x00000060},
1522 {0x25, 0x00000483}, {0x26, 0x0004f000},
1523 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1524 {0x29, 0x00004783}, {0x2a, 0x00000001},
1525 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1526 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1527 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1528 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1529 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1530 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1531 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1532 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1533 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1534 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1535 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1536 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1537 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1538 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1539 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1540 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1541 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1542 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1543 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1544 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1545 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1546 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1547 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1548 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1549 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1550 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1551 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1552 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1553 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1554 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1555 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1556 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1557 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1558 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1559 {0x10, 0x00000000}, {0x11, 0x00000000},
1560 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1561 {0x10, 0x0009000f}, {0x11, 0x00023100},
1562 {0x12, 0x000d8000}, {0x12, 0x00090000},
1563 {0x12, 0x00051000}, {0x12, 0x00012000},
1564 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1565 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1566 {0x13, 0x000183a4}, {0x13, 0x00014398},
1567 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1568 {0x13, 0x000080a4}, {0x13, 0x00004098},
1569 {0x13, 0x00000000}, {0x14, 0x0001944c},
1570 {0x14, 0x00059444}, {0x14, 0x0009944c},
1571 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1572 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1573 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1574 {0x16, 0x000a0330}, {0x16, 0x00060330},
1575 {0x16, 0x00020330}, {0x00, 0x00010159},
1576 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1577 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1578 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1579 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1580 {0x00, 0x00030159},
1581 {0xff, 0xffffffff}
1582};
06d05463 1583#endif
26f1fad2 1584
19102f84
JS		 1585static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
1586 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1587 {0x00, 0x00030000}, {0x08, 0x00008400},
1588 {0x18, 0x00000407}, {0x19, 0x00000012},
1589 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1590 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1591 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1592 {0x57, 0x000d0000}, {0x58, 0x000be180},
1593 {0x67, 0x00001552}, {0x83, 0x00000000},
1594 {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
1595 {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
1596 {0xb5, 0x00008166}, {0xb6, 0x0000803e},
1597 {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
1598 {0xb9, 0x00080001}, {0xba, 0x00040001},
1599 {0xbb, 0x00000400}, {0xbf, 0x000c0000},
1600 {0xc2, 0x00002400}, {0xc3, 0x00000009},
1601 {0xc4, 0x00040c91}, {0xc5, 0x00099999},
1602 {0xc6, 0x000000a3}, {0xc7, 0x00088820},
1603 {0xc8, 0x00076c06}, {0xc9, 0x00000000},
1604 {0xca, 0x00080000}, {0xdf, 0x00000180},
1605 {0xef, 0x000001a0}, {0x51, 0x00069545},
1606 {0x52, 0x0007e45e}, {0x53, 0x00000071},
1607 {0x56, 0x00051ff3}, {0x35, 0x000000a8},
1608 {0x35, 0x000001e2}, {0x35, 0x000002a8},
1609 {0x36, 0x00001c24}, {0x36, 0x00009c24},
1610 {0x36, 0x00011c24}, {0x36, 0x00019c24},
1611 {0x18, 0x00000c07}, {0x5a, 0x00048000},
1612 {0x19, 0x000739d0},
1613#ifdef EXT_PA_8192EU
1614 /* External PA or external LNA */
1615 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1616 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1617 {0x34, 0x0000604a}, {0x34, 0x00005047},
1618 {0x34, 0x0000400a}, {0x34, 0x00003007},
1619 {0x34, 0x00002004}, {0x34, 0x00001001},
1620 {0x34, 0x00000000},
1621#else
1622 /* Regular */
1623 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1624 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1625 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1626 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1627 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1628 {0x34, 0x00000014},
1629#endif
1630 {0x00, 0x00030159},
1631 {0x84, 0x00068180},
1632 {0x86, 0x0000014e},
1633 {0x87, 0x00048e00},
1634 {0x8e, 0x00065540},
1635 {0x8f, 0x00088000},
1636 {0xef, 0x000020a0},
1637#ifdef EXT_PA_8192EU
1638 /* External PA or external LNA */
1639 {0x3b, 0x000f07b0},
1640#else
1641 {0x3b, 0x000f02b0},
1642#endif
1643 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1644 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1645 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1646 {0x3b, 0x0008f780},
1647#ifdef EXT_PA_8192EU
1648 /* External PA or external LNA */
1649 {0x3b, 0x000787b0},
1650#else
1651 {0x3b, 0x00078730},
1652#endif
1653 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1654 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1655 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1656 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1657 {0xfe, 0x00000000}, {0x18, 0x0000fc07},
1658 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1659 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1660 {0x1e, 0x00000001}, {0x1f, 0x00080000},
1661 {0x00, 0x00033e70},
1662 {0xff, 0xffffffff}
1663};
1664
1665static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
1666 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1667 {0x00, 0x00030000}, {0x08, 0x00008400},
1668 {0x18, 0x00000407}, {0x19, 0x00000012},
1669 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1670 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1671 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1672 {0x57, 0x000d0000}, {0x58, 0x000be180},
1673 {0x67, 0x00001552}, {0x7f, 0x00000082},
1674 {0x81, 0x0003f000}, {0x83, 0x00000000},
1675 {0xdf, 0x00000180}, {0xef, 0x000001a0},
1676 {0x51, 0x00069545}, {0x52, 0x0007e42e},
1677 {0x53, 0x00000071}, {0x56, 0x00051ff3},
1678 {0x35, 0x000000a8}, {0x35, 0x000001e0},
1679 {0x35, 0x000002a8}, {0x36, 0x00001ca8},
1680 {0x36, 0x00009c24}, {0x36, 0x00011c24},
1681 {0x36, 0x00019c24}, {0x18, 0x00000c07},
1682 {0x5a, 0x00048000}, {0x19, 0x000739d0},
1683#ifdef EXT_PA_8192EU
1684 /* External PA or external LNA */
1685 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1686 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1687 {0x34, 0x0000604a}, {0x34, 0x00005047},
1688 {0x34, 0x0000400a}, {0x34, 0x00003007},
1689 {0x34, 0x00002004}, {0x34, 0x00001001},
1690 {0x34, 0x00000000},
1691#else
1692 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1693 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1694 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1695 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1696 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1697 {0x34, 0x00000014},
1698#endif
1699 {0x00, 0x00030159}, {0x84, 0x00068180},
1700 {0x86, 0x000000ce}, {0x87, 0x00048a00},
1701 {0x8e, 0x00065540}, {0x8f, 0x00088000},
1702 {0xef, 0x000020a0},
1703#ifdef EXT_PA_8192EU
1704 /* External PA or external LNA */
1705 {0x3b, 0x000f07b0},
1706#else
1707 {0x3b, 0x000f02b0},
1708#endif
1709
1710 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1711 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1712 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1713 {0x3b, 0x0008f780},
1714#ifdef EXT_PA_8192EU
1715 /* External PA or external LNA */
1716 {0x3b, 0x000787b0},
1717#else
1718 {0x3b, 0x00078730},
1719#endif
1720 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1721 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1722 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1723 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1724 {0x00, 0x00010159}, {0xfe, 0x00000000},
1725 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1726 {0xfe, 0x00000000}, {0x1e, 0x00000001},
1727 {0x1f, 0x00080000}, {0x00, 0x00033e70},
1728 {0xff, 0xffffffff}
1729};
1730
26f1fad2
JS		 1731static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1732 { /* RF_A */
1733 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1734 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1735 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1736 .hspiread = REG_HSPI_XA_READBACK,
1737 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1738 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1739 },
1740 { /* RF_B */
1741 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1742 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1743 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1744 .hspiread = REG_HSPI_XB_READBACK,
1745 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1746 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1747 },
1748};
1749
04a74a9f 1750static const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
26f1fad2
JS		 1751 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1752 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1753 REG_OFDM0_ENERGY_CCA_THRES,
1754 REG_OFDM0_AGCR_SSI_TABLE,
1755 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1756 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1757 REG_OFDM0_XC_TX_AFE,
1758 REG_OFDM0_XD_TX_AFE,
1759 REG_OFDM0_RX_IQ_EXT_ANTA
1760};
1761
1762static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1763{
1764 struct usb_device *udev = priv->udev;
1765 int len;
1766 u8 data;
1767
1768 mutex_lock(&priv->usb_buf_mutex);
1769 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1770 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1771 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1772 RTW_USB_CONTROL_MSG_TIMEOUT);
1773 data = priv->usb_buf.val8;
1774 mutex_unlock(&priv->usb_buf_mutex);
1775
1776 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1777 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1778 __func__, addr, data, len);
1779 return data;
1780}
1781
1782static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1783{
1784 struct usb_device *udev = priv->udev;
1785 int len;
1786 u16 data;
1787
1788 mutex_lock(&priv->usb_buf_mutex);
1789 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1790 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1791 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1792 RTW_USB_CONTROL_MSG_TIMEOUT);
1793 data = le16_to_cpu(priv->usb_buf.val16);
1794 mutex_unlock(&priv->usb_buf_mutex);
1795
1796 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1797 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1798 __func__, addr, data, len);
1799 return data;
1800}
1801
1802static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1803{
1804 struct usb_device *udev = priv->udev;
1805 int len;
1806 u32 data;
1807
1808 mutex_lock(&priv->usb_buf_mutex);
1809 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1810 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1811 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1812 RTW_USB_CONTROL_MSG_TIMEOUT);
1813 data = le32_to_cpu(priv->usb_buf.val32);
1814 mutex_unlock(&priv->usb_buf_mutex);
1815
1816 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1817 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1818 __func__, addr, data, len);
1819 return data;
1820}
1821
1822static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1823{
1824 struct usb_device *udev = priv->udev;
1825 int ret;
1826
1827 mutex_lock(&priv->usb_buf_mutex);
1828 priv->usb_buf.val8 = val;
1829 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1830 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1831 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1832 RTW_USB_CONTROL_MSG_TIMEOUT);
1833
1834 mutex_unlock(&priv->usb_buf_mutex);
1835
1836 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1837 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1838 __func__, addr, val);
1839 return ret;
1840}
1841
1842static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1843{
1844 struct usb_device *udev = priv->udev;
1845 int ret;
1846
1847 mutex_lock(&priv->usb_buf_mutex);
1848 priv->usb_buf.val16 = cpu_to_le16(val);
1849 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1850 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1851 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1852 RTW_USB_CONTROL_MSG_TIMEOUT);
1853 mutex_unlock(&priv->usb_buf_mutex);
1854
1855 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1856 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1857 __func__, addr, val);
1858 return ret;
1859}
1860
1861static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1862{
1863 struct usb_device *udev = priv->udev;
1864 int ret;
1865
1866 mutex_lock(&priv->usb_buf_mutex);
1867 priv->usb_buf.val32 = cpu_to_le32(val);
1868 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1869 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1870 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1871 RTW_USB_CONTROL_MSG_TIMEOUT);
1872 mutex_unlock(&priv->usb_buf_mutex);
1873
1874 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1875 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1876 __func__, addr, val);
1877 return ret;
1878}
1879
1880static int
1881rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1882{
1883 struct usb_device *udev = priv->udev;
1884 int blocksize = priv->fops->writeN_block_size;
1885 int ret, i, count, remainder;
1886
1887 count = len / blocksize;
1888 remainder = len % blocksize;
1889
1890 for (i = 0; i < count; i++) {
1891 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1892 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1893 addr, 0, buf, blocksize,
1894 RTW_USB_CONTROL_MSG_TIMEOUT);
1895 if (ret != blocksize)
1896 goto write_error;
1897
1898 addr += blocksize;
1899 buf += blocksize;
1900 }
1901
1902 if (remainder) {
1903 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1904 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1905 addr, 0, buf, remainder,
1906 RTW_USB_CONTROL_MSG_TIMEOUT);
1907 if (ret != remainder)
1908 goto write_error;
1909 }
1910
1911 return len;
1912
1913write_error:
1914 dev_info(&udev->dev,
1915 "%s: Failed to write block at addr: %04x size: %04x\n",
1916 __func__, addr, blocksize);
1917 return -EAGAIN;
1918}
1919
1920static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1921 enum rtl8xxxu_rfpath path, u8 reg)
1922{
1923 u32 hssia, val32, retval;
1924
1925 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1926 if (path != RF_A)
1927 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1928 else
1929 val32 = hssia;
1930
1931 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1932 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1933 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1934 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1935 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1936
1937 udelay(10);
1938
1939 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1940 udelay(100);
1941
1942 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1943 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1944 udelay(10);
1945
1946 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1947 if (val32 & FPGA0_HSSI_PARM1_PI)
1948 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1949 else
1950 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1951
1952 retval &= 0xfffff;
1953
1954 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1955 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1956 __func__, reg, retval);
1957 return retval;
1958}
1959
22a31d45
JS		 1960/*
1961 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1962 * have write issues in high temperature conditions. We may have to
1963 * retry writing them.
1964 */
26f1fad2
JS		 1965static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1966 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1967{
1968 int ret, retval;
2949b9ee 1969 u32 dataaddr, val32;
26f1fad2
JS		 1970
1971 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1972 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1973 __func__, reg, data);
1974
1975 data &= FPGA0_LSSI_PARM_DATA_MASK;
1976 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1977
2949b9ee
JS		 1978 if (priv->rtl_chip == RTL8192E) {
1979 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1980 val32 &= ~0x20000;
1981 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1982 }
1983
26f1fad2
JS		 1984 /* Use XB for path B */
1985 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1986 if (ret != sizeof(dataaddr))
1987 retval = -EIO;
1988 else
1989 retval = 0;
1990
1991 udelay(1);
1992
2949b9ee
JS		 1993 if (priv->rtl_chip == RTL8192E) {
1994 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1995 val32 |= 0x20000;
1996 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1997 }
1998
26f1fad2
JS		 1999 return retval;
2000}
2001
8da91571
JS		 2002static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
2003 struct h2c_cmd *h2c, int len)
26f1fad2
JS		 2004{
2005 struct device *dev = &priv->udev->dev;
2006 int mbox_nr, retry, retval = 0;
2007 int mbox_reg, mbox_ext_reg;
2008 u8 val8;
2009
2010 mutex_lock(&priv->h2c_mutex);
2011
2012 mbox_nr = priv->next_mbox;
2013 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
ed35d094
JS		 2014 mbox_ext_reg = priv->fops->mbox_ext_reg +
2015 (mbox_nr * priv->fops->mbox_ext_width);
26f1fad2
JS		 2016
2017 /*
2018 * MBOX ready?
2019 */
2020 retry = 100;
2021 do {
2022 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
2023 if (!(val8 & BIT(mbox_nr)))
2024 break;
2025 } while (retry--);
2026
2027 if (!retry) {
c7a5a190 2028 dev_info(dev, "%s: Mailbox busy\n", __func__);
26f1fad2
JS		 2029 retval = -EBUSY;
2030 goto error;
2031 }
2032
2033 /*
2034 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
2035 */
8da91571 2036 if (len > sizeof(u32)) {
ed35d094
JS		 2037 if (priv->fops->mbox_ext_width == 4) {
2038 rtl8xxxu_write32(priv, mbox_ext_reg,
2039 le32_to_cpu(h2c->raw_wide.ext));
2040 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
2041 dev_info(dev, "H2C_EXT %08x\n",
2042 le32_to_cpu(h2c->raw_wide.ext));
2043 } else {
2044 rtl8xxxu_write16(priv, mbox_ext_reg,
2045 le16_to_cpu(h2c->raw.ext));
2046 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
2047 dev_info(dev, "H2C_EXT %04x\n",
2048 le16_to_cpu(h2c->raw.ext));
2049 }
26f1fad2
JS		 2050 }
2051 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
2052 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
2053 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
2054
2055 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
2056
2057error:
2058 mutex_unlock(&priv->h2c_mutex);
2059 return retval;
2060}
2061
394f1bd3
JS		 2062static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
2063{
2064 struct h2c_cmd h2c;
2065 int reqnum = 0;
2066
2067 memset(&h2c, 0, sizeof(struct h2c_cmd));
2068 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
2069 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
2070 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
2071 h2c.bt_mp_oper.data = data;
2072 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
2073
2074 reqnum++;
2075 memset(&h2c, 0, sizeof(struct h2c_cmd));
2076 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
2077 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
2078 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
2079 h2c.bt_mp_oper.addr = reg;
2080 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
2081}
2082
8396a41c 2083static void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 2084{
2085 u8 val8;
2086 u32 val32;
2087
2088 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
2089 val8 |= BIT(0) | BIT(3);
2090 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
2091
2092 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
2093 val32 &= ~(BIT(4) | BIT(5));
2094 val32 |= BIT(3);
2095 if (priv->rf_paths == 2) {
2096 val32 &= ~(BIT(20) | BIT(21));
2097 val32 |= BIT(19);
2098 }
2099 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
2100
2101 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2102 val32 &= ~OFDM_RF_PATH_TX_MASK;
2103 if (priv->tx_paths == 2)
2104 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
ba17d824 2105 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
26f1fad2
JS		 2106 val32 |= OFDM_RF_PATH_TX_B;
2107 else
2108 val32 |= OFDM_RF_PATH_TX_A;
2109 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2110
2111 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2112 val32 &= ~FPGA_RF_MODE_JAPAN;
2113 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2114
2115 if (priv->rf_paths == 2)
2116 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
2117 else
2118 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
2119
2120 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
2121 if (priv->rf_paths == 2)
2122 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
2123
2124 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
2125}
2126
7eb1400c 2127static void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 2128{
2129 u8 sps0;
2130 u32 val32;
2131
26f1fad2
JS		 2132 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
2133
2134 /* RF RX code for preamble power saving */
2135 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
2136 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
2137 if (priv->rf_paths == 2)
2138 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
2139 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
2140
2141 /* Disable TX for four paths */
2142 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2143 val32 &= ~OFDM_RF_PATH_TX_MASK;
2144 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2145
2146 /* Enable power saving */
2147 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2148 val32 |= FPGA_RF_MODE_JAPAN;
2149 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2150
2151 /* AFE control register to power down bits [30:22] */
2152 if (priv->rf_paths == 2)
2153 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
2154 else
2155 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
2156
2157 /* Power down RF module */
2158 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
2159 if (priv->rf_paths == 2)
2160 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
2161
2162 sps0 &= ~(BIT(0) | BIT(3));
2163 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
2164}
2165
2166
2167static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
2168{
2169 u8 val8;
2170
2171 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
2172 val8 &= ~BIT(6);
2173 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
2174
2175 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
2176 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
2177 val8 &= ~BIT(0);
2178 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
2179}
2180
2181
2182/*
2183 * The rtl8723a has 3 channel groups for it's efuse settings. It only
2184 * supports the 2.4GHz band, so channels 1 - 14:
2185 * group 0: channels 1 - 3
2186 * group 1: channels 4 - 9
2187 * group 2: channels 10 - 14
2188 *
2189 * Note: We index from 0 in the code
2190 */
2191static int rtl8723a_channel_to_group(int channel)
2192{
2193 int group;
2194
2195 if (channel < 4)
2196 group = 0;
2197 else if (channel < 10)
2198 group = 1;
2199 else
2200 group = 2;
2201
2202 return group;
2203}
2204
9e24772a
JS		 2205/*
2206 * Valid for rtl8723bu and rtl8192eu
2207 */
5ac74145 2208static int rtl8xxxu_gen2_channel_to_group(int channel)
e796dab4
JS		 2209{
2210 int group;
2211
2212 if (channel < 3)
2213 group = 0;
2214 else if (channel < 6)
2215 group = 1;
2216 else if (channel < 9)
2217 group = 2;
2218 else if (channel < 12)
2219 group = 3;
2220 else
2221 group = 4;
2222
2223 return group;
2224}
2225
e09718c2 2226static void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
26f1fad2
JS		 2227{
2228 struct rtl8xxxu_priv *priv = hw->priv;
2229 u32 val32, rsr;
2230 u8 val8, opmode;
2231 bool ht = true;
2232 int sec_ch_above, channel;
2233 int i;
2234
2235 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
2236 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
2237 channel = hw->conf.chandef.chan->hw_value;
2238
2239 switch (hw->conf.chandef.width) {
2240 case NL80211_CHAN_WIDTH_20_NOHT:
2241 ht = false;
2242 case NL80211_CHAN_WIDTH_20:
2243 opmode |= BW_OPMODE_20MHZ;
2244 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
2245
2246 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2247 val32 &= ~FPGA_RF_MODE;
2248 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2249
2250 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2251 val32 &= ~FPGA_RF_MODE;
2252 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2253
2254 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
2255 val32 |= FPGA0_ANALOG2_20MHZ;
2256 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
2257 break;
2258 case NL80211_CHAN_WIDTH_40:
2259 if (hw->conf.chandef.center_freq1 >
2260 hw->conf.chandef.chan->center_freq) {
2261 sec_ch_above = 1;
2262 channel += 2;
2263 } else {
2264 sec_ch_above = 0;
2265 channel -= 2;
2266 }
2267
2268 opmode &= ~BW_OPMODE_20MHZ;
2269 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
2270 rsr &= ~RSR_RSC_BANDWIDTH_40M;
2271 if (sec_ch_above)
2272 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
2273 else
2274 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
2275 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
2276
2277 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2278 val32 |= FPGA_RF_MODE;
2279 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2280
2281 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2282 val32 |= FPGA_RF_MODE;
2283 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2284
2285 /*
2286 * Set Control channel to upper or lower. These settings
2287 * are required only for 40MHz
2288 */
2289 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
2290 val32 &= ~CCK0_SIDEBAND;
2291 if (!sec_ch_above)
2292 val32 |= CCK0_SIDEBAND;
2293 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
2294
2295 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
2296 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
2297 if (sec_ch_above)
2298 val32 |= OFDM_LSTF_PRIME_CH_LOW;
2299 else
2300 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
2301 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
2302
2303 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
2304 val32 &= ~FPGA0_ANALOG2_20MHZ;
2305 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
2306
2307 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
2308 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
2309 if (sec_ch_above)
2310 val32 |= FPGA0_PS_UPPER_CHANNEL;
2311 else
2312 val32 |= FPGA0_PS_LOWER_CHANNEL;
2313 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
2314 break;
2315
2316 default:
2317 break;
2318 }
2319
2320 for (i = RF_A; i < priv->rf_paths; i++) {
2321 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2322 val32 &= ~MODE_AG_CHANNEL_MASK;
2323 val32 |= channel;
2324 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2325 }
2326
2327 if (ht)
2328 val8 = 0x0e;
2329 else
2330 val8 = 0x0a;
2331
2332 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
2333 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
2334
2335 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
2336 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
2337
2338 for (i = RF_A; i < priv->rf_paths; i++) {
2339 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2340 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
2341 val32 &= ~MODE_AG_CHANNEL_20MHZ;
2342 else
2343 val32 |= MODE_AG_CHANNEL_20MHZ;
2344 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2345 }
2346}
2347
3a56bf6a 2348static void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
c3f9506f
JS		 2349{
2350 struct rtl8xxxu_priv *priv = hw->priv;
2351 u32 val32, rsr;
368633ce 2352 u8 val8, subchannel;
c3f9506f
JS		 2353 u16 rf_mode_bw;
2354 bool ht = true;
2355 int sec_ch_above, channel;
2356 int i;
2357
2358 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
2359 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
2360 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
2361 channel = hw->conf.chandef.chan->hw_value;
2362
2363/* Hack */
2364 subchannel = 0;
2365
2366 switch (hw->conf.chandef.width) {
2367 case NL80211_CHAN_WIDTH_20_NOHT:
2368 ht = false;
2369 case NL80211_CHAN_WIDTH_20:
2370 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
2371 subchannel = 0;
2372
2373 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2374 val32 &= ~FPGA_RF_MODE;
2375 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2376
2377 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2378 val32 &= ~FPGA_RF_MODE;
2379 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2380
2381 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
2382 val32 &= ~(BIT(30) | BIT(31));
2383 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
2384
2385 break;
2386 case NL80211_CHAN_WIDTH_40:
2387 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
2388
2389 if (hw->conf.chandef.center_freq1 >
2390 hw->conf.chandef.chan->center_freq) {
2391 sec_ch_above = 1;
2392 channel += 2;
2393 } else {
2394 sec_ch_above = 0;
2395 channel -= 2;
2396 }
2397
2398 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2399 val32 |= FPGA_RF_MODE;
2400 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2401
2402 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2403 val32 |= FPGA_RF_MODE;
2404 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2405
2406 /*
2407 * Set Control channel to upper or lower. These settings
2408 * are required only for 40MHz
2409 */
2410 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
2411 val32 &= ~CCK0_SIDEBAND;
2412 if (!sec_ch_above)
2413 val32 |= CCK0_SIDEBAND;
2414 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
2415
2416 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
2417 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
2418 if (sec_ch_above)
2419 val32 |= OFDM_LSTF_PRIME_CH_LOW;
2420 else
2421 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
2422 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
2423
2424 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
2425 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
2426 if (sec_ch_above)
2427 val32 |= FPGA0_PS_UPPER_CHANNEL;
2428 else
2429 val32 |= FPGA0_PS_LOWER_CHANNEL;
2430 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
2431 break;
2432 case NL80211_CHAN_WIDTH_80:
2433 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
2434 break;
2435 default:
2436 break;
2437 }
2438
2439 for (i = RF_A; i < priv->rf_paths; i++) {
2440 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2441 val32 &= ~MODE_AG_CHANNEL_MASK;
2442 val32 |= channel;
2443 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2444 }
2445
2446 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
2447 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
2448
2449 if (ht)
2450 val8 = 0x0e;
2451 else
2452 val8 = 0x0a;
2453
2454 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
2455 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
2456
2457 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
2458 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
2459
2460 for (i = RF_A; i < priv->rf_paths; i++) {
2461 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2462 val32 &= ~MODE_AG_BW_MASK;
2463 switch(hw->conf.chandef.width) {
2464 case NL80211_CHAN_WIDTH_80:
2465 val32 |= MODE_AG_BW_80MHZ_8723B;
2466 break;
2467 case NL80211_CHAN_WIDTH_40:
2468 val32 |= MODE_AG_BW_40MHZ_8723B;
2469 break;
2470 default:
2471 val32 |= MODE_AG_BW_20MHZ_8723B;
2472 break;
2473 }
2474 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2475 }
2476}
2477
26f1fad2 2478static void
42a3bc7a 2479rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
26f1fad2 2480{
2fc0b8e5 2481 struct rtl8xxxu_power_base *power_base = priv->power_base;
26f1fad2
JS		 2482 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
2483 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
2484 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
2485 u8 val8;
2486 int group, i;
2487
2488 group = rtl8723a_channel_to_group(channel);
2489
2fc0b8e5
JS		 2490 cck[0] = priv->cck_tx_power_index_A[group] - 1;
2491 cck[1] = priv->cck_tx_power_index_B[group] - 1;
26f1fad2 2492
b591e982
JS		 2493 if (priv->hi_pa) {
2494 if (cck[0] > 0x20)
2495 cck[0] = 0x20;
2496 if (cck[1] > 0x20)
2497 cck[1] = 0x20;
2498 }
2499
26f1fad2
JS		 2500 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
2501 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
2fc0b8e5
JS		 2502 if (ofdm[0])
2503 ofdm[0] -= 1;
2504 if (ofdm[1])
2505 ofdm[1] -= 1;
26f1fad2
JS		 2506
2507 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
2508 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
2509
2510 mcsbase[0] = ofdm[0];
2511 mcsbase[1] = ofdm[1];
2512 if (!ht40) {
2513 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
2514 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
2515 }
2516
2517 if (priv->tx_paths > 1) {
2518 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
2519 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
2520 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
2521 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
2522 }
2523
2524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
2525 dev_info(&priv->udev->dev,
2526 "%s: Setting TX power CCK A: %02x, "
2527 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
2528 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
2529
2530 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
2531 if (cck[i] > RF6052_MAX_TX_PWR)
2532 cck[i] = RF6052_MAX_TX_PWR;
2533 if (ofdm[i] > RF6052_MAX_TX_PWR)
2534 ofdm[i] = RF6052_MAX_TX_PWR;
2535 }
2536
2537 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2538 val32 &= 0xffff00ff;
2539 val32 |= (cck[0] << 8);
2540 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2541
2542 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2543 val32 &= 0xff;
2544 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2545 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2546
2547 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2548 val32 &= 0xffffff00;
2549 val32 |= cck[1];
2550 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2551
2552 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2553 val32 &= 0xff;
2554 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2555 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2556
2557 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2558 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2559 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2560 ofdmbase[1] << 16 | ofdmbase[1] << 24;
26f1fad2 2561
2fc0b8e5
JS		 2562 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
2563 ofdm_a + power_base->reg_0e00);
2564 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
2565 ofdm_b + power_base->reg_0830);
2566
2567 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
2568 ofdm_a + power_base->reg_0e04);
2569 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
2570 ofdm_b + power_base->reg_0834);
26f1fad2
JS		 2571
2572 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2573 mcsbase[0] << 16 | mcsbase[0] << 24;
2574 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2575 mcsbase[1] << 16 | mcsbase[1] << 24;
2576
2fc0b8e5
JS		 2577 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
2578 mcs_a + power_base->reg_0e10);
2579 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
2580 mcs_b + power_base->reg_083c);
26f1fad2 2581
2fc0b8e5
JS		 2582 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
2583 mcs_a + power_base->reg_0e14);
2584 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
2585 mcs_b + power_base->reg_0848);
26f1fad2 2586
2fc0b8e5
JS		 2587 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
2588 mcs_a + power_base->reg_0e18);
2589 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
2590 mcs_b + power_base->reg_084c);
26f1fad2 2591
2fc0b8e5
JS		 2592 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
2593 mcs_a + power_base->reg_0e1c);
26f1fad2
JS		 2594 for (i = 0; i < 3; i++) {
2595 if (i != 2)
2596 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2597 else
2598 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2599 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2600 }
2fc0b8e5
JS		 2601 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
2602 mcs_b + power_base->reg_0868);
26f1fad2
JS		 2603 for (i = 0; i < 3; i++) {
2604 if (i != 2)
2605 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2606 else
2607 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2608 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2609 }
2610}
2611
e796dab4
JS		 2612static void
2613rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2614{
1d3cc44d
JS		 2615 u32 val32, ofdm, mcs;
2616 u8 cck, ofdmbase, mcsbase;
54bed43f 2617 int group, tx_idx;
e796dab4 2618
54bed43f 2619 tx_idx = 0;
5ac74145 2620 group = rtl8xxxu_gen2_channel_to_group(channel);
54bed43f
JS		 2621
2622 cck = priv->cck_tx_power_index_B[group];
2623 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2624 val32 &= 0xffff00ff;
2625 val32 |= (cck << 8);
2626 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2627
2628 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2629 val32 &= 0xff;
2630 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2631 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2632
2633 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2634 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2635 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2636
2637 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2638 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
1d3cc44d
JS		 2639
2640 mcsbase = priv->ht40_1s_tx_power_index_B[group];
2641 if (ht40)
2642 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2643 else
2644 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2645 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2646
2647 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2648 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
e796dab4
JS		 2649}
2650
57e42a21
JS		 2651static void
2652rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2653{
2654 u32 val32, ofdm, mcs;
2655 u8 cck, ofdmbase, mcsbase;
2656 int group, tx_idx;
2657
2658 tx_idx = 0;
5ac74145 2659 group = rtl8xxxu_gen2_channel_to_group(channel);
57e42a21
JS		 2660
2661 cck = priv->cck_tx_power_index_A[group];
2662
2663 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2664 val32 &= 0xffff00ff;
2665 val32 |= (cck << 8);
2666 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2667
2668 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2669 val32 &= 0xff;
2670 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2671 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2672
2673 ofdmbase = priv->ht40_1s_tx_power_index_A[group];
2674 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
2675 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2676
2677 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2678 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
2679
2680 mcsbase = priv->ht40_1s_tx_power_index_A[group];
2681 if (ht40)
2682 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
2683 else
2684 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
2685 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2686
2687 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2688 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
2689 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
2690 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
2691
2692 if (priv->tx_paths > 1) {
2693 cck = priv->cck_tx_power_index_B[group];
2694
2695 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2696 val32 &= 0xff;
2697 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2698 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2699
2700 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2701 val32 &= 0xffffff00;
2702 val32 |= cck;
2703 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2704
2705 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2706 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2707 ofdm = ofdmbase | ofdmbase << 8 |
2708 ofdmbase << 16 | ofdmbase << 24;
2709
2710 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm);
2711 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm);
2712
2713 mcsbase = priv->ht40_1s_tx_power_index_B[group];
2714 if (ht40)
2715 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2716 else
2717 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2718 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2719
2720 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs);
2721 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs);
2722 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs);
2723 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs);
2724 }
2725}
2726
26f1fad2
JS		 2727static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2728 enum nl80211_iftype linktype)
2729{
a26703f3 2730 u8 val8;
26f1fad2 2731
a26703f3 2732 val8 = rtl8xxxu_read8(priv, REG_MSR);
26f1fad2
JS		 2733 val8 &= ~MSR_LINKTYPE_MASK;
2734
2735 switch (linktype) {
2736 case NL80211_IFTYPE_UNSPECIFIED:
2737 val8 |= MSR_LINKTYPE_NONE;
2738 break;
2739 case NL80211_IFTYPE_ADHOC:
2740 val8 |= MSR_LINKTYPE_ADHOC;
2741 break;
2742 case NL80211_IFTYPE_STATION:
2743 val8 |= MSR_LINKTYPE_STATION;
2744 break;
2745 case NL80211_IFTYPE_AP:
2746 val8 |= MSR_LINKTYPE_AP;
2747 break;
2748 default:
2749 goto out;
2750 }
2751
2752 rtl8xxxu_write8(priv, REG_MSR, val8);
2753out:
2754 return;
2755}
2756
2757static void
2758rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2759{
2760 u16 val16;
2761
2762 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2763 RETRY_LIMIT_SHORT_MASK) |
2764 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2765 RETRY_LIMIT_LONG_MASK);
2766
2767 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2768}
2769
2770static void
2771rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2772{
2773 u16 val16;
2774
2775 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2776 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2777
2778 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2779}
2780
2781static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2782{
2783 struct device *dev = &priv->udev->dev;
2784 char *cut;
2785
2786 switch (priv->chip_cut) {
2787 case 0:
2788 cut = "A";
2789 break;
2790 case 1:
2791 cut = "B";
2792 break;
0e5d435a
JS		 2793 case 2:
2794 cut = "C";
2795 break;
2796 case 3:
2797 cut = "D";
2798 break;
2799 case 4:
2800 cut = "E";
2801 break;
26f1fad2
JS		 2802 default:
2803 cut = "unknown";
2804 }
2805
2806 dev_info(dev,
2807 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
0e5d435a
JS		 2808 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2809 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2810 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
26f1fad2
JS		 2811
2812 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2813}
2814
2815static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2816{
2817 struct device *dev = &priv->udev->dev;
2818 u32 val32, bonding;
2819 u16 val16;
2820
2821 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2822 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2823 SYS_CFG_CHIP_VERSION_SHIFT;
2824 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2825 dev_info(dev, "Unsupported test chip\n");
2826 return -ENOTSUPP;
2827 }
2828
2829 if (val32 & SYS_CFG_BT_FUNC) {
35a741fe
JS		 2830 if (priv->chip_cut >= 3) {
2831 sprintf(priv->chip_name, "8723BU");
ba17d824 2832 priv->rtl_chip = RTL8723B;
35a741fe
JS		 2833 } else {
2834 sprintf(priv->chip_name, "8723AU");
0e28b975 2835 priv->usb_interrupts = 1;
ba17d824 2836 priv->rtl_chip = RTL8723A;
35a741fe
JS		 2837 }
2838
26f1fad2
JS		 2839 priv->rf_paths = 1;
2840 priv->rx_paths = 1;
2841 priv->tx_paths = 1;
26f1fad2
JS		 2842
2843 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2844 if (val32 & MULTI_WIFI_FUNC_EN)
2845 priv->has_wifi = 1;
2846 if (val32 & MULTI_BT_FUNC_EN)
2847 priv->has_bluetooth = 1;
2848 if (val32 & MULTI_GPS_FUNC_EN)
2849 priv->has_gps = 1;
38451998 2850 priv->is_multi_func = 1;
26f1fad2
JS		 2851 } else if (val32 & SYS_CFG_TYPE_ID) {
2852 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2853 bonding &= HPON_FSM_BONDING_MASK;
55c0b6ae
JS		 2854 if (priv->fops->tx_desc_size ==
2855 sizeof(struct rtl8xxxu_txdesc40)) {
0e5d435a
JS		 2856 if (bonding == HPON_FSM_BONDING_1T2R) {
2857 sprintf(priv->chip_name, "8191EU");
2858 priv->rf_paths = 2;
2859 priv->rx_paths = 2;
2860 priv->tx_paths = 1;
ba17d824 2861 priv->rtl_chip = RTL8191E;
0e5d435a
JS		 2862 } else {
2863 sprintf(priv->chip_name, "8192EU");
2864 priv->rf_paths = 2;
2865 priv->rx_paths = 2;
2866 priv->tx_paths = 2;
ba17d824 2867 priv->rtl_chip = RTL8192E;
0e5d435a
JS		 2868 }
2869 } else if (bonding == HPON_FSM_BONDING_1T2R) {
26f1fad2
JS		 2870 sprintf(priv->chip_name, "8191CU");
2871 priv->rf_paths = 2;
2872 priv->rx_paths = 2;
2873 priv->tx_paths = 1;
0e28b975 2874 priv->usb_interrupts = 1;
ba17d824 2875 priv->rtl_chip = RTL8191C;
26f1fad2
JS		 2876 } else {
2877 sprintf(priv->chip_name, "8192CU");
2878 priv->rf_paths = 2;
2879 priv->rx_paths = 2;
2880 priv->tx_paths = 2;
0e28b975 2881 priv->usb_interrupts = 1;
ba17d824 2882 priv->rtl_chip = RTL8192C;
26f1fad2
JS		 2883 }
2884 priv->has_wifi = 1;
2885 } else {
2886 sprintf(priv->chip_name, "8188CU");
2887 priv->rf_paths = 1;
2888 priv->rx_paths = 1;
2889 priv->tx_paths = 1;
ba17d824 2890 priv->rtl_chip = RTL8188C;
0e28b975 2891 priv->usb_interrupts = 1;
26f1fad2
JS		 2892 priv->has_wifi = 1;
2893 }
2894
ba17d824
JS		 2895 switch (priv->rtl_chip) {
2896 case RTL8188E:
2897 case RTL8192E:
2898 case RTL8723B:
0e5d435a
JS		 2899 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2900 case SYS_CFG_VENDOR_ID_TSMC:
2901 sprintf(priv->chip_vendor, "TSMC");
2902 break;
2903 case SYS_CFG_VENDOR_ID_SMIC:
2904 sprintf(priv->chip_vendor, "SMIC");
2905 priv->vendor_smic = 1;
2906 break;
2907 case SYS_CFG_VENDOR_ID_UMC:
2908 sprintf(priv->chip_vendor, "UMC");
2909 priv->vendor_umc = 1;
2910 break;
2911 default:
2912 sprintf(priv->chip_vendor, "unknown");
2913 }
2914 break;
2915 default:
2916 if (val32 & SYS_CFG_VENDOR_ID) {
2917 sprintf(priv->chip_vendor, "UMC");
2918 priv->vendor_umc = 1;
2919 } else {
2920 sprintf(priv->chip_vendor, "TSMC");
2921 }
2922 }
26f1fad2
JS		 2923
2924 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2925 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2926
2927 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2928 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2929 priv->ep_tx_high_queue = 1;
2930 priv->ep_tx_count++;
2931 }
2932
2933 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2934 priv->ep_tx_normal_queue = 1;
2935 priv->ep_tx_count++;
2936 }
2937
2938 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2939 priv->ep_tx_low_queue = 1;
2940 priv->ep_tx_count++;
2941 }
2942
2943 /*
2944 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2945 */
2946 if (!priv->ep_tx_count) {
2947 switch (priv->nr_out_eps) {
35a741fe 2948 case 4:
26f1fad2
JS		 2949 case 3:
2950 priv->ep_tx_low_queue = 1;
2951 priv->ep_tx_count++;
2952 case 2:
2953 priv->ep_tx_normal_queue = 1;
2954 priv->ep_tx_count++;
2955 case 1:
2956 priv->ep_tx_high_queue = 1;
2957 priv->ep_tx_count++;
2958 break;
2959 default:
2960 dev_info(dev, "Unsupported USB TX end-points\n");
2961 return -ENOTSUPP;
2962 }
2963 }
2964
2965 return 0;
2966}
2967
2968static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2969{
d38f1c37
JS		 2970 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2971
2972 if (efuse->rtl_id != cpu_to_le16(0x8129))
26f1fad2
JS		 2973 return -EINVAL;
2974
d38f1c37 2975 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
26f1fad2
JS		 2976
2977 memcpy(priv->cck_tx_power_index_A,
d38f1c37 2978 efuse->cck_tx_power_index_A,
3e84f938 2979 sizeof(efuse->cck_tx_power_index_A));
26f1fad2 2980 memcpy(priv->cck_tx_power_index_B,
d38f1c37 2981 efuse->cck_tx_power_index_B,
3e84f938 2982 sizeof(efuse->cck_tx_power_index_B));
26f1fad2
JS		 2983
2984 memcpy(priv->ht40_1s_tx_power_index_A,
d38f1c37 2985 efuse->ht40_1s_tx_power_index_A,
3e84f938 2986 sizeof(efuse->ht40_1s_tx_power_index_A));
26f1fad2 2987 memcpy(priv->ht40_1s_tx_power_index_B,
d38f1c37 2988 efuse->ht40_1s_tx_power_index_B,
3e84f938 2989 sizeof(efuse->ht40_1s_tx_power_index_B));
26f1fad2
JS		 2990
2991 memcpy(priv->ht20_tx_power_index_diff,
d38f1c37 2992 efuse->ht20_tx_power_index_diff,
3e84f938 2993 sizeof(efuse->ht20_tx_power_index_diff));
26f1fad2 2994 memcpy(priv->ofdm_tx_power_index_diff,
d38f1c37 2995 efuse->ofdm_tx_power_index_diff,
3e84f938 2996 sizeof(efuse->ofdm_tx_power_index_diff));
26f1fad2
JS		 2997
2998 memcpy(priv->ht40_max_power_offset,
d38f1c37 2999 efuse->ht40_max_power_offset,
3e84f938 3000 sizeof(efuse->ht40_max_power_offset));
26f1fad2 3001 memcpy(priv->ht20_max_power_offset,
d38f1c37 3002 efuse->ht20_max_power_offset,
3e84f938 3003 sizeof(efuse->ht20_max_power_offset));
26f1fad2 3004
4ef22eb9
JS		 3005 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
3006 priv->has_xtalk = 1;
3007 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
3008 }
2fc0b8e5
JS		 3009
3010 priv->power_base = &rtl8723a_power_base;
3011
26f1fad2 3012 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
d38f1c37 3013 efuse->vendor_name);
26f1fad2 3014 dev_info(&priv->udev->dev, "Product: %.41s\n",
d38f1c37 3015 efuse->device_name);
26f1fad2
JS		 3016 return 0;
3017}
3018
3c836d60
JS		 3019static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
3020{
b8ba8602 3021 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
3be26999 3022 int i;
b8ba8602
JS		 3023
3024 if (efuse->rtl_id != cpu_to_le16(0x8129))
3c836d60
JS		 3025 return -EINVAL;
3026
b8ba8602 3027 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
3c836d60 3028
3be26999
JS		 3029 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
3030 sizeof(efuse->tx_power_index_A.cck_base));
3031 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
3032 sizeof(efuse->tx_power_index_B.cck_base));
3033
3034 memcpy(priv->ht40_1s_tx_power_index_A,
3035 efuse->tx_power_index_A.ht40_base,
3036 sizeof(efuse->tx_power_index_A.ht40_base));
3037 memcpy(priv->ht40_1s_tx_power_index_B,
3038 efuse->tx_power_index_B.ht40_base,
3039 sizeof(efuse->tx_power_index_B.ht40_base));
3040
3041 priv->ofdm_tx_power_diff[0].a =
3042 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
3043 priv->ofdm_tx_power_diff[0].b =
3044 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
3045
3046 priv->ht20_tx_power_diff[0].a =
3047 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
3048 priv->ht20_tx_power_diff[0].b =
3049 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
3050
3051 priv->ht40_tx_power_diff[0].a = 0;
3052 priv->ht40_tx_power_diff[0].b = 0;
3053
3054 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
3055 priv->ofdm_tx_power_diff[i].a =
3056 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
3057 priv->ofdm_tx_power_diff[i].b =
3058 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
3059
3060 priv->ht20_tx_power_diff[i].a =
3061 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
3062 priv->ht20_tx_power_diff[i].b =
3063 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
3064
3065 priv->ht40_tx_power_diff[i].a =
3066 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
3067 priv->ht40_tx_power_diff[i].b =
3068 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
3069 }
3070
4ef22eb9
JS		 3071 priv->has_xtalk = 1;
3072 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
3073
b8ba8602
JS		 3074 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
3075 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
3c836d60
JS		 3076
3077 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
3078 int i;
3079 unsigned char *raw = priv->efuse_wifi.raw;
3080
3081 dev_info(&priv->udev->dev,
3082 "%s: dumping efuse (0x%02zx bytes):\n",
3083 __func__, sizeof(struct rtl8723bu_efuse));
3084 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
3085 dev_info(&priv->udev->dev, "%02x: "
3086 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
3087 raw[i], raw[i + 1], raw[i + 2],
3088 raw[i + 3], raw[i + 4], raw[i + 5],
3089 raw[i + 6], raw[i + 7]);
3090 }
3091 }
3092
3093 return 0;
3094}
3095
c0963772
KV		 3096#ifdef CONFIG_RTL8XXXU_UNTESTED
3097
26f1fad2
JS		 3098static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
3099{
49594441 3100 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
26f1fad2
JS		 3101 int i;
3102
49594441 3103 if (efuse->rtl_id != cpu_to_le16(0x8129))
26f1fad2
JS		 3104 return -EINVAL;
3105
49594441 3106 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
26f1fad2
JS		 3107
3108 memcpy(priv->cck_tx_power_index_A,
49594441 3109 efuse->cck_tx_power_index_A,
3e84f938 3110 sizeof(efuse->cck_tx_power_index_A));
26f1fad2 3111 memcpy(priv->cck_tx_power_index_B,
49594441 3112 efuse->cck_tx_power_index_B,
3e84f938 3113 sizeof(efuse->cck_tx_power_index_B));
26f1fad2
JS		 3114
3115 memcpy(priv->ht40_1s_tx_power_index_A,
49594441 3116 efuse->ht40_1s_tx_power_index_A,
3e84f938 3117 sizeof(efuse->ht40_1s_tx_power_index_A));
26f1fad2 3118 memcpy(priv->ht40_1s_tx_power_index_B,
49594441 3119 efuse->ht40_1s_tx_power_index_B,
3e84f938 3120 sizeof(efuse->ht40_1s_tx_power_index_B));
26f1fad2 3121 memcpy(priv->ht40_2s_tx_power_index_diff,
49594441 3122 efuse->ht40_2s_tx_power_index_diff,
3e84f938 3123 sizeof(efuse->ht40_2s_tx_power_index_diff));
26f1fad2
JS		 3124
3125 memcpy(priv->ht20_tx_power_index_diff,
49594441 3126 efuse->ht20_tx_power_index_diff,
3e84f938 3127 sizeof(efuse->ht20_tx_power_index_diff));
26f1fad2 3128 memcpy(priv->ofdm_tx_power_index_diff,
49594441 3129 efuse->ofdm_tx_power_index_diff,
3e84f938 3130 sizeof(efuse->ofdm_tx_power_index_diff));
26f1fad2
JS		 3131
3132 memcpy(priv->ht40_max_power_offset,
49594441 3133 efuse->ht40_max_power_offset,
3e84f938 3134 sizeof(efuse->ht40_max_power_offset));
26f1fad2 3135 memcpy(priv->ht20_max_power_offset,
49594441 3136 efuse->ht20_max_power_offset,
3e84f938 3137 sizeof(efuse->ht20_max_power_offset));
26f1fad2
JS		 3138
3139 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
49594441 3140 efuse->vendor_name);
26f1fad2 3141 dev_info(&priv->udev->dev, "Product: %.20s\n",
49594441 3142 efuse->device_name);
26f1fad2 3143
2fc0b8e5
JS		 3144 priv->power_base = &rtl8192c_power_base;
3145
49594441 3146 if (efuse->rf_regulatory & 0x20) {
26f1fad2 3147 sprintf(priv->chip_name, "8188RU");
8d95c808 3148 priv->rtl_chip = RTL8188R;
26f1fad2 3149 priv->hi_pa = 1;
cabb550e 3150 priv->no_pape = 1;
2fc0b8e5 3151 priv->power_base = &rtl8188r_power_base;
26f1fad2
JS		 3152 }
3153
3154 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
3155 unsigned char *raw = priv->efuse_wifi.raw;
3156
3157 dev_info(&priv->udev->dev,
3158 "%s: dumping efuse (0x%02zx bytes):\n",
3159 __func__, sizeof(struct rtl8192cu_efuse));
3160 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
3161 dev_info(&priv->udev->dev, "%02x: "
3162 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
3163 raw[i], raw[i + 1], raw[i + 2],
3164 raw[i + 3], raw[i + 4], raw[i + 5],
3165 raw[i + 6], raw[i + 7]);
3166 }
3167 }
3168 return 0;
3169}
3170
c0963772
KV		 3171#endif
3172
3307d840
JS		 3173static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
3174{
b7dda34d 3175 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
3307d840
JS		 3176 int i;
3177
b7dda34d 3178 if (efuse->rtl_id != cpu_to_le16(0x8129))
3307d840
JS		 3179 return -EINVAL;
3180
b7dda34d 3181 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
3307d840 3182
9e24772a
JS		 3183 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
3184 sizeof(efuse->tx_power_index_A.cck_base));
3185 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
3186 sizeof(efuse->tx_power_index_B.cck_base));
3187
3188 memcpy(priv->ht40_1s_tx_power_index_A,
3189 efuse->tx_power_index_A.ht40_base,
3190 sizeof(efuse->tx_power_index_A.ht40_base));
3191 memcpy(priv->ht40_1s_tx_power_index_B,
3192 efuse->tx_power_index_B.ht40_base,
3193 sizeof(efuse->tx_power_index_B.ht40_base));
3194
3195 priv->ht20_tx_power_diff[0].a =
3196 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
3197 priv->ht20_tx_power_diff[0].b =
3198 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
3199
3200 priv->ht40_tx_power_diff[0].a = 0;
3201 priv->ht40_tx_power_diff[0].b = 0;
3202
3203 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
3204 priv->ofdm_tx_power_diff[i].a =
3205 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
3206 priv->ofdm_tx_power_diff[i].b =
3207 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
3208
3209 priv->ht20_tx_power_diff[i].a =
3210 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
3211 priv->ht20_tx_power_diff[i].b =
3212 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
3213
3214 priv->ht40_tx_power_diff[i].a =
3215 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
3216 priv->ht40_tx_power_diff[i].b =
3217 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
3218 }
3219
4ef22eb9
JS		 3220 priv->has_xtalk = 1;
3221 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
3222
b7dda34d
JS		 3223 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
3224 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
3225 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
3307d840
JS		 3226
3227 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
3228 unsigned char *raw = priv->efuse_wifi.raw;
3229
3230 dev_info(&priv->udev->dev,
3231 "%s: dumping efuse (0x%02zx bytes):\n",
3232 __func__, sizeof(struct rtl8192eu_efuse));
3233 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
3234 dev_info(&priv->udev->dev, "%02x: "
3235 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
3236 raw[i], raw[i + 1], raw[i + 2],
3237 raw[i + 3], raw[i + 4], raw[i + 5],
3238 raw[i + 6], raw[i + 7]);
3239 }
3240 }
0e5d435a 3241 return 0;
3307d840
JS		 3242}
3243
26f1fad2
JS		 3244static int
3245rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
3246{
3247 int i;
3248 u8 val8;
3249 u32 val32;
3250
3251 /* Write Address */
3252 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
3253 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
3254 val8 &= 0xfc;
3255 val8 |= (offset >> 8) & 0x03;
3256 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
3257
3258 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
3259 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
3260
3261 /* Poll for data read */
3262 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3263 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
3264 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3265 if (val32 & BIT(31))
3266 break;
3267 }
3268
3269 if (i == RTL8XXXU_MAX_REG_POLL)
3270 return -EIO;
3271
3272 udelay(50);
3273 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3274
3275 *data = val32 & 0xff;
3276 return 0;
3277}
3278
3279static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
3280{
3281 struct device *dev = &priv->udev->dev;
3282 int i, ret = 0;
3283 u8 val8, word_mask, header, extheader;
3284 u16 val16, efuse_addr, offset;
3285 u32 val32;
3286
3287 val16 = rtl8xxxu_read16(priv, REG_9346CR);
3288 if (val16 & EEPROM_ENABLE)
3289 priv->has_eeprom = 1;
3290 if (val16 & EEPROM_BOOT)
3291 priv->boot_eeprom = 1;
3292
38451998
JS		 3293 if (priv->is_multi_func) {
3294 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
3295 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
3296 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
3297 }
26f1fad2
JS		 3298
3299 dev_dbg(dev, "Booting from %s\n",
3300 priv->boot_eeprom ? "EEPROM" : "EFUSE");
3301
3302 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
3303
3304 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
3305 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3306 if (!(val16 & SYS_ISO_PWC_EV12V)) {
3307 val16 |= SYS_ISO_PWC_EV12V;
3308 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3309 }
3310 /* Reset: 0x0000[28], default valid */
3311 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3312 if (!(val16 & SYS_FUNC_ELDR)) {
3313 val16 |= SYS_FUNC_ELDR;
3314 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3315 }
3316
3317 /*
3318 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
3319 */
3320 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
3321 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
3322 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
3323 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
3324 }
3325
3326 /* Default value is 0xff */
3307d840 3327 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
26f1fad2
JS		 3328
3329 efuse_addr = 0;
3330 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
f6c47702
JS		 3331 u16 map_addr;
3332
26f1fad2
JS		 3333 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
3334 if (ret || header == 0xff)
3335 goto exit;
3336
3337 if ((header & 0x1f) == 0x0f) { /* extended header */
3338 offset = (header & 0xe0) >> 5;
3339
3340 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
3341 &extheader);
3342 if (ret)
3343 goto exit;
3344 /* All words disabled */
3345 if ((extheader & 0x0f) == 0x0f)
3346 continue;
3347
3348 offset |= ((extheader & 0xf0) >> 1);
3349 word_mask = extheader & 0x0f;
3350 } else {
3351 offset = (header >> 4) & 0x0f;
3352 word_mask = header & 0x0f;
3353 }
3354
f6c47702
JS		 3355 /* Get word enable value from PG header */
3356
3357 /* We have 8 bits to indicate validity */
3358 map_addr = offset * 8;
3359 if (map_addr >= EFUSE_MAP_LEN) {
3360 dev_warn(dev, "%s: Illegal map_addr (%04x), "
3361 "efuse corrupt!\n",
3362 __func__, map_addr);
26f1fad2
JS		 3363 ret = -EINVAL;
3364 goto exit;
3365 }
f6c47702
JS		 3366 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
3367 /* Check word enable condition in the section */
32a39dd4 3368 if (word_mask & BIT(i)) {
f6c47702 3369 map_addr += 2;
32a39dd4
JS		 3370 continue;
3371 }
3372
3373 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
3374 if (ret)
3375 goto exit;
3376 priv->efuse_wifi.raw[map_addr++] = val8;
3377
3378 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
3379 if (ret)
3380 goto exit;
3381 priv->efuse_wifi.raw[map_addr++] = val8;
f6c47702 3382 }
26f1fad2
JS		 3383 }
3384
3385exit:
3386 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
3387
3388 return ret;
3389}
3390
d48fe60e
JS		 3391static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
3392{
3393 u8 val8;
3394 u16 sys_func;
3395
3396 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 3397 val8 &= ~BIT(0);
d48fe60e 3398 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7d4ccb8b 3399
d48fe60e
JS		 3400 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3401 sys_func &= ~SYS_FUNC_CPU_ENABLE;
3402 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
7d4ccb8b 3403
d48fe60e 3404 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 3405 val8 |= BIT(0);
d48fe60e 3406 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7d4ccb8b
JS		 3407
3408 sys_func |= SYS_FUNC_CPU_ENABLE;
3409 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3410}
3411
3412static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
3413{
3414 u8 val8;
3415 u16 sys_func;
3416
3417 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3418 val8 &= ~BIT(1);
3419 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
3420
3421 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3422 val8 &= ~BIT(0);
3423 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3424
3425 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3426 sys_func &= ~SYS_FUNC_CPU_ENABLE;
3427 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3428
3429 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3430 val8 &= ~BIT(1);
3431 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
3432
3433 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3434 val8 |= BIT(0);
3435 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3436
d48fe60e
JS		 3437 sys_func |= SYS_FUNC_CPU_ENABLE;
3438 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3439}
3440
26f1fad2
JS		 3441static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
3442{
3443 struct device *dev = &priv->udev->dev;
3444 int ret = 0, i;
3445 u32 val32;
3446
3447 /* Poll checksum report */
3448 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
3449 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3450 if (val32 & MCU_FW_DL_CSUM_REPORT)
3451 break;
3452 }
3453
3454 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
3455 dev_warn(dev, "Firmware checksum poll timed out\n");
3456 ret = -EAGAIN;
3457 goto exit;
3458 }
3459
3460 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3461 val32 |= MCU_FW_DL_READY;
3462 val32 &= ~MCU_WINT_INIT_READY;
3463 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
3464
d48fe60e
JS		 3465 /*
3466 * Reset the 8051 in order for the firmware to start running,
3467 * otherwise it won't come up on the 8192eu
3468 */
7d4ccb8b 3469 priv->fops->reset_8051(priv);
d48fe60e 3470
26f1fad2
JS		 3471 /* Wait for firmware to become ready */
3472 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
3473 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3474 if (val32 & MCU_WINT_INIT_READY)
3475 break;
3476
3477 udelay(100);
3478 }
3479
3480 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
3481 dev_warn(dev, "Firmware failed to start\n");
3482 ret = -EAGAIN;
3483 goto exit;
3484 }
3485
3a4be6a0
JS		 3486 /*
3487 * Init H2C command
3488 */
ba17d824 3489 if (priv->rtl_chip == RTL8723B)
3a4be6a0 3490 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
26f1fad2
JS		 3491exit:
3492 return ret;
3493}
3494
3495static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
3496{
3497 int pages, remainder, i, ret;
d48fe60e 3498 u8 val8;
26f1fad2
JS		 3499 u16 val16;
3500 u32 val32;
3501 u8 *fwptr;
3502
3503 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
3504 val8 |= 4;
3505 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
3506
3507 /* 8051 enable */
3508 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
43154f6f
JS		 3509 val16 |= SYS_FUNC_CPU_ENABLE;
3510 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 3511
216202ae
JS		 3512 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
3513 if (val8 & MCU_FW_RAM_SEL) {
3514 pr_info("do the RAM reset\n");
3515 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
7d4ccb8b 3516 priv->fops->reset_8051(priv);
216202ae
JS		 3517 }
3518
26f1fad2
JS		 3519 /* MCU firmware download enable */
3520 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 3521 val8 |= MCU_FW_DL_ENABLE;
3522 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 3523
3524 /* 8051 reset */
3525 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
ef1c0499
JS		 3526 val32 &= ~BIT(19);
3527 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
26f1fad2
JS		 3528
3529 /* Reset firmware download checksum */
3530 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 3531 val8 |= MCU_FW_DL_CSUM_REPORT;
3532 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 3533
3534 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
3535 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
3536
3537 fwptr = priv->fw_data->data;
3538
3539 for (i = 0; i < pages; i++) {
3540 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 3541 val8 |= i;
3542 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 3543
3544 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
3545 fwptr, RTL_FW_PAGE_SIZE);
3546 if (ret != RTL_FW_PAGE_SIZE) {
3547 ret = -EAGAIN;
3548 goto fw_abort;
3549 }
3550
3551 fwptr += RTL_FW_PAGE_SIZE;
3552 }
3553
3554 if (remainder) {
3555 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 3556 val8 |= i;
3557 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 3558 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
3559 fwptr, remainder);
3560 if (ret != remainder) {
3561 ret = -EAGAIN;
3562 goto fw_abort;
3563 }
3564 }
3565
3566 ret = 0;
3567fw_abort:
3568 /* MCU firmware download disable */
3569 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
ef1c0499
JS		 3570 val16 &= ~MCU_FW_DL_ENABLE;
3571 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
26f1fad2
JS		 3572
3573 return ret;
3574}
3575
3576static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
3577{
3578 struct device *dev = &priv->udev->dev;
3579 const struct firmware *fw;
3580 int ret = 0;
3581 u16 signature;
3582
3583 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
3584 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
3585 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
3586 ret = -EAGAIN;
3587 goto exit;
3588 }
3589 if (!fw) {
3590 dev_warn(dev, "Firmware data not available\n");
3591 ret = -EINVAL;
3592 goto exit;
3593 }
3594
3595 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
98e27cbd
TK		 3596 if (!priv->fw_data) {
3597 ret = -ENOMEM;
3598 goto exit;
3599 }
26f1fad2
JS		 3600 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
3601
3602 signature = le16_to_cpu(priv->fw_data->signature);
3603 switch (signature & 0xfff0) {
0e5d435a 3604 case 0x92e0:
26f1fad2
JS		 3605 case 0x92c0:
3606 case 0x88c0:
35a741fe 3607 case 0x5300:
26f1fad2
JS		 3608 case 0x2300:
3609 break;
3610 default:
3611 ret = -EINVAL;
3612 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
3613 __func__, signature);
3614 }
3615
3616 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
3617 le16_to_cpu(priv->fw_data->major_version),
3618 priv->fw_data->minor_version, signature);
3619
3620exit:
3621 release_firmware(fw);
3622 return ret;
3623}
3624
3625static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
3626{
3627 char *fw_name;
3628 int ret;
3629
3630 switch (priv->chip_cut) {
3631 case 0:
3632 fw_name = "rtlwifi/rtl8723aufw_A.bin";
3633 break;
3634 case 1:
3635 if (priv->enable_bluetooth)
3636 fw_name = "rtlwifi/rtl8723aufw_B.bin";
3637 else
3638 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
3639
3640 break;
3641 default:
3642 return -EINVAL;
3643 }
3644
3645 ret = rtl8xxxu_load_firmware(priv, fw_name);
3646 return ret;
3647}
3648
35a741fe
JS		 3649static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
3650{
3651 char *fw_name;
3652 int ret;
3653
3654 if (priv->enable_bluetooth)
3655 fw_name = "rtlwifi/rtl8723bu_bt.bin";
3656 else
3657 fw_name = "rtlwifi/rtl8723bu_nic.bin";
3658
3659 ret = rtl8xxxu_load_firmware(priv, fw_name);
3660 return ret;
3661}
3662
c0963772
KV		 3663#ifdef CONFIG_RTL8XXXU_UNTESTED
3664
26f1fad2
JS		 3665static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
3666{
3667 char *fw_name;
3668 int ret;
3669
3670 if (!priv->vendor_umc)
3671 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
ba17d824 3672 else if (priv->chip_cut || priv->rtl_chip == RTL8192C)
26f1fad2
JS		 3673 fw_name = "rtlwifi/rtl8192cufw_B.bin";
3674 else
3675 fw_name = "rtlwifi/rtl8192cufw_A.bin";
3676
3677 ret = rtl8xxxu_load_firmware(priv, fw_name);
3678
3679 return ret;
3680}
3681
c0963772
KV		 3682#endif
3683
3307d840
JS		 3684static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
3685{
3686 char *fw_name;
3687 int ret;
3688
0e5d435a 3689 fw_name = "rtlwifi/rtl8192eu_nic.bin";
3307d840
JS		 3690
3691 ret = rtl8xxxu_load_firmware(priv, fw_name);
3692
3693 return ret;
3694}
3695
26f1fad2
JS		 3696static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
3697{
3698 u16 val16;
3699 int i = 100;
3700
3701 /* Inform 8051 to perform reset */
3702 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
3703
3704 for (i = 100; i > 0; i--) {
3705 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3706
3707 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
3708 dev_dbg(&priv->udev->dev,
3709 "%s: Firmware self reset success!\n", __func__);
3710 break;
3711 }
3712 udelay(50);
3713 }
3714
3715 if (!i) {
3716 /* Force firmware reset */
3717 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3718 val16 &= ~SYS_FUNC_CPU_ENABLE;
3719 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3720 }
3721}
3722
f0d9f5e9
JS		 3723static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3724{
3725 u32 val32;
3726
70bc1e24 3727 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1);
f0d9f5e9 3728 val32 &= ~(BIT(20) | BIT(24));
70bc1e24 3729 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32);
f0d9f5e9
JS		 3730
3731 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3732 val32 &= ~BIT(4);
3a4be6a0
JS		 3733 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3734
3735 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
f0d9f5e9
JS		 3736 val32 |= BIT(3);
3737 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3738
3739 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
f0d9f5e9
JS		 3740 val32 |= BIT(24);
3741 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3742
3a4be6a0
JS		 3743 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3744 val32 &= ~BIT(23);
3745 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3746
120e627f 3747 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
f0d9f5e9 3748 val32 |= (BIT(0) | BIT(1));
120e627f 3749 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
f0d9f5e9 3750
59b74397 3751 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
f0d9f5e9
JS		 3752 val32 &= 0xffffff00;
3753 val32 |= 0x77;
59b74397 3754 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3a4be6a0
JS		 3755
3756 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3757 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3758 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
f0d9f5e9
JS		 3759}
3760
26f1fad2 3761static int
c606e662 3762rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
26f1fad2 3763{
c606e662 3764 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
26f1fad2
JS		 3765 int i, ret;
3766 u16 reg;
3767 u8 val;
3768
3769 for (i = 0; ; i++) {
3770 reg = array[i].reg;
3771 val = array[i].val;
3772
3773 if (reg == 0xffff && val == 0xff)
3774 break;
3775
3776 ret = rtl8xxxu_write8(priv, reg, val);
3777 if (ret != 1) {
3778 dev_warn(&priv->udev->dev,
c606e662
JS		 3779 "Failed to initialize MAC "
3780 "(reg: %04x, val %02x)\n", reg, val);
26f1fad2
JS		 3781 return -EAGAIN;
3782 }
3783 }
3784
8a59485c 3785 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
8baf670b 3786 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
26f1fad2
JS		 3787
3788 return 0;
3789}
3790
3791static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3792 struct rtl8xxxu_reg32val *array)
3793{
3794 int i, ret;
3795 u16 reg;
3796 u32 val;
3797
3798 for (i = 0; ; i++) {
3799 reg = array[i].reg;
3800 val = array[i].val;
3801
3802 if (reg == 0xffff && val == 0xffffffff)
3803 break;
3804
3805 ret = rtl8xxxu_write32(priv, reg, val);
3806 if (ret != sizeof(val)) {
3807 dev_warn(&priv->udev->dev,
3808 "Failed to initialize PHY\n");
3809 return -EAGAIN;
3810 }
3811 udelay(1);
3812 }
3813
3814 return 0;
3815}
3816
de7c189c 3817static void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
26f1fad2 3818{
b84cac16 3819 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
04313eb4 3820 u16 val16;
26f1fad2
JS		 3821 u32 val32;
3822
cb877250
JS		 3823 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3824 udelay(2);
3825 val8 |= AFE_PLL_320_ENABLE;
3826 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3827 udelay(2);
3ca7b32c 3828
cb877250
JS		 3829 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3830 udelay(2);
26f1fad2 3831
cb877250
JS		 3832 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3833 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3834 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 3835
cb877250
JS		 3836 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3837 val32 &= ~AFE_XTAL_RF_GATE;
3838 if (priv->has_bluetooth)
3839 val32 &= ~AFE_XTAL_BT_GATE;
3840 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
26f1fad2
JS		 3841
3842 /* 6. 0x1f[7:0] = 0x07 */
3843 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3844 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3845
cb877250 3846 if (priv->hi_pa)
abd71bdb
JS		 3847 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3848 else if (priv->tx_paths == 2)
3849 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3850 else
26f1fad2
JS		 3851 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3852
78a84219 3853 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
26f1fad2
JS		 3854 priv->vendor_umc && priv->chip_cut == 1)
3855 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
c82f8d11
JS		 3856
3857 if (priv->hi_pa)
3858 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3859 else
3860 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
b84cac16
JS		 3861
3862 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3863 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3864 ldohci12 = 0x57;
3865 lpldo = 1;
3866 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
3867 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
cb877250
JS		 3868}
3869
3870static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv)
3871{
3872 u8 val8;
3873 u16 val16;
3874
3875 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3876 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
3877 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3878
3879 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3880
3881 /* 6. 0x1f[7:0] = 0x07 */
3882 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3883 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3884
3885 /* Why? */
3886 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3887 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3888 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
c82f8d11
JS		 3889
3890 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
cb877250
JS		 3891}
3892
3893static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv)
3894{
3895 u8 val8;
3896 u16 val16;
3897
3898 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3899 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
3900 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3901
3902 /* 6. 0x1f[7:0] = 0x07 */
3903 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3904 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3905
3906 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3907 val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |
3908 SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);
3909 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3910 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3911 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3912 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);
c82f8d11
JS		 3913
3914 if (priv->hi_pa)
3915 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table);
3916 else
3917 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table);
cb877250
JS		 3918}
3919
3920/*
3921 * Most of this is black magic retrieved from the old rtl8723au driver
3922 */
3923static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3924{
b84cac16 3925 u8 val8;
cb877250
JS		 3926 u32 val32;
3927
3928 priv->fops->init_phy_bb(priv);
26f1fad2
JS		 3929
3930 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3931 /*
3932 * For 1T2R boards, patch the registers.
3933 *
3934 * It looks like 8191/2 1T2R boards use path B for TX
3935 */
3936 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3937 val32 &= ~(BIT(0) | BIT(1));
3938 val32 |= BIT(1);
3939 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3940
3941 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3942 val32 &= ~0x300033;
3943 val32 |= 0x200022;
3944 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3945
3946 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
bd8fe40c 3947 val32 &= ~CCK0_AFE_RX_MASK;
9068308a 3948 val32 &= 0x00ffffff;
bd8fe40c
JS		 3949 val32 |= 0x40000000;
3950 val32 |= CCK0_AFE_RX_ANT_B;
26f1fad2
JS		 3951 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3952
3953 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3954 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3955 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3956 OFDM_RF_PATH_TX_B);
3957 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3958
3959 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3960 val32 &= ~(BIT(4) | BIT(5));
3961 val32 |= BIT(4);
3962 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3963
3964 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3965 val32 &= ~(BIT(27) | BIT(26));
3966 val32 |= BIT(27);
3967 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3968
3969 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3970 val32 &= ~(BIT(27) | BIT(26));
3971 val32 |= BIT(27);
3972 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3973
3974 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3975 val32 &= ~(BIT(27) | BIT(26));
3976 val32 |= BIT(27);
3977 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3978
3979 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3980 val32 &= ~(BIT(27) | BIT(26));
3981 val32 |= BIT(27);
3982 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3983
3984 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3985 val32 &= ~(BIT(27) | BIT(26));
3986 val32 |= BIT(27);
3987 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3988 }
3989
4ef22eb9 3990 if (priv->has_xtalk) {
26f1fad2
JS		 3991 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3992
4ef22eb9 3993 val8 = priv->xtalk;
26f1fad2
JS		 3994 val32 &= 0xff000fff;
3995 val32 |= ((val8 | (val8 << 6)) << 12);
3996
3997 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3998 }
3999
8a59485c
JS		 4000 if (priv->rtl_chip == RTL8192E)
4001 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
4002
26f1fad2
JS		 4003 return 0;
4004}
4005
4006static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
4007 struct rtl8xxxu_rfregval *array,
4008 enum rtl8xxxu_rfpath path)
4009{
4010 int i, ret;
4011 u8 reg;
4012 u32 val;
4013
4014 for (i = 0; ; i++) {
4015 reg = array[i].reg;
4016 val = array[i].val;
4017
4018 if (reg == 0xff && val == 0xffffffff)
4019 break;
4020
4021 switch (reg) {
4022 case 0xfe:
4023 msleep(50);
4024 continue;
4025 case 0xfd:
4026 mdelay(5);
4027 continue;
4028 case 0xfc:
4029 mdelay(1);
4030 continue;
4031 case 0xfb:
4032 udelay(50);
4033 continue;
4034 case 0xfa:
4035 udelay(5);
4036 continue;
4037 case 0xf9:
4038 udelay(1);
4039 continue;
4040 }
4041
26f1fad2
JS		 4042 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
4043 if (ret) {
4044 dev_warn(&priv->udev->dev,
4045 "Failed to initialize RF\n");
4046 return -EAGAIN;
4047 }
4048 udelay(1);
4049 }
4050
4051 return 0;
4052}
4053
4054static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
4055 struct rtl8xxxu_rfregval *table,
4056 enum rtl8xxxu_rfpath path)
4057{
4058 u32 val32;
4059 u16 val16, rfsi_rfenv;
4060 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
4061
4062 switch (path) {
4063 case RF_A:
4064 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
4065 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
4066 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
4067 break;
4068 case RF_B:
4069 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
4070 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
4071 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
4072 break;
4073 default:
4074 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
4075 __func__, path + 'A');
4076 return -EINVAL;
4077 }
4078 /* For path B, use XB */
4079 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
4080 rfsi_rfenv &= FPGA0_RF_RFENV;
4081
4082 /*
4083 * These two we might be able to optimize into one
4084 */
4085 val32 = rtl8xxxu_read32(priv, reg_int_oe);
4086 val32 |= BIT(20); /* 0x10 << 16 */
4087 rtl8xxxu_write32(priv, reg_int_oe, val32);
4088 udelay(1);
4089
4090 val32 = rtl8xxxu_read32(priv, reg_int_oe);
4091 val32 |= BIT(4);
4092 rtl8xxxu_write32(priv, reg_int_oe, val32);
4093 udelay(1);
4094
4095 /*
4096 * These two we might be able to optimize into one
4097 */
4098 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
4099 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
4100 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
4101 udelay(1);
4102
4103 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
4104 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
4105 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
4106 udelay(1);
4107
4108 rtl8xxxu_init_rf_regs(priv, table, path);
4109
4110 /* For path B, use XB */
4111 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
4112 val16 &= ~FPGA0_RF_RFENV;
4113 val16 |= rfsi_rfenv;
4114 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
4115
4116 return 0;
4117}
4118
4062b8ff
JS		 4119static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv)
4120{
4121 int ret;
4122
4123 ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A);
4124
4125 /* Reduce 80M spur */
4126 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4127 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4128 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4129 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4130
4131 return ret;
4132}
4133
4134static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
4135{
4136 int ret;
4137
4138 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A);
4139 /*
4140 * PHY LCK
4141 */
4142 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
4143 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
4144 msleep(200);
4145 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
4146
4147 return ret;
4148}
4149
4150#ifdef CONFIG_RTL8XXXU_UNTESTED
4151static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv)
4152{
4153 struct rtl8xxxu_rfregval *rftable;
4154 int ret;
4155
8d95c808
JS		 4156 if (priv->rtl_chip == RTL8188R) {
4157 rftable = rtl8188ru_radioa_1t_highpa_table;
4062b8ff
JS		 4158 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4159 } else if (priv->rf_paths == 1) {
4160 rftable = rtl8192cu_radioa_1t_init_table;
4161 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4162 } else {
4163 rftable = rtl8192cu_radioa_2t_init_table;
4164 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4165 if (ret)
4166 goto exit;
4167 rftable = rtl8192cu_radiob_2t_init_table;
4168 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4169 }
4170
4171exit:
4172 return ret;
4173}
4174#endif
4175
4176static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv)
4177{
4178 int ret;
4179
4180 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A);
4181 if (ret)
4182 goto exit;
4183
4184 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B);
4185
4186exit:
4187 return ret;
4188}
4189
26f1fad2
JS		 4190static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
4191{
4192 int ret = -EBUSY;
4193 int count = 0;
4194 u32 value;
4195
4196 value = LLT_OP_WRITE | address << 8 | data;
4197
4198 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
4199
4200 do {
4201 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
4202 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
4203 ret = 0;
4204 break;
4205 }
4206 } while (count++ < 20);
4207
4208 return ret;
4209}
4210
4211static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
4212{
4213 int ret;
4214 int i;
4215
4216 for (i = 0; i < last_tx_page; i++) {
4217 ret = rtl8xxxu_llt_write(priv, i, i + 1);
4218 if (ret)
4219 goto exit;
4220 }
4221
4222 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
4223 if (ret)
4224 goto exit;
4225
4226 /* Mark remaining pages as a ring buffer */
4227 for (i = last_tx_page + 1; i < 0xff; i++) {
4228 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
4229 if (ret)
4230 goto exit;
4231 }
4232
4233 /* Let last entry point to the start entry of ring buffer */
4234 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
4235 if (ret)
4236 goto exit;
4237
4238exit:
4239 return ret;
4240}
4241
74b99bed
JS		 4242static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
4243{
4244 u32 val32;
4245 int ret = 0;
4246 int i;
4247
4248 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
74b99bed
JS		 4249 val32 |= AUTO_LLT_INIT_LLT;
4250 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
4251
4252 for (i = 500; i; i--) {
4253 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
4254 if (!(val32 & AUTO_LLT_INIT_LLT))
4255 break;
4256 usleep_range(2, 4);
4257 }
4258
4de24819 4259 if (!i) {
74b99bed
JS		 4260 ret = -EBUSY;
4261 dev_warn(&priv->udev->dev, "LLT table init failed\n");
4262 }
74b99bed
JS		 4263
4264 return ret;
4265}
4266
26f1fad2
JS		 4267static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
4268{
4269 u16 val16, hi, lo;
4270 u16 hiq, mgq, bkq, beq, viq, voq;
4271 int hip, mgp, bkp, bep, vip, vop;
4272 int ret = 0;
4273
4274 switch (priv->ep_tx_count) {
4275 case 1:
4276 if (priv->ep_tx_high_queue) {
4277 hi = TRXDMA_QUEUE_HIGH;
4278 } else if (priv->ep_tx_low_queue) {
4279 hi = TRXDMA_QUEUE_LOW;
4280 } else if (priv->ep_tx_normal_queue) {
4281 hi = TRXDMA_QUEUE_NORMAL;
4282 } else {
4283 hi = 0;
4284 ret = -EINVAL;
4285 }
4286
4287 hiq = hi;
4288 mgq = hi;
4289 bkq = hi;
4290 beq = hi;
4291 viq = hi;
4292 voq = hi;
4293
4294 hip = 0;
4295 mgp = 0;
4296 bkp = 0;
4297 bep = 0;
4298 vip = 0;
4299 vop = 0;
4300 break;
4301 case 2:
4302 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
4303 hi = TRXDMA_QUEUE_HIGH;
4304 lo = TRXDMA_QUEUE_LOW;
4305 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
4306 hi = TRXDMA_QUEUE_NORMAL;
4307 lo = TRXDMA_QUEUE_LOW;
4308 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
4309 hi = TRXDMA_QUEUE_HIGH;
4310 lo = TRXDMA_QUEUE_NORMAL;
4311 } else {
4312 ret = -EINVAL;
4313 hi = 0;
4314 lo = 0;
4315 }
4316
4317 hiq = hi;
4318 mgq = hi;
4319 bkq = lo;
4320 beq = lo;
4321 viq = hi;
4322 voq = hi;
4323
4324 hip = 0;
4325 mgp = 0;
4326 bkp = 1;
4327 bep = 1;
4328 vip = 0;
4329 vop = 0;
4330 break;
4331 case 3:
4332 beq = TRXDMA_QUEUE_LOW;
4333 bkq = TRXDMA_QUEUE_LOW;
4334 viq = TRXDMA_QUEUE_NORMAL;
4335 voq = TRXDMA_QUEUE_HIGH;
4336 mgq = TRXDMA_QUEUE_HIGH;
4337 hiq = TRXDMA_QUEUE_HIGH;
4338
4339 hip = hiq ^ 3;
4340 mgp = mgq ^ 3;
4341 bkp = bkq ^ 3;
4342 bep = beq ^ 3;
4343 vip = viq ^ 3;
4344 vop = viq ^ 3;
4345 break;
4346 default:
4347 ret = -EINVAL;
4348 }
4349
4350 /*
4351 * None of the vendor drivers are configuring the beacon
4352 * queue here .... why?
4353 */
4354 if (!ret) {
4355 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
4356 val16 &= 0x7;
4357 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
4358 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
4359 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
4360 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
4361 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
4362 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
4363 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
4364
4365 priv->pipe_out[TXDESC_QUEUE_VO] =
4366 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
4367 priv->pipe_out[TXDESC_QUEUE_VI] =
4368 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
4369 priv->pipe_out[TXDESC_QUEUE_BE] =
4370 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
4371 priv->pipe_out[TXDESC_QUEUE_BK] =
4372 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
4373 priv->pipe_out[TXDESC_QUEUE_BEACON] =
4374 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
4375 priv->pipe_out[TXDESC_QUEUE_MGNT] =
4376 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
4377 priv->pipe_out[TXDESC_QUEUE_HIGH] =
4378 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
4379 priv->pipe_out[TXDESC_QUEUE_CMD] =
4380 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
4381 }
4382
4383 return ret;
4384}
4385
4386static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
4387 bool iqk_ok, int result[][8],
4388 int candidate, bool tx_only)
4389{
4390 u32 oldval, x, tx0_a, reg;
4391 int y, tx0_c;
4392 u32 val32;
4393
4394 if (!iqk_ok)
4395 return;
4396
4397 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4398 oldval = val32 >> 22;
4399
4400 x = result[candidate][0];
4401 if ((x & 0x00000200) != 0)
4402 x = x | 0xfffffc00;
4403 tx0_a = (x * oldval) >> 8;
4404
4405 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4406 val32 &= ~0x3ff;
4407 val32 |= tx0_a;
4408 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
4409
4410 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4411 val32 &= ~BIT(31);
4412 if ((x * oldval >> 7) & 0x1)
4413 val32 |= BIT(31);
4414 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4415
4416 y = result[candidate][1];
4417 if ((y & 0x00000200) != 0)
4418 y = y | 0xfffffc00;
4419 tx0_c = (y * oldval) >> 8;
4420
4421 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
4422 val32 &= ~0xf0000000;
4423 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
4424 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
4425
4426 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4427 val32 &= ~0x003f0000;
4428 val32 |= ((tx0_c & 0x3f) << 16);
4429 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
4430
4431 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4432 val32 &= ~BIT(29);
4433 if ((y * oldval >> 7) & 0x1)
4434 val32 |= BIT(29);
4435 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4436
4437 if (tx_only) {
4438 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
4439 return;
4440 }
4441
4442 reg = result[candidate][2];
4443
4444 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
4445 val32 &= ~0x3ff;
4446 val32 |= (reg & 0x3ff);
4447 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
4448
4449 reg = result[candidate][3] & 0x3F;
4450
4451 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
4452 val32 &= ~0xfc00;
4453 val32 |= ((reg << 10) & 0xfc00);
4454 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
4455
4456 reg = (result[candidate][3] >> 6) & 0xF;
4457
4458 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
4459 val32 &= ~0xf0000000;
4460 val32 |= (reg << 28);
4461 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
4462}
4463
4464static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
4465 bool iqk_ok, int result[][8],
4466 int candidate, bool tx_only)
4467{
4468 u32 oldval, x, tx1_a, reg;
4469 int y, tx1_c;
4470 u32 val32;
4471
4472 if (!iqk_ok)
4473 return;
4474
4475 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4476 oldval = val32 >> 22;
4477
4478 x = result[candidate][4];
4479 if ((x & 0x00000200) != 0)
4480 x = x | 0xfffffc00;
4481 tx1_a = (x * oldval) >> 8;
4482
4483 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4484 val32 &= ~0x3ff;
4485 val32 |= tx1_a;
4486 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
4487
4488 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4489 val32 &= ~BIT(27);
4490 if ((x * oldval >> 7) & 0x1)
4491 val32 |= BIT(27);
4492 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4493
4494 y = result[candidate][5];
4495 if ((y & 0x00000200) != 0)
4496 y = y | 0xfffffc00;
4497 tx1_c = (y * oldval) >> 8;
4498
4499 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
4500 val32 &= ~0xf0000000;
4501 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
4502 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
4503
4504 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4505 val32 &= ~0x003f0000;
4506 val32 |= ((tx1_c & 0x3f) << 16);
4507 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
4508
4509 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4510 val32 &= ~BIT(25);
4511 if ((y * oldval >> 7) & 0x1)
4512 val32 |= BIT(25);
4513 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4514
4515 if (tx_only) {
4516 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
4517 return;
4518 }
4519
4520 reg = result[candidate][6];
4521
4522 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
4523 val32 &= ~0x3ff;
4524 val32 |= (reg & 0x3ff);
4525 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
4526
4527 reg = result[candidate][7] & 0x3f;
4528
4529 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
4530 val32 &= ~0xfc00;
4531 val32 |= ((reg << 10) & 0xfc00);
4532 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
4533
4534 reg = (result[candidate][7] >> 6) & 0xf;
4535
4536 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
4537 val32 &= ~0x0000f000;
4538 val32 |= (reg << 12);
4539 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
4540}
4541
4542#define MAX_TOLERANCE 5
4543
4544static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
4545 int result[][8], int c1, int c2)
4546{
4547 u32 i, j, diff, simubitmap, bound = 0;
4548 int candidate[2] = {-1, -1}; /* for path A and path B */
4549 bool retval = true;
4550
4551 if (priv->tx_paths > 1)
4552 bound = 8;
4553 else
4554 bound = 4;
4555
4556 simubitmap = 0;
4557
4558 for (i = 0; i < bound; i++) {
4559 diff = (result[c1][i] > result[c2][i]) ?
4560 (result[c1][i] - result[c2][i]) :
4561 (result[c2][i] - result[c1][i]);
4562 if (diff > MAX_TOLERANCE) {
4563 if ((i == 2 || i == 6) && !simubitmap) {
4564 if (result[c1][i] + result[c1][i + 1] == 0)
4565 candidate[(i / 4)] = c2;
4566 else if (result[c2][i] + result[c2][i + 1] == 0)
4567 candidate[(i / 4)] = c1;
4568 else
4569 simubitmap = simubitmap | (1 << i);
4570 } else {
4571 simubitmap = simubitmap | (1 << i);
4572 }
4573 }
4574 }
4575
4576 if (simubitmap == 0) {
4577 for (i = 0; i < (bound / 4); i++) {
4578 if (candidate[i] >= 0) {
4579 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
4580 result[3][j] = result[candidate[i]][j];
4581 retval = false;
4582 }
4583 }
4584 return retval;
4585 } else if (!(simubitmap & 0x0f)) {
4586 /* path A OK */
4587 for (i = 0; i < 4; i++)
4588 result[3][i] = result[c1][i];
4589 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
4590 /* path B OK */
4591 for (i = 4; i < 8; i++)
4592 result[3][i] = result[c1][i];
4593 }
4594
4595 return false;
4596}
4597
85f46635
JS		 4598static bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
4599 int result[][8], int c1, int c2)
e1547c53
JS		 4600{
4601 u32 i, j, diff, simubitmap, bound = 0;
4602 int candidate[2] = {-1, -1}; /* for path A and path B */
4603 int tmp1, tmp2;
4604 bool retval = true;
4605
4606 if (priv->tx_paths > 1)
4607 bound = 8;
4608 else
4609 bound = 4;
4610
4611 simubitmap = 0;
4612
4613 for (i = 0; i < bound; i++) {
4614 if (i & 1) {
4615 if ((result[c1][i] & 0x00000200))
4616 tmp1 = result[c1][i] | 0xfffffc00;
4617 else
4618 tmp1 = result[c1][i];
4619
4620 if ((result[c2][i]& 0x00000200))
4621 tmp2 = result[c2][i] | 0xfffffc00;
4622 else
4623 tmp2 = result[c2][i];
4624 } else {
4625 tmp1 = result[c1][i];
4626 tmp2 = result[c2][i];
4627 }
4628
4629 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
4630
4631 if (diff > MAX_TOLERANCE) {
4632 if ((i == 2 || i == 6) && !simubitmap) {
4633 if (result[c1][i] + result[c1][i + 1] == 0)
4634 candidate[(i / 4)] = c2;
4635 else if (result[c2][i] + result[c2][i + 1] == 0)
4636 candidate[(i / 4)] = c1;
4637 else
4638 simubitmap = simubitmap | (1 << i);
4639 } else {
4640 simubitmap = simubitmap | (1 << i);
4641 }
4642 }
4643 }
4644
4645 if (simubitmap == 0) {
4646 for (i = 0; i < (bound / 4); i++) {
4647 if (candidate[i] >= 0) {
4648 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
4649 result[3][j] = result[candidate[i]][j];
4650 retval = false;
4651 }
4652 }
4653 return retval;
4654 } else {
4655 if (!(simubitmap & 0x03)) {
4656 /* path A TX OK */
4657 for (i = 0; i < 2; i++)
4658 result[3][i] = result[c1][i];
4659 }
4660
4661 if (!(simubitmap & 0x0c)) {
4662 /* path A RX OK */
4663 for (i = 2; i < 4; i++)
4664 result[3][i] = result[c1][i];
4665 }
4666
4667 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4668 /* path B RX OK */
4669 for (i = 4; i < 6; i++)
4670 result[3][i] = result[c1][i];
4671 }
4672
4673 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4674 /* path B RX OK */
4675 for (i = 6; i < 8; i++)
4676 result[3][i] = result[c1][i];
4677 }
4678 }
4679
4680 return false;
4681}
4682
26f1fad2
JS		 4683static void
4684rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
4685{
4686 int i;
4687
4688 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4689 backup[i] = rtl8xxxu_read8(priv, reg[i]);
4690
4691 backup[i] = rtl8xxxu_read32(priv, reg[i]);
4692}
4693
4694static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
4695 const u32 *reg, u32 *backup)
4696{
4697 int i;
4698
4699 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4700 rtl8xxxu_write8(priv, reg[i], backup[i]);
4701
4702 rtl8xxxu_write32(priv, reg[i], backup[i]);
4703}
4704
4705static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4706 u32 *backup, int count)
4707{
4708 int i;
4709
4710 for (i = 0; i < count; i++)
4711 backup[i] = rtl8xxxu_read32(priv, regs[i]);
4712}
4713
4714static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4715 u32 *backup, int count)
4716{
4717 int i;
4718
4719 for (i = 0; i < count; i++)
4720 rtl8xxxu_write32(priv, regs[i], backup[i]);
4721}
4722
4723
4724static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
4725 bool path_a_on)
4726{
4727 u32 path_on;
4728 int i;
4729
26f1fad2 4730 if (priv->tx_paths == 1) {
8634af5e
JS		 4731 path_on = priv->fops->adda_1t_path_on;
4732 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
26f1fad2 4733 } else {
8634af5e
JS		 4734 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
4735 priv->fops->adda_2t_path_on_b;
4736
26f1fad2
JS		 4737 rtl8xxxu_write32(priv, regs[0], path_on);
4738 }
4739
4740 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
4741 rtl8xxxu_write32(priv, regs[i], path_on);
4742}
4743
4744static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
4745 const u32 *regs, u32 *backup)
4746{
4747 int i = 0;
4748
4749 rtl8xxxu_write8(priv, regs[i], 0x3f);
4750
4751 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
4752 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
4753
4754 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
4755}
4756
4757static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
4758{
4759 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
4760 int result = 0;
4761
4762 /* path-A IQK setting */
4763 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
4764 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
4765 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
4766
4767 val32 = (priv->rf_paths > 1) ? 0x28160202 :
4768 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
4769 0x28160502;
4770 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
4771
4772 /* path-B IQK setting */
4773 if (priv->rf_paths > 1) {
4774 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
4775 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
4776 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
4777 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
4778 }
4779
4780 /* LO calibration setting */
4781 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
4782
4783 /* One shot, path A LOK & IQK */
4784 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4785 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4786
4787 mdelay(1);
4788
4789 /* Check failed */
4790 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4791 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4792 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4793 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4794
4795 if (!(reg_eac & BIT(28)) &&
4796 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4797 ((reg_e9c & 0x03ff0000) != 0x00420000))
4798 result |= 0x01;
4799 else /* If TX not OK, ignore RX */
4800 goto out;
4801
4802 /* If TX is OK, check whether RX is OK */
4803 if (!(reg_eac & BIT(27)) &&
4804 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4805 ((reg_eac & 0x03ff0000) != 0x00360000))
4806 result |= 0x02;
4807 else
4808 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
4809 __func__);
4810out:
4811 return result;
4812}
4813
4814static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
4815{
4816 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4817 int result = 0;
4818
4819 /* One shot, path B LOK & IQK */
4820 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4821 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4822
4823 mdelay(1);
4824
4825 /* Check failed */
4826 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4827 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4828 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4829 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4830 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4831
4832 if (!(reg_eac & BIT(31)) &&
4833 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4834 ((reg_ebc & 0x03ff0000) != 0x00420000))
4835 result |= 0x01;
4836 else
4837 goto out;
4838
4839 if (!(reg_eac & BIT(30)) &&
4840 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4841 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4842 result |= 0x02;
4843 else
4844 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4845 __func__);
4846out:
4847 return result;
4848}
4849
e1547c53
JS		 4850static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4851{
4852 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4853 int result = 0;
4854
4855 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4856
4857 /*
4858 * Leave IQK mode
4859 */
4860 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4861 val32 &= 0x000000ff;
4862 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4863
4864 /*
4865 * Enable path A PA in TX IQK mode
4866 */
4867 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4868 val32 |= 0x80000;
4869 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4870 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4871 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4872 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4873
4874 /*
4875 * Tx IQK setting
4876 */
4877 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4878 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4879
4880 /* path-A IQK setting */
4881 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4882 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4883 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4884 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4885
4886 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4887 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4888 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4889 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4890
4891 /* LO calibration setting */
4892 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4893
4894 /*
4895 * Enter IQK mode
4896 */
4897 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4898 val32 &= 0x000000ff;
4899 val32 |= 0x80800000;
4900 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4901
4902 /*
4903 * The vendor driver indicates the USB module is always using
4904 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4905 */
4906 if (priv->rf_paths > 1)
4907 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4908 else
4909 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4910
4911 /*
4912 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4913 * No trace of this in the 8192eu or 8188eu vendor drivers.
4914 */
4915 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4916
4917 /* One shot, path A LOK & IQK */
4918 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4919 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4920
4921 mdelay(1);
4922
4923 /* Restore Ant Path */
4924 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4925#ifdef RTL8723BU_BT
4926 /* GNT_BT = 1 */
4927 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4928#endif
4929
4930 /*
4931 * Leave IQK mode
4932 */
4933 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4934 val32 &= 0x000000ff;
4935 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4936
4937 /* Check failed */
4938 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4939 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4940 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4941
4942 val32 = (reg_e9c >> 16) & 0x3ff;
4943 if (val32 & 0x200)
4944 val32 = 0x400 - val32;
4945
4946 if (!(reg_eac & BIT(28)) &&
4947 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4948 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4949 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4950 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4951 val32 < 0xf)
4952 result |= 0x01;
4953 else /* If TX not OK, ignore RX */
4954 goto out;
4955
4956out:
4957 return result;
4958}
4959
4960static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4961{
4962 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4963 int result = 0;
4964
4965 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4966
4967 /*
4968 * Leave IQK mode
4969 */
4970 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4971 val32 &= 0x000000ff;
4972 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4973
4974 /*
4975 * Enable path A PA in TX IQK mode
4976 */
4977 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4978 val32 |= 0x80000;
4979 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4980 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4981 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4982 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4983
4984 /*
4985 * Tx IQK setting
4986 */
4987 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4988 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4989
4990 /* path-A IQK setting */
4991 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4992 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4993 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4994 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4995
4996 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4997 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4998 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4999 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
5000
5001 /* LO calibration setting */
5002 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
5003
5004 /*
5005 * Enter IQK mode
5006 */
5007 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5008 val32 &= 0x000000ff;
5009 val32 |= 0x80800000;
5010 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5011
5012 /*
5013 * The vendor driver indicates the USB module is always using
5014 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
5015 */
5016 if (priv->rf_paths > 1)
5017 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
5018 else
5019 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
5020
5021 /*
5022 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
5023 * No trace of this in the 8192eu or 8188eu vendor drivers.
5024 */
5025 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
5026
5027 /* One shot, path A LOK & IQK */
5028 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
5029 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5030
5031 mdelay(1);
5032
5033 /* Restore Ant Path */
5034 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
5035#ifdef RTL8723BU_BT
5036 /* GNT_BT = 1 */
5037 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
5038#endif
5039
5040 /*
5041 * Leave IQK mode
5042 */
5043 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5044 val32 &= 0x000000ff;
5045 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5046
5047 /* Check failed */
5048 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5049 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
5050 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
5051
5052 val32 = (reg_e9c >> 16) & 0x3ff;
5053 if (val32 & 0x200)
5054 val32 = 0x400 - val32;
5055
5056 if (!(reg_eac & BIT(28)) &&
5057 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
5058 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
5059 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
5060 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
5061 val32 < 0xf)
5062 result |= 0x01;
5063 else /* If TX not OK, ignore RX */
5064 goto out;
5065
5066 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
5067 ((reg_e9c & 0x3ff0000) >> 16);
5068 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
5069
5070 /*
5071 * Modify RX IQK mode
5072 */
5073 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5074 val32 &= 0x000000ff;
5075 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5076 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5077 val32 |= 0x80000;
5078 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5079 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
5080 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5081 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
5082
5083 /*
5084 * PA, PAD setting
5085 */
5086 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
5087 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
5088
5089 /*
5090 * RX IQK setting
5091 */
5092 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5093
5094 /* path-A IQK setting */
5095 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5096 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
5097 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5098 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5099
5100 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
5101 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
5102 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
5103 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
5104
5105 /* LO calibration setting */
5106 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
5107
5108 /*
5109 * Enter IQK mode
5110 */
5111 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5112 val32 &= 0x000000ff;
5113 val32 |= 0x80800000;
5114 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5115
5116 if (priv->rf_paths > 1)
5117 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
5118 else
5119 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
5120
5121 /*
5122 * Disable BT
5123 */
5124 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
5125
5126 /* One shot, path A LOK & IQK */
5127 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
5128 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5129
5130 mdelay(1);
5131
5132 /* Restore Ant Path */
5133 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
5134#ifdef RTL8723BU_BT
5135 /* GNT_BT = 1 */
5136 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
5137#endif
5138
5139 /*
5140 * Leave IQK mode
5141 */
5142 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5143 val32 &= 0x000000ff;
5144 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5145
5146 /* Check failed */
5147 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5148 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
5149
5150 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
5151
5152 val32 = (reg_eac >> 16) & 0x3ff;
5153 if (val32 & 0x200)
5154 val32 = 0x400 - val32;
5155
5156 if (!(reg_eac & BIT(27)) &&
5157 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
5158 ((reg_eac & 0x03ff0000) != 0x00360000) &&
5159 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
5160 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
5161 val32 < 0xf)
5162 result |= 0x02;
5163 else /* If TX not OK, ignore RX */
5164 goto out;
5165out:
5166 return result;
5167}
5168
f991f4e9
JS		 5169static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)
5170{
5171 u32 reg_eac, reg_e94, reg_e9c;
5172 int result = 0;
5173
5174 /*
5175 * TX IQK
5176 * PA/PAD controlled by 0x0
5177 */
5178 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5179 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180);
5180 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5181
5182 /* Path A IQK setting */
5183 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
5184 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5185 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5186 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5187
5188 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303);
5189 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000);
5190
5191 /* LO calibration setting */
5192 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
5193
5194 /* One shot, path A LOK & IQK */
5195 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
5196 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5197
5198 mdelay(10);
5199
5200 /* Check failed */
5201 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5202 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
5203 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
5204
5205 if (!(reg_eac & BIT(28)) &&
5206 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
5207 ((reg_e9c & 0x03ff0000) != 0x00420000))
5208 result |= 0x01;
5209
5210 return result;
5211}
5212
5213static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
5214{
5215 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
5216 int result = 0;
5217
5218 /* Leave IQK mode */
5219 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
5220
5221 /* Enable path A PA in TX IQK mode */
5222 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
5223 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
5224 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
5225 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);
5226
5227 /* PA/PAD control by 0x56, and set = 0x0 */
5228 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
5229 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
5230
5231 /* Enter IQK mode */
5232 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5233
5234 /* TX IQK setting */
5235 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5236 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5237
5238 /* path-A IQK setting */
5239 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
5240 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5241 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5242 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5243
5244 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
5245 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f);
5246
5247 /* LO calibration setting */
5248 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
5249
5250 /* One shot, path A LOK & IQK */
5251 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5252 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5253
5254 mdelay(10);
5255
5256 /* Check failed */
5257 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5258 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
5259 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
5260
5261 if (!(reg_eac & BIT(28)) &&
5262 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
5263 ((reg_e9c & 0x03ff0000) != 0x00420000)) {
5264 result |= 0x01;
5265 } else {
5266 /* PA/PAD controlled by 0x0 */
5267 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5268 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
5269 goto out;
5270 }
5271
5272 val32 = 0x80007c00 |
5273 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);
5274 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
5275
5276 /* Modify RX IQK mode table */
5277 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5278
5279 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
5280 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
5281 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
5282 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);
5283
5284 /* PA/PAD control by 0x56, and set = 0x0 */
5285 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
5286 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
5287
5288 /* Enter IQK mode */
5289 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5290
5291 /* IQK setting */
5292 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5293
5294 /* Path A IQK setting */
5295 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5296 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
5297 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5298 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5299
5300 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
5301 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
5302
5303 /* LO calibration setting */
5304 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
5305
5306 /* One shot, path A LOK & IQK */
5307 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5308 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5309
5310 mdelay(10);
5311
5312 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5313 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
5314
5315 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5316 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
5317
5318 if (!(reg_eac & BIT(27)) &&
5319 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
5320 ((reg_eac & 0x03ff0000) != 0x00360000))
5321 result |= 0x02;
5322 else
5323 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
5324 __func__);
5325
5326out:
5327 return result;
5328}
5329
5330static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)
5331{
5332 u32 reg_eac, reg_eb4, reg_ebc;
5333 int result = 0;
5334
5335 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5336 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180);
5337 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5338
5339 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5340 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5341
5342 /* Path B IQK setting */
5343 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5344 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5345 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
5346 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5347
5348 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2);
5349 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);
5350
5351 /* LO calibration setting */
5352 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911);
5353
5354 /* One shot, path A LOK & IQK */
5355 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5356 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5357
5358 mdelay(1);
5359
5360 /* Check failed */
5361 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5362 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5363 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5364
5365 if (!(reg_eac & BIT(31)) &&
5366 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
5367 ((reg_ebc & 0x03ff0000) != 0x00420000))
5368 result |= 0x01;
5369 else
5370 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
5371 __func__);
5372
5373 return result;
5374}
5375
5376static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
5377{
5378 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;
5379 int result = 0;
5380
5381 /* Leave IQK mode */
5382 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5383
5384 /* Enable path A PA in TX IQK mode */
5385 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
5386 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
5387 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
5388 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b);
5389
5390 /* PA/PAD control by 0x56, and set = 0x0 */
5391 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
5392 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
5393
5394 /* Enter IQK mode */
5395 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5396
5397 /* TX IQK setting */
5398 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5399 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5400
5401 /* path-A IQK setting */
5402 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5403 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5404 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
5405 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5406
5407 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f);
5408 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f);
5409
5410 /* LO calibration setting */
5411 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
5412
5413 /* One shot, path A LOK & IQK */
5414 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5415 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5416
5417 mdelay(10);
5418
5419 /* Check failed */
5420 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5421 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5422 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5423
5424 if (!(reg_eac & BIT(31)) &&
5425 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
5426 ((reg_ebc & 0x03ff0000) != 0x00420000)) {
5427 result |= 0x01;
5428 } else {
5429 /*
5430 * PA/PAD controlled by 0x0
5431 * Vendor driver restores RF_A here which I believe is a bug
5432 */
5433 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5434 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
5435 goto out;
5436 }
5437
5438 val32 = 0x80007c00 |
5439 (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);
5440 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
5441
5442 /* Modify RX IQK mode table */
5443 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5444
5445 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
5446 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
5447 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
5448 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa);
5449
5450 /* PA/PAD control by 0x56, and set = 0x0 */
5451 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
5452 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
5453
5454 /* Enter IQK mode */
5455 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5456
5457 /* IQK setting */
5458 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5459
5460 /* Path A IQK setting */
5461 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5462 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5463 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5464 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);
5465
5466 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
5467 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
5468
5469 /* LO calibration setting */
5470 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
5471
5472 /* One shot, path A LOK & IQK */
5473 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5474 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5475
5476 mdelay(10);
5477
5478 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5479 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
5480 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
5481
5482 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5483 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
5484
5485 if (!(reg_eac & BIT(30)) &&
5486 ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
5487 ((reg_ecc & 0x03ff0000) != 0x00360000))
5488 result |= 0x02;
5489 else
5490 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
5491 __func__);
5492
5493out:
5494 return result;
5495}
5496
26f1fad2
JS		 5497static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
5498 int result[][8], int t)
5499{
5500 struct device *dev = &priv->udev->dev;
5501 u32 i, val32;
5502 int path_a_ok, path_b_ok;
5503 int retry = 2;
5504 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
5505 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
5506 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
5507 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
5508 REG_TX_OFDM_BBON, REG_TX_TO_RX,
5509 REG_TX_TO_TX, REG_RX_CCK,
5510 REG_RX_OFDM, REG_RX_WAIT_RIFS,
5511 REG_RX_TO_RX, REG_STANDBY,
5512 REG_SLEEP, REG_PMPD_ANAEN
5513 };
5514 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
5515 REG_TXPAUSE, REG_BEACON_CTRL,
5516 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
5517 };
5518 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
5519 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
5520 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
5521 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
5522 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
5523 };
5524
5525 /*
5526 * Note: IQ calibration must be performed after loading
5527 * PHY_REG.txt , and radio_a, radio_b.txt
5528 */
5529
5530 if (t == 0) {
5531 /* Save ADDA parameters, turn Path A ADDA on */
5532 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
5533 RTL8XXXU_ADDA_REGS);
5534 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5535 rtl8xxxu_save_regs(priv, iqk_bb_regs,
5536 priv->bb_backup, RTL8XXXU_BB_REGS);
5537 }
5538
5539 rtl8xxxu_path_adda_on(priv, adda_regs, true);
5540
5541 if (t == 0) {
5542 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
5543 if (val32 & FPGA0_HSSI_PARM1_PI)
5544 priv->pi_enabled = 1;
5545 }
5546
5547 if (!priv->pi_enabled) {
5548 /* Switch BB to PI mode to do IQ Calibration. */
5549 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
5550 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
5551 }
5552
5553 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5554 val32 &= ~FPGA_RF_MODE_CCK;
5555 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
5556
5557 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
5558 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
5559 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
5560
cabb550e
JS		 5561 if (!priv->no_pape) {
5562 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
5563 val32 |= (FPGA0_RF_PAPE |
5564 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
5565 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
5566 }
26f1fad2
JS		 5567
5568 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
5569 val32 &= ~BIT(10);
5570 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
5571 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
5572 val32 &= ~BIT(10);
5573 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
5574
5575 if (priv->tx_paths > 1) {
5576 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
5577 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
5578 }
5579
5580 /* MAC settings */
5581 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
5582
5583 /* Page B init */
5584 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
5585
5586 if (priv->tx_paths > 1)
5587 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
5588
5589 /* IQ calibration setting */
5590 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5591 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5592 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5593
5594 for (i = 0; i < retry; i++) {
5595 path_a_ok = rtl8xxxu_iqk_path_a(priv);
5596 if (path_a_ok == 0x03) {
5597 val32 = rtl8xxxu_read32(priv,
5598 REG_TX_POWER_BEFORE_IQK_A);
5599 result[t][0] = (val32 >> 16) & 0x3ff;
5600 val32 = rtl8xxxu_read32(priv,
5601 REG_TX_POWER_AFTER_IQK_A);
5602 result[t][1] = (val32 >> 16) & 0x3ff;
5603 val32 = rtl8xxxu_read32(priv,
5604 REG_RX_POWER_BEFORE_IQK_A_2);
5605 result[t][2] = (val32 >> 16) & 0x3ff;
5606 val32 = rtl8xxxu_read32(priv,
5607 REG_RX_POWER_AFTER_IQK_A_2);
5608 result[t][3] = (val32 >> 16) & 0x3ff;
5609 break;
5610 } else if (i == (retry - 1) && path_a_ok == 0x01) {
5611 /* TX IQK OK */
5612 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
5613 __func__);
5614
5615 val32 = rtl8xxxu_read32(priv,
5616 REG_TX_POWER_BEFORE_IQK_A);
5617 result[t][0] = (val32 >> 16) & 0x3ff;
5618 val32 = rtl8xxxu_read32(priv,
5619 REG_TX_POWER_AFTER_IQK_A);
5620 result[t][1] = (val32 >> 16) & 0x3ff;
5621 }
5622 }
5623
5624 if (!path_a_ok)
5625 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
5626
5627 if (priv->tx_paths > 1) {
5628 /*
5629 * Path A into standby
5630 */
5631 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
5632 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
5633 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5634
5635 /* Turn Path B ADDA on */
5636 rtl8xxxu_path_adda_on(priv, adda_regs, false);
5637
5638 for (i = 0; i < retry; i++) {
5639 path_b_ok = rtl8xxxu_iqk_path_b(priv);
5640 if (path_b_ok == 0x03) {
5641 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5642 result[t][4] = (val32 >> 16) & 0x3ff;
5643 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5644 result[t][5] = (val32 >> 16) & 0x3ff;
5645 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
5646 result[t][6] = (val32 >> 16) & 0x3ff;
5647 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
5648 result[t][7] = (val32 >> 16) & 0x3ff;
5649 break;
5650 } else if (i == (retry - 1) && path_b_ok == 0x01) {
5651 /* TX IQK OK */
5652 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5653 result[t][4] = (val32 >> 16) & 0x3ff;
5654 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5655 result[t][5] = (val32 >> 16) & 0x3ff;
5656 }
5657 }
5658
5659 if (!path_b_ok)
5660 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
5661 }
5662
5663 /* Back to BB mode, load original value */
5664 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
5665
5666 if (t) {
5667 if (!priv->pi_enabled) {
5668 /*
5669 * Switch back BB to SI mode after finishing
5670 * IQ Calibration
5671 */
5672 val32 = 0x01000000;
5673 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
5674 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
5675 }
5676
5677 /* Reload ADDA power saving parameters */
5678 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
5679 RTL8XXXU_ADDA_REGS);
5680
5681 /* Reload MAC parameters */
5682 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5683
5684 /* Reload BB parameters */
5685 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
5686 priv->bb_backup, RTL8XXXU_BB_REGS);
5687
5688 /* Restore RX initial gain */
5689 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
5690
5691 if (priv->tx_paths > 1) {
5692 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
5693 0x00032ed3);
5694 }
5695
5696 /* Load 0xe30 IQC default value */
5697 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
5698 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
5699 }
5700}
5701
e1547c53
JS		 5702static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
5703 int result[][8], int t)
5704{
5705 struct device *dev = &priv->udev->dev;
5706 u32 i, val32;
5707 int path_a_ok /*, path_b_ok */;
5708 int retry = 2;
5709 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
5710 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
5711 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
5712 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
5713 REG_TX_OFDM_BBON, REG_TX_TO_RX,
5714 REG_TX_TO_TX, REG_RX_CCK,
5715 REG_RX_OFDM, REG_RX_WAIT_RIFS,
5716 REG_RX_TO_RX, REG_STANDBY,
5717 REG_SLEEP, REG_PMPD_ANAEN
5718 };
5719 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
5720 REG_TXPAUSE, REG_BEACON_CTRL,
5721 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
5722 };
5723 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
5724 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
5725 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
5726 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
5727 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
5728 };
5729 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
5730 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
5731
5732 /*
5733 * Note: IQ calibration must be performed after loading
5734 * PHY_REG.txt , and radio_a, radio_b.txt
5735 */
5736
5737 if (t == 0) {
5738 /* Save ADDA parameters, turn Path A ADDA on */
5739 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
5740 RTL8XXXU_ADDA_REGS);
5741 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5742 rtl8xxxu_save_regs(priv, iqk_bb_regs,
5743 priv->bb_backup, RTL8XXXU_BB_REGS);
5744 }
5745
5746 rtl8xxxu_path_adda_on(priv, adda_regs, true);
5747
5748 /* MAC settings */
5749 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
5750
5751 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
5752 val32 |= 0x0f000000;
5753 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
5754
5755 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
5756 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
5757 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
5758
e1547c53
JS		 5759 /*
5760 * RX IQ calibration setting for 8723B D cut large current issue
5761 * when leaving IPS
5762 */
5763 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5764 val32 &= 0x000000ff;
5765 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5766
5767 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5768 val32 |= 0x80000;
5769 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5770
5771 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
5772 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5773 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
5774
5775 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5776 val32 |= 0x20;
5777 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5778
5779 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
5780
5781 for (i = 0; i < retry; i++) {
5782 path_a_ok = rtl8723bu_iqk_path_a(priv);
5783 if (path_a_ok == 0x01) {
5784 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5785 val32 &= 0x000000ff;
5786 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5787
e1547c53
JS		 5788 val32 = rtl8xxxu_read32(priv,
5789 REG_TX_POWER_BEFORE_IQK_A);
5790 result[t][0] = (val32 >> 16) & 0x3ff;
5791 val32 = rtl8xxxu_read32(priv,
5792 REG_TX_POWER_AFTER_IQK_A);
5793 result[t][1] = (val32 >> 16) & 0x3ff;
5794
5795 break;
5796 }
5797 }
5798
5799 if (!path_a_ok)
5800 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
5801
5802 for (i = 0; i < retry; i++) {
5803 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
5804 if (path_a_ok == 0x03) {
5805 val32 = rtl8xxxu_read32(priv,
5806 REG_RX_POWER_BEFORE_IQK_A_2);
5807 result[t][2] = (val32 >> 16) & 0x3ff;
5808 val32 = rtl8xxxu_read32(priv,
5809 REG_RX_POWER_AFTER_IQK_A_2);
5810 result[t][3] = (val32 >> 16) & 0x3ff;
5811
5812 break;
5813 }
5814 }
5815
5816 if (!path_a_ok)
5817 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
5818
5819 if (priv->tx_paths > 1) {
5820#if 1
5821 dev_warn(dev, "%s: Path B not supported\n", __func__);
5822#else
5823
5824 /*
5825 * Path A into standby
5826 */
5827 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5828 val32 &= 0x000000ff;
5829 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5830 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
5831
5832 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5833 val32 &= 0x000000ff;
5834 val32 |= 0x80800000;
5835 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5836
5837 /* Turn Path B ADDA on */
5838 rtl8xxxu_path_adda_on(priv, adda_regs, false);
5839
5840 for (i = 0; i < retry; i++) {
5841 path_b_ok = rtl8xxxu_iqk_path_b(priv);
5842 if (path_b_ok == 0x03) {
5843 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5844 result[t][4] = (val32 >> 16) & 0x3ff;
5845 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5846 result[t][5] = (val32 >> 16) & 0x3ff;
5847 break;
5848 }
5849 }
5850
5851 if (!path_b_ok)
5852 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
5853
5854 for (i = 0; i < retry; i++) {
5855 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
5856 if (path_a_ok == 0x03) {
5857 val32 = rtl8xxxu_read32(priv,
5858 REG_RX_POWER_BEFORE_IQK_B_2);
5859 result[t][6] = (val32 >> 16) & 0x3ff;
5860 val32 = rtl8xxxu_read32(priv,
5861 REG_RX_POWER_AFTER_IQK_B_2);
5862 result[t][7] = (val32 >> 16) & 0x3ff;
5863 break;
5864 }
5865 }
5866
5867 if (!path_b_ok)
5868 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
5869#endif
5870 }
5871
5872 /* Back to BB mode, load original value */
5873 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5874 val32 &= 0x000000ff;
5875 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5876
5877 if (t) {
5878 /* Reload ADDA power saving parameters */
5879 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
5880 RTL8XXXU_ADDA_REGS);
5881
5882 /* Reload MAC parameters */
5883 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5884
5885 /* Reload BB parameters */
5886 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
5887 priv->bb_backup, RTL8XXXU_BB_REGS);
5888
5889 /* Restore RX initial gain */
5890 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5891 val32 &= 0xffffff00;
5892 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
5893 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
5894
5895 if (priv->tx_paths > 1) {
5896 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
5897 val32 &= 0xffffff00;
5898 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5899 val32 | 0x50);
5900 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5901 val32 | xb_agc);
5902 }
5903
5904 /* Load 0xe30 IQC default value */
5905 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
5906 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
5907 }
5908}
5909
f991f4e9
JS		 5910static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
5911 int result[][8], int t)
5912{
5913 struct device *dev = &priv->udev->dev;
5914 u32 i, val32;
5915 int path_a_ok, path_b_ok;
5916 int retry = 2;
5917 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
5918 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
5919 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
5920 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
5921 REG_TX_OFDM_BBON, REG_TX_TO_RX,
5922 REG_TX_TO_TX, REG_RX_CCK,
5923 REG_RX_OFDM, REG_RX_WAIT_RIFS,
5924 REG_RX_TO_RX, REG_STANDBY,
5925 REG_SLEEP, REG_PMPD_ANAEN
5926 };
5927 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
5928 REG_TXPAUSE, REG_BEACON_CTRL,
5929 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
5930 };
5931 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
5932 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
5933 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
5934 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
5935 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING
5936 };
5937 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
5938 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
5939
5940 /*
5941 * Note: IQ calibration must be performed after loading
5942 * PHY_REG.txt , and radio_a, radio_b.txt
5943 */
5944
5945 if (t == 0) {
5946 /* Save ADDA parameters, turn Path A ADDA on */
5947 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
5948 RTL8XXXU_ADDA_REGS);
5949 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5950 rtl8xxxu_save_regs(priv, iqk_bb_regs,
5951 priv->bb_backup, RTL8XXXU_BB_REGS);
5952 }
5953
5954 rtl8xxxu_path_adda_on(priv, adda_regs, true);
5955
5956 /* MAC settings */
5957 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
5958
5959 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
5960 val32 |= 0x0f000000;
5961 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
5962
5963 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
5964 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
5965 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200);
5966
5967 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
5968 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
5969 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
5970
5971 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
5972 val32 |= BIT(10);
5973 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
5974 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
5975 val32 |= BIT(10);
5976 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
5977
5978 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5979 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5980 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5981
5982 for (i = 0; i < retry; i++) {
5983 path_a_ok = rtl8192eu_iqk_path_a(priv);
5984 if (path_a_ok == 0x01) {
5985 val32 = rtl8xxxu_read32(priv,
5986 REG_TX_POWER_BEFORE_IQK_A);
5987 result[t][0] = (val32 >> 16) & 0x3ff;
5988 val32 = rtl8xxxu_read32(priv,
5989 REG_TX_POWER_AFTER_IQK_A);
5990 result[t][1] = (val32 >> 16) & 0x3ff;
5991
5992 break;
5993 }
5994 }
5995
5996 if (!path_a_ok)
5997 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
5998
5999 for (i = 0; i < retry; i++) {
6000 path_a_ok = rtl8192eu_rx_iqk_path_a(priv);
6001 if (path_a_ok == 0x03) {
6002 val32 = rtl8xxxu_read32(priv,
6003 REG_RX_POWER_BEFORE_IQK_A_2);
6004 result[t][2] = (val32 >> 16) & 0x3ff;
6005 val32 = rtl8xxxu_read32(priv,
6006 REG_RX_POWER_AFTER_IQK_A_2);
6007 result[t][3] = (val32 >> 16) & 0x3ff;
6008
6009 break;
6010 }
6011 }
6012
6013 if (!path_a_ok)
6014 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
6015
6016 if (priv->rf_paths > 1) {
f991f4e9
JS		 6017 /* Path A into standby */
6018 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
6019 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
6020 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
6021
6022 /* Turn Path B ADDA on */
6023 rtl8xxxu_path_adda_on(priv, adda_regs, false);
6024
6025 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
6026 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
6027 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
6028
6029 for (i = 0; i < retry; i++) {
6030 path_b_ok = rtl8192eu_iqk_path_b(priv);
6031 if (path_b_ok == 0x01) {
6032 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
6033 result[t][4] = (val32 >> 16) & 0x3ff;
6034 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
6035 result[t][5] = (val32 >> 16) & 0x3ff;
6036 break;
6037 }
6038 }
6039
6040 if (!path_b_ok)
6041 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
6042
6043 for (i = 0; i < retry; i++) {
6044 path_b_ok = rtl8192eu_rx_iqk_path_b(priv);
6045 if (path_a_ok == 0x03) {
6046 val32 = rtl8xxxu_read32(priv,
6047 REG_RX_POWER_BEFORE_IQK_B_2);
6048 result[t][6] = (val32 >> 16) & 0x3ff;
6049 val32 = rtl8xxxu_read32(priv,
6050 REG_RX_POWER_AFTER_IQK_B_2);
6051 result[t][7] = (val32 >> 16) & 0x3ff;
6052 break;
6053 }
6054 }
6055
6056 if (!path_b_ok)
6057 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
6058 }
6059
6060 /* Back to BB mode, load original value */
6061 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
6062
6063 if (t) {
6064 /* Reload ADDA power saving parameters */
6065 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
6066 RTL8XXXU_ADDA_REGS);
6067
6068 /* Reload MAC parameters */
6069 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
6070
6071 /* Reload BB parameters */
6072 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
6073 priv->bb_backup, RTL8XXXU_BB_REGS);
6074
6075 /* Restore RX initial gain */
6076 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
6077 val32 &= 0xffffff00;
6078 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
6079 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
6080
6081 if (priv->rf_paths > 1) {
6082 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
6083 val32 &= 0xffffff00;
6084 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
6085 val32 | 0x50);
6086 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
6087 val32 | xb_agc);
6088 }
6089
6090 /* Load 0xe30 IQC default value */
6091 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
6092 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
6093 }
6094}
6095
c7a5a190
JS		 6096static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
6097{
6098 struct h2c_cmd h2c;
6099
6100 if (priv->fops->mbox_ext_width < 4)
6101 return;
6102
6103 memset(&h2c, 0, sizeof(struct h2c_cmd));
6104 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
6105 h2c.bt_wlan_calibration.data = start;
6106
6107 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
6108}
6109
28466e92 6110static void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 6111{
6112 struct device *dev = &priv->udev->dev;
6113 int result[4][8]; /* last is final result */
6114 int i, candidate;
6115 bool path_a_ok, path_b_ok;
6116 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
6117 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
6118 s32 reg_tmp = 0;
6119 bool simu;
6120
c7a5a190
JS		 6121 rtl8xxxu_prepare_calibrate(priv, 1);
6122
26f1fad2
JS		 6123 memset(result, 0, sizeof(result));
6124 candidate = -1;
6125
6126 path_a_ok = false;
6127 path_b_ok = false;
6128
6129 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6130
6131 for (i = 0; i < 3; i++) {
6132 rtl8xxxu_phy_iqcalibrate(priv, result, i);
6133
6134 if (i == 1) {
6135 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
6136 if (simu) {
6137 candidate = 0;
6138 break;
6139 }
6140 }
6141
6142 if (i == 2) {
6143 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
6144 if (simu) {
6145 candidate = 0;
6146 break;
6147 }
6148
6149 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
6150 if (simu) {
6151 candidate = 1;
6152 } else {
6153 for (i = 0; i < 8; i++)
6154 reg_tmp += result[3][i];
6155
6156 if (reg_tmp)
6157 candidate = 3;
6158 else
6159 candidate = -1;
6160 }
6161 }
6162 }
6163
6164 for (i = 0; i < 4; i++) {
6165 reg_e94 = result[i][0];
6166 reg_e9c = result[i][1];
6167 reg_ea4 = result[i][2];
6168 reg_eac = result[i][3];
6169 reg_eb4 = result[i][4];
6170 reg_ebc = result[i][5];
6171 reg_ec4 = result[i][6];
6172 reg_ecc = result[i][7];
6173 }
6174
6175 if (candidate >= 0) {
6176 reg_e94 = result[candidate][0];
6177 priv->rege94 = reg_e94;
6178 reg_e9c = result[candidate][1];
6179 priv->rege9c = reg_e9c;
6180 reg_ea4 = result[candidate][2];
6181 reg_eac = result[candidate][3];
6182 reg_eb4 = result[candidate][4];
6183 priv->regeb4 = reg_eb4;
6184 reg_ebc = result[candidate][5];
6185 priv->regebc = reg_ebc;
6186 reg_ec4 = result[candidate][6];
6187 reg_ecc = result[candidate][7];
6188 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
6189 dev_dbg(dev,
6190 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6191 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
6192 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
6193 path_a_ok = true;
6194 path_b_ok = true;
6195 } else {
6196 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
6197 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
6198 }
6199
6200 if (reg_e94 && candidate >= 0)
6201 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
6202 candidate, (reg_ea4 == 0));
6203
6204 if (priv->tx_paths > 1 && reg_eb4)
6205 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
6206 candidate, (reg_ec4 == 0));
6207
04a74a9f 6208 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
26f1fad2 6209 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
c7a5a190
JS		 6210
6211 rtl8xxxu_prepare_calibrate(priv, 0);
26f1fad2
JS		 6212}
6213
e1547c53
JS		 6214static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
6215{
6216 struct device *dev = &priv->udev->dev;
6217 int result[4][8]; /* last is final result */
6218 int i, candidate;
6219 bool path_a_ok, path_b_ok;
6220 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
6221 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
6222 u32 val32, bt_control;
6223 s32 reg_tmp = 0;
6224 bool simu;
6225
6226 rtl8xxxu_prepare_calibrate(priv, 1);
6227
6228 memset(result, 0, sizeof(result));
6229 candidate = -1;
6230
6231 path_a_ok = false;
6232 path_b_ok = false;
6233
6234 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
6235
6236 for (i = 0; i < 3; i++) {
6237 rtl8723bu_phy_iqcalibrate(priv, result, i);
6238
6239 if (i == 1) {
85f46635
JS		 6240 simu = rtl8xxxu_gen2_simularity_compare(priv,
6241 result, 0, 1);
e1547c53
JS		 6242 if (simu) {
6243 candidate = 0;
6244 break;
6245 }
6246 }
6247
6248 if (i == 2) {
85f46635
JS		 6249 simu = rtl8xxxu_gen2_simularity_compare(priv,
6250 result, 0, 2);
e1547c53
JS		 6251 if (simu) {
6252 candidate = 0;
6253 break;
6254 }
6255
85f46635
JS		 6256 simu = rtl8xxxu_gen2_simularity_compare(priv,
6257 result, 1, 2);
e1547c53
JS		 6258 if (simu) {
6259 candidate = 1;
6260 } else {
6261 for (i = 0; i < 8; i++)
6262 reg_tmp += result[3][i];
6263
6264 if (reg_tmp)
6265 candidate = 3;
6266 else
6267 candidate = -1;
6268 }
6269 }
6270 }
6271
6272 for (i = 0; i < 4; i++) {
6273 reg_e94 = result[i][0];
6274 reg_e9c = result[i][1];
6275 reg_ea4 = result[i][2];
6276 reg_eac = result[i][3];
6277 reg_eb4 = result[i][4];
6278 reg_ebc = result[i][5];
6279 reg_ec4 = result[i][6];
6280 reg_ecc = result[i][7];
6281 }
6282
6283 if (candidate >= 0) {
6284 reg_e94 = result[candidate][0];
6285 priv->rege94 = reg_e94;
6286 reg_e9c = result[candidate][1];
6287 priv->rege9c = reg_e9c;
6288 reg_ea4 = result[candidate][2];
6289 reg_eac = result[candidate][3];
6290 reg_eb4 = result[candidate][4];
6291 priv->regeb4 = reg_eb4;
6292 reg_ebc = result[candidate][5];
6293 priv->regebc = reg_ebc;
6294 reg_ec4 = result[candidate][6];
6295 reg_ecc = result[candidate][7];
6296 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
6297 dev_dbg(dev,
6298 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6299 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
6300 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
6301 path_a_ok = true;
6302 path_b_ok = true;
6303 } else {
6304 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
6305 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
6306 }
6307
6308 if (reg_e94 && candidate >= 0)
6309 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
6310 candidate, (reg_ea4 == 0));
6311
6312 if (priv->tx_paths > 1 && reg_eb4)
6313 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
6314 candidate, (reg_ec4 == 0));
6315
04a74a9f 6316 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
e1547c53
JS		 6317 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
6318
6319 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
6320
6321 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
6322 val32 |= 0x80000;
6323 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
6324 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
6325 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
6326 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
6327 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
6328 val32 |= 0x20;
6329 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
6330 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
6331
15f9dc99
JS		 6332 if (priv->rf_paths > 1)
6333 dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__);
6334
e1547c53
JS		 6335 rtl8xxxu_prepare_calibrate(priv, 0);
6336}
6337
f991f4e9
JS		 6338static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
6339{
6340 struct device *dev = &priv->udev->dev;
6341 int result[4][8]; /* last is final result */
6342 int i, candidate;
6343 bool path_a_ok, path_b_ok;
6344 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
6345 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
6346 bool simu;
6347
6348 memset(result, 0, sizeof(result));
6349 candidate = -1;
6350
6351 path_a_ok = false;
6352 path_b_ok = false;
6353
6354 for (i = 0; i < 3; i++) {
6355 rtl8192eu_phy_iqcalibrate(priv, result, i);
6356
6357 if (i == 1) {
85f46635
JS		 6358 simu = rtl8xxxu_gen2_simularity_compare(priv,
6359 result, 0, 1);
f991f4e9
JS		 6360 if (simu) {
6361 candidate = 0;
6362 break;
6363 }
6364 }
6365
6366 if (i == 2) {
85f46635
JS		 6367 simu = rtl8xxxu_gen2_simularity_compare(priv,
6368 result, 0, 2);
f991f4e9
JS		 6369 if (simu) {
6370 candidate = 0;
6371 break;
6372 }
6373
85f46635
JS		 6374 simu = rtl8xxxu_gen2_simularity_compare(priv,
6375 result, 1, 2);
f991f4e9
JS		 6376 if (simu)
6377 candidate = 1;
6378 else
6379 candidate = 3;
6380 }
6381 }
6382
6383 for (i = 0; i < 4; i++) {
6384 reg_e94 = result[i][0];
6385 reg_e9c = result[i][1];
6386 reg_ea4 = result[i][2];
6387 reg_eac = result[i][3];
6388 reg_eb4 = result[i][4];
6389 reg_ebc = result[i][5];
6390 reg_ec4 = result[i][6];
6391 reg_ecc = result[i][7];
6392 }
6393
6394 if (candidate >= 0) {
6395 reg_e94 = result[candidate][0];
6396 priv->rege94 = reg_e94;
6397 reg_e9c = result[candidate][1];
6398 priv->rege9c = reg_e9c;
6399 reg_ea4 = result[candidate][2];
6400 reg_eac = result[candidate][3];
6401 reg_eb4 = result[candidate][4];
6402 priv->regeb4 = reg_eb4;
6403 reg_ebc = result[candidate][5];
6404 priv->regebc = reg_ebc;
6405 reg_ec4 = result[candidate][6];
6406 reg_ecc = result[candidate][7];
6407 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
6408 dev_dbg(dev,
6409 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6410 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
6411 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
6412 path_a_ok = true;
6413 path_b_ok = true;
6414 } else {
6415 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
6416 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
6417 }
6418
6419 if (reg_e94 && candidate >= 0)
6420 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
6421 candidate, (reg_ea4 == 0));
6422
6423 if (priv->rf_paths > 1)
6424 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
6425 candidate, (reg_ec4 == 0));
6426
04a74a9f 6427 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
f991f4e9
JS		 6428 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
6429}
6430
26f1fad2
JS		 6431static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
6432{
6433 u32 val32;
6434 u32 rf_amode, rf_bmode = 0, lstf;
6435
6436 /* Check continuous TX and Packet TX */
6437 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
6438
6439 if (lstf & OFDM_LSTF_MASK) {
6440 /* Disable all continuous TX */
6441 val32 = lstf & ~OFDM_LSTF_MASK;
6442 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
6443
6444 /* Read original RF mode Path A */
6445 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
6446
6447 /* Set RF mode to standby Path A */
6448 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
6449 (rf_amode & 0x8ffff) | 0x10000);
6450
6451 /* Path-B */
6452 if (priv->tx_paths > 1) {
6453 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
6454 RF6052_REG_AC);
6455
6456 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
6457 (rf_bmode & 0x8ffff) | 0x10000);
6458 }
6459 } else {
6460 /* Deal with Packet TX case */
6461 /* block all queues */
6462 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6463 }
6464
6465 /* Start LC calibration */
0d698dec
JS		 6466 if (priv->fops->has_s0s1)
6467 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
26f1fad2
JS		 6468 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
6469 val32 |= 0x08000;
6470 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
6471
6472 msleep(100);
6473
0d698dec
JS		 6474 if (priv->fops->has_s0s1)
6475 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
6476
26f1fad2
JS		 6477 /* Restore original parameters */
6478 if (lstf & OFDM_LSTF_MASK) {
6479 /* Path-A */
6480 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
6481 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
6482
6483 /* Path-B */
6484 if (priv->tx_paths > 1)
6485 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
6486 rf_bmode);
6487 } else /* Deal with Packet TX case */
6488 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
6489}
6490
6491static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
6492{
6493 int i;
6494 u16 reg;
6495
6496 reg = REG_MACID;
6497
6498 for (i = 0; i < ETH_ALEN; i++)
6499 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
6500
6501 return 0;
6502}
6503
6504static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
6505{
6506 int i;
6507 u16 reg;
6508
6509 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
6510
6511 reg = REG_BSSID;
6512
6513 for (i = 0; i < ETH_ALEN; i++)
6514 rtl8xxxu_write8(priv, reg + i, bssid[i]);
6515
6516 return 0;
6517}
6518
6519static void
6520rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
6521{
6522 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
6523 u8 max_agg = 0xf;
6524 int i;
6525
6526 ampdu_factor = 1 << (ampdu_factor + 2);
6527 if (ampdu_factor > max_agg)
6528 ampdu_factor = max_agg;
6529
6530 for (i = 0; i < 4; i++) {
6531 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
6532 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
6533
6534 if ((vals[i] & 0x0f) > ampdu_factor)
6535 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
6536
6537 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
6538 }
6539}
6540
6541static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
6542{
6543 u8 val8;
6544
6545 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
6546 val8 &= 0xf8;
6547 val8 |= density;
6548 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
6549}
6550
6551static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
6552{
6553 u8 val8;
37ba4b62 6554 int count, ret = 0;
26f1fad2
JS		 6555
6556 /* Start of rtl8723AU_card_enable_flow */
6557 /* Act to Cardemu sequence*/
6558 /* Turn off RF */
6559 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
6560
6561 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
6562 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6563 val8 &= ~LEDCFG2_DPDT_SELECT;
6564 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6565
6566 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
6567 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6568 val8 |= BIT(1);
6569 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6570
6571 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6572 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6573 if ((val8 & BIT(1)) == 0)
6574 break;
6575 udelay(10);
6576 }
6577
6578 if (!count) {
6579 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
6580 __func__);
6581 ret = -EBUSY;
6582 goto exit;
6583 }
6584
6585 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
6586 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6587 val8 |= SYS_ISO_ANALOG_IPS;
6588 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6589
6590 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
6591 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6592 val8 &= ~LDOA15_ENABLE;
6593 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6594
6595exit:
6596 return ret;
6597}
6598
fe37d5f6
JS		 6599static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
6600{
6601 u8 val8;
6602 u16 val16;
6603 u32 val32;
37ba4b62 6604 int count, ret = 0;
fe37d5f6
JS		 6605
6606 /* Turn off RF */
6607 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
6608
6609 /* Enable rising edge triggering interrupt */
6610 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
6611 val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
6612 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
6613
6614 /* Release WLON reset 0x04[16]= 1*/
8e254960 6615 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
fe37d5f6 6616 val32 |= APS_FSMCO_WLON_RESET;
8e254960 6617 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
fe37d5f6
JS		 6618
6619 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
6620 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6621 val8 |= BIT(1);
6622 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6623
6624 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6625 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6626 if ((val8 & BIT(1)) == 0)
6627 break;
6628 udelay(10);
6629 }
6630
6631 if (!count) {
6632 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
6633 __func__);
6634 ret = -EBUSY;
6635 goto exit;
6636 }
6637
6638 /* Enable BT control XTAL setting */
6639 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
6640 val8 &= ~AFE_MISC_WL_XTAL_CTRL;
6641 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
6642
6643 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
6644 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6645 val8 |= SYS_ISO_ANALOG_IPS;
6646 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6647
6648 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
6649 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6650 val8 &= ~LDOA15_ENABLE;
6651 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6652
6653exit:
6654 return ret;
6655}
6656
26f1fad2
JS		 6657static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
6658{
6659 u8 val8;
6660 u8 val32;
37ba4b62 6661 int count, ret = 0;
26f1fad2
JS		 6662
6663 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6664
6665 /*
6666 * Poll - wait for RX packet to complete
6667 */
6668 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6669 val32 = rtl8xxxu_read32(priv, 0x5f8);
6670 if (!val32)
6671 break;
6672 udelay(10);
6673 }
6674
6675 if (!count) {
6676 dev_warn(&priv->udev->dev,
6677 "%s: RX poll timed out (0x05f8)\n", __func__);
6678 ret = -EBUSY;
6679 goto exit;
6680 }
6681
6682 /* Disable CCK and OFDM, clock gated */
6683 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
6684 val8 &= ~SYS_FUNC_BBRSTB;
6685 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
6686
6687 udelay(2);
6688
6689 /* Reset baseband */
6690 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
6691 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
6692 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
6693
6694 /* Reset MAC TRX */
6695 val8 = rtl8xxxu_read8(priv, REG_CR);
6696 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
6697 rtl8xxxu_write8(priv, REG_CR, val8);
6698
6699 /* Reset MAC TRX */
6700 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
6701 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
6702 rtl8xxxu_write8(priv, REG_CR + 1, val8);
6703
6704 /* Respond TX OK to scheduler */
6705 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
6706 val8 |= DUAL_TSF_TX_OK;
6707 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
6708
6709exit:
6710 return ret;
6711}
6712
c05a9dbf 6713static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 6714{
6715 u8 val8;
6716
6717 /* Clear suspend enable and power down enable*/
6718 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6719 val8 &= ~(BIT(3) | BIT(7));
6720 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6721
6722 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
6723 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
6724 val8 &= ~BIT(0);
6725 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
6726
6727 /* 0x04[12:11] = 11 enable WL suspend*/
6728 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6729 val8 &= ~(BIT(3) | BIT(4));
6730 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6731}
6732
c05a9dbf
JS		 6733static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
6734{
6735 u8 val8;
6736
6737 /* Clear suspend enable and power down enable*/
6738 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6739 val8 &= ~(BIT(3) | BIT(4));
6740 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6741}
6742
6743static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
6744{
6745 u8 val8;
6746 u32 val32;
6747 int count, ret = 0;
6748
6749 /* disable HWPDN 0x04[15]=0*/
6750 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6751 val8 &= ~BIT(7);
6752 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6753
6754 /* disable SW LPS 0x04[10]= 0 */
6755 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6756 val8 &= ~BIT(2);
6757 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6758
6759 /* disable WL suspend*/
6760 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6761 val8 &= ~(BIT(3) | BIT(4));
6762 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6763
6764 /* wait till 0x04[17] = 1 power ready*/
6765 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6766 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6767 if (val32 & BIT(17))
6768 break;
6769
6770 udelay(10);
6771 }
6772
6773 if (!count) {
6774 ret = -EBUSY;
6775 goto exit;
6776 }
6777
6778 /* We should be able to optimize the following three entries into one */
6779
6780 /* release WLON reset 0x04[16]= 1*/
6781 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
6782 val8 |= BIT(0);
6783 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
6784
6785 /* set, then poll until 0 */
6786 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6787 val32 |= APS_FSMCO_MAC_ENABLE;
6788 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6789
6790 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6791 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6792 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
6793 ret = 0;
6794 break;
6795 }
6796 udelay(10);
6797 }
6798
6799 if (!count) {
6800 ret = -EBUSY;
6801 goto exit;
6802 }
6803
6804exit:
6805 return ret;
6806}
6807
6808static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 6809{
6810 u8 val8;
6811 u32 val32;
6812 int count, ret = 0;
6813
6814 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
6815 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6816 val8 |= LDOA15_ENABLE;
6817 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6818
6819 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
6820 val8 = rtl8xxxu_read8(priv, 0x0067);
6821 val8 &= ~BIT(4);
6822 rtl8xxxu_write8(priv, 0x0067, val8);
6823
6824 mdelay(1);
6825
6826 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
6827 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6828 val8 &= ~SYS_ISO_ANALOG_IPS;
6829 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6830
6831 /* disable SW LPS 0x04[10]= 0 */
6832 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6833 val8 &= ~BIT(2);
6834 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6835
6836 /* wait till 0x04[17] = 1 power ready*/
6837 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6838 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6839 if (val32 & BIT(17))
6840 break;
6841
6842 udelay(10);
6843 }
6844
6845 if (!count) {
6846 ret = -EBUSY;
6847 goto exit;
6848 }
6849
6850 /* We should be able to optimize the following three entries into one */
6851
6852 /* release WLON reset 0x04[16]= 1*/
6853 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
6854 val8 |= BIT(0);
6855 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
6856
6857 /* disable HWPDN 0x04[15]= 0*/
6858 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6859 val8 &= ~BIT(7);
6860 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6861
6862 /* disable WL suspend*/
6863 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6864 val8 &= ~(BIT(3) | BIT(4));
6865 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6866
6867 /* set, then poll until 0 */
6868 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6869 val32 |= APS_FSMCO_MAC_ENABLE;
6870 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6871
6872 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6873 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6874 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
6875 ret = 0;
6876 break;
6877 }
6878 udelay(10);
6879 }
6880
6881 if (!count) {
6882 ret = -EBUSY;
6883 goto exit;
6884 }
6885
6886 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
6887 /*
6888 * Note: Vendor driver actually clears this bit, despite the
6889 * documentation claims it's being set!
6890 */
6891 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6892 val8 |= LEDCFG2_DPDT_SELECT;
6893 val8 &= ~LEDCFG2_DPDT_SELECT;
6894 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6895
6896exit:
6897 return ret;
6898}
6899
42836db1
JS		 6900static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
6901{
6902 u8 val8;
6903 u32 val32;
6904 int count, ret = 0;
6905
6906 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
6907 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6908 val8 |= LDOA15_ENABLE;
6909 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6910
6911 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
6912 val8 = rtl8xxxu_read8(priv, 0x0067);
6913 val8 &= ~BIT(4);
6914 rtl8xxxu_write8(priv, 0x0067, val8);
6915
6916 mdelay(1);
6917
6918 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
6919 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6920 val8 &= ~SYS_ISO_ANALOG_IPS;
6921 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6922
6923 /* Disable SW LPS 0x04[10]= 0 */
6924 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
6925 val32 &= ~APS_FSMCO_SW_LPS;
6926 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6927
6928 /* Wait until 0x04[17] = 1 power ready */
6929 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6930 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6931 if (val32 & BIT(17))
6932 break;
6933
6934 udelay(10);
6935 }
6936
6937 if (!count) {
6938 ret = -EBUSY;
6939 goto exit;
6940 }
6941
6942 /* We should be able to optimize the following three entries into one */
6943
6944 /* Release WLON reset 0x04[16]= 1*/
6945 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6946 val32 |= APS_FSMCO_WLON_RESET;
6947 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6948
6949 /* Disable HWPDN 0x04[15]= 0*/
6950 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6951 val32 &= ~APS_FSMCO_HW_POWERDOWN;
6952 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6953
6954 /* Disable WL suspend*/
6955 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6956 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
6957 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6958
6959 /* Set, then poll until 0 */
6960 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6961 val32 |= APS_FSMCO_MAC_ENABLE;
6962 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6963
6964 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6965 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6966 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
6967 ret = 0;
6968 break;
6969 }
6970 udelay(10);
6971 }
6972
6973 if (!count) {
6974 ret = -EBUSY;
6975 goto exit;
6976 }
6977
6978 /* Enable WL control XTAL setting */
6979 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
6980 val8 |= AFE_MISC_WL_XTAL_CTRL;
6981 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
6982
6983 /* Enable falling edge triggering interrupt */
6984 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
6985 val8 |= BIT(1);
6986 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
6987
6988 /* Enable GPIO9 interrupt mode */
6989 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
6990 val8 |= BIT(1);
6991 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
6992
6993 /* Enable GPIO9 input mode */
6994 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
6995 val8 &= ~BIT(1);
6996 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
6997
6998 /* Enable HSISR GPIO[C:0] interrupt */
6999 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
7000 val8 |= BIT(0);
7001 rtl8xxxu_write8(priv, REG_HSIMR, val8);
7002
7003 /* Enable HSISR GPIO9 interrupt */
7004 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
7005 val8 |= BIT(1);
7006 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
7007
7008 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
7009 val8 |= MULTI_WIFI_HW_ROF_EN;
7010 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
7011
7012 /* For GPIO9 internal pull high setting BIT(14) */
7013 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
7014 val8 |= BIT(6);
7015 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
7016
7017exit:
7018 return ret;
7019}
7020
26f1fad2
JS		 7021static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
7022{
7023 u8 val8;
7024
7025 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
7026 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
7027
7028 /* 0x04[12:11] = 01 enable WL suspend */
7029 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
7030 val8 &= ~BIT(4);
7031 val8 |= BIT(3);
7032 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
7033
7034 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
7035 val8 |= BIT(7);
7036 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
7037
7038 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
7039 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
7040 val8 |= BIT(0);
7041 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
7042
7043 return 0;
7044}
7045
430b454c
JS		 7046static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
7047{
145428ec 7048 struct device *dev = &priv->udev->dev;
430b454c
JS		 7049 u32 val32;
7050 int retry, retval;
7051
7052 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7053
7054 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
7055 val32 |= RXPKT_NUM_RW_RELEASE_EN;
7056 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
7057
7058 retry = 100;
7059 retval = -EBUSY;
7060
7061 do {
7062 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
7063 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
7064 retval = 0;
7065 break;
7066 }
7067 } while (retry--);
7068
7069 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
7070 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
7071 mdelay(2);
145428ec
JS		 7072
7073 if (!retry)
7074 dev_warn(dev, "Failed to flush FIFO\n");
430b454c
JS		 7075
7076 return retval;
7077}
7078
747bf237
JS		 7079static void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
7080{
7081 /* Fix USB interface interference issue */
7082 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
7083 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
7084 rtl8xxxu_write8(priv, 0xfe42, 0x80);
7085 /*
7086 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
7087 * 8 and 5, for which I have found no documentation.
7088 */
7089 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
7090
7091 /*
7092 * Solve too many protocol error on USB bus.
7093 * Can't do this for 8188/8192 UMC A cut parts
7094 */
7095 if (!(!priv->chip_cut && priv->vendor_umc)) {
7096 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
7097 rtl8xxxu_write8(priv, 0xfe41, 0x94);
7098 rtl8xxxu_write8(priv, 0xfe42, 0x80);
7099
7100 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
7101 rtl8xxxu_write8(priv, 0xfe41, 0x19);
7102 rtl8xxxu_write8(priv, 0xfe42, 0x80);
7103
7104 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
7105 rtl8xxxu_write8(priv, 0xfe41, 0x91);
7106 rtl8xxxu_write8(priv, 0xfe42, 0x80);
7107
7108 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
7109 rtl8xxxu_write8(priv, 0xfe41, 0x81);
7110 rtl8xxxu_write8(priv, 0xfe42, 0x80);
7111 }
7112}
7113
7114static void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
7115{
7116 u32 val32;
7117
7118 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
7119 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
7120 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
7121}
7122
26f1fad2
JS		 7123static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
7124{
7125 u8 val8;
7126 u16 val16;
7127 u32 val32;
7128 int ret;
7129
7130 /*
7131 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
7132 */
7133 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
7134
c05a9dbf 7135 rtl8723a_disabled_to_emu(priv);
26f1fad2 7136
c05a9dbf 7137 ret = rtl8723a_emu_to_active(priv);
26f1fad2
JS		 7138 if (ret)
7139 goto exit;
7140
7141 /*
7142 * 0x0004[19] = 1, reset 8051
7143 */
7144 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
7145 val8 |= BIT(3);
7146 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
7147
7148 /*
7149 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7150 * Set CR bit10 to enable 32k calibration.
7151 */
7152 val16 = rtl8xxxu_read16(priv, REG_CR);
7153 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
7154 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
7155 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
7156 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
7157 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
7158 rtl8xxxu_write16(priv, REG_CR, val16);
7159
7160 /* For EFuse PG */
7161 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
7162 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
7163 val32 |= (0x06 << 28);
7164 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
7165exit:
7166 return ret;
7167}
7168
42836db1
JS		 7169static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
7170{
7171 u8 val8;
7172 u16 val16;
7173 u32 val32;
7174 int ret;
7175
7176 rtl8723a_disabled_to_emu(priv);
7177
7178 ret = rtl8723b_emu_to_active(priv);
7179 if (ret)
7180 goto exit;
7181
7182 /*
7183 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7184 * Set CR bit10 to enable 32k calibration.
7185 */
7186 val16 = rtl8xxxu_read16(priv, REG_CR);
7187 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
7188 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
7189 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
7190 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
7191 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
7192 rtl8xxxu_write16(priv, REG_CR, val16);
7193
7194 /*
7195 * BT coexist power on settings. This is identical for 1 and 2
7196 * antenna parts.
7197 */
7198 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
7199
7200 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
7201 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
7202 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
7203
7204 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
7205 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
7206 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
7207 /* Antenna inverse */
7208 rtl8xxxu_write8(priv, 0xfe08, 0x01);
7209
7210 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
7211 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
7212 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
7213
7214 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
7215 val32 |= LEDCFG0_DPDT_SELECT;
7216 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
7217
7218 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
7219 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
7220 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
7221exit:
7222 return ret;
7223}
7224
c0963772
KV		 7225#ifdef CONFIG_RTL8XXXU_UNTESTED
7226
26f1fad2
JS		 7227static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
7228{
7229 u8 val8;
7230 u16 val16;
7231 u32 val32;
7232 int i;
7233
7234 for (i = 100; i; i--) {
7235 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
7236 if (val8 & APS_FSMCO_PFM_ALDN)
7237 break;
7238 }
7239
7240 if (!i) {
7241 pr_info("%s: Poll failed\n", __func__);
7242 return -ENODEV;
7243 }
7244
7245 /*
7246 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
7247 */
7248 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
7249 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
7250 udelay(100);
7251
7252 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
7253 if (!(val8 & LDOV12D_ENABLE)) {
7254 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
7255 val8 |= LDOV12D_ENABLE;
7256 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
7257
7258 udelay(100);
7259
7260 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
7261 val8 &= ~SYS_ISO_MD2PP;
7262 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
7263 }
7264
7265 /*
7266 * Auto enable WLAN
7267 */
7268 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
7269 val16 |= APS_FSMCO_MAC_ENABLE;
7270 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
7271
7272 for (i = 1000; i; i--) {
7273 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
7274 if (!(val16 & APS_FSMCO_MAC_ENABLE))
7275 break;
7276 }
7277 if (!i) {
7278 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
7279 return -EBUSY;
7280 }
7281
7282 /*
7283 * Enable radio, GPIO, LED
7284 */
7285 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
7286 APS_FSMCO_PFM_ALDN;
7287 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
7288
7289 /*
7290 * Release RF digital isolation
7291 */
7292 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
7293 val16 &= ~SYS_ISO_DIOR;
7294 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
7295
7296 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
7297 val8 &= ~APSD_CTRL_OFF;
7298 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
7299 for (i = 200; i; i--) {
7300 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
7301 if (!(val8 & APSD_CTRL_OFF_STATUS))
7302 break;
7303 }
7304
7305 if (!i) {
7306 pr_info("%s: APSD_CTRL poll failed\n", __func__);
7307 return -EBUSY;
7308 }
7309
7310 /*
7311 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7312 */
7313 val16 = rtl8xxxu_read16(priv, REG_CR);
7314 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
7315 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
7316 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
7317 rtl8xxxu_write16(priv, REG_CR, val16);
7318
b9f9d699
JS		 7319 rtl8xxxu_write8(priv, 0xfe10, 0x19);
7320
26f1fad2
JS		 7321 /*
7322 * Workaround for 8188RU LNA power leakage problem.
7323 */
8d95c808 7324 if (priv->rtl_chip == RTL8188R) {
26f1fad2
JS		 7325 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
7326 val32 &= ~BIT(1);
7327 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
7328 }
7329 return 0;
7330}
7331
c0963772
KV		 7332#endif
7333
28e460b0
JS		 7334/*
7335 * This is needed for 8723bu as well, presumable
7336 */
7337static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)
7338{
7339 u8 val8;
7340 u32 val32;
7341
7342 /*
7343 * 40Mhz crystal source, MAC 0x28[2]=0
7344 */
7345 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
7346 val8 &= 0xfb;
7347 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
7348
7349 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
7350 val32 &= 0xfffffc7f;
7351 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
7352
7353 /*
7354 * 92e AFE parameter
7355 * AFE PLL KVCO selection, MAC 0x28[6]=1
7356 */
7357 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
7358 val8 &= 0xbf;
7359 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
7360
7361 /*
7362 * AFE PLL KVCO selection, MAC 0x78[21]=0
7363 */
7364 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
7365 val32 &= 0xffdfffff;
7366 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
7367}
7368
c05a9dbf
JS		 7369static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
7370{
7371 u16 val16;
7372 u32 val32;
7373 int ret;
7374
7375 ret = 0;
7376
7377 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
7378 if (val32 & SYS_CFG_SPS_LDO_SEL) {
7379 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
7380 } else {
7381 /*
7382 * Raise 1.2V voltage
7383 */
7384 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
7385 val32 &= 0xff0fffff;
7386 val32 |= 0x00500000;
7387 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
7388 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
7389 }
7390
28e460b0
JS		 7391 /*
7392 * Adjust AFE before enabling PLL
7393 */
7394 rtl8192e_crystal_afe_adjust(priv);
c05a9dbf
JS		 7395 rtl8192e_disabled_to_emu(priv);
7396
7397 ret = rtl8192e_emu_to_active(priv);
7398 if (ret)
7399 goto exit;
7400
7401 rtl8xxxu_write16(priv, REG_CR, 0x0000);
7402
7403 /*
7404 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7405 * Set CR bit10 to enable 32k calibration.
7406 */
7407 val16 = rtl8xxxu_read16(priv, REG_CR);
7408 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
7409 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
7410 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
7411 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
7412 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
7413 rtl8xxxu_write16(priv, REG_CR, val16);
7414
7415exit:
7416 return ret;
7417}
7418
26f1fad2
JS		 7419static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
7420{
7421 u8 val8;
7422 u16 val16;
7423 u32 val32;
7424
7425 /*
7426 * Workaround for 8188RU LNA power leakage problem.
7427 */
8d95c808 7428 if (priv->rtl_chip == RTL8188R) {
26f1fad2
JS		 7429 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
7430 val32 |= BIT(1);
7431 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
7432 }
7433
430b454c
JS		 7434 rtl8xxxu_flush_fifo(priv);
7435
26f1fad2
JS		 7436 rtl8xxxu_active_to_lps(priv);
7437
7438 /* Turn off RF */
7439 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
7440
7441 /* Reset Firmware if running in RAM */
7442 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
7443 rtl8xxxu_firmware_self_reset(priv);
7444
7445 /* Reset MCU */
7446 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
7447 val16 &= ~SYS_FUNC_CPU_ENABLE;
7448 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
7449
7450 /* Reset MCU ready status */
7451 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
7452
7453 rtl8xxxu_active_to_emu(priv);
7454 rtl8xxxu_emu_to_disabled(priv);
7455
7456 /* Reset MCU IO Wrapper */
7457 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
7458 val8 &= ~BIT(0);
7459 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7460
7461 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
7462 val8 |= BIT(0);
7463 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7464
7465 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
7466 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
7467}
7468
fe37d5f6
JS		 7469static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
7470{
7471 u8 val8;
7472 u16 val16;
7473
430b454c
JS		 7474 rtl8xxxu_flush_fifo(priv);
7475
fe37d5f6
JS		 7476 /*
7477 * Disable TX report timer
7478 */
7479 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
7480 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
7481 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
7482
8e254960 7483 rtl8xxxu_write8(priv, REG_CR, 0x0000);
fe37d5f6
JS		 7484
7485 rtl8xxxu_active_to_lps(priv);
7486
7487 /* Reset Firmware if running in RAM */
7488 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
7489 rtl8xxxu_firmware_self_reset(priv);
7490
7491 /* Reset MCU */
7492 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
7493 val16 &= ~SYS_FUNC_CPU_ENABLE;
7494 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
7495
7496 /* Reset MCU ready status */
7497 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
7498
7499 rtl8723bu_active_to_emu(priv);
8e254960
JS		 7500
7501 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
7502 val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */
7503 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
7504
7505 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
7506 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
7507 val8 |= BIT(0);
7508 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
fe37d5f6
JS		 7509}
7510
a3a5dac6 7511#ifdef NEED_PS_TDMA
3ca7b32c
JS		 7512static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
7513 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
7514{
7515 struct h2c_cmd h2c;
7516
7517 memset(&h2c, 0, sizeof(struct h2c_cmd));
7518 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
7519 h2c.b_type_dma.data1 = arg1;
7520 h2c.b_type_dma.data2 = arg2;
7521 h2c.b_type_dma.data3 = arg3;
7522 h2c.b_type_dma.data4 = arg4;
7523 h2c.b_type_dma.data5 = arg5;
7524 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
7525}
a3a5dac6 7526#endif
3ca7b32c 7527
ae5c01fd
JS		 7528static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv)
7529{
7530 u32 val32;
7531 u8 val8;
7532
7533 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
7534 val8 |= BIT(5);
7535 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
7536
7537 /*
7538 * WLAN action by PTA
7539 */
7540 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
7541
7542 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
7543 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
7544 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
7545
7546 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
7547 val32 |= (BIT(0) | BIT(1));
7548 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
7549
7550 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
7551
7552 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
7553 val32 &= ~BIT(24);
7554 val32 |= BIT(23);
7555 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
7556
7557 /*
7558 * Fix external switch Main->S1, Aux->S0
7559 */
7560 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
7561 val8 &= ~BIT(0);
7562 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
7563}
7564
0290e7d0 7565static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
26f1fad2 7566{
f37e9228
JS		 7567 struct h2c_cmd h2c;
7568 u32 val32;
7569 u8 val8;
7570
7571 /*
7572 * No indication anywhere as to what 0x0790 does. The 2 antenna
7573 * vendor code preserves bits 6-7 here.
7574 */
7575 rtl8xxxu_write8(priv, 0x0790, 0x05);
7576 /*
7577 * 0x0778 seems to be related to enabling the number of antennas
7578 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
7579 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
7580 */
7581 rtl8xxxu_write8(priv, 0x0778, 0x01);
7582
7583 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
7584 val8 |= BIT(5);
7585 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
7586
7587 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
7588
394f1bd3
JS		 7589 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
7590
f37e9228
JS		 7591 /*
7592 * Set BT grant to low
7593 */
7594 memset(&h2c, 0, sizeof(struct h2c_cmd));
7595 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
7596 h2c.bt_grant.data = 0;
7597 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
7598
7599 /*
7600 * WLAN action by PTA
7601 */
fc1c89b3 7602 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
f37e9228
JS		 7603
7604 /*
7605 * BT select S0/S1 controlled by WiFi
7606 */
7607 val8 = rtl8xxxu_read8(priv, 0x0067);
7608 val8 |= BIT(5);
7609 rtl8xxxu_write8(priv, 0x0067, val8);
7610
7611 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
37f44dc7 7612 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
f37e9228
JS		 7613 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
7614
7615 /*
7616 * Bits 6/7 are marked in/out ... but for what?
7617 */
7618 rtl8xxxu_write8(priv, 0x0974, 0xff);
7619
120e627f 7620 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
f37e9228 7621 val32 |= (BIT(0) | BIT(1));
120e627f 7622 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
f37e9228
JS		 7623
7624 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
7625
7626 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
7627 val32 &= ~BIT(24);
7628 val32 |= BIT(23);
7629 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
7630
7631 /*
7632 * Fix external switch Main->S1, Aux->S0
7633 */
7634 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
7635 val8 &= ~BIT(0);
7636 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
7637
7638 memset(&h2c, 0, sizeof(struct h2c_cmd));
7639 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
7640 h2c.ant_sel_rsv.ant_inverse = 1;
7641 h2c.ant_sel_rsv.int_switch_type = 0;
7642 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
7643
7644 /*
7645 * 0x280, 0x00, 0x200, 0x80 - not clear
7646 */
3ca7b32c
JS		 7647 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
7648
7649 /*
7650 * Software control, antenna at WiFi side
7651 */
a3a5dac6 7652#ifdef NEED_PS_TDMA
a228a5db 7653 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
a3a5dac6
JS		 7654#endif
7655
7656 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
7657 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
7658 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
7659 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
3ca7b32c 7660
6b9eae01
JS		 7661 memset(&h2c, 0, sizeof(struct h2c_cmd));
7662 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
7663 h2c.bt_info.data = BIT(0);
7664 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
7665
6b9eae01
JS		 7666 memset(&h2c, 0, sizeof(struct h2c_cmd));
7667 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
7668 h2c.ignore_wlan.data = 0;
7669 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
26f1fad2
JS		 7670}
7671
6a07b791 7672static void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
fc89a41f
JS		 7673{
7674 u32 val32;
7675
fc89a41f
JS		 7676 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
7677 val32 &= ~(BIT(22) | BIT(23));
7678 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
7679}
7680
3e88ca44
JS		 7681static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
7682{
7683 u32 agg_rx;
7684 u8 agg_ctrl;
7685
7686 /*
7687 * For now simply disable RX aggregation
7688 */
7689 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
7690 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
7691
7692 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
7693 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
7694 agg_rx &= ~0xff0f;
7695
7696 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
7697 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
7698}
7699
9c79bf95
JS		 7700static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
7701{
7702 u32 val32;
7703
7704 /* Time duration for NHM unit: 4us, 0x2710=40ms */
7705 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
7706 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
7707 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
7708 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
7709 /* TH8 */
7710 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
7711 val32 |= 0xff;
7712 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
7713 /* Enable CCK */
7714 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
7715 val32 |= BIT(8) | BIT(9) | BIT(10);
7716 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
7717 /* Max power amongst all RX antennas */
7718 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
7719 val32 |= BIT(7);
7720 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
7721}
7722
89c2a097
JS		 7723static void rtl8xxxu_old_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
7724{
7725 u8 val8;
7726 u32 val32;
7727
7728 if (priv->ep_tx_normal_queue)
7729 val8 = TX_PAGE_NUM_NORM_PQ;
7730 else
7731 val8 = 0;
7732
7733 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
7734
7735 val32 = (TX_PAGE_NUM_PUBQ << RQPN_PUB_PQ_SHIFT) | RQPN_LOAD;
7736
7737 if (priv->ep_tx_high_queue)
7738 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
7739 if (priv->ep_tx_low_queue)
7740 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
7741
7742 rtl8xxxu_write32(priv, REG_RQPN, val32);
7743}
7744
7745static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
7746{
7747 struct rtl8xxxu_fileops *fops = priv->fops;
7748 u32 hq, lq, nq, eq, pubq;
7749 u32 val32;
7750
7751 hq = 0;
7752 lq = 0;
7753 nq = 0;
7754 eq = 0;
7755 pubq = 0;
7756
7757 if (priv->ep_tx_high_queue)
7758 hq = fops->page_num_hi;
7759 if (priv->ep_tx_low_queue)
7760 lq = fops->page_num_lo;
7761 if (priv->ep_tx_normal_queue)
7762 nq = fops->page_num_norm;
7763
7764 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
7765 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
7766
7767 pubq = fops->total_page_num - hq - lq - nq;
7768
7769 val32 = RQPN_LOAD;
7770 val32 |= (hq << RQPN_HI_PQ_SHIFT);
7771 val32 |= (lq << RQPN_LO_PQ_SHIFT);
7772 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
7773
7774 rtl8xxxu_write32(priv, REG_RQPN, val32);
7775}
7776
26f1fad2
JS		 7777static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
7778{
7779 struct rtl8xxxu_priv *priv = hw->priv;
7780 struct device *dev = &priv->udev->dev;
26f1fad2
JS		 7781 bool macpower;
7782 int ret;
7783 u8 val8;
7784 u16 val16;
7785 u32 val32;
7786
7787 /* Check if MAC is already powered on */
7788 val8 = rtl8xxxu_read8(priv, REG_CR);
7789
7790 /*
7791 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
7792 * initialized. First MAC returns 0xea, second MAC returns 0x00
7793 */
7794 if (val8 == 0xea)
7795 macpower = false;
7796 else
7797 macpower = true;
7798
7799 ret = priv->fops->power_on(priv);
7800 if (ret < 0) {
7801 dev_warn(dev, "%s: Failed power on\n", __func__);
7802 goto exit;
7803 }
7804
07bb46be 7805 if (!macpower) {
89c2a097
JS		 7806 if (priv->fops->total_page_num)
7807 rtl8xxxu_init_queue_reserved_page(priv);
59b24dad 7808 else
89c2a097 7809 rtl8xxxu_old_init_queue_reserved_page(priv);
07bb46be
JS		 7810 }
7811
59b24dad
JS		 7812 ret = rtl8xxxu_init_queue_priority(priv);
7813 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
7814 if (ret)
7815 goto exit;
7816
7817 /*
7818 * Set RX page boundary
7819 */
24e8e7ec 7820 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, priv->fops->trxff_boundary);
59b24dad 7821
a47b9d47
JS		 7822 ret = rtl8xxxu_download_firmware(priv);
7823 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
7824 if (ret)
7825 goto exit;
7826 ret = rtl8xxxu_start_firmware(priv);
7827 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
7828 if (ret)
7829 goto exit;
7830
f0d9f5e9
JS		 7831 if (priv->fops->phy_init_antenna_selection)
7832 priv->fops->phy_init_antenna_selection(priv);
7833
c606e662 7834 ret = rtl8xxxu_init_mac(priv);
b7dd8ff9 7835
26f1fad2
JS		 7836 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
7837 if (ret)
7838 goto exit;
7839
7840 ret = rtl8xxxu_init_phy_bb(priv);
7841 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
7842 if (ret)
7843 goto exit;
7844
4062b8ff 7845 ret = priv->fops->init_phy_rf(priv);
26f1fad2
JS		 7846 if (ret)
7847 goto exit;
7848
c157863d 7849 /* RFSW Control - clear bit 14 ?? */
b816901b 7850 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
c157863d 7851 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
31133da7
JS		 7852
7853 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
cabb550e
JS		 7854 FPGA0_RF_ANTSWB |
7855 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
7856 if (!priv->no_pape) {
7857 val32 |= (FPGA0_RF_PAPE |
7858 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
7859 }
c157863d 7860 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
cabb550e 7861
c157863d
JS		 7862 /* 0x860[6:5]= 00 - why? - this sets antenna B */
7863 if (priv->rtl_chip != RTL8192E)
7864 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
7865
f2a4163a 7866 if (!macpower) {
1f1b20f1
JS		 7867 /*
7868 * Set TX buffer boundary
7869 */
80805aa5
JS		 7870 if (priv->rtl_chip == RTL8192E)
7871 val8 = TX_TOTAL_PAGE_NUM_8192E + 1;
7872 else
7873 val8 = TX_TOTAL_PAGE_NUM + 1;
1f1b20f1 7874
ba17d824 7875 if (priv->rtl_chip == RTL8723B)
1f1b20f1
JS		 7876 val8 -= 1;
7877
7878 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
7879 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
7880 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
7881 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
7882 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
7883 }
7884
26f1fad2 7885 /*
9b323ee9
JS		 7886 * The vendor drivers set PBP for all devices, except 8192e.
7887 * There is no explanation for this in any of the sources.
26f1fad2 7888 */
9b323ee9
JS		 7889 val8 = (priv->fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
7890 (priv->fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
2e7c7b34
JS		 7891 if (priv->rtl_chip != RTL8192E)
7892 rtl8xxxu_write8(priv, REG_PBP, val8);
26f1fad2 7893
59b24dad
JS		 7894 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
7895 if (!macpower) {
7896 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
7897 if (ret) {
7898 dev_warn(dev, "%s: LLT table init failed\n", __func__);
7899 goto exit;
7900 }
7901
0486e80b
JS		 7902 /*
7903 * Chip specific quirks
7904 */
747bf237 7905 priv->fops->usb_quirks(priv);
0486e80b 7906
59b24dad
JS		 7907 /*
7908 * Presumably this is for 8188EU as well
7909 * Enable TX report and TX report timer
7910 */
7911 if (priv->rtl_chip == RTL8723B) {
7912 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
7913 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
7914 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
7915 /* Set MAX RPT MACID */
7916 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
7917 /* TX report Timer. Unit: 32us */
7918 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
7919
7920 /* tmp ps ? */
7921 val8 = rtl8xxxu_read8(priv, 0xa3);
7922 val8 &= 0xf8;
7923 rtl8xxxu_write8(priv, 0xa3, val8);
7924 }
7925 }
7926
26f1fad2
JS		 7927 /*
7928 * Unit in 8 bytes, not obvious what it is used for
7929 */
7930 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
7931
57e5e2e6
JS		 7932 if (priv->rtl_chip == RTL8192E) {
7933 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
7934 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
7935 } else {
7936 /*
7937 * Enable all interrupts - not obvious USB needs to do this
7938 */
7939 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
7940 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
7941 }
26f1fad2
JS		 7942
7943 rtl8xxxu_set_mac(priv);
7944 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
7945
7946 /*
7947 * Configure initial WMAC settings
7948 */
7949 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
26f1fad2
JS		 7950 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
7951 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
7952 rtl8xxxu_write32(priv, REG_RCR, val32);
7953
7954 /*
7955 * Accept all multicast
7956 */
7957 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
7958 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
7959
7960 /*
7961 * Init adaptive controls
7962 */
7963 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
7964 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
7965 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
7966 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
7967
7968 /* CCK = 0x0a, OFDM = 0x10 */
7969 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
7970 rtl8xxxu_set_retry(priv, 0x30, 0x30);
7971 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
7972
7973 /*
7974 * Init EDCA
7975 */
7976 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
7977
7978 /* Set CCK SIFS */
7979 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
7980
7981 /* Set OFDM SIFS */
7982 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
7983
7984 /* TXOP */
7985 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
7986 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
7987 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
7988 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
7989
7990 /* Set data auto rate fallback retry count */
7991 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
7992 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
7993 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
7994 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
7995
7996 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
7997 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
7998 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
7999
8000 /* Set ACK timeout */
8001 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
8002
8003 /*
8004 * Initialize beacon parameters
8005 */
8006 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
8007 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
8008 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
8009 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
8010 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
8011 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
8012
c3690604
JS		 8013 /*
8014 * Initialize burst parameters
8015 */
ba17d824 8016 if (priv->rtl_chip == RTL8723B) {
c3690604
JS		 8017 /*
8018 * For USB high speed set 512B packets
8019 */
8020 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
8021 val8 &= ~(BIT(4) | BIT(5));
8022 val8 |= BIT(4);
8023 val8 |= BIT(1) | BIT(2) | BIT(3);
8024 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
8025
8026 /*
8027 * For USB high speed set 512B packets
8028 */
8029 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
8030 val8 |= BIT(7);
8031 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
8032
8033 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
8034 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
8035 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
8036 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
8037 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
8038 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
8039 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
8040
8041 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
8042 val8 |= BIT(5) | BIT(6);
8043 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
8044 }
8045
3e88ca44
JS		 8046 if (priv->fops->init_aggregation)
8047 priv->fops->init_aggregation(priv);
8048
26f1fad2
JS		 8049 /*
8050 * Enable CCK and OFDM block
8051 */
8052 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
8053 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
8054 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
8055
8056 /*
8057 * Invalidate all CAM entries - bit 30 is undocumented
8058 */
8059 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
8060
8061 /*
8062 * Start out with default power levels for channel 6, 20MHz
8063 */
e796dab4 8064 priv->fops->set_tx_power(priv, 1, false);
26f1fad2
JS		 8065
8066 /* Let the 8051 take control of antenna setting */
5bdb6b08
JS		 8067 if (priv->rtl_chip != RTL8192E) {
8068 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
8069 val8 |= LEDCFG2_DPDT_SELECT;
8070 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
8071 }
26f1fad2
JS		 8072
8073 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
8074
8075 /* Disable BAR - not sure if this has any effect on USB */
8076 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
8077
8078 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
8079
9c79bf95
JS		 8080 if (priv->fops->init_statistics)
8081 priv->fops->init_statistics(priv);
8082
b052b7fc
JS		 8083 if (priv->rtl_chip == RTL8192E) {
8084 /*
8085 * 0x4c6[3] 1: RTS BW = Data BW
8086 * 0: RTS BW depends on CCA / secondary CCA result.
8087 */
8088 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
8089 val8 &= ~BIT(3);
8090 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
8091 /*
8092 * Reset USB mode switch setting
8093 */
8094 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
8095 }
8096
fa0f2d48
JS		 8097 rtl8723a_phy_lc_calibrate(priv);
8098
e1547c53 8099 priv->fops->phy_iq_calibrate(priv);
26f1fad2
JS		 8100
8101 /*
8102 * This should enable thermal meter
8103 */
55c0b6ae 8104 if (priv->fops->tx_desc_size == sizeof(struct rtl8xxxu_txdesc40))
72143b9e
JS		 8105 rtl8xxxu_write_rfreg(priv,
8106 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
8107 else
8108 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
26f1fad2 8109
26f1fad2
JS		 8110 /* Set NAV_UPPER to 30000us */
8111 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
8112 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
8113
ba17d824 8114 if (priv->rtl_chip == RTL8723A) {
4042e617
JS		 8115 /*
8116 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
8117 * but we need to find root cause.
8118 * This is 8723au only.
8119 */
8120 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
8121 if ((val32 & 0xff000000) != 0x83000000) {
8122 val32 |= FPGA_RF_MODE_CCK;
8123 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
8124 }
3021e51f
JS		 8125 } else if (priv->rtl_chip == RTL8192E) {
8126 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
26f1fad2
JS		 8127 }
8128
8129 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
8130 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
8131 /* ack for xmit mgmt frames. */
8132 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
8133
e1394fe5
JS		 8134 if (priv->rtl_chip == RTL8192E) {
8135 /*
8136 * Fix LDPC rx hang issue.
8137 */
8138 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
8139 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
8140 val32 &= 0xfff00fff;
8141 val32 |= 0x0007e000;
46b37831 8142 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
e1394fe5 8143 }
26f1fad2
JS		 8144exit:
8145 return ret;
8146}
8147
26f1fad2
JS		 8148static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
8149 struct ieee80211_key_conf *key, const u8 *mac)
8150{
8151 u32 cmd, val32, addr, ctrl;
8152 int j, i, tmp_debug;
8153
8154 tmp_debug = rtl8xxxu_debug;
8155 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
8156 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
8157
8158 /*
8159 * This is a bit of a hack - the lower bits of the cipher
8160 * suite selector happens to match the cipher index in the CAM
8161 */
8162 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
8163 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
8164
8165 for (j = 5; j >= 0; j--) {
8166 switch (j) {
8167 case 0:
8168 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
8169 break;
8170 case 1:
8171 val32 = mac[2] | (mac[3] << 8) |
8172 (mac[4] << 16) | (mac[5] << 24);
8173 break;
8174 default:
8175 i = (j - 2) << 2;
8176 val32 = key->key[i] | (key->key[i + 1] << 8) |
8177 key->key[i + 2] << 16 | key->key[i + 3] << 24;
8178 break;
8179 }
8180
8181 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
8182 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
8183 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
8184 udelay(100);
8185 }
8186
8187 rtl8xxxu_debug = tmp_debug;
8188}
8189
8190static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
56e4374a 8191 struct ieee80211_vif *vif, const u8 *mac)
26f1fad2
JS		 8192{
8193 struct rtl8xxxu_priv *priv = hw->priv;
8194 u8 val8;
8195
8196 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
8197 val8 |= BEACON_DISABLE_TSF_UPDATE;
8198 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
8199}
8200
8201static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
8202 struct ieee80211_vif *vif)
8203{
8204 struct rtl8xxxu_priv *priv = hw->priv;
8205 u8 val8;
8206
8207 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
8208 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
8209 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
8210}
8211
c6e39da0
JS		 8212static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
8213 u32 ramask, int sgi)
26f1fad2
JS		 8214{
8215 struct h2c_cmd h2c;
8216
f653e690
JS		 8217 memset(&h2c, 0, sizeof(struct h2c_cmd));
8218
26f1fad2
JS		 8219 h2c.ramask.cmd = H2C_SET_RATE_MASK;
8220 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
8221 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
8222
8223 h2c.ramask.arg = 0x80;
8224 if (sgi)
8225 h2c.ramask.arg |= 0x20;
8226
7ff8c1ae 8227 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
8da91571
JS		 8228 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
8229 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
26f1fad2
JS		 8230}
8231
a8c8dfa5
JS		 8232static void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
8233 u32 ramask, int sgi)
f653e690
JS		 8234{
8235 struct h2c_cmd h2c;
8236 u8 bw = 0;
8237
8238 memset(&h2c, 0, sizeof(struct h2c_cmd));
8239
8240 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
8241 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
8242 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
8243 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
8244 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
8245
8246 h2c.ramask.arg = 0x80;
8247 h2c.b_macid_cfg.data1 = 0;
8248 if (sgi)
8249 h2c.b_macid_cfg.data1 |= BIT(7);
8250
8251 h2c.b_macid_cfg.data2 = bw;
8252
8253 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
8254 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
8255 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
8256}
8257
beb55316
JS		 8258static void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
8259 u8 macid, bool connect)
7d794eaa
JS		 8260{
8261 struct h2c_cmd h2c;
8262
8263 memset(&h2c, 0, sizeof(struct h2c_cmd));
8264
8265 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
8266
8267 if (connect)
8268 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
8269 else
8270 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
8271
8272 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
8273}
8274
32353a78
JS		 8275static void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
8276 u8 macid, bool connect)
7d794eaa
JS		 8277{
8278 struct h2c_cmd h2c;
8279
8280 memset(&h2c, 0, sizeof(struct h2c_cmd));
8281
8282 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
8283 if (connect)
8284 h2c.media_status_rpt.parm |= BIT(0);
8285 else
8286 h2c.media_status_rpt.parm &= ~BIT(0);
8287
8288 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
8289}
8290
26f1fad2
JS		 8291static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
8292{
8293 u32 val32;
8294 u8 rate_idx = 0;
8295
8296 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
8297
8298 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
8299 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
8300 val32 |= rate_cfg;
8301 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
8302
8303 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
8304
8305 while (rate_cfg) {
8306 rate_cfg = (rate_cfg >> 1);
8307 rate_idx++;
8308 }
8309 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
8310}
8311
8312static void
8313rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
8314 struct ieee80211_bss_conf *bss_conf, u32 changed)
8315{
8316 struct rtl8xxxu_priv *priv = hw->priv;
8317 struct device *dev = &priv->udev->dev;
8318 struct ieee80211_sta *sta;
8319 u32 val32;
8320 u8 val8;
8321
8322 if (changed & BSS_CHANGED_ASSOC) {
26f1fad2
JS		 8323 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
8324
26f1fad2
JS		 8325 rtl8xxxu_set_linktype(priv, vif->type);
8326
8327 if (bss_conf->assoc) {
8328 u32 ramask;
8329 int sgi = 0;
8330
8331 rcu_read_lock();
8332 sta = ieee80211_find_sta(vif, bss_conf->bssid);
8333 if (!sta) {
8334 dev_info(dev, "%s: ASSOC no sta found\n",
8335 __func__);
8336 rcu_read_unlock();
8337 goto error;
8338 }
8339
8340 if (sta->ht_cap.ht_supported)
8341 dev_info(dev, "%s: HT supported\n", __func__);
8342 if (sta->vht_cap.vht_supported)
8343 dev_info(dev, "%s: VHT supported\n", __func__);
8344
8345 /* TODO: Set bits 28-31 for rate adaptive id */
8346 ramask = (sta->supp_rates[0] & 0xfff) |
8347 sta->ht_cap.mcs.rx_mask[0] << 12 |
8348 sta->ht_cap.mcs.rx_mask[1] << 20;
8349 if (sta->ht_cap.cap &
8350 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
8351 sgi = 1;
8352 rcu_read_unlock();
8353
f653e690 8354 priv->fops->update_rate_mask(priv, ramask, sgi);
26f1fad2 8355
26f1fad2
JS		 8356 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
8357
8358 rtl8723a_stop_tx_beacon(priv);
8359
8360 /* joinbss sequence */
8361 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
8362 0xc000 | bss_conf->aid);
8363
7d794eaa 8364 priv->fops->report_connect(priv, 0, true);
26f1fad2 8365 } else {
26f1fad2
JS		 8366 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
8367 val8 |= BEACON_DISABLE_TSF_UPDATE;
8368 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
8369
7d794eaa 8370 priv->fops->report_connect(priv, 0, false);
26f1fad2 8371 }
26f1fad2
JS		 8372 }
8373
8374 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
8375 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
8376 bss_conf->use_short_preamble);
8377 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
8378 if (bss_conf->use_short_preamble)
8379 val32 |= RSR_ACK_SHORT_PREAMBLE;
8380 else
8381 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
8382 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
8383 }
8384
8385 if (changed & BSS_CHANGED_ERP_SLOT) {
8386 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
8387 bss_conf->use_short_slot);
8388
8389 if (bss_conf->use_short_slot)
8390 val8 = 9;
8391 else
8392 val8 = 20;
8393 rtl8xxxu_write8(priv, REG_SLOT, val8);
8394 }
8395
8396 if (changed & BSS_CHANGED_BSSID) {
8397 dev_dbg(dev, "Changed BSSID!\n");
8398 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
8399 }
8400
8401 if (changed & BSS_CHANGED_BASIC_RATES) {
8402 dev_dbg(dev, "Changed BASIC_RATES!\n");
8403 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
8404 }
8405error:
8406 return;
8407}
8408
8409static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
8410{
8411 u32 rtlqueue;
8412
8413 switch (queue) {
8414 case IEEE80211_AC_VO:
8415 rtlqueue = TXDESC_QUEUE_VO;
8416 break;
8417 case IEEE80211_AC_VI:
8418 rtlqueue = TXDESC_QUEUE_VI;
8419 break;
8420 case IEEE80211_AC_BE:
8421 rtlqueue = TXDESC_QUEUE_BE;
8422 break;
8423 case IEEE80211_AC_BK:
8424 rtlqueue = TXDESC_QUEUE_BK;
8425 break;
8426 default:
8427 rtlqueue = TXDESC_QUEUE_BE;
8428 }
8429
8430 return rtlqueue;
8431}
8432
8433static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
8434{
8435 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8436 u32 queue;
8437
8438 if (ieee80211_is_mgmt(hdr->frame_control))
8439 queue = TXDESC_QUEUE_MGNT;
8440 else
8441 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
8442
8443 return queue;
8444}
8445
179e1742
JS		 8446/*
8447 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
8448 * format. The descriptor checksum is still only calculated over the
8449 * initial 32 bytes of the descriptor!
8450 */
dbb2896b 8451static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
26f1fad2
JS		 8452{
8453 __le16 *ptr = (__le16 *)tx_desc;
8454 u16 csum = 0;
8455 int i;
8456
8457 /*
8458 * Clear csum field before calculation, as the csum field is
8459 * in the middle of the struct.
8460 */
8461 tx_desc->csum = cpu_to_le16(0);
8462
dbb2896b 8463 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
26f1fad2
JS		 8464 csum = csum ^ le16_to_cpu(ptr[i]);
8465
8466 tx_desc->csum |= cpu_to_le16(csum);
8467}
8468
8469static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
8470{
8471 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
8472 unsigned long flags;
8473
8474 spin_lock_irqsave(&priv->tx_urb_lock, flags);
8475 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
8476 list_del(&tx_urb->list);
8477 priv->tx_urb_free_count--;
8478 usb_free_urb(&tx_urb->urb);
8479 }
8480 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
8481}
8482
8483static struct rtl8xxxu_tx_urb *
8484rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
8485{
8486 struct rtl8xxxu_tx_urb *tx_urb;
8487 unsigned long flags;
8488
8489 spin_lock_irqsave(&priv->tx_urb_lock, flags);
8490 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
8491 struct rtl8xxxu_tx_urb, list);
8492 if (tx_urb) {
8493 list_del(&tx_urb->list);
8494 priv->tx_urb_free_count--;
8495 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
8496 !priv->tx_stopped) {
8497 priv->tx_stopped = true;
8498 ieee80211_stop_queues(priv->hw);
8499 }
8500 }
8501
8502 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
8503
8504 return tx_urb;
8505}
8506
8507static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
8508 struct rtl8xxxu_tx_urb *tx_urb)
8509{
8510 unsigned long flags;
8511
8512 INIT_LIST_HEAD(&tx_urb->list);
8513
8514 spin_lock_irqsave(&priv->tx_urb_lock, flags);
8515
8516 list_add(&tx_urb->list, &priv->tx_urb_free_list);
8517 priv->tx_urb_free_count++;
8518 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
8519 priv->tx_stopped) {
8520 priv->tx_stopped = false;
8521 ieee80211_wake_queues(priv->hw);
8522 }
8523
8524 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
8525}
8526
8527static void rtl8xxxu_tx_complete(struct urb *urb)
8528{
8529 struct sk_buff *skb = (struct sk_buff *)urb->context;
8530 struct ieee80211_tx_info *tx_info;
8531 struct ieee80211_hw *hw;
179e1742 8532 struct rtl8xxxu_priv *priv;
26f1fad2
JS		 8533 struct rtl8xxxu_tx_urb *tx_urb =
8534 container_of(urb, struct rtl8xxxu_tx_urb, urb);
8535
8536 tx_info = IEEE80211_SKB_CB(skb);
8537 hw = tx_info->rate_driver_data[0];
179e1742 8538 priv = hw->priv;
26f1fad2 8539
179e1742 8540 skb_pull(skb, priv->fops->tx_desc_size);
26f1fad2
JS		 8541
8542 ieee80211_tx_info_clear_status(tx_info);
8543 tx_info->status.rates[0].idx = -1;
8544 tx_info->status.rates[0].count = 0;
8545
8546 if (!urb->status)
8547 tx_info->flags |= IEEE80211_TX_STAT_ACK;
8548
8549 ieee80211_tx_status_irqsafe(hw, skb);
8550
179e1742 8551 rtl8xxxu_free_tx_urb(priv, tx_urb);
26f1fad2
JS		 8552}
8553
8554static void rtl8xxxu_dump_action(struct device *dev,
8555 struct ieee80211_hdr *hdr)
8556{
8557 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
8558 u16 cap, timeout;
8559
8560 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
8561 return;
8562
8563 switch (mgmt->u.action.u.addba_resp.action_code) {
8564 case WLAN_ACTION_ADDBA_RESP:
8565 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
8566 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
8567 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
8568 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
8569 "status %02x\n",
8570 timeout,
8571 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
8572 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
8573 (cap >> 1) & 0x1,
8574 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
8575 break;
8576 case WLAN_ACTION_ADDBA_REQ:
8577 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
8578 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
8579 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
8580 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
8581 timeout,
8582 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
8583 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
8584 (cap >> 1) & 0x1);
8585 break;
8586 default:
8587 dev_info(dev, "action frame %02x\n",
8588 mgmt->u.action.u.addba_resp.action_code);
8589 break;
8590 }
8591}
8592
8593static void rtl8xxxu_tx(struct ieee80211_hw *hw,
8594 struct ieee80211_tx_control *control,
8595 struct sk_buff *skb)
8596{
8597 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8598 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
8599 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
8600 struct rtl8xxxu_priv *priv = hw->priv;
dbb2896b
JS		 8601 struct rtl8xxxu_txdesc32 *tx_desc;
8602 struct rtl8xxxu_txdesc40 *tx_desc40;
26f1fad2
JS		 8603 struct rtl8xxxu_tx_urb *tx_urb;
8604 struct ieee80211_sta *sta = NULL;
8605 struct ieee80211_vif *vif = tx_info->control.vif;
8606 struct device *dev = &priv->udev->dev;
8607 u32 queue, rate;
8608 u16 pktlen = skb->len;
8609 u16 seq_number;
8610 u16 rate_flag = tx_info->control.rates[0].flags;
179e1742 8611 int tx_desc_size = priv->fops->tx_desc_size;
26f1fad2 8612 int ret;
cc2646d4 8613 bool usedesc40, ampdu_enable;
26f1fad2 8614
179e1742 8615 if (skb_headroom(skb) < tx_desc_size) {
26f1fad2
JS		 8616 dev_warn(dev,
8617 "%s: Not enough headroom (%i) for tx descriptor\n",
8618 __func__, skb_headroom(skb));
8619 goto error;
8620 }
8621
179e1742 8622 if (unlikely(skb->len > (65535 - tx_desc_size))) {
26f1fad2
JS		 8623 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
8624 __func__, skb->len);
8625 goto error;
8626 }
8627
8628 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
8629 if (!tx_urb) {
8630 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
8631 goto error;
8632 }
8633
8634 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
8635 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
8636 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
8637
8638 if (ieee80211_is_action(hdr->frame_control))
8639 rtl8xxxu_dump_action(dev, hdr);
8640
cc2646d4 8641 usedesc40 = (tx_desc_size == 40);
26f1fad2
JS		 8642 tx_info->rate_driver_data[0] = hw;
8643
8644 if (control && control->sta)
8645 sta = control->sta;
8646
dbb2896b 8647 tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size);
26f1fad2 8648
179e1742 8649 memset(tx_desc, 0, tx_desc_size);
26f1fad2 8650 tx_desc->pkt_size = cpu_to_le16(pktlen);
179e1742 8651 tx_desc->pkt_offset = tx_desc_size;
26f1fad2
JS		 8652
8653 tx_desc->txdw0 =
8654 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
8655 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
8656 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
8657 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
8658
8659 queue = rtl8xxxu_queue_select(hw, skb);
8660 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
8661
8662 if (tx_info->control.hw_key) {
8663 switch (tx_info->control.hw_key->cipher) {
8664 case WLAN_CIPHER_SUITE_WEP40:
8665 case WLAN_CIPHER_SUITE_WEP104:
8666 case WLAN_CIPHER_SUITE_TKIP:
8667 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
8668 break;
8669 case WLAN_CIPHER_SUITE_CCMP:
8670 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
8671 break;
8672 default:
8673 break;
8674 }
8675 }
8676
26f1fad2 8677 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
a40ace4f 8678 ampdu_enable = false;
26f1fad2
JS		 8679 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
8680 if (sta->ht_cap.ht_supported) {
8681 u32 ampdu, val32;
8682
8683 ampdu = (u32)sta->ht_cap.ampdu_density;
8684 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
8685 tx_desc->txdw2 |= cpu_to_le32(val32);
ce2d1dbb 8686
a40ace4f
JS		 8687 ampdu_enable = true;
8688 }
8689 }
8690
4c683607
JS		 8691 if (rate_flag & IEEE80211_TX_RC_MCS)
8692 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
8693 else
8694 rate = tx_rate->hw_value;
8695
cc2646d4
JS		 8696 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
8697 if (!usedesc40) {
4c683607
JS		 8698 tx_desc->txdw5 = cpu_to_le32(rate);
8699
8700 if (ieee80211_is_data(hdr->frame_control))
8701 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
8702
cc2646d4 8703 tx_desc->txdw3 =
33f37249 8704 cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
cc2646d4 8705
a40ace4f 8706 if (ampdu_enable)
33f37249 8707 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
a40ace4f 8708 else
33f37249 8709 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
4c683607
JS		 8710
8711 if (ieee80211_is_mgmt(hdr->frame_control)) {
8712 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
8713 tx_desc->txdw4 |=
33f37249 8714 cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
4c683607 8715 tx_desc->txdw5 |=
33f37249 8716 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
4c683607 8717 tx_desc->txdw5 |=
33f37249 8718 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
4c683607
JS		 8719 }
8720
8721 if (ieee80211_is_data_qos(hdr->frame_control))
33f37249 8722 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
4c683607
JS		 8723
8724 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
8725 (sta && vif && vif->bss_conf.use_short_preamble))
33f37249 8726 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
4c683607
JS		 8727
8728 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
8729 (ieee80211_is_data_qos(hdr->frame_control) &&
8730 sta && sta->ht_cap.cap &
8731 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
1df1de34 8732 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
4c683607
JS		 8733 }
8734
8735 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
8736 /*
8737 * Use RTS rate 24M - does the mac80211 tell
8738 * us which to use?
8739 */
8740 tx_desc->txdw4 |=
8741 cpu_to_le32(DESC_RATE_24M <<
33f37249 8742 TXDESC32_RTS_RATE_SHIFT);
4c683607 8743 tx_desc->txdw4 |=
33f37249
JS		 8744 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
8745 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4c683607 8746 }
a40ace4f 8747 } else {
dbb2896b 8748 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc;
cc2646d4 8749
4c683607
JS		 8750 tx_desc40->txdw4 = cpu_to_le32(rate);
8751 if (ieee80211_is_data(hdr->frame_control)) {
8752 tx_desc->txdw4 |=
8753 cpu_to_le32(0x1f <<
33f37249 8754 TXDESC40_DATA_RATE_FB_SHIFT);
4c683607
JS		 8755 }
8756
cc2646d4 8757 tx_desc40->txdw9 =
33f37249 8758 cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
cc2646d4 8759
a40ace4f 8760 if (ampdu_enable)
33f37249 8761 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
a40ace4f 8762 else
33f37249 8763 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
26f1fad2 8764
4c683607
JS		 8765 if (ieee80211_is_mgmt(hdr->frame_control)) {
8766 tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value);
8767 tx_desc40->txdw3 |=
33f37249 8768 cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
4c683607 8769 tx_desc40->txdw4 |=
33f37249 8770 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
4c683607 8771 tx_desc40->txdw4 |=
33f37249 8772 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
4c683607
JS		 8773 }
8774
8775 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
8776 (sta && vif && vif->bss_conf.use_short_preamble))
8777 tx_desc40->txdw5 |=
33f37249 8778 cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
4c683607
JS		 8779
8780 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
8781 /*
8782 * Use RTS rate 24M - does the mac80211 tell
8783 * us which to use?
8784 */
8785 tx_desc->txdw4 |=
8786 cpu_to_le32(DESC_RATE_24M <<
33f37249
JS		 8787 TXDESC40_RTS_RATE_SHIFT);
8788 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
8789 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
4c683607 8790 }
6979494a 8791 }
26f1fad2
JS		 8792
8793 rtl8xxxu_calc_tx_desc_csum(tx_desc);
8794
8795 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
8796 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
8797
8798 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
8799 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
8800 if (ret) {
8801 usb_unanchor_urb(&tx_urb->urb);
8802 rtl8xxxu_free_tx_urb(priv, tx_urb);
8803 goto error;
8804 }
8805 return;
8806error:
8807 dev_kfree_skb(skb);
8808}
8809
8810static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
8811 struct ieee80211_rx_status *rx_status,
87957081
JS		 8812 struct rtl8723au_phy_stats *phy_stats,
8813 u32 rxmcs)
26f1fad2
JS		 8814{
8815 if (phy_stats->sgi_en)
8816 rx_status->flag |= RX_FLAG_SHORT_GI;
8817
87957081 8818 if (rxmcs < DESC_RATE_6M) {
26f1fad2
JS		 8819 /*
8820 * Handle PHY stats for CCK rates
8821 */
8822 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
8823
8824 switch (cck_agc_rpt & 0xc0) {
8825 case 0xc0:
8826 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
8827 break;
8828 case 0x80:
8829 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
8830 break;
8831 case 0x40:
8832 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
8833 break;
8834 case 0x00:
8835 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
8836 break;
8837 }
8838 } else {
8839 rx_status->signal =
8840 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
8841 }
8842}
8843
8844static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
8845{
8846 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
8847 unsigned long flags;
8848
8849 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8850
8851 list_for_each_entry_safe(rx_urb, tmp,
8852 &priv->rx_urb_pending_list, list) {
8853 list_del(&rx_urb->list);
8854 priv->rx_urb_pending_count--;
8855 usb_free_urb(&rx_urb->urb);
8856 }
8857
8858 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8859}
8860
8861static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
8862 struct rtl8xxxu_rx_urb *rx_urb)
8863{
8864 struct sk_buff *skb;
8865 unsigned long flags;
8866 int pending = 0;
8867
8868 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8869
8870 if (!priv->shutdown) {
8871 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
8872 priv->rx_urb_pending_count++;
8873 pending = priv->rx_urb_pending_count;
8874 } else {
8875 skb = (struct sk_buff *)rx_urb->urb.context;
8876 dev_kfree_skb(skb);
8877 usb_free_urb(&rx_urb->urb);
8878 }
8879
8880 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8881
8882 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
8883 schedule_work(&priv->rx_urb_wq);
8884}
8885
8886static void rtl8xxxu_rx_urb_work(struct work_struct *work)
8887{
8888 struct rtl8xxxu_priv *priv;
8889 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
8890 struct list_head local;
8891 struct sk_buff *skb;
8892 unsigned long flags;
8893 int ret;
8894
8895 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
8896 INIT_LIST_HEAD(&local);
8897
8898 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8899
8900 list_splice_init(&priv->rx_urb_pending_list, &local);
8901 priv->rx_urb_pending_count = 0;
8902
8903 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8904
8905 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
8906 list_del_init(&rx_urb->list);
8907 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
8908 /*
8909 * If out of memory or temporary error, put it back on the
8910 * queue and try again. Otherwise the device is dead/gone
8911 * and we should drop it.
8912 */
8913 switch (ret) {
8914 case 0:
8915 break;
8916 case -ENOMEM:
8917 case -EAGAIN:
8918 rtl8xxxu_queue_rx_urb(priv, rx_urb);
8919 break;
8920 default:
8921 pr_info("failed to requeue urb %i\n", ret);
8922 skb = (struct sk_buff *)rx_urb->urb.context;
8923 dev_kfree_skb(skb);
8924 usb_free_urb(&rx_urb->urb);
8925 }
8926 }
8927}
8928
a49c7ce1 8929static int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv,
b18cdfdb
JS		 8930 struct sk_buff *skb,
8931 struct ieee80211_rx_status *rx_status)
8932{
a49c7ce1
JS		 8933 struct rtl8xxxu_rxdesc16 *rx_desc =
8934 (struct rtl8xxxu_rxdesc16 *)skb->data;
b18cdfdb 8935 struct rtl8723au_phy_stats *phy_stats;
2cb79eb7
JS		 8936 __le32 *_rx_desc_le = (__le32 *)skb->data;
8937 u32 *_rx_desc = (u32 *)skb->data;
b18cdfdb 8938 int drvinfo_sz, desc_shift;
2cb79eb7
JS		 8939 int i;
8940
a49c7ce1 8941 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
2cb79eb7 8942 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
b18cdfdb 8943
a49c7ce1 8944 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
b18cdfdb
JS		 8945
8946 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
8947
8948 drvinfo_sz = rx_desc->drvinfo_sz * 8;
8949 desc_shift = rx_desc->shift;
8950 skb_pull(skb, drvinfo_sz + desc_shift);
8951
8952 if (rx_desc->phy_stats)
87957081
JS		 8953 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
8954 rx_desc->rxmcs);
b18cdfdb
JS		 8955
8956 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
8957 rx_status->flag |= RX_FLAG_MACTIME_START;
8958
8959 if (!rx_desc->swdec)
8960 rx_status->flag |= RX_FLAG_DECRYPTED;
8961 if (rx_desc->crc32)
8962 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
8963 if (rx_desc->bw)
8964 rx_status->flag |= RX_FLAG_40MHZ;
8965
8966 if (rx_desc->rxht) {
8967 rx_status->flag |= RX_FLAG_HT;
8968 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
8969 } else {
8970 rx_status->rate_idx = rx_desc->rxmcs;
8971 }
8972
8973 return RX_TYPE_DATA_PKT;
8974}
8975
a49c7ce1 8976static int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv,
b18cdfdb
JS		 8977 struct sk_buff *skb,
8978 struct ieee80211_rx_status *rx_status)
8979{
a49c7ce1
JS		 8980 struct rtl8xxxu_rxdesc24 *rx_desc =
8981 (struct rtl8xxxu_rxdesc24 *)skb->data;
b18cdfdb 8982 struct rtl8723au_phy_stats *phy_stats;
2cb79eb7
JS		 8983 __le32 *_rx_desc_le = (__le32 *)skb->data;
8984 u32 *_rx_desc = (u32 *)skb->data;
b18cdfdb 8985 int drvinfo_sz, desc_shift;
2cb79eb7
JS		 8986 int i;
8987
a49c7ce1 8988 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
2cb79eb7 8989 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
b18cdfdb 8990
a49c7ce1 8991 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
b18cdfdb
JS		 8992
8993 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
8994
8995 drvinfo_sz = rx_desc->drvinfo_sz * 8;
8996 desc_shift = rx_desc->shift;
8997 skb_pull(skb, drvinfo_sz + desc_shift);
8998
e975b87c
JS		 8999 if (rx_desc->rpt_sel) {
9000 struct device *dev = &priv->udev->dev;
9001 dev_dbg(dev, "%s: C2H packet\n", __func__);
9002 return RX_TYPE_C2H;
9003 }
9004
87957081
JS		 9005 if (rx_desc->phy_stats)
9006 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
9007 rx_desc->rxmcs);
9008
b18cdfdb
JS		 9009 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
9010 rx_status->flag |= RX_FLAG_MACTIME_START;
9011
9012 if (!rx_desc->swdec)
9013 rx_status->flag |= RX_FLAG_DECRYPTED;
9014 if (rx_desc->crc32)
9015 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
9016 if (rx_desc->bw)
9017 rx_status->flag |= RX_FLAG_40MHZ;
9018
9019 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
9020 rx_status->flag |= RX_FLAG_HT;
9021 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
9022 } else {
9023 rx_status->rate_idx = rx_desc->rxmcs;
9024 }
9025
e975b87c 9026 return RX_TYPE_DATA_PKT;
b18cdfdb
JS		 9027}
9028
b2b43b78
JS		 9029static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
9030 struct sk_buff *skb)
9031{
9032 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
9033 struct device *dev = &priv->udev->dev;
9034 int len;
9035
9036 len = skb->len - 2;
9037
5e00d503
JS		 9038 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
9039 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
b2b43b78
JS		 9040
9041 switch(c2h->id) {
9042 case C2H_8723B_BT_INFO:
9043 if (c2h->bt_info.response_source >
9044 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
5e00d503 9045 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
b2b43b78 9046 else
5e00d503 9047 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
b2b43b78
JS		 9048
9049 if (c2h->bt_info.bt_has_reset)
5e00d503 9050 dev_dbg(dev, "BT has been reset\n");
394f1bd3 9051 if (c2h->bt_info.tx_rx_mask)
5e00d503 9052 dev_dbg(dev, "BT TRx mask\n");
b2b43b78
JS		 9053
9054 break;
394f1bd3 9055 case C2H_8723B_BT_MP_INFO:
5e00d503
JS		 9056 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
9057 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
394f1bd3 9058 break;
55a18dd1
JS		 9059 case C2H_8723B_RA_REPORT:
9060 dev_dbg(dev,
9061 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
9062 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
9063 c2h->ra_report.macid, c2h->ra_report.noisy_state);
9064 break;
b2b43b78 9065 default:
739dc9f2
JS		 9066 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
9067 c2h->id, c2h->seq);
9068 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
9069 16, 1, c2h->raw.payload, len, false);
b2b43b78
JS		 9070 break;
9071 }
9072}
9073
26f1fad2
JS		 9074static void rtl8xxxu_rx_complete(struct urb *urb)
9075{
9076 struct rtl8xxxu_rx_urb *rx_urb =
9077 container_of(urb, struct rtl8xxxu_rx_urb, urb);
9078 struct ieee80211_hw *hw = rx_urb->hw;
9079 struct rtl8xxxu_priv *priv = hw->priv;
9080 struct sk_buff *skb = (struct sk_buff *)urb->context;
26f1fad2 9081 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
26f1fad2 9082 struct device *dev = &priv->udev->dev;
2cb79eb7 9083 int rx_type;
26f1fad2 9084
26f1fad2
JS		 9085 skb_put(skb, urb->actual_length);
9086
9087 if (urb->status == 0) {
26f1fad2
JS		 9088 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
9089
b18cdfdb 9090 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
26f1fad2
JS		 9091
9092 rx_status->freq = hw->conf.chandef.chan->center_freq;
9093 rx_status->band = hw->conf.chandef.chan->band;
9094
b18cdfdb
JS		 9095 if (rx_type == RX_TYPE_DATA_PKT)
9096 ieee80211_rx_irqsafe(hw, skb);
b2b43b78
JS		 9097 else {
9098 rtl8723bu_handle_c2h(priv, skb);
b18cdfdb 9099 dev_kfree_skb(skb);
b2b43b78 9100 }
26f1fad2 9101
26f1fad2
JS		 9102 skb = NULL;
9103 rx_urb->urb.context = NULL;
9104 rtl8xxxu_queue_rx_urb(priv, rx_urb);
9105 } else {
9106 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
9107 goto cleanup;
9108 }
9109 return;
9110
9111cleanup:
9112 usb_free_urb(urb);
9113 dev_kfree_skb(skb);
9114 return;
9115}
9116
9117static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
9118 struct rtl8xxxu_rx_urb *rx_urb)
9119{
9120 struct sk_buff *skb;
9121 int skb_size;
a49c7ce1 9122 int ret, rx_desc_sz;
26f1fad2 9123
a49c7ce1
JS		 9124 rx_desc_sz = priv->fops->rx_desc_size;
9125 skb_size = rx_desc_sz + RTL_RX_BUFFER_SIZE;
26f1fad2
JS		 9126 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
9127 if (!skb)
9128 return -ENOMEM;
9129
a49c7ce1 9130 memset(skb->data, 0, rx_desc_sz);
26f1fad2
JS		 9131 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
9132 skb_size, rtl8xxxu_rx_complete, skb);
9133 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
9134 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
9135 if (ret)
9136 usb_unanchor_urb(&rx_urb->urb);
9137 return ret;
9138}
9139
9140static void rtl8xxxu_int_complete(struct urb *urb)
9141{
9142 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
9143 struct device *dev = &priv->udev->dev;
9144 int ret;
9145
9146 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
9147 if (urb->status == 0) {
9148 usb_anchor_urb(urb, &priv->int_anchor);
9149 ret = usb_submit_urb(urb, GFP_ATOMIC);
9150 if (ret)
9151 usb_unanchor_urb(urb);
9152 } else {
9153 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
9154 }
9155}
9156
9157
9158static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
9159{
9160 struct rtl8xxxu_priv *priv = hw->priv;
9161 struct urb *urb;
9162 u32 val32;
9163 int ret;
9164
9165 urb = usb_alloc_urb(0, GFP_KERNEL);
9166 if (!urb)
9167 return -ENOMEM;
9168
9169 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
9170 priv->int_buf, USB_INTR_CONTENT_LENGTH,
9171 rtl8xxxu_int_complete, priv, 1);
9172 usb_anchor_urb(urb, &priv->int_anchor);
9173 ret = usb_submit_urb(urb, GFP_KERNEL);
9174 if (ret) {
9175 usb_unanchor_urb(urb);
9176 goto error;
9177 }
9178
9179 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
9180 val32 |= USB_HIMR_CPWM;
9181 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
9182
9183error:
9184 return ret;
9185}
9186
9187static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
9188 struct ieee80211_vif *vif)
9189{
9190 struct rtl8xxxu_priv *priv = hw->priv;
9191 int ret;
9192 u8 val8;
9193
9194 switch (vif->type) {
9195 case NL80211_IFTYPE_STATION:
9196 rtl8723a_stop_tx_beacon(priv);
9197
9198 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
9199 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
9200 BEACON_DISABLE_TSF_UPDATE;
9201 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
9202 ret = 0;
9203 break;
9204 default:
9205 ret = -EOPNOTSUPP;
9206 }
9207
9208 rtl8xxxu_set_linktype(priv, vif->type);
9209
9210 return ret;
9211}
9212
9213static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
9214 struct ieee80211_vif *vif)
9215{
9216 struct rtl8xxxu_priv *priv = hw->priv;
9217
9218 dev_dbg(&priv->udev->dev, "%s\n", __func__);
9219}
9220
9221static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
9222{
9223 struct rtl8xxxu_priv *priv = hw->priv;
9224 struct device *dev = &priv->udev->dev;
9225 u16 val16;
9226 int ret = 0, channel;
9227 bool ht40;
9228
9229 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
9230 dev_info(dev,
9231 "%s: channel: %i (changed %08x chandef.width %02x)\n",
9232 __func__, hw->conf.chandef.chan->hw_value,
9233 changed, hw->conf.chandef.width);
9234
9235 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
9236 val16 = ((hw->conf.long_frame_max_tx_count <<
9237 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
9238 ((hw->conf.short_frame_max_tx_count <<
9239 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
9240 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
9241 }
9242
9243 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
9244 switch (hw->conf.chandef.width) {
9245 case NL80211_CHAN_WIDTH_20_NOHT:
9246 case NL80211_CHAN_WIDTH_20:
9247 ht40 = false;
9248 break;
9249 case NL80211_CHAN_WIDTH_40:
9250 ht40 = true;
9251 break;
9252 default:
9253 ret = -ENOTSUPP;
9254 goto exit;
9255 }
9256
9257 channel = hw->conf.chandef.chan->hw_value;
9258
e796dab4 9259 priv->fops->set_tx_power(priv, channel, ht40);
26f1fad2 9260
1ea8e846 9261 priv->fops->config_channel(hw);
26f1fad2
JS		 9262 }
9263
9264exit:
9265 return ret;
9266}
9267
9268static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
9269 struct ieee80211_vif *vif, u16 queue,
9270 const struct ieee80211_tx_queue_params *param)
9271{
9272 struct rtl8xxxu_priv *priv = hw->priv;
9273 struct device *dev = &priv->udev->dev;
9274 u32 val32;
9275 u8 aifs, acm_ctrl, acm_bit;
9276
9277 aifs = param->aifs;
9278
9279 val32 = aifs |
9280 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
9281 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
9282 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
9283
9284 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
9285 dev_dbg(dev,
9286 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
9287 __func__, queue, val32, param->acm, acm_ctrl);
9288
9289 switch (queue) {
9290 case IEEE80211_AC_VO:
9291 acm_bit = ACM_HW_CTRL_VO;
9292 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
9293 break;
9294 case IEEE80211_AC_VI:
9295 acm_bit = ACM_HW_CTRL_VI;
9296 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
9297 break;
9298 case IEEE80211_AC_BE:
9299 acm_bit = ACM_HW_CTRL_BE;
9300 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
9301 break;
9302 case IEEE80211_AC_BK:
9303 acm_bit = ACM_HW_CTRL_BK;
9304 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
9305 break;
9306 default:
9307 acm_bit = 0;
9308 break;
9309 }
9310
9311 if (param->acm)
9312 acm_ctrl |= acm_bit;
9313 else
9314 acm_ctrl &= ~acm_bit;
9315 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
9316
9317 return 0;
9318}
9319
9320static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
9321 unsigned int changed_flags,
9322 unsigned int *total_flags, u64 multicast)
9323{
9324 struct rtl8xxxu_priv *priv = hw->priv;
3bed4bfa 9325 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
26f1fad2
JS		 9326
9327 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
9328 __func__, changed_flags, *total_flags);
9329
3bed4bfa
BR		 9330 /*
9331 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
9332 */
9333
9334 if (*total_flags & FIF_FCSFAIL)
9335 rcr |= RCR_ACCEPT_CRC32;
9336 else
9337 rcr &= ~RCR_ACCEPT_CRC32;
9338
9339 /*
9340 * FIF_PLCPFAIL not supported?
9341 */
9342
9343 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
9344 rcr &= ~RCR_CHECK_BSSID_BEACON;
9345 else
9346 rcr |= RCR_CHECK_BSSID_BEACON;
9347
9348 if (*total_flags & FIF_CONTROL)
9349 rcr |= RCR_ACCEPT_CTRL_FRAME;
9350 else
9351 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
9352
9353 if (*total_flags & FIF_OTHER_BSS) {
9354 rcr |= RCR_ACCEPT_AP;
9355 rcr &= ~RCR_CHECK_BSSID_MATCH;
9356 } else {
9357 rcr &= ~RCR_ACCEPT_AP;
9358 rcr |= RCR_CHECK_BSSID_MATCH;
9359 }
9360
9361 if (*total_flags & FIF_PSPOLL)
9362 rcr |= RCR_ACCEPT_PM;
9363 else
9364 rcr &= ~RCR_ACCEPT_PM;
9365
9366 /*
9367 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
9368 */
9369
9370 rtl8xxxu_write32(priv, REG_RCR, rcr);
9371
755bda11
JS		 9372 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
9373 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
9374 FIF_PROBE_REQ);
26f1fad2
JS		 9375}
9376
9377static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
9378{
9379 if (rts > 2347)
9380 return -EINVAL;
9381
9382 return 0;
9383}
9384
9385static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
9386 struct ieee80211_vif *vif,
9387 struct ieee80211_sta *sta,
9388 struct ieee80211_key_conf *key)
9389{
9390 struct rtl8xxxu_priv *priv = hw->priv;
9391 struct device *dev = &priv->udev->dev;
9392 u8 mac_addr[ETH_ALEN];
9393 u8 val8;
9394 u16 val16;
9395 u32 val32;
9396 int retval = -EOPNOTSUPP;
9397
9398 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
9399 __func__, cmd, key->cipher, key->keyidx);
9400
9401 if (vif->type != NL80211_IFTYPE_STATION)
9402 return -EOPNOTSUPP;
9403
9404 if (key->keyidx > 3)
9405 return -EOPNOTSUPP;
9406
9407 switch (key->cipher) {
9408 case WLAN_CIPHER_SUITE_WEP40:
9409 case WLAN_CIPHER_SUITE_WEP104:
9410
9411 break;
9412 case WLAN_CIPHER_SUITE_CCMP:
9413 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
9414 break;
9415 case WLAN_CIPHER_SUITE_TKIP:
9416 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
9417 default:
9418 return -EOPNOTSUPP;
9419 }
9420
9421 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
9422 dev_dbg(dev, "%s: pairwise key\n", __func__);
9423 ether_addr_copy(mac_addr, sta->addr);
9424 } else {
9425 dev_dbg(dev, "%s: group key\n", __func__);
9426 eth_broadcast_addr(mac_addr);
9427 }
9428
9429 val16 = rtl8xxxu_read16(priv, REG_CR);
9430 val16 |= CR_SECURITY_ENABLE;
9431 rtl8xxxu_write16(priv, REG_CR, val16);
9432
9433 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
9434 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
9435 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
9436 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
9437
9438 switch (cmd) {
9439 case SET_KEY:
9440 key->hw_key_idx = key->keyidx;
9441 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
9442 rtl8xxxu_cam_write(priv, key, mac_addr);
9443 retval = 0;
9444 break;
9445 case DISABLE_KEY:
9446 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
9447 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
9448 key->keyidx << CAM_CMD_KEY_SHIFT;
9449 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
9450 retval = 0;
9451 break;
9452 default:
9453 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
9454 }
9455
9456 return retval;
9457}
9458
9459static int
9460rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 9461 struct ieee80211_ampdu_params *params)
26f1fad2
JS		 9462{
9463 struct rtl8xxxu_priv *priv = hw->priv;
9464 struct device *dev = &priv->udev->dev;
9465 u8 ampdu_factor, ampdu_density;
50ea05ef
SS		 9466 struct ieee80211_sta *sta = params->sta;
9467 enum ieee80211_ampdu_mlme_action action = params->action;
26f1fad2
JS		 9468
9469 switch (action) {
9470 case IEEE80211_AMPDU_TX_START:
9471 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
9472 ampdu_factor = sta->ht_cap.ampdu_factor;
9473 ampdu_density = sta->ht_cap.ampdu_density;
9474 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
9475 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
9476 dev_dbg(dev,
9477 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
9478 ampdu_factor, ampdu_density);
9479 break;
9480 case IEEE80211_AMPDU_TX_STOP_FLUSH:
9481 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
9482 rtl8xxxu_set_ampdu_factor(priv, 0);
9483 rtl8xxxu_set_ampdu_min_space(priv, 0);
9484 break;
9485 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
9486 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
9487 __func__);
9488 rtl8xxxu_set_ampdu_factor(priv, 0);
9489 rtl8xxxu_set_ampdu_min_space(priv, 0);
9490 break;
9491 case IEEE80211_AMPDU_RX_START:
9492 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
9493 break;
9494 case IEEE80211_AMPDU_RX_STOP:
9495 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
9496 break;
9497 default:
9498 break;
9499 }
9500 return 0;
9501}
9502
9503static int rtl8xxxu_start(struct ieee80211_hw *hw)
9504{
9505 struct rtl8xxxu_priv *priv = hw->priv;
9506 struct rtl8xxxu_rx_urb *rx_urb;
9507 struct rtl8xxxu_tx_urb *tx_urb;
9508 unsigned long flags;
9509 int ret, i;
9510
9511 ret = 0;
9512
9513 init_usb_anchor(&priv->rx_anchor);
9514 init_usb_anchor(&priv->tx_anchor);
9515 init_usb_anchor(&priv->int_anchor);
9516
db08de94 9517 priv->fops->enable_rf(priv);
0e28b975
JS		 9518 if (priv->usb_interrupts) {
9519 ret = rtl8xxxu_submit_int_urb(hw);
9520 if (ret)
9521 goto exit;
9522 }
26f1fad2
JS		 9523
9524 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
9525 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
9526 if (!tx_urb) {
9527 if (!i)
9528 ret = -ENOMEM;
9529
9530 goto error_out;
9531 }
9532 usb_init_urb(&tx_urb->urb);
9533 INIT_LIST_HEAD(&tx_urb->list);
9534 tx_urb->hw = hw;
9535 list_add(&tx_urb->list, &priv->tx_urb_free_list);
9536 priv->tx_urb_free_count++;
9537 }
9538
9539 priv->tx_stopped = false;
9540
9541 spin_lock_irqsave(&priv->rx_urb_lock, flags);
9542 priv->shutdown = false;
9543 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
9544
9545 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
9546 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
9547 if (!rx_urb) {
9548 if (!i)
9549 ret = -ENOMEM;
9550
9551 goto error_out;
9552 }
9553 usb_init_urb(&rx_urb->urb);
9554 INIT_LIST_HEAD(&rx_urb->list);
9555 rx_urb->hw = hw;
9556
9557 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
9558 }
9559exit:
9560 /*
c85ea115 9561 * Accept all data and mgmt frames
26f1fad2 9562 */
c85ea115 9563 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
26f1fad2
JS		 9564 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
9565
9566 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
9567
9568 return ret;
9569
9570error_out:
9571 rtl8xxxu_free_tx_resources(priv);
9572 /*
9573 * Disable all data and mgmt frames
9574 */
9575 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
9576 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
9577
9578 return ret;
9579}
9580
9581static void rtl8xxxu_stop(struct ieee80211_hw *hw)
9582{
9583 struct rtl8xxxu_priv *priv = hw->priv;
9584 unsigned long flags;
9585
9586 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
9587
9588 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
9589 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
9590
9591 spin_lock_irqsave(&priv->rx_urb_lock, flags);
9592 priv->shutdown = true;
9593 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
9594
9595 usb_kill_anchored_urbs(&priv->rx_anchor);
9596 usb_kill_anchored_urbs(&priv->tx_anchor);
0e28b975
JS		 9597 if (priv->usb_interrupts)
9598 usb_kill_anchored_urbs(&priv->int_anchor);
26f1fad2 9599
265697eb
JS		 9600 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
9601
fc89a41f 9602 priv->fops->disable_rf(priv);
26f1fad2
JS		 9603
9604 /*
9605 * Disable interrupts
9606 */
0e28b975
JS		 9607 if (priv->usb_interrupts)
9608 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
26f1fad2
JS		 9609
9610 rtl8xxxu_free_rx_resources(priv);
9611 rtl8xxxu_free_tx_resources(priv);
9612}
9613
9614static const struct ieee80211_ops rtl8xxxu_ops = {
9615 .tx = rtl8xxxu_tx,
9616 .add_interface = rtl8xxxu_add_interface,
9617 .remove_interface = rtl8xxxu_remove_interface,
9618 .config = rtl8xxxu_config,
9619 .conf_tx = rtl8xxxu_conf_tx,
9620 .bss_info_changed = rtl8xxxu_bss_info_changed,
9621 .configure_filter = rtl8xxxu_configure_filter,
9622 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
9623 .start = rtl8xxxu_start,
9624 .stop = rtl8xxxu_stop,
9625 .sw_scan_start = rtl8xxxu_sw_scan_start,
9626 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
9627 .set_key = rtl8xxxu_set_key,
9628 .ampdu_action = rtl8xxxu_ampdu_action,
9629};
9630
9631static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
9632 struct usb_interface *interface)
9633{
9634 struct usb_interface_descriptor *interface_desc;
9635 struct usb_host_interface *host_interface;
9636 struct usb_endpoint_descriptor *endpoint;
9637 struct device *dev = &priv->udev->dev;
9638 int i, j = 0, endpoints;
9639 u8 dir, xtype, num;
9640 int ret = 0;
9641
9642 host_interface = &interface->altsetting[0];
9643 interface_desc = &host_interface->desc;
9644 endpoints = interface_desc->bNumEndpoints;
9645
9646 for (i = 0; i < endpoints; i++) {
9647 endpoint = &host_interface->endpoint[i].desc;
9648
9649 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
9650 num = usb_endpoint_num(endpoint);
9651 xtype = usb_endpoint_type(endpoint);
9652 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
9653 dev_dbg(dev,
9654 "%s: endpoint: dir %02x, # %02x, type %02x\n",
9655 __func__, dir, num, xtype);
9656 if (usb_endpoint_dir_in(endpoint) &&
9657 usb_endpoint_xfer_bulk(endpoint)) {
9658 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
9659 dev_dbg(dev, "%s: in endpoint num %i\n",
9660 __func__, num);
9661
9662 if (priv->pipe_in) {
9663 dev_warn(dev,
9664 "%s: Too many IN pipes\n", __func__);
9665 ret = -EINVAL;
9666 goto exit;
9667 }
9668
9669 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
9670 }
9671
9672 if (usb_endpoint_dir_in(endpoint) &&
9673 usb_endpoint_xfer_int(endpoint)) {
9674 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
9675 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
9676 __func__, num);
9677
9678 if (priv->pipe_interrupt) {
9679 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
9680 __func__);
9681 ret = -EINVAL;
9682 goto exit;
9683 }
9684
9685 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
9686 }
9687
9688 if (usb_endpoint_dir_out(endpoint) &&
9689 usb_endpoint_xfer_bulk(endpoint)) {
9690 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
9691 dev_dbg(dev, "%s: out endpoint num %i\n",
9692 __func__, num);
9693 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
9694 dev_warn(dev,
9695 "%s: Too many OUT pipes\n", __func__);
9696 ret = -EINVAL;
9697 goto exit;
9698 }
9699 priv->out_ep[j++] = num;
9700 }
9701 }
9702exit:
9703 priv->nr_out_eps = j;
9704 return ret;
9705}
9706
9707static int rtl8xxxu_probe(struct usb_interface *interface,
9708 const struct usb_device_id *id)
9709{
9710 struct rtl8xxxu_priv *priv;
9711 struct ieee80211_hw *hw;
9712 struct usb_device *udev;
9713 struct ieee80211_supported_band *sband;
9714 int ret = 0;
9715 int untested = 1;
9716
9717 udev = usb_get_dev(interface_to_usbdev(interface));
9718
9719 switch (id->idVendor) {
9720 case USB_VENDOR_ID_REALTEK:
9721 switch(id->idProduct) {
9722 case 0x1724:
9723 case 0x8176:
9724 case 0x8178:
9725 case 0x817f:
9726 untested = 0;
9727 break;
9728 }
9729 break;
9730 case 0x7392:
9731 if (id->idProduct == 0x7811)
9732 untested = 0;
9733 break;
e1d70c9b
JS		 9734 case 0x050d:
9735 if (id->idProduct == 0x1004)
9736 untested = 0;
9737 break;
26f1fad2
JS		 9738 default:
9739 break;
9740 }
9741
9742 if (untested) {
eaa4d14c 9743 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 9744 dev_info(&udev->dev,
9745 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
9746 id->idVendor, id->idProduct);
9747 dev_info(&udev->dev,
9748 "Please report results to Jes.Sorensen@gmail.com\n");
9749 }
9750
9751 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
9752 if (!hw) {
9753 ret = -ENOMEM;
9754 goto exit;
9755 }
9756
9757 priv = hw->priv;
9758 priv->hw = hw;
9759 priv->udev = udev;
9760 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
9761 mutex_init(&priv->usb_buf_mutex);
9762 mutex_init(&priv->h2c_mutex);
9763 INIT_LIST_HEAD(&priv->tx_urb_free_list);
9764 spin_lock_init(&priv->tx_urb_lock);
9765 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
9766 spin_lock_init(&priv->rx_urb_lock);
9767 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
9768
9769 usb_set_intfdata(interface, hw);
9770
9771 ret = rtl8xxxu_parse_usb(priv, interface);
9772 if (ret)
9773 goto exit;
9774
9775 ret = rtl8xxxu_identify_chip(priv);
9776 if (ret) {
9777 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
9778 goto exit;
9779 }
9780
9781 ret = rtl8xxxu_read_efuse(priv);
9782 if (ret) {
9783 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
9784 goto exit;
9785 }
9786
9787 ret = priv->fops->parse_efuse(priv);
9788 if (ret) {
9789 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
9790 goto exit;
9791 }
9792
9793 rtl8xxxu_print_chipinfo(priv);
9794
9795 ret = priv->fops->load_firmware(priv);
9796 if (ret) {
9797 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
9798 goto exit;
9799 }
9800
9801 ret = rtl8xxxu_init_device(hw);
9802
9803 hw->wiphy->max_scan_ssids = 1;
9804 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
9805 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
9806 hw->queues = 4;
9807
9808 sband = &rtl8xxxu_supported_band;
9809 sband->ht_cap.ht_supported = true;
9810 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
9811 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
9812 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
9813 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
9814 sband->ht_cap.mcs.rx_mask[0] = 0xff;
9815 sband->ht_cap.mcs.rx_mask[4] = 0x01;
9816 if (priv->rf_paths > 1) {
9817 sband->ht_cap.mcs.rx_mask[1] = 0xff;
9818 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
9819 }
9820 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
9821 /*
9822 * Some APs will negotiate HT20_40 in a noisy environment leading
9823 * to miserable performance. Rather than defaulting to this, only
9824 * enable it if explicitly requested at module load time.
9825 */
9826 if (rtl8xxxu_ht40_2g) {
9827 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
9828 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
9829 }
57fbcce3 9830 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
26f1fad2
JS		 9831
9832 hw->wiphy->rts_threshold = 2347;
9833
9834 SET_IEEE80211_DEV(priv->hw, &interface->dev);
9835 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
9836
179e1742 9837 hw->extra_tx_headroom = priv->fops->tx_desc_size;
26f1fad2
JS		 9838 ieee80211_hw_set(hw, SIGNAL_DBM);
9839 /*
9840 * The firmware handles rate control
9841 */
9842 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
9843 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
9844
9845 ret = ieee80211_register_hw(priv->hw);
9846 if (ret) {
9847 dev_err(&udev->dev, "%s: Failed to register: %i\n",
9848 __func__, ret);
9849 goto exit;
9850 }
9851
9852exit:
9853 if (ret < 0)
9854 usb_put_dev(udev);
9855 return ret;
9856}
9857
9858static void rtl8xxxu_disconnect(struct usb_interface *interface)
9859{
9860 struct rtl8xxxu_priv *priv;
9861 struct ieee80211_hw *hw;
9862
9863 hw = usb_get_intfdata(interface);
9864 priv = hw->priv;
9865
8cae2f1d
JS		 9866 ieee80211_unregister_hw(hw);
9867
9868 priv->fops->power_off(priv);
9869
26f1fad2
JS		 9870 usb_set_intfdata(interface, NULL);
9871
9872 dev_info(&priv->udev->dev, "disconnecting\n");
9873
26f1fad2
JS		 9874 kfree(priv->fw_data);
9875 mutex_destroy(&priv->usb_buf_mutex);
9876 mutex_destroy(&priv->h2c_mutex);
9877
9878 usb_put_dev(priv->udev);
9879 ieee80211_free_hw(hw);
9880}
9881
9882static struct rtl8xxxu_fileops rtl8723au_fops = {
9883 .parse_efuse = rtl8723au_parse_efuse,
9884 .load_firmware = rtl8723au_load_firmware,
9885 .power_on = rtl8723au_power_on,
fe37d5f6 9886 .power_off = rtl8xxxu_power_off,
7d4ccb8b 9887 .reset_8051 = rtl8xxxu_reset_8051,
74b99bed 9888 .llt_init = rtl8xxxu_init_llt_table,
de7c189c 9889 .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
4062b8ff 9890 .init_phy_rf = rtl8723au_init_phy_rf,
28466e92 9891 .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
e09718c2 9892 .config_channel = rtl8xxxu_gen1_config_channel,
a49c7ce1 9893 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
8396a41c 9894 .enable_rf = rtl8xxxu_gen1_enable_rf,
7eb1400c 9895 .disable_rf = rtl8xxxu_gen1_disable_rf,
747bf237 9896 .usb_quirks = rtl8xxxu_gen1_usb_quirks,
42a3bc7a 9897 .set_tx_power = rtl8xxxu_gen1_set_tx_power,
c6e39da0 9898 .update_rate_mask = rtl8xxxu_update_rate_mask,
beb55316 9899 .report_connect = rtl8xxxu_gen1_report_connect,
26f1fad2 9900 .writeN_block_size = 1024,
ed35d094
JS		 9901 .mbox_ext_reg = REG_HMBOX_EXT_0,
9902 .mbox_ext_width = 2,
dbb2896b 9903 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
a49c7ce1 9904 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
8634af5e
JS		 9905 .adda_1t_init = 0x0b1b25a0,
9906 .adda_1t_path_on = 0x0bdb25a0,
9907 .adda_2t_path_on_a = 0x04db25a4,
9908 .adda_2t_path_on_b = 0x0b1b25a4,
24e8e7ec 9909 .trxff_boundary = 0x27ff,
9b323ee9
JS		 9910 .pbp_rx = PBP_PAGE_SIZE_128,
9911 .pbp_tx = PBP_PAGE_SIZE_128,
8db71451 9912 .mactable = rtl8xxxu_gen1_mac_init_table,
26f1fad2
JS		 9913};
9914
35a741fe 9915static struct rtl8xxxu_fileops rtl8723bu_fops = {
3c836d60 9916 .parse_efuse = rtl8723bu_parse_efuse,
35a741fe 9917 .load_firmware = rtl8723bu_load_firmware,
42836db1 9918 .power_on = rtl8723bu_power_on,
fe37d5f6 9919 .power_off = rtl8723bu_power_off,
7d4ccb8b 9920 .reset_8051 = rtl8723bu_reset_8051,
35a741fe 9921 .llt_init = rtl8xxxu_auto_llt_table,
cb877250 9922 .init_phy_bb = rtl8723bu_init_phy_bb,
4062b8ff 9923 .init_phy_rf = rtl8723bu_init_phy_rf,
f0d9f5e9 9924 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
e1547c53 9925 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
3a56bf6a 9926 .config_channel = rtl8xxxu_gen2_config_channel,
a49c7ce1 9927 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
3e88ca44 9928 .init_aggregation = rtl8723bu_init_aggregation,
9c79bf95 9929 .init_statistics = rtl8723bu_init_statistics,
db08de94 9930 .enable_rf = rtl8723b_enable_rf,
6a07b791 9931 .disable_rf = rtl8xxxu_gen2_disable_rf,
747bf237 9932 .usb_quirks = rtl8xxxu_gen2_usb_quirks,
e796dab4 9933 .set_tx_power = rtl8723b_set_tx_power,
a8c8dfa5 9934 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
32353a78 9935 .report_connect = rtl8xxxu_gen2_report_connect,
adfc0124 9936 .writeN_block_size = 1024,
ed35d094
JS		 9937 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
9938 .mbox_ext_width = 4,
dbb2896b 9939 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
a49c7ce1 9940 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
0d698dec 9941 .has_s0s1 = 1,
8634af5e
JS		 9942 .adda_1t_init = 0x01c00014,
9943 .adda_1t_path_on = 0x01c00014,
9944 .adda_2t_path_on_a = 0x01c00014,
9945 .adda_2t_path_on_b = 0x01c00014,
24e8e7ec 9946 .trxff_boundary = 0x3f7f,
9b323ee9
JS		 9947 .pbp_rx = PBP_PAGE_SIZE_256,
9948 .pbp_tx = PBP_PAGE_SIZE_256,
c606e662 9949 .mactable = rtl8723b_mac_init_table,
35a741fe
JS		 9950};
9951
c0963772
KV		 9952#ifdef CONFIG_RTL8XXXU_UNTESTED
9953
26f1fad2
JS		 9954static struct rtl8xxxu_fileops rtl8192cu_fops = {
9955 .parse_efuse = rtl8192cu_parse_efuse,
9956 .load_firmware = rtl8192cu_load_firmware,
9957 .power_on = rtl8192cu_power_on,
fe37d5f6 9958 .power_off = rtl8xxxu_power_off,
7d4ccb8b 9959 .reset_8051 = rtl8xxxu_reset_8051,
74b99bed 9960 .llt_init = rtl8xxxu_init_llt_table,
de7c189c 9961 .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
4062b8ff 9962 .init_phy_rf = rtl8192cu_init_phy_rf,
28466e92 9963 .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
e09718c2 9964 .config_channel = rtl8xxxu_gen1_config_channel,
a49c7ce1 9965 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
8396a41c 9966 .enable_rf = rtl8xxxu_gen1_enable_rf,
7eb1400c 9967 .disable_rf = rtl8xxxu_gen1_disable_rf,
747bf237 9968 .usb_quirks = rtl8xxxu_gen1_usb_quirks,
42a3bc7a 9969 .set_tx_power = rtl8xxxu_gen1_set_tx_power,
c6e39da0 9970 .update_rate_mask = rtl8xxxu_update_rate_mask,
beb55316 9971 .report_connect = rtl8xxxu_gen1_report_connect,
26f1fad2 9972 .writeN_block_size = 128,
ed35d094
JS		 9973 .mbox_ext_reg = REG_HMBOX_EXT_0,
9974 .mbox_ext_width = 2,
dbb2896b 9975 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
a49c7ce1 9976 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
8634af5e
JS		 9977 .adda_1t_init = 0x0b1b25a0,
9978 .adda_1t_path_on = 0x0bdb25a0,
9979 .adda_2t_path_on_a = 0x04db25a4,
9980 .adda_2t_path_on_b = 0x0b1b25a4,
24e8e7ec 9981 .trxff_boundary = 0x27ff,
9b323ee9
JS		 9982 .pbp_rx = PBP_PAGE_SIZE_128,
9983 .pbp_tx = PBP_PAGE_SIZE_128,
8db71451 9984 .mactable = rtl8xxxu_gen1_mac_init_table,
26f1fad2
JS		 9985};
9986
c0963772
KV		 9987#endif
9988
3307d840
JS		 9989static struct rtl8xxxu_fileops rtl8192eu_fops = {
9990 .parse_efuse = rtl8192eu_parse_efuse,
9991 .load_firmware = rtl8192eu_load_firmware,
c05a9dbf 9992 .power_on = rtl8192eu_power_on,
fe37d5f6 9993 .power_off = rtl8xxxu_power_off,
7d4ccb8b 9994 .reset_8051 = rtl8xxxu_reset_8051,
74b99bed 9995 .llt_init = rtl8xxxu_auto_llt_table,
cb877250 9996 .init_phy_bb = rtl8192eu_init_phy_bb,
4062b8ff 9997 .init_phy_rf = rtl8192eu_init_phy_rf,
f991f4e9 9998 .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
3a56bf6a 9999 .config_channel = rtl8xxxu_gen2_config_channel,
a49c7ce1 10000 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
ae5c01fd 10001 .enable_rf = rtl8192e_enable_rf,
6a07b791 10002 .disable_rf = rtl8xxxu_gen2_disable_rf,
747bf237 10003 .usb_quirks = rtl8xxxu_gen2_usb_quirks,
57e42a21 10004 .set_tx_power = rtl8192e_set_tx_power,
a8c8dfa5 10005 .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
32353a78 10006 .report_connect = rtl8xxxu_gen2_report_connect,
c05a9dbf 10007 .writeN_block_size = 128,
ed35d094
JS		 10008 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
10009 .mbox_ext_width = 4,
f3fc2511 10010 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
a49c7ce1 10011 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
55c0b6ae 10012 .has_s0s1 = 0,
8634af5e
JS		 10013 .adda_1t_init = 0x0fc01616,
10014 .adda_1t_path_on = 0x0fc01616,
10015 .adda_2t_path_on_a = 0x0fc01616,
10016 .adda_2t_path_on_b = 0x0fc01616,
24e8e7ec 10017 .trxff_boundary = 0x3cff,
c606e662 10018 .mactable = rtl8192e_mac_init_table,
89c2a097
JS		 10019 .total_page_num = TX_TOTAL_PAGE_NUM_8192E,
10020 .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E,
10021 .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E,
10022 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E,
3307d840
JS		 10023};
10024
26f1fad2
JS		 10025static struct usb_device_id dev_table[] = {
10026{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
10027 .driver_info = (unsigned long)&rtl8723au_fops},
10028{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
10029 .driver_info = (unsigned long)&rtl8723au_fops},
10030{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
10031 .driver_info = (unsigned long)&rtl8723au_fops},
3307d840
JS		 10032{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
10033 .driver_info = (unsigned long)&rtl8192eu_fops},
35a741fe
JS		 10034{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
10035 .driver_info = (unsigned long)&rtl8723bu_fops},
033695bd
KV		 10036#ifdef CONFIG_RTL8XXXU_UNTESTED
10037/* Still supported by rtlwifi */
26f1fad2
JS		 10038{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
10039 .driver_info = (unsigned long)&rtl8192cu_fops},
10040{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
10041 .driver_info = (unsigned long)&rtl8192cu_fops},
10042{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
10043 .driver_info = (unsigned long)&rtl8192cu_fops},
10044/* Tested by Larry Finger */
10045{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
10046 .driver_info = (unsigned long)&rtl8192cu_fops},
e1d70c9b
JS		 10047/* Tested by Andrea Merello */
10048{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
10049 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 10050/* Currently untested 8188 series devices */
10051{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
10052 .driver_info = (unsigned long)&rtl8192cu_fops},
10053{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
10054 .driver_info = (unsigned long)&rtl8192cu_fops},
10055{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
10056 .driver_info = (unsigned long)&rtl8192cu_fops},
10057{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
10058 .driver_info = (unsigned long)&rtl8192cu_fops},
10059{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
10060 .driver_info = (unsigned long)&rtl8192cu_fops},
10061{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
10062 .driver_info = (unsigned long)&rtl8192cu_fops},
10063{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
10064 .driver_info = (unsigned long)&rtl8192cu_fops},
10065{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
10066 .driver_info = (unsigned long)&rtl8192cu_fops},
10067{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
10068 .driver_info = (unsigned long)&rtl8192cu_fops},
10069{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
10070 .driver_info = (unsigned long)&rtl8192cu_fops},
10071{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
10072 .driver_info = (unsigned long)&rtl8192cu_fops},
10073{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
10074 .driver_info = (unsigned long)&rtl8192cu_fops},
10075{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
10076 .driver_info = (unsigned long)&rtl8192cu_fops},
10077{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
10078 .driver_info = (unsigned long)&rtl8192cu_fops},
10079{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
10080 .driver_info = (unsigned long)&rtl8192cu_fops},
10081{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
10082 .driver_info = (unsigned long)&rtl8192cu_fops},
10083{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
10084 .driver_info = (unsigned long)&rtl8192cu_fops},
10085{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
10086 .driver_info = (unsigned long)&rtl8192cu_fops},
10087{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
10088 .driver_info = (unsigned long)&rtl8192cu_fops},
10089{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
10090 .driver_info = (unsigned long)&rtl8192cu_fops},
10091{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
10092 .driver_info = (unsigned long)&rtl8192cu_fops},
10093{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
10094 .driver_info = (unsigned long)&rtl8192cu_fops},
10095{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
10096 .driver_info = (unsigned long)&rtl8192cu_fops},
10097{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
10098 .driver_info = (unsigned long)&rtl8192cu_fops},
10099{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
10100 .driver_info = (unsigned long)&rtl8192cu_fops},
10101{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
10102 .driver_info = (unsigned long)&rtl8192cu_fops},
10103{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
10104 .driver_info = (unsigned long)&rtl8192cu_fops},
10105{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
10106 .driver_info = (unsigned long)&rtl8192cu_fops},
10107{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
10108 .driver_info = (unsigned long)&rtl8192cu_fops},
10109{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
10110 .driver_info = (unsigned long)&rtl8192cu_fops},
10111{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
10112 .driver_info = (unsigned long)&rtl8192cu_fops},
10113{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
10114 .driver_info = (unsigned long)&rtl8192cu_fops},
10115{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
10116 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 10117{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
10118 .driver_info = (unsigned long)&rtl8192cu_fops},
10119{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
10120 .driver_info = (unsigned long)&rtl8192cu_fops},
10121{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
10122 .driver_info = (unsigned long)&rtl8192cu_fops},
10123{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
10124 .driver_info = (unsigned long)&rtl8192cu_fops},
10125{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
10126 .driver_info = (unsigned long)&rtl8192cu_fops},
10127{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
10128 .driver_info = (unsigned long)&rtl8192cu_fops},
10129{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
10130 .driver_info = (unsigned long)&rtl8192cu_fops},
10131/* Currently untested 8192 series devices */
10132{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
10133 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 10134{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
10135 .driver_info = (unsigned long)&rtl8192cu_fops},
10136{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
10137 .driver_info = (unsigned long)&rtl8192cu_fops},
10138{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
10139 .driver_info = (unsigned long)&rtl8192cu_fops},
10140{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
10141 .driver_info = (unsigned long)&rtl8192cu_fops},
10142{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
10143 .driver_info = (unsigned long)&rtl8192cu_fops},
10144{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
10145 .driver_info = (unsigned long)&rtl8192cu_fops},
10146{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
10147 .driver_info = (unsigned long)&rtl8192cu_fops},
10148{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
10149 .driver_info = (unsigned long)&rtl8192cu_fops},
10150{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
10151 .driver_info = (unsigned long)&rtl8192cu_fops},
10152{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
10153 .driver_info = (unsigned long)&rtl8192cu_fops},
10154{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
10155 .driver_info = (unsigned long)&rtl8192cu_fops},
10156{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
10157 .driver_info = (unsigned long)&rtl8192cu_fops},
10158{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
10159 .driver_info = (unsigned long)&rtl8192cu_fops},
10160{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
10161 .driver_info = (unsigned long)&rtl8192cu_fops},
10162{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
10163 .driver_info = (unsigned long)&rtl8192cu_fops},
10164{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
10165 .driver_info = (unsigned long)&rtl8192cu_fops},
10166{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
10167 .driver_info = (unsigned long)&rtl8192cu_fops},
10168{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
10169 .driver_info = (unsigned long)&rtl8192cu_fops},
10170{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
10171 .driver_info = (unsigned long)&rtl8192cu_fops},
10172{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
10173 .driver_info = (unsigned long)&rtl8192cu_fops},
10174{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
10175 .driver_info = (unsigned long)&rtl8192cu_fops},
10176{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
10177 .driver_info = (unsigned long)&rtl8192cu_fops},
10178{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
10179 .driver_info = (unsigned long)&rtl8192cu_fops},
10180#endif
10181{ }
10182};
10183
10184static struct usb_driver rtl8xxxu_driver = {
10185 .name = DRIVER_NAME,
10186 .probe = rtl8xxxu_probe,
10187 .disconnect = rtl8xxxu_disconnect,
10188 .id_table = dev_table,
6a62f9d5 10189 .no_dynamic_id = 1,
26f1fad2
JS		 10190 .disable_hub_initiated_lpm = 1,
10191};
10192
10193static int __init rtl8xxxu_module_init(void)
10194{
10195 int res;
10196
10197 res = usb_register(&rtl8xxxu_driver);
10198 if (res < 0)
10199 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
10200
10201 return res;
10202}
10203
10204static void __exit rtl8xxxu_module_exit(void)
10205{
10206 usb_deregister(&rtl8xxxu_driver);
10207}
10208
10209
10210MODULE_DEVICE_TABLE(usb, dev_table);
10211
10212module_init(rtl8xxxu_module_init);
10213module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
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