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rtl8xxxu: Only setup USB interrupts for parts which support it
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
CommitLineData
26f1fad2
JS		 1/*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
3307d840 45static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
b001e086 57MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
35a741fe
JS		 58MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
26f1fad2
JS		 60
61module_param_named(debug, rtl8xxxu_debug, int, 0600);
62MODULE_PARM_DESC(debug, "Set debug mask");
63module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66#define USB_VENDOR_ID_REALTEK 0x0bda
67/* Minimum IEEE80211_MAX_FRAME_LEN */
68#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69#define RTL8XXXU_RX_URBS 32
70#define RTL8XXXU_RX_URB_PENDING_WATER 8
71#define RTL8XXXU_TX_URBS 64
72#define RTL8XXXU_TX_URB_LOW_WATER 25
73#define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91};
92
93static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122};
123
124static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129};
130
131static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154};
155
156static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
157 {0x800, 0x80040000}, {0x804, 0x00000003},
158 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
159 {0x810, 0x10001331}, {0x814, 0x020c3d10},
160 {0x818, 0x02200385}, {0x81c, 0x00000000},
161 {0x820, 0x01000100}, {0x824, 0x00390004},
162 {0x828, 0x00000000}, {0x82c, 0x00000000},
163 {0x830, 0x00000000}, {0x834, 0x00000000},
164 {0x838, 0x00000000}, {0x83c, 0x00000000},
165 {0x840, 0x00010000}, {0x844, 0x00000000},
166 {0x848, 0x00000000}, {0x84c, 0x00000000},
167 {0x850, 0x00000000}, {0x854, 0x00000000},
168 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
169 {0x860, 0x66f60110}, {0x864, 0x061f0130},
170 {0x868, 0x00000000}, {0x86c, 0x32323200},
171 {0x870, 0x07000760}, {0x874, 0x22004000},
172 {0x878, 0x00000808}, {0x87c, 0x00000000},
173 {0x880, 0xc0083070}, {0x884, 0x000004d5},
174 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
175 {0x890, 0x00000800}, {0x894, 0xfffffffe},
176 {0x898, 0x40302010}, {0x89c, 0x00706050},
177 {0x900, 0x00000000}, {0x904, 0x00000023},
178 {0x908, 0x00000000}, {0x90c, 0x81121111},
179 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
180 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
181 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
182 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
183 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
184 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
185 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
186 {0xa78, 0x00000900},
187 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
188 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
189 {0xc10, 0x08800000}, {0xc14, 0x40000100},
190 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
191 {0xc20, 0x00000000}, {0xc24, 0x00000000},
192 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
193 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
194 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
195 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
196 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
197 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
198 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
199 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
200 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
201 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
202 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
203 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
204 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
205 {0xc90, 0x00121820}, {0xc94, 0x00000000},
206 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
207 {0xca0, 0x00000000}, {0xca4, 0x00000080},
208 {0xca8, 0x00000000}, {0xcac, 0x00000000},
209 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
210 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
211 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
212 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
213 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
214 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
215 {0xce0, 0x00222222}, {0xce4, 0x00000000},
216 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
217 {0xd00, 0x00080740}, {0xd04, 0x00020401},
218 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
219 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
220 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
221 {0xd30, 0x00000000}, {0xd34, 0x80608000},
222 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
223 {0xd40, 0x00000000}, {0xd44, 0x00000000},
224 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
225 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
226 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
227 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
228 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
229 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
230 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
231 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
232 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
233 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
234 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
235 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
236 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
237 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
238 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
239 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
240 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
241 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
242 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
243 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
244 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
245 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
246 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
247 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
248 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
249 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
250 {0xf00, 0x00000300},
251 {0xffff, 0xffffffff},
252};
253
254static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
255 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
256 {0x800, 0x80040002}, {0x804, 0x00000003},
257 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
258 {0x810, 0x10000330}, {0x814, 0x020c3d10},
259 {0x818, 0x02200385}, {0x81c, 0x00000000},
260 {0x820, 0x01000100}, {0x824, 0x00390004},
261 {0x828, 0x01000100}, {0x82c, 0x00390004},
262 {0x830, 0x27272727}, {0x834, 0x27272727},
263 {0x838, 0x27272727}, {0x83c, 0x27272727},
264 {0x840, 0x00010000}, {0x844, 0x00010000},
265 {0x848, 0x27272727}, {0x84c, 0x27272727},
266 {0x850, 0x00000000}, {0x854, 0x00000000},
267 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
268 {0x860, 0x66e60230}, {0x864, 0x061f0130},
269 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
270 {0x870, 0x07000700}, {0x874, 0x22184000},
271 {0x878, 0x08080808}, {0x87c, 0x00000000},
272 {0x880, 0xc0083070}, {0x884, 0x000004d5},
273 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
274 {0x890, 0x00000800}, {0x894, 0xfffffffe},
275 {0x898, 0x40302010}, {0x89c, 0x00706050},
276 {0x900, 0x00000000}, {0x904, 0x00000023},
277 {0x908, 0x00000000}, {0x90c, 0x81121313},
278 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
279 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
280 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
281 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
282 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
283 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
284 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
285 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
286 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
287 {0xc10, 0x08800000}, {0xc14, 0x40000100},
288 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
289 {0xc20, 0x00000000}, {0xc24, 0x00000000},
290 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
291 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
292 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
293 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
294 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
295 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
296 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
297 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
298 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
299 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
300 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
301 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
302 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
303 {0xc90, 0x00121820}, {0xc94, 0x00000000},
304 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
305 {0xca0, 0x00000000}, {0xca4, 0x00000080},
306 {0xca8, 0x00000000}, {0xcac, 0x00000000},
307 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
308 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
309 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
310 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
311 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
312 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
313 {0xce0, 0x00222222}, {0xce4, 0x00000000},
314 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
315 {0xd00, 0x00080740}, {0xd04, 0x00020403},
316 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
317 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
318 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
319 {0xd30, 0x00000000}, {0xd34, 0x80608000},
320 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
321 {0xd40, 0x00000000}, {0xd44, 0x00000000},
322 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
323 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
324 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
325 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
326 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
327 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
328 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
329 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
330 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
331 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
332 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
333 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
334 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
335 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
336 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
337 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
338 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
339 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
340 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
341 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
342 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
343 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
344 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
345 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
346 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
347 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
348 {0xf00, 0x00000300},
349 {0xffff, 0xffffffff},
350};
351
352static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
353 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
354 {0x040, 0x000c0004}, {0x800, 0x80040000},
355 {0x804, 0x00000001}, {0x808, 0x0000fc00},
356 {0x80c, 0x0000000a}, {0x810, 0x10005388},
357 {0x814, 0x020c3d10}, {0x818, 0x02200385},
358 {0x81c, 0x00000000}, {0x820, 0x01000100},
359 {0x824, 0x00390204}, {0x828, 0x00000000},
360 {0x82c, 0x00000000}, {0x830, 0x00000000},
361 {0x834, 0x00000000}, {0x838, 0x00000000},
362 {0x83c, 0x00000000}, {0x840, 0x00010000},
363 {0x844, 0x00000000}, {0x848, 0x00000000},
364 {0x84c, 0x00000000}, {0x850, 0x00000000},
365 {0x854, 0x00000000}, {0x858, 0x569a569a},
366 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
367 {0x864, 0x061f0130}, {0x868, 0x00000000},
368 {0x86c, 0x20202000}, {0x870, 0x03000300},
369 {0x874, 0x22004000}, {0x878, 0x00000808},
370 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
371 {0x884, 0x000004d5}, {0x888, 0x00000000},
372 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
373 {0x894, 0xfffffffe}, {0x898, 0x40302010},
374 {0x89c, 0x00706050}, {0x900, 0x00000000},
375 {0x904, 0x00000023}, {0x908, 0x00000000},
376 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
377 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
378 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
379 {0xa14, 0x11144028}, {0xa18, 0x00881117},
380 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
381 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
382 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
383 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
384 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
385 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
386 {0xc14, 0x40000100}, {0xc18, 0x08800000},
387 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
388 {0xc24, 0x00000000}, {0xc28, 0x00000000},
389 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
390 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
391 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
392 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
393 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
394 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
395 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
396 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
397 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
398 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
399 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
400 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
401 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
402 {0xc94, 0x00000000}, {0xc98, 0x00121820},
403 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
404 {0xca4, 0x00000080}, {0xca8, 0x00000000},
405 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
406 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
407 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
408 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
409 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
410 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
411 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
412 {0xce4, 0x00000000}, {0xce8, 0x37644302},
413 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
414 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
415 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
416 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
417 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
418 {0xd34, 0x80608000}, {0xd38, 0x00000000},
419 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
420 {0xd44, 0x00000000}, {0xd48, 0x00000000},
421 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
422 {0xd54, 0x00000000}, {0xd58, 0x00000000},
423 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
424 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
425 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
426 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
427 {0xe00, 0x24242424}, {0xe04, 0x24242424},
428 {0xe08, 0x03902024}, {0xe10, 0x24242424},
429 {0xe14, 0x24242424}, {0xe18, 0x24242424},
430 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
431 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
432 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
433 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
434 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
435 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
436 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
437 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
438 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
439 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
440 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
441 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
442 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
443 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
444 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
445 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
446 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
447 {0xf00, 0x00000300},
448 {0xffff, 0xffffffff},
449};
450
451static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
452 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
453 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
454 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
455 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
456 {0xc78, 0x78080001}, {0xc78, 0x77090001},
457 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
458 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
459 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
460 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
461 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
462 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
463 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
464 {0xc78, 0x68180001}, {0xc78, 0x67190001},
465 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
466 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
467 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
468 {0xc78, 0x60200001}, {0xc78, 0x49210001},
469 {0xc78, 0x48220001}, {0xc78, 0x47230001},
470 {0xc78, 0x46240001}, {0xc78, 0x45250001},
471 {0xc78, 0x44260001}, {0xc78, 0x43270001},
472 {0xc78, 0x42280001}, {0xc78, 0x41290001},
473 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
474 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
475 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
476 {0xc78, 0x21300001}, {0xc78, 0x20310001},
477 {0xc78, 0x06320001}, {0xc78, 0x05330001},
478 {0xc78, 0x04340001}, {0xc78, 0x03350001},
479 {0xc78, 0x02360001}, {0xc78, 0x01370001},
480 {0xc78, 0x00380001}, {0xc78, 0x00390001},
481 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
482 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
483 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
484 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
485 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
486 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
487 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
488 {0xc78, 0x78480001}, {0xc78, 0x77490001},
489 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
490 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
491 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
492 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
493 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
494 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
495 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
496 {0xc78, 0x68580001}, {0xc78, 0x67590001},
497 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
498 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
499 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
500 {0xc78, 0x60600001}, {0xc78, 0x49610001},
501 {0xc78, 0x48620001}, {0xc78, 0x47630001},
502 {0xc78, 0x46640001}, {0xc78, 0x45650001},
503 {0xc78, 0x44660001}, {0xc78, 0x43670001},
504 {0xc78, 0x42680001}, {0xc78, 0x41690001},
505 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
506 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
507 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
508 {0xc78, 0x21700001}, {0xc78, 0x20710001},
509 {0xc78, 0x06720001}, {0xc78, 0x05730001},
510 {0xc78, 0x04740001}, {0xc78, 0x03750001},
511 {0xc78, 0x02760001}, {0xc78, 0x01770001},
512 {0xc78, 0x00780001}, {0xc78, 0x00790001},
513 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
514 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
515 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
516 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
517 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
518 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
519 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
520 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
521 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
522 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
523 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
524 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
525 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
526 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
527 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
528 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
529 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
530 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
531 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
532 {0xffff, 0xffffffff}
533};
534
535static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
536 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
537 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
538 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
539 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
540 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
541 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
542 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
543 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
544 {0xc78, 0x73100001}, {0xc78, 0x72110001},
545 {0xc78, 0x71120001}, {0xc78, 0x70130001},
546 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
547 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
548 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
549 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
550 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
551 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
552 {0xc78, 0x63200001}, {0xc78, 0x62210001},
553 {0xc78, 0x61220001}, {0xc78, 0x60230001},
554 {0xc78, 0x46240001}, {0xc78, 0x45250001},
555 {0xc78, 0x44260001}, {0xc78, 0x43270001},
556 {0xc78, 0x42280001}, {0xc78, 0x41290001},
557 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
558 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
559 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
560 {0xc78, 0x21300001}, {0xc78, 0x20310001},
561 {0xc78, 0x06320001}, {0xc78, 0x05330001},
562 {0xc78, 0x04340001}, {0xc78, 0x03350001},
563 {0xc78, 0x02360001}, {0xc78, 0x01370001},
564 {0xc78, 0x00380001}, {0xc78, 0x00390001},
565 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
566 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
567 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
568 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
569 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
570 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
571 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
572 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
573 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
574 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
575 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
576 {0xc78, 0x73500001}, {0xc78, 0x72510001},
577 {0xc78, 0x71520001}, {0xc78, 0x70530001},
578 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
579 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
580 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
581 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
582 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
583 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
584 {0xc78, 0x63600001}, {0xc78, 0x62610001},
585 {0xc78, 0x61620001}, {0xc78, 0x60630001},
586 {0xc78, 0x46640001}, {0xc78, 0x45650001},
587 {0xc78, 0x44660001}, {0xc78, 0x43670001},
588 {0xc78, 0x42680001}, {0xc78, 0x41690001},
589 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
590 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
591 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
592 {0xc78, 0x21700001}, {0xc78, 0x20710001},
593 {0xc78, 0x06720001}, {0xc78, 0x05730001},
594 {0xc78, 0x04740001}, {0xc78, 0x03750001},
595 {0xc78, 0x02760001}, {0xc78, 0x01770001},
596 {0xc78, 0x00780001}, {0xc78, 0x00790001},
597 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
598 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
599 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
600 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
601 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
602 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
603 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
604 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
605 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
606 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
607 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
608 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
609 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
610 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
611 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
612 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
613 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
614 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
615 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
616 {0xffff, 0xffffffff}
617};
618
619static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
620 {0x00, 0x00030159}, {0x01, 0x00031284},
621 {0x02, 0x00098000}, {0x03, 0x00039c63},
622 {0x04, 0x000210e7}, {0x09, 0x0002044f},
623 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
624 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
625 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
626 {0x19, 0x00000000}, {0x1a, 0x00030355},
627 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
628 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
629 {0x1f, 0x00000000}, {0x20, 0x0000b614},
630 {0x21, 0x0006c000}, {0x22, 0x00000000},
631 {0x23, 0x00001558}, {0x24, 0x00000060},
632 {0x25, 0x00000483}, {0x26, 0x0004f000},
633 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
634 {0x29, 0x00004783}, {0x2a, 0x00000001},
635 {0x2b, 0x00021334}, {0x2a, 0x00000000},
636 {0x2b, 0x00000054}, {0x2a, 0x00000001},
637 {0x2b, 0x00000808}, {0x2b, 0x00053333},
638 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
639 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
640 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
641 {0x2b, 0x00000808}, {0x2b, 0x00063333},
642 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
643 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
644 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
645 {0x2b, 0x00000808}, {0x2b, 0x00073333},
646 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
647 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
648 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
649 {0x2b, 0x00000709}, {0x2b, 0x00063333},
650 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
651 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
652 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
653 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
654 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
655 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
656 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
657 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
658 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
659 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
660 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
661 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
662 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
663 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
664 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
665 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
666 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
667 {0x10, 0x0002000f}, {0x11, 0x000203f9},
668 {0x10, 0x0003000f}, {0x11, 0x000ff500},
669 {0x10, 0x00000000}, {0x11, 0x00000000},
670 {0x10, 0x0008000f}, {0x11, 0x0003f100},
671 {0x10, 0x0009000f}, {0x11, 0x00023100},
672 {0x12, 0x00032000}, {0x12, 0x00071000},
673 {0x12, 0x000b0000}, {0x12, 0x000fc000},
674 {0x13, 0x000287b3}, {0x13, 0x000244b7},
675 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
676 {0x13, 0x00018493}, {0x13, 0x0001429b},
677 {0x13, 0x00010299}, {0x13, 0x0000c29c},
678 {0x13, 0x000081a0}, {0x13, 0x000040ac},
679 {0x13, 0x00000020}, {0x14, 0x0001944c},
680 {0x14, 0x00059444}, {0x14, 0x0009944c},
681 {0x14, 0x000d9444}, {0x15, 0x0000f474},
682 {0x15, 0x0004f477}, {0x15, 0x0008f455},
683 {0x15, 0x000cf455}, {0x16, 0x00000339},
684 {0x16, 0x00040339}, {0x16, 0x00080339},
685 {0x16, 0x000c0366}, {0x00, 0x00010159},
686 {0x18, 0x0000f401}, {0xfe, 0x00000000},
687 {0xfe, 0x00000000}, {0x1f, 0x00000003},
688 {0xfe, 0x00000000}, {0xfe, 0x00000000},
689 {0x1e, 0x00000247}, {0x1f, 0x00000000},
690 {0x00, 0x00030159},
691 {0xff, 0xffffffff}
692};
693
694static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
695 {0x00, 0x00030159}, {0x01, 0x00031284},
696 {0x02, 0x00098000}, {0x03, 0x00018c63},
697 {0x04, 0x000210e7}, {0x09, 0x0002044f},
698 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
699 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
700 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
701 {0x19, 0x00000000}, {0x1a, 0x00010255},
702 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
703 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
704 {0x1f, 0x00080001}, {0x20, 0x0000b614},
705 {0x21, 0x0006c000}, {0x22, 0x00000000},
706 {0x23, 0x00001558}, {0x24, 0x00000060},
707 {0x25, 0x00000483}, {0x26, 0x0004f000},
708 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
709 {0x29, 0x00004783}, {0x2a, 0x00000001},
710 {0x2b, 0x00021334}, {0x2a, 0x00000000},
711 {0x2b, 0x00000054}, {0x2a, 0x00000001},
712 {0x2b, 0x00000808}, {0x2b, 0x00053333},
713 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
714 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
715 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
716 {0x2b, 0x00000808}, {0x2b, 0x00063333},
717 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
718 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
719 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
720 {0x2b, 0x00000808}, {0x2b, 0x00073333},
721 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
722 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
723 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
724 {0x2b, 0x00000709}, {0x2b, 0x00063333},
725 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
726 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
727 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
728 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
729 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
730 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
731 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
732 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
733 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
734 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
735 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
736 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
737 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
738 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
739 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
740 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
741 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
742 {0x10, 0x0002000f}, {0x11, 0x000203f9},
743 {0x10, 0x0003000f}, {0x11, 0x000ff500},
744 {0x10, 0x00000000}, {0x11, 0x00000000},
745 {0x10, 0x0008000f}, {0x11, 0x0003f100},
746 {0x10, 0x0009000f}, {0x11, 0x00023100},
747 {0x12, 0x00032000}, {0x12, 0x00071000},
748 {0x12, 0x000b0000}, {0x12, 0x000fc000},
749 {0x13, 0x000287b3}, {0x13, 0x000244b7},
750 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
751 {0x13, 0x00018493}, {0x13, 0x0001429b},
752 {0x13, 0x00010299}, {0x13, 0x0000c29c},
753 {0x13, 0x000081a0}, {0x13, 0x000040ac},
754 {0x13, 0x00000020}, {0x14, 0x0001944c},
755 {0x14, 0x00059444}, {0x14, 0x0009944c},
756 {0x14, 0x000d9444}, {0x15, 0x0000f424},
757 {0x15, 0x0004f424}, {0x15, 0x0008f424},
758 {0x15, 0x000cf424}, {0x16, 0x000e0330},
759 {0x16, 0x000a0330}, {0x16, 0x00060330},
760 {0x16, 0x00020330}, {0x00, 0x00010159},
761 {0x18, 0x0000f401}, {0xfe, 0x00000000},
762 {0xfe, 0x00000000}, {0x1f, 0x00080003},
763 {0xfe, 0x00000000}, {0xfe, 0x00000000},
764 {0x1e, 0x00044457}, {0x1f, 0x00080000},
765 {0x00, 0x00030159},
766 {0xff, 0xffffffff}
767};
768
769static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
770 {0x00, 0x00030159}, {0x01, 0x00031284},
771 {0x02, 0x00098000}, {0x03, 0x00018c63},
772 {0x04, 0x000210e7}, {0x09, 0x0002044f},
773 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
774 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
775 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
776 {0x12, 0x00032000}, {0x12, 0x00071000},
777 {0x12, 0x000b0000}, {0x12, 0x000fc000},
778 {0x13, 0x000287af}, {0x13, 0x000244b7},
779 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
780 {0x13, 0x00018493}, {0x13, 0x00014297},
781 {0x13, 0x00010295}, {0x13, 0x0000c298},
782 {0x13, 0x0000819c}, {0x13, 0x000040a8},
783 {0x13, 0x0000001c}, {0x14, 0x0001944c},
784 {0x14, 0x00059444}, {0x14, 0x0009944c},
785 {0x14, 0x000d9444}, {0x15, 0x0000f424},
786 {0x15, 0x0004f424}, {0x15, 0x0008f424},
787 {0x15, 0x000cf424}, {0x16, 0x000e0330},
788 {0x16, 0x000a0330}, {0x16, 0x00060330},
789 {0x16, 0x00020330},
790 {0xff, 0xffffffff}
791};
792
793static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
794 {0x00, 0x00030159}, {0x01, 0x00031284},
795 {0x02, 0x00098000}, {0x03, 0x00018c63},
796 {0x04, 0x000210e7}, {0x09, 0x0002044f},
797 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
798 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
799 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
800 {0x19, 0x00000000}, {0x1a, 0x00010255},
801 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
802 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
803 {0x1f, 0x00080001}, {0x20, 0x0000b614},
804 {0x21, 0x0006c000}, {0x22, 0x00000000},
805 {0x23, 0x00001558}, {0x24, 0x00000060},
806 {0x25, 0x00000483}, {0x26, 0x0004f000},
807 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
808 {0x29, 0x00004783}, {0x2a, 0x00000001},
809 {0x2b, 0x00021334}, {0x2a, 0x00000000},
810 {0x2b, 0x00000054}, {0x2a, 0x00000001},
811 {0x2b, 0x00000808}, {0x2b, 0x00053333},
812 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
813 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
814 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
815 {0x2b, 0x00000808}, {0x2b, 0x00063333},
816 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
817 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
818 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
819 {0x2b, 0x00000808}, {0x2b, 0x00073333},
820 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
821 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
822 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
823 {0x2b, 0x00000709}, {0x2b, 0x00063333},
824 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
825 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
826 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
827 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
828 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
829 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
830 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
831 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
832 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
833 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
834 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
835 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
836 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
837 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
838 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
839 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
840 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
841 {0x10, 0x0002000f}, {0x11, 0x000203f9},
842 {0x10, 0x0003000f}, {0x11, 0x000ff500},
843 {0x10, 0x00000000}, {0x11, 0x00000000},
844 {0x10, 0x0008000f}, {0x11, 0x0003f100},
845 {0x10, 0x0009000f}, {0x11, 0x00023100},
846 {0x12, 0x00032000}, {0x12, 0x00071000},
847 {0x12, 0x000b0000}, {0x12, 0x000fc000},
848 {0x13, 0x000287b3}, {0x13, 0x000244b7},
849 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
850 {0x13, 0x00018493}, {0x13, 0x0001429b},
851 {0x13, 0x00010299}, {0x13, 0x0000c29c},
852 {0x13, 0x000081a0}, {0x13, 0x000040ac},
853 {0x13, 0x00000020}, {0x14, 0x0001944c},
854 {0x14, 0x00059444}, {0x14, 0x0009944c},
855 {0x14, 0x000d9444}, {0x15, 0x0000f405},
856 {0x15, 0x0004f405}, {0x15, 0x0008f405},
857 {0x15, 0x000cf405}, {0x16, 0x000e0330},
858 {0x16, 0x000a0330}, {0x16, 0x00060330},
859 {0x16, 0x00020330}, {0x00, 0x00010159},
860 {0x18, 0x0000f401}, {0xfe, 0x00000000},
861 {0xfe, 0x00000000}, {0x1f, 0x00080003},
862 {0xfe, 0x00000000}, {0xfe, 0x00000000},
863 {0x1e, 0x00044457}, {0x1f, 0x00080000},
864 {0x00, 0x00030159},
865 {0xff, 0xffffffff}
866};
867
868static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
869 {0x00, 0x00030159}, {0x01, 0x00031284},
870 {0x02, 0x00098000}, {0x03, 0x00018c63},
871 {0x04, 0x000210e7}, {0x09, 0x0002044f},
872 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
873 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
874 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
875 {0x19, 0x00000000}, {0x1a, 0x00000255},
876 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
877 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
878 {0x1f, 0x00080001}, {0x20, 0x0000b614},
879 {0x21, 0x0006c000}, {0x22, 0x0000083c},
880 {0x23, 0x00001558}, {0x24, 0x00000060},
881 {0x25, 0x00000483}, {0x26, 0x0004f000},
882 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
883 {0x29, 0x00004783}, {0x2a, 0x00000001},
884 {0x2b, 0x00021334}, {0x2a, 0x00000000},
885 {0x2b, 0x00000054}, {0x2a, 0x00000001},
886 {0x2b, 0x00000808}, {0x2b, 0x00053333},
887 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
888 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
889 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
890 {0x2b, 0x00000808}, {0x2b, 0x00063333},
891 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
892 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
893 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
894 {0x2b, 0x00000808}, {0x2b, 0x00073333},
895 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
896 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
897 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
898 {0x2b, 0x00000709}, {0x2b, 0x00063333},
899 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
900 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
901 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
902 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
903 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
904 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
905 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
906 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
907 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
908 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
909 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
910 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
911 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
912 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
913 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
914 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
915 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
916 {0x10, 0x0002000f}, {0x11, 0x000203f9},
917 {0x10, 0x0003000f}, {0x11, 0x000ff500},
918 {0x10, 0x00000000}, {0x11, 0x00000000},
919 {0x10, 0x0008000f}, {0x11, 0x0003f100},
920 {0x10, 0x0009000f}, {0x11, 0x00023100},
921 {0x12, 0x000d8000}, {0x12, 0x00090000},
922 {0x12, 0x00051000}, {0x12, 0x00012000},
923 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
924 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
925 {0x13, 0x000183a4}, {0x13, 0x00014398},
926 {0x13, 0x000101a4}, {0x13, 0x0000c198},
927 {0x13, 0x000080a4}, {0x13, 0x00004098},
928 {0x13, 0x00000000}, {0x14, 0x0001944c},
929 {0x14, 0x00059444}, {0x14, 0x0009944c},
930 {0x14, 0x000d9444}, {0x15, 0x0000f405},
931 {0x15, 0x0004f405}, {0x15, 0x0008f405},
932 {0x15, 0x000cf405}, {0x16, 0x000e0330},
933 {0x16, 0x000a0330}, {0x16, 0x00060330},
934 {0x16, 0x00020330}, {0x00, 0x00010159},
935 {0x18, 0x0000f401}, {0xfe, 0x00000000},
936 {0xfe, 0x00000000}, {0x1f, 0x00080003},
937 {0xfe, 0x00000000}, {0xfe, 0x00000000},
938 {0x1e, 0x00044457}, {0x1f, 0x00080000},
939 {0x00, 0x00030159},
940 {0xff, 0xffffffff}
941};
942
943static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
944 { /* RF_A */
945 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
946 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
947 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
948 .hspiread = REG_HSPI_XA_READBACK,
949 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
950 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
951 },
952 { /* RF_B */
953 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
954 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
955 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
956 .hspiread = REG_HSPI_XB_READBACK,
957 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
958 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
959 },
960};
961
962static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
963 REG_OFDM0_XA_RX_IQ_IMBALANCE,
964 REG_OFDM0_XB_RX_IQ_IMBALANCE,
965 REG_OFDM0_ENERGY_CCA_THRES,
966 REG_OFDM0_AGCR_SSI_TABLE,
967 REG_OFDM0_XA_TX_IQ_IMBALANCE,
968 REG_OFDM0_XB_TX_IQ_IMBALANCE,
969 REG_OFDM0_XC_TX_AFE,
970 REG_OFDM0_XD_TX_AFE,
971 REG_OFDM0_RX_IQ_EXT_ANTA
972};
973
974static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
975{
976 struct usb_device *udev = priv->udev;
977 int len;
978 u8 data;
979
980 mutex_lock(&priv->usb_buf_mutex);
981 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
982 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
983 addr, 0, &priv->usb_buf.val8, sizeof(u8),
984 RTW_USB_CONTROL_MSG_TIMEOUT);
985 data = priv->usb_buf.val8;
986 mutex_unlock(&priv->usb_buf_mutex);
987
988 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
989 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
990 __func__, addr, data, len);
991 return data;
992}
993
994static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
995{
996 struct usb_device *udev = priv->udev;
997 int len;
998 u16 data;
999
1000 mutex_lock(&priv->usb_buf_mutex);
1001 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1002 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1003 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1004 RTW_USB_CONTROL_MSG_TIMEOUT);
1005 data = le16_to_cpu(priv->usb_buf.val16);
1006 mutex_unlock(&priv->usb_buf_mutex);
1007
1008 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1009 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1010 __func__, addr, data, len);
1011 return data;
1012}
1013
1014static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1015{
1016 struct usb_device *udev = priv->udev;
1017 int len;
1018 u32 data;
1019
1020 mutex_lock(&priv->usb_buf_mutex);
1021 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1022 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1023 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1024 RTW_USB_CONTROL_MSG_TIMEOUT);
1025 data = le32_to_cpu(priv->usb_buf.val32);
1026 mutex_unlock(&priv->usb_buf_mutex);
1027
1028 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1029 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1030 __func__, addr, data, len);
1031 return data;
1032}
1033
1034static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1035{
1036 struct usb_device *udev = priv->udev;
1037 int ret;
1038
1039 mutex_lock(&priv->usb_buf_mutex);
1040 priv->usb_buf.val8 = val;
1041 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1042 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1043 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1044 RTW_USB_CONTROL_MSG_TIMEOUT);
1045
1046 mutex_unlock(&priv->usb_buf_mutex);
1047
1048 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1049 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1050 __func__, addr, val);
1051 return ret;
1052}
1053
1054static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1055{
1056 struct usb_device *udev = priv->udev;
1057 int ret;
1058
1059 mutex_lock(&priv->usb_buf_mutex);
1060 priv->usb_buf.val16 = cpu_to_le16(val);
1061 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1062 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1063 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1064 RTW_USB_CONTROL_MSG_TIMEOUT);
1065 mutex_unlock(&priv->usb_buf_mutex);
1066
1067 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1068 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1069 __func__, addr, val);
1070 return ret;
1071}
1072
1073static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1074{
1075 struct usb_device *udev = priv->udev;
1076 int ret;
1077
1078 mutex_lock(&priv->usb_buf_mutex);
1079 priv->usb_buf.val32 = cpu_to_le32(val);
1080 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1081 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1082 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1083 RTW_USB_CONTROL_MSG_TIMEOUT);
1084 mutex_unlock(&priv->usb_buf_mutex);
1085
1086 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1087 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1088 __func__, addr, val);
1089 return ret;
1090}
1091
1092static int
1093rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1094{
1095 struct usb_device *udev = priv->udev;
1096 int blocksize = priv->fops->writeN_block_size;
1097 int ret, i, count, remainder;
1098
1099 count = len / blocksize;
1100 remainder = len % blocksize;
1101
1102 for (i = 0; i < count; i++) {
1103 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1104 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1105 addr, 0, buf, blocksize,
1106 RTW_USB_CONTROL_MSG_TIMEOUT);
1107 if (ret != blocksize)
1108 goto write_error;
1109
1110 addr += blocksize;
1111 buf += blocksize;
1112 }
1113
1114 if (remainder) {
1115 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1116 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1117 addr, 0, buf, remainder,
1118 RTW_USB_CONTROL_MSG_TIMEOUT);
1119 if (ret != remainder)
1120 goto write_error;
1121 }
1122
1123 return len;
1124
1125write_error:
1126 dev_info(&udev->dev,
1127 "%s: Failed to write block at addr: %04x size: %04x\n",
1128 __func__, addr, blocksize);
1129 return -EAGAIN;
1130}
1131
1132static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1133 enum rtl8xxxu_rfpath path, u8 reg)
1134{
1135 u32 hssia, val32, retval;
1136
1137 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1138 if (path != RF_A)
1139 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1140 else
1141 val32 = hssia;
1142
1143 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1144 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1145 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1146 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1147 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1148
1149 udelay(10);
1150
1151 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1152 udelay(100);
1153
1154 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1155 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1156 udelay(10);
1157
1158 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1159 if (val32 & FPGA0_HSSI_PARM1_PI)
1160 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1161 else
1162 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1163
1164 retval &= 0xfffff;
1165
1166 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1167 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1168 __func__, reg, retval);
1169 return retval;
1170}
1171
1172static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1173 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1174{
1175 int ret, retval;
1176 u32 dataaddr;
1177
1178 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1179 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1180 __func__, reg, data);
1181
1182 data &= FPGA0_LSSI_PARM_DATA_MASK;
1183 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1184
1185 /* Use XB for path B */
1186 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1187 if (ret != sizeof(dataaddr))
1188 retval = -EIO;
1189 else
1190 retval = 0;
1191
1192 udelay(1);
1193
1194 return retval;
1195}
1196
1197static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1198{
1199 struct device *dev = &priv->udev->dev;
1200 int mbox_nr, retry, retval = 0;
1201 int mbox_reg, mbox_ext_reg;
1202 u8 val8;
1203
1204 mutex_lock(&priv->h2c_mutex);
1205
1206 mbox_nr = priv->next_mbox;
1207 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1208 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1209
1210 /*
1211 * MBOX ready?
1212 */
1213 retry = 100;
1214 do {
1215 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1216 if (!(val8 & BIT(mbox_nr)))
1217 break;
1218 } while (retry--);
1219
1220 if (!retry) {
1221 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1222 retval = -EBUSY;
1223 goto error;
1224 }
1225
1226 /*
1227 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1228 */
1229 if (h2c->cmd.cmd & H2C_EXT) {
1230 rtl8xxxu_write16(priv, mbox_ext_reg,
1231 le16_to_cpu(h2c->raw.ext));
1232 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1233 dev_info(dev, "H2C_EXT %04x\n",
1234 le16_to_cpu(h2c->raw.ext));
1235 }
1236 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1237 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1238 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1239
1240 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1241
1242error:
1243 mutex_unlock(&priv->h2c_mutex);
1244 return retval;
1245}
1246
1247static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1248{
1249 u8 val8;
1250 u32 val32;
1251
1252 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1253 val8 |= BIT(0) | BIT(3);
1254 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1255
1256 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1257 val32 &= ~(BIT(4) | BIT(5));
1258 val32 |= BIT(3);
1259 if (priv->rf_paths == 2) {
1260 val32 &= ~(BIT(20) | BIT(21));
1261 val32 |= BIT(19);
1262 }
1263 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1264
1265 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1266 val32 &= ~OFDM_RF_PATH_TX_MASK;
1267 if (priv->tx_paths == 2)
1268 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1269 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1270 val32 |= OFDM_RF_PATH_TX_B;
1271 else
1272 val32 |= OFDM_RF_PATH_TX_A;
1273 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1274
1275 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1276 val32 &= ~FPGA_RF_MODE_JAPAN;
1277 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1278
1279 if (priv->rf_paths == 2)
1280 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1281 else
1282 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1283
1284 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1285 if (priv->rf_paths == 2)
1286 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1287
1288 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1289}
1290
1291static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1292{
1293 u8 sps0;
1294 u32 val32;
1295
1296 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1297
1298 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1299
1300 /* RF RX code for preamble power saving */
1301 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1302 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1303 if (priv->rf_paths == 2)
1304 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1305 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1306
1307 /* Disable TX for four paths */
1308 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1309 val32 &= ~OFDM_RF_PATH_TX_MASK;
1310 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1311
1312 /* Enable power saving */
1313 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1314 val32 |= FPGA_RF_MODE_JAPAN;
1315 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1316
1317 /* AFE control register to power down bits [30:22] */
1318 if (priv->rf_paths == 2)
1319 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1320 else
1321 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1322
1323 /* Power down RF module */
1324 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1325 if (priv->rf_paths == 2)
1326 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1327
1328 sps0 &= ~(BIT(0) | BIT(3));
1329 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1330}
1331
1332
1333static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1334{
1335 u8 val8;
1336
1337 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1338 val8 &= ~BIT(6);
1339 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1340
1341 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1342 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1343 val8 &= ~BIT(0);
1344 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1345}
1346
1347
1348/*
1349 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1350 * supports the 2.4GHz band, so channels 1 - 14:
1351 * group 0: channels 1 - 3
1352 * group 1: channels 4 - 9
1353 * group 2: channels 10 - 14
1354 *
1355 * Note: We index from 0 in the code
1356 */
1357static int rtl8723a_channel_to_group(int channel)
1358{
1359 int group;
1360
1361 if (channel < 4)
1362 group = 0;
1363 else if (channel < 10)
1364 group = 1;
1365 else
1366 group = 2;
1367
1368 return group;
1369}
1370
1371static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1372{
1373 struct rtl8xxxu_priv *priv = hw->priv;
1374 u32 val32, rsr;
1375 u8 val8, opmode;
1376 bool ht = true;
1377 int sec_ch_above, channel;
1378 int i;
1379
1380 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1381 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1382 channel = hw->conf.chandef.chan->hw_value;
1383
1384 switch (hw->conf.chandef.width) {
1385 case NL80211_CHAN_WIDTH_20_NOHT:
1386 ht = false;
1387 case NL80211_CHAN_WIDTH_20:
1388 opmode |= BW_OPMODE_20MHZ;
1389 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1390
1391 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1392 val32 &= ~FPGA_RF_MODE;
1393 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1394
1395 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1396 val32 &= ~FPGA_RF_MODE;
1397 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1398
1399 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1400 val32 |= FPGA0_ANALOG2_20MHZ;
1401 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1402 break;
1403 case NL80211_CHAN_WIDTH_40:
1404 if (hw->conf.chandef.center_freq1 >
1405 hw->conf.chandef.chan->center_freq) {
1406 sec_ch_above = 1;
1407 channel += 2;
1408 } else {
1409 sec_ch_above = 0;
1410 channel -= 2;
1411 }
1412
1413 opmode &= ~BW_OPMODE_20MHZ;
1414 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1415 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1416 if (sec_ch_above)
1417 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1418 else
1419 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1420 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1421
1422 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1423 val32 |= FPGA_RF_MODE;
1424 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1425
1426 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1427 val32 |= FPGA_RF_MODE;
1428 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1429
1430 /*
1431 * Set Control channel to upper or lower. These settings
1432 * are required only for 40MHz
1433 */
1434 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1435 val32 &= ~CCK0_SIDEBAND;
1436 if (!sec_ch_above)
1437 val32 |= CCK0_SIDEBAND;
1438 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1439
1440 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1441 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1442 if (sec_ch_above)
1443 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1444 else
1445 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1446 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1447
1448 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1449 val32 &= ~FPGA0_ANALOG2_20MHZ;
1450 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1451
1452 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1453 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1454 if (sec_ch_above)
1455 val32 |= FPGA0_PS_UPPER_CHANNEL;
1456 else
1457 val32 |= FPGA0_PS_LOWER_CHANNEL;
1458 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1459 break;
1460
1461 default:
1462 break;
1463 }
1464
1465 for (i = RF_A; i < priv->rf_paths; i++) {
1466 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1467 val32 &= ~MODE_AG_CHANNEL_MASK;
1468 val32 |= channel;
1469 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1470 }
1471
1472 if (ht)
1473 val8 = 0x0e;
1474 else
1475 val8 = 0x0a;
1476
1477 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1478 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1479
1480 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1481 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1482
1483 for (i = RF_A; i < priv->rf_paths; i++) {
1484 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1485 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1486 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1487 else
1488 val32 |= MODE_AG_CHANNEL_20MHZ;
1489 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1490 }
1491}
1492
1493static void
1494rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1495{
1496 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1497 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1498 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1499 u8 val8;
1500 int group, i;
1501
1502 group = rtl8723a_channel_to_group(channel);
1503
1504 cck[0] = priv->cck_tx_power_index_A[group];
1505 cck[1] = priv->cck_tx_power_index_B[group];
1506
1507 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1508 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1509
1510 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1511 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1512
1513 mcsbase[0] = ofdm[0];
1514 mcsbase[1] = ofdm[1];
1515 if (!ht40) {
1516 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1517 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1518 }
1519
1520 if (priv->tx_paths > 1) {
1521 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1522 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1523 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1524 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1525 }
1526
1527 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1528 dev_info(&priv->udev->dev,
1529 "%s: Setting TX power CCK A: %02x, "
1530 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1531 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1532
1533 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1534 if (cck[i] > RF6052_MAX_TX_PWR)
1535 cck[i] = RF6052_MAX_TX_PWR;
1536 if (ofdm[i] > RF6052_MAX_TX_PWR)
1537 ofdm[i] = RF6052_MAX_TX_PWR;
1538 }
1539
1540 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1541 val32 &= 0xffff00ff;
1542 val32 |= (cck[0] << 8);
1543 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1544
1545 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1546 val32 &= 0xff;
1547 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1548 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1549
1550 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1551 val32 &= 0xffffff00;
1552 val32 |= cck[1];
1553 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1554
1555 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1556 val32 &= 0xff;
1557 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1558 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1559
1560 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1561 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1562 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1563 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1564 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1565 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1566
1567 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1568 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1569
1570 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1571 mcsbase[0] << 16 | mcsbase[0] << 24;
1572 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1573 mcsbase[1] << 16 | mcsbase[1] << 24;
1574
1575 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1576 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1577
1578 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1579 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1580
1581 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1582 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1583
1584 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1585 for (i = 0; i < 3; i++) {
1586 if (i != 2)
1587 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1588 else
1589 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1590 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1591 }
1592 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1593 for (i = 0; i < 3; i++) {
1594 if (i != 2)
1595 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1596 else
1597 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1598 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1599 }
1600}
1601
1602static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1603 enum nl80211_iftype linktype)
1604{
a26703f3 1605 u8 val8;
26f1fad2 1606
a26703f3 1607 val8 = rtl8xxxu_read8(priv, REG_MSR);
26f1fad2
JS		 1608 val8 &= ~MSR_LINKTYPE_MASK;
1609
1610 switch (linktype) {
1611 case NL80211_IFTYPE_UNSPECIFIED:
1612 val8 |= MSR_LINKTYPE_NONE;
1613 break;
1614 case NL80211_IFTYPE_ADHOC:
1615 val8 |= MSR_LINKTYPE_ADHOC;
1616 break;
1617 case NL80211_IFTYPE_STATION:
1618 val8 |= MSR_LINKTYPE_STATION;
1619 break;
1620 case NL80211_IFTYPE_AP:
1621 val8 |= MSR_LINKTYPE_AP;
1622 break;
1623 default:
1624 goto out;
1625 }
1626
1627 rtl8xxxu_write8(priv, REG_MSR, val8);
1628out:
1629 return;
1630}
1631
1632static void
1633rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1634{
1635 u16 val16;
1636
1637 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1638 RETRY_LIMIT_SHORT_MASK) |
1639 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1640 RETRY_LIMIT_LONG_MASK);
1641
1642 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1643}
1644
1645static void
1646rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1647{
1648 u16 val16;
1649
1650 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1651 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1652
1653 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1654}
1655
1656static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1657{
1658 struct device *dev = &priv->udev->dev;
1659 char *cut;
1660
1661 switch (priv->chip_cut) {
1662 case 0:
1663 cut = "A";
1664 break;
1665 case 1:
1666 cut = "B";
1667 break;
0e5d435a
JS		 1668 case 2:
1669 cut = "C";
1670 break;
1671 case 3:
1672 cut = "D";
1673 break;
1674 case 4:
1675 cut = "E";
1676 break;
26f1fad2
JS		 1677 default:
1678 cut = "unknown";
1679 }
1680
1681 dev_info(dev,
1682 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
0e5d435a
JS		 1683 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1684 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1685 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
26f1fad2
JS		 1686
1687 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1688}
1689
1690static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1691{
1692 struct device *dev = &priv->udev->dev;
1693 u32 val32, bonding;
1694 u16 val16;
1695
1696 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1697 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1698 SYS_CFG_CHIP_VERSION_SHIFT;
1699 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1700 dev_info(dev, "Unsupported test chip\n");
1701 return -ENOTSUPP;
1702 }
1703
1704 if (val32 & SYS_CFG_BT_FUNC) {
35a741fe
JS		 1705 if (priv->chip_cut >= 3) {
1706 sprintf(priv->chip_name, "8723BU");
1707 priv->rtlchip = 0x8723b;
1708 } else {
1709 sprintf(priv->chip_name, "8723AU");
0e28b975 1710 priv->usb_interrupts = 1;
35a741fe
JS		 1711 priv->rtlchip = 0x8723a;
1712 }
1713
26f1fad2
JS		 1714 priv->rf_paths = 1;
1715 priv->rx_paths = 1;
1716 priv->tx_paths = 1;
26f1fad2
JS		 1717
1718 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1719 if (val32 & MULTI_WIFI_FUNC_EN)
1720 priv->has_wifi = 1;
1721 if (val32 & MULTI_BT_FUNC_EN)
1722 priv->has_bluetooth = 1;
1723 if (val32 & MULTI_GPS_FUNC_EN)
1724 priv->has_gps = 1;
38451998 1725 priv->is_multi_func = 1;
26f1fad2
JS		 1726 } else if (val32 & SYS_CFG_TYPE_ID) {
1727 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1728 bonding &= HPON_FSM_BONDING_MASK;
0e5d435a
JS		 1729 if (priv->chip_cut >= 3) {
1730 if (bonding == HPON_FSM_BONDING_1T2R) {
1731 sprintf(priv->chip_name, "8191EU");
1732 priv->rf_paths = 2;
1733 priv->rx_paths = 2;
1734 priv->tx_paths = 1;
1735 priv->rtlchip = 0x8191e;
1736 } else {
1737 sprintf(priv->chip_name, "8192EU");
1738 priv->rf_paths = 2;
1739 priv->rx_paths = 2;
1740 priv->tx_paths = 2;
1741 priv->rtlchip = 0x8192e;
1742 }
1743 } else if (bonding == HPON_FSM_BONDING_1T2R) {
26f1fad2
JS		 1744 sprintf(priv->chip_name, "8191CU");
1745 priv->rf_paths = 2;
1746 priv->rx_paths = 2;
1747 priv->tx_paths = 1;
0e28b975 1748 priv->usb_interrupts = 1;
26f1fad2
JS		 1749 priv->rtlchip = 0x8191c;
1750 } else {
1751 sprintf(priv->chip_name, "8192CU");
1752 priv->rf_paths = 2;
1753 priv->rx_paths = 2;
1754 priv->tx_paths = 2;
0e28b975 1755 priv->usb_interrupts = 1;
26f1fad2
JS		 1756 priv->rtlchip = 0x8192c;
1757 }
1758 priv->has_wifi = 1;
1759 } else {
1760 sprintf(priv->chip_name, "8188CU");
1761 priv->rf_paths = 1;
1762 priv->rx_paths = 1;
1763 priv->tx_paths = 1;
1764 priv->rtlchip = 0x8188c;
0e28b975 1765 priv->usb_interrupts = 1;
26f1fad2
JS		 1766 priv->has_wifi = 1;
1767 }
1768
0e5d435a
JS		 1769 switch (priv->rtlchip) {
1770 case 0x8188e:
1771 case 0x8192e:
1772 case 0x8723b:
1773 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1774 case SYS_CFG_VENDOR_ID_TSMC:
1775 sprintf(priv->chip_vendor, "TSMC");
1776 break;
1777 case SYS_CFG_VENDOR_ID_SMIC:
1778 sprintf(priv->chip_vendor, "SMIC");
1779 priv->vendor_smic = 1;
1780 break;
1781 case SYS_CFG_VENDOR_ID_UMC:
1782 sprintf(priv->chip_vendor, "UMC");
1783 priv->vendor_umc = 1;
1784 break;
1785 default:
1786 sprintf(priv->chip_vendor, "unknown");
1787 }
1788 break;
1789 default:
1790 if (val32 & SYS_CFG_VENDOR_ID) {
1791 sprintf(priv->chip_vendor, "UMC");
1792 priv->vendor_umc = 1;
1793 } else {
1794 sprintf(priv->chip_vendor, "TSMC");
1795 }
1796 }
26f1fad2
JS		 1797
1798 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1799 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1800
1801 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1802 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1803 priv->ep_tx_high_queue = 1;
1804 priv->ep_tx_count++;
1805 }
1806
1807 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1808 priv->ep_tx_normal_queue = 1;
1809 priv->ep_tx_count++;
1810 }
1811
1812 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1813 priv->ep_tx_low_queue = 1;
1814 priv->ep_tx_count++;
1815 }
1816
1817 /*
1818 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1819 */
1820 if (!priv->ep_tx_count) {
1821 switch (priv->nr_out_eps) {
35a741fe 1822 case 4:
26f1fad2
JS		 1823 case 3:
1824 priv->ep_tx_low_queue = 1;
1825 priv->ep_tx_count++;
1826 case 2:
1827 priv->ep_tx_normal_queue = 1;
1828 priv->ep_tx_count++;
1829 case 1:
1830 priv->ep_tx_high_queue = 1;
1831 priv->ep_tx_count++;
1832 break;
1833 default:
1834 dev_info(dev, "Unsupported USB TX end-points\n");
1835 return -ENOTSUPP;
1836 }
1837 }
1838
1839 return 0;
1840}
1841
1842static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1843{
1844 if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1845 return -EINVAL;
1846
1847 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1848
1849 memcpy(priv->cck_tx_power_index_A,
1850 priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1851 sizeof(priv->cck_tx_power_index_A));
1852 memcpy(priv->cck_tx_power_index_B,
1853 priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1854 sizeof(priv->cck_tx_power_index_B));
1855
1856 memcpy(priv->ht40_1s_tx_power_index_A,
1857 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1858 sizeof(priv->ht40_1s_tx_power_index_A));
1859 memcpy(priv->ht40_1s_tx_power_index_B,
1860 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1861 sizeof(priv->ht40_1s_tx_power_index_B));
1862
1863 memcpy(priv->ht20_tx_power_index_diff,
1864 priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1865 sizeof(priv->ht20_tx_power_index_diff));
1866 memcpy(priv->ofdm_tx_power_index_diff,
1867 priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1868 sizeof(priv->ofdm_tx_power_index_diff));
1869
1870 memcpy(priv->ht40_max_power_offset,
1871 priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1872 sizeof(priv->ht40_max_power_offset));
1873 memcpy(priv->ht20_max_power_offset,
1874 priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1875 sizeof(priv->ht20_max_power_offset));
1876
1877 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1878 priv->efuse_wifi.efuse8723.vendor_name);
1879 dev_info(&priv->udev->dev, "Product: %.41s\n",
1880 priv->efuse_wifi.efuse8723.device_name);
1881 return 0;
1882}
1883
3c836d60
JS		 1884static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
1885{
1886 if (priv->efuse_wifi.efuse8723bu.rtl_id != cpu_to_le16(0x8129))
1887 return -EINVAL;
1888
1889 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723bu.mac_addr);
1890
1891 memcpy(priv->cck_tx_power_index_A,
1892 priv->efuse_wifi.efuse8723bu.cck_tx_power_index_A,
1893 sizeof(priv->cck_tx_power_index_A));
1894 memcpy(priv->cck_tx_power_index_B,
1895 priv->efuse_wifi.efuse8723bu.cck_tx_power_index_B,
1896 sizeof(priv->cck_tx_power_index_B));
1897
1898 memcpy(priv->ht40_1s_tx_power_index_A,
1899 priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_A,
1900 sizeof(priv->ht40_1s_tx_power_index_A));
1901 memcpy(priv->ht40_1s_tx_power_index_B,
1902 priv->efuse_wifi.efuse8723bu.ht40_1s_tx_power_index_B,
1903 sizeof(priv->ht40_1s_tx_power_index_B));
1904
1905 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1906 priv->efuse_wifi.efuse8723bu.vendor_name);
1907 dev_info(&priv->udev->dev, "Product: %.41s\n",
1908 priv->efuse_wifi.efuse8723bu.device_name);
1909
1910 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1911 int i;
1912 unsigned char *raw = priv->efuse_wifi.raw;
1913
1914 dev_info(&priv->udev->dev,
1915 "%s: dumping efuse (0x%02zx bytes):\n",
1916 __func__, sizeof(struct rtl8723bu_efuse));
1917 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
1918 dev_info(&priv->udev->dev, "%02x: "
1919 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1920 raw[i], raw[i + 1], raw[i + 2],
1921 raw[i + 3], raw[i + 4], raw[i + 5],
1922 raw[i + 6], raw[i + 7]);
1923 }
1924 }
1925
1926 return 0;
1927}
1928
c0963772
KV		 1929#ifdef CONFIG_RTL8XXXU_UNTESTED
1930
26f1fad2
JS		 1931static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1932{
1933 int i;
1934
1935 if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1936 return -EINVAL;
1937
1938 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1939
1940 memcpy(priv->cck_tx_power_index_A,
1941 priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1942 sizeof(priv->cck_tx_power_index_A));
1943 memcpy(priv->cck_tx_power_index_B,
1944 priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1945 sizeof(priv->cck_tx_power_index_B));
1946
1947 memcpy(priv->ht40_1s_tx_power_index_A,
1948 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1949 sizeof(priv->ht40_1s_tx_power_index_A));
1950 memcpy(priv->ht40_1s_tx_power_index_B,
1951 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1952 sizeof(priv->ht40_1s_tx_power_index_B));
1953 memcpy(priv->ht40_2s_tx_power_index_diff,
1954 priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1955 sizeof(priv->ht40_2s_tx_power_index_diff));
1956
1957 memcpy(priv->ht20_tx_power_index_diff,
1958 priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1959 sizeof(priv->ht20_tx_power_index_diff));
1960 memcpy(priv->ofdm_tx_power_index_diff,
1961 priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1962 sizeof(priv->ofdm_tx_power_index_diff));
1963
1964 memcpy(priv->ht40_max_power_offset,
1965 priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1966 sizeof(priv->ht40_max_power_offset));
1967 memcpy(priv->ht20_max_power_offset,
1968 priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1969 sizeof(priv->ht20_max_power_offset));
1970
1971 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1972 priv->efuse_wifi.efuse8192.vendor_name);
1973 dev_info(&priv->udev->dev, "Product: %.20s\n",
1974 priv->efuse_wifi.efuse8192.device_name);
1975
1976 if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1977 sprintf(priv->chip_name, "8188RU");
1978 priv->hi_pa = 1;
1979 }
1980
1981 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1982 unsigned char *raw = priv->efuse_wifi.raw;
1983
1984 dev_info(&priv->udev->dev,
1985 "%s: dumping efuse (0x%02zx bytes):\n",
1986 __func__, sizeof(struct rtl8192cu_efuse));
1987 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1988 dev_info(&priv->udev->dev, "%02x: "
1989 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1990 raw[i], raw[i + 1], raw[i + 2],
1991 raw[i + 3], raw[i + 4], raw[i + 5],
1992 raw[i + 6], raw[i + 7]);
1993 }
1994 }
1995 return 0;
1996}
1997
c0963772
KV		 1998#endif
1999
3307d840
JS		 2000static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2001{
2002 int i;
2003
2004 if (priv->efuse_wifi.efuse8192eu.rtl_id != cpu_to_le16(0x8129))
2005 return -EINVAL;
2006
2007 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192eu.mac_addr);
2008
2009 memcpy(priv->cck_tx_power_index_A,
2010 priv->efuse_wifi.efuse8192eu.cck_tx_power_index_A,
2011 sizeof(priv->cck_tx_power_index_A));
2012 memcpy(priv->cck_tx_power_index_B,
2013 priv->efuse_wifi.efuse8192eu.cck_tx_power_index_B,
2014 sizeof(priv->cck_tx_power_index_B));
2015
2016 memcpy(priv->ht40_1s_tx_power_index_A,
2017 priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_A,
2018 sizeof(priv->ht40_1s_tx_power_index_A));
2019 memcpy(priv->ht40_1s_tx_power_index_B,
2020 priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_B,
2021 sizeof(priv->ht40_1s_tx_power_index_B));
2022
2023 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
2024 priv->efuse_wifi.efuse8192eu.vendor_name);
2025 dev_info(&priv->udev->dev, "Product: %.11s\n",
2026 priv->efuse_wifi.efuse8192eu.device_name);
2027 dev_info(&priv->udev->dev, "Serial: %.11s\n",
2028 priv->efuse_wifi.efuse8192eu.serial);
2029
2030 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2031 unsigned char *raw = priv->efuse_wifi.raw;
2032
2033 dev_info(&priv->udev->dev,
2034 "%s: dumping efuse (0x%02zx bytes):\n",
2035 __func__, sizeof(struct rtl8192eu_efuse));
2036 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2037 dev_info(&priv->udev->dev, "%02x: "
2038 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2039 raw[i], raw[i + 1], raw[i + 2],
2040 raw[i + 3], raw[i + 4], raw[i + 5],
2041 raw[i + 6], raw[i + 7]);
2042 }
2043 }
0e5d435a 2044 return 0;
3307d840
JS		 2045}
2046
26f1fad2
JS		 2047static int
2048rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2049{
2050 int i;
2051 u8 val8;
2052 u32 val32;
2053
2054 /* Write Address */
2055 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2056 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2057 val8 &= 0xfc;
2058 val8 |= (offset >> 8) & 0x03;
2059 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2060
2061 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2062 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2063
2064 /* Poll for data read */
2065 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2066 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2067 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2068 if (val32 & BIT(31))
2069 break;
2070 }
2071
2072 if (i == RTL8XXXU_MAX_REG_POLL)
2073 return -EIO;
2074
2075 udelay(50);
2076 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2077
2078 *data = val32 & 0xff;
2079 return 0;
2080}
2081
2082static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2083{
2084 struct device *dev = &priv->udev->dev;
2085 int i, ret = 0;
2086 u8 val8, word_mask, header, extheader;
2087 u16 val16, efuse_addr, offset;
2088 u32 val32;
2089
2090 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2091 if (val16 & EEPROM_ENABLE)
2092 priv->has_eeprom = 1;
2093 if (val16 & EEPROM_BOOT)
2094 priv->boot_eeprom = 1;
2095
38451998
JS		 2096 if (priv->is_multi_func) {
2097 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2098 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2099 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2100 }
26f1fad2
JS		 2101
2102 dev_dbg(dev, "Booting from %s\n",
2103 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2104
2105 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2106
2107 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2108 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2109 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2110 val16 |= SYS_ISO_PWC_EV12V;
2111 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2112 }
2113 /* Reset: 0x0000[28], default valid */
2114 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2115 if (!(val16 & SYS_FUNC_ELDR)) {
2116 val16 |= SYS_FUNC_ELDR;
2117 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2118 }
2119
2120 /*
2121 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2122 */
2123 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2124 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2125 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2126 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2127 }
2128
2129 /* Default value is 0xff */
3307d840 2130 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
26f1fad2
JS		 2131
2132 efuse_addr = 0;
2133 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2134 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2135 if (ret || header == 0xff)
2136 goto exit;
2137
2138 if ((header & 0x1f) == 0x0f) { /* extended header */
2139 offset = (header & 0xe0) >> 5;
2140
2141 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2142 &extheader);
2143 if (ret)
2144 goto exit;
2145 /* All words disabled */
2146 if ((extheader & 0x0f) == 0x0f)
2147 continue;
2148
2149 offset |= ((extheader & 0xf0) >> 1);
2150 word_mask = extheader & 0x0f;
2151 } else {
2152 offset = (header >> 4) & 0x0f;
2153 word_mask = header & 0x0f;
2154 }
2155
2156 if (offset < EFUSE_MAX_SECTION_8723A) {
2157 u16 map_addr;
2158 /* Get word enable value from PG header */
2159
2160 /* We have 8 bits to indicate validity */
2161 map_addr = offset * 8;
3307d840 2162 if (map_addr >= EFUSE_MAP_LEN) {
26f1fad2
JS		 2163 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2164 "efuse corrupt!\n",
2165 __func__, map_addr);
2166 ret = -EINVAL;
2167 goto exit;
2168 }
2169 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2170 /* Check word enable condition in the section */
2171 if (!(word_mask & BIT(i))) {
2172 ret = rtl8xxxu_read_efuse8(priv,
2173 efuse_addr++,
2174 &val8);
2175 if (ret)
2176 goto exit;
2177 priv->efuse_wifi.raw[map_addr++] = val8;
2178
2179 ret = rtl8xxxu_read_efuse8(priv,
2180 efuse_addr++,
2181 &val8);
2182 if (ret)
2183 goto exit;
2184 priv->efuse_wifi.raw[map_addr++] = val8;
2185 } else
2186 map_addr += 2;
2187 }
2188 } else {
2189 dev_warn(dev,
2190 "%s: Illegal offset (%04x), efuse corrupt!\n",
2191 __func__, offset);
2192 ret = -EINVAL;
2193 goto exit;
2194 }
2195 }
2196
2197exit:
2198 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2199
2200 return ret;
2201}
2202
d48fe60e
JS		 2203static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2204{
2205 u8 val8;
2206 u16 sys_func;
2207
2208 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 2209 val8 &= ~BIT(0);
d48fe60e
JS		 2210 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2211 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2212 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2213 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2214 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 2215 val8 |= BIT(0);
d48fe60e
JS		 2216 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2217 sys_func |= SYS_FUNC_CPU_ENABLE;
2218 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2219}
2220
26f1fad2
JS		 2221static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2222{
2223 struct device *dev = &priv->udev->dev;
2224 int ret = 0, i;
2225 u32 val32;
2226
2227 /* Poll checksum report */
2228 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2229 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2230 if (val32 & MCU_FW_DL_CSUM_REPORT)
2231 break;
2232 }
2233
2234 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2235 dev_warn(dev, "Firmware checksum poll timed out\n");
2236 ret = -EAGAIN;
2237 goto exit;
2238 }
2239
2240 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2241 val32 |= MCU_FW_DL_READY;
2242 val32 &= ~MCU_WINT_INIT_READY;
2243 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2244
d48fe60e
JS		 2245 /*
2246 * Reset the 8051 in order for the firmware to start running,
2247 * otherwise it won't come up on the 8192eu
2248 */
2249 rtl8xxxu_reset_8051(priv);
2250
26f1fad2
JS		 2251 /* Wait for firmware to become ready */
2252 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2253 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2254 if (val32 & MCU_WINT_INIT_READY)
2255 break;
2256
2257 udelay(100);
2258 }
2259
2260 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2261 dev_warn(dev, "Firmware failed to start\n");
2262 ret = -EAGAIN;
2263 goto exit;
2264 }
2265
2266exit:
2267 return ret;
2268}
2269
2270static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2271{
2272 int pages, remainder, i, ret;
d48fe60e 2273 u8 val8;
26f1fad2
JS		 2274 u16 val16;
2275 u32 val32;
2276 u8 *fwptr;
2277
2278 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2279 val8 |= 4;
2280 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2281
2282 /* 8051 enable */
2283 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
43154f6f
JS		 2284 val16 |= SYS_FUNC_CPU_ENABLE;
2285 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 2286
216202ae
JS		 2287 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2288 if (val8 & MCU_FW_RAM_SEL) {
2289 pr_info("do the RAM reset\n");
2290 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
d48fe60e 2291 rtl8xxxu_reset_8051(priv);
216202ae
JS		 2292 }
2293
26f1fad2
JS		 2294 /* MCU firmware download enable */
2295 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2296 val8 |= MCU_FW_DL_ENABLE;
2297 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 2298
2299 /* 8051 reset */
2300 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2301 val32 &= ~BIT(19);
2302 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
26f1fad2
JS		 2303
2304 /* Reset firmware download checksum */
2305 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2306 val8 |= MCU_FW_DL_CSUM_REPORT;
2307 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 2308
2309 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2310 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2311
2312 fwptr = priv->fw_data->data;
2313
2314 for (i = 0; i < pages; i++) {
2315 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 2316 val8 |= i;
2317 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 2318
2319 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2320 fwptr, RTL_FW_PAGE_SIZE);
2321 if (ret != RTL_FW_PAGE_SIZE) {
2322 ret = -EAGAIN;
2323 goto fw_abort;
2324 }
2325
2326 fwptr += RTL_FW_PAGE_SIZE;
2327 }
2328
2329 if (remainder) {
2330 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 2331 val8 |= i;
2332 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 2333 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2334 fwptr, remainder);
2335 if (ret != remainder) {
2336 ret = -EAGAIN;
2337 goto fw_abort;
2338 }
2339 }
2340
2341 ret = 0;
2342fw_abort:
2343 /* MCU firmware download disable */
2344 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2345 val16 &= ~MCU_FW_DL_ENABLE;
2346 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
26f1fad2
JS		 2347
2348 return ret;
2349}
2350
2351static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2352{
2353 struct device *dev = &priv->udev->dev;
2354 const struct firmware *fw;
2355 int ret = 0;
2356 u16 signature;
2357
2358 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2359 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2360 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2361 ret = -EAGAIN;
2362 goto exit;
2363 }
2364 if (!fw) {
2365 dev_warn(dev, "Firmware data not available\n");
2366 ret = -EINVAL;
2367 goto exit;
2368 }
2369
2370 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
98e27cbd
TK		 2371 if (!priv->fw_data) {
2372 ret = -ENOMEM;
2373 goto exit;
2374 }
26f1fad2
JS		 2375 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2376
2377 signature = le16_to_cpu(priv->fw_data->signature);
2378 switch (signature & 0xfff0) {
0e5d435a 2379 case 0x92e0:
26f1fad2
JS		 2380 case 0x92c0:
2381 case 0x88c0:
35a741fe 2382 case 0x5300:
26f1fad2
JS		 2383 case 0x2300:
2384 break;
2385 default:
2386 ret = -EINVAL;
2387 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2388 __func__, signature);
2389 }
2390
2391 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2392 le16_to_cpu(priv->fw_data->major_version),
2393 priv->fw_data->minor_version, signature);
2394
2395exit:
2396 release_firmware(fw);
2397 return ret;
2398}
2399
2400static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2401{
2402 char *fw_name;
2403 int ret;
2404
2405 switch (priv->chip_cut) {
2406 case 0:
2407 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2408 break;
2409 case 1:
2410 if (priv->enable_bluetooth)
2411 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2412 else
2413 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2414
2415 break;
2416 default:
2417 return -EINVAL;
2418 }
2419
2420 ret = rtl8xxxu_load_firmware(priv, fw_name);
2421 return ret;
2422}
2423
35a741fe
JS		 2424static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2425{
2426 char *fw_name;
2427 int ret;
2428
2429 if (priv->enable_bluetooth)
2430 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2431 else
2432 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2433
2434 ret = rtl8xxxu_load_firmware(priv, fw_name);
2435 return ret;
2436}
2437
c0963772
KV		 2438#ifdef CONFIG_RTL8XXXU_UNTESTED
2439
26f1fad2
JS		 2440static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2441{
2442 char *fw_name;
2443 int ret;
2444
2445 if (!priv->vendor_umc)
2446 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2447 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2448 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2449 else
2450 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2451
2452 ret = rtl8xxxu_load_firmware(priv, fw_name);
2453
2454 return ret;
2455}
2456
c0963772
KV		 2457#endif
2458
3307d840
JS		 2459static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2460{
2461 char *fw_name;
2462 int ret;
2463
0e5d435a 2464 fw_name = "rtlwifi/rtl8192eu_nic.bin";
3307d840
JS		 2465
2466 ret = rtl8xxxu_load_firmware(priv, fw_name);
2467
2468 return ret;
2469}
2470
26f1fad2
JS		 2471static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2472{
2473 u16 val16;
2474 int i = 100;
2475
2476 /* Inform 8051 to perform reset */
2477 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2478
2479 for (i = 100; i > 0; i--) {
2480 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2481
2482 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2483 dev_dbg(&priv->udev->dev,
2484 "%s: Firmware self reset success!\n", __func__);
2485 break;
2486 }
2487 udelay(50);
2488 }
2489
2490 if (!i) {
2491 /* Force firmware reset */
2492 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2493 val16 &= ~SYS_FUNC_CPU_ENABLE;
2494 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2495 }
2496}
2497
2498static int
2499rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2500{
2501 int i, ret;
2502 u16 reg;
2503 u8 val;
2504
2505 for (i = 0; ; i++) {
2506 reg = array[i].reg;
2507 val = array[i].val;
2508
2509 if (reg == 0xffff && val == 0xff)
2510 break;
2511
2512 ret = rtl8xxxu_write8(priv, reg, val);
2513 if (ret != 1) {
2514 dev_warn(&priv->udev->dev,
2515 "Failed to initialize MAC\n");
2516 return -EAGAIN;
2517 }
2518 }
2519
2520 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2521
2522 return 0;
2523}
2524
2525static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2526 struct rtl8xxxu_reg32val *array)
2527{
2528 int i, ret;
2529 u16 reg;
2530 u32 val;
2531
2532 for (i = 0; ; i++) {
2533 reg = array[i].reg;
2534 val = array[i].val;
2535
2536 if (reg == 0xffff && val == 0xffffffff)
2537 break;
2538
2539 ret = rtl8xxxu_write32(priv, reg, val);
2540 if (ret != sizeof(val)) {
2541 dev_warn(&priv->udev->dev,
2542 "Failed to initialize PHY\n");
2543 return -EAGAIN;
2544 }
2545 udelay(1);
2546 }
2547
2548 return 0;
2549}
2550
2551/*
2552 * Most of this is black magic retrieved from the old rtl8723au driver
2553 */
2554static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2555{
2556 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2557 u32 val32;
2558
2559 /*
2560 * Todo: The vendor driver maintains a table of PHY register
2561 * addresses, which is initialized here. Do we need this?
2562 */
2563
2564 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2565 udelay(2);
2566 val8 |= AFE_PLL_320_ENABLE;
2567 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2568 udelay(2);
2569
2570 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2571 udelay(2);
2572
2573 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2574 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2575 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2576
2577 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2578 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2579 val32 &= ~AFE_XTAL_RF_GATE;
2580 if (priv->has_bluetooth)
2581 val32 &= ~AFE_XTAL_BT_GATE;
2582 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2583
2584 /* 6. 0x1f[7:0] = 0x07 */
2585 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2586 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2587
2588 if (priv->hi_pa)
2589 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2590 else if (priv->tx_paths == 2)
2591 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2592 else
2593 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2594
2595
2596 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2597 priv->vendor_umc && priv->chip_cut == 1)
2598 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2599
2600 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2601 /*
2602 * For 1T2R boards, patch the registers.
2603 *
2604 * It looks like 8191/2 1T2R boards use path B for TX
2605 */
2606 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2607 val32 &= ~(BIT(0) | BIT(1));
2608 val32 |= BIT(1);
2609 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2610
2611 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2612 val32 &= ~0x300033;
2613 val32 |= 0x200022;
2614 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2615
2616 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2617 val32 &= 0xff000000;
2618 val32 |= 0x45000000;
2619 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2620
2621 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2622 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2623 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2624 OFDM_RF_PATH_TX_B);
2625 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2626
2627 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2628 val32 &= ~(BIT(4) | BIT(5));
2629 val32 |= BIT(4);
2630 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2631
2632 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2633 val32 &= ~(BIT(27) | BIT(26));
2634 val32 |= BIT(27);
2635 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2636
2637 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2638 val32 &= ~(BIT(27) | BIT(26));
2639 val32 |= BIT(27);
2640 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2641
2642 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2643 val32 &= ~(BIT(27) | BIT(26));
2644 val32 |= BIT(27);
2645 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2646
2647 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2648 val32 &= ~(BIT(27) | BIT(26));
2649 val32 |= BIT(27);
2650 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2651
2652 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2653 val32 &= ~(BIT(27) | BIT(26));
2654 val32 |= BIT(27);
2655 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2656 }
2657
2658 if (priv->hi_pa)
2659 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2660 else
2661 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2662
35a741fe 2663 if ((priv->rtlchip == 0x8723a || priv->rtlchip == 0x8723b) &&
26f1fad2
JS		 2664 priv->efuse_wifi.efuse8723.version >= 0x01) {
2665 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2666
2667 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2668 val32 &= 0xff000fff;
2669 val32 |= ((val8 | (val8 << 6)) << 12);
2670
2671 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2672 }
2673
2674 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2675 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2676 ldohci12 = 0x57;
2677 lpldo = 1;
2678 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2679
2680 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2681
2682 return 0;
2683}
2684
2685static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2686 struct rtl8xxxu_rfregval *array,
2687 enum rtl8xxxu_rfpath path)
2688{
2689 int i, ret;
2690 u8 reg;
2691 u32 val;
2692
2693 for (i = 0; ; i++) {
2694 reg = array[i].reg;
2695 val = array[i].val;
2696
2697 if (reg == 0xff && val == 0xffffffff)
2698 break;
2699
2700 switch (reg) {
2701 case 0xfe:
2702 msleep(50);
2703 continue;
2704 case 0xfd:
2705 mdelay(5);
2706 continue;
2707 case 0xfc:
2708 mdelay(1);
2709 continue;
2710 case 0xfb:
2711 udelay(50);
2712 continue;
2713 case 0xfa:
2714 udelay(5);
2715 continue;
2716 case 0xf9:
2717 udelay(1);
2718 continue;
2719 }
2720
26f1fad2
JS		 2721 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2722 if (ret) {
2723 dev_warn(&priv->udev->dev,
2724 "Failed to initialize RF\n");
2725 return -EAGAIN;
2726 }
2727 udelay(1);
2728 }
2729
2730 return 0;
2731}
2732
2733static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2734 struct rtl8xxxu_rfregval *table,
2735 enum rtl8xxxu_rfpath path)
2736{
2737 u32 val32;
2738 u16 val16, rfsi_rfenv;
2739 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2740
2741 switch (path) {
2742 case RF_A:
2743 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2744 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2745 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2746 break;
2747 case RF_B:
2748 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2749 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2750 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2751 break;
2752 default:
2753 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2754 __func__, path + 'A');
2755 return -EINVAL;
2756 }
2757 /* For path B, use XB */
2758 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2759 rfsi_rfenv &= FPGA0_RF_RFENV;
2760
2761 /*
2762 * These two we might be able to optimize into one
2763 */
2764 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2765 val32 |= BIT(20); /* 0x10 << 16 */
2766 rtl8xxxu_write32(priv, reg_int_oe, val32);
2767 udelay(1);
2768
2769 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2770 val32 |= BIT(4);
2771 rtl8xxxu_write32(priv, reg_int_oe, val32);
2772 udelay(1);
2773
2774 /*
2775 * These two we might be able to optimize into one
2776 */
2777 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2778 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2779 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2780 udelay(1);
2781
2782 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2783 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2784 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2785 udelay(1);
2786
2787 rtl8xxxu_init_rf_regs(priv, table, path);
2788
2789 /* For path B, use XB */
2790 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2791 val16 &= ~FPGA0_RF_RFENV;
2792 val16 |= rfsi_rfenv;
2793 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2794
2795 return 0;
2796}
2797
2798static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2799{
2800 int ret = -EBUSY;
2801 int count = 0;
2802 u32 value;
2803
2804 value = LLT_OP_WRITE | address << 8 | data;
2805
2806 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2807
2808 do {
2809 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2810 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2811 ret = 0;
2812 break;
2813 }
2814 } while (count++ < 20);
2815
2816 return ret;
2817}
2818
2819static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2820{
2821 int ret;
2822 int i;
2823
2824 for (i = 0; i < last_tx_page; i++) {
2825 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2826 if (ret)
2827 goto exit;
2828 }
2829
2830 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2831 if (ret)
2832 goto exit;
2833
2834 /* Mark remaining pages as a ring buffer */
2835 for (i = last_tx_page + 1; i < 0xff; i++) {
2836 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2837 if (ret)
2838 goto exit;
2839 }
2840
2841 /* Let last entry point to the start entry of ring buffer */
2842 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2843 if (ret)
2844 goto exit;
2845
2846exit:
2847 return ret;
2848}
2849
74b99bed
JS		 2850static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2851{
2852 u32 val32;
2853 int ret = 0;
2854 int i;
2855
2856 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
74b99bed
JS		 2857 val32 |= AUTO_LLT_INIT_LLT;
2858 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2859
2860 for (i = 500; i; i--) {
2861 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2862 if (!(val32 & AUTO_LLT_INIT_LLT))
2863 break;
2864 usleep_range(2, 4);
2865 }
2866
4de24819 2867 if (!i) {
74b99bed
JS		 2868 ret = -EBUSY;
2869 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2870 }
74b99bed
JS		 2871
2872 return ret;
2873}
2874
26f1fad2
JS		 2875static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2876{
2877 u16 val16, hi, lo;
2878 u16 hiq, mgq, bkq, beq, viq, voq;
2879 int hip, mgp, bkp, bep, vip, vop;
2880 int ret = 0;
2881
2882 switch (priv->ep_tx_count) {
2883 case 1:
2884 if (priv->ep_tx_high_queue) {
2885 hi = TRXDMA_QUEUE_HIGH;
2886 } else if (priv->ep_tx_low_queue) {
2887 hi = TRXDMA_QUEUE_LOW;
2888 } else if (priv->ep_tx_normal_queue) {
2889 hi = TRXDMA_QUEUE_NORMAL;
2890 } else {
2891 hi = 0;
2892 ret = -EINVAL;
2893 }
2894
2895 hiq = hi;
2896 mgq = hi;
2897 bkq = hi;
2898 beq = hi;
2899 viq = hi;
2900 voq = hi;
2901
2902 hip = 0;
2903 mgp = 0;
2904 bkp = 0;
2905 bep = 0;
2906 vip = 0;
2907 vop = 0;
2908 break;
2909 case 2:
2910 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2911 hi = TRXDMA_QUEUE_HIGH;
2912 lo = TRXDMA_QUEUE_LOW;
2913 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2914 hi = TRXDMA_QUEUE_NORMAL;
2915 lo = TRXDMA_QUEUE_LOW;
2916 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2917 hi = TRXDMA_QUEUE_HIGH;
2918 lo = TRXDMA_QUEUE_NORMAL;
2919 } else {
2920 ret = -EINVAL;
2921 hi = 0;
2922 lo = 0;
2923 }
2924
2925 hiq = hi;
2926 mgq = hi;
2927 bkq = lo;
2928 beq = lo;
2929 viq = hi;
2930 voq = hi;
2931
2932 hip = 0;
2933 mgp = 0;
2934 bkp = 1;
2935 bep = 1;
2936 vip = 0;
2937 vop = 0;
2938 break;
2939 case 3:
2940 beq = TRXDMA_QUEUE_LOW;
2941 bkq = TRXDMA_QUEUE_LOW;
2942 viq = TRXDMA_QUEUE_NORMAL;
2943 voq = TRXDMA_QUEUE_HIGH;
2944 mgq = TRXDMA_QUEUE_HIGH;
2945 hiq = TRXDMA_QUEUE_HIGH;
2946
2947 hip = hiq ^ 3;
2948 mgp = mgq ^ 3;
2949 bkp = bkq ^ 3;
2950 bep = beq ^ 3;
2951 vip = viq ^ 3;
2952 vop = viq ^ 3;
2953 break;
2954 default:
2955 ret = -EINVAL;
2956 }
2957
2958 /*
2959 * None of the vendor drivers are configuring the beacon
2960 * queue here .... why?
2961 */
2962 if (!ret) {
2963 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2964 val16 &= 0x7;
2965 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2966 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2967 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2968 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2969 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2970 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2971 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2972
2973 priv->pipe_out[TXDESC_QUEUE_VO] =
2974 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2975 priv->pipe_out[TXDESC_QUEUE_VI] =
2976 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2977 priv->pipe_out[TXDESC_QUEUE_BE] =
2978 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2979 priv->pipe_out[TXDESC_QUEUE_BK] =
2980 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2981 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2982 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2983 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2984 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2985 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2986 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2987 priv->pipe_out[TXDESC_QUEUE_CMD] =
2988 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2989 }
2990
2991 return ret;
2992}
2993
2994static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2995 bool iqk_ok, int result[][8],
2996 int candidate, bool tx_only)
2997{
2998 u32 oldval, x, tx0_a, reg;
2999 int y, tx0_c;
3000 u32 val32;
3001
3002 if (!iqk_ok)
3003 return;
3004
3005 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3006 oldval = val32 >> 22;
3007
3008 x = result[candidate][0];
3009 if ((x & 0x00000200) != 0)
3010 x = x | 0xfffffc00;
3011 tx0_a = (x * oldval) >> 8;
3012
3013 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3014 val32 &= ~0x3ff;
3015 val32 |= tx0_a;
3016 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3017
3018 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3019 val32 &= ~BIT(31);
3020 if ((x * oldval >> 7) & 0x1)
3021 val32 |= BIT(31);
3022 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3023
3024 y = result[candidate][1];
3025 if ((y & 0x00000200) != 0)
3026 y = y | 0xfffffc00;
3027 tx0_c = (y * oldval) >> 8;
3028
3029 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3030 val32 &= ~0xf0000000;
3031 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3032 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3033
3034 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3035 val32 &= ~0x003f0000;
3036 val32 |= ((tx0_c & 0x3f) << 16);
3037 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3038
3039 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3040 val32 &= ~BIT(29);
3041 if ((y * oldval >> 7) & 0x1)
3042 val32 |= BIT(29);
3043 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3044
3045 if (tx_only) {
3046 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3047 return;
3048 }
3049
3050 reg = result[candidate][2];
3051
3052 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3053 val32 &= ~0x3ff;
3054 val32 |= (reg & 0x3ff);
3055 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3056
3057 reg = result[candidate][3] & 0x3F;
3058
3059 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3060 val32 &= ~0xfc00;
3061 val32 |= ((reg << 10) & 0xfc00);
3062 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3063
3064 reg = (result[candidate][3] >> 6) & 0xF;
3065
3066 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3067 val32 &= ~0xf0000000;
3068 val32 |= (reg << 28);
3069 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3070}
3071
3072static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3073 bool iqk_ok, int result[][8],
3074 int candidate, bool tx_only)
3075{
3076 u32 oldval, x, tx1_a, reg;
3077 int y, tx1_c;
3078 u32 val32;
3079
3080 if (!iqk_ok)
3081 return;
3082
3083 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3084 oldval = val32 >> 22;
3085
3086 x = result[candidate][4];
3087 if ((x & 0x00000200) != 0)
3088 x = x | 0xfffffc00;
3089 tx1_a = (x * oldval) >> 8;
3090
3091 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3092 val32 &= ~0x3ff;
3093 val32 |= tx1_a;
3094 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3095
3096 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3097 val32 &= ~BIT(27);
3098 if ((x * oldval >> 7) & 0x1)
3099 val32 |= BIT(27);
3100 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3101
3102 y = result[candidate][5];
3103 if ((y & 0x00000200) != 0)
3104 y = y | 0xfffffc00;
3105 tx1_c = (y * oldval) >> 8;
3106
3107 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3108 val32 &= ~0xf0000000;
3109 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3110 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3111
3112 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3113 val32 &= ~0x003f0000;
3114 val32 |= ((tx1_c & 0x3f) << 16);
3115 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3116
3117 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3118 val32 &= ~BIT(25);
3119 if ((y * oldval >> 7) & 0x1)
3120 val32 |= BIT(25);
3121 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3122
3123 if (tx_only) {
3124 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3125 return;
3126 }
3127
3128 reg = result[candidate][6];
3129
3130 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3131 val32 &= ~0x3ff;
3132 val32 |= (reg & 0x3ff);
3133 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3134
3135 reg = result[candidate][7] & 0x3f;
3136
3137 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3138 val32 &= ~0xfc00;
3139 val32 |= ((reg << 10) & 0xfc00);
3140 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3141
3142 reg = (result[candidate][7] >> 6) & 0xf;
3143
3144 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3145 val32 &= ~0x0000f000;
3146 val32 |= (reg << 12);
3147 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3148}
3149
3150#define MAX_TOLERANCE 5
3151
3152static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3153 int result[][8], int c1, int c2)
3154{
3155 u32 i, j, diff, simubitmap, bound = 0;
3156 int candidate[2] = {-1, -1}; /* for path A and path B */
3157 bool retval = true;
3158
3159 if (priv->tx_paths > 1)
3160 bound = 8;
3161 else
3162 bound = 4;
3163
3164 simubitmap = 0;
3165
3166 for (i = 0; i < bound; i++) {
3167 diff = (result[c1][i] > result[c2][i]) ?
3168 (result[c1][i] - result[c2][i]) :
3169 (result[c2][i] - result[c1][i]);
3170 if (diff > MAX_TOLERANCE) {
3171 if ((i == 2 || i == 6) && !simubitmap) {
3172 if (result[c1][i] + result[c1][i + 1] == 0)
3173 candidate[(i / 4)] = c2;
3174 else if (result[c2][i] + result[c2][i + 1] == 0)
3175 candidate[(i / 4)] = c1;
3176 else
3177 simubitmap = simubitmap | (1 << i);
3178 } else {
3179 simubitmap = simubitmap | (1 << i);
3180 }
3181 }
3182 }
3183
3184 if (simubitmap == 0) {
3185 for (i = 0; i < (bound / 4); i++) {
3186 if (candidate[i] >= 0) {
3187 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3188 result[3][j] = result[candidate[i]][j];
3189 retval = false;
3190 }
3191 }
3192 return retval;
3193 } else if (!(simubitmap & 0x0f)) {
3194 /* path A OK */
3195 for (i = 0; i < 4; i++)
3196 result[3][i] = result[c1][i];
3197 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3198 /* path B OK */
3199 for (i = 4; i < 8; i++)
3200 result[3][i] = result[c1][i];
3201 }
3202
3203 return false;
3204}
3205
3206static void
3207rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3208{
3209 int i;
3210
3211 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3212 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3213
3214 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3215}
3216
3217static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3218 const u32 *reg, u32 *backup)
3219{
3220 int i;
3221
3222 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3223 rtl8xxxu_write8(priv, reg[i], backup[i]);
3224
3225 rtl8xxxu_write32(priv, reg[i], backup[i]);
3226}
3227
3228static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3229 u32 *backup, int count)
3230{
3231 int i;
3232
3233 for (i = 0; i < count; i++)
3234 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3235}
3236
3237static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3238 u32 *backup, int count)
3239{
3240 int i;
3241
3242 for (i = 0; i < count; i++)
3243 rtl8xxxu_write32(priv, regs[i], backup[i]);
3244}
3245
3246
3247static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3248 bool path_a_on)
3249{
3250 u32 path_on;
3251 int i;
3252
3253 path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3254 if (priv->tx_paths == 1) {
3255 path_on = 0x0bdb25a0;
3256 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3257 } else {
3258 rtl8xxxu_write32(priv, regs[0], path_on);
3259 }
3260
3261 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3262 rtl8xxxu_write32(priv, regs[i], path_on);
3263}
3264
3265static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3266 const u32 *regs, u32 *backup)
3267{
3268 int i = 0;
3269
3270 rtl8xxxu_write8(priv, regs[i], 0x3f);
3271
3272 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3273 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3274
3275 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3276}
3277
3278static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3279{
3280 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3281 int result = 0;
3282
3283 /* path-A IQK setting */
3284 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3285 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3286 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3287
3288 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3289 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3290 0x28160502;
3291 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3292
3293 /* path-B IQK setting */
3294 if (priv->rf_paths > 1) {
3295 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3296 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3297 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3298 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3299 }
3300
3301 /* LO calibration setting */
3302 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3303
3304 /* One shot, path A LOK & IQK */
3305 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3306 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3307
3308 mdelay(1);
3309
3310 /* Check failed */
3311 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3312 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3313 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3314 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3315
3316 if (!(reg_eac & BIT(28)) &&
3317 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3318 ((reg_e9c & 0x03ff0000) != 0x00420000))
3319 result |= 0x01;
3320 else /* If TX not OK, ignore RX */
3321 goto out;
3322
3323 /* If TX is OK, check whether RX is OK */
3324 if (!(reg_eac & BIT(27)) &&
3325 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3326 ((reg_eac & 0x03ff0000) != 0x00360000))
3327 result |= 0x02;
3328 else
3329 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3330 __func__);
3331out:
3332 return result;
3333}
3334
3335static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3336{
3337 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3338 int result = 0;
3339
3340 /* One shot, path B LOK & IQK */
3341 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3342 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3343
3344 mdelay(1);
3345
3346 /* Check failed */
3347 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3348 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3349 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3350 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3351 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3352
3353 if (!(reg_eac & BIT(31)) &&
3354 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3355 ((reg_ebc & 0x03ff0000) != 0x00420000))
3356 result |= 0x01;
3357 else
3358 goto out;
3359
3360 if (!(reg_eac & BIT(30)) &&
3361 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3362 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3363 result |= 0x02;
3364 else
3365 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3366 __func__);
3367out:
3368 return result;
3369}
3370
3371static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3372 int result[][8], int t)
3373{
3374 struct device *dev = &priv->udev->dev;
3375 u32 i, val32;
3376 int path_a_ok, path_b_ok;
3377 int retry = 2;
3378 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3379 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3380 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3381 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3382 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3383 REG_TX_TO_TX, REG_RX_CCK,
3384 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3385 REG_RX_TO_RX, REG_STANDBY,
3386 REG_SLEEP, REG_PMPD_ANAEN
3387 };
3388 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3389 REG_TXPAUSE, REG_BEACON_CTRL,
3390 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3391 };
3392 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3393 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3394 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3395 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3396 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3397 };
3398
3399 /*
3400 * Note: IQ calibration must be performed after loading
3401 * PHY_REG.txt , and radio_a, radio_b.txt
3402 */
3403
3404 if (t == 0) {
3405 /* Save ADDA parameters, turn Path A ADDA on */
3406 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3407 RTL8XXXU_ADDA_REGS);
3408 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3409 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3410 priv->bb_backup, RTL8XXXU_BB_REGS);
3411 }
3412
3413 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3414
3415 if (t == 0) {
3416 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3417 if (val32 & FPGA0_HSSI_PARM1_PI)
3418 priv->pi_enabled = 1;
3419 }
3420
3421 if (!priv->pi_enabled) {
3422 /* Switch BB to PI mode to do IQ Calibration. */
3423 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3424 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3425 }
3426
3427 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3428 val32 &= ~FPGA_RF_MODE_CCK;
3429 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3430
3431 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3432 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3433 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3434
3435 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3436 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3437 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3438
3439 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3440 val32 &= ~BIT(10);
3441 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3442 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3443 val32 &= ~BIT(10);
3444 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3445
3446 if (priv->tx_paths > 1) {
3447 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3448 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3449 }
3450
3451 /* MAC settings */
3452 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3453
3454 /* Page B init */
3455 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3456
3457 if (priv->tx_paths > 1)
3458 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3459
3460 /* IQ calibration setting */
3461 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3462 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3463 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3464
3465 for (i = 0; i < retry; i++) {
3466 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3467 if (path_a_ok == 0x03) {
3468 val32 = rtl8xxxu_read32(priv,
3469 REG_TX_POWER_BEFORE_IQK_A);
3470 result[t][0] = (val32 >> 16) & 0x3ff;
3471 val32 = rtl8xxxu_read32(priv,
3472 REG_TX_POWER_AFTER_IQK_A);
3473 result[t][1] = (val32 >> 16) & 0x3ff;
3474 val32 = rtl8xxxu_read32(priv,
3475 REG_RX_POWER_BEFORE_IQK_A_2);
3476 result[t][2] = (val32 >> 16) & 0x3ff;
3477 val32 = rtl8xxxu_read32(priv,
3478 REG_RX_POWER_AFTER_IQK_A_2);
3479 result[t][3] = (val32 >> 16) & 0x3ff;
3480 break;
3481 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3482 /* TX IQK OK */
3483 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3484 __func__);
3485
3486 val32 = rtl8xxxu_read32(priv,
3487 REG_TX_POWER_BEFORE_IQK_A);
3488 result[t][0] = (val32 >> 16) & 0x3ff;
3489 val32 = rtl8xxxu_read32(priv,
3490 REG_TX_POWER_AFTER_IQK_A);
3491 result[t][1] = (val32 >> 16) & 0x3ff;
3492 }
3493 }
3494
3495 if (!path_a_ok)
3496 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3497
3498 if (priv->tx_paths > 1) {
3499 /*
3500 * Path A into standby
3501 */
3502 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3503 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3504 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3505
3506 /* Turn Path B ADDA on */
3507 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3508
3509 for (i = 0; i < retry; i++) {
3510 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3511 if (path_b_ok == 0x03) {
3512 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3513 result[t][4] = (val32 >> 16) & 0x3ff;
3514 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3515 result[t][5] = (val32 >> 16) & 0x3ff;
3516 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3517 result[t][6] = (val32 >> 16) & 0x3ff;
3518 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3519 result[t][7] = (val32 >> 16) & 0x3ff;
3520 break;
3521 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3522 /* TX IQK OK */
3523 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3524 result[t][4] = (val32 >> 16) & 0x3ff;
3525 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3526 result[t][5] = (val32 >> 16) & 0x3ff;
3527 }
3528 }
3529
3530 if (!path_b_ok)
3531 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3532 }
3533
3534 /* Back to BB mode, load original value */
3535 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3536
3537 if (t) {
3538 if (!priv->pi_enabled) {
3539 /*
3540 * Switch back BB to SI mode after finishing
3541 * IQ Calibration
3542 */
3543 val32 = 0x01000000;
3544 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3545 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3546 }
3547
3548 /* Reload ADDA power saving parameters */
3549 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3550 RTL8XXXU_ADDA_REGS);
3551
3552 /* Reload MAC parameters */
3553 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3554
3555 /* Reload BB parameters */
3556 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3557 priv->bb_backup, RTL8XXXU_BB_REGS);
3558
3559 /* Restore RX initial gain */
3560 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3561
3562 if (priv->tx_paths > 1) {
3563 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3564 0x00032ed3);
3565 }
3566
3567 /* Load 0xe30 IQC default value */
3568 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3569 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3570 }
3571}
3572
3573static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3574{
3575 struct device *dev = &priv->udev->dev;
3576 int result[4][8]; /* last is final result */
3577 int i, candidate;
3578 bool path_a_ok, path_b_ok;
3579 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3580 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3581 s32 reg_tmp = 0;
3582 bool simu;
3583
3584 memset(result, 0, sizeof(result));
3585 candidate = -1;
3586
3587 path_a_ok = false;
3588 path_b_ok = false;
3589
3590 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3591
3592 for (i = 0; i < 3; i++) {
3593 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3594
3595 if (i == 1) {
3596 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3597 if (simu) {
3598 candidate = 0;
3599 break;
3600 }
3601 }
3602
3603 if (i == 2) {
3604 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3605 if (simu) {
3606 candidate = 0;
3607 break;
3608 }
3609
3610 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3611 if (simu) {
3612 candidate = 1;
3613 } else {
3614 for (i = 0; i < 8; i++)
3615 reg_tmp += result[3][i];
3616
3617 if (reg_tmp)
3618 candidate = 3;
3619 else
3620 candidate = -1;
3621 }
3622 }
3623 }
3624
3625 for (i = 0; i < 4; i++) {
3626 reg_e94 = result[i][0];
3627 reg_e9c = result[i][1];
3628 reg_ea4 = result[i][2];
3629 reg_eac = result[i][3];
3630 reg_eb4 = result[i][4];
3631 reg_ebc = result[i][5];
3632 reg_ec4 = result[i][6];
3633 reg_ecc = result[i][7];
3634 }
3635
3636 if (candidate >= 0) {
3637 reg_e94 = result[candidate][0];
3638 priv->rege94 = reg_e94;
3639 reg_e9c = result[candidate][1];
3640 priv->rege9c = reg_e9c;
3641 reg_ea4 = result[candidate][2];
3642 reg_eac = result[candidate][3];
3643 reg_eb4 = result[candidate][4];
3644 priv->regeb4 = reg_eb4;
3645 reg_ebc = result[candidate][5];
3646 priv->regebc = reg_ebc;
3647 reg_ec4 = result[candidate][6];
3648 reg_ecc = result[candidate][7];
3649 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3650 dev_dbg(dev,
3651 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3652 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3653 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3654 path_a_ok = true;
3655 path_b_ok = true;
3656 } else {
3657 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3658 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3659 }
3660
3661 if (reg_e94 && candidate >= 0)
3662 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3663 candidate, (reg_ea4 == 0));
3664
3665 if (priv->tx_paths > 1 && reg_eb4)
3666 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3667 candidate, (reg_ec4 == 0));
3668
3669 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3670 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3671}
3672
3673static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3674{
3675 u32 val32;
3676 u32 rf_amode, rf_bmode = 0, lstf;
3677
3678 /* Check continuous TX and Packet TX */
3679 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3680
3681 if (lstf & OFDM_LSTF_MASK) {
3682 /* Disable all continuous TX */
3683 val32 = lstf & ~OFDM_LSTF_MASK;
3684 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3685
3686 /* Read original RF mode Path A */
3687 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3688
3689 /* Set RF mode to standby Path A */
3690 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3691 (rf_amode & 0x8ffff) | 0x10000);
3692
3693 /* Path-B */
3694 if (priv->tx_paths > 1) {
3695 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3696 RF6052_REG_AC);
3697
3698 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3699 (rf_bmode & 0x8ffff) | 0x10000);
3700 }
3701 } else {
3702 /* Deal with Packet TX case */
3703 /* block all queues */
3704 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3705 }
3706
3707 /* Start LC calibration */
3708 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3709 val32 |= 0x08000;
3710 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3711
3712 msleep(100);
3713
3714 /* Restore original parameters */
3715 if (lstf & OFDM_LSTF_MASK) {
3716 /* Path-A */
3717 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3718 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3719
3720 /* Path-B */
3721 if (priv->tx_paths > 1)
3722 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3723 rf_bmode);
3724 } else /* Deal with Packet TX case */
3725 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3726}
3727
3728static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3729{
3730 int i;
3731 u16 reg;
3732
3733 reg = REG_MACID;
3734
3735 for (i = 0; i < ETH_ALEN; i++)
3736 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3737
3738 return 0;
3739}
3740
3741static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3742{
3743 int i;
3744 u16 reg;
3745
3746 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3747
3748 reg = REG_BSSID;
3749
3750 for (i = 0; i < ETH_ALEN; i++)
3751 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3752
3753 return 0;
3754}
3755
3756static void
3757rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3758{
3759 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3760 u8 max_agg = 0xf;
3761 int i;
3762
3763 ampdu_factor = 1 << (ampdu_factor + 2);
3764 if (ampdu_factor > max_agg)
3765 ampdu_factor = max_agg;
3766
3767 for (i = 0; i < 4; i++) {
3768 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3769 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3770
3771 if ((vals[i] & 0x0f) > ampdu_factor)
3772 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3773
3774 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3775 }
3776}
3777
3778static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3779{
3780 u8 val8;
3781
3782 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3783 val8 &= 0xf8;
3784 val8 |= density;
3785 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3786}
3787
3788static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3789{
3790 u8 val8;
3791 int count, ret;
3792
3793 /* Start of rtl8723AU_card_enable_flow */
3794 /* Act to Cardemu sequence*/
3795 /* Turn off RF */
3796 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3797
3798 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3799 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3800 val8 &= ~LEDCFG2_DPDT_SELECT;
3801 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3802
3803 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3804 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3805 val8 |= BIT(1);
3806 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3807
3808 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3809 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3810 if ((val8 & BIT(1)) == 0)
3811 break;
3812 udelay(10);
3813 }
3814
3815 if (!count) {
3816 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3817 __func__);
3818 ret = -EBUSY;
3819 goto exit;
3820 }
3821
3822 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3823 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3824 val8 |= SYS_ISO_ANALOG_IPS;
3825 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3826
3827 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3828 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3829 val8 &= ~LDOA15_ENABLE;
3830 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3831
3832exit:
3833 return ret;
3834}
3835
3836static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3837{
3838 u8 val8;
3839 u8 val32;
3840 int count, ret;
3841
3842 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3843
3844 /*
3845 * Poll - wait for RX packet to complete
3846 */
3847 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3848 val32 = rtl8xxxu_read32(priv, 0x5f8);
3849 if (!val32)
3850 break;
3851 udelay(10);
3852 }
3853
3854 if (!count) {
3855 dev_warn(&priv->udev->dev,
3856 "%s: RX poll timed out (0x05f8)\n", __func__);
3857 ret = -EBUSY;
3858 goto exit;
3859 }
3860
3861 /* Disable CCK and OFDM, clock gated */
3862 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3863 val8 &= ~SYS_FUNC_BBRSTB;
3864 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3865
3866 udelay(2);
3867
3868 /* Reset baseband */
3869 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3870 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3871 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3872
3873 /* Reset MAC TRX */
3874 val8 = rtl8xxxu_read8(priv, REG_CR);
3875 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3876 rtl8xxxu_write8(priv, REG_CR, val8);
3877
3878 /* Reset MAC TRX */
3879 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3880 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3881 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3882
3883 /* Respond TX OK to scheduler */
3884 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3885 val8 |= DUAL_TSF_TX_OK;
3886 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3887
3888exit:
3889 return ret;
3890}
3891
c05a9dbf 3892static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 3893{
3894 u8 val8;
3895
3896 /* Clear suspend enable and power down enable*/
3897 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3898 val8 &= ~(BIT(3) | BIT(7));
3899 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3900
3901 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3902 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3903 val8 &= ~BIT(0);
3904 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3905
3906 /* 0x04[12:11] = 11 enable WL suspend*/
3907 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3908 val8 &= ~(BIT(3) | BIT(4));
3909 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3910}
3911
c05a9dbf
JS		 3912static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
3913{
3914 u8 val8;
3915
3916 /* Clear suspend enable and power down enable*/
3917 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3918 val8 &= ~(BIT(3) | BIT(4));
3919 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3920}
3921
3922static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
3923{
3924 u8 val8;
3925 u32 val32;
3926 int count, ret = 0;
3927
3928 /* disable HWPDN 0x04[15]=0*/
3929 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3930 val8 &= ~BIT(7);
3931 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3932
3933 /* disable SW LPS 0x04[10]= 0 */
3934 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3935 val8 &= ~BIT(2);
3936 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3937
3938 /* disable WL suspend*/
3939 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3940 val8 &= ~(BIT(3) | BIT(4));
3941 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3942
3943 /* wait till 0x04[17] = 1 power ready*/
3944 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3945 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3946 if (val32 & BIT(17))
3947 break;
3948
3949 udelay(10);
3950 }
3951
3952 if (!count) {
3953 ret = -EBUSY;
3954 goto exit;
3955 }
3956
3957 /* We should be able to optimize the following three entries into one */
3958
3959 /* release WLON reset 0x04[16]= 1*/
3960 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3961 val8 |= BIT(0);
3962 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3963
3964 /* set, then poll until 0 */
3965 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3966 val32 |= APS_FSMCO_MAC_ENABLE;
3967 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3968
3969 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3970 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3971 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3972 ret = 0;
3973 break;
3974 }
3975 udelay(10);
3976 }
3977
3978 if (!count) {
3979 ret = -EBUSY;
3980 goto exit;
3981 }
3982
3983exit:
3984 return ret;
3985}
3986
3987static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 3988{
3989 u8 val8;
3990 u32 val32;
3991 int count, ret = 0;
3992
3993 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3994 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3995 val8 |= LDOA15_ENABLE;
3996 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3997
3998 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3999 val8 = rtl8xxxu_read8(priv, 0x0067);
4000 val8 &= ~BIT(4);
4001 rtl8xxxu_write8(priv, 0x0067, val8);
4002
4003 mdelay(1);
4004
4005 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
4006 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4007 val8 &= ~SYS_ISO_ANALOG_IPS;
4008 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4009
4010 /* disable SW LPS 0x04[10]= 0 */
4011 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4012 val8 &= ~BIT(2);
4013 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4014
4015 /* wait till 0x04[17] = 1 power ready*/
4016 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4017 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4018 if (val32 & BIT(17))
4019 break;
4020
4021 udelay(10);
4022 }
4023
4024 if (!count) {
4025 ret = -EBUSY;
4026 goto exit;
4027 }
4028
4029 /* We should be able to optimize the following three entries into one */
4030
4031 /* release WLON reset 0x04[16]= 1*/
4032 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4033 val8 |= BIT(0);
4034 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4035
4036 /* disable HWPDN 0x04[15]= 0*/
4037 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4038 val8 &= ~BIT(7);
4039 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4040
4041 /* disable WL suspend*/
4042 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4043 val8 &= ~(BIT(3) | BIT(4));
4044 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4045
4046 /* set, then poll until 0 */
4047 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4048 val32 |= APS_FSMCO_MAC_ENABLE;
4049 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
4050
4051 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
4052 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
4053 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
4054 ret = 0;
4055 break;
4056 }
4057 udelay(10);
4058 }
4059
4060 if (!count) {
4061 ret = -EBUSY;
4062 goto exit;
4063 }
4064
4065 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
4066 /*
4067 * Note: Vendor driver actually clears this bit, despite the
4068 * documentation claims it's being set!
4069 */
4070 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4071 val8 |= LEDCFG2_DPDT_SELECT;
4072 val8 &= ~LEDCFG2_DPDT_SELECT;
4073 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4074
4075exit:
4076 return ret;
4077}
4078
4079static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
4080{
4081 u8 val8;
4082
4083 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
4084 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
4085
4086 /* 0x04[12:11] = 01 enable WL suspend */
4087 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4088 val8 &= ~BIT(4);
4089 val8 |= BIT(3);
4090 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4091
4092 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
4093 val8 |= BIT(7);
4094 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
4095
4096 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
4097 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
4098 val8 |= BIT(0);
4099 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
4100
4101 return 0;
4102}
4103
4104static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
4105{
4106 u8 val8;
4107 u16 val16;
4108 u32 val32;
4109 int ret;
4110
4111 /*
4112 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4113 */
4114 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4115
c05a9dbf 4116 rtl8723a_disabled_to_emu(priv);
26f1fad2 4117
c05a9dbf 4118 ret = rtl8723a_emu_to_active(priv);
26f1fad2
JS		 4119 if (ret)
4120 goto exit;
4121
4122 /*
4123 * 0x0004[19] = 1, reset 8051
4124 */
4125 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
4126 val8 |= BIT(3);
4127 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
4128
4129 /*
4130 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4131 * Set CR bit10 to enable 32k calibration.
4132 */
4133 val16 = rtl8xxxu_read16(priv, REG_CR);
4134 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4135 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4136 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4137 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4138 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4139 rtl8xxxu_write16(priv, REG_CR, val16);
4140
4141 /* For EFuse PG */
4142 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
4143 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
4144 val32 |= (0x06 << 28);
4145 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
4146exit:
4147 return ret;
4148}
4149
c0963772
KV		 4150#ifdef CONFIG_RTL8XXXU_UNTESTED
4151
26f1fad2
JS		 4152static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
4153{
4154 u8 val8;
4155 u16 val16;
4156 u32 val32;
4157 int i;
4158
4159 for (i = 100; i; i--) {
4160 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
4161 if (val8 & APS_FSMCO_PFM_ALDN)
4162 break;
4163 }
4164
4165 if (!i) {
4166 pr_info("%s: Poll failed\n", __func__);
4167 return -ENODEV;
4168 }
4169
4170 /*
4171 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
4172 */
4173 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4174 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
4175 udelay(100);
4176
4177 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
4178 if (!(val8 & LDOV12D_ENABLE)) {
4179 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
4180 val8 |= LDOV12D_ENABLE;
4181 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
4182
4183 udelay(100);
4184
4185 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4186 val8 &= ~SYS_ISO_MD2PP;
4187 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4188 }
4189
4190 /*
4191 * Auto enable WLAN
4192 */
4193 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4194 val16 |= APS_FSMCO_MAC_ENABLE;
4195 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4196
4197 for (i = 1000; i; i--) {
4198 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4199 if (!(val16 & APS_FSMCO_MAC_ENABLE))
4200 break;
4201 }
4202 if (!i) {
4203 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
4204 return -EBUSY;
4205 }
4206
4207 /*
4208 * Enable radio, GPIO, LED
4209 */
4210 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
4211 APS_FSMCO_PFM_ALDN;
4212 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4213
4214 /*
4215 * Release RF digital isolation
4216 */
4217 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
4218 val16 &= ~SYS_ISO_DIOR;
4219 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
4220
4221 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4222 val8 &= ~APSD_CTRL_OFF;
4223 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
4224 for (i = 200; i; i--) {
4225 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4226 if (!(val8 & APSD_CTRL_OFF_STATUS))
4227 break;
4228 }
4229
4230 if (!i) {
4231 pr_info("%s: APSD_CTRL poll failed\n", __func__);
4232 return -EBUSY;
4233 }
4234
4235 /*
4236 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4237 */
4238 val16 = rtl8xxxu_read16(priv, REG_CR);
4239 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4240 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
4241 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
4242 rtl8xxxu_write16(priv, REG_CR, val16);
4243
4244 /*
4245 * Workaround for 8188RU LNA power leakage problem.
4246 */
4247 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4248 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4249 val32 &= ~BIT(1);
4250 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4251 }
4252 return 0;
4253}
4254
c0963772
KV		 4255#endif
4256
c05a9dbf
JS		 4257static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
4258{
4259 u16 val16;
4260 u32 val32;
4261 int ret;
4262
4263 ret = 0;
4264
4265 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
4266 if (val32 & SYS_CFG_SPS_LDO_SEL) {
4267 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
4268 } else {
4269 /*
4270 * Raise 1.2V voltage
4271 */
4272 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
4273 val32 &= 0xff0fffff;
4274 val32 |= 0x00500000;
4275 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
4276 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
4277 }
4278
4279 rtl8192e_disabled_to_emu(priv);
4280
4281 ret = rtl8192e_emu_to_active(priv);
4282 if (ret)
4283 goto exit;
4284
4285 rtl8xxxu_write16(priv, REG_CR, 0x0000);
4286
4287 /*
4288 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4289 * Set CR bit10 to enable 32k calibration.
4290 */
4291 val16 = rtl8xxxu_read16(priv, REG_CR);
4292 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4293 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
4294 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
4295 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
4296 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
4297 rtl8xxxu_write16(priv, REG_CR, val16);
4298
4299exit:
4300 return ret;
4301}
4302
26f1fad2
JS		 4303static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
4304{
4305 u8 val8;
4306 u16 val16;
4307 u32 val32;
4308
4309 /*
4310 * Workaround for 8188RU LNA power leakage problem.
4311 */
4312 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4313 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4314 val32 |= BIT(1);
4315 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4316 }
4317
4318 rtl8xxxu_active_to_lps(priv);
4319
4320 /* Turn off RF */
4321 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
4322
4323 /* Reset Firmware if running in RAM */
4324 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
4325 rtl8xxxu_firmware_self_reset(priv);
4326
4327 /* Reset MCU */
4328 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4329 val16 &= ~SYS_FUNC_CPU_ENABLE;
4330 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4331
4332 /* Reset MCU ready status */
4333 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4334
4335 rtl8xxxu_active_to_emu(priv);
4336 rtl8xxxu_emu_to_disabled(priv);
4337
4338 /* Reset MCU IO Wrapper */
4339 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4340 val8 &= ~BIT(0);
4341 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4342
4343 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4344 val8 |= BIT(0);
4345 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4346
4347 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
4348 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4349}
4350
4351static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4352{
4353 if (!priv->has_bluetooth)
4354 return;
4355}
4356
4357static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4358{
4359 struct rtl8xxxu_priv *priv = hw->priv;
4360 struct device *dev = &priv->udev->dev;
4361 struct rtl8xxxu_rfregval *rftable;
4362 bool macpower;
4363 int ret;
4364 u8 val8;
4365 u16 val16;
4366 u32 val32;
4367
4368 /* Check if MAC is already powered on */
4369 val8 = rtl8xxxu_read8(priv, REG_CR);
4370
4371 /*
4372 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4373 * initialized. First MAC returns 0xea, second MAC returns 0x00
4374 */
4375 if (val8 == 0xea)
4376 macpower = false;
4377 else
4378 macpower = true;
4379
4380 ret = priv->fops->power_on(priv);
4381 if (ret < 0) {
4382 dev_warn(dev, "%s: Failed power on\n", __func__);
4383 goto exit;
4384 }
4385
07bb46be
JS		 4386 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4387 if (!macpower) {
4388 if (priv->ep_tx_normal_queue)
4389 val8 = TX_PAGE_NUM_NORM_PQ;
4390 else
4391 val8 = 0;
4392
4393 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4394
4395 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4396
4397 if (priv->ep_tx_high_queue)
4398 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4399 if (priv->ep_tx_low_queue)
4400 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4401
4402 rtl8xxxu_write32(priv, REG_RQPN, val32);
4403
4404 /*
4405 * Set TX buffer boundary
4406 */
4407 val8 = TX_TOTAL_PAGE_NUM + 1;
4408 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4409 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4410 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4411 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4412 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4413 }
4414
a47b9d47
JS		 4415 ret = rtl8xxxu_download_firmware(priv);
4416 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4417 if (ret)
4418 goto exit;
4419 ret = rtl8xxxu_start_firmware(priv);
4420 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4421 if (ret)
4422 goto exit;
4423
07bb46be
JS		 4424 ret = rtl8xxxu_init_queue_priority(priv);
4425 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4426 if (ret)
4427 goto exit;
4428
26f1fad2
JS		 4429 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4430 if (!macpower) {
74b99bed 4431 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
26f1fad2
JS		 4432 if (ret) {
4433 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4434 goto exit;
4435 }
4436 }
4437
b63d0aac
JS		 4438 if (priv->rtlchip == 0x8192e) {
4439 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
4440 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
4441 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
99ad16cb
JS		 4442
4443 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4444 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
b63d0aac
JS		 4445 }
4446
26f1fad2
JS		 4447 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4448 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4449 if (ret)
4450 goto exit;
4451
4452 ret = rtl8xxxu_init_phy_bb(priv);
4453 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4454 if (ret)
4455 goto exit;
4456
4457 switch(priv->rtlchip) {
4458 case 0x8723a:
4459 rftable = rtl8723au_radioa_1t_init_table;
4460 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4461 break;
4462 case 0x8188c:
4463 if (priv->hi_pa)
4464 rftable = rtl8188ru_radioa_1t_highpa_table;
4465 else
4466 rftable = rtl8192cu_radioa_1t_init_table;
4467 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4468 break;
4469 case 0x8191c:
4470 rftable = rtl8192cu_radioa_1t_init_table;
4471 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4472 break;
4473 case 0x8192c:
4474 rftable = rtl8192cu_radioa_2t_init_table;
4475 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4476 if (ret)
4477 break;
4478 rftable = rtl8192cu_radiob_2t_init_table;
4479 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4480 break;
4481 default:
4482 ret = -EINVAL;
4483 }
4484
4485 if (ret)
4486 goto exit;
4487
4488 /* Reduce 80M spur */
4489 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4490 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4491 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4492 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4493
4494 /* RFSW Control - clear bit 14 ?? */
4495 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4496 /* 0x07000760 */
4497 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4498 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4499 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4500 FPGA0_RF_BD_CTRL_SHIFT);
4501 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4502 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4503 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4504
4505 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4506 RF6052_REG_MODE_AG);
4507
26f1fad2
JS		 4508 /*
4509 * Set RX page boundary
4510 */
4511 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4512 /*
4513 * Transfer page size is always 128
4514 */
4515 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4516 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4517 rtl8xxxu_write8(priv, REG_PBP, val8);
4518
4519 /*
4520 * Unit in 8 bytes, not obvious what it is used for
4521 */
4522 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4523
4524 /*
4525 * Enable all interrupts - not obvious USB needs to do this
4526 */
4527 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4528 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4529
4530 rtl8xxxu_set_mac(priv);
4531 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4532
4533 /*
4534 * Configure initial WMAC settings
4535 */
4536 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
26f1fad2
JS		 4537 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4538 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4539 rtl8xxxu_write32(priv, REG_RCR, val32);
4540
4541 /*
4542 * Accept all multicast
4543 */
4544 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4545 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4546
4547 /*
4548 * Init adaptive controls
4549 */
4550 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4551 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4552 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4553 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4554
4555 /* CCK = 0x0a, OFDM = 0x10 */
4556 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4557 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4558 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4559
4560 /*
4561 * Init EDCA
4562 */
4563 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4564
4565 /* Set CCK SIFS */
4566 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4567
4568 /* Set OFDM SIFS */
4569 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4570
4571 /* TXOP */
4572 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4573 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4574 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4575 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4576
4577 /* Set data auto rate fallback retry count */
4578 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4579 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4580 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4581 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4582
4583 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4584 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4585 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4586
4587 /* Set ACK timeout */
4588 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4589
4590 /*
4591 * Initialize beacon parameters
4592 */
4593 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4594 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4595 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4596 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4597 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4598 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4599
4600 /*
4601 * Enable CCK and OFDM block
4602 */
4603 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4604 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4605 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4606
4607 /*
4608 * Invalidate all CAM entries - bit 30 is undocumented
4609 */
4610 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4611
4612 /*
4613 * Start out with default power levels for channel 6, 20MHz
4614 */
4615 rtl8723a_set_tx_power(priv, 1, false);
4616
4617 /* Let the 8051 take control of antenna setting */
4618 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4619 val8 |= LEDCFG2_DPDT_SELECT;
4620 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4621
4622 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4623
4624 /* Disable BAR - not sure if this has any effect on USB */
4625 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4626
4627 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4628
e5c447cc 4629 rtl8723a_phy_iq_calibrate(priv);
26f1fad2
JS		 4630
4631 /*
4632 * This should enable thermal meter
4633 */
4634 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4635
4636 rtl8723a_phy_lc_calibrate(priv);
4637
4638 /* fix USB interface interference issue */
4639 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4640 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4641 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4642 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4643
4644 /* Solve too many protocol error on USB bus */
4645 /* Can't do this for 8188/8192 UMC A cut parts */
4646 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4647 rtl8xxxu_write8(priv, 0xfe41, 0x94);
4648 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4649
4650 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4651 rtl8xxxu_write8(priv, 0xfe41, 0x19);
4652 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4653
4654 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4655 rtl8xxxu_write8(priv, 0xfe41, 0x91);
4656 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4657
4658 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4659 rtl8xxxu_write8(priv, 0xfe41, 0x81);
4660 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4661
4662 /* Init BT hw config. */
4663 rtl8xxxu_init_bt(priv);
4664
4665 /*
4666 * Not sure if we really need to save these parameters, but the
4667 * vendor driver does
4668 */
4669 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4670 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4671 priv->path_a_hi_power = 1;
4672
4673 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4674 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4675
4676 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4677 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4678
4679 /* Set NAV_UPPER to 30000us */
4680 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4681 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4682
4042e617
JS		 4683 if (priv->rtlchip == 0x8723a) {
4684 /*
4685 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4686 * but we need to find root cause.
4687 * This is 8723au only.
4688 */
4689 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4690 if ((val32 & 0xff000000) != 0x83000000) {
4691 val32 |= FPGA_RF_MODE_CCK;
4692 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4693 }
26f1fad2
JS		 4694 }
4695
4696 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4697 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4698 /* ack for xmit mgmt frames. */
4699 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4700
4701exit:
4702 return ret;
4703}
4704
4705static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4706{
4707 struct rtl8xxxu_priv *priv = hw->priv;
4708
4709 rtl8xxxu_power_off(priv);
4710}
4711
4712static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4713 struct ieee80211_key_conf *key, const u8 *mac)
4714{
4715 u32 cmd, val32, addr, ctrl;
4716 int j, i, tmp_debug;
4717
4718 tmp_debug = rtl8xxxu_debug;
4719 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4720 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4721
4722 /*
4723 * This is a bit of a hack - the lower bits of the cipher
4724 * suite selector happens to match the cipher index in the CAM
4725 */
4726 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4727 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4728
4729 for (j = 5; j >= 0; j--) {
4730 switch (j) {
4731 case 0:
4732 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4733 break;
4734 case 1:
4735 val32 = mac[2] | (mac[3] << 8) |
4736 (mac[4] << 16) | (mac[5] << 24);
4737 break;
4738 default:
4739 i = (j - 2) << 2;
4740 val32 = key->key[i] | (key->key[i + 1] << 8) |
4741 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4742 break;
4743 }
4744
4745 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4746 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4747 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4748 udelay(100);
4749 }
4750
4751 rtl8xxxu_debug = tmp_debug;
4752}
4753
4754static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
56e4374a 4755 struct ieee80211_vif *vif, const u8 *mac)
26f1fad2
JS		 4756{
4757 struct rtl8xxxu_priv *priv = hw->priv;
4758 u8 val8;
4759
4760 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4761 val8 |= BEACON_DISABLE_TSF_UPDATE;
4762 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4763}
4764
4765static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4766 struct ieee80211_vif *vif)
4767{
4768 struct rtl8xxxu_priv *priv = hw->priv;
4769 u8 val8;
4770
4771 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4772 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4773 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4774}
4775
4776static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4777 u32 ramask, int sgi)
4778{
4779 struct h2c_cmd h2c;
4780
4781 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4782 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4783 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4784
4785 h2c.ramask.arg = 0x80;
4786 if (sgi)
4787 h2c.ramask.arg |= 0x20;
4788
4789 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4790 ramask, h2c.ramask.arg);
4791 rtl8723a_h2c_cmd(priv, &h2c);
4792}
4793
4794static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4795{
4796 u32 val32;
4797 u8 rate_idx = 0;
4798
4799 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4800
4801 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4802 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4803 val32 |= rate_cfg;
4804 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4805
4806 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4807
4808 while (rate_cfg) {
4809 rate_cfg = (rate_cfg >> 1);
4810 rate_idx++;
4811 }
4812 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4813}
4814
4815static void
4816rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4817 struct ieee80211_bss_conf *bss_conf, u32 changed)
4818{
4819 struct rtl8xxxu_priv *priv = hw->priv;
4820 struct device *dev = &priv->udev->dev;
4821 struct ieee80211_sta *sta;
4822 u32 val32;
4823 u8 val8;
4824
4825 if (changed & BSS_CHANGED_ASSOC) {
4826 struct h2c_cmd h2c;
4827
4828 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4829
4830 memset(&h2c, 0, sizeof(struct h2c_cmd));
4831 rtl8xxxu_set_linktype(priv, vif->type);
4832
4833 if (bss_conf->assoc) {
4834 u32 ramask;
4835 int sgi = 0;
4836
4837 rcu_read_lock();
4838 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4839 if (!sta) {
4840 dev_info(dev, "%s: ASSOC no sta found\n",
4841 __func__);
4842 rcu_read_unlock();
4843 goto error;
4844 }
4845
4846 if (sta->ht_cap.ht_supported)
4847 dev_info(dev, "%s: HT supported\n", __func__);
4848 if (sta->vht_cap.vht_supported)
4849 dev_info(dev, "%s: VHT supported\n", __func__);
4850
4851 /* TODO: Set bits 28-31 for rate adaptive id */
4852 ramask = (sta->supp_rates[0] & 0xfff) |
4853 sta->ht_cap.mcs.rx_mask[0] << 12 |
4854 sta->ht_cap.mcs.rx_mask[1] << 20;
4855 if (sta->ht_cap.cap &
4856 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4857 sgi = 1;
4858 rcu_read_unlock();
4859
4860 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4861
26f1fad2
JS		 4862 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4863
4864 rtl8723a_stop_tx_beacon(priv);
4865
4866 /* joinbss sequence */
4867 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4868 0xc000 | bss_conf->aid);
4869
4870 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4871 } else {
26f1fad2
JS		 4872 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4873 val8 |= BEACON_DISABLE_TSF_UPDATE;
4874 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4875
26f1fad2
JS		 4876 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4877 }
4878 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4879 rtl8723a_h2c_cmd(priv, &h2c);
4880 }
4881
4882 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4883 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4884 bss_conf->use_short_preamble);
4885 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4886 if (bss_conf->use_short_preamble)
4887 val32 |= RSR_ACK_SHORT_PREAMBLE;
4888 else
4889 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4890 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4891 }
4892
4893 if (changed & BSS_CHANGED_ERP_SLOT) {
4894 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4895 bss_conf->use_short_slot);
4896
4897 if (bss_conf->use_short_slot)
4898 val8 = 9;
4899 else
4900 val8 = 20;
4901 rtl8xxxu_write8(priv, REG_SLOT, val8);
4902 }
4903
4904 if (changed & BSS_CHANGED_BSSID) {
4905 dev_dbg(dev, "Changed BSSID!\n");
4906 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4907 }
4908
4909 if (changed & BSS_CHANGED_BASIC_RATES) {
4910 dev_dbg(dev, "Changed BASIC_RATES!\n");
4911 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4912 }
4913error:
4914 return;
4915}
4916
4917static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4918{
4919 u32 rtlqueue;
4920
4921 switch (queue) {
4922 case IEEE80211_AC_VO:
4923 rtlqueue = TXDESC_QUEUE_VO;
4924 break;
4925 case IEEE80211_AC_VI:
4926 rtlqueue = TXDESC_QUEUE_VI;
4927 break;
4928 case IEEE80211_AC_BE:
4929 rtlqueue = TXDESC_QUEUE_BE;
4930 break;
4931 case IEEE80211_AC_BK:
4932 rtlqueue = TXDESC_QUEUE_BK;
4933 break;
4934 default:
4935 rtlqueue = TXDESC_QUEUE_BE;
4936 }
4937
4938 return rtlqueue;
4939}
4940
4941static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4942{
4943 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4944 u32 queue;
4945
4946 if (ieee80211_is_mgmt(hdr->frame_control))
4947 queue = TXDESC_QUEUE_MGNT;
4948 else
4949 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4950
4951 return queue;
4952}
4953
4954static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4955{
4956 __le16 *ptr = (__le16 *)tx_desc;
4957 u16 csum = 0;
4958 int i;
4959
4960 /*
4961 * Clear csum field before calculation, as the csum field is
4962 * in the middle of the struct.
4963 */
4964 tx_desc->csum = cpu_to_le16(0);
4965
4966 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4967 csum = csum ^ le16_to_cpu(ptr[i]);
4968
4969 tx_desc->csum |= cpu_to_le16(csum);
4970}
4971
4972static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4973{
4974 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4975 unsigned long flags;
4976
4977 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4978 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4979 list_del(&tx_urb->list);
4980 priv->tx_urb_free_count--;
4981 usb_free_urb(&tx_urb->urb);
4982 }
4983 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4984}
4985
4986static struct rtl8xxxu_tx_urb *
4987rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4988{
4989 struct rtl8xxxu_tx_urb *tx_urb;
4990 unsigned long flags;
4991
4992 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4993 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4994 struct rtl8xxxu_tx_urb, list);
4995 if (tx_urb) {
4996 list_del(&tx_urb->list);
4997 priv->tx_urb_free_count--;
4998 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4999 !priv->tx_stopped) {
5000 priv->tx_stopped = true;
5001 ieee80211_stop_queues(priv->hw);
5002 }
5003 }
5004
5005 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5006
5007 return tx_urb;
5008}
5009
5010static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5011 struct rtl8xxxu_tx_urb *tx_urb)
5012{
5013 unsigned long flags;
5014
5015 INIT_LIST_HEAD(&tx_urb->list);
5016
5017 spin_lock_irqsave(&priv->tx_urb_lock, flags);
5018
5019 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5020 priv->tx_urb_free_count++;
5021 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5022 priv->tx_stopped) {
5023 priv->tx_stopped = false;
5024 ieee80211_wake_queues(priv->hw);
5025 }
5026
5027 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5028}
5029
5030static void rtl8xxxu_tx_complete(struct urb *urb)
5031{
5032 struct sk_buff *skb = (struct sk_buff *)urb->context;
5033 struct ieee80211_tx_info *tx_info;
5034 struct ieee80211_hw *hw;
5035 struct rtl8xxxu_tx_urb *tx_urb =
5036 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5037
5038 tx_info = IEEE80211_SKB_CB(skb);
5039 hw = tx_info->rate_driver_data[0];
5040
5041 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
5042
5043 ieee80211_tx_info_clear_status(tx_info);
5044 tx_info->status.rates[0].idx = -1;
5045 tx_info->status.rates[0].count = 0;
5046
5047 if (!urb->status)
5048 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5049
5050 ieee80211_tx_status_irqsafe(hw, skb);
5051
5052 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
5053}
5054
5055static void rtl8xxxu_dump_action(struct device *dev,
5056 struct ieee80211_hdr *hdr)
5057{
5058 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5059 u16 cap, timeout;
5060
5061 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5062 return;
5063
5064 switch (mgmt->u.action.u.addba_resp.action_code) {
5065 case WLAN_ACTION_ADDBA_RESP:
5066 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5067 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5068 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5069 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5070 "status %02x\n",
5071 timeout,
5072 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5073 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5074 (cap >> 1) & 0x1,
5075 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5076 break;
5077 case WLAN_ACTION_ADDBA_REQ:
5078 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5079 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5080 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5081 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5082 timeout,
5083 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5084 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5085 (cap >> 1) & 0x1);
5086 break;
5087 default:
5088 dev_info(dev, "action frame %02x\n",
5089 mgmt->u.action.u.addba_resp.action_code);
5090 break;
5091 }
5092}
5093
5094static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5095 struct ieee80211_tx_control *control,
5096 struct sk_buff *skb)
5097{
5098 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5099 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5100 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
5101 struct rtl8xxxu_priv *priv = hw->priv;
5102 struct rtl8xxxu_tx_desc *tx_desc;
5103 struct rtl8xxxu_tx_urb *tx_urb;
5104 struct ieee80211_sta *sta = NULL;
5105 struct ieee80211_vif *vif = tx_info->control.vif;
5106 struct device *dev = &priv->udev->dev;
5107 u32 queue, rate;
5108 u16 pktlen = skb->len;
5109 u16 seq_number;
5110 u16 rate_flag = tx_info->control.rates[0].flags;
5111 int ret;
5112
5113 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
5114 dev_warn(dev,
5115 "%s: Not enough headroom (%i) for tx descriptor\n",
5116 __func__, skb_headroom(skb));
5117 goto error;
5118 }
5119
5120 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
5121 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5122 __func__, skb->len);
5123 goto error;
5124 }
5125
5126 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5127 if (!tx_urb) {
5128 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5129 goto error;
5130 }
5131
5132 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5133 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
5134 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
5135
5136 if (ieee80211_is_action(hdr->frame_control))
5137 rtl8xxxu_dump_action(dev, hdr);
5138
5139 tx_info->rate_driver_data[0] = hw;
5140
5141 if (control && control->sta)
5142 sta = control->sta;
5143
5144 tx_desc = (struct rtl8xxxu_tx_desc *)
5145 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
5146
5147 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
5148 tx_desc->pkt_size = cpu_to_le16(pktlen);
5149 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
5150
5151 tx_desc->txdw0 =
5152 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5153 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5154 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5155 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5156
5157 queue = rtl8xxxu_queue_select(hw, skb);
5158 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5159
5160 if (tx_info->control.hw_key) {
5161 switch (tx_info->control.hw_key->cipher) {
5162 case WLAN_CIPHER_SUITE_WEP40:
5163 case WLAN_CIPHER_SUITE_WEP104:
5164 case WLAN_CIPHER_SUITE_TKIP:
5165 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5166 break;
5167 case WLAN_CIPHER_SUITE_CCMP:
5168 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5169 break;
5170 default:
5171 break;
5172 }
5173 }
5174
5175 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5176 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
5177
5178 if (rate_flag & IEEE80211_TX_RC_MCS)
5179 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
5180 else
5181 rate = tx_rate->hw_value;
5182 tx_desc->txdw5 = cpu_to_le32(rate);
5183
5184 if (ieee80211_is_data(hdr->frame_control))
5185 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5186
5187 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5188 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5189 if (sta->ht_cap.ht_supported) {
5190 u32 ampdu, val32;
5191
5192 ampdu = (u32)sta->ht_cap.ampdu_density;
5193 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5194 tx_desc->txdw2 |= cpu_to_le32(val32);
5195 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
5196 } else
5197 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5198 } else
5199 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
5200
5201 if (ieee80211_is_data_qos(hdr->frame_control))
5202 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
5203 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5204 (sta && vif && vif->bss_conf.use_short_preamble))
5205 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
5206 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
5207 (ieee80211_is_data_qos(hdr->frame_control) &&
5208 sta && sta->ht_cap.cap &
5209 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
5210 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
5211 }
5212 if (ieee80211_is_mgmt(hdr->frame_control)) {
5213 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
5214 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
5215 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
5216 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
5217 }
5218
5219 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
5220 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
5221 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
5222 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
5223 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
5224 }
5225
5226 rtl8xxxu_calc_tx_desc_csum(tx_desc);
5227
5228 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5229 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5230
5231 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5232 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5233 if (ret) {
5234 usb_unanchor_urb(&tx_urb->urb);
5235 rtl8xxxu_free_tx_urb(priv, tx_urb);
5236 goto error;
5237 }
5238 return;
5239error:
5240 dev_kfree_skb(skb);
5241}
5242
5243static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5244 struct ieee80211_rx_status *rx_status,
5245 struct rtl8xxxu_rx_desc *rx_desc,
5246 struct rtl8723au_phy_stats *phy_stats)
5247{
5248 if (phy_stats->sgi_en)
5249 rx_status->flag |= RX_FLAG_SHORT_GI;
5250
5251 if (rx_desc->rxmcs < DESC_RATE_6M) {
5252 /*
5253 * Handle PHY stats for CCK rates
5254 */
5255 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5256
5257 switch (cck_agc_rpt & 0xc0) {
5258 case 0xc0:
5259 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5260 break;
5261 case 0x80:
5262 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5263 break;
5264 case 0x40:
5265 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5266 break;
5267 case 0x00:
5268 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5269 break;
5270 }
5271 } else {
5272 rx_status->signal =
5273 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5274 }
5275}
5276
5277static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5278{
5279 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5280 unsigned long flags;
5281
5282 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5283
5284 list_for_each_entry_safe(rx_urb, tmp,
5285 &priv->rx_urb_pending_list, list) {
5286 list_del(&rx_urb->list);
5287 priv->rx_urb_pending_count--;
5288 usb_free_urb(&rx_urb->urb);
5289 }
5290
5291 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5292}
5293
5294static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5295 struct rtl8xxxu_rx_urb *rx_urb)
5296{
5297 struct sk_buff *skb;
5298 unsigned long flags;
5299 int pending = 0;
5300
5301 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5302
5303 if (!priv->shutdown) {
5304 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5305 priv->rx_urb_pending_count++;
5306 pending = priv->rx_urb_pending_count;
5307 } else {
5308 skb = (struct sk_buff *)rx_urb->urb.context;
5309 dev_kfree_skb(skb);
5310 usb_free_urb(&rx_urb->urb);
5311 }
5312
5313 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5314
5315 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5316 schedule_work(&priv->rx_urb_wq);
5317}
5318
5319static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5320{
5321 struct rtl8xxxu_priv *priv;
5322 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5323 struct list_head local;
5324 struct sk_buff *skb;
5325 unsigned long flags;
5326 int ret;
5327
5328 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5329 INIT_LIST_HEAD(&local);
5330
5331 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5332
5333 list_splice_init(&priv->rx_urb_pending_list, &local);
5334 priv->rx_urb_pending_count = 0;
5335
5336 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5337
5338 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5339 list_del_init(&rx_urb->list);
5340 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5341 /*
5342 * If out of memory or temporary error, put it back on the
5343 * queue and try again. Otherwise the device is dead/gone
5344 * and we should drop it.
5345 */
5346 switch (ret) {
5347 case 0:
5348 break;
5349 case -ENOMEM:
5350 case -EAGAIN:
5351 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5352 break;
5353 default:
5354 pr_info("failed to requeue urb %i\n", ret);
5355 skb = (struct sk_buff *)rx_urb->urb.context;
5356 dev_kfree_skb(skb);
5357 usb_free_urb(&rx_urb->urb);
5358 }
5359 }
5360}
5361
5362static void rtl8xxxu_rx_complete(struct urb *urb)
5363{
5364 struct rtl8xxxu_rx_urb *rx_urb =
5365 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5366 struct ieee80211_hw *hw = rx_urb->hw;
5367 struct rtl8xxxu_priv *priv = hw->priv;
5368 struct sk_buff *skb = (struct sk_buff *)urb->context;
5369 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5370 struct rtl8723au_phy_stats *phy_stats;
5371 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
26f1fad2
JS		 5372 struct device *dev = &priv->udev->dev;
5373 __le32 *_rx_desc_le = (__le32 *)skb->data;
5374 u32 *_rx_desc = (u32 *)skb->data;
a9ffa615 5375 int drvinfo_sz, desc_shift, i;
26f1fad2
JS		 5376
5377 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5378 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5379
26f1fad2
JS		 5380 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5381 desc_shift = rx_desc->shift;
5382 skb_put(skb, urb->actual_length);
5383
5384 if (urb->status == 0) {
5385 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5386 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5387
5388 skb_pull(skb, drvinfo_sz + desc_shift);
5389
26f1fad2
JS		 5390 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5391
5392 if (rx_desc->phy_stats)
5393 rtl8xxxu_rx_parse_phystats(priv, rx_status,
5394 rx_desc, phy_stats);
5395
5396 rx_status->freq = hw->conf.chandef.chan->center_freq;
5397 rx_status->band = hw->conf.chandef.chan->band;
5398
5399 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5400 rx_status->flag |= RX_FLAG_MACTIME_START;
5401
5402 if (!rx_desc->swdec)
5403 rx_status->flag |= RX_FLAG_DECRYPTED;
5404 if (rx_desc->crc32)
5405 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5406 if (rx_desc->bw)
5407 rx_status->flag |= RX_FLAG_40MHZ;
5408
5409 if (rx_desc->rxht) {
5410 rx_status->flag |= RX_FLAG_HT;
5411 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5412 } else {
5413 rx_status->rate_idx = rx_desc->rxmcs;
5414 }
5415
5416 ieee80211_rx_irqsafe(hw, skb);
5417 skb = NULL;
5418 rx_urb->urb.context = NULL;
5419 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5420 } else {
5421 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5422 goto cleanup;
5423 }
5424 return;
5425
5426cleanup:
5427 usb_free_urb(urb);
5428 dev_kfree_skb(skb);
5429 return;
5430}
5431
5432static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5433 struct rtl8xxxu_rx_urb *rx_urb)
5434{
5435 struct sk_buff *skb;
5436 int skb_size;
5437 int ret;
5438
5439 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5440 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5441 if (!skb)
5442 return -ENOMEM;
5443
5444 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5445 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5446 skb_size, rtl8xxxu_rx_complete, skb);
5447 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5448 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5449 if (ret)
5450 usb_unanchor_urb(&rx_urb->urb);
5451 return ret;
5452}
5453
5454static void rtl8xxxu_int_complete(struct urb *urb)
5455{
5456 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5457 struct device *dev = &priv->udev->dev;
5458 int ret;
5459
5460 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5461 if (urb->status == 0) {
5462 usb_anchor_urb(urb, &priv->int_anchor);
5463 ret = usb_submit_urb(urb, GFP_ATOMIC);
5464 if (ret)
5465 usb_unanchor_urb(urb);
5466 } else {
5467 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5468 }
5469}
5470
5471
5472static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5473{
5474 struct rtl8xxxu_priv *priv = hw->priv;
5475 struct urb *urb;
5476 u32 val32;
5477 int ret;
5478
5479 urb = usb_alloc_urb(0, GFP_KERNEL);
5480 if (!urb)
5481 return -ENOMEM;
5482
5483 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5484 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5485 rtl8xxxu_int_complete, priv, 1);
5486 usb_anchor_urb(urb, &priv->int_anchor);
5487 ret = usb_submit_urb(urb, GFP_KERNEL);
5488 if (ret) {
5489 usb_unanchor_urb(urb);
5490 goto error;
5491 }
5492
5493 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5494 val32 |= USB_HIMR_CPWM;
5495 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5496
5497error:
5498 return ret;
5499}
5500
5501static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5502 struct ieee80211_vif *vif)
5503{
5504 struct rtl8xxxu_priv *priv = hw->priv;
5505 int ret;
5506 u8 val8;
5507
5508 switch (vif->type) {
5509 case NL80211_IFTYPE_STATION:
5510 rtl8723a_stop_tx_beacon(priv);
5511
5512 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5513 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5514 BEACON_DISABLE_TSF_UPDATE;
5515 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5516 ret = 0;
5517 break;
5518 default:
5519 ret = -EOPNOTSUPP;
5520 }
5521
5522 rtl8xxxu_set_linktype(priv, vif->type);
5523
5524 return ret;
5525}
5526
5527static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5528 struct ieee80211_vif *vif)
5529{
5530 struct rtl8xxxu_priv *priv = hw->priv;
5531
5532 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5533}
5534
5535static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5536{
5537 struct rtl8xxxu_priv *priv = hw->priv;
5538 struct device *dev = &priv->udev->dev;
5539 u16 val16;
5540 int ret = 0, channel;
5541 bool ht40;
5542
5543 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5544 dev_info(dev,
5545 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5546 __func__, hw->conf.chandef.chan->hw_value,
5547 changed, hw->conf.chandef.width);
5548
5549 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5550 val16 = ((hw->conf.long_frame_max_tx_count <<
5551 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5552 ((hw->conf.short_frame_max_tx_count <<
5553 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5554 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5555 }
5556
5557 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5558 switch (hw->conf.chandef.width) {
5559 case NL80211_CHAN_WIDTH_20_NOHT:
5560 case NL80211_CHAN_WIDTH_20:
5561 ht40 = false;
5562 break;
5563 case NL80211_CHAN_WIDTH_40:
5564 ht40 = true;
5565 break;
5566 default:
5567 ret = -ENOTSUPP;
5568 goto exit;
5569 }
5570
5571 channel = hw->conf.chandef.chan->hw_value;
5572
5573 rtl8723a_set_tx_power(priv, channel, ht40);
5574
5575 rtl8723au_config_channel(hw);
5576 }
5577
5578exit:
5579 return ret;
5580}
5581
5582static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5583 struct ieee80211_vif *vif, u16 queue,
5584 const struct ieee80211_tx_queue_params *param)
5585{
5586 struct rtl8xxxu_priv *priv = hw->priv;
5587 struct device *dev = &priv->udev->dev;
5588 u32 val32;
5589 u8 aifs, acm_ctrl, acm_bit;
5590
5591 aifs = param->aifs;
5592
5593 val32 = aifs |
5594 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5595 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5596 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5597
5598 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5599 dev_dbg(dev,
5600 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5601 __func__, queue, val32, param->acm, acm_ctrl);
5602
5603 switch (queue) {
5604 case IEEE80211_AC_VO:
5605 acm_bit = ACM_HW_CTRL_VO;
5606 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5607 break;
5608 case IEEE80211_AC_VI:
5609 acm_bit = ACM_HW_CTRL_VI;
5610 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5611 break;
5612 case IEEE80211_AC_BE:
5613 acm_bit = ACM_HW_CTRL_BE;
5614 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5615 break;
5616 case IEEE80211_AC_BK:
5617 acm_bit = ACM_HW_CTRL_BK;
5618 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5619 break;
5620 default:
5621 acm_bit = 0;
5622 break;
5623 }
5624
5625 if (param->acm)
5626 acm_ctrl |= acm_bit;
5627 else
5628 acm_ctrl &= ~acm_bit;
5629 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5630
5631 return 0;
5632}
5633
5634static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5635 unsigned int changed_flags,
5636 unsigned int *total_flags, u64 multicast)
5637{
5638 struct rtl8xxxu_priv *priv = hw->priv;
3bed4bfa 5639 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
26f1fad2
JS		 5640
5641 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5642 __func__, changed_flags, *total_flags);
5643
3bed4bfa
BR		 5644 /*
5645 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5646 */
5647
5648 if (*total_flags & FIF_FCSFAIL)
5649 rcr |= RCR_ACCEPT_CRC32;
5650 else
5651 rcr &= ~RCR_ACCEPT_CRC32;
5652
5653 /*
5654 * FIF_PLCPFAIL not supported?
5655 */
5656
5657 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5658 rcr &= ~RCR_CHECK_BSSID_BEACON;
5659 else
5660 rcr |= RCR_CHECK_BSSID_BEACON;
5661
5662 if (*total_flags & FIF_CONTROL)
5663 rcr |= RCR_ACCEPT_CTRL_FRAME;
5664 else
5665 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5666
5667 if (*total_flags & FIF_OTHER_BSS) {
5668 rcr |= RCR_ACCEPT_AP;
5669 rcr &= ~RCR_CHECK_BSSID_MATCH;
5670 } else {
5671 rcr &= ~RCR_ACCEPT_AP;
5672 rcr |= RCR_CHECK_BSSID_MATCH;
5673 }
5674
5675 if (*total_flags & FIF_PSPOLL)
5676 rcr |= RCR_ACCEPT_PM;
5677 else
5678 rcr &= ~RCR_ACCEPT_PM;
5679
5680 /*
5681 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5682 */
5683
5684 rtl8xxxu_write32(priv, REG_RCR, rcr);
5685
755bda11
JS		 5686 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5687 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5688 FIF_PROBE_REQ);
26f1fad2
JS		 5689}
5690
5691static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5692{
5693 if (rts > 2347)
5694 return -EINVAL;
5695
5696 return 0;
5697}
5698
5699static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5700 struct ieee80211_vif *vif,
5701 struct ieee80211_sta *sta,
5702 struct ieee80211_key_conf *key)
5703{
5704 struct rtl8xxxu_priv *priv = hw->priv;
5705 struct device *dev = &priv->udev->dev;
5706 u8 mac_addr[ETH_ALEN];
5707 u8 val8;
5708 u16 val16;
5709 u32 val32;
5710 int retval = -EOPNOTSUPP;
5711
5712 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5713 __func__, cmd, key->cipher, key->keyidx);
5714
5715 if (vif->type != NL80211_IFTYPE_STATION)
5716 return -EOPNOTSUPP;
5717
5718 if (key->keyidx > 3)
5719 return -EOPNOTSUPP;
5720
5721 switch (key->cipher) {
5722 case WLAN_CIPHER_SUITE_WEP40:
5723 case WLAN_CIPHER_SUITE_WEP104:
5724
5725 break;
5726 case WLAN_CIPHER_SUITE_CCMP:
5727 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5728 break;
5729 case WLAN_CIPHER_SUITE_TKIP:
5730 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5731 default:
5732 return -EOPNOTSUPP;
5733 }
5734
5735 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5736 dev_dbg(dev, "%s: pairwise key\n", __func__);
5737 ether_addr_copy(mac_addr, sta->addr);
5738 } else {
5739 dev_dbg(dev, "%s: group key\n", __func__);
5740 eth_broadcast_addr(mac_addr);
5741 }
5742
5743 val16 = rtl8xxxu_read16(priv, REG_CR);
5744 val16 |= CR_SECURITY_ENABLE;
5745 rtl8xxxu_write16(priv, REG_CR, val16);
5746
5747 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5748 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5749 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5750 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5751
5752 switch (cmd) {
5753 case SET_KEY:
5754 key->hw_key_idx = key->keyidx;
5755 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5756 rtl8xxxu_cam_write(priv, key, mac_addr);
5757 retval = 0;
5758 break;
5759 case DISABLE_KEY:
5760 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5761 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5762 key->keyidx << CAM_CMD_KEY_SHIFT;
5763 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5764 retval = 0;
5765 break;
5766 default:
5767 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5768 }
5769
5770 return retval;
5771}
5772
5773static int
5774rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 5775 struct ieee80211_ampdu_params *params)
26f1fad2
JS		 5776{
5777 struct rtl8xxxu_priv *priv = hw->priv;
5778 struct device *dev = &priv->udev->dev;
5779 u8 ampdu_factor, ampdu_density;
50ea05ef
SS		 5780 struct ieee80211_sta *sta = params->sta;
5781 enum ieee80211_ampdu_mlme_action action = params->action;
26f1fad2
JS		 5782
5783 switch (action) {
5784 case IEEE80211_AMPDU_TX_START:
5785 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5786 ampdu_factor = sta->ht_cap.ampdu_factor;
5787 ampdu_density = sta->ht_cap.ampdu_density;
5788 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5789 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5790 dev_dbg(dev,
5791 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5792 ampdu_factor, ampdu_density);
5793 break;
5794 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5795 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5796 rtl8xxxu_set_ampdu_factor(priv, 0);
5797 rtl8xxxu_set_ampdu_min_space(priv, 0);
5798 break;
5799 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5800 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5801 __func__);
5802 rtl8xxxu_set_ampdu_factor(priv, 0);
5803 rtl8xxxu_set_ampdu_min_space(priv, 0);
5804 break;
5805 case IEEE80211_AMPDU_RX_START:
5806 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5807 break;
5808 case IEEE80211_AMPDU_RX_STOP:
5809 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5810 break;
5811 default:
5812 break;
5813 }
5814 return 0;
5815}
5816
5817static int rtl8xxxu_start(struct ieee80211_hw *hw)
5818{
5819 struct rtl8xxxu_priv *priv = hw->priv;
5820 struct rtl8xxxu_rx_urb *rx_urb;
5821 struct rtl8xxxu_tx_urb *tx_urb;
5822 unsigned long flags;
5823 int ret, i;
5824
5825 ret = 0;
5826
5827 init_usb_anchor(&priv->rx_anchor);
5828 init_usb_anchor(&priv->tx_anchor);
5829 init_usb_anchor(&priv->int_anchor);
5830
5831 rtl8723a_enable_rf(priv);
0e28b975
JS		 5832 if (priv->usb_interrupts) {
5833 ret = rtl8xxxu_submit_int_urb(hw);
5834 if (ret)
5835 goto exit;
5836 }
26f1fad2
JS		 5837
5838 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5839 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5840 if (!tx_urb) {
5841 if (!i)
5842 ret = -ENOMEM;
5843
5844 goto error_out;
5845 }
5846 usb_init_urb(&tx_urb->urb);
5847 INIT_LIST_HEAD(&tx_urb->list);
5848 tx_urb->hw = hw;
5849 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5850 priv->tx_urb_free_count++;
5851 }
5852
5853 priv->tx_stopped = false;
5854
5855 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5856 priv->shutdown = false;
5857 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5858
5859 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5860 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5861 if (!rx_urb) {
5862 if (!i)
5863 ret = -ENOMEM;
5864
5865 goto error_out;
5866 }
5867 usb_init_urb(&rx_urb->urb);
5868 INIT_LIST_HEAD(&rx_urb->list);
5869 rx_urb->hw = hw;
5870
5871 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5872 }
5873exit:
5874 /*
c85ea115 5875 * Accept all data and mgmt frames
26f1fad2 5876 */
c85ea115 5877 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
26f1fad2
JS		 5878 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5879
5880 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5881
5882 return ret;
5883
5884error_out:
5885 rtl8xxxu_free_tx_resources(priv);
5886 /*
5887 * Disable all data and mgmt frames
5888 */
5889 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5890 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5891
5892 return ret;
5893}
5894
5895static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5896{
5897 struct rtl8xxxu_priv *priv = hw->priv;
5898 unsigned long flags;
5899
5900 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5901
5902 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5903 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5904
5905 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5906 priv->shutdown = true;
5907 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5908
5909 usb_kill_anchored_urbs(&priv->rx_anchor);
5910 usb_kill_anchored_urbs(&priv->tx_anchor);
0e28b975
JS		 5911 if (priv->usb_interrupts)
5912 usb_kill_anchored_urbs(&priv->int_anchor);
26f1fad2
JS		 5913
5914 rtl8723a_disable_rf(priv);
5915
5916 /*
5917 * Disable interrupts
5918 */
0e28b975
JS		 5919 if (priv->usb_interrupts)
5920 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
26f1fad2
JS		 5921
5922 rtl8xxxu_free_rx_resources(priv);
5923 rtl8xxxu_free_tx_resources(priv);
5924}
5925
5926static const struct ieee80211_ops rtl8xxxu_ops = {
5927 .tx = rtl8xxxu_tx,
5928 .add_interface = rtl8xxxu_add_interface,
5929 .remove_interface = rtl8xxxu_remove_interface,
5930 .config = rtl8xxxu_config,
5931 .conf_tx = rtl8xxxu_conf_tx,
5932 .bss_info_changed = rtl8xxxu_bss_info_changed,
5933 .configure_filter = rtl8xxxu_configure_filter,
5934 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5935 .start = rtl8xxxu_start,
5936 .stop = rtl8xxxu_stop,
5937 .sw_scan_start = rtl8xxxu_sw_scan_start,
5938 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5939 .set_key = rtl8xxxu_set_key,
5940 .ampdu_action = rtl8xxxu_ampdu_action,
5941};
5942
5943static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5944 struct usb_interface *interface)
5945{
5946 struct usb_interface_descriptor *interface_desc;
5947 struct usb_host_interface *host_interface;
5948 struct usb_endpoint_descriptor *endpoint;
5949 struct device *dev = &priv->udev->dev;
5950 int i, j = 0, endpoints;
5951 u8 dir, xtype, num;
5952 int ret = 0;
5953
5954 host_interface = &interface->altsetting[0];
5955 interface_desc = &host_interface->desc;
5956 endpoints = interface_desc->bNumEndpoints;
5957
5958 for (i = 0; i < endpoints; i++) {
5959 endpoint = &host_interface->endpoint[i].desc;
5960
5961 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5962 num = usb_endpoint_num(endpoint);
5963 xtype = usb_endpoint_type(endpoint);
5964 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5965 dev_dbg(dev,
5966 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5967 __func__, dir, num, xtype);
5968 if (usb_endpoint_dir_in(endpoint) &&
5969 usb_endpoint_xfer_bulk(endpoint)) {
5970 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5971 dev_dbg(dev, "%s: in endpoint num %i\n",
5972 __func__, num);
5973
5974 if (priv->pipe_in) {
5975 dev_warn(dev,
5976 "%s: Too many IN pipes\n", __func__);
5977 ret = -EINVAL;
5978 goto exit;
5979 }
5980
5981 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5982 }
5983
5984 if (usb_endpoint_dir_in(endpoint) &&
5985 usb_endpoint_xfer_int(endpoint)) {
5986 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5987 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5988 __func__, num);
5989
5990 if (priv->pipe_interrupt) {
5991 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5992 __func__);
5993 ret = -EINVAL;
5994 goto exit;
5995 }
5996
5997 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5998 }
5999
6000 if (usb_endpoint_dir_out(endpoint) &&
6001 usb_endpoint_xfer_bulk(endpoint)) {
6002 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
6003 dev_dbg(dev, "%s: out endpoint num %i\n",
6004 __func__, num);
6005 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
6006 dev_warn(dev,
6007 "%s: Too many OUT pipes\n", __func__);
6008 ret = -EINVAL;
6009 goto exit;
6010 }
6011 priv->out_ep[j++] = num;
6012 }
6013 }
6014exit:
6015 priv->nr_out_eps = j;
6016 return ret;
6017}
6018
6019static int rtl8xxxu_probe(struct usb_interface *interface,
6020 const struct usb_device_id *id)
6021{
6022 struct rtl8xxxu_priv *priv;
6023 struct ieee80211_hw *hw;
6024 struct usb_device *udev;
6025 struct ieee80211_supported_band *sband;
6026 int ret = 0;
6027 int untested = 1;
6028
6029 udev = usb_get_dev(interface_to_usbdev(interface));
6030
6031 switch (id->idVendor) {
6032 case USB_VENDOR_ID_REALTEK:
6033 switch(id->idProduct) {
6034 case 0x1724:
6035 case 0x8176:
6036 case 0x8178:
6037 case 0x817f:
6038 untested = 0;
6039 break;
6040 }
6041 break;
6042 case 0x7392:
6043 if (id->idProduct == 0x7811)
6044 untested = 0;
6045 break;
6046 default:
6047 break;
6048 }
6049
6050 if (untested) {
6051 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
6052 dev_info(&udev->dev,
6053 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6054 id->idVendor, id->idProduct);
6055 dev_info(&udev->dev,
6056 "Please report results to Jes.Sorensen@gmail.com\n");
6057 }
6058
6059 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6060 if (!hw) {
6061 ret = -ENOMEM;
6062 goto exit;
6063 }
6064
6065 priv = hw->priv;
6066 priv->hw = hw;
6067 priv->udev = udev;
6068 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6069 mutex_init(&priv->usb_buf_mutex);
6070 mutex_init(&priv->h2c_mutex);
6071 INIT_LIST_HEAD(&priv->tx_urb_free_list);
6072 spin_lock_init(&priv->tx_urb_lock);
6073 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6074 spin_lock_init(&priv->rx_urb_lock);
6075 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6076
6077 usb_set_intfdata(interface, hw);
6078
6079 ret = rtl8xxxu_parse_usb(priv, interface);
6080 if (ret)
6081 goto exit;
6082
6083 ret = rtl8xxxu_identify_chip(priv);
6084 if (ret) {
6085 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6086 goto exit;
6087 }
6088
6089 ret = rtl8xxxu_read_efuse(priv);
6090 if (ret) {
6091 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6092 goto exit;
6093 }
6094
6095 ret = priv->fops->parse_efuse(priv);
6096 if (ret) {
6097 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6098 goto exit;
6099 }
6100
6101 rtl8xxxu_print_chipinfo(priv);
6102
6103 ret = priv->fops->load_firmware(priv);
6104 if (ret) {
6105 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6106 goto exit;
6107 }
6108
6109 ret = rtl8xxxu_init_device(hw);
6110
6111 hw->wiphy->max_scan_ssids = 1;
6112 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6113 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6114 hw->queues = 4;
6115
6116 sband = &rtl8xxxu_supported_band;
6117 sband->ht_cap.ht_supported = true;
6118 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6119 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6120 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6121 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6122 sband->ht_cap.mcs.rx_mask[0] = 0xff;
6123 sband->ht_cap.mcs.rx_mask[4] = 0x01;
6124 if (priv->rf_paths > 1) {
6125 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6126 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6127 }
6128 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6129 /*
6130 * Some APs will negotiate HT20_40 in a noisy environment leading
6131 * to miserable performance. Rather than defaulting to this, only
6132 * enable it if explicitly requested at module load time.
6133 */
6134 if (rtl8xxxu_ht40_2g) {
6135 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6136 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6137 }
6138 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
6139
6140 hw->wiphy->rts_threshold = 2347;
6141
6142 SET_IEEE80211_DEV(priv->hw, &interface->dev);
6143 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6144
6145 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
6146 ieee80211_hw_set(hw, SIGNAL_DBM);
6147 /*
6148 * The firmware handles rate control
6149 */
6150 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6151 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6152
6153 ret = ieee80211_register_hw(priv->hw);
6154 if (ret) {
6155 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6156 __func__, ret);
6157 goto exit;
6158 }
6159
6160exit:
6161 if (ret < 0)
6162 usb_put_dev(udev);
6163 return ret;
6164}
6165
6166static void rtl8xxxu_disconnect(struct usb_interface *interface)
6167{
6168 struct rtl8xxxu_priv *priv;
6169 struct ieee80211_hw *hw;
6170
6171 hw = usb_get_intfdata(interface);
6172 priv = hw->priv;
6173
6174 rtl8xxxu_disable_device(hw);
6175 usb_set_intfdata(interface, NULL);
6176
6177 dev_info(&priv->udev->dev, "disconnecting\n");
6178
6179 ieee80211_unregister_hw(hw);
6180
6181 kfree(priv->fw_data);
6182 mutex_destroy(&priv->usb_buf_mutex);
6183 mutex_destroy(&priv->h2c_mutex);
6184
6185 usb_put_dev(priv->udev);
6186 ieee80211_free_hw(hw);
6187}
6188
6189static struct rtl8xxxu_fileops rtl8723au_fops = {
6190 .parse_efuse = rtl8723au_parse_efuse,
6191 .load_firmware = rtl8723au_load_firmware,
6192 .power_on = rtl8723au_power_on,
74b99bed 6193 .llt_init = rtl8xxxu_init_llt_table,
26f1fad2
JS		 6194 .writeN_block_size = 1024,
6195};
6196
35a741fe 6197static struct rtl8xxxu_fileops rtl8723bu_fops = {
3c836d60 6198 .parse_efuse = rtl8723bu_parse_efuse,
35a741fe
JS		 6199 .load_firmware = rtl8723bu_load_firmware,
6200 .power_on = rtl8723au_power_on,
6201 .llt_init = rtl8xxxu_auto_llt_table,
adfc0124 6202 .writeN_block_size = 1024,
35a741fe
JS		 6203};
6204
c0963772
KV		 6205#ifdef CONFIG_RTL8XXXU_UNTESTED
6206
26f1fad2
JS		 6207static struct rtl8xxxu_fileops rtl8192cu_fops = {
6208 .parse_efuse = rtl8192cu_parse_efuse,
6209 .load_firmware = rtl8192cu_load_firmware,
6210 .power_on = rtl8192cu_power_on,
74b99bed 6211 .llt_init = rtl8xxxu_init_llt_table,
26f1fad2
JS		 6212 .writeN_block_size = 128,
6213};
6214
c0963772
KV		 6215#endif
6216
3307d840
JS		 6217static struct rtl8xxxu_fileops rtl8192eu_fops = {
6218 .parse_efuse = rtl8192eu_parse_efuse,
6219 .load_firmware = rtl8192eu_load_firmware,
c05a9dbf 6220 .power_on = rtl8192eu_power_on,
74b99bed 6221 .llt_init = rtl8xxxu_auto_llt_table,
c05a9dbf 6222 .writeN_block_size = 128,
3307d840
JS		 6223};
6224
26f1fad2
JS		 6225static struct usb_device_id dev_table[] = {
6226{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6227 .driver_info = (unsigned long)&rtl8723au_fops},
6228{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6229 .driver_info = (unsigned long)&rtl8723au_fops},
6230{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6231 .driver_info = (unsigned long)&rtl8723au_fops},
3307d840
JS		 6232{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6233 .driver_info = (unsigned long)&rtl8192eu_fops},
35a741fe
JS		 6234{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6235 .driver_info = (unsigned long)&rtl8723bu_fops},
033695bd
KV		 6236#ifdef CONFIG_RTL8XXXU_UNTESTED
6237/* Still supported by rtlwifi */
26f1fad2
JS		 6238{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6239 .driver_info = (unsigned long)&rtl8192cu_fops},
6240{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6241 .driver_info = (unsigned long)&rtl8192cu_fops},
6242{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6243 .driver_info = (unsigned long)&rtl8192cu_fops},
6244/* Tested by Larry Finger */
6245{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6246 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 6247/* Currently untested 8188 series devices */
6248{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6249 .driver_info = (unsigned long)&rtl8192cu_fops},
6250{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6251 .driver_info = (unsigned long)&rtl8192cu_fops},
6252{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6253 .driver_info = (unsigned long)&rtl8192cu_fops},
6254{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6255 .driver_info = (unsigned long)&rtl8192cu_fops},
6256{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6257 .driver_info = (unsigned long)&rtl8192cu_fops},
6258{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6259 .driver_info = (unsigned long)&rtl8192cu_fops},
6260{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6261 .driver_info = (unsigned long)&rtl8192cu_fops},
6262{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6263 .driver_info = (unsigned long)&rtl8192cu_fops},
6264{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6265 .driver_info = (unsigned long)&rtl8192cu_fops},
6266{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6267 .driver_info = (unsigned long)&rtl8192cu_fops},
6268{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6269 .driver_info = (unsigned long)&rtl8192cu_fops},
6270{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6271 .driver_info = (unsigned long)&rtl8192cu_fops},
6272{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6273 .driver_info = (unsigned long)&rtl8192cu_fops},
6274{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6275 .driver_info = (unsigned long)&rtl8192cu_fops},
6276{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6277 .driver_info = (unsigned long)&rtl8192cu_fops},
6278{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6279 .driver_info = (unsigned long)&rtl8192cu_fops},
6280{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6281 .driver_info = (unsigned long)&rtl8192cu_fops},
6282{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6283 .driver_info = (unsigned long)&rtl8192cu_fops},
6284{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6285 .driver_info = (unsigned long)&rtl8192cu_fops},
6286{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6287 .driver_info = (unsigned long)&rtl8192cu_fops},
6288{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6289 .driver_info = (unsigned long)&rtl8192cu_fops},
6290{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6291 .driver_info = (unsigned long)&rtl8192cu_fops},
6292{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6293 .driver_info = (unsigned long)&rtl8192cu_fops},
6294{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6295 .driver_info = (unsigned long)&rtl8192cu_fops},
6296{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6297 .driver_info = (unsigned long)&rtl8192cu_fops},
6298{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6299 .driver_info = (unsigned long)&rtl8192cu_fops},
6300{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6301 .driver_info = (unsigned long)&rtl8192cu_fops},
6302{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6303 .driver_info = (unsigned long)&rtl8192cu_fops},
6304{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6305 .driver_info = (unsigned long)&rtl8192cu_fops},
6306{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6307 .driver_info = (unsigned long)&rtl8192cu_fops},
6308{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6309 .driver_info = (unsigned long)&rtl8192cu_fops},
6310{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6311 .driver_info = (unsigned long)&rtl8192cu_fops},
6312{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6313 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 6314{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6315 .driver_info = (unsigned long)&rtl8192cu_fops},
6316{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6317 .driver_info = (unsigned long)&rtl8192cu_fops},
6318{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6319 .driver_info = (unsigned long)&rtl8192cu_fops},
6320{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6321 .driver_info = (unsigned long)&rtl8192cu_fops},
6322{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6323 .driver_info = (unsigned long)&rtl8192cu_fops},
6324{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6325 .driver_info = (unsigned long)&rtl8192cu_fops},
6326{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6327 .driver_info = (unsigned long)&rtl8192cu_fops},
6328/* Currently untested 8192 series devices */
6329{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6330 .driver_info = (unsigned long)&rtl8192cu_fops},
6331{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6332 .driver_info = (unsigned long)&rtl8192cu_fops},
6333{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6334 .driver_info = (unsigned long)&rtl8192cu_fops},
6335{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6336 .driver_info = (unsigned long)&rtl8192cu_fops},
6337{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6338 .driver_info = (unsigned long)&rtl8192cu_fops},
6339{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6340 .driver_info = (unsigned long)&rtl8192cu_fops},
6341{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6342 .driver_info = (unsigned long)&rtl8192cu_fops},
6343{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6344 .driver_info = (unsigned long)&rtl8192cu_fops},
6345{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6346 .driver_info = (unsigned long)&rtl8192cu_fops},
6347{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6348 .driver_info = (unsigned long)&rtl8192cu_fops},
6349{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6350 .driver_info = (unsigned long)&rtl8192cu_fops},
6351{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6352 .driver_info = (unsigned long)&rtl8192cu_fops},
6353{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6354 .driver_info = (unsigned long)&rtl8192cu_fops},
6355{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6356 .driver_info = (unsigned long)&rtl8192cu_fops},
6357{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6358 .driver_info = (unsigned long)&rtl8192cu_fops},
6359{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6360 .driver_info = (unsigned long)&rtl8192cu_fops},
6361{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6362 .driver_info = (unsigned long)&rtl8192cu_fops},
6363{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6364 .driver_info = (unsigned long)&rtl8192cu_fops},
6365{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6366 .driver_info = (unsigned long)&rtl8192cu_fops},
6367{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6368 .driver_info = (unsigned long)&rtl8192cu_fops},
6369{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6370 .driver_info = (unsigned long)&rtl8192cu_fops},
6371{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6372 .driver_info = (unsigned long)&rtl8192cu_fops},
6373{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6374 .driver_info = (unsigned long)&rtl8192cu_fops},
6375{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6376 .driver_info = (unsigned long)&rtl8192cu_fops},
6377{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6378 .driver_info = (unsigned long)&rtl8192cu_fops},
6379#endif
6380{ }
6381};
6382
6383static struct usb_driver rtl8xxxu_driver = {
6384 .name = DRIVER_NAME,
6385 .probe = rtl8xxxu_probe,
6386 .disconnect = rtl8xxxu_disconnect,
6387 .id_table = dev_table,
6388 .disable_hub_initiated_lpm = 1,
6389};
6390
6391static int __init rtl8xxxu_module_init(void)
6392{
6393 int res;
6394
6395 res = usb_register(&rtl8xxxu_driver);
6396 if (res < 0)
6397 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6398
6399 return res;
6400}
6401
6402static void __exit rtl8xxxu_module_exit(void)
6403{
6404 usb_deregister(&rtl8xxxu_driver);
6405}
6406
6407
6408MODULE_DEVICE_TABLE(usb, dev_table);
6409
6410module_init(rtl8xxxu_module_init);
6411module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
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