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rtl8xxxu: Set 8723bu TX power for CCK and OFDM rates
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
CommitLineData
26f1fad2
JS		 1/*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
3307d840 45static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
b001e086 57MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
35a741fe
JS		 58MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
26f1fad2
JS		 60
61module_param_named(debug, rtl8xxxu_debug, int, 0600);
62MODULE_PARM_DESC(debug, "Set debug mask");
63module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66#define USB_VENDOR_ID_REALTEK 0x0bda
67/* Minimum IEEE80211_MAX_FRAME_LEN */
68#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69#define RTL8XXXU_RX_URBS 32
70#define RTL8XXXU_RX_URB_PENDING_WATER 8
71#define RTL8XXXU_TX_URBS 64
72#define RTL8XXXU_TX_URB_LOW_WATER 25
73#define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91};
92
93static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
95 .hw_value = 1, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
97 .hw_value = 2, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
99 .hw_value = 3, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
101 .hw_value = 4, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
103 .hw_value = 5, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
105 .hw_value = 6, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
107 .hw_value = 7, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
109 .hw_value = 8, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
111 .hw_value = 9, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
113 .hw_value = 10, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
115 .hw_value = 11, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
117 .hw_value = 12, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
119 .hw_value = 13, .max_power = 30 },
120 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
121 .hw_value = 14, .max_power = 30 }
122};
123
124static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129};
130
131static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154};
155
b7dd8ff9
JS		 156static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185};
186
26f1fad2
JS		 187static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
188 {0x800, 0x80040000}, {0x804, 0x00000003},
189 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
190 {0x810, 0x10001331}, {0x814, 0x020c3d10},
191 {0x818, 0x02200385}, {0x81c, 0x00000000},
192 {0x820, 0x01000100}, {0x824, 0x00390004},
193 {0x828, 0x00000000}, {0x82c, 0x00000000},
194 {0x830, 0x00000000}, {0x834, 0x00000000},
195 {0x838, 0x00000000}, {0x83c, 0x00000000},
196 {0x840, 0x00010000}, {0x844, 0x00000000},
197 {0x848, 0x00000000}, {0x84c, 0x00000000},
198 {0x850, 0x00000000}, {0x854, 0x00000000},
199 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
200 {0x860, 0x66f60110}, {0x864, 0x061f0130},
201 {0x868, 0x00000000}, {0x86c, 0x32323200},
202 {0x870, 0x07000760}, {0x874, 0x22004000},
203 {0x878, 0x00000808}, {0x87c, 0x00000000},
204 {0x880, 0xc0083070}, {0x884, 0x000004d5},
205 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
206 {0x890, 0x00000800}, {0x894, 0xfffffffe},
207 {0x898, 0x40302010}, {0x89c, 0x00706050},
208 {0x900, 0x00000000}, {0x904, 0x00000023},
209 {0x908, 0x00000000}, {0x90c, 0x81121111},
210 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
211 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
212 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
213 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
214 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
215 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
216 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
217 {0xa78, 0x00000900},
218 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
219 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
220 {0xc10, 0x08800000}, {0xc14, 0x40000100},
221 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
222 {0xc20, 0x00000000}, {0xc24, 0x00000000},
223 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
224 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
225 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
226 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
227 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
228 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
229 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
230 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
231 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
232 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
233 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
234 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
235 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
236 {0xc90, 0x00121820}, {0xc94, 0x00000000},
237 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
238 {0xca0, 0x00000000}, {0xca4, 0x00000080},
239 {0xca8, 0x00000000}, {0xcac, 0x00000000},
240 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
241 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
242 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
243 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
244 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
245 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
246 {0xce0, 0x00222222}, {0xce4, 0x00000000},
247 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
248 {0xd00, 0x00080740}, {0xd04, 0x00020401},
249 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
250 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
251 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
252 {0xd30, 0x00000000}, {0xd34, 0x80608000},
253 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
254 {0xd40, 0x00000000}, {0xd44, 0x00000000},
255 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
256 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
257 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
258 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
259 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
260 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
261 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
262 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
263 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
264 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
265 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
266 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
267 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
268 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
269 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
270 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
271 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
272 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
273 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
274 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
275 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
276 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
277 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
278 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
279 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
280 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
281 {0xf00, 0x00000300},
282 {0xffff, 0xffffffff},
283};
284
36c32588
JS		 285static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
286 {0x800, 0x80040000}, {0x804, 0x00000003},
287 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
288 {0x810, 0x10001331}, {0x814, 0x020c3d10},
289 {0x818, 0x02200385}, {0x81c, 0x00000000},
290 {0x820, 0x01000100}, {0x824, 0x00190204},
291 {0x828, 0x00000000}, {0x82c, 0x00000000},
292 {0x830, 0x00000000}, {0x834, 0x00000000},
293 {0x838, 0x00000000}, {0x83c, 0x00000000},
294 {0x840, 0x00010000}, {0x844, 0x00000000},
295 {0x848, 0x00000000}, {0x84c, 0x00000000},
296 {0x850, 0x00000000}, {0x854, 0x00000000},
297 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
298 {0x860, 0x66f60110}, {0x864, 0x061f0649},
299 {0x868, 0x00000000}, {0x86c, 0x27272700},
300 {0x870, 0x07000760}, {0x874, 0x25004000},
301 {0x878, 0x00000808}, {0x87c, 0x00000000},
302 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
303 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
304 {0x890, 0x00000800}, {0x894, 0xfffffffe},
305 {0x898, 0x40302010}, {0x89c, 0x00706050},
306 {0x900, 0x00000000}, {0x904, 0x00000023},
307 {0x908, 0x00000000}, {0x90c, 0x81121111},
308 {0x910, 0x00000002}, {0x914, 0x00000201},
309 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
310 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
311 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
312 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
313 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
314 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
315 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
316 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
317 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
318 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
319 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
320 {0xc10, 0x08800000}, {0xc14, 0x40000100},
321 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
322 {0xc20, 0x00000000}, {0xc24, 0x00000000},
323 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
324 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
325 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
326 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
327 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
328 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
329 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
330 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
331 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
332 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
333 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
334 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
335 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
336 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
337 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
338 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
339 {0xca8, 0x00000000}, {0xcac, 0x00000000},
340 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
341 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
342 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
343 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
344 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
345 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
346 {0xce0, 0x00222222}, {0xce4, 0x00000000},
347 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
348 {0xd00, 0x00000740}, {0xd04, 0x40020401},
349 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
350 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
351 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
352 {0xd30, 0x00000000}, {0xd34, 0x80608000},
353 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
354 {0xd40, 0x00000000}, {0xd44, 0x00000000},
355 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
356 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
357 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
358 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
359 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
360 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
361 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
362 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
363 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
364 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
365 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
366 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
367 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
368 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
369 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
370 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
371 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
372 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
373 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
374 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
375 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
376 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
377 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
378 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
379 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
380 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
381 {0xf00, 0x00000300},
382 {0x820, 0x01000100}, {0x800, 0x83040000},
383 {0xffff, 0xffffffff},
384};
385
26f1fad2
JS		 386static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
387 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
388 {0x800, 0x80040002}, {0x804, 0x00000003},
389 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
390 {0x810, 0x10000330}, {0x814, 0x020c3d10},
391 {0x818, 0x02200385}, {0x81c, 0x00000000},
392 {0x820, 0x01000100}, {0x824, 0x00390004},
393 {0x828, 0x01000100}, {0x82c, 0x00390004},
394 {0x830, 0x27272727}, {0x834, 0x27272727},
395 {0x838, 0x27272727}, {0x83c, 0x27272727},
396 {0x840, 0x00010000}, {0x844, 0x00010000},
397 {0x848, 0x27272727}, {0x84c, 0x27272727},
398 {0x850, 0x00000000}, {0x854, 0x00000000},
399 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
400 {0x860, 0x66e60230}, {0x864, 0x061f0130},
401 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
402 {0x870, 0x07000700}, {0x874, 0x22184000},
403 {0x878, 0x08080808}, {0x87c, 0x00000000},
404 {0x880, 0xc0083070}, {0x884, 0x000004d5},
405 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
406 {0x890, 0x00000800}, {0x894, 0xfffffffe},
407 {0x898, 0x40302010}, {0x89c, 0x00706050},
408 {0x900, 0x00000000}, {0x904, 0x00000023},
409 {0x908, 0x00000000}, {0x90c, 0x81121313},
410 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
411 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
412 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
413 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
414 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
415 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
416 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
417 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
418 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
419 {0xc10, 0x08800000}, {0xc14, 0x40000100},
420 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
421 {0xc20, 0x00000000}, {0xc24, 0x00000000},
422 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
423 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
424 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
425 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
426 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
427 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
428 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
429 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
430 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
431 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
432 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
433 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
434 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
435 {0xc90, 0x00121820}, {0xc94, 0x00000000},
436 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
437 {0xca0, 0x00000000}, {0xca4, 0x00000080},
438 {0xca8, 0x00000000}, {0xcac, 0x00000000},
439 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
440 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
441 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
442 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
443 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
444 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
445 {0xce0, 0x00222222}, {0xce4, 0x00000000},
446 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
447 {0xd00, 0x00080740}, {0xd04, 0x00020403},
448 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
449 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
450 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
451 {0xd30, 0x00000000}, {0xd34, 0x80608000},
452 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
453 {0xd40, 0x00000000}, {0xd44, 0x00000000},
454 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
455 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
456 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
457 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
458 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
459 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
460 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
461 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
462 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
463 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
464 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
465 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
466 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
467 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
468 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
469 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
470 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
471 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
472 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
473 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
474 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
475 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
476 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
477 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
478 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
479 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
480 {0xf00, 0x00000300},
481 {0xffff, 0xffffffff},
482};
483
484static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
485 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
486 {0x040, 0x000c0004}, {0x800, 0x80040000},
487 {0x804, 0x00000001}, {0x808, 0x0000fc00},
488 {0x80c, 0x0000000a}, {0x810, 0x10005388},
489 {0x814, 0x020c3d10}, {0x818, 0x02200385},
490 {0x81c, 0x00000000}, {0x820, 0x01000100},
491 {0x824, 0x00390204}, {0x828, 0x00000000},
492 {0x82c, 0x00000000}, {0x830, 0x00000000},
493 {0x834, 0x00000000}, {0x838, 0x00000000},
494 {0x83c, 0x00000000}, {0x840, 0x00010000},
495 {0x844, 0x00000000}, {0x848, 0x00000000},
496 {0x84c, 0x00000000}, {0x850, 0x00000000},
497 {0x854, 0x00000000}, {0x858, 0x569a569a},
498 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
499 {0x864, 0x061f0130}, {0x868, 0x00000000},
500 {0x86c, 0x20202000}, {0x870, 0x03000300},
501 {0x874, 0x22004000}, {0x878, 0x00000808},
502 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
503 {0x884, 0x000004d5}, {0x888, 0x00000000},
504 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
505 {0x894, 0xfffffffe}, {0x898, 0x40302010},
506 {0x89c, 0x00706050}, {0x900, 0x00000000},
507 {0x904, 0x00000023}, {0x908, 0x00000000},
508 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
509 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
510 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
511 {0xa14, 0x11144028}, {0xa18, 0x00881117},
512 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
513 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
514 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
515 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
516 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
517 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
518 {0xc14, 0x40000100}, {0xc18, 0x08800000},
519 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
520 {0xc24, 0x00000000}, {0xc28, 0x00000000},
521 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
522 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
523 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
524 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
525 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
526 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
527 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
528 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
529 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
530 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
531 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
532 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
533 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
534 {0xc94, 0x00000000}, {0xc98, 0x00121820},
535 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
536 {0xca4, 0x00000080}, {0xca8, 0x00000000},
537 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
538 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
539 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
540 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
541 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
542 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
543 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
544 {0xce4, 0x00000000}, {0xce8, 0x37644302},
545 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
546 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
547 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
548 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
549 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
550 {0xd34, 0x80608000}, {0xd38, 0x00000000},
551 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
552 {0xd44, 0x00000000}, {0xd48, 0x00000000},
553 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
554 {0xd54, 0x00000000}, {0xd58, 0x00000000},
555 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
556 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
557 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
558 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
559 {0xe00, 0x24242424}, {0xe04, 0x24242424},
560 {0xe08, 0x03902024}, {0xe10, 0x24242424},
561 {0xe14, 0x24242424}, {0xe18, 0x24242424},
562 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
563 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
564 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
565 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
566 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
567 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
568 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
569 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
570 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
571 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
572 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
573 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
574 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
575 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
576 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
577 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
578 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
579 {0xf00, 0x00000300},
580 {0xffff, 0xffffffff},
581};
582
583static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
584 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
585 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
586 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
587 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
588 {0xc78, 0x78080001}, {0xc78, 0x77090001},
589 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
590 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
591 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
592 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
593 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
594 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
595 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
596 {0xc78, 0x68180001}, {0xc78, 0x67190001},
597 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
598 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
599 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
600 {0xc78, 0x60200001}, {0xc78, 0x49210001},
601 {0xc78, 0x48220001}, {0xc78, 0x47230001},
602 {0xc78, 0x46240001}, {0xc78, 0x45250001},
603 {0xc78, 0x44260001}, {0xc78, 0x43270001},
604 {0xc78, 0x42280001}, {0xc78, 0x41290001},
605 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
606 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
607 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
608 {0xc78, 0x21300001}, {0xc78, 0x20310001},
609 {0xc78, 0x06320001}, {0xc78, 0x05330001},
610 {0xc78, 0x04340001}, {0xc78, 0x03350001},
611 {0xc78, 0x02360001}, {0xc78, 0x01370001},
612 {0xc78, 0x00380001}, {0xc78, 0x00390001},
613 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
614 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
615 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
616 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
617 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
618 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
619 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
620 {0xc78, 0x78480001}, {0xc78, 0x77490001},
621 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
622 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
623 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
624 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
625 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
626 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
627 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
628 {0xc78, 0x68580001}, {0xc78, 0x67590001},
629 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
630 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
631 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
632 {0xc78, 0x60600001}, {0xc78, 0x49610001},
633 {0xc78, 0x48620001}, {0xc78, 0x47630001},
634 {0xc78, 0x46640001}, {0xc78, 0x45650001},
635 {0xc78, 0x44660001}, {0xc78, 0x43670001},
636 {0xc78, 0x42680001}, {0xc78, 0x41690001},
637 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
638 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
639 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
640 {0xc78, 0x21700001}, {0xc78, 0x20710001},
641 {0xc78, 0x06720001}, {0xc78, 0x05730001},
642 {0xc78, 0x04740001}, {0xc78, 0x03750001},
643 {0xc78, 0x02760001}, {0xc78, 0x01770001},
644 {0xc78, 0x00780001}, {0xc78, 0x00790001},
645 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
646 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
647 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
648 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
649 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
650 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
651 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
652 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
653 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
654 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
655 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
656 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
657 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
658 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
659 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
660 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
661 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
662 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
663 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
664 {0xffff, 0xffffffff}
665};
666
667static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
668 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
669 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
670 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
671 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
672 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
673 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
674 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
675 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
676 {0xc78, 0x73100001}, {0xc78, 0x72110001},
677 {0xc78, 0x71120001}, {0xc78, 0x70130001},
678 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
679 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
680 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
681 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
682 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
683 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
684 {0xc78, 0x63200001}, {0xc78, 0x62210001},
685 {0xc78, 0x61220001}, {0xc78, 0x60230001},
686 {0xc78, 0x46240001}, {0xc78, 0x45250001},
687 {0xc78, 0x44260001}, {0xc78, 0x43270001},
688 {0xc78, 0x42280001}, {0xc78, 0x41290001},
689 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
690 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
691 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
692 {0xc78, 0x21300001}, {0xc78, 0x20310001},
693 {0xc78, 0x06320001}, {0xc78, 0x05330001},
694 {0xc78, 0x04340001}, {0xc78, 0x03350001},
695 {0xc78, 0x02360001}, {0xc78, 0x01370001},
696 {0xc78, 0x00380001}, {0xc78, 0x00390001},
697 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
698 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
699 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
700 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
701 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
702 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
703 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
704 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
705 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
706 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
707 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
708 {0xc78, 0x73500001}, {0xc78, 0x72510001},
709 {0xc78, 0x71520001}, {0xc78, 0x70530001},
710 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
711 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
712 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
713 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
714 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
715 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
716 {0xc78, 0x63600001}, {0xc78, 0x62610001},
717 {0xc78, 0x61620001}, {0xc78, 0x60630001},
718 {0xc78, 0x46640001}, {0xc78, 0x45650001},
719 {0xc78, 0x44660001}, {0xc78, 0x43670001},
720 {0xc78, 0x42680001}, {0xc78, 0x41690001},
721 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
722 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
723 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
724 {0xc78, 0x21700001}, {0xc78, 0x20710001},
725 {0xc78, 0x06720001}, {0xc78, 0x05730001},
726 {0xc78, 0x04740001}, {0xc78, 0x03750001},
727 {0xc78, 0x02760001}, {0xc78, 0x01770001},
728 {0xc78, 0x00780001}, {0xc78, 0x00790001},
729 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
730 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
731 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
732 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
733 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
734 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
735 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
736 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
737 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
738 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
739 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
740 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
741 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
742 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
743 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
744 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
745 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
746 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
747 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
748 {0xffff, 0xffffffff}
749};
750
b9f498e1
JS		 751static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
752 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
753 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
754 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
755 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
756 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
757 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
758 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
759 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
760 {0xc78, 0xed100001}, {0xc78, 0xec110001},
761 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
762 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
763 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
764 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
765 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
766 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
767 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
768 {0xc78, 0x65200001}, {0xc78, 0x64210001},
769 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
770 {0xc78, 0x49240001}, {0xc78, 0x48250001},
771 {0xc78, 0x47260001}, {0xc78, 0x46270001},
772 {0xc78, 0x45280001}, {0xc78, 0x44290001},
773 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
774 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
775 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
776 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
777 {0xc78, 0x08320001}, {0xc78, 0x07330001},
778 {0xc78, 0x06340001}, {0xc78, 0x05350001},
779 {0xc78, 0x04360001}, {0xc78, 0x03370001},
780 {0xc78, 0x02380001}, {0xc78, 0x01390001},
781 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
782 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
783 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
784 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
785 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
786 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
787 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
788 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
789 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
790 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
791 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
792 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
793 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
794 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
795 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
796 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
797 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
798 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
799 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
800 {0xc78, 0x65600001}, {0xc78, 0x64610001},
801 {0xc78, 0x63620001}, {0xc78, 0x62630001},
802 {0xc78, 0x61640001}, {0xc78, 0x48650001},
803 {0xc78, 0x47660001}, {0xc78, 0x46670001},
804 {0xc78, 0x45680001}, {0xc78, 0x44690001},
805 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
806 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
807 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
808 {0xc78, 0x24700001}, {0xc78, 0x09710001},
809 {0xc78, 0x08720001}, {0xc78, 0x07730001},
810 {0xc78, 0x06740001}, {0xc78, 0x05750001},
811 {0xc78, 0x04760001}, {0xc78, 0x03770001},
812 {0xc78, 0x02780001}, {0xc78, 0x01790001},
813 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
814 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
815 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
816 {0xc50, 0x69553422},
817 {0xc50, 0x69553420},
818 {0x824, 0x00390204},
819 {0xffff, 0xffffffff}
820};
821
26f1fad2
JS		 822static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
823 {0x00, 0x00030159}, {0x01, 0x00031284},
824 {0x02, 0x00098000}, {0x03, 0x00039c63},
825 {0x04, 0x000210e7}, {0x09, 0x0002044f},
826 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
827 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
828 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
829 {0x19, 0x00000000}, {0x1a, 0x00030355},
830 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
831 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
832 {0x1f, 0x00000000}, {0x20, 0x0000b614},
833 {0x21, 0x0006c000}, {0x22, 0x00000000},
834 {0x23, 0x00001558}, {0x24, 0x00000060},
835 {0x25, 0x00000483}, {0x26, 0x0004f000},
836 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
837 {0x29, 0x00004783}, {0x2a, 0x00000001},
838 {0x2b, 0x00021334}, {0x2a, 0x00000000},
839 {0x2b, 0x00000054}, {0x2a, 0x00000001},
840 {0x2b, 0x00000808}, {0x2b, 0x00053333},
841 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
842 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
843 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
844 {0x2b, 0x00000808}, {0x2b, 0x00063333},
845 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
846 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
847 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
848 {0x2b, 0x00000808}, {0x2b, 0x00073333},
849 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
850 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
851 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
852 {0x2b, 0x00000709}, {0x2b, 0x00063333},
853 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
854 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
855 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
856 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
857 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
858 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
859 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
860 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
861 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
862 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
863 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
864 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
865 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
866 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
867 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
868 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
869 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
870 {0x10, 0x0002000f}, {0x11, 0x000203f9},
871 {0x10, 0x0003000f}, {0x11, 0x000ff500},
872 {0x10, 0x00000000}, {0x11, 0x00000000},
873 {0x10, 0x0008000f}, {0x11, 0x0003f100},
874 {0x10, 0x0009000f}, {0x11, 0x00023100},
875 {0x12, 0x00032000}, {0x12, 0x00071000},
876 {0x12, 0x000b0000}, {0x12, 0x000fc000},
877 {0x13, 0x000287b3}, {0x13, 0x000244b7},
878 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
879 {0x13, 0x00018493}, {0x13, 0x0001429b},
880 {0x13, 0x00010299}, {0x13, 0x0000c29c},
881 {0x13, 0x000081a0}, {0x13, 0x000040ac},
882 {0x13, 0x00000020}, {0x14, 0x0001944c},
883 {0x14, 0x00059444}, {0x14, 0x0009944c},
884 {0x14, 0x000d9444}, {0x15, 0x0000f474},
885 {0x15, 0x0004f477}, {0x15, 0x0008f455},
886 {0x15, 0x000cf455}, {0x16, 0x00000339},
887 {0x16, 0x00040339}, {0x16, 0x00080339},
888 {0x16, 0x000c0366}, {0x00, 0x00010159},
889 {0x18, 0x0000f401}, {0xfe, 0x00000000},
890 {0xfe, 0x00000000}, {0x1f, 0x00000003},
891 {0xfe, 0x00000000}, {0xfe, 0x00000000},
892 {0x1e, 0x00000247}, {0x1f, 0x00000000},
893 {0x00, 0x00030159},
894 {0xff, 0xffffffff}
895};
896
22a31d45
JS		 897static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
898 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
899 {0xfe, 0x00000000}, {0xfe, 0x00000000},
900 {0xfe, 0x00000000}, {0xb1, 0x00000018},
901 {0xfe, 0x00000000}, {0xfe, 0x00000000},
902 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
903 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
904 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
905 {0x5c, 0x00000002}, {0x7c, 0x00000002},
906 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
907 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
908 {0x1e, 0x00000000}, {0xdf, 0x00000780},
909 {0x50, 0x00067435},
910 /*
911 * The 8723bu vendor driver indicates that bit 8 should be set in
912 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
913 * they never actually check the package type - and just default
914 * to not setting it.
915 */
916 {0x51, 0x0006b04e},
917 {0x52, 0x000007d2}, {0x53, 0x00000000},
918 {0x54, 0x00050400}, {0x55, 0x0004026e},
919 {0xdd, 0x0000004c}, {0x70, 0x00067435},
920 /*
921 * 0x71 has same package type condition as for register 0x51
922 */
923 {0x71, 0x0006b04e},
924 {0x72, 0x000007d2}, {0x73, 0x00000000},
925 {0x74, 0x00050400}, {0x75, 0x0004026e},
926 {0xef, 0x00000100}, {0x34, 0x0000add7},
927 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
928 {0x35, 0x00005000}, {0x34, 0x00008dd1},
929 {0x35, 0x00004400}, {0x34, 0x00007dce},
930 {0x35, 0x00003800}, {0x34, 0x00006cd1},
931 {0x35, 0x00004400}, {0x34, 0x00005cce},
932 {0x35, 0x00003800}, {0x34, 0x000048ce},
933 {0x35, 0x00004400}, {0x34, 0x000034ce},
934 {0x35, 0x00003800}, {0x34, 0x00002451},
935 {0x35, 0x00004400}, {0x34, 0x0000144e},
936 {0x35, 0x00003800}, {0x34, 0x00000051},
937 {0x35, 0x00004400}, {0xef, 0x00000000},
938 {0xef, 0x00000100}, {0xed, 0x00000010},
939 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
940 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
941 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
942 {0x44, 0x000044d1}, {0x44, 0x000034ce},
943 {0x44, 0x00002451}, {0x44, 0x0000144e},
944 {0x44, 0x00000051}, {0xef, 0x00000000},
945 {0xed, 0x00000000}, {0x7f, 0x00020080},
946 {0xef, 0x00002000}, {0x3b, 0x000380ef},
947 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
948 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
949 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
950 {0x3b, 0x00000900}, {0xef, 0x00000000},
951 {0xed, 0x00000001}, {0x40, 0x000380ef},
952 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
953 {0x40, 0x000200bc}, {0x40, 0x000188a5},
954 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
955 {0x40, 0x00000900}, {0xed, 0x00000000},
956 {0x82, 0x00080000}, {0x83, 0x00008000},
957 {0x84, 0x00048d80}, {0x85, 0x00068000},
958 {0xa2, 0x00080000}, {0xa3, 0x00008000},
959 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
960 {0xed, 0x00000002}, {0xef, 0x00000002},
961 {0x56, 0x00000032}, {0x76, 0x00000032},
962 {0x01, 0x00000780},
963 {0xff, 0xffffffff}
964};
965
26f1fad2
JS		 966static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
967 {0x00, 0x00030159}, {0x01, 0x00031284},
968 {0x02, 0x00098000}, {0x03, 0x00018c63},
969 {0x04, 0x000210e7}, {0x09, 0x0002044f},
970 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
971 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
972 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
973 {0x19, 0x00000000}, {0x1a, 0x00010255},
974 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
975 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
976 {0x1f, 0x00080001}, {0x20, 0x0000b614},
977 {0x21, 0x0006c000}, {0x22, 0x00000000},
978 {0x23, 0x00001558}, {0x24, 0x00000060},
979 {0x25, 0x00000483}, {0x26, 0x0004f000},
980 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
981 {0x29, 0x00004783}, {0x2a, 0x00000001},
982 {0x2b, 0x00021334}, {0x2a, 0x00000000},
983 {0x2b, 0x00000054}, {0x2a, 0x00000001},
984 {0x2b, 0x00000808}, {0x2b, 0x00053333},
985 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
986 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
987 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
988 {0x2b, 0x00000808}, {0x2b, 0x00063333},
989 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
990 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
991 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
992 {0x2b, 0x00000808}, {0x2b, 0x00073333},
993 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
994 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
995 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
996 {0x2b, 0x00000709}, {0x2b, 0x00063333},
997 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
998 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
999 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1000 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1001 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1002 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1003 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1004 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1005 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1006 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1007 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1008 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1009 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1010 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1011 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1012 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1013 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1014 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1015 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1016 {0x10, 0x00000000}, {0x11, 0x00000000},
1017 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1018 {0x10, 0x0009000f}, {0x11, 0x00023100},
1019 {0x12, 0x00032000}, {0x12, 0x00071000},
1020 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1021 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1022 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1023 {0x13, 0x00018493}, {0x13, 0x0001429b},
1024 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1025 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1026 {0x13, 0x00000020}, {0x14, 0x0001944c},
1027 {0x14, 0x00059444}, {0x14, 0x0009944c},
1028 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1029 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1030 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1031 {0x16, 0x000a0330}, {0x16, 0x00060330},
1032 {0x16, 0x00020330}, {0x00, 0x00010159},
1033 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1034 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1035 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1036 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1037 {0x00, 0x00030159},
1038 {0xff, 0xffffffff}
1039};
1040
1041static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1042 {0x00, 0x00030159}, {0x01, 0x00031284},
1043 {0x02, 0x00098000}, {0x03, 0x00018c63},
1044 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1045 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1046 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1047 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1048 {0x12, 0x00032000}, {0x12, 0x00071000},
1049 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1050 {0x13, 0x000287af}, {0x13, 0x000244b7},
1051 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1052 {0x13, 0x00018493}, {0x13, 0x00014297},
1053 {0x13, 0x00010295}, {0x13, 0x0000c298},
1054 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1055 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1056 {0x14, 0x00059444}, {0x14, 0x0009944c},
1057 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1058 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1059 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1060 {0x16, 0x000a0330}, {0x16, 0x00060330},
1061 {0x16, 0x00020330},
1062 {0xff, 0xffffffff}
1063};
1064
1065static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1066 {0x00, 0x00030159}, {0x01, 0x00031284},
1067 {0x02, 0x00098000}, {0x03, 0x00018c63},
1068 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1069 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1070 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1071 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1072 {0x19, 0x00000000}, {0x1a, 0x00010255},
1073 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1074 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1075 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1076 {0x21, 0x0006c000}, {0x22, 0x00000000},
1077 {0x23, 0x00001558}, {0x24, 0x00000060},
1078 {0x25, 0x00000483}, {0x26, 0x0004f000},
1079 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1080 {0x29, 0x00004783}, {0x2a, 0x00000001},
1081 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1082 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1083 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1084 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1085 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1086 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1087 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1088 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1089 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1090 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1091 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1092 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1093 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1094 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1095 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1096 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1097 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1098 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1099 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1100 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1101 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1102 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1103 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1104 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1105 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1106 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1107 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1108 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1109 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1110 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1111 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1112 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1113 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1114 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1115 {0x10, 0x00000000}, {0x11, 0x00000000},
1116 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1117 {0x10, 0x0009000f}, {0x11, 0x00023100},
1118 {0x12, 0x00032000}, {0x12, 0x00071000},
1119 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1120 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1121 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1122 {0x13, 0x00018493}, {0x13, 0x0001429b},
1123 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1124 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1125 {0x13, 0x00000020}, {0x14, 0x0001944c},
1126 {0x14, 0x00059444}, {0x14, 0x0009944c},
1127 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1128 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1129 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1130 {0x16, 0x000a0330}, {0x16, 0x00060330},
1131 {0x16, 0x00020330}, {0x00, 0x00010159},
1132 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1133 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1134 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1135 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1136 {0x00, 0x00030159},
1137 {0xff, 0xffffffff}
1138};
1139
1140static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1141 {0x00, 0x00030159}, {0x01, 0x00031284},
1142 {0x02, 0x00098000}, {0x03, 0x00018c63},
1143 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1144 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1145 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1146 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1147 {0x19, 0x00000000}, {0x1a, 0x00000255},
1148 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1149 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1150 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1151 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1152 {0x23, 0x00001558}, {0x24, 0x00000060},
1153 {0x25, 0x00000483}, {0x26, 0x0004f000},
1154 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1155 {0x29, 0x00004783}, {0x2a, 0x00000001},
1156 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1157 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1158 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1159 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1160 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1162 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1164 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1166 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1167 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1168 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1169 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1170 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1171 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1172 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1173 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1174 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1175 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1176 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1177 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1178 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1179 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1180 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1181 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1182 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1183 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1184 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1185 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1186 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1187 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1188 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1189 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1190 {0x10, 0x00000000}, {0x11, 0x00000000},
1191 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1192 {0x10, 0x0009000f}, {0x11, 0x00023100},
1193 {0x12, 0x000d8000}, {0x12, 0x00090000},
1194 {0x12, 0x00051000}, {0x12, 0x00012000},
1195 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1196 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1197 {0x13, 0x000183a4}, {0x13, 0x00014398},
1198 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1199 {0x13, 0x000080a4}, {0x13, 0x00004098},
1200 {0x13, 0x00000000}, {0x14, 0x0001944c},
1201 {0x14, 0x00059444}, {0x14, 0x0009944c},
1202 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1203 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1204 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1205 {0x16, 0x000a0330}, {0x16, 0x00060330},
1206 {0x16, 0x00020330}, {0x00, 0x00010159},
1207 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1208 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1209 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1210 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1211 {0x00, 0x00030159},
1212 {0xff, 0xffffffff}
1213};
1214
1215static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1216 { /* RF_A */
1217 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1218 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1219 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1220 .hspiread = REG_HSPI_XA_READBACK,
1221 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1222 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1223 },
1224 { /* RF_B */
1225 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1226 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1227 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1228 .hspiread = REG_HSPI_XB_READBACK,
1229 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1230 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1231 },
1232};
1233
1234static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1235 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1236 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1237 REG_OFDM0_ENERGY_CCA_THRES,
1238 REG_OFDM0_AGCR_SSI_TABLE,
1239 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1240 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1241 REG_OFDM0_XC_TX_AFE,
1242 REG_OFDM0_XD_TX_AFE,
1243 REG_OFDM0_RX_IQ_EXT_ANTA
1244};
1245
1246static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1247{
1248 struct usb_device *udev = priv->udev;
1249 int len;
1250 u8 data;
1251
1252 mutex_lock(&priv->usb_buf_mutex);
1253 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1254 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1255 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1256 RTW_USB_CONTROL_MSG_TIMEOUT);
1257 data = priv->usb_buf.val8;
1258 mutex_unlock(&priv->usb_buf_mutex);
1259
1260 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1261 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1262 __func__, addr, data, len);
1263 return data;
1264}
1265
1266static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1267{
1268 struct usb_device *udev = priv->udev;
1269 int len;
1270 u16 data;
1271
1272 mutex_lock(&priv->usb_buf_mutex);
1273 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1274 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1275 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1276 RTW_USB_CONTROL_MSG_TIMEOUT);
1277 data = le16_to_cpu(priv->usb_buf.val16);
1278 mutex_unlock(&priv->usb_buf_mutex);
1279
1280 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1281 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1282 __func__, addr, data, len);
1283 return data;
1284}
1285
1286static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1287{
1288 struct usb_device *udev = priv->udev;
1289 int len;
1290 u32 data;
1291
1292 mutex_lock(&priv->usb_buf_mutex);
1293 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1294 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1295 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1296 RTW_USB_CONTROL_MSG_TIMEOUT);
1297 data = le32_to_cpu(priv->usb_buf.val32);
1298 mutex_unlock(&priv->usb_buf_mutex);
1299
1300 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1301 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1302 __func__, addr, data, len);
1303 return data;
1304}
1305
1306static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1307{
1308 struct usb_device *udev = priv->udev;
1309 int ret;
1310
1311 mutex_lock(&priv->usb_buf_mutex);
1312 priv->usb_buf.val8 = val;
1313 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1314 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1315 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1316 RTW_USB_CONTROL_MSG_TIMEOUT);
1317
1318 mutex_unlock(&priv->usb_buf_mutex);
1319
1320 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1321 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1322 __func__, addr, val);
1323 return ret;
1324}
1325
1326static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1327{
1328 struct usb_device *udev = priv->udev;
1329 int ret;
1330
1331 mutex_lock(&priv->usb_buf_mutex);
1332 priv->usb_buf.val16 = cpu_to_le16(val);
1333 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1334 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1335 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1336 RTW_USB_CONTROL_MSG_TIMEOUT);
1337 mutex_unlock(&priv->usb_buf_mutex);
1338
1339 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1340 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1341 __func__, addr, val);
1342 return ret;
1343}
1344
1345static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1346{
1347 struct usb_device *udev = priv->udev;
1348 int ret;
1349
1350 mutex_lock(&priv->usb_buf_mutex);
1351 priv->usb_buf.val32 = cpu_to_le32(val);
1352 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1353 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1354 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1355 RTW_USB_CONTROL_MSG_TIMEOUT);
1356 mutex_unlock(&priv->usb_buf_mutex);
1357
1358 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1359 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1360 __func__, addr, val);
1361 return ret;
1362}
1363
1364static int
1365rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1366{
1367 struct usb_device *udev = priv->udev;
1368 int blocksize = priv->fops->writeN_block_size;
1369 int ret, i, count, remainder;
1370
1371 count = len / blocksize;
1372 remainder = len % blocksize;
1373
1374 for (i = 0; i < count; i++) {
1375 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1376 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1377 addr, 0, buf, blocksize,
1378 RTW_USB_CONTROL_MSG_TIMEOUT);
1379 if (ret != blocksize)
1380 goto write_error;
1381
1382 addr += blocksize;
1383 buf += blocksize;
1384 }
1385
1386 if (remainder) {
1387 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1388 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1389 addr, 0, buf, remainder,
1390 RTW_USB_CONTROL_MSG_TIMEOUT);
1391 if (ret != remainder)
1392 goto write_error;
1393 }
1394
1395 return len;
1396
1397write_error:
1398 dev_info(&udev->dev,
1399 "%s: Failed to write block at addr: %04x size: %04x\n",
1400 __func__, addr, blocksize);
1401 return -EAGAIN;
1402}
1403
1404static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1405 enum rtl8xxxu_rfpath path, u8 reg)
1406{
1407 u32 hssia, val32, retval;
1408
1409 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1410 if (path != RF_A)
1411 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1412 else
1413 val32 = hssia;
1414
1415 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1416 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1417 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1418 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1419 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1420
1421 udelay(10);
1422
1423 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1424 udelay(100);
1425
1426 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1427 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1428 udelay(10);
1429
1430 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1431 if (val32 & FPGA0_HSSI_PARM1_PI)
1432 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1433 else
1434 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1435
1436 retval &= 0xfffff;
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1439 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1440 __func__, reg, retval);
1441 return retval;
1442}
1443
22a31d45
JS		 1444/*
1445 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1446 * have write issues in high temperature conditions. We may have to
1447 * retry writing them.
1448 */
26f1fad2
JS		 1449static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1450 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1451{
1452 int ret, retval;
1453 u32 dataaddr;
1454
1455 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1456 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1457 __func__, reg, data);
1458
1459 data &= FPGA0_LSSI_PARM_DATA_MASK;
1460 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1461
1462 /* Use XB for path B */
1463 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1464 if (ret != sizeof(dataaddr))
1465 retval = -EIO;
1466 else
1467 retval = 0;
1468
1469 udelay(1);
1470
1471 return retval;
1472}
1473
8da91571
JS		 1474static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1475 struct h2c_cmd *h2c, int len)
26f1fad2
JS		 1476{
1477 struct device *dev = &priv->udev->dev;
1478 int mbox_nr, retry, retval = 0;
1479 int mbox_reg, mbox_ext_reg;
1480 u8 val8;
1481
1482 mutex_lock(&priv->h2c_mutex);
1483
1484 mbox_nr = priv->next_mbox;
1485 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
ed35d094
JS		 1486 mbox_ext_reg = priv->fops->mbox_ext_reg +
1487 (mbox_nr * priv->fops->mbox_ext_width);
26f1fad2
JS		 1488
1489 /*
1490 * MBOX ready?
1491 */
1492 retry = 100;
1493 do {
1494 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1495 if (!(val8 & BIT(mbox_nr)))
1496 break;
1497 } while (retry--);
1498
1499 if (!retry) {
c7a5a190 1500 dev_info(dev, "%s: Mailbox busy\n", __func__);
26f1fad2
JS		 1501 retval = -EBUSY;
1502 goto error;
1503 }
1504
1505 /*
1506 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1507 */
8da91571 1508 if (len > sizeof(u32)) {
ed35d094
JS		 1509 if (priv->fops->mbox_ext_width == 4) {
1510 rtl8xxxu_write32(priv, mbox_ext_reg,
1511 le32_to_cpu(h2c->raw_wide.ext));
1512 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1513 dev_info(dev, "H2C_EXT %08x\n",
1514 le32_to_cpu(h2c->raw_wide.ext));
1515 } else {
1516 rtl8xxxu_write16(priv, mbox_ext_reg,
1517 le16_to_cpu(h2c->raw.ext));
1518 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1519 dev_info(dev, "H2C_EXT %04x\n",
1520 le16_to_cpu(h2c->raw.ext));
1521 }
26f1fad2
JS		 1522 }
1523 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1524 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1525 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1526
1527 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1528
1529error:
1530 mutex_unlock(&priv->h2c_mutex);
1531 return retval;
1532}
1533
394f1bd3
JS		 1534static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1535{
1536 struct h2c_cmd h2c;
1537 int reqnum = 0;
1538
1539 memset(&h2c, 0, sizeof(struct h2c_cmd));
1540 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1541 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1542 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1543 h2c.bt_mp_oper.data = data;
1544 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1545
1546 reqnum++;
1547 memset(&h2c, 0, sizeof(struct h2c_cmd));
1548 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1549 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
1550 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
1551 h2c.bt_mp_oper.addr = reg;
1552 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
1553}
1554
26f1fad2
JS		 1555static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1556{
1557 u8 val8;
1558 u32 val32;
1559
1560 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1561 val8 |= BIT(0) | BIT(3);
1562 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1563
1564 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1565 val32 &= ~(BIT(4) | BIT(5));
1566 val32 |= BIT(3);
1567 if (priv->rf_paths == 2) {
1568 val32 &= ~(BIT(20) | BIT(21));
1569 val32 |= BIT(19);
1570 }
1571 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1572
1573 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1574 val32 &= ~OFDM_RF_PATH_TX_MASK;
1575 if (priv->tx_paths == 2)
1576 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1577 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1578 val32 |= OFDM_RF_PATH_TX_B;
1579 else
1580 val32 |= OFDM_RF_PATH_TX_A;
1581 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1582
1583 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1584 val32 &= ~FPGA_RF_MODE_JAPAN;
1585 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1586
1587 if (priv->rf_paths == 2)
1588 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1589 else
1590 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1591
1592 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1593 if (priv->rf_paths == 2)
1594 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1595
1596 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1597}
1598
db08de94
JS		 1599static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
1600{
1601}
1602
26f1fad2
JS		 1603static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1604{
1605 u8 sps0;
1606 u32 val32;
1607
1608 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1609
1610 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1611
1612 /* RF RX code for preamble power saving */
1613 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1614 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1615 if (priv->rf_paths == 2)
1616 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1617 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1618
1619 /* Disable TX for four paths */
1620 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1621 val32 &= ~OFDM_RF_PATH_TX_MASK;
1622 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1623
1624 /* Enable power saving */
1625 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1626 val32 |= FPGA_RF_MODE_JAPAN;
1627 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1628
1629 /* AFE control register to power down bits [30:22] */
1630 if (priv->rf_paths == 2)
1631 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1632 else
1633 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1634
1635 /* Power down RF module */
1636 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1637 if (priv->rf_paths == 2)
1638 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1639
1640 sps0 &= ~(BIT(0) | BIT(3));
1641 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1642}
1643
1644
1645static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1646{
1647 u8 val8;
1648
1649 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1650 val8 &= ~BIT(6);
1651 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1652
1653 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1654 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1655 val8 &= ~BIT(0);
1656 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1657}
1658
1659
1660/*
1661 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1662 * supports the 2.4GHz band, so channels 1 - 14:
1663 * group 0: channels 1 - 3
1664 * group 1: channels 4 - 9
1665 * group 2: channels 10 - 14
1666 *
1667 * Note: We index from 0 in the code
1668 */
1669static int rtl8723a_channel_to_group(int channel)
1670{
1671 int group;
1672
1673 if (channel < 4)
1674 group = 0;
1675 else if (channel < 10)
1676 group = 1;
1677 else
1678 group = 2;
1679
1680 return group;
1681}
1682
e796dab4
JS		 1683static int rtl8723b_channel_to_group(int channel)
1684{
1685 int group;
1686
1687 if (channel < 3)
1688 group = 0;
1689 else if (channel < 6)
1690 group = 1;
1691 else if (channel < 9)
1692 group = 2;
1693 else if (channel < 12)
1694 group = 3;
1695 else
1696 group = 4;
1697
1698 return group;
1699}
1700
26f1fad2
JS		 1701static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1702{
1703 struct rtl8xxxu_priv *priv = hw->priv;
1704 u32 val32, rsr;
1705 u8 val8, opmode;
1706 bool ht = true;
1707 int sec_ch_above, channel;
1708 int i;
1709
1710 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1711 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1712 channel = hw->conf.chandef.chan->hw_value;
1713
1714 switch (hw->conf.chandef.width) {
1715 case NL80211_CHAN_WIDTH_20_NOHT:
1716 ht = false;
1717 case NL80211_CHAN_WIDTH_20:
1718 opmode |= BW_OPMODE_20MHZ;
1719 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1720
1721 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1722 val32 &= ~FPGA_RF_MODE;
1723 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1724
1725 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1726 val32 &= ~FPGA_RF_MODE;
1727 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1728
1729 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1730 val32 |= FPGA0_ANALOG2_20MHZ;
1731 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1732 break;
1733 case NL80211_CHAN_WIDTH_40:
1734 if (hw->conf.chandef.center_freq1 >
1735 hw->conf.chandef.chan->center_freq) {
1736 sec_ch_above = 1;
1737 channel += 2;
1738 } else {
1739 sec_ch_above = 0;
1740 channel -= 2;
1741 }
1742
1743 opmode &= ~BW_OPMODE_20MHZ;
1744 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1745 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1746 if (sec_ch_above)
1747 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1748 else
1749 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1750 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1751
1752 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1753 val32 |= FPGA_RF_MODE;
1754 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1755
1756 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1757 val32 |= FPGA_RF_MODE;
1758 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1759
1760 /*
1761 * Set Control channel to upper or lower. These settings
1762 * are required only for 40MHz
1763 */
1764 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1765 val32 &= ~CCK0_SIDEBAND;
1766 if (!sec_ch_above)
1767 val32 |= CCK0_SIDEBAND;
1768 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1769
1770 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1771 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1772 if (sec_ch_above)
1773 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1774 else
1775 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1776 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1777
1778 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1779 val32 &= ~FPGA0_ANALOG2_20MHZ;
1780 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1781
1782 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1783 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1784 if (sec_ch_above)
1785 val32 |= FPGA0_PS_UPPER_CHANNEL;
1786 else
1787 val32 |= FPGA0_PS_LOWER_CHANNEL;
1788 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1789 break;
1790
1791 default:
1792 break;
1793 }
1794
1795 for (i = RF_A; i < priv->rf_paths; i++) {
1796 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1797 val32 &= ~MODE_AG_CHANNEL_MASK;
1798 val32 |= channel;
1799 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1800 }
1801
1802 if (ht)
1803 val8 = 0x0e;
1804 else
1805 val8 = 0x0a;
1806
1807 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1808 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1809
1810 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1811 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1812
1813 for (i = RF_A; i < priv->rf_paths; i++) {
1814 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1815 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1816 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1817 else
1818 val32 |= MODE_AG_CHANNEL_20MHZ;
1819 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1820 }
1821}
1822
c3f9506f
JS		 1823static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
1824{
1825 struct rtl8xxxu_priv *priv = hw->priv;
1826 u32 val32, rsr;
368633ce 1827 u8 val8, subchannel;
c3f9506f
JS		 1828 u16 rf_mode_bw;
1829 bool ht = true;
1830 int sec_ch_above, channel;
1831 int i;
1832
1833 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1834 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1835 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1836 channel = hw->conf.chandef.chan->hw_value;
1837
1838/* Hack */
1839 subchannel = 0;
1840
1841 switch (hw->conf.chandef.width) {
1842 case NL80211_CHAN_WIDTH_20_NOHT:
1843 ht = false;
1844 case NL80211_CHAN_WIDTH_20:
1845 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1846 subchannel = 0;
1847
1848 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1849 val32 &= ~FPGA_RF_MODE;
1850 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1851
1852 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1853 val32 &= ~FPGA_RF_MODE;
1854 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1855
1856 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1857 val32 &= ~(BIT(30) | BIT(31));
1858 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1859
1860 break;
1861 case NL80211_CHAN_WIDTH_40:
1862 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1863
1864 if (hw->conf.chandef.center_freq1 >
1865 hw->conf.chandef.chan->center_freq) {
1866 sec_ch_above = 1;
1867 channel += 2;
1868 } else {
1869 sec_ch_above = 0;
1870 channel -= 2;
1871 }
1872
1873 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1874 val32 |= FPGA_RF_MODE;
1875 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1876
1877 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1878 val32 |= FPGA_RF_MODE;
1879 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1880
1881 /*
1882 * Set Control channel to upper or lower. These settings
1883 * are required only for 40MHz
1884 */
1885 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1886 val32 &= ~CCK0_SIDEBAND;
1887 if (!sec_ch_above)
1888 val32 |= CCK0_SIDEBAND;
1889 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1890
1891 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1892 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1893 if (sec_ch_above)
1894 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1895 else
1896 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1897 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1898
1899 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1900 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1901 if (sec_ch_above)
1902 val32 |= FPGA0_PS_UPPER_CHANNEL;
1903 else
1904 val32 |= FPGA0_PS_LOWER_CHANNEL;
1905 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1906 break;
1907 case NL80211_CHAN_WIDTH_80:
1908 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1909 break;
1910 default:
1911 break;
1912 }
1913
1914 for (i = RF_A; i < priv->rf_paths; i++) {
1915 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1916 val32 &= ~MODE_AG_CHANNEL_MASK;
1917 val32 |= channel;
1918 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1919 }
1920
1921 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1922 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1923
1924 if (ht)
1925 val8 = 0x0e;
1926 else
1927 val8 = 0x0a;
1928
1929 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1930 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1931
1932 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1933 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1934
1935 for (i = RF_A; i < priv->rf_paths; i++) {
1936 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1937 val32 &= ~MODE_AG_BW_MASK;
1938 switch(hw->conf.chandef.width) {
1939 case NL80211_CHAN_WIDTH_80:
1940 val32 |= MODE_AG_BW_80MHZ_8723B;
1941 break;
1942 case NL80211_CHAN_WIDTH_40:
1943 val32 |= MODE_AG_BW_40MHZ_8723B;
1944 break;
1945 default:
1946 val32 |= MODE_AG_BW_20MHZ_8723B;
1947 break;
1948 }
1949 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1950 }
1951}
1952
26f1fad2
JS		 1953static void
1954rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1955{
1956 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1957 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1958 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1959 u8 val8;
1960 int group, i;
1961
1962 group = rtl8723a_channel_to_group(channel);
1963
1964 cck[0] = priv->cck_tx_power_index_A[group];
1965 cck[1] = priv->cck_tx_power_index_B[group];
1966
1967 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1968 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1969
1970 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1971 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1972
1973 mcsbase[0] = ofdm[0];
1974 mcsbase[1] = ofdm[1];
1975 if (!ht40) {
1976 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1977 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1978 }
1979
1980 if (priv->tx_paths > 1) {
1981 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1982 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1983 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1984 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1985 }
1986
1987 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1988 dev_info(&priv->udev->dev,
1989 "%s: Setting TX power CCK A: %02x, "
1990 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1991 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1992
1993 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1994 if (cck[i] > RF6052_MAX_TX_PWR)
1995 cck[i] = RF6052_MAX_TX_PWR;
1996 if (ofdm[i] > RF6052_MAX_TX_PWR)
1997 ofdm[i] = RF6052_MAX_TX_PWR;
1998 }
1999
2000 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2001 val32 &= 0xffff00ff;
2002 val32 |= (cck[0] << 8);
2003 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2004
2005 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2006 val32 &= 0xff;
2007 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2008 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2009
2010 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2011 val32 &= 0xffffff00;
2012 val32 |= cck[1];
2013 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2014
2015 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2016 val32 &= 0xff;
2017 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2018 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2019
2020 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2021 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2022 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2023 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2024 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2025 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2026
2027 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2028 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2029
2030 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2031 mcsbase[0] << 16 | mcsbase[0] << 24;
2032 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2033 mcsbase[1] << 16 | mcsbase[1] << 24;
2034
2035 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2036 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2037
2038 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2039 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2040
2041 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2042 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2043
2044 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2045 for (i = 0; i < 3; i++) {
2046 if (i != 2)
2047 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2048 else
2049 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2050 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2051 }
2052 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2053 for (i = 0; i < 3; i++) {
2054 if (i != 2)
2055 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2056 else
2057 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2058 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2059 }
2060}
2061
e796dab4
JS		 2062static void
2063rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2064{
54bed43f
JS		 2065 u32 val32, ofdm;
2066 u8 cck, ofdmbase;
2067 int group, tx_idx;
e796dab4 2068
54bed43f 2069 tx_idx = 0;
e796dab4 2070 group = rtl8723b_channel_to_group(channel);
54bed43f
JS		 2071
2072 cck = priv->cck_tx_power_index_B[group];
2073 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2074 val32 &= 0xffff00ff;
2075 val32 |= (cck << 8);
2076 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2077
2078 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2079 val32 &= 0xff;
2080 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2081 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2082
2083 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2084 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2085 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2086
2087 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2088 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
e796dab4
JS		 2089}
2090
26f1fad2
JS		 2091static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2092 enum nl80211_iftype linktype)
2093{
a26703f3 2094 u8 val8;
26f1fad2 2095
a26703f3 2096 val8 = rtl8xxxu_read8(priv, REG_MSR);
26f1fad2
JS		 2097 val8 &= ~MSR_LINKTYPE_MASK;
2098
2099 switch (linktype) {
2100 case NL80211_IFTYPE_UNSPECIFIED:
2101 val8 |= MSR_LINKTYPE_NONE;
2102 break;
2103 case NL80211_IFTYPE_ADHOC:
2104 val8 |= MSR_LINKTYPE_ADHOC;
2105 break;
2106 case NL80211_IFTYPE_STATION:
2107 val8 |= MSR_LINKTYPE_STATION;
2108 break;
2109 case NL80211_IFTYPE_AP:
2110 val8 |= MSR_LINKTYPE_AP;
2111 break;
2112 default:
2113 goto out;
2114 }
2115
2116 rtl8xxxu_write8(priv, REG_MSR, val8);
2117out:
2118 return;
2119}
2120
2121static void
2122rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2123{
2124 u16 val16;
2125
2126 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2127 RETRY_LIMIT_SHORT_MASK) |
2128 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2129 RETRY_LIMIT_LONG_MASK);
2130
2131 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2132}
2133
2134static void
2135rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2136{
2137 u16 val16;
2138
2139 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2140 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2141
2142 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2143}
2144
2145static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2146{
2147 struct device *dev = &priv->udev->dev;
2148 char *cut;
2149
2150 switch (priv->chip_cut) {
2151 case 0:
2152 cut = "A";
2153 break;
2154 case 1:
2155 cut = "B";
2156 break;
0e5d435a
JS		 2157 case 2:
2158 cut = "C";
2159 break;
2160 case 3:
2161 cut = "D";
2162 break;
2163 case 4:
2164 cut = "E";
2165 break;
26f1fad2
JS		 2166 default:
2167 cut = "unknown";
2168 }
2169
2170 dev_info(dev,
2171 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
0e5d435a
JS		 2172 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2173 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2174 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
26f1fad2
JS		 2175
2176 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2177}
2178
2179static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2180{
2181 struct device *dev = &priv->udev->dev;
2182 u32 val32, bonding;
2183 u16 val16;
2184
2185 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2186 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2187 SYS_CFG_CHIP_VERSION_SHIFT;
2188 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2189 dev_info(dev, "Unsupported test chip\n");
2190 return -ENOTSUPP;
2191 }
2192
2193 if (val32 & SYS_CFG_BT_FUNC) {
35a741fe
JS		 2194 if (priv->chip_cut >= 3) {
2195 sprintf(priv->chip_name, "8723BU");
2196 priv->rtlchip = 0x8723b;
2197 } else {
2198 sprintf(priv->chip_name, "8723AU");
0e28b975 2199 priv->usb_interrupts = 1;
35a741fe
JS		 2200 priv->rtlchip = 0x8723a;
2201 }
2202
26f1fad2
JS		 2203 priv->rf_paths = 1;
2204 priv->rx_paths = 1;
2205 priv->tx_paths = 1;
26f1fad2
JS		 2206
2207 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2208 if (val32 & MULTI_WIFI_FUNC_EN)
2209 priv->has_wifi = 1;
2210 if (val32 & MULTI_BT_FUNC_EN)
2211 priv->has_bluetooth = 1;
2212 if (val32 & MULTI_GPS_FUNC_EN)
2213 priv->has_gps = 1;
38451998 2214 priv->is_multi_func = 1;
26f1fad2
JS		 2215 } else if (val32 & SYS_CFG_TYPE_ID) {
2216 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2217 bonding &= HPON_FSM_BONDING_MASK;
0e5d435a
JS		 2218 if (priv->chip_cut >= 3) {
2219 if (bonding == HPON_FSM_BONDING_1T2R) {
2220 sprintf(priv->chip_name, "8191EU");
2221 priv->rf_paths = 2;
2222 priv->rx_paths = 2;
2223 priv->tx_paths = 1;
2224 priv->rtlchip = 0x8191e;
2225 } else {
2226 sprintf(priv->chip_name, "8192EU");
2227 priv->rf_paths = 2;
2228 priv->rx_paths = 2;
2229 priv->tx_paths = 2;
2230 priv->rtlchip = 0x8192e;
2231 }
2232 } else if (bonding == HPON_FSM_BONDING_1T2R) {
26f1fad2
JS		 2233 sprintf(priv->chip_name, "8191CU");
2234 priv->rf_paths = 2;
2235 priv->rx_paths = 2;
2236 priv->tx_paths = 1;
0e28b975 2237 priv->usb_interrupts = 1;
26f1fad2
JS		 2238 priv->rtlchip = 0x8191c;
2239 } else {
2240 sprintf(priv->chip_name, "8192CU");
2241 priv->rf_paths = 2;
2242 priv->rx_paths = 2;
2243 priv->tx_paths = 2;
0e28b975 2244 priv->usb_interrupts = 1;
26f1fad2
JS		 2245 priv->rtlchip = 0x8192c;
2246 }
2247 priv->has_wifi = 1;
2248 } else {
2249 sprintf(priv->chip_name, "8188CU");
2250 priv->rf_paths = 1;
2251 priv->rx_paths = 1;
2252 priv->tx_paths = 1;
2253 priv->rtlchip = 0x8188c;
0e28b975 2254 priv->usb_interrupts = 1;
26f1fad2
JS		 2255 priv->has_wifi = 1;
2256 }
2257
0e5d435a
JS		 2258 switch (priv->rtlchip) {
2259 case 0x8188e:
2260 case 0x8192e:
2261 case 0x8723b:
2262 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2263 case SYS_CFG_VENDOR_ID_TSMC:
2264 sprintf(priv->chip_vendor, "TSMC");
2265 break;
2266 case SYS_CFG_VENDOR_ID_SMIC:
2267 sprintf(priv->chip_vendor, "SMIC");
2268 priv->vendor_smic = 1;
2269 break;
2270 case SYS_CFG_VENDOR_ID_UMC:
2271 sprintf(priv->chip_vendor, "UMC");
2272 priv->vendor_umc = 1;
2273 break;
2274 default:
2275 sprintf(priv->chip_vendor, "unknown");
2276 }
2277 break;
2278 default:
2279 if (val32 & SYS_CFG_VENDOR_ID) {
2280 sprintf(priv->chip_vendor, "UMC");
2281 priv->vendor_umc = 1;
2282 } else {
2283 sprintf(priv->chip_vendor, "TSMC");
2284 }
2285 }
26f1fad2
JS		 2286
2287 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2288 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2289
2290 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2291 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2292 priv->ep_tx_high_queue = 1;
2293 priv->ep_tx_count++;
2294 }
2295
2296 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2297 priv->ep_tx_normal_queue = 1;
2298 priv->ep_tx_count++;
2299 }
2300
2301 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2302 priv->ep_tx_low_queue = 1;
2303 priv->ep_tx_count++;
2304 }
2305
2306 /*
2307 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2308 */
2309 if (!priv->ep_tx_count) {
2310 switch (priv->nr_out_eps) {
35a741fe 2311 case 4:
26f1fad2
JS		 2312 case 3:
2313 priv->ep_tx_low_queue = 1;
2314 priv->ep_tx_count++;
2315 case 2:
2316 priv->ep_tx_normal_queue = 1;
2317 priv->ep_tx_count++;
2318 case 1:
2319 priv->ep_tx_high_queue = 1;
2320 priv->ep_tx_count++;
2321 break;
2322 default:
2323 dev_info(dev, "Unsupported USB TX end-points\n");
2324 return -ENOTSUPP;
2325 }
2326 }
2327
2328 return 0;
2329}
2330
2331static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2332{
d38f1c37
JS		 2333 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2334
2335 if (efuse->rtl_id != cpu_to_le16(0x8129))
26f1fad2
JS		 2336 return -EINVAL;
2337
d38f1c37 2338 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
26f1fad2
JS		 2339
2340 memcpy(priv->cck_tx_power_index_A,
d38f1c37 2341 efuse->cck_tx_power_index_A,
3e84f938 2342 sizeof(efuse->cck_tx_power_index_A));
26f1fad2 2343 memcpy(priv->cck_tx_power_index_B,
d38f1c37 2344 efuse->cck_tx_power_index_B,
3e84f938 2345 sizeof(efuse->cck_tx_power_index_B));
26f1fad2
JS		 2346
2347 memcpy(priv->ht40_1s_tx_power_index_A,
d38f1c37 2348 efuse->ht40_1s_tx_power_index_A,
3e84f938 2349 sizeof(efuse->ht40_1s_tx_power_index_A));
26f1fad2 2350 memcpy(priv->ht40_1s_tx_power_index_B,
d38f1c37 2351 efuse->ht40_1s_tx_power_index_B,
3e84f938 2352 sizeof(efuse->ht40_1s_tx_power_index_B));
26f1fad2
JS		 2353
2354 memcpy(priv->ht20_tx_power_index_diff,
d38f1c37 2355 efuse->ht20_tx_power_index_diff,
3e84f938 2356 sizeof(efuse->ht20_tx_power_index_diff));
26f1fad2 2357 memcpy(priv->ofdm_tx_power_index_diff,
d38f1c37 2358 efuse->ofdm_tx_power_index_diff,
3e84f938 2359 sizeof(efuse->ofdm_tx_power_index_diff));
26f1fad2
JS		 2360
2361 memcpy(priv->ht40_max_power_offset,
d38f1c37 2362 efuse->ht40_max_power_offset,
3e84f938 2363 sizeof(efuse->ht40_max_power_offset));
26f1fad2 2364 memcpy(priv->ht20_max_power_offset,
d38f1c37 2365 efuse->ht20_max_power_offset,
3e84f938 2366 sizeof(efuse->ht20_max_power_offset));
26f1fad2 2367
4ef22eb9
JS		 2368 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2369 priv->has_xtalk = 1;
2370 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2371 }
26f1fad2 2372 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
d38f1c37 2373 efuse->vendor_name);
26f1fad2 2374 dev_info(&priv->udev->dev, "Product: %.41s\n",
d38f1c37 2375 efuse->device_name);
26f1fad2
JS		 2376 return 0;
2377}
2378
3c836d60
JS		 2379static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2380{
b8ba8602 2381 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
3be26999 2382 int i;
b8ba8602
JS		 2383
2384 if (efuse->rtl_id != cpu_to_le16(0x8129))
3c836d60
JS		 2385 return -EINVAL;
2386
b8ba8602 2387 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
3c836d60 2388
3be26999
JS		 2389 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2390 sizeof(efuse->tx_power_index_A.cck_base));
2391 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2392 sizeof(efuse->tx_power_index_B.cck_base));
2393
2394 memcpy(priv->ht40_1s_tx_power_index_A,
2395 efuse->tx_power_index_A.ht40_base,
2396 sizeof(efuse->tx_power_index_A.ht40_base));
2397 memcpy(priv->ht40_1s_tx_power_index_B,
2398 efuse->tx_power_index_B.ht40_base,
2399 sizeof(efuse->tx_power_index_B.ht40_base));
2400
2401 priv->ofdm_tx_power_diff[0].a =
2402 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2403 priv->ofdm_tx_power_diff[0].b =
2404 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2405
2406 priv->ht20_tx_power_diff[0].a =
2407 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2408 priv->ht20_tx_power_diff[0].b =
2409 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2410
2411 priv->ht40_tx_power_diff[0].a = 0;
2412 priv->ht40_tx_power_diff[0].b = 0;
2413
2414 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2415 priv->ofdm_tx_power_diff[i].a =
2416 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2417 priv->ofdm_tx_power_diff[i].b =
2418 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2419
2420 priv->ht20_tx_power_diff[i].a =
2421 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2422 priv->ht20_tx_power_diff[i].b =
2423 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2424
2425 priv->ht40_tx_power_diff[i].a =
2426 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2427 priv->ht40_tx_power_diff[i].b =
2428 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2429 }
2430
4ef22eb9
JS		 2431 priv->has_xtalk = 1;
2432 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2433
b8ba8602
JS		 2434 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2435 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
3c836d60
JS		 2436
2437 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2438 int i;
2439 unsigned char *raw = priv->efuse_wifi.raw;
2440
2441 dev_info(&priv->udev->dev,
2442 "%s: dumping efuse (0x%02zx bytes):\n",
2443 __func__, sizeof(struct rtl8723bu_efuse));
2444 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2445 dev_info(&priv->udev->dev, "%02x: "
2446 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2447 raw[i], raw[i + 1], raw[i + 2],
2448 raw[i + 3], raw[i + 4], raw[i + 5],
2449 raw[i + 6], raw[i + 7]);
2450 }
2451 }
2452
2453 return 0;
2454}
2455
c0963772
KV		 2456#ifdef CONFIG_RTL8XXXU_UNTESTED
2457
26f1fad2
JS		 2458static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
2459{
49594441 2460 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
26f1fad2
JS		 2461 int i;
2462
49594441 2463 if (efuse->rtl_id != cpu_to_le16(0x8129))
26f1fad2
JS		 2464 return -EINVAL;
2465
49594441 2466 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
26f1fad2
JS		 2467
2468 memcpy(priv->cck_tx_power_index_A,
49594441 2469 efuse->cck_tx_power_index_A,
3e84f938 2470 sizeof(efuse->cck_tx_power_index_A));
26f1fad2 2471 memcpy(priv->cck_tx_power_index_B,
49594441 2472 efuse->cck_tx_power_index_B,
3e84f938 2473 sizeof(efuse->cck_tx_power_index_B));
26f1fad2
JS		 2474
2475 memcpy(priv->ht40_1s_tx_power_index_A,
49594441 2476 efuse->ht40_1s_tx_power_index_A,
3e84f938 2477 sizeof(efuse->ht40_1s_tx_power_index_A));
26f1fad2 2478 memcpy(priv->ht40_1s_tx_power_index_B,
49594441 2479 efuse->ht40_1s_tx_power_index_B,
3e84f938 2480 sizeof(efuse->ht40_1s_tx_power_index_B));
26f1fad2 2481 memcpy(priv->ht40_2s_tx_power_index_diff,
49594441 2482 efuse->ht40_2s_tx_power_index_diff,
3e84f938 2483 sizeof(efuse->ht40_2s_tx_power_index_diff));
26f1fad2
JS		 2484
2485 memcpy(priv->ht20_tx_power_index_diff,
49594441 2486 efuse->ht20_tx_power_index_diff,
3e84f938 2487 sizeof(efuse->ht20_tx_power_index_diff));
26f1fad2 2488 memcpy(priv->ofdm_tx_power_index_diff,
49594441 2489 efuse->ofdm_tx_power_index_diff,
3e84f938 2490 sizeof(efuse->ofdm_tx_power_index_diff));
26f1fad2
JS		 2491
2492 memcpy(priv->ht40_max_power_offset,
49594441 2493 efuse->ht40_max_power_offset,
3e84f938 2494 sizeof(efuse->ht40_max_power_offset));
26f1fad2 2495 memcpy(priv->ht20_max_power_offset,
49594441 2496 efuse->ht20_max_power_offset,
3e84f938 2497 sizeof(efuse->ht20_max_power_offset));
26f1fad2
JS		 2498
2499 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
49594441 2500 efuse->vendor_name);
26f1fad2 2501 dev_info(&priv->udev->dev, "Product: %.20s\n",
49594441 2502 efuse->device_name);
26f1fad2 2503
49594441 2504 if (efuse->rf_regulatory & 0x20) {
26f1fad2
JS		 2505 sprintf(priv->chip_name, "8188RU");
2506 priv->hi_pa = 1;
2507 }
2508
2509 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2510 unsigned char *raw = priv->efuse_wifi.raw;
2511
2512 dev_info(&priv->udev->dev,
2513 "%s: dumping efuse (0x%02zx bytes):\n",
2514 __func__, sizeof(struct rtl8192cu_efuse));
2515 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
2516 dev_info(&priv->udev->dev, "%02x: "
2517 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2518 raw[i], raw[i + 1], raw[i + 2],
2519 raw[i + 3], raw[i + 4], raw[i + 5],
2520 raw[i + 6], raw[i + 7]);
2521 }
2522 }
2523 return 0;
2524}
2525
c0963772
KV		 2526#endif
2527
3307d840
JS		 2528static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
2529{
b7dda34d 2530 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
3307d840
JS		 2531 int i;
2532
b7dda34d 2533 if (efuse->rtl_id != cpu_to_le16(0x8129))
3307d840
JS		 2534 return -EINVAL;
2535
b7dda34d 2536 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
3307d840 2537
4ef22eb9
JS		 2538 priv->has_xtalk = 1;
2539 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
2540
b7dda34d
JS		 2541 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2542 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
2543 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
3307d840
JS		 2544
2545 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2546 unsigned char *raw = priv->efuse_wifi.raw;
2547
2548 dev_info(&priv->udev->dev,
2549 "%s: dumping efuse (0x%02zx bytes):\n",
2550 __func__, sizeof(struct rtl8192eu_efuse));
2551 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
2552 dev_info(&priv->udev->dev, "%02x: "
2553 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2554 raw[i], raw[i + 1], raw[i + 2],
2555 raw[i + 3], raw[i + 4], raw[i + 5],
2556 raw[i + 6], raw[i + 7]);
2557 }
2558 }
0e5d435a 2559 return 0;
3307d840
JS		 2560}
2561
26f1fad2
JS		 2562static int
2563rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
2564{
2565 int i;
2566 u8 val8;
2567 u32 val32;
2568
2569 /* Write Address */
2570 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
2571 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
2572 val8 &= 0xfc;
2573 val8 |= (offset >> 8) & 0x03;
2574 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2575
2576 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2577 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2578
2579 /* Poll for data read */
2580 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2581 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2582 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2583 if (val32 & BIT(31))
2584 break;
2585 }
2586
2587 if (i == RTL8XXXU_MAX_REG_POLL)
2588 return -EIO;
2589
2590 udelay(50);
2591 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2592
2593 *data = val32 & 0xff;
2594 return 0;
2595}
2596
2597static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2598{
2599 struct device *dev = &priv->udev->dev;
2600 int i, ret = 0;
2601 u8 val8, word_mask, header, extheader;
2602 u16 val16, efuse_addr, offset;
2603 u32 val32;
2604
2605 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2606 if (val16 & EEPROM_ENABLE)
2607 priv->has_eeprom = 1;
2608 if (val16 & EEPROM_BOOT)
2609 priv->boot_eeprom = 1;
2610
38451998
JS		 2611 if (priv->is_multi_func) {
2612 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2613 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2614 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2615 }
26f1fad2
JS		 2616
2617 dev_dbg(dev, "Booting from %s\n",
2618 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2619
2620 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2621
2622 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2623 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2624 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2625 val16 |= SYS_ISO_PWC_EV12V;
2626 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2627 }
2628 /* Reset: 0x0000[28], default valid */
2629 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2630 if (!(val16 & SYS_FUNC_ELDR)) {
2631 val16 |= SYS_FUNC_ELDR;
2632 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2633 }
2634
2635 /*
2636 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2637 */
2638 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2639 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2640 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2641 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2642 }
2643
2644 /* Default value is 0xff */
3307d840 2645 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
26f1fad2
JS		 2646
2647 efuse_addr = 0;
2648 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
f6c47702
JS		 2649 u16 map_addr;
2650
26f1fad2
JS		 2651 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2652 if (ret || header == 0xff)
2653 goto exit;
2654
2655 if ((header & 0x1f) == 0x0f) { /* extended header */
2656 offset = (header & 0xe0) >> 5;
2657
2658 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2659 &extheader);
2660 if (ret)
2661 goto exit;
2662 /* All words disabled */
2663 if ((extheader & 0x0f) == 0x0f)
2664 continue;
2665
2666 offset |= ((extheader & 0xf0) >> 1);
2667 word_mask = extheader & 0x0f;
2668 } else {
2669 offset = (header >> 4) & 0x0f;
2670 word_mask = header & 0x0f;
2671 }
2672
f6c47702
JS		 2673 /* Get word enable value from PG header */
2674
2675 /* We have 8 bits to indicate validity */
2676 map_addr = offset * 8;
2677 if (map_addr >= EFUSE_MAP_LEN) {
2678 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2679 "efuse corrupt!\n",
2680 __func__, map_addr);
26f1fad2
JS		 2681 ret = -EINVAL;
2682 goto exit;
2683 }
f6c47702
JS		 2684 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2685 /* Check word enable condition in the section */
32a39dd4 2686 if (word_mask & BIT(i)) {
f6c47702 2687 map_addr += 2;
32a39dd4
JS		 2688 continue;
2689 }
2690
2691 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2692 if (ret)
2693 goto exit;
2694 priv->efuse_wifi.raw[map_addr++] = val8;
2695
2696 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
2697 if (ret)
2698 goto exit;
2699 priv->efuse_wifi.raw[map_addr++] = val8;
f6c47702 2700 }
26f1fad2
JS		 2701 }
2702
2703exit:
2704 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2705
2706 return ret;
2707}
2708
d48fe60e
JS		 2709static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2710{
2711 u8 val8;
2712 u16 sys_func;
2713
2714 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 2715 val8 &= ~BIT(0);
d48fe60e
JS		 2716 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2717 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2718 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2719 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2720 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 2721 val8 |= BIT(0);
d48fe60e
JS		 2722 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2723 sys_func |= SYS_FUNC_CPU_ENABLE;
2724 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2725}
2726
26f1fad2
JS		 2727static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2728{
2729 struct device *dev = &priv->udev->dev;
2730 int ret = 0, i;
2731 u32 val32;
2732
2733 /* Poll checksum report */
2734 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2735 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2736 if (val32 & MCU_FW_DL_CSUM_REPORT)
2737 break;
2738 }
2739
2740 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2741 dev_warn(dev, "Firmware checksum poll timed out\n");
2742 ret = -EAGAIN;
2743 goto exit;
2744 }
2745
2746 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2747 val32 |= MCU_FW_DL_READY;
2748 val32 &= ~MCU_WINT_INIT_READY;
2749 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2750
d48fe60e
JS		 2751 /*
2752 * Reset the 8051 in order for the firmware to start running,
2753 * otherwise it won't come up on the 8192eu
2754 */
2755 rtl8xxxu_reset_8051(priv);
2756
26f1fad2
JS		 2757 /* Wait for firmware to become ready */
2758 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2759 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2760 if (val32 & MCU_WINT_INIT_READY)
2761 break;
2762
2763 udelay(100);
2764 }
2765
2766 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2767 dev_warn(dev, "Firmware failed to start\n");
2768 ret = -EAGAIN;
2769 goto exit;
2770 }
2771
3a4be6a0
JS		 2772 /*
2773 * Init H2C command
2774 */
2775 if (priv->rtlchip == 0x8723b)
2776 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
26f1fad2
JS		 2777exit:
2778 return ret;
2779}
2780
2781static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2782{
2783 int pages, remainder, i, ret;
d48fe60e 2784 u8 val8;
26f1fad2
JS		 2785 u16 val16;
2786 u32 val32;
2787 u8 *fwptr;
2788
2789 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2790 val8 |= 4;
2791 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2792
2793 /* 8051 enable */
2794 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
43154f6f
JS		 2795 val16 |= SYS_FUNC_CPU_ENABLE;
2796 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 2797
216202ae
JS		 2798 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2799 if (val8 & MCU_FW_RAM_SEL) {
2800 pr_info("do the RAM reset\n");
2801 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
d48fe60e 2802 rtl8xxxu_reset_8051(priv);
216202ae
JS		 2803 }
2804
26f1fad2
JS		 2805 /* MCU firmware download enable */
2806 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2807 val8 |= MCU_FW_DL_ENABLE;
2808 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 2809
2810 /* 8051 reset */
2811 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2812 val32 &= ~BIT(19);
2813 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
26f1fad2
JS		 2814
2815 /* Reset firmware download checksum */
2816 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2817 val8 |= MCU_FW_DL_CSUM_REPORT;
2818 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 2819
2820 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2821 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2822
2823 fwptr = priv->fw_data->data;
2824
2825 for (i = 0; i < pages; i++) {
2826 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 2827 val8 |= i;
2828 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 2829
2830 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2831 fwptr, RTL_FW_PAGE_SIZE);
2832 if (ret != RTL_FW_PAGE_SIZE) {
2833 ret = -EAGAIN;
2834 goto fw_abort;
2835 }
2836
2837 fwptr += RTL_FW_PAGE_SIZE;
2838 }
2839
2840 if (remainder) {
2841 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 2842 val8 |= i;
2843 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 2844 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2845 fwptr, remainder);
2846 if (ret != remainder) {
2847 ret = -EAGAIN;
2848 goto fw_abort;
2849 }
2850 }
2851
2852 ret = 0;
2853fw_abort:
2854 /* MCU firmware download disable */
2855 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2856 val16 &= ~MCU_FW_DL_ENABLE;
2857 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
26f1fad2
JS		 2858
2859 return ret;
2860}
2861
2862static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2863{
2864 struct device *dev = &priv->udev->dev;
2865 const struct firmware *fw;
2866 int ret = 0;
2867 u16 signature;
2868
2869 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2870 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2871 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2872 ret = -EAGAIN;
2873 goto exit;
2874 }
2875 if (!fw) {
2876 dev_warn(dev, "Firmware data not available\n");
2877 ret = -EINVAL;
2878 goto exit;
2879 }
2880
2881 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
98e27cbd
TK		 2882 if (!priv->fw_data) {
2883 ret = -ENOMEM;
2884 goto exit;
2885 }
26f1fad2
JS		 2886 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2887
2888 signature = le16_to_cpu(priv->fw_data->signature);
2889 switch (signature & 0xfff0) {
0e5d435a 2890 case 0x92e0:
26f1fad2
JS		 2891 case 0x92c0:
2892 case 0x88c0:
35a741fe 2893 case 0x5300:
26f1fad2
JS		 2894 case 0x2300:
2895 break;
2896 default:
2897 ret = -EINVAL;
2898 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2899 __func__, signature);
2900 }
2901
2902 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2903 le16_to_cpu(priv->fw_data->major_version),
2904 priv->fw_data->minor_version, signature);
2905
2906exit:
2907 release_firmware(fw);
2908 return ret;
2909}
2910
2911static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2912{
2913 char *fw_name;
2914 int ret;
2915
2916 switch (priv->chip_cut) {
2917 case 0:
2918 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2919 break;
2920 case 1:
2921 if (priv->enable_bluetooth)
2922 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2923 else
2924 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2925
2926 break;
2927 default:
2928 return -EINVAL;
2929 }
2930
2931 ret = rtl8xxxu_load_firmware(priv, fw_name);
2932 return ret;
2933}
2934
35a741fe
JS		 2935static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
2936{
2937 char *fw_name;
2938 int ret;
2939
2940 if (priv->enable_bluetooth)
2941 fw_name = "rtlwifi/rtl8723bu_bt.bin";
2942 else
2943 fw_name = "rtlwifi/rtl8723bu_nic.bin";
2944
2945 ret = rtl8xxxu_load_firmware(priv, fw_name);
2946 return ret;
2947}
2948
c0963772
KV		 2949#ifdef CONFIG_RTL8XXXU_UNTESTED
2950
26f1fad2
JS		 2951static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2952{
2953 char *fw_name;
2954 int ret;
2955
2956 if (!priv->vendor_umc)
2957 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2958 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2959 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2960 else
2961 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2962
2963 ret = rtl8xxxu_load_firmware(priv, fw_name);
2964
2965 return ret;
2966}
2967
c0963772
KV		 2968#endif
2969
3307d840
JS		 2970static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2971{
2972 char *fw_name;
2973 int ret;
2974
0e5d435a 2975 fw_name = "rtlwifi/rtl8192eu_nic.bin";
3307d840
JS		 2976
2977 ret = rtl8xxxu_load_firmware(priv, fw_name);
2978
2979 return ret;
2980}
2981
26f1fad2
JS		 2982static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2983{
2984 u16 val16;
2985 int i = 100;
2986
2987 /* Inform 8051 to perform reset */
2988 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2989
2990 for (i = 100; i > 0; i--) {
2991 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2992
2993 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2994 dev_dbg(&priv->udev->dev,
2995 "%s: Firmware self reset success!\n", __func__);
2996 break;
2997 }
2998 udelay(50);
2999 }
3000
3001 if (!i) {
3002 /* Force firmware reset */
3003 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3004 val16 &= ~SYS_FUNC_CPU_ENABLE;
3005 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3006 }
3007}
3008
f0d9f5e9
JS		 3009static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3010{
3011 u32 val32;
3012
3013 val32 = rtl8xxxu_read32(priv, 0x64);
3014 val32 &= ~(BIT(20) | BIT(24));
3015 rtl8xxxu_write32(priv, 0x64, val32);
3016
3017 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3018 val32 &= ~BIT(4);
3a4be6a0
JS		 3019 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3020
3021 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
f0d9f5e9
JS		 3022 val32 |= BIT(3);
3023 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3024
3025 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
f0d9f5e9
JS		 3026 val32 |= BIT(24);
3027 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3028
3a4be6a0
JS		 3029 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3030 val32 &= ~BIT(23);
3031 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3032
120e627f 3033 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
f0d9f5e9 3034 val32 |= (BIT(0) | BIT(1));
120e627f 3035 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
f0d9f5e9 3036
59b74397 3037 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
f0d9f5e9
JS		 3038 val32 &= 0xffffff00;
3039 val32 |= 0x77;
59b74397 3040 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3a4be6a0
JS		 3041
3042 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3043 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3044 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
f0d9f5e9
JS		 3045}
3046
26f1fad2
JS		 3047static int
3048rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
3049{
3050 int i, ret;
3051 u16 reg;
3052 u8 val;
3053
3054 for (i = 0; ; i++) {
3055 reg = array[i].reg;
3056 val = array[i].val;
3057
3058 if (reg == 0xffff && val == 0xff)
3059 break;
3060
3061 ret = rtl8xxxu_write8(priv, reg, val);
3062 if (ret != 1) {
3063 dev_warn(&priv->udev->dev,
3064 "Failed to initialize MAC\n");
3065 return -EAGAIN;
3066 }
3067 }
3068
8baf670b
JS		 3069 if (priv->rtlchip != 0x8723b)
3070 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
26f1fad2
JS		 3071
3072 return 0;
3073}
3074
3075static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3076 struct rtl8xxxu_reg32val *array)
3077{
3078 int i, ret;
3079 u16 reg;
3080 u32 val;
3081
3082 for (i = 0; ; i++) {
3083 reg = array[i].reg;
3084 val = array[i].val;
3085
3086 if (reg == 0xffff && val == 0xffffffff)
3087 break;
3088
3089 ret = rtl8xxxu_write32(priv, reg, val);
3090 if (ret != sizeof(val)) {
3091 dev_warn(&priv->udev->dev,
3092 "Failed to initialize PHY\n");
3093 return -EAGAIN;
3094 }
3095 udelay(1);
3096 }
3097
3098 return 0;
3099}
3100
3101/*
3102 * Most of this is black magic retrieved from the old rtl8723au driver
3103 */
3104static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3105{
3106 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
04313eb4 3107 u16 val16;
26f1fad2
JS		 3108 u32 val32;
3109
3110 /*
3111 * Todo: The vendor driver maintains a table of PHY register
3112 * addresses, which is initialized here. Do we need this?
3113 */
3114
3ca7b32c 3115 if (priv->rtlchip == 0x8723b) {
8baf670b
JS		 3116 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3117 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB |
3118 SYS_FUNC_DIO_RF;
3119 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3120
3ca7b32c
JS		 3121 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3122 } else {
3123 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3124 udelay(2);
3125 val8 |= AFE_PLL_320_ENABLE;
3126 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3127 udelay(2);
3128
3129 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3130 udelay(2);
26f1fad2 3131
8baf670b
JS		 3132 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3133 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3134 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3135 }
26f1fad2 3136
04313eb4
JS		 3137 if (priv->rtlchip != 0x8723b) {
3138 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
3139 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3140 val32 &= ~AFE_XTAL_RF_GATE;
3141 if (priv->has_bluetooth)
3142 val32 &= ~AFE_XTAL_BT_GATE;
3143 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
3144 }
26f1fad2
JS		 3145
3146 /* 6. 0x1f[7:0] = 0x07 */
3147 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3148 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3149
3150 if (priv->hi_pa)
3151 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3152 else if (priv->tx_paths == 2)
3153 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
8baf670b
JS		 3154 else if (priv->rtlchip == 0x8723b) {
3155 /*
3156 * Why?
3157 */
3158 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3159 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
36c32588 3160 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
8baf670b 3161 } else
26f1fad2
JS		 3162 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3163
3164
3165 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
3166 priv->vendor_umc && priv->chip_cut == 1)
3167 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
3168
3169 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3170 /*
3171 * For 1T2R boards, patch the registers.
3172 *
3173 * It looks like 8191/2 1T2R boards use path B for TX
3174 */
3175 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3176 val32 &= ~(BIT(0) | BIT(1));
3177 val32 |= BIT(1);
3178 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3179
3180 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3181 val32 &= ~0x300033;
3182 val32 |= 0x200022;
3183 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3184
3185 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
3186 val32 &= 0xff000000;
3187 val32 |= 0x45000000;
3188 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3189
3190 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3191 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3192 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3193 OFDM_RF_PATH_TX_B);
3194 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3195
3196 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3197 val32 &= ~(BIT(4) | BIT(5));
3198 val32 |= BIT(4);
3199 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3200
3201 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3202 val32 &= ~(BIT(27) | BIT(26));
3203 val32 |= BIT(27);
3204 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3205
3206 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3207 val32 &= ~(BIT(27) | BIT(26));
3208 val32 |= BIT(27);
3209 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3210
3211 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3212 val32 &= ~(BIT(27) | BIT(26));
3213 val32 |= BIT(27);
3214 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3215
3216 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3217 val32 &= ~(BIT(27) | BIT(26));
3218 val32 |= BIT(27);
3219 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3220
3221 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3222 val32 &= ~(BIT(27) | BIT(26));
3223 val32 |= BIT(27);
3224 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3225 }
3226
b9f498e1
JS		 3227 if (priv->rtlchip == 0x8723b)
3228 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
3229 else if (priv->hi_pa)
26f1fad2
JS		 3230 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3231 else
3232 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
3233
4ef22eb9 3234 if (priv->has_xtalk) {
26f1fad2
JS		 3235 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3236
4ef22eb9 3237 val8 = priv->xtalk;
26f1fad2
JS		 3238 val32 &= 0xff000fff;
3239 val32 |= ((val8 | (val8 << 6)) << 12);
3240
3241 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3242 }
3243
a0e262bc
JS		 3244 if (priv->rtlchip != 0x8723bu) {
3245 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3246 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3247 ldohci12 = 0x57;
3248 lpldo = 1;
3249 val32 = (lpldo << 24) | (ldohci12 << 16) |
3250 (ldov12d << 8) | ldoa15;
3251
3252 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
3253 }
26f1fad2
JS		 3254
3255 return 0;
3256}
3257
3258static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3259 struct rtl8xxxu_rfregval *array,
3260 enum rtl8xxxu_rfpath path)
3261{
3262 int i, ret;
3263 u8 reg;
3264 u32 val;
3265
3266 for (i = 0; ; i++) {
3267 reg = array[i].reg;
3268 val = array[i].val;
3269
3270 if (reg == 0xff && val == 0xffffffff)
3271 break;
3272
3273 switch (reg) {
3274 case 0xfe:
3275 msleep(50);
3276 continue;
3277 case 0xfd:
3278 mdelay(5);
3279 continue;
3280 case 0xfc:
3281 mdelay(1);
3282 continue;
3283 case 0xfb:
3284 udelay(50);
3285 continue;
3286 case 0xfa:
3287 udelay(5);
3288 continue;
3289 case 0xf9:
3290 udelay(1);
3291 continue;
3292 }
3293
26f1fad2
JS		 3294 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3295 if (ret) {
3296 dev_warn(&priv->udev->dev,
3297 "Failed to initialize RF\n");
3298 return -EAGAIN;
3299 }
3300 udelay(1);
3301 }
3302
3303 return 0;
3304}
3305
3306static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3307 struct rtl8xxxu_rfregval *table,
3308 enum rtl8xxxu_rfpath path)
3309{
3310 u32 val32;
3311 u16 val16, rfsi_rfenv;
3312 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3313
3314 switch (path) {
3315 case RF_A:
3316 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3317 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3318 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3319 break;
3320 case RF_B:
3321 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3322 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3323 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3324 break;
3325 default:
3326 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3327 __func__, path + 'A');
3328 return -EINVAL;
3329 }
3330 /* For path B, use XB */
3331 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3332 rfsi_rfenv &= FPGA0_RF_RFENV;
3333
3334 /*
3335 * These two we might be able to optimize into one
3336 */
3337 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3338 val32 |= BIT(20); /* 0x10 << 16 */
3339 rtl8xxxu_write32(priv, reg_int_oe, val32);
3340 udelay(1);
3341
3342 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3343 val32 |= BIT(4);
3344 rtl8xxxu_write32(priv, reg_int_oe, val32);
3345 udelay(1);
3346
3347 /*
3348 * These two we might be able to optimize into one
3349 */
3350 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3351 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
3352 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3353 udelay(1);
3354
3355 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
3356 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
3357 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
3358 udelay(1);
3359
3360 rtl8xxxu_init_rf_regs(priv, table, path);
3361
3362 /* For path B, use XB */
3363 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
3364 val16 &= ~FPGA0_RF_RFENV;
3365 val16 |= rfsi_rfenv;
3366 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
3367
3368 return 0;
3369}
3370
3371static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
3372{
3373 int ret = -EBUSY;
3374 int count = 0;
3375 u32 value;
3376
3377 value = LLT_OP_WRITE | address << 8 | data;
3378
3379 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
3380
3381 do {
3382 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
3383 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
3384 ret = 0;
3385 break;
3386 }
3387 } while (count++ < 20);
3388
3389 return ret;
3390}
3391
3392static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3393{
3394 int ret;
3395 int i;
3396
3397 for (i = 0; i < last_tx_page; i++) {
3398 ret = rtl8xxxu_llt_write(priv, i, i + 1);
3399 if (ret)
3400 goto exit;
3401 }
3402
3403 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
3404 if (ret)
3405 goto exit;
3406
3407 /* Mark remaining pages as a ring buffer */
3408 for (i = last_tx_page + 1; i < 0xff; i++) {
3409 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
3410 if (ret)
3411 goto exit;
3412 }
3413
3414 /* Let last entry point to the start entry of ring buffer */
3415 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
3416 if (ret)
3417 goto exit;
3418
3419exit:
3420 return ret;
3421}
3422
74b99bed
JS		 3423static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
3424{
3425 u32 val32;
3426 int ret = 0;
3427 int i;
3428
3429 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
74b99bed
JS		 3430 val32 |= AUTO_LLT_INIT_LLT;
3431 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
3432
3433 for (i = 500; i; i--) {
3434 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
3435 if (!(val32 & AUTO_LLT_INIT_LLT))
3436 break;
3437 usleep_range(2, 4);
3438 }
3439
4de24819 3440 if (!i) {
74b99bed
JS		 3441 ret = -EBUSY;
3442 dev_warn(&priv->udev->dev, "LLT table init failed\n");
3443 }
74b99bed
JS		 3444
3445 return ret;
3446}
3447
26f1fad2
JS		 3448static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
3449{
3450 u16 val16, hi, lo;
3451 u16 hiq, mgq, bkq, beq, viq, voq;
3452 int hip, mgp, bkp, bep, vip, vop;
3453 int ret = 0;
3454
3455 switch (priv->ep_tx_count) {
3456 case 1:
3457 if (priv->ep_tx_high_queue) {
3458 hi = TRXDMA_QUEUE_HIGH;
3459 } else if (priv->ep_tx_low_queue) {
3460 hi = TRXDMA_QUEUE_LOW;
3461 } else if (priv->ep_tx_normal_queue) {
3462 hi = TRXDMA_QUEUE_NORMAL;
3463 } else {
3464 hi = 0;
3465 ret = -EINVAL;
3466 }
3467
3468 hiq = hi;
3469 mgq = hi;
3470 bkq = hi;
3471 beq = hi;
3472 viq = hi;
3473 voq = hi;
3474
3475 hip = 0;
3476 mgp = 0;
3477 bkp = 0;
3478 bep = 0;
3479 vip = 0;
3480 vop = 0;
3481 break;
3482 case 2:
3483 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
3484 hi = TRXDMA_QUEUE_HIGH;
3485 lo = TRXDMA_QUEUE_LOW;
3486 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
3487 hi = TRXDMA_QUEUE_NORMAL;
3488 lo = TRXDMA_QUEUE_LOW;
3489 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
3490 hi = TRXDMA_QUEUE_HIGH;
3491 lo = TRXDMA_QUEUE_NORMAL;
3492 } else {
3493 ret = -EINVAL;
3494 hi = 0;
3495 lo = 0;
3496 }
3497
3498 hiq = hi;
3499 mgq = hi;
3500 bkq = lo;
3501 beq = lo;
3502 viq = hi;
3503 voq = hi;
3504
3505 hip = 0;
3506 mgp = 0;
3507 bkp = 1;
3508 bep = 1;
3509 vip = 0;
3510 vop = 0;
3511 break;
3512 case 3:
3513 beq = TRXDMA_QUEUE_LOW;
3514 bkq = TRXDMA_QUEUE_LOW;
3515 viq = TRXDMA_QUEUE_NORMAL;
3516 voq = TRXDMA_QUEUE_HIGH;
3517 mgq = TRXDMA_QUEUE_HIGH;
3518 hiq = TRXDMA_QUEUE_HIGH;
3519
3520 hip = hiq ^ 3;
3521 mgp = mgq ^ 3;
3522 bkp = bkq ^ 3;
3523 bep = beq ^ 3;
3524 vip = viq ^ 3;
3525 vop = viq ^ 3;
3526 break;
3527 default:
3528 ret = -EINVAL;
3529 }
3530
3531 /*
3532 * None of the vendor drivers are configuring the beacon
3533 * queue here .... why?
3534 */
3535 if (!ret) {
3536 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
3537 val16 &= 0x7;
3538 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
3539 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
3540 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
3541 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
3542 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
3543 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
3544 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
3545
3546 priv->pipe_out[TXDESC_QUEUE_VO] =
3547 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
3548 priv->pipe_out[TXDESC_QUEUE_VI] =
3549 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
3550 priv->pipe_out[TXDESC_QUEUE_BE] =
3551 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
3552 priv->pipe_out[TXDESC_QUEUE_BK] =
3553 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
3554 priv->pipe_out[TXDESC_QUEUE_BEACON] =
3555 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3556 priv->pipe_out[TXDESC_QUEUE_MGNT] =
3557 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
3558 priv->pipe_out[TXDESC_QUEUE_HIGH] =
3559 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
3560 priv->pipe_out[TXDESC_QUEUE_CMD] =
3561 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
3562 }
3563
3564 return ret;
3565}
3566
3567static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
3568 bool iqk_ok, int result[][8],
3569 int candidate, bool tx_only)
3570{
3571 u32 oldval, x, tx0_a, reg;
3572 int y, tx0_c;
3573 u32 val32;
3574
3575 if (!iqk_ok)
3576 return;
3577
3578 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3579 oldval = val32 >> 22;
3580
3581 x = result[candidate][0];
3582 if ((x & 0x00000200) != 0)
3583 x = x | 0xfffffc00;
3584 tx0_a = (x * oldval) >> 8;
3585
3586 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3587 val32 &= ~0x3ff;
3588 val32 |= tx0_a;
3589 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3590
3591 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3592 val32 &= ~BIT(31);
3593 if ((x * oldval >> 7) & 0x1)
3594 val32 |= BIT(31);
3595 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3596
3597 y = result[candidate][1];
3598 if ((y & 0x00000200) != 0)
3599 y = y | 0xfffffc00;
3600 tx0_c = (y * oldval) >> 8;
3601
3602 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
3603 val32 &= ~0xf0000000;
3604 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
3605 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
3606
3607 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
3608 val32 &= ~0x003f0000;
3609 val32 |= ((tx0_c & 0x3f) << 16);
3610 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
3611
3612 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3613 val32 &= ~BIT(29);
3614 if ((y * oldval >> 7) & 0x1)
3615 val32 |= BIT(29);
3616 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3617
3618 if (tx_only) {
3619 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3620 return;
3621 }
3622
3623 reg = result[candidate][2];
3624
3625 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3626 val32 &= ~0x3ff;
3627 val32 |= (reg & 0x3ff);
3628 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3629
3630 reg = result[candidate][3] & 0x3F;
3631
3632 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
3633 val32 &= ~0xfc00;
3634 val32 |= ((reg << 10) & 0xfc00);
3635 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
3636
3637 reg = (result[candidate][3] >> 6) & 0xF;
3638
3639 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
3640 val32 &= ~0xf0000000;
3641 val32 |= (reg << 28);
3642 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
3643}
3644
3645static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
3646 bool iqk_ok, int result[][8],
3647 int candidate, bool tx_only)
3648{
3649 u32 oldval, x, tx1_a, reg;
3650 int y, tx1_c;
3651 u32 val32;
3652
3653 if (!iqk_ok)
3654 return;
3655
3656 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3657 oldval = val32 >> 22;
3658
3659 x = result[candidate][4];
3660 if ((x & 0x00000200) != 0)
3661 x = x | 0xfffffc00;
3662 tx1_a = (x * oldval) >> 8;
3663
3664 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3665 val32 &= ~0x3ff;
3666 val32 |= tx1_a;
3667 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3668
3669 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3670 val32 &= ~BIT(27);
3671 if ((x * oldval >> 7) & 0x1)
3672 val32 |= BIT(27);
3673 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3674
3675 y = result[candidate][5];
3676 if ((y & 0x00000200) != 0)
3677 y = y | 0xfffffc00;
3678 tx1_c = (y * oldval) >> 8;
3679
3680 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3681 val32 &= ~0xf0000000;
3682 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3683 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3684
3685 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3686 val32 &= ~0x003f0000;
3687 val32 |= ((tx1_c & 0x3f) << 16);
3688 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3689
3690 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3691 val32 &= ~BIT(25);
3692 if ((y * oldval >> 7) & 0x1)
3693 val32 |= BIT(25);
3694 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3695
3696 if (tx_only) {
3697 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3698 return;
3699 }
3700
3701 reg = result[candidate][6];
3702
3703 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3704 val32 &= ~0x3ff;
3705 val32 |= (reg & 0x3ff);
3706 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3707
3708 reg = result[candidate][7] & 0x3f;
3709
3710 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3711 val32 &= ~0xfc00;
3712 val32 |= ((reg << 10) & 0xfc00);
3713 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3714
3715 reg = (result[candidate][7] >> 6) & 0xf;
3716
3717 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3718 val32 &= ~0x0000f000;
3719 val32 |= (reg << 12);
3720 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3721}
3722
3723#define MAX_TOLERANCE 5
3724
3725static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3726 int result[][8], int c1, int c2)
3727{
3728 u32 i, j, diff, simubitmap, bound = 0;
3729 int candidate[2] = {-1, -1}; /* for path A and path B */
3730 bool retval = true;
3731
3732 if (priv->tx_paths > 1)
3733 bound = 8;
3734 else
3735 bound = 4;
3736
3737 simubitmap = 0;
3738
3739 for (i = 0; i < bound; i++) {
3740 diff = (result[c1][i] > result[c2][i]) ?
3741 (result[c1][i] - result[c2][i]) :
3742 (result[c2][i] - result[c1][i]);
3743 if (diff > MAX_TOLERANCE) {
3744 if ((i == 2 || i == 6) && !simubitmap) {
3745 if (result[c1][i] + result[c1][i + 1] == 0)
3746 candidate[(i / 4)] = c2;
3747 else if (result[c2][i] + result[c2][i + 1] == 0)
3748 candidate[(i / 4)] = c1;
3749 else
3750 simubitmap = simubitmap | (1 << i);
3751 } else {
3752 simubitmap = simubitmap | (1 << i);
3753 }
3754 }
3755 }
3756
3757 if (simubitmap == 0) {
3758 for (i = 0; i < (bound / 4); i++) {
3759 if (candidate[i] >= 0) {
3760 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3761 result[3][j] = result[candidate[i]][j];
3762 retval = false;
3763 }
3764 }
3765 return retval;
3766 } else if (!(simubitmap & 0x0f)) {
3767 /* path A OK */
3768 for (i = 0; i < 4; i++)
3769 result[3][i] = result[c1][i];
3770 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3771 /* path B OK */
3772 for (i = 4; i < 8; i++)
3773 result[3][i] = result[c1][i];
3774 }
3775
3776 return false;
3777}
3778
e1547c53
JS		 3779static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
3780 int result[][8], int c1, int c2)
3781{
3782 u32 i, j, diff, simubitmap, bound = 0;
3783 int candidate[2] = {-1, -1}; /* for path A and path B */
3784 int tmp1, tmp2;
3785 bool retval = true;
3786
3787 if (priv->tx_paths > 1)
3788 bound = 8;
3789 else
3790 bound = 4;
3791
3792 simubitmap = 0;
3793
3794 for (i = 0; i < bound; i++) {
3795 if (i & 1) {
3796 if ((result[c1][i] & 0x00000200))
3797 tmp1 = result[c1][i] | 0xfffffc00;
3798 else
3799 tmp1 = result[c1][i];
3800
3801 if ((result[c2][i]& 0x00000200))
3802 tmp2 = result[c2][i] | 0xfffffc00;
3803 else
3804 tmp2 = result[c2][i];
3805 } else {
3806 tmp1 = result[c1][i];
3807 tmp2 = result[c2][i];
3808 }
3809
3810 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
3811
3812 if (diff > MAX_TOLERANCE) {
3813 if ((i == 2 || i == 6) && !simubitmap) {
3814 if (result[c1][i] + result[c1][i + 1] == 0)
3815 candidate[(i / 4)] = c2;
3816 else if (result[c2][i] + result[c2][i + 1] == 0)
3817 candidate[(i / 4)] = c1;
3818 else
3819 simubitmap = simubitmap | (1 << i);
3820 } else {
3821 simubitmap = simubitmap | (1 << i);
3822 }
3823 }
3824 }
3825
3826 if (simubitmap == 0) {
3827 for (i = 0; i < (bound / 4); i++) {
3828 if (candidate[i] >= 0) {
3829 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3830 result[3][j] = result[candidate[i]][j];
3831 retval = false;
3832 }
3833 }
3834 return retval;
3835 } else {
3836 if (!(simubitmap & 0x03)) {
3837 /* path A TX OK */
3838 for (i = 0; i < 2; i++)
3839 result[3][i] = result[c1][i];
3840 }
3841
3842 if (!(simubitmap & 0x0c)) {
3843 /* path A RX OK */
3844 for (i = 2; i < 4; i++)
3845 result[3][i] = result[c1][i];
3846 }
3847
3848 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3849 /* path B RX OK */
3850 for (i = 4; i < 6; i++)
3851 result[3][i] = result[c1][i];
3852 }
3853
3854 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3855 /* path B RX OK */
3856 for (i = 6; i < 8; i++)
3857 result[3][i] = result[c1][i];
3858 }
3859 }
3860
3861 return false;
3862}
3863
26f1fad2
JS		 3864static void
3865rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3866{
3867 int i;
3868
3869 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3870 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3871
3872 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3873}
3874
3875static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3876 const u32 *reg, u32 *backup)
3877{
3878 int i;
3879
3880 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3881 rtl8xxxu_write8(priv, reg[i], backup[i]);
3882
3883 rtl8xxxu_write32(priv, reg[i], backup[i]);
3884}
3885
3886static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3887 u32 *backup, int count)
3888{
3889 int i;
3890
3891 for (i = 0; i < count; i++)
3892 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3893}
3894
3895static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3896 u32 *backup, int count)
3897{
3898 int i;
3899
3900 for (i = 0; i < count; i++)
3901 rtl8xxxu_write32(priv, regs[i], backup[i]);
3902}
3903
3904
3905static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3906 bool path_a_on)
3907{
3908 u32 path_on;
3909 int i;
3910
26f1fad2 3911 if (priv->tx_paths == 1) {
8634af5e
JS		 3912 path_on = priv->fops->adda_1t_path_on;
3913 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
26f1fad2 3914 } else {
8634af5e
JS		 3915 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3916 priv->fops->adda_2t_path_on_b;
3917
26f1fad2
JS		 3918 rtl8xxxu_write32(priv, regs[0], path_on);
3919 }
3920
3921 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3922 rtl8xxxu_write32(priv, regs[i], path_on);
3923}
3924
3925static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3926 const u32 *regs, u32 *backup)
3927{
3928 int i = 0;
3929
3930 rtl8xxxu_write8(priv, regs[i], 0x3f);
3931
3932 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3933 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3934
3935 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3936}
3937
3938static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3939{
3940 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3941 int result = 0;
3942
3943 /* path-A IQK setting */
3944 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3945 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3946 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3947
3948 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3949 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3950 0x28160502;
3951 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3952
3953 /* path-B IQK setting */
3954 if (priv->rf_paths > 1) {
3955 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3956 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3957 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3958 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3959 }
3960
3961 /* LO calibration setting */
3962 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3963
3964 /* One shot, path A LOK & IQK */
3965 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3966 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3967
3968 mdelay(1);
3969
3970 /* Check failed */
3971 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3972 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3973 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3974 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3975
3976 if (!(reg_eac & BIT(28)) &&
3977 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3978 ((reg_e9c & 0x03ff0000) != 0x00420000))
3979 result |= 0x01;
3980 else /* If TX not OK, ignore RX */
3981 goto out;
3982
3983 /* If TX is OK, check whether RX is OK */
3984 if (!(reg_eac & BIT(27)) &&
3985 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3986 ((reg_eac & 0x03ff0000) != 0x00360000))
3987 result |= 0x02;
3988 else
3989 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3990 __func__);
3991out:
3992 return result;
3993}
3994
3995static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3996{
3997 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3998 int result = 0;
3999
4000 /* One shot, path B LOK & IQK */
4001 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4002 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4003
4004 mdelay(1);
4005
4006 /* Check failed */
4007 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4008 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4009 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4010 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4011 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4012
4013 if (!(reg_eac & BIT(31)) &&
4014 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4015 ((reg_ebc & 0x03ff0000) != 0x00420000))
4016 result |= 0x01;
4017 else
4018 goto out;
4019
4020 if (!(reg_eac & BIT(30)) &&
4021 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4022 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4023 result |= 0x02;
4024 else
4025 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4026 __func__);
4027out:
4028 return result;
4029}
4030
e1547c53
JS		 4031static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4032{
4033 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4034 int result = 0;
4035
4036 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4037
4038 /*
4039 * Leave IQK mode
4040 */
4041 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4042 val32 &= 0x000000ff;
4043 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4044
4045 /*
4046 * Enable path A PA in TX IQK mode
4047 */
4048 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4049 val32 |= 0x80000;
4050 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4051 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4052 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4053 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4054
4055 /*
4056 * Tx IQK setting
4057 */
4058 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4059 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4060
4061 /* path-A IQK setting */
4062 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4063 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4064 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4065 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4066
4067 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4068 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4069 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4070 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4071
4072 /* LO calibration setting */
4073 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4074
4075 /*
4076 * Enter IQK mode
4077 */
4078 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4079 val32 &= 0x000000ff;
4080 val32 |= 0x80800000;
4081 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4082
4083 /*
4084 * The vendor driver indicates the USB module is always using
4085 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4086 */
4087 if (priv->rf_paths > 1)
4088 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4089 else
4090 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4091
4092 /*
4093 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4094 * No trace of this in the 8192eu or 8188eu vendor drivers.
4095 */
4096 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4097
4098 /* One shot, path A LOK & IQK */
4099 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4100 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4101
4102 mdelay(1);
4103
4104 /* Restore Ant Path */
4105 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4106#ifdef RTL8723BU_BT
4107 /* GNT_BT = 1 */
4108 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4109#endif
4110
4111 /*
4112 * Leave IQK mode
4113 */
4114 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4115 val32 &= 0x000000ff;
4116 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4117
4118 /* Check failed */
4119 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4120 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4121 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4122
4123 val32 = (reg_e9c >> 16) & 0x3ff;
4124 if (val32 & 0x200)
4125 val32 = 0x400 - val32;
4126
4127 if (!(reg_eac & BIT(28)) &&
4128 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4129 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4130 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4131 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4132 val32 < 0xf)
4133 result |= 0x01;
4134 else /* If TX not OK, ignore RX */
4135 goto out;
4136
4137out:
4138 return result;
4139}
4140
4141static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4142{
4143 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4144 int result = 0;
4145
4146 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4147
4148 /*
4149 * Leave IQK mode
4150 */
4151 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4152 val32 &= 0x000000ff;
4153 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4154
4155 /*
4156 * Enable path A PA in TX IQK mode
4157 */
4158 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4159 val32 |= 0x80000;
4160 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4161 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4162 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4163 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4164
4165 /*
4166 * Tx IQK setting
4167 */
4168 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4169 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4170
4171 /* path-A IQK setting */
4172 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4173 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4174 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4175 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4176
4177 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4178 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4179 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4180 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4181
4182 /* LO calibration setting */
4183 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4184
4185 /*
4186 * Enter IQK mode
4187 */
4188 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4189 val32 &= 0x000000ff;
4190 val32 |= 0x80800000;
4191 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4192
4193 /*
4194 * The vendor driver indicates the USB module is always using
4195 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4196 */
4197 if (priv->rf_paths > 1)
4198 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4199 else
4200 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4201
4202 /*
4203 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4204 * No trace of this in the 8192eu or 8188eu vendor drivers.
4205 */
4206 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4207
4208 /* One shot, path A LOK & IQK */
4209 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4210 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4211
4212 mdelay(1);
4213
4214 /* Restore Ant Path */
4215 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4216#ifdef RTL8723BU_BT
4217 /* GNT_BT = 1 */
4218 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4219#endif
4220
4221 /*
4222 * Leave IQK mode
4223 */
4224 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4225 val32 &= 0x000000ff;
4226 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4227
4228 /* Check failed */
4229 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4230 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4231 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4232
4233 val32 = (reg_e9c >> 16) & 0x3ff;
4234 if (val32 & 0x200)
4235 val32 = 0x400 - val32;
4236
4237 if (!(reg_eac & BIT(28)) &&
4238 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4239 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4240 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4241 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4242 val32 < 0xf)
4243 result |= 0x01;
4244 else /* If TX not OK, ignore RX */
4245 goto out;
4246
4247 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4248 ((reg_e9c & 0x3ff0000) >> 16);
4249 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4250
4251 /*
4252 * Modify RX IQK mode
4253 */
4254 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4255 val32 &= 0x000000ff;
4256 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4257 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4258 val32 |= 0x80000;
4259 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4260 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4261 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4262 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4263
4264 /*
4265 * PA, PAD setting
4266 */
4267 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4268 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4269
4270 /*
4271 * RX IQK setting
4272 */
4273 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4274
4275 /* path-A IQK setting */
4276 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
4277 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
4278 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4279 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4280
4281 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
4282 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
4283 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4284 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4285
4286 /* LO calibration setting */
4287 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
4288
4289 /*
4290 * Enter IQK mode
4291 */
4292 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4293 val32 &= 0x000000ff;
4294 val32 |= 0x80800000;
4295 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4296
4297 if (priv->rf_paths > 1)
4298 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4299 else
4300 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4301
4302 /*
4303 * Disable BT
4304 */
4305 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4306
4307 /* One shot, path A LOK & IQK */
4308 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4309 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4310
4311 mdelay(1);
4312
4313 /* Restore Ant Path */
4314 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4315#ifdef RTL8723BU_BT
4316 /* GNT_BT = 1 */
4317 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4318#endif
4319
4320 /*
4321 * Leave IQK mode
4322 */
4323 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4324 val32 &= 0x000000ff;
4325 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4326
4327 /* Check failed */
4328 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4329 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4330
4331 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
4332
4333 val32 = (reg_eac >> 16) & 0x3ff;
4334 if (val32 & 0x200)
4335 val32 = 0x400 - val32;
4336
4337 if (!(reg_eac & BIT(27)) &&
4338 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4339 ((reg_eac & 0x03ff0000) != 0x00360000) &&
4340 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
4341 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
4342 val32 < 0xf)
4343 result |= 0x02;
4344 else /* If TX not OK, ignore RX */
4345 goto out;
4346out:
4347 return result;
4348}
4349
4350#ifdef RTL8723BU_PATH_B
4351static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv)
4352{
4353 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel;
4354 int result = 0;
4355
4356 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4357
4358 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4359 val32 &= 0x000000ff;
4360 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4361
4362 /* One shot, path B LOK & IQK */
4363 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4364 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4365
4366 mdelay(1);
4367
4368 /* Check failed */
4369 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4370 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4371 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4372 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4373 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4374
4375 if (!(reg_eac & BIT(31)) &&
4376 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4377 ((reg_ebc & 0x03ff0000) != 0x00420000))
4378 result |= 0x01;
4379 else
4380 goto out;
4381
4382 if (!(reg_eac & BIT(30)) &&
4383 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4384 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4385 result |= 0x02;
4386 else
4387 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4388 __func__);
4389out:
4390 return result;
4391}
4392#endif
4393
26f1fad2
JS		 4394static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4395 int result[][8], int t)
4396{
4397 struct device *dev = &priv->udev->dev;
4398 u32 i, val32;
4399 int path_a_ok, path_b_ok;
4400 int retry = 2;
4401 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4402 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4403 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4404 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4405 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4406 REG_TX_TO_TX, REG_RX_CCK,
4407 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4408 REG_RX_TO_RX, REG_STANDBY,
4409 REG_SLEEP, REG_PMPD_ANAEN
4410 };
4411 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4412 REG_TXPAUSE, REG_BEACON_CTRL,
4413 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4414 };
4415 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4416 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4417 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4418 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4419 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4420 };
4421
4422 /*
4423 * Note: IQ calibration must be performed after loading
4424 * PHY_REG.txt , and radio_a, radio_b.txt
4425 */
4426
4427 if (t == 0) {
4428 /* Save ADDA parameters, turn Path A ADDA on */
4429 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4430 RTL8XXXU_ADDA_REGS);
4431 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4432 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4433 priv->bb_backup, RTL8XXXU_BB_REGS);
4434 }
4435
4436 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4437
4438 if (t == 0) {
4439 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
4440 if (val32 & FPGA0_HSSI_PARM1_PI)
4441 priv->pi_enabled = 1;
4442 }
4443
4444 if (!priv->pi_enabled) {
4445 /* Switch BB to PI mode to do IQ Calibration. */
4446 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
4447 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
4448 }
4449
4450 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4451 val32 &= ~FPGA_RF_MODE_CCK;
4452 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4453
4454 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4455 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4456 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4457
4458 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
4459 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4460 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4461
4462 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
4463 val32 &= ~BIT(10);
4464 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
4465 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
4466 val32 &= ~BIT(10);
4467 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
4468
4469 if (priv->tx_paths > 1) {
4470 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4471 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
4472 }
4473
4474 /* MAC settings */
4475 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4476
4477 /* Page B init */
4478 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
4479
4480 if (priv->tx_paths > 1)
4481 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
4482
4483 /* IQ calibration setting */
4484 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4485 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4486 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4487
4488 for (i = 0; i < retry; i++) {
4489 path_a_ok = rtl8xxxu_iqk_path_a(priv);
4490 if (path_a_ok == 0x03) {
4491 val32 = rtl8xxxu_read32(priv,
4492 REG_TX_POWER_BEFORE_IQK_A);
4493 result[t][0] = (val32 >> 16) & 0x3ff;
4494 val32 = rtl8xxxu_read32(priv,
4495 REG_TX_POWER_AFTER_IQK_A);
4496 result[t][1] = (val32 >> 16) & 0x3ff;
4497 val32 = rtl8xxxu_read32(priv,
4498 REG_RX_POWER_BEFORE_IQK_A_2);
4499 result[t][2] = (val32 >> 16) & 0x3ff;
4500 val32 = rtl8xxxu_read32(priv,
4501 REG_RX_POWER_AFTER_IQK_A_2);
4502 result[t][3] = (val32 >> 16) & 0x3ff;
4503 break;
4504 } else if (i == (retry - 1) && path_a_ok == 0x01) {
4505 /* TX IQK OK */
4506 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
4507 __func__);
4508
4509 val32 = rtl8xxxu_read32(priv,
4510 REG_TX_POWER_BEFORE_IQK_A);
4511 result[t][0] = (val32 >> 16) & 0x3ff;
4512 val32 = rtl8xxxu_read32(priv,
4513 REG_TX_POWER_AFTER_IQK_A);
4514 result[t][1] = (val32 >> 16) & 0x3ff;
4515 }
4516 }
4517
4518 if (!path_a_ok)
4519 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
4520
4521 if (priv->tx_paths > 1) {
4522 /*
4523 * Path A into standby
4524 */
4525 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
4526 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
4527 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
4528
4529 /* Turn Path B ADDA on */
4530 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4531
4532 for (i = 0; i < retry; i++) {
4533 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4534 if (path_b_ok == 0x03) {
4535 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4536 result[t][4] = (val32 >> 16) & 0x3ff;
4537 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4538 result[t][5] = (val32 >> 16) & 0x3ff;
4539 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4540 result[t][6] = (val32 >> 16) & 0x3ff;
4541 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4542 result[t][7] = (val32 >> 16) & 0x3ff;
4543 break;
4544 } else if (i == (retry - 1) && path_b_ok == 0x01) {
4545 /* TX IQK OK */
4546 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4547 result[t][4] = (val32 >> 16) & 0x3ff;
4548 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4549 result[t][5] = (val32 >> 16) & 0x3ff;
4550 }
4551 }
4552
4553 if (!path_b_ok)
4554 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4555 }
4556
4557 /* Back to BB mode, load original value */
4558 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
4559
4560 if (t) {
4561 if (!priv->pi_enabled) {
4562 /*
4563 * Switch back BB to SI mode after finishing
4564 * IQ Calibration
4565 */
4566 val32 = 0x01000000;
4567 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
4568 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
4569 }
4570
4571 /* Reload ADDA power saving parameters */
4572 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4573 RTL8XXXU_ADDA_REGS);
4574
4575 /* Reload MAC parameters */
4576 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4577
4578 /* Reload BB parameters */
4579 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4580 priv->bb_backup, RTL8XXXU_BB_REGS);
4581
4582 /* Restore RX initial gain */
4583 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
4584
4585 if (priv->tx_paths > 1) {
4586 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
4587 0x00032ed3);
4588 }
4589
4590 /* Load 0xe30 IQC default value */
4591 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4592 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4593 }
4594}
4595
e1547c53
JS		 4596static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
4597 int result[][8], int t)
4598{
4599 struct device *dev = &priv->udev->dev;
4600 u32 i, val32;
4601 int path_a_ok /*, path_b_ok */;
4602 int retry = 2;
4603 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
4604 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
4605 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
4606 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
4607 REG_TX_OFDM_BBON, REG_TX_TO_RX,
4608 REG_TX_TO_TX, REG_RX_CCK,
4609 REG_RX_OFDM, REG_RX_WAIT_RIFS,
4610 REG_RX_TO_RX, REG_STANDBY,
4611 REG_SLEEP, REG_PMPD_ANAEN
4612 };
4613 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
4614 REG_TXPAUSE, REG_BEACON_CTRL,
4615 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
4616 };
4617 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
4618 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
4619 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
4620 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
4621 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
4622 };
4623 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
4624 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
4625
4626 /*
4627 * Note: IQ calibration must be performed after loading
4628 * PHY_REG.txt , and radio_a, radio_b.txt
4629 */
4630
4631 if (t == 0) {
4632 /* Save ADDA parameters, turn Path A ADDA on */
4633 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
4634 RTL8XXXU_ADDA_REGS);
4635 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4636 rtl8xxxu_save_regs(priv, iqk_bb_regs,
4637 priv->bb_backup, RTL8XXXU_BB_REGS);
4638 }
4639
4640 rtl8xxxu_path_adda_on(priv, adda_regs, true);
4641
4642 /* MAC settings */
4643 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
4644
4645 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
4646 val32 |= 0x0f000000;
4647 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
4648
4649 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
4650 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
4651 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
4652
4653#ifdef RTL8723BU_PATH_B
4654 /* Set RF mode to standby Path B */
4655 if (priv->tx_paths > 1)
4656 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000);
4657#endif
4658
4659#if 0
4660 /* Page B init */
4661 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000);
4662
4663 if (priv->tx_paths > 1)
4664 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000);
4665#endif
4666
4667 /*
4668 * RX IQ calibration setting for 8723B D cut large current issue
4669 * when leaving IPS
4670 */
4671 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4672 val32 &= 0x000000ff;
4673 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4674
4675 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4676 val32 |= 0x80000;
4677 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4678
4679 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4680 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4681 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4682
4683 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
4684 val32 |= 0x20;
4685 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
4686
4687 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
4688
4689 for (i = 0; i < retry; i++) {
4690 path_a_ok = rtl8723bu_iqk_path_a(priv);
4691 if (path_a_ok == 0x01) {
4692 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4693 val32 &= 0x000000ff;
4694 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4695
4696#if 0 /* Only needed in restore case, we may need this when going to suspend */
4697 priv->RFCalibrateInfo.TxLOK[RF_A] =
4698 rtl8xxxu_read_rfreg(priv, RF_A,
4699 RF6052_REG_TXM_IDAC);
4700#endif
4701
4702 val32 = rtl8xxxu_read32(priv,
4703 REG_TX_POWER_BEFORE_IQK_A);
4704 result[t][0] = (val32 >> 16) & 0x3ff;
4705 val32 = rtl8xxxu_read32(priv,
4706 REG_TX_POWER_AFTER_IQK_A);
4707 result[t][1] = (val32 >> 16) & 0x3ff;
4708
4709 break;
4710 }
4711 }
4712
4713 if (!path_a_ok)
4714 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
4715
4716 for (i = 0; i < retry; i++) {
4717 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
4718 if (path_a_ok == 0x03) {
4719 val32 = rtl8xxxu_read32(priv,
4720 REG_RX_POWER_BEFORE_IQK_A_2);
4721 result[t][2] = (val32 >> 16) & 0x3ff;
4722 val32 = rtl8xxxu_read32(priv,
4723 REG_RX_POWER_AFTER_IQK_A_2);
4724 result[t][3] = (val32 >> 16) & 0x3ff;
4725
4726 break;
4727 }
4728 }
4729
4730 if (!path_a_ok)
4731 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
4732
4733 if (priv->tx_paths > 1) {
4734#if 1
4735 dev_warn(dev, "%s: Path B not supported\n", __func__);
4736#else
4737
4738 /*
4739 * Path A into standby
4740 */
4741 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4742 val32 &= 0x000000ff;
4743 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4744 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
4745
4746 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4747 val32 &= 0x000000ff;
4748 val32 |= 0x80800000;
4749 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4750
4751 /* Turn Path B ADDA on */
4752 rtl8xxxu_path_adda_on(priv, adda_regs, false);
4753
4754 for (i = 0; i < retry; i++) {
4755 path_b_ok = rtl8xxxu_iqk_path_b(priv);
4756 if (path_b_ok == 0x03) {
4757 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4758 result[t][4] = (val32 >> 16) & 0x3ff;
4759 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4760 result[t][5] = (val32 >> 16) & 0x3ff;
4761 break;
4762 }
4763 }
4764
4765 if (!path_b_ok)
4766 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
4767
4768 for (i = 0; i < retry; i++) {
4769 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
4770 if (path_a_ok == 0x03) {
4771 val32 = rtl8xxxu_read32(priv,
4772 REG_RX_POWER_BEFORE_IQK_B_2);
4773 result[t][6] = (val32 >> 16) & 0x3ff;
4774 val32 = rtl8xxxu_read32(priv,
4775 REG_RX_POWER_AFTER_IQK_B_2);
4776 result[t][7] = (val32 >> 16) & 0x3ff;
4777 break;
4778 }
4779 }
4780
4781 if (!path_b_ok)
4782 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
4783#endif
4784 }
4785
4786 /* Back to BB mode, load original value */
4787 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4788 val32 &= 0x000000ff;
4789 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4790
4791 if (t) {
4792 /* Reload ADDA power saving parameters */
4793 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
4794 RTL8XXXU_ADDA_REGS);
4795
4796 /* Reload MAC parameters */
4797 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
4798
4799 /* Reload BB parameters */
4800 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
4801 priv->bb_backup, RTL8XXXU_BB_REGS);
4802
4803 /* Restore RX initial gain */
4804 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4805 val32 &= 0xffffff00;
4806 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
4807 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
4808
4809 if (priv->tx_paths > 1) {
4810 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
4811 val32 &= 0xffffff00;
4812 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4813 val32 | 0x50);
4814 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
4815 val32 | xb_agc);
4816 }
4817
4818 /* Load 0xe30 IQC default value */
4819 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
4820 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
4821 }
4822}
4823
c7a5a190
JS		 4824static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
4825{
4826 struct h2c_cmd h2c;
4827
4828 if (priv->fops->mbox_ext_width < 4)
4829 return;
4830
4831 memset(&h2c, 0, sizeof(struct h2c_cmd));
4832 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
4833 h2c.bt_wlan_calibration.data = start;
4834
4835 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
4836}
4837
e1547c53 4838static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 4839{
4840 struct device *dev = &priv->udev->dev;
4841 int result[4][8]; /* last is final result */
4842 int i, candidate;
4843 bool path_a_ok, path_b_ok;
4844 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4845 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4846 s32 reg_tmp = 0;
4847 bool simu;
4848
c7a5a190
JS		 4849 rtl8xxxu_prepare_calibrate(priv, 1);
4850
26f1fad2
JS		 4851 memset(result, 0, sizeof(result));
4852 candidate = -1;
4853
4854 path_a_ok = false;
4855 path_b_ok = false;
4856
4857 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4858
4859 for (i = 0; i < 3; i++) {
4860 rtl8xxxu_phy_iqcalibrate(priv, result, i);
4861
4862 if (i == 1) {
4863 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
4864 if (simu) {
4865 candidate = 0;
4866 break;
4867 }
4868 }
4869
4870 if (i == 2) {
4871 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
4872 if (simu) {
4873 candidate = 0;
4874 break;
4875 }
4876
4877 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
4878 if (simu) {
4879 candidate = 1;
4880 } else {
4881 for (i = 0; i < 8; i++)
4882 reg_tmp += result[3][i];
4883
4884 if (reg_tmp)
4885 candidate = 3;
4886 else
4887 candidate = -1;
4888 }
4889 }
4890 }
4891
4892 for (i = 0; i < 4; i++) {
4893 reg_e94 = result[i][0];
4894 reg_e9c = result[i][1];
4895 reg_ea4 = result[i][2];
4896 reg_eac = result[i][3];
4897 reg_eb4 = result[i][4];
4898 reg_ebc = result[i][5];
4899 reg_ec4 = result[i][6];
4900 reg_ecc = result[i][7];
4901 }
4902
4903 if (candidate >= 0) {
4904 reg_e94 = result[candidate][0];
4905 priv->rege94 = reg_e94;
4906 reg_e9c = result[candidate][1];
4907 priv->rege9c = reg_e9c;
4908 reg_ea4 = result[candidate][2];
4909 reg_eac = result[candidate][3];
4910 reg_eb4 = result[candidate][4];
4911 priv->regeb4 = reg_eb4;
4912 reg_ebc = result[candidate][5];
4913 priv->regebc = reg_ebc;
4914 reg_ec4 = result[candidate][6];
4915 reg_ecc = result[candidate][7];
4916 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
4917 dev_dbg(dev,
4918 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
4919 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
4920 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
4921 path_a_ok = true;
4922 path_b_ok = true;
4923 } else {
4924 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
4925 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
4926 }
4927
4928 if (reg_e94 && candidate >= 0)
4929 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
4930 candidate, (reg_ea4 == 0));
4931
4932 if (priv->tx_paths > 1 && reg_eb4)
4933 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
4934 candidate, (reg_ec4 == 0));
4935
4936 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4937 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
c7a5a190
JS		 4938
4939 rtl8xxxu_prepare_calibrate(priv, 0);
26f1fad2
JS		 4940}
4941
e1547c53
JS		 4942static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
4943{
4944 struct device *dev = &priv->udev->dev;
4945 int result[4][8]; /* last is final result */
4946 int i, candidate;
4947 bool path_a_ok, path_b_ok;
4948 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
4949 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4950 u32 val32, bt_control;
4951 s32 reg_tmp = 0;
4952 bool simu;
4953
4954 rtl8xxxu_prepare_calibrate(priv, 1);
4955
4956 memset(result, 0, sizeof(result));
4957 candidate = -1;
4958
4959 path_a_ok = false;
4960 path_b_ok = false;
4961
4962 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
4963
4964 for (i = 0; i < 3; i++) {
4965 rtl8723bu_phy_iqcalibrate(priv, result, i);
4966
4967 if (i == 1) {
4968 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
4969 if (simu) {
4970 candidate = 0;
4971 break;
4972 }
4973 }
4974
4975 if (i == 2) {
4976 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
4977 if (simu) {
4978 candidate = 0;
4979 break;
4980 }
4981
4982 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
4983 if (simu) {
4984 candidate = 1;
4985 } else {
4986 for (i = 0; i < 8; i++)
4987 reg_tmp += result[3][i];
4988
4989 if (reg_tmp)
4990 candidate = 3;
4991 else
4992 candidate = -1;
4993 }
4994 }
4995 }
4996
4997 for (i = 0; i < 4; i++) {
4998 reg_e94 = result[i][0];
4999 reg_e9c = result[i][1];
5000 reg_ea4 = result[i][2];
5001 reg_eac = result[i][3];
5002 reg_eb4 = result[i][4];
5003 reg_ebc = result[i][5];
5004 reg_ec4 = result[i][6];
5005 reg_ecc = result[i][7];
5006 }
5007
5008 if (candidate >= 0) {
5009 reg_e94 = result[candidate][0];
5010 priv->rege94 = reg_e94;
5011 reg_e9c = result[candidate][1];
5012 priv->rege9c = reg_e9c;
5013 reg_ea4 = result[candidate][2];
5014 reg_eac = result[candidate][3];
5015 reg_eb4 = result[candidate][4];
5016 priv->regeb4 = reg_eb4;
5017 reg_ebc = result[candidate][5];
5018 priv->regebc = reg_ebc;
5019 reg_ec4 = result[candidate][6];
5020 reg_ecc = result[candidate][7];
5021 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
5022 dev_dbg(dev,
5023 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
5024 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
5025 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
5026 path_a_ok = true;
5027 path_b_ok = true;
5028 } else {
5029 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
5030 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
5031 }
5032
5033 if (reg_e94 && candidate >= 0)
5034 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
5035 candidate, (reg_ea4 == 0));
5036
5037 if (priv->tx_paths > 1 && reg_eb4)
5038 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
5039 candidate, (reg_ec4 == 0));
5040
5041 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
5042 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
5043
5044 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
5045
5046 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5047 val32 |= 0x80000;
5048 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5049 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
5050 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5051 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
5052 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5053 val32 |= 0x20;
5054 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5055 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
5056
5057 if (priv->rf_paths > 1) {
5058 dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__);
5059#ifdef RTL8723BU_PATH_B
5060 if (RF_Path == 0x0) //S1
5061 ODM_SetIQCbyRFpath(pDM_Odm, 0);
5062 else //S0
5063 ODM_SetIQCbyRFpath(pDM_Odm, 1);
5064#endif
5065 }
5066 rtl8xxxu_prepare_calibrate(priv, 0);
5067}
5068
26f1fad2
JS		 5069static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
5070{
5071 u32 val32;
5072 u32 rf_amode, rf_bmode = 0, lstf;
5073
5074 /* Check continuous TX and Packet TX */
5075 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
5076
5077 if (lstf & OFDM_LSTF_MASK) {
5078 /* Disable all continuous TX */
5079 val32 = lstf & ~OFDM_LSTF_MASK;
5080 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
5081
5082 /* Read original RF mode Path A */
5083 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
5084
5085 /* Set RF mode to standby Path A */
5086 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
5087 (rf_amode & 0x8ffff) | 0x10000);
5088
5089 /* Path-B */
5090 if (priv->tx_paths > 1) {
5091 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
5092 RF6052_REG_AC);
5093
5094 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5095 (rf_bmode & 0x8ffff) | 0x10000);
5096 }
5097 } else {
5098 /* Deal with Packet TX case */
5099 /* block all queues */
5100 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5101 }
5102
5103 /* Start LC calibration */
0d698dec
JS		 5104 if (priv->fops->has_s0s1)
5105 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
26f1fad2
JS		 5106 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
5107 val32 |= 0x08000;
5108 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
5109
5110 msleep(100);
5111
0d698dec
JS		 5112 if (priv->fops->has_s0s1)
5113 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
5114
26f1fad2
JS		 5115 /* Restore original parameters */
5116 if (lstf & OFDM_LSTF_MASK) {
5117 /* Path-A */
5118 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
5119 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
5120
5121 /* Path-B */
5122 if (priv->tx_paths > 1)
5123 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
5124 rf_bmode);
5125 } else /* Deal with Packet TX case */
5126 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
5127}
5128
5129static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
5130{
5131 int i;
5132 u16 reg;
5133
5134 reg = REG_MACID;
5135
5136 for (i = 0; i < ETH_ALEN; i++)
5137 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
5138
5139 return 0;
5140}
5141
5142static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
5143{
5144 int i;
5145 u16 reg;
5146
5147 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
5148
5149 reg = REG_BSSID;
5150
5151 for (i = 0; i < ETH_ALEN; i++)
5152 rtl8xxxu_write8(priv, reg + i, bssid[i]);
5153
5154 return 0;
5155}
5156
5157static void
5158rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
5159{
5160 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
5161 u8 max_agg = 0xf;
5162 int i;
5163
5164 ampdu_factor = 1 << (ampdu_factor + 2);
5165 if (ampdu_factor > max_agg)
5166 ampdu_factor = max_agg;
5167
5168 for (i = 0; i < 4; i++) {
5169 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
5170 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
5171
5172 if ((vals[i] & 0x0f) > ampdu_factor)
5173 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
5174
5175 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
5176 }
5177}
5178
5179static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
5180{
5181 u8 val8;
5182
5183 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
5184 val8 &= 0xf8;
5185 val8 |= density;
5186 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
5187}
5188
5189static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
5190{
5191 u8 val8;
5192 int count, ret;
5193
5194 /* Start of rtl8723AU_card_enable_flow */
5195 /* Act to Cardemu sequence*/
5196 /* Turn off RF */
5197 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
5198
5199 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
5200 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5201 val8 &= ~LEDCFG2_DPDT_SELECT;
5202 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5203
5204 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
5205 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5206 val8 |= BIT(1);
5207 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5208
5209 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5210 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5211 if ((val8 & BIT(1)) == 0)
5212 break;
5213 udelay(10);
5214 }
5215
5216 if (!count) {
5217 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
5218 __func__);
5219 ret = -EBUSY;
5220 goto exit;
5221 }
5222
5223 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
5224 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5225 val8 |= SYS_ISO_ANALOG_IPS;
5226 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5227
5228 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
5229 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5230 val8 &= ~LDOA15_ENABLE;
5231 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5232
5233exit:
5234 return ret;
5235}
5236
5237static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
5238{
5239 u8 val8;
5240 u8 val32;
5241 int count, ret;
5242
5243 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5244
5245 /*
5246 * Poll - wait for RX packet to complete
5247 */
5248 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5249 val32 = rtl8xxxu_read32(priv, 0x5f8);
5250 if (!val32)
5251 break;
5252 udelay(10);
5253 }
5254
5255 if (!count) {
5256 dev_warn(&priv->udev->dev,
5257 "%s: RX poll timed out (0x05f8)\n", __func__);
5258 ret = -EBUSY;
5259 goto exit;
5260 }
5261
5262 /* Disable CCK and OFDM, clock gated */
5263 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5264 val8 &= ~SYS_FUNC_BBRSTB;
5265 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5266
5267 udelay(2);
5268
5269 /* Reset baseband */
5270 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
5271 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
5272 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
5273
5274 /* Reset MAC TRX */
5275 val8 = rtl8xxxu_read8(priv, REG_CR);
5276 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
5277 rtl8xxxu_write8(priv, REG_CR, val8);
5278
5279 /* Reset MAC TRX */
5280 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
5281 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
5282 rtl8xxxu_write8(priv, REG_CR + 1, val8);
5283
5284 /* Respond TX OK to scheduler */
5285 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
5286 val8 |= DUAL_TSF_TX_OK;
5287 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
5288
5289exit:
5290 return ret;
5291}
5292
c05a9dbf 5293static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 5294{
5295 u8 val8;
5296
5297 /* Clear suspend enable and power down enable*/
5298 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5299 val8 &= ~(BIT(3) | BIT(7));
5300 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5301
5302 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
5303 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5304 val8 &= ~BIT(0);
5305 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5306
5307 /* 0x04[12:11] = 11 enable WL suspend*/
5308 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5309 val8 &= ~(BIT(3) | BIT(4));
5310 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5311}
5312
c05a9dbf
JS		 5313static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
5314{
5315 u8 val8;
5316
5317 /* Clear suspend enable and power down enable*/
5318 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5319 val8 &= ~(BIT(3) | BIT(4));
5320 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5321}
5322
5323static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
5324{
5325 u8 val8;
5326 u32 val32;
5327 int count, ret = 0;
5328
5329 /* disable HWPDN 0x04[15]=0*/
5330 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5331 val8 &= ~BIT(7);
5332 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5333
5334 /* disable SW LPS 0x04[10]= 0 */
5335 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5336 val8 &= ~BIT(2);
5337 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5338
5339 /* disable WL suspend*/
5340 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5341 val8 &= ~(BIT(3) | BIT(4));
5342 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5343
5344 /* wait till 0x04[17] = 1 power ready*/
5345 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5346 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5347 if (val32 & BIT(17))
5348 break;
5349
5350 udelay(10);
5351 }
5352
5353 if (!count) {
5354 ret = -EBUSY;
5355 goto exit;
5356 }
5357
5358 /* We should be able to optimize the following three entries into one */
5359
5360 /* release WLON reset 0x04[16]= 1*/
5361 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5362 val8 |= BIT(0);
5363 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5364
5365 /* set, then poll until 0 */
5366 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5367 val32 |= APS_FSMCO_MAC_ENABLE;
5368 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5369
5370 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5371 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5372 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5373 ret = 0;
5374 break;
5375 }
5376 udelay(10);
5377 }
5378
5379 if (!count) {
5380 ret = -EBUSY;
5381 goto exit;
5382 }
5383
5384exit:
5385 return ret;
5386}
5387
5388static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 5389{
5390 u8 val8;
5391 u32 val32;
5392 int count, ret = 0;
5393
5394 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
5395 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5396 val8 |= LDOA15_ENABLE;
5397 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5398
5399 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5400 val8 = rtl8xxxu_read8(priv, 0x0067);
5401 val8 &= ~BIT(4);
5402 rtl8xxxu_write8(priv, 0x0067, val8);
5403
5404 mdelay(1);
5405
5406 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5407 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5408 val8 &= ~SYS_ISO_ANALOG_IPS;
5409 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5410
5411 /* disable SW LPS 0x04[10]= 0 */
5412 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5413 val8 &= ~BIT(2);
5414 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5415
5416 /* wait till 0x04[17] = 1 power ready*/
5417 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5418 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5419 if (val32 & BIT(17))
5420 break;
5421
5422 udelay(10);
5423 }
5424
5425 if (!count) {
5426 ret = -EBUSY;
5427 goto exit;
5428 }
5429
5430 /* We should be able to optimize the following three entries into one */
5431
5432 /* release WLON reset 0x04[16]= 1*/
5433 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5434 val8 |= BIT(0);
5435 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5436
5437 /* disable HWPDN 0x04[15]= 0*/
5438 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5439 val8 &= ~BIT(7);
5440 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5441
5442 /* disable WL suspend*/
5443 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5444 val8 &= ~(BIT(3) | BIT(4));
5445 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5446
5447 /* set, then poll until 0 */
5448 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5449 val32 |= APS_FSMCO_MAC_ENABLE;
5450 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5451
5452 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5453 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5454 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5455 ret = 0;
5456 break;
5457 }
5458 udelay(10);
5459 }
5460
5461 if (!count) {
5462 ret = -EBUSY;
5463 goto exit;
5464 }
5465
5466 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
5467 /*
5468 * Note: Vendor driver actually clears this bit, despite the
5469 * documentation claims it's being set!
5470 */
5471 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
5472 val8 |= LEDCFG2_DPDT_SELECT;
5473 val8 &= ~LEDCFG2_DPDT_SELECT;
5474 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
5475
5476exit:
5477 return ret;
5478}
5479
42836db1
JS		 5480static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
5481{
5482 u8 val8;
5483 u32 val32;
5484 int count, ret = 0;
5485
5486 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
5487 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
5488 val8 |= LDOA15_ENABLE;
5489 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
5490
5491 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
5492 val8 = rtl8xxxu_read8(priv, 0x0067);
5493 val8 &= ~BIT(4);
5494 rtl8xxxu_write8(priv, 0x0067, val8);
5495
5496 mdelay(1);
5497
5498 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
5499 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5500 val8 &= ~SYS_ISO_ANALOG_IPS;
5501 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5502
5503 /* Disable SW LPS 0x04[10]= 0 */
5504 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5505 val32 &= ~APS_FSMCO_SW_LPS;
5506 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5507
5508 /* Wait until 0x04[17] = 1 power ready */
5509 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5510 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5511 if (val32 & BIT(17))
5512 break;
5513
5514 udelay(10);
5515 }
5516
5517 if (!count) {
5518 ret = -EBUSY;
5519 goto exit;
5520 }
5521
5522 /* We should be able to optimize the following three entries into one */
5523
5524 /* Release WLON reset 0x04[16]= 1*/
5525 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5526 val32 |= APS_FSMCO_WLON_RESET;
5527 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5528
5529 /* Disable HWPDN 0x04[15]= 0*/
5530 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5531 val32 &= ~APS_FSMCO_HW_POWERDOWN;
5532 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5533
5534 /* Disable WL suspend*/
5535 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5536 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
5537 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5538
5539 /* Set, then poll until 0 */
5540 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5541 val32 |= APS_FSMCO_MAC_ENABLE;
5542 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
5543
5544 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
5545 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
5546 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
5547 ret = 0;
5548 break;
5549 }
5550 udelay(10);
5551 }
5552
5553 if (!count) {
5554 ret = -EBUSY;
5555 goto exit;
5556 }
5557
5558 /* Enable WL control XTAL setting */
5559 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
5560 val8 |= AFE_MISC_WL_XTAL_CTRL;
5561 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
5562
5563 /* Enable falling edge triggering interrupt */
5564 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
5565 val8 |= BIT(1);
5566 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
5567
5568 /* Enable GPIO9 interrupt mode */
5569 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
5570 val8 |= BIT(1);
5571 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
5572
5573 /* Enable GPIO9 input mode */
5574 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
5575 val8 &= ~BIT(1);
5576 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
5577
5578 /* Enable HSISR GPIO[C:0] interrupt */
5579 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
5580 val8 |= BIT(0);
5581 rtl8xxxu_write8(priv, REG_HSIMR, val8);
5582
5583 /* Enable HSISR GPIO9 interrupt */
5584 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
5585 val8 |= BIT(1);
5586 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
5587
5588 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
5589 val8 |= MULTI_WIFI_HW_ROF_EN;
5590 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
5591
5592 /* For GPIO9 internal pull high setting BIT(14) */
5593 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
5594 val8 |= BIT(6);
5595 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
5596
5597exit:
5598 return ret;
5599}
5600
26f1fad2
JS		 5601static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
5602{
5603 u8 val8;
5604
5605 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
5606 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
5607
5608 /* 0x04[12:11] = 01 enable WL suspend */
5609 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5610 val8 &= ~BIT(4);
5611 val8 |= BIT(3);
5612 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5613
5614 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
5615 val8 |= BIT(7);
5616 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
5617
5618 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
5619 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
5620 val8 |= BIT(0);
5621 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
5622
5623 return 0;
5624}
5625
5626static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
5627{
5628 u8 val8;
5629 u16 val16;
5630 u32 val32;
5631 int ret;
5632
5633 /*
5634 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5635 */
5636 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5637
c05a9dbf 5638 rtl8723a_disabled_to_emu(priv);
26f1fad2 5639
c05a9dbf 5640 ret = rtl8723a_emu_to_active(priv);
26f1fad2
JS		 5641 if (ret)
5642 goto exit;
5643
5644 /*
5645 * 0x0004[19] = 1, reset 8051
5646 */
5647 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
5648 val8 |= BIT(3);
5649 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
5650
5651 /*
5652 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5653 * Set CR bit10 to enable 32k calibration.
5654 */
5655 val16 = rtl8xxxu_read16(priv, REG_CR);
5656 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5657 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5658 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5659 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5660 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5661 rtl8xxxu_write16(priv, REG_CR, val16);
5662
5663 /* For EFuse PG */
5664 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
5665 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
5666 val32 |= (0x06 << 28);
5667 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
5668exit:
5669 return ret;
5670}
5671
42836db1
JS		 5672static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
5673{
5674 u8 val8;
5675 u16 val16;
5676 u32 val32;
5677 int ret;
5678
5679 rtl8723a_disabled_to_emu(priv);
5680
5681 ret = rtl8723b_emu_to_active(priv);
5682 if (ret)
5683 goto exit;
5684
5685 /*
5686 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5687 * Set CR bit10 to enable 32k calibration.
5688 */
5689 val16 = rtl8xxxu_read16(priv, REG_CR);
5690 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5691 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5692 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5693 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5694 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5695 rtl8xxxu_write16(priv, REG_CR, val16);
5696
5697 /*
5698 * BT coexist power on settings. This is identical for 1 and 2
5699 * antenna parts.
5700 */
5701 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
5702
5703 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5704 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
5705 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5706
5707 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
5708 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
5709 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
5710 /* Antenna inverse */
5711 rtl8xxxu_write8(priv, 0xfe08, 0x01);
5712
5713 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
5714 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
5715 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
5716
5717 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
5718 val32 |= LEDCFG0_DPDT_SELECT;
5719 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
5720
5721 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
5722 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
5723 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
5724exit:
5725 return ret;
5726}
5727
c0963772
KV		 5728#ifdef CONFIG_RTL8XXXU_UNTESTED
5729
26f1fad2
JS		 5730static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
5731{
5732 u8 val8;
5733 u16 val16;
5734 u32 val32;
5735 int i;
5736
5737 for (i = 100; i; i--) {
5738 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
5739 if (val8 & APS_FSMCO_PFM_ALDN)
5740 break;
5741 }
5742
5743 if (!i) {
5744 pr_info("%s: Poll failed\n", __func__);
5745 return -ENODEV;
5746 }
5747
5748 /*
5749 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
5750 */
5751 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
5752 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
5753 udelay(100);
5754
5755 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
5756 if (!(val8 & LDOV12D_ENABLE)) {
5757 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
5758 val8 |= LDOV12D_ENABLE;
5759 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
5760
5761 udelay(100);
5762
5763 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
5764 val8 &= ~SYS_ISO_MD2PP;
5765 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
5766 }
5767
5768 /*
5769 * Auto enable WLAN
5770 */
5771 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5772 val16 |= APS_FSMCO_MAC_ENABLE;
5773 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5774
5775 for (i = 1000; i; i--) {
5776 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
5777 if (!(val16 & APS_FSMCO_MAC_ENABLE))
5778 break;
5779 }
5780 if (!i) {
5781 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
5782 return -EBUSY;
5783 }
5784
5785 /*
5786 * Enable radio, GPIO, LED
5787 */
5788 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
5789 APS_FSMCO_PFM_ALDN;
5790 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
5791
5792 /*
5793 * Release RF digital isolation
5794 */
5795 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
5796 val16 &= ~SYS_ISO_DIOR;
5797 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
5798
5799 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5800 val8 &= ~APSD_CTRL_OFF;
5801 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
5802 for (i = 200; i; i--) {
5803 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
5804 if (!(val8 & APSD_CTRL_OFF_STATUS))
5805 break;
5806 }
5807
5808 if (!i) {
5809 pr_info("%s: APSD_CTRL poll failed\n", __func__);
5810 return -EBUSY;
5811 }
5812
5813 /*
5814 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5815 */
5816 val16 = rtl8xxxu_read16(priv, REG_CR);
5817 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5818 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
5819 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
5820 rtl8xxxu_write16(priv, REG_CR, val16);
5821
5822 /*
5823 * Workaround for 8188RU LNA power leakage problem.
5824 */
5825 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5826 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5827 val32 &= ~BIT(1);
5828 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5829 }
5830 return 0;
5831}
5832
c0963772
KV		 5833#endif
5834
c05a9dbf
JS		 5835static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
5836{
5837 u16 val16;
5838 u32 val32;
5839 int ret;
5840
5841 ret = 0;
5842
5843 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
5844 if (val32 & SYS_CFG_SPS_LDO_SEL) {
5845 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
5846 } else {
5847 /*
5848 * Raise 1.2V voltage
5849 */
5850 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
5851 val32 &= 0xff0fffff;
5852 val32 |= 0x00500000;
5853 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
5854 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
5855 }
5856
5857 rtl8192e_disabled_to_emu(priv);
5858
5859 ret = rtl8192e_emu_to_active(priv);
5860 if (ret)
5861 goto exit;
5862
5863 rtl8xxxu_write16(priv, REG_CR, 0x0000);
5864
5865 /*
5866 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
5867 * Set CR bit10 to enable 32k calibration.
5868 */
5869 val16 = rtl8xxxu_read16(priv, REG_CR);
5870 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
5871 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
5872 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
5873 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
5874 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
5875 rtl8xxxu_write16(priv, REG_CR, val16);
5876
5877exit:
5878 return ret;
5879}
5880
26f1fad2
JS		 5881static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
5882{
5883 u8 val8;
5884 u16 val16;
5885 u32 val32;
5886
5887 /*
5888 * Workaround for 8188RU LNA power leakage problem.
5889 */
5890 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
5891 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
5892 val32 |= BIT(1);
5893 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
5894 }
5895
5896 rtl8xxxu_active_to_lps(priv);
5897
5898 /* Turn off RF */
5899 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
5900
5901 /* Reset Firmware if running in RAM */
5902 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
5903 rtl8xxxu_firmware_self_reset(priv);
5904
5905 /* Reset MCU */
5906 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
5907 val16 &= ~SYS_FUNC_CPU_ENABLE;
5908 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
5909
5910 /* Reset MCU ready status */
5911 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
5912
5913 rtl8xxxu_active_to_emu(priv);
5914 rtl8xxxu_emu_to_disabled(priv);
5915
5916 /* Reset MCU IO Wrapper */
5917 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5918 val8 &= ~BIT(0);
5919 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5920
5921 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
5922 val8 |= BIT(0);
5923 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
5924
5925 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
5926 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
5927}
5928
a3a5dac6 5929#ifdef NEED_PS_TDMA
3ca7b32c
JS		 5930static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
5931 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
5932{
5933 struct h2c_cmd h2c;
5934
5935 memset(&h2c, 0, sizeof(struct h2c_cmd));
5936 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
5937 h2c.b_type_dma.data1 = arg1;
5938 h2c.b_type_dma.data2 = arg2;
5939 h2c.b_type_dma.data3 = arg3;
5940 h2c.b_type_dma.data4 = arg4;
5941 h2c.b_type_dma.data5 = arg5;
5942 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
5943}
a3a5dac6 5944#endif
3ca7b32c 5945
f37e9228 5946static void rtl8723bu_init_bt(struct rtl8xxxu_priv *priv)
26f1fad2 5947{
f37e9228
JS		 5948 struct h2c_cmd h2c;
5949 u32 val32;
5950 u8 val8;
5951
5952 /*
5953 * No indication anywhere as to what 0x0790 does. The 2 antenna
5954 * vendor code preserves bits 6-7 here.
5955 */
5956 rtl8xxxu_write8(priv, 0x0790, 0x05);
5957 /*
5958 * 0x0778 seems to be related to enabling the number of antennas
5959 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
5960 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
5961 */
5962 rtl8xxxu_write8(priv, 0x0778, 0x01);
5963
5964 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
5965 val8 |= BIT(5);
5966 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
5967
5968 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
5969
394f1bd3
JS		 5970 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
5971
f37e9228
JS		 5972 /*
5973 * Set BT grant to low
5974 */
5975 memset(&h2c, 0, sizeof(struct h2c_cmd));
5976 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
5977 h2c.bt_grant.data = 0;
5978 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
5979
5980 /*
5981 * WLAN action by PTA
5982 */
fc1c89b3 5983 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
f37e9228
JS		 5984
5985 /*
5986 * BT select S0/S1 controlled by WiFi
5987 */
5988 val8 = rtl8xxxu_read8(priv, 0x0067);
5989 val8 |= BIT(5);
5990 rtl8xxxu_write8(priv, 0x0067, val8);
5991
5992 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
5993 val32 |= BIT(11);
5994 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
5995
5996 /*
5997 * Bits 6/7 are marked in/out ... but for what?
5998 */
5999 rtl8xxxu_write8(priv, 0x0974, 0xff);
6000
120e627f 6001 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
f37e9228 6002 val32 |= (BIT(0) | BIT(1));
120e627f 6003 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
f37e9228
JS		 6004
6005 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
6006
6007 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
6008 val32 &= ~BIT(24);
6009 val32 |= BIT(23);
6010 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
6011
6012 /*
6013 * Fix external switch Main->S1, Aux->S0
6014 */
6015 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
6016 val8 &= ~BIT(0);
6017 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
6018
6019 memset(&h2c, 0, sizeof(struct h2c_cmd));
6020 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
6021 h2c.ant_sel_rsv.ant_inverse = 1;
6022 h2c.ant_sel_rsv.int_switch_type = 0;
6023 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
6024
6025 /*
6026 * 0x280, 0x00, 0x200, 0x80 - not clear
6027 */
3ca7b32c
JS		 6028 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
6029
6030 /*
6031 * Software control, antenna at WiFi side
6032 */
a3a5dac6 6033#ifdef NEED_PS_TDMA
a228a5db 6034 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
a3a5dac6
JS		 6035#endif
6036
6037 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
6038 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
6039 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
6040 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
3ca7b32c 6041
6b9eae01
JS		 6042 memset(&h2c, 0, sizeof(struct h2c_cmd));
6043 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
6044 h2c.bt_info.data = BIT(0);
6045 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
6046
6b9eae01
JS		 6047 memset(&h2c, 0, sizeof(struct h2c_cmd));
6048 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
6049 h2c.ignore_wlan.data = 0;
6050 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
26f1fad2
JS		 6051}
6052
3e88ca44
JS		 6053static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
6054{
6055 u32 agg_rx;
6056 u8 agg_ctrl;
6057
6058 /*
6059 * For now simply disable RX aggregation
6060 */
6061 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
6062 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
6063
6064 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
6065 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
6066 agg_rx &= ~0xff0f;
6067
6068 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
6069 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
6070}
6071
9c79bf95
JS		 6072static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
6073{
6074 u32 val32;
6075
6076 /* Time duration for NHM unit: 4us, 0x2710=40ms */
6077 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
6078 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
6079 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
6080 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
6081 /* TH8 */
6082 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
6083 val32 |= 0xff;
6084 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
6085 /* Enable CCK */
6086 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
6087 val32 |= BIT(8) | BIT(9) | BIT(10);
6088 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
6089 /* Max power amongst all RX antennas */
6090 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
6091 val32 |= BIT(7);
6092 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
6093}
6094
26f1fad2
JS		 6095static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
6096{
6097 struct rtl8xxxu_priv *priv = hw->priv;
6098 struct device *dev = &priv->udev->dev;
6099 struct rtl8xxxu_rfregval *rftable;
6100 bool macpower;
6101 int ret;
6102 u8 val8;
6103 u16 val16;
6104 u32 val32;
6105
6106 /* Check if MAC is already powered on */
6107 val8 = rtl8xxxu_read8(priv, REG_CR);
6108
6109 /*
6110 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
6111 * initialized. First MAC returns 0xea, second MAC returns 0x00
6112 */
6113 if (val8 == 0xea)
6114 macpower = false;
6115 else
6116 macpower = true;
6117
6118 ret = priv->fops->power_on(priv);
6119 if (ret < 0) {
6120 dev_warn(dev, "%s: Failed power on\n", __func__);
6121 goto exit;
6122 }
6123
07bb46be
JS		 6124 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
6125 if (!macpower) {
79fb5fe9
JS		 6126 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
6127 if (ret) {
6128 dev_warn(dev, "%s: LLT table init failed\n", __func__);
6129 goto exit;
6130 }
6131
6132 /*
6133 * Presumably this is for 8188EU as well
6134 * Enable TX report and TX report timer
6135 */
6136 if (priv->rtlchip == 0x8723bu) {
6137 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
6138 val8 |= BIT(1);
6139 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
6140 /* Set MAX RPT MACID */
6141 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
6142 /* TX report Timer. Unit: 32us */
6143 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
360157eb
JS		 6144
6145 /* tmp ps ? */
6146 val8 = rtl8xxxu_read8(priv, 0xa3);
6147 val8 &= 0xf8;
6148 rtl8xxxu_write8(priv, 0xa3, val8);
79fb5fe9 6149 }
07bb46be
JS		 6150 }
6151
a47b9d47
JS		 6152 ret = rtl8xxxu_download_firmware(priv);
6153 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
6154 if (ret)
6155 goto exit;
6156 ret = rtl8xxxu_start_firmware(priv);
6157 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
6158 if (ret)
6159 goto exit;
6160
6431ea00
JS		 6161 /* Solve too many protocol error on USB bus */
6162 /* Can't do this for 8188/8192 UMC A cut parts */
6163 if (priv->rtlchip == 0x8723a ||
6164 ((priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c ||
6165 priv->rtlchip == 0x8188c) &&
6166 (priv->chip_cut || !priv->vendor_umc))) {
6167 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6168 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6169 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6170
6171 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6172 rtl8xxxu_write8(priv, 0xfe41, 0x19);
6173 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6174
6175 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
6176 rtl8xxxu_write8(priv, 0xfe41, 0x91);
6177 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6178
6179 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
6180 rtl8xxxu_write8(priv, 0xfe41, 0x81);
6181 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6182 }
6183
3a4be6a0 6184 if (priv->rtlchip == 0x8192e) {
99ad16cb
JS		 6185 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
6186 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
b63d0aac
JS		 6187 }
6188
f0d9f5e9
JS		 6189 if (priv->fops->phy_init_antenna_selection)
6190 priv->fops->phy_init_antenna_selection(priv);
6191
b7dd8ff9
JS		 6192 if (priv->rtlchip == 0x8723b)
6193 ret = rtl8xxxu_init_mac(priv, rtl8723b_mac_init_table);
6194 else
6195 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
6196
26f1fad2
JS		 6197 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
6198 if (ret)
6199 goto exit;
6200
6201 ret = rtl8xxxu_init_phy_bb(priv);
6202 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
6203 if (ret)
6204 goto exit;
6205
6206 switch(priv->rtlchip) {
6207 case 0x8723a:
6208 rftable = rtl8723au_radioa_1t_init_table;
6209 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6210 break;
22a31d45
JS		 6211 case 0x8723b:
6212 rftable = rtl8723bu_radioa_1t_init_table;
6213 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
5ac61789
JS		 6214 /*
6215 * PHY LCK
6216 */
6217 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
6218 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
6219 msleep(200);
6220 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
22a31d45 6221 break;
26f1fad2
JS		 6222 case 0x8188c:
6223 if (priv->hi_pa)
6224 rftable = rtl8188ru_radioa_1t_highpa_table;
6225 else
6226 rftable = rtl8192cu_radioa_1t_init_table;
6227 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6228 break;
6229 case 0x8191c:
6230 rftable = rtl8192cu_radioa_1t_init_table;
6231 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6232 break;
6233 case 0x8192c:
6234 rftable = rtl8192cu_radioa_2t_init_table;
6235 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
6236 if (ret)
6237 break;
6238 rftable = rtl8192cu_radiob_2t_init_table;
6239 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
6240 break;
6241 default:
6242 ret = -EINVAL;
6243 }
6244
6245 if (ret)
6246 goto exit;
6247
2f109c8e
JS		 6248 /*
6249 * Chip specific quirks
6250 */
6251 if (priv->rtlchip == 0x8723a) {
6252 /* Fix USB interface interference issue */
6253 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6254 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6255 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6256 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6257
6258 /* Reduce 80M spur */
f30ed675
JS		 6259 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
6260 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
6261 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
6262 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
2f109c8e
JS		 6263 } else {
6264 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
6265 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
6266 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
f30ed675 6267 }
26f1fad2 6268
f2a4163a 6269 if (!macpower) {
1f1b20f1
JS		 6270 if (priv->ep_tx_normal_queue)
6271 val8 = TX_PAGE_NUM_NORM_PQ;
6272 else
6273 val8 = 0;
6274
6275 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
6276
6277 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
6278
6279 if (priv->ep_tx_high_queue)
6280 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
6281 if (priv->ep_tx_low_queue)
6282 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
6283
6284 rtl8xxxu_write32(priv, REG_RQPN, val32);
6285
6286 /*
6287 * Set TX buffer boundary
6288 */
6289 val8 = TX_TOTAL_PAGE_NUM + 1;
6290
6291 if (priv->rtlchip == 0x8723b)
6292 val8 -= 1;
6293
6294 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
6295 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
6296 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
6297 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
6298 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
6299 }
6300
6301 ret = rtl8xxxu_init_queue_priority(priv);
6302 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
6303 if (ret)
6304 goto exit;
6305
26f1fad2 6306 /* RFSW Control - clear bit 14 ?? */
b87212ce
JS		 6307 if (priv->rtlchip != 0x8723b)
6308 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
26f1fad2
JS		 6309 /* 0x07000760 */
6310 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
6311 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
6312 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
6313 FPGA0_RF_BD_CTRL_SHIFT);
6314 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
6315 /* 0x860[6:5]= 00 - why? - this sets antenna B */
6316 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
6317
6318 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
6319 RF6052_REG_MODE_AG);
6320
26f1fad2
JS		 6321 /*
6322 * Set RX page boundary
6323 */
fadfa041
JS		 6324 if (priv->rtlchip == 0x8723b)
6325 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f);
6326 else
6327 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
26f1fad2
JS		 6328 /*
6329 * Transfer page size is always 128
6330 */
b87212ce
JS		 6331 if (priv->rtlchip == 0x8723b)
6332 val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) |
6333 (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT);
6334 else
6335 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
6336 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
26f1fad2
JS		 6337 rtl8xxxu_write8(priv, REG_PBP, val8);
6338
6339 /*
6340 * Unit in 8 bytes, not obvious what it is used for
6341 */
6342 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
6343
6344 /*
6345 * Enable all interrupts - not obvious USB needs to do this
6346 */
6347 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
6348 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
6349
6350 rtl8xxxu_set_mac(priv);
6351 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
6352
6353 /*
6354 * Configure initial WMAC settings
6355 */
6356 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
26f1fad2
JS		 6357 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
6358 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
6359 rtl8xxxu_write32(priv, REG_RCR, val32);
6360
6361 /*
6362 * Accept all multicast
6363 */
6364 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
6365 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
6366
6367 /*
6368 * Init adaptive controls
6369 */
6370 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6371 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6372 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
6373 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6374
6375 /* CCK = 0x0a, OFDM = 0x10 */
6376 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
6377 rtl8xxxu_set_retry(priv, 0x30, 0x30);
6378 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
6379
6380 /*
6381 * Init EDCA
6382 */
6383 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
6384
6385 /* Set CCK SIFS */
6386 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
6387
6388 /* Set OFDM SIFS */
6389 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
6390
6391 /* TXOP */
6392 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
6393 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
6394 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
6395 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
6396
6397 /* Set data auto rate fallback retry count */
6398 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
6399 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
6400 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
6401 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
6402
6403 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
6404 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
6405 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
6406
6407 /* Set ACK timeout */
6408 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
6409
6410 /*
6411 * Initialize beacon parameters
6412 */
6413 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
6414 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
6415 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
6416 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
6417 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
6418 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
6419
c3690604
JS		 6420 /*
6421 * Initialize burst parameters
6422 */
6423 if (priv->rtlchip == 0x8723b) {
6424 /*
6425 * For USB high speed set 512B packets
6426 */
6427 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
6428 val8 &= ~(BIT(4) | BIT(5));
6429 val8 |= BIT(4);
6430 val8 |= BIT(1) | BIT(2) | BIT(3);
6431 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
6432
6433 /*
6434 * For USB high speed set 512B packets
6435 */
6436 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
6437 val8 |= BIT(7);
6438 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
6439
6440 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
6441 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
6442 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
6443 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
6444 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
6445 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
6446 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
6447
6448 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
6449 val8 |= BIT(5) | BIT(6);
6450 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
6451 }
6452
3e88ca44
JS		 6453 if (priv->fops->init_aggregation)
6454 priv->fops->init_aggregation(priv);
6455
26f1fad2
JS		 6456 /*
6457 * Enable CCK and OFDM block
6458 */
6459 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6460 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
6461 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6462
6463 /*
6464 * Invalidate all CAM entries - bit 30 is undocumented
6465 */
6466 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
6467
6468 /*
6469 * Start out with default power levels for channel 6, 20MHz
6470 */
e796dab4 6471 priv->fops->set_tx_power(priv, 1, false);
26f1fad2
JS		 6472
6473 /* Let the 8051 take control of antenna setting */
6474 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6475 val8 |= LEDCFG2_DPDT_SELECT;
6476 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6477
6478 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
6479
6480 /* Disable BAR - not sure if this has any effect on USB */
6481 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
6482
6483 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
6484
9c79bf95
JS		 6485 if (priv->fops->init_statistics)
6486 priv->fops->init_statistics(priv);
6487
fa0f2d48
JS		 6488 rtl8723a_phy_lc_calibrate(priv);
6489
e1547c53 6490 priv->fops->phy_iq_calibrate(priv);
26f1fad2
JS		 6491
6492 /*
6493 * This should enable thermal meter
6494 */
6495 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
6496
26f1fad2 6497 /* Init BT hw config. */
f37e9228
JS		 6498 if (priv->fops->init_bt)
6499 priv->fops->init_bt(priv);
26f1fad2 6500
26f1fad2
JS		 6501 /* Set NAV_UPPER to 30000us */
6502 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
6503 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
6504
4042e617
JS		 6505 if (priv->rtlchip == 0x8723a) {
6506 /*
6507 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
6508 * but we need to find root cause.
6509 * This is 8723au only.
6510 */
6511 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6512 if ((val32 & 0xff000000) != 0x83000000) {
6513 val32 |= FPGA_RF_MODE_CCK;
6514 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
6515 }
26f1fad2
JS		 6516 }
6517
6518 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
6519 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
6520 /* ack for xmit mgmt frames. */
6521 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
6522
6523exit:
6524 return ret;
6525}
6526
6527static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
6528{
6529 struct rtl8xxxu_priv *priv = hw->priv;
6530
6531 rtl8xxxu_power_off(priv);
6532}
6533
6534static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
6535 struct ieee80211_key_conf *key, const u8 *mac)
6536{
6537 u32 cmd, val32, addr, ctrl;
6538 int j, i, tmp_debug;
6539
6540 tmp_debug = rtl8xxxu_debug;
6541 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
6542 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
6543
6544 /*
6545 * This is a bit of a hack - the lower bits of the cipher
6546 * suite selector happens to match the cipher index in the CAM
6547 */
6548 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
6549 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
6550
6551 for (j = 5; j >= 0; j--) {
6552 switch (j) {
6553 case 0:
6554 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
6555 break;
6556 case 1:
6557 val32 = mac[2] | (mac[3] << 8) |
6558 (mac[4] << 16) | (mac[5] << 24);
6559 break;
6560 default:
6561 i = (j - 2) << 2;
6562 val32 = key->key[i] | (key->key[i + 1] << 8) |
6563 key->key[i + 2] << 16 | key->key[i + 3] << 24;
6564 break;
6565 }
6566
6567 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
6568 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
6569 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
6570 udelay(100);
6571 }
6572
6573 rtl8xxxu_debug = tmp_debug;
6574}
6575
6576static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
56e4374a 6577 struct ieee80211_vif *vif, const u8 *mac)
26f1fad2
JS		 6578{
6579 struct rtl8xxxu_priv *priv = hw->priv;
6580 u8 val8;
6581
6582 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6583 val8 |= BEACON_DISABLE_TSF_UPDATE;
6584 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6585}
6586
6587static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
6588 struct ieee80211_vif *vif)
6589{
6590 struct rtl8xxxu_priv *priv = hw->priv;
6591 u8 val8;
6592
6593 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6594 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
6595 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6596}
6597
6598static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
6599 u32 ramask, int sgi)
6600{
6601 struct h2c_cmd h2c;
6602
6603 h2c.ramask.cmd = H2C_SET_RATE_MASK;
6604 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
6605 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
6606
6607 h2c.ramask.arg = 0x80;
6608 if (sgi)
6609 h2c.ramask.arg |= 0x20;
6610
7ff8c1ae 6611 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
8da91571
JS		 6612 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
6613 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
26f1fad2
JS		 6614}
6615
6616static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
6617{
6618 u32 val32;
6619 u8 rate_idx = 0;
6620
6621 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
6622
6623 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6624 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
6625 val32 |= rate_cfg;
6626 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6627
6628 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
6629
6630 while (rate_cfg) {
6631 rate_cfg = (rate_cfg >> 1);
6632 rate_idx++;
6633 }
6634 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
6635}
6636
6637static void
6638rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6639 struct ieee80211_bss_conf *bss_conf, u32 changed)
6640{
6641 struct rtl8xxxu_priv *priv = hw->priv;
6642 struct device *dev = &priv->udev->dev;
6643 struct ieee80211_sta *sta;
6644 u32 val32;
6645 u8 val8;
6646
6647 if (changed & BSS_CHANGED_ASSOC) {
6648 struct h2c_cmd h2c;
6649
6650 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
6651
6652 memset(&h2c, 0, sizeof(struct h2c_cmd));
6653 rtl8xxxu_set_linktype(priv, vif->type);
6654
6655 if (bss_conf->assoc) {
6656 u32 ramask;
6657 int sgi = 0;
6658
6659 rcu_read_lock();
6660 sta = ieee80211_find_sta(vif, bss_conf->bssid);
6661 if (!sta) {
6662 dev_info(dev, "%s: ASSOC no sta found\n",
6663 __func__);
6664 rcu_read_unlock();
6665 goto error;
6666 }
6667
6668 if (sta->ht_cap.ht_supported)
6669 dev_info(dev, "%s: HT supported\n", __func__);
6670 if (sta->vht_cap.vht_supported)
6671 dev_info(dev, "%s: VHT supported\n", __func__);
6672
6673 /* TODO: Set bits 28-31 for rate adaptive id */
6674 ramask = (sta->supp_rates[0] & 0xfff) |
6675 sta->ht_cap.mcs.rx_mask[0] << 12 |
6676 sta->ht_cap.mcs.rx_mask[1] << 20;
6677 if (sta->ht_cap.cap &
6678 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6679 sgi = 1;
6680 rcu_read_unlock();
6681
6682 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
6683
26f1fad2
JS		 6684 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
6685
6686 rtl8723a_stop_tx_beacon(priv);
6687
6688 /* joinbss sequence */
6689 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
6690 0xc000 | bss_conf->aid);
6691
6692 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
6693 } else {
26f1fad2
JS		 6694 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6695 val8 |= BEACON_DISABLE_TSF_UPDATE;
6696 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6697
26f1fad2
JS		 6698 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
6699 }
6700 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
8da91571 6701 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
26f1fad2
JS		 6702 }
6703
6704 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
6705 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
6706 bss_conf->use_short_preamble);
6707 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
6708 if (bss_conf->use_short_preamble)
6709 val32 |= RSR_ACK_SHORT_PREAMBLE;
6710 else
6711 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
6712 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
6713 }
6714
6715 if (changed & BSS_CHANGED_ERP_SLOT) {
6716 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
6717 bss_conf->use_short_slot);
6718
6719 if (bss_conf->use_short_slot)
6720 val8 = 9;
6721 else
6722 val8 = 20;
6723 rtl8xxxu_write8(priv, REG_SLOT, val8);
6724 }
6725
6726 if (changed & BSS_CHANGED_BSSID) {
6727 dev_dbg(dev, "Changed BSSID!\n");
6728 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
6729 }
6730
6731 if (changed & BSS_CHANGED_BASIC_RATES) {
6732 dev_dbg(dev, "Changed BASIC_RATES!\n");
6733 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
6734 }
6735error:
6736 return;
6737}
6738
6739static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
6740{
6741 u32 rtlqueue;
6742
6743 switch (queue) {
6744 case IEEE80211_AC_VO:
6745 rtlqueue = TXDESC_QUEUE_VO;
6746 break;
6747 case IEEE80211_AC_VI:
6748 rtlqueue = TXDESC_QUEUE_VI;
6749 break;
6750 case IEEE80211_AC_BE:
6751 rtlqueue = TXDESC_QUEUE_BE;
6752 break;
6753 case IEEE80211_AC_BK:
6754 rtlqueue = TXDESC_QUEUE_BK;
6755 break;
6756 default:
6757 rtlqueue = TXDESC_QUEUE_BE;
6758 }
6759
6760 return rtlqueue;
6761}
6762
6763static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
6764{
6765 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6766 u32 queue;
6767
6768 if (ieee80211_is_mgmt(hdr->frame_control))
6769 queue = TXDESC_QUEUE_MGNT;
6770 else
6771 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
6772
6773 return queue;
6774}
6775
6776static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
6777{
6778 __le16 *ptr = (__le16 *)tx_desc;
6779 u16 csum = 0;
6780 int i;
6781
6782 /*
6783 * Clear csum field before calculation, as the csum field is
6784 * in the middle of the struct.
6785 */
6786 tx_desc->csum = cpu_to_le16(0);
6787
6788 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
6789 csum = csum ^ le16_to_cpu(ptr[i]);
6790
6791 tx_desc->csum |= cpu_to_le16(csum);
6792}
6793
6794static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
6795{
6796 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
6797 unsigned long flags;
6798
6799 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6800 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
6801 list_del(&tx_urb->list);
6802 priv->tx_urb_free_count--;
6803 usb_free_urb(&tx_urb->urb);
6804 }
6805 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6806}
6807
6808static struct rtl8xxxu_tx_urb *
6809rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
6810{
6811 struct rtl8xxxu_tx_urb *tx_urb;
6812 unsigned long flags;
6813
6814 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6815 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
6816 struct rtl8xxxu_tx_urb, list);
6817 if (tx_urb) {
6818 list_del(&tx_urb->list);
6819 priv->tx_urb_free_count--;
6820 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
6821 !priv->tx_stopped) {
6822 priv->tx_stopped = true;
6823 ieee80211_stop_queues(priv->hw);
6824 }
6825 }
6826
6827 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6828
6829 return tx_urb;
6830}
6831
6832static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
6833 struct rtl8xxxu_tx_urb *tx_urb)
6834{
6835 unsigned long flags;
6836
6837 INIT_LIST_HEAD(&tx_urb->list);
6838
6839 spin_lock_irqsave(&priv->tx_urb_lock, flags);
6840
6841 list_add(&tx_urb->list, &priv->tx_urb_free_list);
6842 priv->tx_urb_free_count++;
6843 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
6844 priv->tx_stopped) {
6845 priv->tx_stopped = false;
6846 ieee80211_wake_queues(priv->hw);
6847 }
6848
6849 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
6850}
6851
6852static void rtl8xxxu_tx_complete(struct urb *urb)
6853{
6854 struct sk_buff *skb = (struct sk_buff *)urb->context;
6855 struct ieee80211_tx_info *tx_info;
6856 struct ieee80211_hw *hw;
6857 struct rtl8xxxu_tx_urb *tx_urb =
6858 container_of(urb, struct rtl8xxxu_tx_urb, urb);
6859
6860 tx_info = IEEE80211_SKB_CB(skb);
6861 hw = tx_info->rate_driver_data[0];
6862
6863 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
6864
6865 ieee80211_tx_info_clear_status(tx_info);
6866 tx_info->status.rates[0].idx = -1;
6867 tx_info->status.rates[0].count = 0;
6868
6869 if (!urb->status)
6870 tx_info->flags |= IEEE80211_TX_STAT_ACK;
6871
6872 ieee80211_tx_status_irqsafe(hw, skb);
6873
6874 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
6875}
6876
6877static void rtl8xxxu_dump_action(struct device *dev,
6878 struct ieee80211_hdr *hdr)
6879{
6880 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
6881 u16 cap, timeout;
6882
6883 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
6884 return;
6885
6886 switch (mgmt->u.action.u.addba_resp.action_code) {
6887 case WLAN_ACTION_ADDBA_RESP:
6888 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
6889 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
6890 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
6891 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
6892 "status %02x\n",
6893 timeout,
6894 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6895 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6896 (cap >> 1) & 0x1,
6897 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
6898 break;
6899 case WLAN_ACTION_ADDBA_REQ:
6900 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
6901 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
6902 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
6903 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
6904 timeout,
6905 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
6906 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
6907 (cap >> 1) & 0x1);
6908 break;
6909 default:
6910 dev_info(dev, "action frame %02x\n",
6911 mgmt->u.action.u.addba_resp.action_code);
6912 break;
6913 }
6914}
6915
6916static void rtl8xxxu_tx(struct ieee80211_hw *hw,
6917 struct ieee80211_tx_control *control,
6918 struct sk_buff *skb)
6919{
6920 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6921 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
6922 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
6923 struct rtl8xxxu_priv *priv = hw->priv;
6924 struct rtl8xxxu_tx_desc *tx_desc;
6925 struct rtl8xxxu_tx_urb *tx_urb;
6926 struct ieee80211_sta *sta = NULL;
6927 struct ieee80211_vif *vif = tx_info->control.vif;
6928 struct device *dev = &priv->udev->dev;
6929 u32 queue, rate;
6930 u16 pktlen = skb->len;
6931 u16 seq_number;
6932 u16 rate_flag = tx_info->control.rates[0].flags;
6933 int ret;
6934
6935 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
6936 dev_warn(dev,
6937 "%s: Not enough headroom (%i) for tx descriptor\n",
6938 __func__, skb_headroom(skb));
6939 goto error;
6940 }
6941
6942 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
6943 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
6944 __func__, skb->len);
6945 goto error;
6946 }
6947
6948 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
6949 if (!tx_urb) {
6950 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
6951 goto error;
6952 }
6953
6954 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
6955 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
6956 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
6957
6958 if (ieee80211_is_action(hdr->frame_control))
6959 rtl8xxxu_dump_action(dev, hdr);
6960
6961 tx_info->rate_driver_data[0] = hw;
6962
6963 if (control && control->sta)
6964 sta = control->sta;
6965
6966 tx_desc = (struct rtl8xxxu_tx_desc *)
6967 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
6968
6969 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
6970 tx_desc->pkt_size = cpu_to_le16(pktlen);
6971 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
6972
6973 tx_desc->txdw0 =
6974 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
6975 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
6976 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
6977 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
6978
6979 queue = rtl8xxxu_queue_select(hw, skb);
6980 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
6981
6982 if (tx_info->control.hw_key) {
6983 switch (tx_info->control.hw_key->cipher) {
6984 case WLAN_CIPHER_SUITE_WEP40:
6985 case WLAN_CIPHER_SUITE_WEP104:
6986 case WLAN_CIPHER_SUITE_TKIP:
6987 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
6988 break;
6989 case WLAN_CIPHER_SUITE_CCMP:
6990 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
6991 break;
6992 default:
6993 break;
6994 }
6995 }
6996
6997 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
6998 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
6999
7000 if (rate_flag & IEEE80211_TX_RC_MCS)
7001 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
7002 else
7003 rate = tx_rate->hw_value;
7004 tx_desc->txdw5 = cpu_to_le32(rate);
7005
7006 if (ieee80211_is_data(hdr->frame_control))
7007 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
7008
7009 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
7010 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
7011 if (sta->ht_cap.ht_supported) {
7012 u32 ampdu, val32;
7013
7014 ampdu = (u32)sta->ht_cap.ampdu_density;
7015 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
7016 tx_desc->txdw2 |= cpu_to_le32(val32);
7017 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
7018 } else
7019 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
7020 } else
7021 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
7022
7023 if (ieee80211_is_data_qos(hdr->frame_control))
7024 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
7025 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
7026 (sta && vif && vif->bss_conf.use_short_preamble))
7027 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
7028 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
7029 (ieee80211_is_data_qos(hdr->frame_control) &&
7030 sta && sta->ht_cap.cap &
7031 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
7032 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
7033 }
7034 if (ieee80211_is_mgmt(hdr->frame_control)) {
7035 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
7036 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
7037 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
7038 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
7039 }
7040
7041 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
7042 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
7043 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
7044 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
7045 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
7046 }
7047
7048 rtl8xxxu_calc_tx_desc_csum(tx_desc);
7049
7050 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
7051 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
7052
7053 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
7054 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
7055 if (ret) {
7056 usb_unanchor_urb(&tx_urb->urb);
7057 rtl8xxxu_free_tx_urb(priv, tx_urb);
7058 goto error;
7059 }
7060 return;
7061error:
7062 dev_kfree_skb(skb);
7063}
7064
7065static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
7066 struct ieee80211_rx_status *rx_status,
7067 struct rtl8xxxu_rx_desc *rx_desc,
7068 struct rtl8723au_phy_stats *phy_stats)
7069{
7070 if (phy_stats->sgi_en)
7071 rx_status->flag |= RX_FLAG_SHORT_GI;
7072
7073 if (rx_desc->rxmcs < DESC_RATE_6M) {
7074 /*
7075 * Handle PHY stats for CCK rates
7076 */
7077 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
7078
7079 switch (cck_agc_rpt & 0xc0) {
7080 case 0xc0:
7081 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
7082 break;
7083 case 0x80:
7084 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
7085 break;
7086 case 0x40:
7087 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
7088 break;
7089 case 0x00:
7090 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
7091 break;
7092 }
7093 } else {
7094 rx_status->signal =
7095 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
7096 }
7097}
7098
7099static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
7100{
7101 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7102 unsigned long flags;
7103
7104 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7105
7106 list_for_each_entry_safe(rx_urb, tmp,
7107 &priv->rx_urb_pending_list, list) {
7108 list_del(&rx_urb->list);
7109 priv->rx_urb_pending_count--;
7110 usb_free_urb(&rx_urb->urb);
7111 }
7112
7113 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7114}
7115
7116static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
7117 struct rtl8xxxu_rx_urb *rx_urb)
7118{
7119 struct sk_buff *skb;
7120 unsigned long flags;
7121 int pending = 0;
7122
7123 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7124
7125 if (!priv->shutdown) {
7126 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
7127 priv->rx_urb_pending_count++;
7128 pending = priv->rx_urb_pending_count;
7129 } else {
7130 skb = (struct sk_buff *)rx_urb->urb.context;
7131 dev_kfree_skb(skb);
7132 usb_free_urb(&rx_urb->urb);
7133 }
7134
7135 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7136
7137 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
7138 schedule_work(&priv->rx_urb_wq);
7139}
7140
7141static void rtl8xxxu_rx_urb_work(struct work_struct *work)
7142{
7143 struct rtl8xxxu_priv *priv;
7144 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
7145 struct list_head local;
7146 struct sk_buff *skb;
7147 unsigned long flags;
7148 int ret;
7149
7150 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
7151 INIT_LIST_HEAD(&local);
7152
7153 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7154
7155 list_splice_init(&priv->rx_urb_pending_list, &local);
7156 priv->rx_urb_pending_count = 0;
7157
7158 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7159
7160 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
7161 list_del_init(&rx_urb->list);
7162 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7163 /*
7164 * If out of memory or temporary error, put it back on the
7165 * queue and try again. Otherwise the device is dead/gone
7166 * and we should drop it.
7167 */
7168 switch (ret) {
7169 case 0:
7170 break;
7171 case -ENOMEM:
7172 case -EAGAIN:
7173 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7174 break;
7175 default:
7176 pr_info("failed to requeue urb %i\n", ret);
7177 skb = (struct sk_buff *)rx_urb->urb.context;
7178 dev_kfree_skb(skb);
7179 usb_free_urb(&rx_urb->urb);
7180 }
7181 }
7182}
7183
b18cdfdb
JS		 7184static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv,
7185 struct sk_buff *skb,
7186 struct ieee80211_rx_status *rx_status)
7187{
7188 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
7189 struct rtl8723au_phy_stats *phy_stats;
7190 int drvinfo_sz, desc_shift;
7191
7192 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
7193
7194 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7195
7196 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7197 desc_shift = rx_desc->shift;
7198 skb_pull(skb, drvinfo_sz + desc_shift);
7199
7200 if (rx_desc->phy_stats)
7201 rtl8xxxu_rx_parse_phystats(priv, rx_status, rx_desc, phy_stats);
7202
7203 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7204 rx_status->flag |= RX_FLAG_MACTIME_START;
7205
7206 if (!rx_desc->swdec)
7207 rx_status->flag |= RX_FLAG_DECRYPTED;
7208 if (rx_desc->crc32)
7209 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7210 if (rx_desc->bw)
7211 rx_status->flag |= RX_FLAG_40MHZ;
7212
7213 if (rx_desc->rxht) {
7214 rx_status->flag |= RX_FLAG_HT;
7215 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7216 } else {
7217 rx_status->rate_idx = rx_desc->rxmcs;
7218 }
7219
7220 return RX_TYPE_DATA_PKT;
7221}
7222
7223static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv,
7224 struct sk_buff *skb,
7225 struct ieee80211_rx_status *rx_status)
7226{
7227 struct rtl8723bu_rx_desc *rx_desc =
7228 (struct rtl8723bu_rx_desc *)skb->data;
7229 struct rtl8723au_phy_stats *phy_stats;
7230 int drvinfo_sz, desc_shift;
7231 int rx_type;
7232
7233 skb_pull(skb, sizeof(struct rtl8723bu_rx_desc));
7234
7235 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
7236
7237 drvinfo_sz = rx_desc->drvinfo_sz * 8;
7238 desc_shift = rx_desc->shift;
7239 skb_pull(skb, drvinfo_sz + desc_shift);
7240
7241 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
7242 rx_status->flag |= RX_FLAG_MACTIME_START;
7243
7244 if (!rx_desc->swdec)
7245 rx_status->flag |= RX_FLAG_DECRYPTED;
7246 if (rx_desc->crc32)
7247 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7248 if (rx_desc->bw)
7249 rx_status->flag |= RX_FLAG_40MHZ;
7250
7251 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
7252 rx_status->flag |= RX_FLAG_HT;
7253 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
7254 } else {
7255 rx_status->rate_idx = rx_desc->rxmcs;
7256 }
7257
7258 if (rx_desc->rpt_sel) {
7259 struct device *dev = &priv->udev->dev;
7260 dev_dbg(dev, "%s: C2H packet\n", __func__);
7261 rx_type = RX_TYPE_C2H;
7262 } else {
7263 rx_type = RX_TYPE_DATA_PKT;
7264 }
7265
7266 return rx_type;
7267}
7268
b2b43b78
JS		 7269static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
7270 struct sk_buff *skb)
7271{
7272 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
7273 struct device *dev = &priv->udev->dev;
7274 int len;
7275
7276 len = skb->len - 2;
7277
6b9eae01 7278 dev_info(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
394f1bd3 7279 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
b2b43b78
JS		 7280
7281 switch(c2h->id) {
7282 case C2H_8723B_BT_INFO:
7283 if (c2h->bt_info.response_source >
7284 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
7285 dev_info(dev, "C2H_BT_INFO WiFi only firmware\n");
7286 else
7287 dev_info(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
7288
7289 if (c2h->bt_info.bt_has_reset)
7290 dev_info(dev, "BT has been reset\n");
394f1bd3
JS		 7291 if (c2h->bt_info.tx_rx_mask)
7292 dev_info(dev, "BT TRx mask\n");
b2b43b78
JS		 7293
7294 break;
394f1bd3
JS		 7295 case C2H_8723B_BT_MP_INFO:
7296 dev_info(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
7297 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
7298 break;
b2b43b78
JS		 7299 default:
7300 pr_info("%s: Unhandled C2H event %02x\n", __func__, c2h->id);
7301 break;
7302 }
7303}
7304
26f1fad2
JS		 7305static void rtl8xxxu_rx_complete(struct urb *urb)
7306{
7307 struct rtl8xxxu_rx_urb *rx_urb =
7308 container_of(urb, struct rtl8xxxu_rx_urb, urb);
7309 struct ieee80211_hw *hw = rx_urb->hw;
7310 struct rtl8xxxu_priv *priv = hw->priv;
7311 struct sk_buff *skb = (struct sk_buff *)urb->context;
26f1fad2 7312 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
26f1fad2
JS		 7313 struct device *dev = &priv->udev->dev;
7314 __le32 *_rx_desc_le = (__le32 *)skb->data;
7315 u32 *_rx_desc = (u32 *)skb->data;
b18cdfdb 7316 int rx_type, i;
26f1fad2
JS		 7317
7318 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
7319 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
7320
26f1fad2
JS		 7321 skb_put(skb, urb->actual_length);
7322
7323 if (urb->status == 0) {
26f1fad2
JS		 7324 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
7325
b18cdfdb 7326 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
26f1fad2
JS		 7327
7328 rx_status->freq = hw->conf.chandef.chan->center_freq;
7329 rx_status->band = hw->conf.chandef.chan->band;
7330
b18cdfdb
JS		 7331 if (rx_type == RX_TYPE_DATA_PKT)
7332 ieee80211_rx_irqsafe(hw, skb);
b2b43b78
JS		 7333 else {
7334 rtl8723bu_handle_c2h(priv, skb);
b18cdfdb 7335 dev_kfree_skb(skb);
b2b43b78 7336 }
26f1fad2 7337
26f1fad2
JS		 7338 skb = NULL;
7339 rx_urb->urb.context = NULL;
7340 rtl8xxxu_queue_rx_urb(priv, rx_urb);
7341 } else {
7342 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7343 goto cleanup;
7344 }
7345 return;
7346
7347cleanup:
7348 usb_free_urb(urb);
7349 dev_kfree_skb(skb);
7350 return;
7351}
7352
7353static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
7354 struct rtl8xxxu_rx_urb *rx_urb)
7355{
7356 struct sk_buff *skb;
7357 int skb_size;
7358 int ret;
7359
7360 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
7361 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
7362 if (!skb)
7363 return -ENOMEM;
7364
7365 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
7366 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
7367 skb_size, rtl8xxxu_rx_complete, skb);
7368 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
7369 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
7370 if (ret)
7371 usb_unanchor_urb(&rx_urb->urb);
7372 return ret;
7373}
7374
7375static void rtl8xxxu_int_complete(struct urb *urb)
7376{
7377 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
7378 struct device *dev = &priv->udev->dev;
7379 int ret;
7380
7381 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
7382 if (urb->status == 0) {
7383 usb_anchor_urb(urb, &priv->int_anchor);
7384 ret = usb_submit_urb(urb, GFP_ATOMIC);
7385 if (ret)
7386 usb_unanchor_urb(urb);
7387 } else {
7388 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
7389 }
7390}
7391
7392
7393static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
7394{
7395 struct rtl8xxxu_priv *priv = hw->priv;
7396 struct urb *urb;
7397 u32 val32;
7398 int ret;
7399
7400 urb = usb_alloc_urb(0, GFP_KERNEL);
7401 if (!urb)
7402 return -ENOMEM;
7403
7404 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
7405 priv->int_buf, USB_INTR_CONTENT_LENGTH,
7406 rtl8xxxu_int_complete, priv, 1);
7407 usb_anchor_urb(urb, &priv->int_anchor);
7408 ret = usb_submit_urb(urb, GFP_KERNEL);
7409 if (ret) {
7410 usb_unanchor_urb(urb);
7411 goto error;
7412 }
7413
7414 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
7415 val32 |= USB_HIMR_CPWM;
7416 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
7417
7418error:
7419 return ret;
7420}
7421
7422static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
7423 struct ieee80211_vif *vif)
7424{
7425 struct rtl8xxxu_priv *priv = hw->priv;
7426 int ret;
7427 u8 val8;
7428
7429 switch (vif->type) {
7430 case NL80211_IFTYPE_STATION:
7431 rtl8723a_stop_tx_beacon(priv);
7432
7433 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
7434 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
7435 BEACON_DISABLE_TSF_UPDATE;
7436 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
7437 ret = 0;
7438 break;
7439 default:
7440 ret = -EOPNOTSUPP;
7441 }
7442
7443 rtl8xxxu_set_linktype(priv, vif->type);
7444
7445 return ret;
7446}
7447
7448static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
7449 struct ieee80211_vif *vif)
7450{
7451 struct rtl8xxxu_priv *priv = hw->priv;
7452
7453 dev_dbg(&priv->udev->dev, "%s\n", __func__);
7454}
7455
7456static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
7457{
7458 struct rtl8xxxu_priv *priv = hw->priv;
7459 struct device *dev = &priv->udev->dev;
7460 u16 val16;
7461 int ret = 0, channel;
7462 bool ht40;
7463
7464 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
7465 dev_info(dev,
7466 "%s: channel: %i (changed %08x chandef.width %02x)\n",
7467 __func__, hw->conf.chandef.chan->hw_value,
7468 changed, hw->conf.chandef.width);
7469
7470 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
7471 val16 = ((hw->conf.long_frame_max_tx_count <<
7472 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
7473 ((hw->conf.short_frame_max_tx_count <<
7474 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
7475 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
7476 }
7477
7478 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
7479 switch (hw->conf.chandef.width) {
7480 case NL80211_CHAN_WIDTH_20_NOHT:
7481 case NL80211_CHAN_WIDTH_20:
7482 ht40 = false;
7483 break;
7484 case NL80211_CHAN_WIDTH_40:
7485 ht40 = true;
7486 break;
7487 default:
7488 ret = -ENOTSUPP;
7489 goto exit;
7490 }
7491
7492 channel = hw->conf.chandef.chan->hw_value;
7493
e796dab4 7494 priv->fops->set_tx_power(priv, channel, ht40);
26f1fad2 7495
1ea8e846 7496 priv->fops->config_channel(hw);
26f1fad2
JS		 7497 }
7498
7499exit:
7500 return ret;
7501}
7502
7503static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
7504 struct ieee80211_vif *vif, u16 queue,
7505 const struct ieee80211_tx_queue_params *param)
7506{
7507 struct rtl8xxxu_priv *priv = hw->priv;
7508 struct device *dev = &priv->udev->dev;
7509 u32 val32;
7510 u8 aifs, acm_ctrl, acm_bit;
7511
7512 aifs = param->aifs;
7513
7514 val32 = aifs |
7515 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
7516 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
7517 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
7518
7519 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
7520 dev_dbg(dev,
7521 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
7522 __func__, queue, val32, param->acm, acm_ctrl);
7523
7524 switch (queue) {
7525 case IEEE80211_AC_VO:
7526 acm_bit = ACM_HW_CTRL_VO;
7527 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
7528 break;
7529 case IEEE80211_AC_VI:
7530 acm_bit = ACM_HW_CTRL_VI;
7531 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
7532 break;
7533 case IEEE80211_AC_BE:
7534 acm_bit = ACM_HW_CTRL_BE;
7535 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
7536 break;
7537 case IEEE80211_AC_BK:
7538 acm_bit = ACM_HW_CTRL_BK;
7539 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
7540 break;
7541 default:
7542 acm_bit = 0;
7543 break;
7544 }
7545
7546 if (param->acm)
7547 acm_ctrl |= acm_bit;
7548 else
7549 acm_ctrl &= ~acm_bit;
7550 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
7551
7552 return 0;
7553}
7554
7555static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
7556 unsigned int changed_flags,
7557 unsigned int *total_flags, u64 multicast)
7558{
7559 struct rtl8xxxu_priv *priv = hw->priv;
3bed4bfa 7560 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
26f1fad2
JS		 7561
7562 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
7563 __func__, changed_flags, *total_flags);
7564
3bed4bfa
BR		 7565 /*
7566 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
7567 */
7568
7569 if (*total_flags & FIF_FCSFAIL)
7570 rcr |= RCR_ACCEPT_CRC32;
7571 else
7572 rcr &= ~RCR_ACCEPT_CRC32;
7573
7574 /*
7575 * FIF_PLCPFAIL not supported?
7576 */
7577
7578 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
7579 rcr &= ~RCR_CHECK_BSSID_BEACON;
7580 else
7581 rcr |= RCR_CHECK_BSSID_BEACON;
7582
7583 if (*total_flags & FIF_CONTROL)
7584 rcr |= RCR_ACCEPT_CTRL_FRAME;
7585 else
7586 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
7587
7588 if (*total_flags & FIF_OTHER_BSS) {
7589 rcr |= RCR_ACCEPT_AP;
7590 rcr &= ~RCR_CHECK_BSSID_MATCH;
7591 } else {
7592 rcr &= ~RCR_ACCEPT_AP;
7593 rcr |= RCR_CHECK_BSSID_MATCH;
7594 }
7595
7596 if (*total_flags & FIF_PSPOLL)
7597 rcr |= RCR_ACCEPT_PM;
7598 else
7599 rcr &= ~RCR_ACCEPT_PM;
7600
7601 /*
7602 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
7603 */
7604
7605 rtl8xxxu_write32(priv, REG_RCR, rcr);
7606
755bda11
JS		 7607 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
7608 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
7609 FIF_PROBE_REQ);
26f1fad2
JS		 7610}
7611
7612static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
7613{
7614 if (rts > 2347)
7615 return -EINVAL;
7616
7617 return 0;
7618}
7619
7620static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
7621 struct ieee80211_vif *vif,
7622 struct ieee80211_sta *sta,
7623 struct ieee80211_key_conf *key)
7624{
7625 struct rtl8xxxu_priv *priv = hw->priv;
7626 struct device *dev = &priv->udev->dev;
7627 u8 mac_addr[ETH_ALEN];
7628 u8 val8;
7629 u16 val16;
7630 u32 val32;
7631 int retval = -EOPNOTSUPP;
7632
7633 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
7634 __func__, cmd, key->cipher, key->keyidx);
7635
7636 if (vif->type != NL80211_IFTYPE_STATION)
7637 return -EOPNOTSUPP;
7638
7639 if (key->keyidx > 3)
7640 return -EOPNOTSUPP;
7641
7642 switch (key->cipher) {
7643 case WLAN_CIPHER_SUITE_WEP40:
7644 case WLAN_CIPHER_SUITE_WEP104:
7645
7646 break;
7647 case WLAN_CIPHER_SUITE_CCMP:
7648 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
7649 break;
7650 case WLAN_CIPHER_SUITE_TKIP:
7651 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
7652 default:
7653 return -EOPNOTSUPP;
7654 }
7655
7656 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
7657 dev_dbg(dev, "%s: pairwise key\n", __func__);
7658 ether_addr_copy(mac_addr, sta->addr);
7659 } else {
7660 dev_dbg(dev, "%s: group key\n", __func__);
7661 eth_broadcast_addr(mac_addr);
7662 }
7663
7664 val16 = rtl8xxxu_read16(priv, REG_CR);
7665 val16 |= CR_SECURITY_ENABLE;
7666 rtl8xxxu_write16(priv, REG_CR, val16);
7667
7668 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
7669 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
7670 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
7671 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
7672
7673 switch (cmd) {
7674 case SET_KEY:
7675 key->hw_key_idx = key->keyidx;
7676 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
7677 rtl8xxxu_cam_write(priv, key, mac_addr);
7678 retval = 0;
7679 break;
7680 case DISABLE_KEY:
7681 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
7682 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
7683 key->keyidx << CAM_CMD_KEY_SHIFT;
7684 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
7685 retval = 0;
7686 break;
7687 default:
7688 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
7689 }
7690
7691 return retval;
7692}
7693
7694static int
7695rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 7696 struct ieee80211_ampdu_params *params)
26f1fad2
JS		 7697{
7698 struct rtl8xxxu_priv *priv = hw->priv;
7699 struct device *dev = &priv->udev->dev;
7700 u8 ampdu_factor, ampdu_density;
50ea05ef
SS		 7701 struct ieee80211_sta *sta = params->sta;
7702 enum ieee80211_ampdu_mlme_action action = params->action;
26f1fad2
JS		 7703
7704 switch (action) {
7705 case IEEE80211_AMPDU_TX_START:
7706 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
7707 ampdu_factor = sta->ht_cap.ampdu_factor;
7708 ampdu_density = sta->ht_cap.ampdu_density;
7709 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
7710 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
7711 dev_dbg(dev,
7712 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
7713 ampdu_factor, ampdu_density);
7714 break;
7715 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7716 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
7717 rtl8xxxu_set_ampdu_factor(priv, 0);
7718 rtl8xxxu_set_ampdu_min_space(priv, 0);
7719 break;
7720 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7721 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
7722 __func__);
7723 rtl8xxxu_set_ampdu_factor(priv, 0);
7724 rtl8xxxu_set_ampdu_min_space(priv, 0);
7725 break;
7726 case IEEE80211_AMPDU_RX_START:
7727 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
7728 break;
7729 case IEEE80211_AMPDU_RX_STOP:
7730 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
7731 break;
7732 default:
7733 break;
7734 }
7735 return 0;
7736}
7737
7738static int rtl8xxxu_start(struct ieee80211_hw *hw)
7739{
7740 struct rtl8xxxu_priv *priv = hw->priv;
7741 struct rtl8xxxu_rx_urb *rx_urb;
7742 struct rtl8xxxu_tx_urb *tx_urb;
7743 unsigned long flags;
7744 int ret, i;
7745
7746 ret = 0;
7747
7748 init_usb_anchor(&priv->rx_anchor);
7749 init_usb_anchor(&priv->tx_anchor);
7750 init_usb_anchor(&priv->int_anchor);
7751
db08de94 7752 priv->fops->enable_rf(priv);
0e28b975
JS		 7753 if (priv->usb_interrupts) {
7754 ret = rtl8xxxu_submit_int_urb(hw);
7755 if (ret)
7756 goto exit;
7757 }
26f1fad2
JS		 7758
7759 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7760 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7761 if (!tx_urb) {
7762 if (!i)
7763 ret = -ENOMEM;
7764
7765 goto error_out;
7766 }
7767 usb_init_urb(&tx_urb->urb);
7768 INIT_LIST_HEAD(&tx_urb->list);
7769 tx_urb->hw = hw;
7770 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7771 priv->tx_urb_free_count++;
7772 }
7773
7774 priv->tx_stopped = false;
7775
7776 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7777 priv->shutdown = false;
7778 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7779
7780 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7781 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7782 if (!rx_urb) {
7783 if (!i)
7784 ret = -ENOMEM;
7785
7786 goto error_out;
7787 }
7788 usb_init_urb(&rx_urb->urb);
7789 INIT_LIST_HEAD(&rx_urb->list);
7790 rx_urb->hw = hw;
7791
7792 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7793 }
7794exit:
7795 /*
c85ea115 7796 * Accept all data and mgmt frames
26f1fad2 7797 */
c85ea115 7798 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
26f1fad2
JS		 7799 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7800
7801 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
7802
7803 return ret;
7804
7805error_out:
7806 rtl8xxxu_free_tx_resources(priv);
7807 /*
7808 * Disable all data and mgmt frames
7809 */
7810 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7811 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7812
7813 return ret;
7814}
7815
7816static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7817{
7818 struct rtl8xxxu_priv *priv = hw->priv;
7819 unsigned long flags;
7820
7821 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7822
7823 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7824 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7825
7826 spin_lock_irqsave(&priv->rx_urb_lock, flags);
7827 priv->shutdown = true;
7828 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7829
7830 usb_kill_anchored_urbs(&priv->rx_anchor);
7831 usb_kill_anchored_urbs(&priv->tx_anchor);
0e28b975
JS		 7832 if (priv->usb_interrupts)
7833 usb_kill_anchored_urbs(&priv->int_anchor);
26f1fad2
JS		 7834
7835 rtl8723a_disable_rf(priv);
7836
7837 /*
7838 * Disable interrupts
7839 */
0e28b975
JS		 7840 if (priv->usb_interrupts)
7841 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
26f1fad2
JS		 7842
7843 rtl8xxxu_free_rx_resources(priv);
7844 rtl8xxxu_free_tx_resources(priv);
7845}
7846
7847static const struct ieee80211_ops rtl8xxxu_ops = {
7848 .tx = rtl8xxxu_tx,
7849 .add_interface = rtl8xxxu_add_interface,
7850 .remove_interface = rtl8xxxu_remove_interface,
7851 .config = rtl8xxxu_config,
7852 .conf_tx = rtl8xxxu_conf_tx,
7853 .bss_info_changed = rtl8xxxu_bss_info_changed,
7854 .configure_filter = rtl8xxxu_configure_filter,
7855 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7856 .start = rtl8xxxu_start,
7857 .stop = rtl8xxxu_stop,
7858 .sw_scan_start = rtl8xxxu_sw_scan_start,
7859 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7860 .set_key = rtl8xxxu_set_key,
7861 .ampdu_action = rtl8xxxu_ampdu_action,
7862};
7863
7864static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7865 struct usb_interface *interface)
7866{
7867 struct usb_interface_descriptor *interface_desc;
7868 struct usb_host_interface *host_interface;
7869 struct usb_endpoint_descriptor *endpoint;
7870 struct device *dev = &priv->udev->dev;
7871 int i, j = 0, endpoints;
7872 u8 dir, xtype, num;
7873 int ret = 0;
7874
7875 host_interface = &interface->altsetting[0];
7876 interface_desc = &host_interface->desc;
7877 endpoints = interface_desc->bNumEndpoints;
7878
7879 for (i = 0; i < endpoints; i++) {
7880 endpoint = &host_interface->endpoint[i].desc;
7881
7882 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7883 num = usb_endpoint_num(endpoint);
7884 xtype = usb_endpoint_type(endpoint);
7885 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7886 dev_dbg(dev,
7887 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7888 __func__, dir, num, xtype);
7889 if (usb_endpoint_dir_in(endpoint) &&
7890 usb_endpoint_xfer_bulk(endpoint)) {
7891 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7892 dev_dbg(dev, "%s: in endpoint num %i\n",
7893 __func__, num);
7894
7895 if (priv->pipe_in) {
7896 dev_warn(dev,
7897 "%s: Too many IN pipes\n", __func__);
7898 ret = -EINVAL;
7899 goto exit;
7900 }
7901
7902 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7903 }
7904
7905 if (usb_endpoint_dir_in(endpoint) &&
7906 usb_endpoint_xfer_int(endpoint)) {
7907 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7908 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7909 __func__, num);
7910
7911 if (priv->pipe_interrupt) {
7912 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7913 __func__);
7914 ret = -EINVAL;
7915 goto exit;
7916 }
7917
7918 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7919 }
7920
7921 if (usb_endpoint_dir_out(endpoint) &&
7922 usb_endpoint_xfer_bulk(endpoint)) {
7923 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7924 dev_dbg(dev, "%s: out endpoint num %i\n",
7925 __func__, num);
7926 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7927 dev_warn(dev,
7928 "%s: Too many OUT pipes\n", __func__);
7929 ret = -EINVAL;
7930 goto exit;
7931 }
7932 priv->out_ep[j++] = num;
7933 }
7934 }
7935exit:
7936 priv->nr_out_eps = j;
7937 return ret;
7938}
7939
7940static int rtl8xxxu_probe(struct usb_interface *interface,
7941 const struct usb_device_id *id)
7942{
7943 struct rtl8xxxu_priv *priv;
7944 struct ieee80211_hw *hw;
7945 struct usb_device *udev;
7946 struct ieee80211_supported_band *sband;
7947 int ret = 0;
7948 int untested = 1;
7949
7950 udev = usb_get_dev(interface_to_usbdev(interface));
7951
7952 switch (id->idVendor) {
7953 case USB_VENDOR_ID_REALTEK:
7954 switch(id->idProduct) {
7955 case 0x1724:
7956 case 0x8176:
7957 case 0x8178:
7958 case 0x817f:
7959 untested = 0;
7960 break;
7961 }
7962 break;
7963 case 0x7392:
7964 if (id->idProduct == 0x7811)
7965 untested = 0;
7966 break;
7967 default:
7968 break;
7969 }
7970
7971 if (untested) {
eaa4d14c 7972 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 7973 dev_info(&udev->dev,
7974 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7975 id->idVendor, id->idProduct);
7976 dev_info(&udev->dev,
7977 "Please report results to Jes.Sorensen@gmail.com\n");
7978 }
7979
7980 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7981 if (!hw) {
7982 ret = -ENOMEM;
7983 goto exit;
7984 }
7985
7986 priv = hw->priv;
7987 priv->hw = hw;
7988 priv->udev = udev;
7989 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7990 mutex_init(&priv->usb_buf_mutex);
7991 mutex_init(&priv->h2c_mutex);
7992 INIT_LIST_HEAD(&priv->tx_urb_free_list);
7993 spin_lock_init(&priv->tx_urb_lock);
7994 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7995 spin_lock_init(&priv->rx_urb_lock);
7996 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7997
7998 usb_set_intfdata(interface, hw);
7999
8000 ret = rtl8xxxu_parse_usb(priv, interface);
8001 if (ret)
8002 goto exit;
8003
8004 ret = rtl8xxxu_identify_chip(priv);
8005 if (ret) {
8006 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
8007 goto exit;
8008 }
8009
8010 ret = rtl8xxxu_read_efuse(priv);
8011 if (ret) {
8012 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
8013 goto exit;
8014 }
8015
8016 ret = priv->fops->parse_efuse(priv);
8017 if (ret) {
8018 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
8019 goto exit;
8020 }
8021
8022 rtl8xxxu_print_chipinfo(priv);
8023
8024 ret = priv->fops->load_firmware(priv);
8025 if (ret) {
8026 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
8027 goto exit;
8028 }
8029
8030 ret = rtl8xxxu_init_device(hw);
8031
8032 hw->wiphy->max_scan_ssids = 1;
8033 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
8034 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
8035 hw->queues = 4;
8036
8037 sband = &rtl8xxxu_supported_band;
8038 sband->ht_cap.ht_supported = true;
8039 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
8040 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
8041 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
8042 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
8043 sband->ht_cap.mcs.rx_mask[0] = 0xff;
8044 sband->ht_cap.mcs.rx_mask[4] = 0x01;
8045 if (priv->rf_paths > 1) {
8046 sband->ht_cap.mcs.rx_mask[1] = 0xff;
8047 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
8048 }
8049 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
8050 /*
8051 * Some APs will negotiate HT20_40 in a noisy environment leading
8052 * to miserable performance. Rather than defaulting to this, only
8053 * enable it if explicitly requested at module load time.
8054 */
8055 if (rtl8xxxu_ht40_2g) {
8056 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
8057 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
8058 }
8059 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
8060
8061 hw->wiphy->rts_threshold = 2347;
8062
8063 SET_IEEE80211_DEV(priv->hw, &interface->dev);
8064 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
8065
8066 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
8067 ieee80211_hw_set(hw, SIGNAL_DBM);
8068 /*
8069 * The firmware handles rate control
8070 */
8071 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
8072 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
8073
8074 ret = ieee80211_register_hw(priv->hw);
8075 if (ret) {
8076 dev_err(&udev->dev, "%s: Failed to register: %i\n",
8077 __func__, ret);
8078 goto exit;
8079 }
8080
8081exit:
8082 if (ret < 0)
8083 usb_put_dev(udev);
8084 return ret;
8085}
8086
8087static void rtl8xxxu_disconnect(struct usb_interface *interface)
8088{
8089 struct rtl8xxxu_priv *priv;
8090 struct ieee80211_hw *hw;
8091
8092 hw = usb_get_intfdata(interface);
8093 priv = hw->priv;
8094
8095 rtl8xxxu_disable_device(hw);
8096 usb_set_intfdata(interface, NULL);
8097
8098 dev_info(&priv->udev->dev, "disconnecting\n");
8099
8100 ieee80211_unregister_hw(hw);
8101
8102 kfree(priv->fw_data);
8103 mutex_destroy(&priv->usb_buf_mutex);
8104 mutex_destroy(&priv->h2c_mutex);
8105
8106 usb_put_dev(priv->udev);
8107 ieee80211_free_hw(hw);
8108}
8109
8110static struct rtl8xxxu_fileops rtl8723au_fops = {
8111 .parse_efuse = rtl8723au_parse_efuse,
8112 .load_firmware = rtl8723au_load_firmware,
8113 .power_on = rtl8723au_power_on,
74b99bed 8114 .llt_init = rtl8xxxu_init_llt_table,
e1547c53 8115 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
c3f9506f 8116 .config_channel = rtl8723au_config_channel,
b18cdfdb 8117 .parse_rx_desc = rtl8723au_parse_rx_desc,
db08de94 8118 .enable_rf = rtl8723a_enable_rf,
e796dab4 8119 .set_tx_power = rtl8723a_set_tx_power,
26f1fad2 8120 .writeN_block_size = 1024,
ed35d094
JS		 8121 .mbox_ext_reg = REG_HMBOX_EXT_0,
8122 .mbox_ext_width = 2,
8634af5e
JS		 8123 .adda_1t_init = 0x0b1b25a0,
8124 .adda_1t_path_on = 0x0bdb25a0,
8125 .adda_2t_path_on_a = 0x04db25a4,
8126 .adda_2t_path_on_b = 0x0b1b25a4,
26f1fad2
JS		 8127};
8128
35a741fe 8129static struct rtl8xxxu_fileops rtl8723bu_fops = {
3c836d60 8130 .parse_efuse = rtl8723bu_parse_efuse,
35a741fe 8131 .load_firmware = rtl8723bu_load_firmware,
42836db1 8132 .power_on = rtl8723bu_power_on,
35a741fe 8133 .llt_init = rtl8xxxu_auto_llt_table,
f0d9f5e9 8134 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
e1547c53 8135 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
c3f9506f 8136 .config_channel = rtl8723bu_config_channel,
f37e9228 8137 .init_bt = rtl8723bu_init_bt,
b18cdfdb 8138 .parse_rx_desc = rtl8723bu_parse_rx_desc,
3e88ca44 8139 .init_aggregation = rtl8723bu_init_aggregation,
9c79bf95 8140 .init_statistics = rtl8723bu_init_statistics,
db08de94 8141 .enable_rf = rtl8723b_enable_rf,
e796dab4 8142 .set_tx_power = rtl8723b_set_tx_power,
adfc0124 8143 .writeN_block_size = 1024,
ed35d094
JS		 8144 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8145 .mbox_ext_width = 4,
0d698dec 8146 .has_s0s1 = 1,
8634af5e
JS		 8147 .adda_1t_init = 0x01c00014,
8148 .adda_1t_path_on = 0x01c00014,
8149 .adda_2t_path_on_a = 0x01c00014,
8150 .adda_2t_path_on_b = 0x01c00014,
35a741fe
JS		 8151};
8152
c0963772
KV		 8153#ifdef CONFIG_RTL8XXXU_UNTESTED
8154
26f1fad2
JS		 8155static struct rtl8xxxu_fileops rtl8192cu_fops = {
8156 .parse_efuse = rtl8192cu_parse_efuse,
8157 .load_firmware = rtl8192cu_load_firmware,
8158 .power_on = rtl8192cu_power_on,
74b99bed 8159 .llt_init = rtl8xxxu_init_llt_table,
e1547c53 8160 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
c3f9506f 8161 .config_channel = rtl8723au_config_channel,
b18cdfdb 8162 .parse_rx_desc = rtl8723au_parse_rx_desc,
db08de94 8163 .enable_rf = rtl8723a_enable_rf,
e796dab4 8164 .set_tx_power = rtl8723a_set_tx_power,
26f1fad2 8165 .writeN_block_size = 128,
ed35d094
JS		 8166 .mbox_ext_reg = REG_HMBOX_EXT_0,
8167 .mbox_ext_width = 2,
8634af5e
JS		 8168 .adda_1t_init = 0x0b1b25a0,
8169 .adda_1t_path_on = 0x0bdb25a0,
8170 .adda_2t_path_on_a = 0x04db25a4,
8171 .adda_2t_path_on_b = 0x0b1b25a4,
26f1fad2
JS		 8172};
8173
c0963772
KV		 8174#endif
8175
3307d840
JS		 8176static struct rtl8xxxu_fileops rtl8192eu_fops = {
8177 .parse_efuse = rtl8192eu_parse_efuse,
8178 .load_firmware = rtl8192eu_load_firmware,
c05a9dbf 8179 .power_on = rtl8192eu_power_on,
74b99bed 8180 .llt_init = rtl8xxxu_auto_llt_table,
e1547c53 8181 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
c3f9506f 8182 .config_channel = rtl8723bu_config_channel,
b18cdfdb 8183 .parse_rx_desc = rtl8723bu_parse_rx_desc,
db08de94 8184 .enable_rf = rtl8723b_enable_rf,
e796dab4 8185 .set_tx_power = rtl8723b_set_tx_power,
c05a9dbf 8186 .writeN_block_size = 128,
ed35d094
JS		 8187 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
8188 .mbox_ext_width = 4,
0d698dec 8189 .has_s0s1 = 1,
8634af5e
JS		 8190 .adda_1t_init = 0x0fc01616,
8191 .adda_1t_path_on = 0x0fc01616,
8192 .adda_2t_path_on_a = 0x0fc01616,
8193 .adda_2t_path_on_b = 0x0fc01616,
3307d840
JS		 8194};
8195
26f1fad2
JS		 8196static struct usb_device_id dev_table[] = {
8197{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
8198 .driver_info = (unsigned long)&rtl8723au_fops},
8199{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
8200 .driver_info = (unsigned long)&rtl8723au_fops},
8201{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
8202 .driver_info = (unsigned long)&rtl8723au_fops},
3307d840
JS		 8203{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
8204 .driver_info = (unsigned long)&rtl8192eu_fops},
35a741fe
JS		 8205{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
8206 .driver_info = (unsigned long)&rtl8723bu_fops},
033695bd
KV		 8207#ifdef CONFIG_RTL8XXXU_UNTESTED
8208/* Still supported by rtlwifi */
26f1fad2
JS		 8209{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
8210 .driver_info = (unsigned long)&rtl8192cu_fops},
8211{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
8212 .driver_info = (unsigned long)&rtl8192cu_fops},
8213{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
8214 .driver_info = (unsigned long)&rtl8192cu_fops},
8215/* Tested by Larry Finger */
8216{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
8217 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 8218/* Currently untested 8188 series devices */
8219{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
8220 .driver_info = (unsigned long)&rtl8192cu_fops},
8221{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
8222 .driver_info = (unsigned long)&rtl8192cu_fops},
8223{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
8224 .driver_info = (unsigned long)&rtl8192cu_fops},
8225{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
8226 .driver_info = (unsigned long)&rtl8192cu_fops},
8227{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
8228 .driver_info = (unsigned long)&rtl8192cu_fops},
8229{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
8230 .driver_info = (unsigned long)&rtl8192cu_fops},
8231{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
8232 .driver_info = (unsigned long)&rtl8192cu_fops},
8233{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
8234 .driver_info = (unsigned long)&rtl8192cu_fops},
8235{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
8236 .driver_info = (unsigned long)&rtl8192cu_fops},
8237{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
8238 .driver_info = (unsigned long)&rtl8192cu_fops},
8239{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
8240 .driver_info = (unsigned long)&rtl8192cu_fops},
8241{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
8242 .driver_info = (unsigned long)&rtl8192cu_fops},
8243{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
8244 .driver_info = (unsigned long)&rtl8192cu_fops},
8245{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
8246 .driver_info = (unsigned long)&rtl8192cu_fops},
8247{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
8248 .driver_info = (unsigned long)&rtl8192cu_fops},
8249{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
8250 .driver_info = (unsigned long)&rtl8192cu_fops},
8251{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
8252 .driver_info = (unsigned long)&rtl8192cu_fops},
8253{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
8254 .driver_info = (unsigned long)&rtl8192cu_fops},
8255{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
8256 .driver_info = (unsigned long)&rtl8192cu_fops},
8257{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
8258 .driver_info = (unsigned long)&rtl8192cu_fops},
8259{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
8260 .driver_info = (unsigned long)&rtl8192cu_fops},
8261{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
8262 .driver_info = (unsigned long)&rtl8192cu_fops},
8263{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
8264 .driver_info = (unsigned long)&rtl8192cu_fops},
8265{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
8266 .driver_info = (unsigned long)&rtl8192cu_fops},
8267{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
8268 .driver_info = (unsigned long)&rtl8192cu_fops},
8269{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
8270 .driver_info = (unsigned long)&rtl8192cu_fops},
8271{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
8272 .driver_info = (unsigned long)&rtl8192cu_fops},
8273{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
8274 .driver_info = (unsigned long)&rtl8192cu_fops},
8275{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
8276 .driver_info = (unsigned long)&rtl8192cu_fops},
8277{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
8278 .driver_info = (unsigned long)&rtl8192cu_fops},
8279{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
8280 .driver_info = (unsigned long)&rtl8192cu_fops},
8281{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
8282 .driver_info = (unsigned long)&rtl8192cu_fops},
8283{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
8284 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 8285{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
8286 .driver_info = (unsigned long)&rtl8192cu_fops},
8287{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
8288 .driver_info = (unsigned long)&rtl8192cu_fops},
8289{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
8290 .driver_info = (unsigned long)&rtl8192cu_fops},
8291{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
8292 .driver_info = (unsigned long)&rtl8192cu_fops},
8293{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
8294 .driver_info = (unsigned long)&rtl8192cu_fops},
8295{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
8296 .driver_info = (unsigned long)&rtl8192cu_fops},
8297{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
8298 .driver_info = (unsigned long)&rtl8192cu_fops},
8299/* Currently untested 8192 series devices */
8300{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
8301 .driver_info = (unsigned long)&rtl8192cu_fops},
8302{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
8303 .driver_info = (unsigned long)&rtl8192cu_fops},
8304{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
8305 .driver_info = (unsigned long)&rtl8192cu_fops},
8306{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
8307 .driver_info = (unsigned long)&rtl8192cu_fops},
8308{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
8309 .driver_info = (unsigned long)&rtl8192cu_fops},
8310{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
8311 .driver_info = (unsigned long)&rtl8192cu_fops},
8312{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
8313 .driver_info = (unsigned long)&rtl8192cu_fops},
8314{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
8315 .driver_info = (unsigned long)&rtl8192cu_fops},
8316{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
8317 .driver_info = (unsigned long)&rtl8192cu_fops},
8318{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
8319 .driver_info = (unsigned long)&rtl8192cu_fops},
8320{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
8321 .driver_info = (unsigned long)&rtl8192cu_fops},
8322{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
8323 .driver_info = (unsigned long)&rtl8192cu_fops},
8324{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
8325 .driver_info = (unsigned long)&rtl8192cu_fops},
8326{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
8327 .driver_info = (unsigned long)&rtl8192cu_fops},
8328{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
8329 .driver_info = (unsigned long)&rtl8192cu_fops},
8330{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
8331 .driver_info = (unsigned long)&rtl8192cu_fops},
8332{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
8333 .driver_info = (unsigned long)&rtl8192cu_fops},
8334{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
8335 .driver_info = (unsigned long)&rtl8192cu_fops},
8336{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
8337 .driver_info = (unsigned long)&rtl8192cu_fops},
8338{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
8339 .driver_info = (unsigned long)&rtl8192cu_fops},
8340{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
8341 .driver_info = (unsigned long)&rtl8192cu_fops},
8342{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
8343 .driver_info = (unsigned long)&rtl8192cu_fops},
8344{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
8345 .driver_info = (unsigned long)&rtl8192cu_fops},
8346{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
8347 .driver_info = (unsigned long)&rtl8192cu_fops},
8348{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
8349 .driver_info = (unsigned long)&rtl8192cu_fops},
8350#endif
8351{ }
8352};
8353
8354static struct usb_driver rtl8xxxu_driver = {
8355 .name = DRIVER_NAME,
8356 .probe = rtl8xxxu_probe,
8357 .disconnect = rtl8xxxu_disconnect,
8358 .id_table = dev_table,
8359 .disable_hub_initiated_lpm = 1,
8360};
8361
8362static int __init rtl8xxxu_module_init(void)
8363{
8364 int res;
8365
8366 res = usb_register(&rtl8xxxu_driver);
8367 if (res < 0)
8368 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
8369
8370 return res;
8371}
8372
8373static void __exit rtl8xxxu_module_exit(void)
8374{
8375 usb_deregister(&rtl8xxxu_driver);
8376}
8377
8378
8379MODULE_DEVICE_TABLE(usb, dev_table);
8380
8381module_init(rtl8xxxu_module_init);
8382module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
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