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26f1fad2 JS |
1 | /* |
2 | * RTL8XXXU mac80211 USB driver | |
3 | * | |
4 | * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> | |
5 | * | |
6 | * Portions, notably calibration code: | |
7 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. | |
8 | * | |
9 | * This driver was written as a replacement for the vendor provided | |
10 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in | |
11 | * their programming interface, I have started adding support for | |
12 | * additional 8xxx chips like the 8192cu, 8188cus, etc. | |
13 | * | |
14 | * This program is free software; you can redistribute it and/or modify it | |
15 | * under the terms of version 2 of the GNU General Public License as | |
16 | * published by the Free Software Foundation. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
19 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
20 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
21 | * more details. | |
22 | */ | |
23 | ||
24 | #include <linux/init.h> | |
25 | #include <linux/kernel.h> | |
26 | #include <linux/sched.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/usb.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/ethtool.h> | |
36 | #include <linux/wireless.h> | |
37 | #include <linux/firmware.h> | |
38 | #include <linux/moduleparam.h> | |
39 | #include <net/mac80211.h> | |
40 | #include "rtl8xxxu.h" | |
41 | #include "rtl8xxxu_regs.h" | |
42 | ||
43 | #define DRIVER_NAME "rtl8xxxu" | |
44 | ||
3307d840 | 45 | static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE; |
26f1fad2 JS |
46 | static bool rtl8xxxu_ht40_2g; |
47 | ||
48 | MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>"); | |
49 | MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); | |
50 | MODULE_LICENSE("GPL"); | |
51 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); | |
52 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); | |
53 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); | |
54 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); | |
55 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); | |
56 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); | |
b001e086 | 57 | MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); |
35a741fe JS |
58 | MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); |
59 | MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); | |
26f1fad2 JS |
60 | |
61 | module_param_named(debug, rtl8xxxu_debug, int, 0600); | |
62 | MODULE_PARM_DESC(debug, "Set debug mask"); | |
63 | module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); | |
64 | MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); | |
65 | ||
66 | #define USB_VENDOR_ID_REALTEK 0x0bda | |
67 | /* Minimum IEEE80211_MAX_FRAME_LEN */ | |
68 | #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN | |
69 | #define RTL8XXXU_RX_URBS 32 | |
70 | #define RTL8XXXU_RX_URB_PENDING_WATER 8 | |
71 | #define RTL8XXXU_TX_URBS 64 | |
72 | #define RTL8XXXU_TX_URB_LOW_WATER 25 | |
73 | #define RTL8XXXU_TX_URB_HIGH_WATER 32 | |
74 | ||
75 | static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, | |
76 | struct rtl8xxxu_rx_urb *rx_urb); | |
77 | ||
78 | static struct ieee80211_rate rtl8xxxu_rates[] = { | |
79 | { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, | |
80 | { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, | |
81 | { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, | |
82 | { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, | |
83 | { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, | |
84 | { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, | |
85 | { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, | |
86 | { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, | |
87 | { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, | |
88 | { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, | |
89 | { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, | |
90 | { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, | |
91 | }; | |
92 | ||
93 | static struct ieee80211_channel rtl8xxxu_channels_2g[] = { | |
57fbcce3 | 94 | { .band = NL80211_BAND_2GHZ, .center_freq = 2412, |
26f1fad2 | 95 | .hw_value = 1, .max_power = 30 }, |
57fbcce3 | 96 | { .band = NL80211_BAND_2GHZ, .center_freq = 2417, |
26f1fad2 | 97 | .hw_value = 2, .max_power = 30 }, |
57fbcce3 | 98 | { .band = NL80211_BAND_2GHZ, .center_freq = 2422, |
26f1fad2 | 99 | .hw_value = 3, .max_power = 30 }, |
57fbcce3 | 100 | { .band = NL80211_BAND_2GHZ, .center_freq = 2427, |
26f1fad2 | 101 | .hw_value = 4, .max_power = 30 }, |
57fbcce3 | 102 | { .band = NL80211_BAND_2GHZ, .center_freq = 2432, |
26f1fad2 | 103 | .hw_value = 5, .max_power = 30 }, |
57fbcce3 | 104 | { .band = NL80211_BAND_2GHZ, .center_freq = 2437, |
26f1fad2 | 105 | .hw_value = 6, .max_power = 30 }, |
57fbcce3 | 106 | { .band = NL80211_BAND_2GHZ, .center_freq = 2442, |
26f1fad2 | 107 | .hw_value = 7, .max_power = 30 }, |
57fbcce3 | 108 | { .band = NL80211_BAND_2GHZ, .center_freq = 2447, |
26f1fad2 | 109 | .hw_value = 8, .max_power = 30 }, |
57fbcce3 | 110 | { .band = NL80211_BAND_2GHZ, .center_freq = 2452, |
26f1fad2 | 111 | .hw_value = 9, .max_power = 30 }, |
57fbcce3 | 112 | { .band = NL80211_BAND_2GHZ, .center_freq = 2457, |
26f1fad2 | 113 | .hw_value = 10, .max_power = 30 }, |
57fbcce3 | 114 | { .band = NL80211_BAND_2GHZ, .center_freq = 2462, |
26f1fad2 | 115 | .hw_value = 11, .max_power = 30 }, |
57fbcce3 | 116 | { .band = NL80211_BAND_2GHZ, .center_freq = 2467, |
26f1fad2 | 117 | .hw_value = 12, .max_power = 30 }, |
57fbcce3 | 118 | { .band = NL80211_BAND_2GHZ, .center_freq = 2472, |
26f1fad2 | 119 | .hw_value = 13, .max_power = 30 }, |
57fbcce3 | 120 | { .band = NL80211_BAND_2GHZ, .center_freq = 2484, |
26f1fad2 JS |
121 | .hw_value = 14, .max_power = 30 } |
122 | }; | |
123 | ||
124 | static struct ieee80211_supported_band rtl8xxxu_supported_band = { | |
125 | .channels = rtl8xxxu_channels_2g, | |
126 | .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), | |
127 | .bitrates = rtl8xxxu_rates, | |
128 | .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), | |
129 | }; | |
130 | ||
131 | static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = { | |
132 | {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, | |
133 | {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, | |
134 | {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, | |
135 | {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, | |
136 | {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, | |
137 | {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, | |
138 | {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, | |
139 | {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, | |
140 | {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, | |
141 | {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, | |
142 | {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, | |
143 | {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, | |
144 | {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, | |
145 | {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, | |
146 | {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, | |
147 | {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, | |
148 | {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, | |
149 | {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, | |
150 | {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, | |
151 | {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, | |
152 | {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, | |
153 | {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, | |
154 | }; | |
155 | ||
b7dd8ff9 JS |
156 | static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { |
157 | {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, | |
158 | {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10}, | |
159 | {0x430, 0x00}, {0x431, 0x00}, | |
160 | {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, | |
161 | {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, | |
162 | {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, | |
163 | {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, | |
164 | {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, | |
165 | {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, | |
166 | {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, | |
167 | {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, | |
168 | {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, | |
169 | {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, | |
170 | {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, | |
171 | {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, | |
172 | {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, | |
173 | {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, | |
174 | {0x516, 0x0a}, {0x525, 0x4f}, | |
175 | {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, | |
176 | {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, | |
177 | {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, | |
178 | {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, | |
179 | {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, | |
180 | {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, | |
181 | {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, | |
182 | {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, | |
183 | {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04}, | |
184 | {0xffff, 0xff}, | |
185 | }; | |
186 | ||
c606e662 JS |
187 | static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = { |
188 | {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7}, | |
189 | {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00}, | |
190 | {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, | |
191 | {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, | |
192 | {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, | |
193 | {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, | |
194 | {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, | |
195 | {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, | |
196 | {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, | |
197 | {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, | |
198 | {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, | |
199 | {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, | |
200 | {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, | |
201 | {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, | |
202 | {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, | |
203 | {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, | |
204 | {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10}, | |
205 | {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff}, | |
206 | {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff}, | |
207 | {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, | |
208 | {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, | |
209 | {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, | |
210 | {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, | |
211 | {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, | |
212 | {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, | |
213 | {0x70b, 0x87}, | |
214 | {0xffff, 0xff}, | |
215 | }; | |
216 | ||
26f1fad2 JS |
217 | static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { |
218 | {0x800, 0x80040000}, {0x804, 0x00000003}, | |
219 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, | |
220 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, | |
221 | {0x818, 0x02200385}, {0x81c, 0x00000000}, | |
222 | {0x820, 0x01000100}, {0x824, 0x00390004}, | |
223 | {0x828, 0x00000000}, {0x82c, 0x00000000}, | |
224 | {0x830, 0x00000000}, {0x834, 0x00000000}, | |
225 | {0x838, 0x00000000}, {0x83c, 0x00000000}, | |
226 | {0x840, 0x00010000}, {0x844, 0x00000000}, | |
227 | {0x848, 0x00000000}, {0x84c, 0x00000000}, | |
228 | {0x850, 0x00000000}, {0x854, 0x00000000}, | |
229 | {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, | |
230 | {0x860, 0x66f60110}, {0x864, 0x061f0130}, | |
231 | {0x868, 0x00000000}, {0x86c, 0x32323200}, | |
232 | {0x870, 0x07000760}, {0x874, 0x22004000}, | |
233 | {0x878, 0x00000808}, {0x87c, 0x00000000}, | |
234 | {0x880, 0xc0083070}, {0x884, 0x000004d5}, | |
235 | {0x888, 0x00000000}, {0x88c, 0xccc000c0}, | |
236 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, | |
237 | {0x898, 0x40302010}, {0x89c, 0x00706050}, | |
238 | {0x900, 0x00000000}, {0x904, 0x00000023}, | |
239 | {0x908, 0x00000000}, {0x90c, 0x81121111}, | |
240 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, | |
241 | {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, | |
242 | {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, | |
243 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, | |
244 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, | |
245 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, | |
246 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, | |
247 | {0xa78, 0x00000900}, | |
248 | {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, | |
249 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, | |
250 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, | |
251 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, | |
252 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, | |
253 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, | |
254 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, | |
255 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, | |
256 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, | |
257 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, | |
258 | {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, | |
259 | {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, | |
260 | {0xc60, 0x00000000}, {0xc64, 0x7112848b}, | |
261 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, | |
262 | {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, | |
263 | {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, | |
264 | {0xc80, 0x40000100}, {0xc84, 0x20f60000}, | |
265 | {0xc88, 0x40000100}, {0xc8c, 0x20200000}, | |
266 | {0xc90, 0x00121820}, {0xc94, 0x00000000}, | |
267 | {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, | |
268 | {0xca0, 0x00000000}, {0xca4, 0x00000080}, | |
269 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, | |
270 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, | |
271 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, | |
272 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, | |
273 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, | |
274 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, | |
275 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, | |
276 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, | |
277 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, | |
278 | {0xd00, 0x00080740}, {0xd04, 0x00020401}, | |
279 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, | |
280 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, | |
281 | {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, | |
282 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, | |
283 | {0xd38, 0x00000000}, {0xd3c, 0x00027293}, | |
284 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, | |
285 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, | |
286 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, | |
287 | {0xd58, 0x00000000}, {0xd5c, 0x30032064}, | |
288 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, | |
289 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, | |
290 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, | |
291 | {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, | |
292 | {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, | |
293 | {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, | |
294 | {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, | |
295 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, | |
296 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, | |
297 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, | |
298 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, | |
299 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, | |
300 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, | |
301 | {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, | |
302 | {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, | |
303 | {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, | |
304 | {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, | |
305 | {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, | |
306 | {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, | |
307 | {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, | |
308 | {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, | |
309 | {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, | |
310 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, | |
311 | {0xf00, 0x00000300}, | |
312 | {0xffff, 0xffffffff}, | |
313 | }; | |
314 | ||
36c32588 JS |
315 | static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = { |
316 | {0x800, 0x80040000}, {0x804, 0x00000003}, | |
317 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, | |
318 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, | |
319 | {0x818, 0x02200385}, {0x81c, 0x00000000}, | |
320 | {0x820, 0x01000100}, {0x824, 0x00190204}, | |
321 | {0x828, 0x00000000}, {0x82c, 0x00000000}, | |
322 | {0x830, 0x00000000}, {0x834, 0x00000000}, | |
323 | {0x838, 0x00000000}, {0x83c, 0x00000000}, | |
324 | {0x840, 0x00010000}, {0x844, 0x00000000}, | |
325 | {0x848, 0x00000000}, {0x84c, 0x00000000}, | |
326 | {0x850, 0x00000000}, {0x854, 0x00000000}, | |
327 | {0x858, 0x569a11a9}, {0x85c, 0x01000014}, | |
328 | {0x860, 0x66f60110}, {0x864, 0x061f0649}, | |
329 | {0x868, 0x00000000}, {0x86c, 0x27272700}, | |
330 | {0x870, 0x07000760}, {0x874, 0x25004000}, | |
331 | {0x878, 0x00000808}, {0x87c, 0x00000000}, | |
332 | {0x880, 0xb0000c1c}, {0x884, 0x00000001}, | |
333 | {0x888, 0x00000000}, {0x88c, 0xccc000c0}, | |
334 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, | |
335 | {0x898, 0x40302010}, {0x89c, 0x00706050}, | |
336 | {0x900, 0x00000000}, {0x904, 0x00000023}, | |
337 | {0x908, 0x00000000}, {0x90c, 0x81121111}, | |
338 | {0x910, 0x00000002}, {0x914, 0x00000201}, | |
339 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, | |
340 | {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, | |
341 | {0xa10, 0x9500bb78}, {0xa14, 0x1114d028}, | |
342 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, | |
343 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, | |
344 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, | |
345 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, | |
346 | {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, | |
347 | {0xa80, 0x21806490}, {0xb2c, 0x00000000}, | |
348 | {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, | |
349 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, | |
350 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, | |
351 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, | |
352 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, | |
353 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, | |
354 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, | |
355 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, | |
356 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, | |
357 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, | |
358 | {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, | |
359 | {0xc58, 0x00013149}, {0xc5c, 0x00250492}, | |
360 | {0xc60, 0x00000000}, {0xc64, 0x7112848b}, | |
361 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, | |
362 | {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, | |
363 | {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, | |
364 | {0xc80, 0x390000e4}, {0xc84, 0x20f60000}, | |
365 | {0xc88, 0x40000100}, {0xc8c, 0x20200000}, | |
366 | {0xc90, 0x00020e1a}, {0xc94, 0x00000000}, | |
367 | {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f}, | |
368 | {0xca0, 0x00000000}, {0xca4, 0x000300a0}, | |
369 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, | |
370 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, | |
371 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, | |
372 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, | |
373 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, | |
374 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, | |
375 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, | |
376 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, | |
377 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, | |
378 | {0xd00, 0x00000740}, {0xd04, 0x40020401}, | |
379 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, | |
380 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc53}, | |
381 | {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, | |
382 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, | |
383 | {0xd38, 0x00000000}, {0xd3c, 0x00127353}, | |
384 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, | |
385 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, | |
386 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, | |
387 | {0xd58, 0x00000282}, {0xd5c, 0x30032064}, | |
388 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, | |
389 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, | |
390 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, | |
391 | {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, | |
392 | {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, | |
393 | {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, | |
394 | {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, | |
395 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, | |
396 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, | |
397 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, | |
398 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, | |
399 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, | |
400 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, | |
401 | {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, | |
402 | {0xe68, 0x001b2556}, {0xe6c, 0x00c00096}, | |
403 | {0xe70, 0x00c00096}, {0xe74, 0x01000056}, | |
404 | {0xe78, 0x01000014}, {0xe7c, 0x01000056}, | |
405 | {0xe80, 0x01000014}, {0xe84, 0x00c00096}, | |
406 | {0xe88, 0x01000056}, {0xe8c, 0x00c00096}, | |
407 | {0xed0, 0x00c00096}, {0xed4, 0x00c00096}, | |
408 | {0xed8, 0x00c00096}, {0xedc, 0x000000d6}, | |
409 | {0xee0, 0x000000d6}, {0xeec, 0x01c00016}, | |
410 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, | |
411 | {0xf00, 0x00000300}, | |
412 | {0x820, 0x01000100}, {0x800, 0x83040000}, | |
413 | {0xffff, 0xffffffff}, | |
414 | }; | |
415 | ||
26f1fad2 JS |
416 | static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { |
417 | {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, | |
418 | {0x800, 0x80040002}, {0x804, 0x00000003}, | |
419 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, | |
420 | {0x810, 0x10000330}, {0x814, 0x020c3d10}, | |
421 | {0x818, 0x02200385}, {0x81c, 0x00000000}, | |
422 | {0x820, 0x01000100}, {0x824, 0x00390004}, | |
423 | {0x828, 0x01000100}, {0x82c, 0x00390004}, | |
424 | {0x830, 0x27272727}, {0x834, 0x27272727}, | |
425 | {0x838, 0x27272727}, {0x83c, 0x27272727}, | |
426 | {0x840, 0x00010000}, {0x844, 0x00010000}, | |
427 | {0x848, 0x27272727}, {0x84c, 0x27272727}, | |
428 | {0x850, 0x00000000}, {0x854, 0x00000000}, | |
429 | {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, | |
430 | {0x860, 0x66e60230}, {0x864, 0x061f0130}, | |
431 | {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, | |
432 | {0x870, 0x07000700}, {0x874, 0x22184000}, | |
433 | {0x878, 0x08080808}, {0x87c, 0x00000000}, | |
434 | {0x880, 0xc0083070}, {0x884, 0x000004d5}, | |
435 | {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, | |
436 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, | |
437 | {0x898, 0x40302010}, {0x89c, 0x00706050}, | |
438 | {0x900, 0x00000000}, {0x904, 0x00000023}, | |
439 | {0x908, 0x00000000}, {0x90c, 0x81121313}, | |
440 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, | |
441 | {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, | |
442 | {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, | |
443 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, | |
444 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, | |
445 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, | |
446 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, | |
447 | {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, | |
448 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, | |
449 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, | |
450 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, | |
451 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, | |
452 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, | |
453 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, | |
454 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, | |
455 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, | |
456 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, | |
457 | {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, | |
458 | {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, | |
459 | {0xc60, 0x00000000}, {0xc64, 0x5116848b}, | |
460 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, | |
461 | {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, | |
462 | {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, | |
463 | {0xc80, 0x40000100}, {0xc84, 0x20f60000}, | |
464 | {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, | |
465 | {0xc90, 0x00121820}, {0xc94, 0x00000000}, | |
466 | {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, | |
467 | {0xca0, 0x00000000}, {0xca4, 0x00000080}, | |
468 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, | |
469 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, | |
470 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, | |
471 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, | |
472 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, | |
473 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, | |
474 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, | |
475 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, | |
476 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, | |
477 | {0xd00, 0x00080740}, {0xd04, 0x00020403}, | |
478 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, | |
479 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, | |
480 | {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, | |
481 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, | |
482 | {0xd38, 0x00000000}, {0xd3c, 0x00027293}, | |
483 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, | |
484 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, | |
485 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, | |
486 | {0xd58, 0x00000000}, {0xd5c, 0x30032064}, | |
487 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, | |
488 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, | |
489 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, | |
490 | {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, | |
491 | {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, | |
492 | {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, | |
493 | {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, | |
494 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, | |
495 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, | |
496 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, | |
497 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, | |
498 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, | |
499 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, | |
500 | {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, | |
501 | {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, | |
502 | {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, | |
503 | {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, | |
504 | {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, | |
505 | {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, | |
506 | {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, | |
507 | {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, | |
508 | {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, | |
509 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, | |
510 | {0xf00, 0x00000300}, | |
511 | {0xffff, 0xffffffff}, | |
512 | }; | |
513 | ||
514 | static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { | |
515 | {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, | |
516 | {0x040, 0x000c0004}, {0x800, 0x80040000}, | |
517 | {0x804, 0x00000001}, {0x808, 0x0000fc00}, | |
518 | {0x80c, 0x0000000a}, {0x810, 0x10005388}, | |
519 | {0x814, 0x020c3d10}, {0x818, 0x02200385}, | |
520 | {0x81c, 0x00000000}, {0x820, 0x01000100}, | |
521 | {0x824, 0x00390204}, {0x828, 0x00000000}, | |
522 | {0x82c, 0x00000000}, {0x830, 0x00000000}, | |
523 | {0x834, 0x00000000}, {0x838, 0x00000000}, | |
524 | {0x83c, 0x00000000}, {0x840, 0x00010000}, | |
525 | {0x844, 0x00000000}, {0x848, 0x00000000}, | |
526 | {0x84c, 0x00000000}, {0x850, 0x00000000}, | |
527 | {0x854, 0x00000000}, {0x858, 0x569a569a}, | |
528 | {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, | |
529 | {0x864, 0x061f0130}, {0x868, 0x00000000}, | |
530 | {0x86c, 0x20202000}, {0x870, 0x03000300}, | |
531 | {0x874, 0x22004000}, {0x878, 0x00000808}, | |
532 | {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, | |
533 | {0x884, 0x000004d5}, {0x888, 0x00000000}, | |
534 | {0x88c, 0xccc000c0}, {0x890, 0x00000800}, | |
535 | {0x894, 0xfffffffe}, {0x898, 0x40302010}, | |
536 | {0x89c, 0x00706050}, {0x900, 0x00000000}, | |
537 | {0x904, 0x00000023}, {0x908, 0x00000000}, | |
538 | {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, | |
539 | {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, | |
540 | {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, | |
541 | {0xa14, 0x11144028}, {0xa18, 0x00881117}, | |
542 | {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, | |
543 | {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, | |
544 | {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, | |
545 | {0xa74, 0x00000007}, {0xc00, 0x48071d40}, | |
546 | {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, | |
547 | {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, | |
548 | {0xc14, 0x40000100}, {0xc18, 0x08800000}, | |
549 | {0xc1c, 0x40000100}, {0xc20, 0x00000000}, | |
550 | {0xc24, 0x00000000}, {0xc28, 0x00000000}, | |
551 | {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, | |
552 | {0xc34, 0x469652cf}, {0xc38, 0x49795994}, | |
553 | {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, | |
554 | {0xc44, 0x000100b7}, {0xc48, 0xec020107}, | |
555 | {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, | |
556 | {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, | |
557 | {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, | |
558 | {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, | |
559 | {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, | |
560 | {0xc74, 0x018610db}, {0xc78, 0x0000001f}, | |
561 | {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, | |
562 | {0xc84, 0x20f60000}, {0xc88, 0x24000090}, | |
563 | {0xc8c, 0x20200000}, {0xc90, 0x00121820}, | |
564 | {0xc94, 0x00000000}, {0xc98, 0x00121820}, | |
565 | {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, | |
566 | {0xca4, 0x00000080}, {0xca8, 0x00000000}, | |
567 | {0xcac, 0x00000000}, {0xcb0, 0x00000000}, | |
568 | {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, | |
569 | {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, | |
570 | {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, | |
571 | {0xccc, 0x00000000}, {0xcd0, 0x00000000}, | |
572 | {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, | |
573 | {0xcdc, 0x00766932}, {0xce0, 0x00222222}, | |
574 | {0xce4, 0x00000000}, {0xce8, 0x37644302}, | |
575 | {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, | |
576 | {0xd04, 0x00020401}, {0xd08, 0x0000907f}, | |
577 | {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, | |
578 | {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, | |
579 | {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, | |
580 | {0xd34, 0x80608000}, {0xd38, 0x00000000}, | |
581 | {0xd3c, 0x00027293}, {0xd40, 0x00000000}, | |
582 | {0xd44, 0x00000000}, {0xd48, 0x00000000}, | |
583 | {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, | |
584 | {0xd54, 0x00000000}, {0xd58, 0x00000000}, | |
585 | {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, | |
586 | {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, | |
587 | {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, | |
588 | {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, | |
589 | {0xe00, 0x24242424}, {0xe04, 0x24242424}, | |
590 | {0xe08, 0x03902024}, {0xe10, 0x24242424}, | |
591 | {0xe14, 0x24242424}, {0xe18, 0x24242424}, | |
592 | {0xe1c, 0x24242424}, {0xe28, 0x00000000}, | |
593 | {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, | |
594 | {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, | |
595 | {0xe40, 0x01007c00}, {0xe44, 0x01004800}, | |
596 | {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, | |
597 | {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, | |
598 | {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, | |
599 | {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, | |
600 | {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, | |
601 | {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, | |
602 | {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, | |
603 | {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, | |
604 | {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, | |
605 | {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, | |
606 | {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, | |
607 | {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, | |
608 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, | |
609 | {0xf00, 0x00000300}, | |
610 | {0xffff, 0xffffffff}, | |
611 | }; | |
612 | ||
ae14c5d2 JS |
613 | static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = { |
614 | {0x800, 0x80040000}, {0x804, 0x00000003}, | |
615 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, | |
616 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, | |
617 | {0x818, 0x02220385}, {0x81c, 0x00000000}, | |
618 | {0x820, 0x01000100}, {0x824, 0x00390204}, | |
619 | {0x828, 0x01000100}, {0x82c, 0x00390204}, | |
620 | {0x830, 0x32323232}, {0x834, 0x30303030}, | |
621 | {0x838, 0x30303030}, {0x83c, 0x30303030}, | |
622 | {0x840, 0x00010000}, {0x844, 0x00010000}, | |
623 | {0x848, 0x28282828}, {0x84c, 0x28282828}, | |
624 | {0x850, 0x00000000}, {0x854, 0x00000000}, | |
625 | {0x858, 0x009a009a}, {0x85c, 0x01000014}, | |
626 | {0x860, 0x66f60000}, {0x864, 0x061f0000}, | |
627 | {0x868, 0x30303030}, {0x86c, 0x30303030}, | |
628 | {0x870, 0x00000000}, {0x874, 0x55004200}, | |
629 | {0x878, 0x08080808}, {0x87c, 0x00000000}, | |
630 | {0x880, 0xb0000c1c}, {0x884, 0x00000001}, | |
631 | {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, | |
632 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, | |
633 | {0x898, 0x40302010}, {0x900, 0x00000000}, | |
634 | {0x904, 0x00000023}, {0x908, 0x00000000}, | |
635 | {0x90c, 0x81121313}, {0x910, 0x806c0001}, | |
636 | {0x914, 0x00000001}, {0x918, 0x00000000}, | |
637 | {0x91c, 0x00010000}, {0x924, 0x00000001}, | |
638 | {0x928, 0x00000000}, {0x92c, 0x00000000}, | |
639 | {0x930, 0x00000000}, {0x934, 0x00000000}, | |
640 | {0x938, 0x00000000}, {0x93c, 0x00000000}, | |
641 | {0x940, 0x00000000}, {0x944, 0x00000000}, | |
642 | {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8}, | |
643 | {0xa04, 0x81ff000c}, {0xa08, 0x8c838300}, | |
644 | {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78}, | |
645 | {0xa14, 0x1114d028}, {0xa18, 0x00881117}, | |
646 | {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000}, | |
647 | {0xa24, 0x090e1317}, {0xa28, 0x00000204}, | |
648 | {0xa2c, 0x00d30000}, {0xa70, 0x101fff00}, | |
649 | {0xa74, 0x00000007}, {0xa78, 0x00000900}, | |
650 | {0xa7c, 0x225b0606}, {0xa80, 0x218075b1}, | |
651 | {0xb38, 0x00000000}, {0xc00, 0x48071d40}, | |
652 | {0xc04, 0x03a05633}, {0xc08, 0x000000e4}, | |
653 | {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, | |
654 | {0xc14, 0x40000100}, {0xc18, 0x08800000}, | |
655 | {0xc1c, 0x40000100}, {0xc20, 0x00000000}, | |
656 | {0xc24, 0x00000000}, {0xc28, 0x00000000}, | |
657 | {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47}, | |
658 | {0xc34, 0x469652af}, {0xc38, 0x49795994}, | |
659 | {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, | |
660 | {0xc44, 0x000100b7}, {0xc48, 0xec020107}, | |
661 | {0xc4c, 0x007f037f}, | |
662 | #ifdef EXT_PA_8192EU | |
663 | /* External PA or external LNA */ | |
664 | {0xc50, 0x00340220}, | |
665 | #else | |
666 | {0xc50, 0x00340020}, | |
667 | #endif | |
668 | {0xc54, 0x0080801f}, | |
669 | #ifdef EXT_PA_8192EU | |
670 | /* External PA or external LNA */ | |
671 | {0xc58, 0x00000220}, | |
672 | #else | |
673 | {0xc58, 0x00000020}, | |
674 | #endif | |
675 | {0xc5c, 0x00248492}, {0xc60, 0x00000000}, | |
676 | {0xc64, 0x7112848b}, {0xc68, 0x47c00bff}, | |
677 | {0xc6c, 0x00000036}, {0xc70, 0x00000600}, | |
678 | {0xc74, 0x02013169}, {0xc78, 0x0000001f}, | |
679 | {0xc7c, 0x00b91612}, | |
680 | #ifdef EXT_PA_8192EU | |
681 | /* External PA or external LNA */ | |
682 | {0xc80, 0x2d4000b5}, | |
683 | #else | |
684 | {0xc80, 0x40000100}, | |
685 | #endif | |
686 | {0xc84, 0x21f60000}, | |
687 | #ifdef EXT_PA_8192EU | |
688 | /* External PA or external LNA */ | |
689 | {0xc88, 0x2d4000b5}, | |
690 | #else | |
691 | {0xc88, 0x40000100}, | |
692 | #endif | |
693 | {0xc8c, 0xa0e40000}, {0xc90, 0x00121820}, | |
694 | {0xc94, 0x00000000}, {0xc98, 0x00121820}, | |
695 | {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, | |
696 | {0xca4, 0x000300a0}, {0xca8, 0x00000000}, | |
697 | {0xcac, 0x00000000}, {0xcb0, 0x00000000}, | |
698 | {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, | |
699 | {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, | |
700 | {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, | |
701 | {0xccc, 0x00000000}, {0xcd0, 0x00000000}, | |
702 | {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, | |
703 | {0xcdc, 0x00766932}, {0xce0, 0x00222222}, | |
704 | {0xce4, 0x00040000}, {0xce8, 0x77644302}, | |
705 | {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, | |
706 | {0xd04, 0x00020403}, {0xd08, 0x0000907f}, | |
707 | {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, | |
708 | {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, | |
709 | {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975}, | |
710 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, | |
711 | {0xd38, 0x00000000}, {0xd3c, 0x00127353}, | |
712 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, | |
713 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, | |
714 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, | |
715 | {0xd58, 0x00000282}, {0xd5c, 0x30032064}, | |
716 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, | |
717 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, | |
718 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, | |
719 | {0xd78, 0x000e3c24}, {0xd80, 0x01081008}, | |
720 | {0xd84, 0x00000800}, {0xd88, 0xf0b50000}, | |
721 | {0xe00, 0x30303030}, {0xe04, 0x30303030}, | |
722 | {0xe08, 0x03903030}, {0xe10, 0x30303030}, | |
723 | {0xe14, 0x30303030}, {0xe18, 0x30303030}, | |
724 | {0xe1c, 0x30303030}, {0xe28, 0x00000000}, | |
725 | {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, | |
726 | {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, | |
727 | {0xe40, 0x01007c00}, {0xe44, 0x01004800}, | |
728 | {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, | |
729 | {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, | |
730 | {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, | |
731 | {0xe60, 0x00000008}, {0xe68, 0x0fc05656}, | |
732 | {0xe6c, 0x03c09696}, {0xe70, 0x03c09696}, | |
733 | {0xe74, 0x0c005656}, {0xe78, 0x0c005656}, | |
734 | {0xe7c, 0x0c005656}, {0xe80, 0x0c005656}, | |
735 | {0xe84, 0x03c09696}, {0xe88, 0x0c005656}, | |
736 | {0xe8c, 0x03c09696}, {0xed0, 0x03c09696}, | |
737 | {0xed4, 0x03c09696}, {0xed8, 0x03c09696}, | |
738 | {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6}, | |
739 | {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c}, | |
740 | {0xee8, 0x00000001}, {0xf14, 0x00000003}, | |
741 | {0xf4c, 0x00000000}, {0xf00, 0x00000300}, | |
742 | {0xffff, 0xffffffff}, | |
743 | }; | |
744 | ||
26f1fad2 JS |
745 | static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { |
746 | {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, | |
747 | {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, | |
748 | {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, | |
749 | {0xc78, 0x7a060001}, {0xc78, 0x79070001}, | |
750 | {0xc78, 0x78080001}, {0xc78, 0x77090001}, | |
751 | {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, | |
752 | {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, | |
753 | {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, | |
754 | {0xc78, 0x70100001}, {0xc78, 0x6f110001}, | |
755 | {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, | |
756 | {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, | |
757 | {0xc78, 0x6a160001}, {0xc78, 0x69170001}, | |
758 | {0xc78, 0x68180001}, {0xc78, 0x67190001}, | |
759 | {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, | |
760 | {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, | |
761 | {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, | |
762 | {0xc78, 0x60200001}, {0xc78, 0x49210001}, | |
763 | {0xc78, 0x48220001}, {0xc78, 0x47230001}, | |
764 | {0xc78, 0x46240001}, {0xc78, 0x45250001}, | |
765 | {0xc78, 0x44260001}, {0xc78, 0x43270001}, | |
766 | {0xc78, 0x42280001}, {0xc78, 0x41290001}, | |
767 | {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, | |
768 | {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, | |
769 | {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, | |
770 | {0xc78, 0x21300001}, {0xc78, 0x20310001}, | |
771 | {0xc78, 0x06320001}, {0xc78, 0x05330001}, | |
772 | {0xc78, 0x04340001}, {0xc78, 0x03350001}, | |
773 | {0xc78, 0x02360001}, {0xc78, 0x01370001}, | |
774 | {0xc78, 0x00380001}, {0xc78, 0x00390001}, | |
775 | {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, | |
776 | {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, | |
777 | {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, | |
778 | {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, | |
779 | {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, | |
780 | {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, | |
781 | {0xc78, 0x7a460001}, {0xc78, 0x79470001}, | |
782 | {0xc78, 0x78480001}, {0xc78, 0x77490001}, | |
783 | {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, | |
784 | {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, | |
785 | {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, | |
786 | {0xc78, 0x70500001}, {0xc78, 0x6f510001}, | |
787 | {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, | |
788 | {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, | |
789 | {0xc78, 0x6a560001}, {0xc78, 0x69570001}, | |
790 | {0xc78, 0x68580001}, {0xc78, 0x67590001}, | |
791 | {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, | |
792 | {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, | |
793 | {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, | |
794 | {0xc78, 0x60600001}, {0xc78, 0x49610001}, | |
795 | {0xc78, 0x48620001}, {0xc78, 0x47630001}, | |
796 | {0xc78, 0x46640001}, {0xc78, 0x45650001}, | |
797 | {0xc78, 0x44660001}, {0xc78, 0x43670001}, | |
798 | {0xc78, 0x42680001}, {0xc78, 0x41690001}, | |
799 | {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, | |
800 | {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, | |
801 | {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, | |
802 | {0xc78, 0x21700001}, {0xc78, 0x20710001}, | |
803 | {0xc78, 0x06720001}, {0xc78, 0x05730001}, | |
804 | {0xc78, 0x04740001}, {0xc78, 0x03750001}, | |
805 | {0xc78, 0x02760001}, {0xc78, 0x01770001}, | |
806 | {0xc78, 0x00780001}, {0xc78, 0x00790001}, | |
807 | {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, | |
808 | {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, | |
809 | {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, | |
810 | {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, | |
811 | {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, | |
812 | {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, | |
813 | {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, | |
814 | {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, | |
815 | {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, | |
816 | {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, | |
817 | {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, | |
818 | {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, | |
819 | {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, | |
820 | {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, | |
821 | {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, | |
822 | {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, | |
823 | {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, | |
824 | {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, | |
825 | {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, | |
826 | {0xffff, 0xffffffff} | |
827 | }; | |
828 | ||
829 | static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { | |
830 | {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, | |
831 | {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, | |
832 | {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, | |
833 | {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, | |
834 | {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, | |
835 | {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, | |
836 | {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, | |
837 | {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, | |
838 | {0xc78, 0x73100001}, {0xc78, 0x72110001}, | |
839 | {0xc78, 0x71120001}, {0xc78, 0x70130001}, | |
840 | {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, | |
841 | {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, | |
842 | {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, | |
843 | {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, | |
844 | {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, | |
845 | {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, | |
846 | {0xc78, 0x63200001}, {0xc78, 0x62210001}, | |
847 | {0xc78, 0x61220001}, {0xc78, 0x60230001}, | |
848 | {0xc78, 0x46240001}, {0xc78, 0x45250001}, | |
849 | {0xc78, 0x44260001}, {0xc78, 0x43270001}, | |
850 | {0xc78, 0x42280001}, {0xc78, 0x41290001}, | |
851 | {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, | |
852 | {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, | |
853 | {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, | |
854 | {0xc78, 0x21300001}, {0xc78, 0x20310001}, | |
855 | {0xc78, 0x06320001}, {0xc78, 0x05330001}, | |
856 | {0xc78, 0x04340001}, {0xc78, 0x03350001}, | |
857 | {0xc78, 0x02360001}, {0xc78, 0x01370001}, | |
858 | {0xc78, 0x00380001}, {0xc78, 0x00390001}, | |
859 | {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, | |
860 | {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, | |
861 | {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, | |
862 | {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, | |
863 | {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, | |
864 | {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, | |
865 | {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, | |
866 | {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, | |
867 | {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, | |
868 | {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, | |
869 | {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, | |
870 | {0xc78, 0x73500001}, {0xc78, 0x72510001}, | |
871 | {0xc78, 0x71520001}, {0xc78, 0x70530001}, | |
872 | {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, | |
873 | {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, | |
874 | {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, | |
875 | {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, | |
876 | {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, | |
877 | {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, | |
878 | {0xc78, 0x63600001}, {0xc78, 0x62610001}, | |
879 | {0xc78, 0x61620001}, {0xc78, 0x60630001}, | |
880 | {0xc78, 0x46640001}, {0xc78, 0x45650001}, | |
881 | {0xc78, 0x44660001}, {0xc78, 0x43670001}, | |
882 | {0xc78, 0x42680001}, {0xc78, 0x41690001}, | |
883 | {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, | |
884 | {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, | |
885 | {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, | |
886 | {0xc78, 0x21700001}, {0xc78, 0x20710001}, | |
887 | {0xc78, 0x06720001}, {0xc78, 0x05730001}, | |
888 | {0xc78, 0x04740001}, {0xc78, 0x03750001}, | |
889 | {0xc78, 0x02760001}, {0xc78, 0x01770001}, | |
890 | {0xc78, 0x00780001}, {0xc78, 0x00790001}, | |
891 | {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, | |
892 | {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, | |
893 | {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, | |
894 | {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, | |
895 | {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, | |
896 | {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, | |
897 | {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, | |
898 | {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, | |
899 | {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, | |
900 | {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, | |
901 | {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, | |
902 | {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, | |
903 | {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, | |
904 | {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, | |
905 | {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, | |
906 | {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, | |
907 | {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, | |
908 | {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, | |
909 | {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, | |
910 | {0xffff, 0xffffffff} | |
911 | }; | |
912 | ||
b9f498e1 JS |
913 | static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = { |
914 | {0xc78, 0xfd000001}, {0xc78, 0xfc010001}, | |
915 | {0xc78, 0xfb020001}, {0xc78, 0xfa030001}, | |
916 | {0xc78, 0xf9040001}, {0xc78, 0xf8050001}, | |
917 | {0xc78, 0xf7060001}, {0xc78, 0xf6070001}, | |
918 | {0xc78, 0xf5080001}, {0xc78, 0xf4090001}, | |
919 | {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001}, | |
920 | {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001}, | |
921 | {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001}, | |
922 | {0xc78, 0xed100001}, {0xc78, 0xec110001}, | |
923 | {0xc78, 0xeb120001}, {0xc78, 0xea130001}, | |
924 | {0xc78, 0xe9140001}, {0xc78, 0xe8150001}, | |
925 | {0xc78, 0xe7160001}, {0xc78, 0xe6170001}, | |
926 | {0xc78, 0xe5180001}, {0xc78, 0xe4190001}, | |
927 | {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001}, | |
928 | {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001}, | |
929 | {0xc78, 0x671e0001}, {0xc78, 0x661f0001}, | |
930 | {0xc78, 0x65200001}, {0xc78, 0x64210001}, | |
931 | {0xc78, 0x63220001}, {0xc78, 0x4a230001}, | |
932 | {0xc78, 0x49240001}, {0xc78, 0x48250001}, | |
933 | {0xc78, 0x47260001}, {0xc78, 0x46270001}, | |
934 | {0xc78, 0x45280001}, {0xc78, 0x44290001}, | |
935 | {0xc78, 0x432a0001}, {0xc78, 0x422b0001}, | |
936 | {0xc78, 0x292c0001}, {0xc78, 0x282d0001}, | |
937 | {0xc78, 0x272e0001}, {0xc78, 0x262f0001}, | |
938 | {0xc78, 0x0a300001}, {0xc78, 0x09310001}, | |
939 | {0xc78, 0x08320001}, {0xc78, 0x07330001}, | |
940 | {0xc78, 0x06340001}, {0xc78, 0x05350001}, | |
941 | {0xc78, 0x04360001}, {0xc78, 0x03370001}, | |
942 | {0xc78, 0x02380001}, {0xc78, 0x01390001}, | |
943 | {0xc78, 0x013a0001}, {0xc78, 0x013b0001}, | |
944 | {0xc78, 0x013c0001}, {0xc78, 0x013d0001}, | |
945 | {0xc78, 0x013e0001}, {0xc78, 0x013f0001}, | |
946 | {0xc78, 0xfc400001}, {0xc78, 0xfb410001}, | |
947 | {0xc78, 0xfa420001}, {0xc78, 0xf9430001}, | |
948 | {0xc78, 0xf8440001}, {0xc78, 0xf7450001}, | |
949 | {0xc78, 0xf6460001}, {0xc78, 0xf5470001}, | |
950 | {0xc78, 0xf4480001}, {0xc78, 0xf3490001}, | |
951 | {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001}, | |
952 | {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001}, | |
953 | {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001}, | |
954 | {0xc78, 0xec500001}, {0xc78, 0xeb510001}, | |
955 | {0xc78, 0xea520001}, {0xc78, 0xe9530001}, | |
956 | {0xc78, 0xe8540001}, {0xc78, 0xe7550001}, | |
957 | {0xc78, 0xe6560001}, {0xc78, 0xe5570001}, | |
958 | {0xc78, 0xe4580001}, {0xc78, 0xe3590001}, | |
959 | {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001}, | |
960 | {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001}, | |
961 | {0xc78, 0x675e0001}, {0xc78, 0x665f0001}, | |
962 | {0xc78, 0x65600001}, {0xc78, 0x64610001}, | |
963 | {0xc78, 0x63620001}, {0xc78, 0x62630001}, | |
964 | {0xc78, 0x61640001}, {0xc78, 0x48650001}, | |
965 | {0xc78, 0x47660001}, {0xc78, 0x46670001}, | |
966 | {0xc78, 0x45680001}, {0xc78, 0x44690001}, | |
967 | {0xc78, 0x436a0001}, {0xc78, 0x426b0001}, | |
968 | {0xc78, 0x286c0001}, {0xc78, 0x276d0001}, | |
969 | {0xc78, 0x266e0001}, {0xc78, 0x256f0001}, | |
970 | {0xc78, 0x24700001}, {0xc78, 0x09710001}, | |
971 | {0xc78, 0x08720001}, {0xc78, 0x07730001}, | |
972 | {0xc78, 0x06740001}, {0xc78, 0x05750001}, | |
973 | {0xc78, 0x04760001}, {0xc78, 0x03770001}, | |
974 | {0xc78, 0x02780001}, {0xc78, 0x01790001}, | |
975 | {0xc78, 0x017a0001}, {0xc78, 0x017b0001}, | |
976 | {0xc78, 0x017c0001}, {0xc78, 0x017d0001}, | |
977 | {0xc78, 0x017e0001}, {0xc78, 0x017f0001}, | |
978 | {0xc50, 0x69553422}, | |
979 | {0xc50, 0x69553420}, | |
980 | {0x824, 0x00390204}, | |
981 | {0xffff, 0xffffffff} | |
982 | }; | |
983 | ||
e293278d JS |
984 | static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = { |
985 | {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, | |
986 | {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, | |
987 | {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, | |
988 | {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, | |
989 | {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, | |
990 | {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, | |
991 | {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, | |
992 | {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, | |
993 | {0xc78, 0xf0100001}, {0xc78, 0xef110001}, | |
994 | {0xc78, 0xee120001}, {0xc78, 0xed130001}, | |
995 | {0xc78, 0xec140001}, {0xc78, 0xeb150001}, | |
996 | {0xc78, 0xea160001}, {0xc78, 0xe9170001}, | |
997 | {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, | |
998 | {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001}, | |
999 | {0xc78, 0xc61c0001}, {0xc78, 0x071d0001}, | |
1000 | {0xc78, 0x061e0001}, {0xc78, 0x051f0001}, | |
1001 | {0xc78, 0x04200001}, {0xc78, 0x03210001}, | |
1002 | {0xc78, 0xaa220001}, {0xc78, 0xa9230001}, | |
1003 | {0xc78, 0xa8240001}, {0xc78, 0xa7250001}, | |
1004 | {0xc78, 0xa6260001}, {0xc78, 0x85270001}, | |
1005 | {0xc78, 0x84280001}, {0xc78, 0x83290001}, | |
1006 | {0xc78, 0x252a0001}, {0xc78, 0x242b0001}, | |
1007 | {0xc78, 0x232c0001}, {0xc78, 0x222d0001}, | |
1008 | {0xc78, 0x672e0001}, {0xc78, 0x662f0001}, | |
1009 | {0xc78, 0x65300001}, {0xc78, 0x64310001}, | |
1010 | {0xc78, 0x63320001}, {0xc78, 0x62330001}, | |
1011 | {0xc78, 0x61340001}, {0xc78, 0x45350001}, | |
1012 | {0xc78, 0x44360001}, {0xc78, 0x43370001}, | |
1013 | {0xc78, 0x42380001}, {0xc78, 0x41390001}, | |
1014 | {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, | |
1015 | {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, | |
1016 | {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, | |
1017 | {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, | |
1018 | {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, | |
1019 | {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, | |
1020 | {0xc78, 0xfa460001}, {0xc78, 0xf9470001}, | |
1021 | {0xc78, 0xf8480001}, {0xc78, 0xf7490001}, | |
1022 | {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001}, | |
1023 | {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001}, | |
1024 | {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001}, | |
1025 | {0xc78, 0xf0500001}, {0xc78, 0xef510001}, | |
1026 | {0xc78, 0xee520001}, {0xc78, 0xed530001}, | |
1027 | {0xc78, 0xec540001}, {0xc78, 0xeb550001}, | |
1028 | {0xc78, 0xea560001}, {0xc78, 0xe9570001}, | |
1029 | {0xc78, 0xe8580001}, {0xc78, 0xe7590001}, | |
1030 | {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001}, | |
1031 | {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001}, | |
1032 | {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001}, | |
1033 | {0xc78, 0x8a600001}, {0xc78, 0x89610001}, | |
1034 | {0xc78, 0x88620001}, {0xc78, 0x87630001}, | |
1035 | {0xc78, 0x86640001}, {0xc78, 0x85650001}, | |
1036 | {0xc78, 0x84660001}, {0xc78, 0x83670001}, | |
1037 | {0xc78, 0x82680001}, {0xc78, 0x6b690001}, | |
1038 | {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001}, | |
1039 | {0xc78, 0x686c0001}, {0xc78, 0x676d0001}, | |
1040 | {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, | |
1041 | {0xc78, 0x64700001}, {0xc78, 0x63710001}, | |
1042 | {0xc78, 0x62720001}, {0xc78, 0x61730001}, | |
1043 | {0xc78, 0x49740001}, {0xc78, 0x48750001}, | |
1044 | {0xc78, 0x47760001}, {0xc78, 0x46770001}, | |
1045 | {0xc78, 0x45780001}, {0xc78, 0x44790001}, | |
1046 | {0xc78, 0x437a0001}, {0xc78, 0x427b0001}, | |
1047 | {0xc78, 0x417c0001}, {0xc78, 0x407d0001}, | |
1048 | {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, | |
1049 | {0xc50, 0x00040022}, {0xc50, 0x00040020}, | |
1050 | {0xffff, 0xffffffff} | |
1051 | }; | |
1052 | ||
1053 | static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = { | |
1054 | {0xc78, 0xfa000001}, {0xc78, 0xf9010001}, | |
1055 | {0xc78, 0xf8020001}, {0xc78, 0xf7030001}, | |
1056 | {0xc78, 0xf6040001}, {0xc78, 0xf5050001}, | |
1057 | {0xc78, 0xf4060001}, {0xc78, 0xf3070001}, | |
1058 | {0xc78, 0xf2080001}, {0xc78, 0xf1090001}, | |
1059 | {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001}, | |
1060 | {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001}, | |
1061 | {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001}, | |
1062 | {0xc78, 0xea100001}, {0xc78, 0xe9110001}, | |
1063 | {0xc78, 0xe8120001}, {0xc78, 0xe7130001}, | |
1064 | {0xc78, 0xe6140001}, {0xc78, 0xe5150001}, | |
1065 | {0xc78, 0xe4160001}, {0xc78, 0xe3170001}, | |
1066 | {0xc78, 0xe2180001}, {0xc78, 0xe1190001}, | |
1067 | {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001}, | |
1068 | {0xc78, 0x881c0001}, {0xc78, 0x871d0001}, | |
1069 | {0xc78, 0x861e0001}, {0xc78, 0x851f0001}, | |
1070 | {0xc78, 0x84200001}, {0xc78, 0x83210001}, | |
1071 | {0xc78, 0x82220001}, {0xc78, 0x6a230001}, | |
1072 | {0xc78, 0x69240001}, {0xc78, 0x68250001}, | |
1073 | {0xc78, 0x67260001}, {0xc78, 0x66270001}, | |
1074 | {0xc78, 0x65280001}, {0xc78, 0x64290001}, | |
1075 | {0xc78, 0x632a0001}, {0xc78, 0x622b0001}, | |
1076 | {0xc78, 0x612c0001}, {0xc78, 0x602d0001}, | |
1077 | {0xc78, 0x472e0001}, {0xc78, 0x462f0001}, | |
1078 | {0xc78, 0x45300001}, {0xc78, 0x44310001}, | |
1079 | {0xc78, 0x43320001}, {0xc78, 0x42330001}, | |
1080 | {0xc78, 0x41340001}, {0xc78, 0x40350001}, | |
1081 | {0xc78, 0x40360001}, {0xc78, 0x40370001}, | |
1082 | {0xc78, 0x40380001}, {0xc78, 0x40390001}, | |
1083 | {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, | |
1084 | {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, | |
1085 | {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, | |
1086 | {0xc78, 0xfa400001}, {0xc78, 0xf9410001}, | |
1087 | {0xc78, 0xf8420001}, {0xc78, 0xf7430001}, | |
1088 | {0xc78, 0xf6440001}, {0xc78, 0xf5450001}, | |
1089 | {0xc78, 0xf4460001}, {0xc78, 0xf3470001}, | |
1090 | {0xc78, 0xf2480001}, {0xc78, 0xf1490001}, | |
1091 | {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001}, | |
1092 | {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001}, | |
1093 | {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001}, | |
1094 | {0xc78, 0xea500001}, {0xc78, 0xe9510001}, | |
1095 | {0xc78, 0xe8520001}, {0xc78, 0xe7530001}, | |
1096 | {0xc78, 0xe6540001}, {0xc78, 0xe5550001}, | |
1097 | {0xc78, 0xe4560001}, {0xc78, 0xe3570001}, | |
1098 | {0xc78, 0xe2580001}, {0xc78, 0xe1590001}, | |
1099 | {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001}, | |
1100 | {0xc78, 0x885c0001}, {0xc78, 0x875d0001}, | |
1101 | {0xc78, 0x865e0001}, {0xc78, 0x855f0001}, | |
1102 | {0xc78, 0x84600001}, {0xc78, 0x83610001}, | |
1103 | {0xc78, 0x82620001}, {0xc78, 0x6a630001}, | |
1104 | {0xc78, 0x69640001}, {0xc78, 0x68650001}, | |
1105 | {0xc78, 0x67660001}, {0xc78, 0x66670001}, | |
1106 | {0xc78, 0x65680001}, {0xc78, 0x64690001}, | |
1107 | {0xc78, 0x636a0001}, {0xc78, 0x626b0001}, | |
1108 | {0xc78, 0x616c0001}, {0xc78, 0x606d0001}, | |
1109 | {0xc78, 0x476e0001}, {0xc78, 0x466f0001}, | |
1110 | {0xc78, 0x45700001}, {0xc78, 0x44710001}, | |
1111 | {0xc78, 0x43720001}, {0xc78, 0x42730001}, | |
1112 | {0xc78, 0x41740001}, {0xc78, 0x40750001}, | |
1113 | {0xc78, 0x40760001}, {0xc78, 0x40770001}, | |
1114 | {0xc78, 0x40780001}, {0xc78, 0x40790001}, | |
1115 | {0xc78, 0x407a0001}, {0xc78, 0x407b0001}, | |
1116 | {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, | |
1117 | {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, | |
1118 | {0xc50, 0x00040222}, {0xc50, 0x00040220}, | |
1119 | {0xffff, 0xffffffff} | |
1120 | }; | |
1121 | ||
26f1fad2 JS |
1122 | static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { |
1123 | {0x00, 0x00030159}, {0x01, 0x00031284}, | |
1124 | {0x02, 0x00098000}, {0x03, 0x00039c63}, | |
1125 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, | |
1126 | {0x0a, 0x0001a3f1}, {0x0b, 0x00014787}, | |
1127 | {0x0c, 0x000896fe}, {0x0d, 0x0000e02c}, | |
1128 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, | |
1129 | {0x19, 0x00000000}, {0x1a, 0x00030355}, | |
1130 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, | |
1131 | {0x1d, 0x000a1250}, {0x1e, 0x0000024f}, | |
1132 | {0x1f, 0x00000000}, {0x20, 0x0000b614}, | |
1133 | {0x21, 0x0006c000}, {0x22, 0x00000000}, | |
1134 | {0x23, 0x00001558}, {0x24, 0x00000060}, | |
1135 | {0x25, 0x00000483}, {0x26, 0x0004f000}, | |
1136 | {0x27, 0x000ec7d9}, {0x28, 0x00057730}, | |
1137 | {0x29, 0x00004783}, {0x2a, 0x00000001}, | |
1138 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, | |
1139 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, | |
1140 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, | |
1141 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, | |
1142 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, | |
1143 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, | |
1144 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, | |
1145 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, | |
1146 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, | |
1147 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, | |
1148 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, | |
1149 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, | |
1150 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, | |
1151 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, | |
1152 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, | |
1153 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, | |
1154 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, | |
1155 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, | |
1156 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, | |
1157 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, | |
1158 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, | |
1159 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, | |
1160 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, | |
1161 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, | |
1162 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, | |
1163 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, | |
1164 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, | |
1165 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, | |
1166 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, | |
1167 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, | |
1168 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, | |
1169 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, | |
1170 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, | |
1171 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, | |
1172 | {0x10, 0x00000000}, {0x11, 0x00000000}, | |
1173 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, | |
1174 | {0x10, 0x0009000f}, {0x11, 0x00023100}, | |
1175 | {0x12, 0x00032000}, {0x12, 0x00071000}, | |
1176 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, | |
1177 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, | |
1178 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, | |
1179 | {0x13, 0x00018493}, {0x13, 0x0001429b}, | |
1180 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, | |
1181 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, | |
1182 | {0x13, 0x00000020}, {0x14, 0x0001944c}, | |
1183 | {0x14, 0x00059444}, {0x14, 0x0009944c}, | |
1184 | {0x14, 0x000d9444}, {0x15, 0x0000f474}, | |
1185 | {0x15, 0x0004f477}, {0x15, 0x0008f455}, | |
1186 | {0x15, 0x000cf455}, {0x16, 0x00000339}, | |
1187 | {0x16, 0x00040339}, {0x16, 0x00080339}, | |
1188 | {0x16, 0x000c0366}, {0x00, 0x00010159}, | |
1189 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, | |
1190 | {0xfe, 0x00000000}, {0x1f, 0x00000003}, | |
1191 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1192 | {0x1e, 0x00000247}, {0x1f, 0x00000000}, | |
1193 | {0x00, 0x00030159}, | |
1194 | {0xff, 0xffffffff} | |
1195 | }; | |
1196 | ||
22a31d45 JS |
1197 | static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = { |
1198 | {0x00, 0x00010000}, {0xb0, 0x000dffe0}, | |
1199 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1200 | {0xfe, 0x00000000}, {0xb1, 0x00000018}, | |
1201 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1202 | {0xfe, 0x00000000}, {0xb2, 0x00084c00}, | |
1203 | {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa}, | |
1204 | {0xb7, 0x00000010}, {0xb8, 0x0000907f}, | |
1205 | {0x5c, 0x00000002}, {0x7c, 0x00000002}, | |
1206 | {0x7e, 0x00000005}, {0x8b, 0x0006fc00}, | |
1207 | {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2}, | |
1208 | {0x1e, 0x00000000}, {0xdf, 0x00000780}, | |
1209 | {0x50, 0x00067435}, | |
1210 | /* | |
1211 | * The 8723bu vendor driver indicates that bit 8 should be set in | |
1212 | * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However | |
1213 | * they never actually check the package type - and just default | |
1214 | * to not setting it. | |
1215 | */ | |
1216 | {0x51, 0x0006b04e}, | |
1217 | {0x52, 0x000007d2}, {0x53, 0x00000000}, | |
1218 | {0x54, 0x00050400}, {0x55, 0x0004026e}, | |
1219 | {0xdd, 0x0000004c}, {0x70, 0x00067435}, | |
1220 | /* | |
1221 | * 0x71 has same package type condition as for register 0x51 | |
1222 | */ | |
1223 | {0x71, 0x0006b04e}, | |
1224 | {0x72, 0x000007d2}, {0x73, 0x00000000}, | |
1225 | {0x74, 0x00050400}, {0x75, 0x0004026e}, | |
1226 | {0xef, 0x00000100}, {0x34, 0x0000add7}, | |
1227 | {0x35, 0x00005c00}, {0x34, 0x00009dd4}, | |
1228 | {0x35, 0x00005000}, {0x34, 0x00008dd1}, | |
1229 | {0x35, 0x00004400}, {0x34, 0x00007dce}, | |
1230 | {0x35, 0x00003800}, {0x34, 0x00006cd1}, | |
1231 | {0x35, 0x00004400}, {0x34, 0x00005cce}, | |
1232 | {0x35, 0x00003800}, {0x34, 0x000048ce}, | |
1233 | {0x35, 0x00004400}, {0x34, 0x000034ce}, | |
1234 | {0x35, 0x00003800}, {0x34, 0x00002451}, | |
1235 | {0x35, 0x00004400}, {0x34, 0x0000144e}, | |
1236 | {0x35, 0x00003800}, {0x34, 0x00000051}, | |
1237 | {0x35, 0x00004400}, {0xef, 0x00000000}, | |
1238 | {0xef, 0x00000100}, {0xed, 0x00000010}, | |
1239 | {0x44, 0x0000add7}, {0x44, 0x00009dd4}, | |
1240 | {0x44, 0x00008dd1}, {0x44, 0x00007dce}, | |
1241 | {0x44, 0x00006cc1}, {0x44, 0x00005cce}, | |
1242 | {0x44, 0x000044d1}, {0x44, 0x000034ce}, | |
1243 | {0x44, 0x00002451}, {0x44, 0x0000144e}, | |
1244 | {0x44, 0x00000051}, {0xef, 0x00000000}, | |
1245 | {0xed, 0x00000000}, {0x7f, 0x00020080}, | |
1246 | {0xef, 0x00002000}, {0x3b, 0x000380ef}, | |
1247 | {0x3b, 0x000302fe}, {0x3b, 0x00028ce6}, | |
1248 | {0x3b, 0x000200bc}, {0x3b, 0x000188a5}, | |
1249 | {0x3b, 0x00010fbc}, {0x3b, 0x00008f71}, | |
1250 | {0x3b, 0x00000900}, {0xef, 0x00000000}, | |
1251 | {0xed, 0x00000001}, {0x40, 0x000380ef}, | |
1252 | {0x40, 0x000302fe}, {0x40, 0x00028ce6}, | |
1253 | {0x40, 0x000200bc}, {0x40, 0x000188a5}, | |
1254 | {0x40, 0x00010fbc}, {0x40, 0x00008f71}, | |
1255 | {0x40, 0x00000900}, {0xed, 0x00000000}, | |
1256 | {0x82, 0x00080000}, {0x83, 0x00008000}, | |
1257 | {0x84, 0x00048d80}, {0x85, 0x00068000}, | |
1258 | {0xa2, 0x00080000}, {0xa3, 0x00008000}, | |
1259 | {0xa4, 0x00048d80}, {0xa5, 0x00068000}, | |
1260 | {0xed, 0x00000002}, {0xef, 0x00000002}, | |
1261 | {0x56, 0x00000032}, {0x76, 0x00000032}, | |
1262 | {0x01, 0x00000780}, | |
1263 | {0xff, 0xffffffff} | |
1264 | }; | |
1265 | ||
26f1fad2 JS |
1266 | static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { |
1267 | {0x00, 0x00030159}, {0x01, 0x00031284}, | |
1268 | {0x02, 0x00098000}, {0x03, 0x00018c63}, | |
1269 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, | |
1270 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, | |
1271 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, | |
1272 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, | |
1273 | {0x19, 0x00000000}, {0x1a, 0x00010255}, | |
1274 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, | |
1275 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, | |
1276 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, | |
1277 | {0x21, 0x0006c000}, {0x22, 0x00000000}, | |
1278 | {0x23, 0x00001558}, {0x24, 0x00000060}, | |
1279 | {0x25, 0x00000483}, {0x26, 0x0004f000}, | |
1280 | {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, | |
1281 | {0x29, 0x00004783}, {0x2a, 0x00000001}, | |
1282 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, | |
1283 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, | |
1284 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, | |
1285 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, | |
1286 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, | |
1287 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, | |
1288 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, | |
1289 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, | |
1290 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, | |
1291 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, | |
1292 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, | |
1293 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, | |
1294 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, | |
1295 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, | |
1296 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, | |
1297 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, | |
1298 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, | |
1299 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, | |
1300 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, | |
1301 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, | |
1302 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, | |
1303 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, | |
1304 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, | |
1305 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, | |
1306 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, | |
1307 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, | |
1308 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, | |
1309 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, | |
1310 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, | |
1311 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, | |
1312 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, | |
1313 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, | |
1314 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, | |
1315 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, | |
1316 | {0x10, 0x00000000}, {0x11, 0x00000000}, | |
1317 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, | |
1318 | {0x10, 0x0009000f}, {0x11, 0x00023100}, | |
1319 | {0x12, 0x00032000}, {0x12, 0x00071000}, | |
1320 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, | |
1321 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, | |
1322 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, | |
1323 | {0x13, 0x00018493}, {0x13, 0x0001429b}, | |
1324 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, | |
1325 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, | |
1326 | {0x13, 0x00000020}, {0x14, 0x0001944c}, | |
1327 | {0x14, 0x00059444}, {0x14, 0x0009944c}, | |
1328 | {0x14, 0x000d9444}, {0x15, 0x0000f424}, | |
1329 | {0x15, 0x0004f424}, {0x15, 0x0008f424}, | |
1330 | {0x15, 0x000cf424}, {0x16, 0x000e0330}, | |
1331 | {0x16, 0x000a0330}, {0x16, 0x00060330}, | |
1332 | {0x16, 0x00020330}, {0x00, 0x00010159}, | |
1333 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, | |
1334 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, | |
1335 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1336 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, | |
1337 | {0x00, 0x00030159}, | |
1338 | {0xff, 0xffffffff} | |
1339 | }; | |
1340 | ||
1341 | static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = { | |
1342 | {0x00, 0x00030159}, {0x01, 0x00031284}, | |
1343 | {0x02, 0x00098000}, {0x03, 0x00018c63}, | |
1344 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, | |
1345 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, | |
1346 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, | |
1347 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, | |
1348 | {0x12, 0x00032000}, {0x12, 0x00071000}, | |
1349 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, | |
1350 | {0x13, 0x000287af}, {0x13, 0x000244b7}, | |
1351 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, | |
1352 | {0x13, 0x00018493}, {0x13, 0x00014297}, | |
1353 | {0x13, 0x00010295}, {0x13, 0x0000c298}, | |
1354 | {0x13, 0x0000819c}, {0x13, 0x000040a8}, | |
1355 | {0x13, 0x0000001c}, {0x14, 0x0001944c}, | |
1356 | {0x14, 0x00059444}, {0x14, 0x0009944c}, | |
1357 | {0x14, 0x000d9444}, {0x15, 0x0000f424}, | |
1358 | {0x15, 0x0004f424}, {0x15, 0x0008f424}, | |
1359 | {0x15, 0x000cf424}, {0x16, 0x000e0330}, | |
1360 | {0x16, 0x000a0330}, {0x16, 0x00060330}, | |
1361 | {0x16, 0x00020330}, | |
1362 | {0xff, 0xffffffff} | |
1363 | }; | |
1364 | ||
1365 | static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = { | |
1366 | {0x00, 0x00030159}, {0x01, 0x00031284}, | |
1367 | {0x02, 0x00098000}, {0x03, 0x00018c63}, | |
1368 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, | |
1369 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, | |
1370 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, | |
1371 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, | |
1372 | {0x19, 0x00000000}, {0x1a, 0x00010255}, | |
1373 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, | |
1374 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, | |
1375 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, | |
1376 | {0x21, 0x0006c000}, {0x22, 0x00000000}, | |
1377 | {0x23, 0x00001558}, {0x24, 0x00000060}, | |
1378 | {0x25, 0x00000483}, {0x26, 0x0004f000}, | |
1379 | {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, | |
1380 | {0x29, 0x00004783}, {0x2a, 0x00000001}, | |
1381 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, | |
1382 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, | |
1383 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, | |
1384 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, | |
1385 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, | |
1386 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, | |
1387 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, | |
1388 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, | |
1389 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, | |
1390 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, | |
1391 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, | |
1392 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, | |
1393 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, | |
1394 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, | |
1395 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, | |
1396 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, | |
1397 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, | |
1398 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, | |
1399 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, | |
1400 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, | |
1401 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, | |
1402 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, | |
1403 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, | |
1404 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, | |
1405 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, | |
1406 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, | |
1407 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, | |
1408 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, | |
1409 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, | |
1410 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, | |
1411 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, | |
1412 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, | |
1413 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, | |
1414 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, | |
1415 | {0x10, 0x00000000}, {0x11, 0x00000000}, | |
1416 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, | |
1417 | {0x10, 0x0009000f}, {0x11, 0x00023100}, | |
1418 | {0x12, 0x00032000}, {0x12, 0x00071000}, | |
1419 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, | |
1420 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, | |
1421 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, | |
1422 | {0x13, 0x00018493}, {0x13, 0x0001429b}, | |
1423 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, | |
1424 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, | |
1425 | {0x13, 0x00000020}, {0x14, 0x0001944c}, | |
1426 | {0x14, 0x00059444}, {0x14, 0x0009944c}, | |
1427 | {0x14, 0x000d9444}, {0x15, 0x0000f405}, | |
1428 | {0x15, 0x0004f405}, {0x15, 0x0008f405}, | |
1429 | {0x15, 0x000cf405}, {0x16, 0x000e0330}, | |
1430 | {0x16, 0x000a0330}, {0x16, 0x00060330}, | |
1431 | {0x16, 0x00020330}, {0x00, 0x00010159}, | |
1432 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, | |
1433 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, | |
1434 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1435 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, | |
1436 | {0x00, 0x00030159}, | |
1437 | {0xff, 0xffffffff} | |
1438 | }; | |
1439 | ||
1440 | static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = { | |
1441 | {0x00, 0x00030159}, {0x01, 0x00031284}, | |
1442 | {0x02, 0x00098000}, {0x03, 0x00018c63}, | |
1443 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, | |
1444 | {0x0a, 0x0001adb0}, {0x0b, 0x00054867}, | |
1445 | {0x0c, 0x0008992e}, {0x0d, 0x0000e529}, | |
1446 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, | |
1447 | {0x19, 0x00000000}, {0x1a, 0x00000255}, | |
1448 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, | |
1449 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, | |
1450 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, | |
1451 | {0x21, 0x0006c000}, {0x22, 0x0000083c}, | |
1452 | {0x23, 0x00001558}, {0x24, 0x00000060}, | |
1453 | {0x25, 0x00000483}, {0x26, 0x0004f000}, | |
1454 | {0x27, 0x000ec7d9}, {0x28, 0x000977c0}, | |
1455 | {0x29, 0x00004783}, {0x2a, 0x00000001}, | |
1456 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, | |
1457 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, | |
1458 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, | |
1459 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, | |
1460 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, | |
1461 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, | |
1462 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, | |
1463 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, | |
1464 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, | |
1465 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, | |
1466 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, | |
1467 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, | |
1468 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, | |
1469 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, | |
1470 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, | |
1471 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, | |
1472 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, | |
1473 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, | |
1474 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, | |
1475 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, | |
1476 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, | |
1477 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, | |
1478 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, | |
1479 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, | |
1480 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, | |
1481 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, | |
1482 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, | |
1483 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, | |
1484 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, | |
1485 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, | |
1486 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, | |
1487 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, | |
1488 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, | |
1489 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, | |
1490 | {0x10, 0x00000000}, {0x11, 0x00000000}, | |
1491 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, | |
1492 | {0x10, 0x0009000f}, {0x11, 0x00023100}, | |
1493 | {0x12, 0x000d8000}, {0x12, 0x00090000}, | |
1494 | {0x12, 0x00051000}, {0x12, 0x00012000}, | |
1495 | {0x13, 0x00028fb4}, {0x13, 0x00024fa8}, | |
1496 | {0x13, 0x000207a4}, {0x13, 0x0001c3b0}, | |
1497 | {0x13, 0x000183a4}, {0x13, 0x00014398}, | |
1498 | {0x13, 0x000101a4}, {0x13, 0x0000c198}, | |
1499 | {0x13, 0x000080a4}, {0x13, 0x00004098}, | |
1500 | {0x13, 0x00000000}, {0x14, 0x0001944c}, | |
1501 | {0x14, 0x00059444}, {0x14, 0x0009944c}, | |
1502 | {0x14, 0x000d9444}, {0x15, 0x0000f405}, | |
1503 | {0x15, 0x0004f405}, {0x15, 0x0008f405}, | |
1504 | {0x15, 0x000cf405}, {0x16, 0x000e0330}, | |
1505 | {0x16, 0x000a0330}, {0x16, 0x00060330}, | |
1506 | {0x16, 0x00020330}, {0x00, 0x00010159}, | |
1507 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, | |
1508 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, | |
1509 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1510 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, | |
1511 | {0x00, 0x00030159}, | |
1512 | {0xff, 0xffffffff} | |
1513 | }; | |
1514 | ||
19102f84 JS |
1515 | static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = { |
1516 | {0x7f, 0x00000082}, {0x81, 0x0003fc00}, | |
1517 | {0x00, 0x00030000}, {0x08, 0x00008400}, | |
1518 | {0x18, 0x00000407}, {0x19, 0x00000012}, | |
1519 | {0x1b, 0x00000064}, {0x1e, 0x00080009}, | |
1520 | {0x1f, 0x00000880}, {0x2f, 0x0001a060}, | |
1521 | {0x3f, 0x00000000}, {0x42, 0x000060c0}, | |
1522 | {0x57, 0x000d0000}, {0x58, 0x000be180}, | |
1523 | {0x67, 0x00001552}, {0x83, 0x00000000}, | |
1524 | {0xb0, 0x000ff9f1}, {0xb1, 0x00055418}, | |
1525 | {0xb2, 0x0008cc00}, {0xb4, 0x00043083}, | |
1526 | {0xb5, 0x00008166}, {0xb6, 0x0000803e}, | |
1527 | {0xb7, 0x0001c69f}, {0xb8, 0x0000407f}, | |
1528 | {0xb9, 0x00080001}, {0xba, 0x00040001}, | |
1529 | {0xbb, 0x00000400}, {0xbf, 0x000c0000}, | |
1530 | {0xc2, 0x00002400}, {0xc3, 0x00000009}, | |
1531 | {0xc4, 0x00040c91}, {0xc5, 0x00099999}, | |
1532 | {0xc6, 0x000000a3}, {0xc7, 0x00088820}, | |
1533 | {0xc8, 0x00076c06}, {0xc9, 0x00000000}, | |
1534 | {0xca, 0x00080000}, {0xdf, 0x00000180}, | |
1535 | {0xef, 0x000001a0}, {0x51, 0x00069545}, | |
1536 | {0x52, 0x0007e45e}, {0x53, 0x00000071}, | |
1537 | {0x56, 0x00051ff3}, {0x35, 0x000000a8}, | |
1538 | {0x35, 0x000001e2}, {0x35, 0x000002a8}, | |
1539 | {0x36, 0x00001c24}, {0x36, 0x00009c24}, | |
1540 | {0x36, 0x00011c24}, {0x36, 0x00019c24}, | |
1541 | {0x18, 0x00000c07}, {0x5a, 0x00048000}, | |
1542 | {0x19, 0x000739d0}, | |
1543 | #ifdef EXT_PA_8192EU | |
1544 | /* External PA or external LNA */ | |
1545 | {0x34, 0x0000a093}, {0x34, 0x0000908f}, | |
1546 | {0x34, 0x0000808c}, {0x34, 0x0000704d}, | |
1547 | {0x34, 0x0000604a}, {0x34, 0x00005047}, | |
1548 | {0x34, 0x0000400a}, {0x34, 0x00003007}, | |
1549 | {0x34, 0x00002004}, {0x34, 0x00001001}, | |
1550 | {0x34, 0x00000000}, | |
1551 | #else | |
1552 | /* Regular */ | |
1553 | {0x34, 0x0000add7}, {0x34, 0x00009dd4}, | |
1554 | {0x34, 0x00008dd1}, {0x34, 0x00007dce}, | |
1555 | {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, | |
1556 | {0x34, 0x00004dc5}, {0x34, 0x000034cc}, | |
1557 | {0x34, 0x0000244f}, {0x34, 0x0000144c}, | |
1558 | {0x34, 0x00000014}, | |
1559 | #endif | |
1560 | {0x00, 0x00030159}, | |
1561 | {0x84, 0x00068180}, | |
1562 | {0x86, 0x0000014e}, | |
1563 | {0x87, 0x00048e00}, | |
1564 | {0x8e, 0x00065540}, | |
1565 | {0x8f, 0x00088000}, | |
1566 | {0xef, 0x000020a0}, | |
1567 | #ifdef EXT_PA_8192EU | |
1568 | /* External PA or external LNA */ | |
1569 | {0x3b, 0x000f07b0}, | |
1570 | #else | |
1571 | {0x3b, 0x000f02b0}, | |
1572 | #endif | |
1573 | {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, | |
1574 | {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, | |
1575 | {0x3b, 0x000a0080}, {0x3b, 0x00090080}, | |
1576 | {0x3b, 0x0008f780}, | |
1577 | #ifdef EXT_PA_8192EU | |
1578 | /* External PA or external LNA */ | |
1579 | {0x3b, 0x000787b0}, | |
1580 | #else | |
1581 | {0x3b, 0x00078730}, | |
1582 | #endif | |
1583 | {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, | |
1584 | {0x3b, 0x00040620}, {0x3b, 0x00037090}, | |
1585 | {0x3b, 0x00020080}, {0x3b, 0x0001f060}, | |
1586 | {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, | |
1587 | {0xfe, 0x00000000}, {0x18, 0x0000fc07}, | |
1588 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1589 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1590 | {0x1e, 0x00000001}, {0x1f, 0x00080000}, | |
1591 | {0x00, 0x00033e70}, | |
1592 | {0xff, 0xffffffff} | |
1593 | }; | |
1594 | ||
1595 | static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = { | |
1596 | {0x7f, 0x00000082}, {0x81, 0x0003fc00}, | |
1597 | {0x00, 0x00030000}, {0x08, 0x00008400}, | |
1598 | {0x18, 0x00000407}, {0x19, 0x00000012}, | |
1599 | {0x1b, 0x00000064}, {0x1e, 0x00080009}, | |
1600 | {0x1f, 0x00000880}, {0x2f, 0x0001a060}, | |
1601 | {0x3f, 0x00000000}, {0x42, 0x000060c0}, | |
1602 | {0x57, 0x000d0000}, {0x58, 0x000be180}, | |
1603 | {0x67, 0x00001552}, {0x7f, 0x00000082}, | |
1604 | {0x81, 0x0003f000}, {0x83, 0x00000000}, | |
1605 | {0xdf, 0x00000180}, {0xef, 0x000001a0}, | |
1606 | {0x51, 0x00069545}, {0x52, 0x0007e42e}, | |
1607 | {0x53, 0x00000071}, {0x56, 0x00051ff3}, | |
1608 | {0x35, 0x000000a8}, {0x35, 0x000001e0}, | |
1609 | {0x35, 0x000002a8}, {0x36, 0x00001ca8}, | |
1610 | {0x36, 0x00009c24}, {0x36, 0x00011c24}, | |
1611 | {0x36, 0x00019c24}, {0x18, 0x00000c07}, | |
1612 | {0x5a, 0x00048000}, {0x19, 0x000739d0}, | |
1613 | #ifdef EXT_PA_8192EU | |
1614 | /* External PA or external LNA */ | |
1615 | {0x34, 0x0000a093}, {0x34, 0x0000908f}, | |
1616 | {0x34, 0x0000808c}, {0x34, 0x0000704d}, | |
1617 | {0x34, 0x0000604a}, {0x34, 0x00005047}, | |
1618 | {0x34, 0x0000400a}, {0x34, 0x00003007}, | |
1619 | {0x34, 0x00002004}, {0x34, 0x00001001}, | |
1620 | {0x34, 0x00000000}, | |
1621 | #else | |
1622 | {0x34, 0x0000add7}, {0x34, 0x00009dd4}, | |
1623 | {0x34, 0x00008dd1}, {0x34, 0x00007dce}, | |
1624 | {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, | |
1625 | {0x34, 0x00004dc5}, {0x34, 0x000034cc}, | |
1626 | {0x34, 0x0000244f}, {0x34, 0x0000144c}, | |
1627 | {0x34, 0x00000014}, | |
1628 | #endif | |
1629 | {0x00, 0x00030159}, {0x84, 0x00068180}, | |
1630 | {0x86, 0x000000ce}, {0x87, 0x00048a00}, | |
1631 | {0x8e, 0x00065540}, {0x8f, 0x00088000}, | |
1632 | {0xef, 0x000020a0}, | |
1633 | #ifdef EXT_PA_8192EU | |
1634 | /* External PA or external LNA */ | |
1635 | {0x3b, 0x000f07b0}, | |
1636 | #else | |
1637 | {0x3b, 0x000f02b0}, | |
1638 | #endif | |
1639 | ||
1640 | {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, | |
1641 | {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, | |
1642 | {0x3b, 0x000a0080}, {0x3b, 0x00090080}, | |
1643 | {0x3b, 0x0008f780}, | |
1644 | #ifdef EXT_PA_8192EU | |
1645 | /* External PA or external LNA */ | |
1646 | {0x3b, 0x000787b0}, | |
1647 | #else | |
1648 | {0x3b, 0x00078730}, | |
1649 | #endif | |
1650 | {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, | |
1651 | {0x3b, 0x00040620}, {0x3b, 0x00037090}, | |
1652 | {0x3b, 0x00020080}, {0x3b, 0x0001f060}, | |
1653 | {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, | |
1654 | {0x00, 0x00010159}, {0xfe, 0x00000000}, | |
1655 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, | |
1656 | {0xfe, 0x00000000}, {0x1e, 0x00000001}, | |
1657 | {0x1f, 0x00080000}, {0x00, 0x00033e70}, | |
1658 | {0xff, 0xffffffff} | |
1659 | }; | |
1660 | ||
26f1fad2 JS |
1661 | static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { |
1662 | { /* RF_A */ | |
1663 | .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, | |
1664 | .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, | |
1665 | .lssiparm = REG_FPGA0_XA_LSSI_PARM, | |
1666 | .hspiread = REG_HSPI_XA_READBACK, | |
1667 | .lssiread = REG_FPGA0_XA_LSSI_READBACK, | |
1668 | .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, | |
1669 | }, | |
1670 | { /* RF_B */ | |
1671 | .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, | |
1672 | .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, | |
1673 | .lssiparm = REG_FPGA0_XB_LSSI_PARM, | |
1674 | .hspiread = REG_HSPI_XB_READBACK, | |
1675 | .lssiread = REG_FPGA0_XB_LSSI_READBACK, | |
1676 | .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, | |
1677 | }, | |
1678 | }; | |
1679 | ||
1680 | static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { | |
1681 | REG_OFDM0_XA_RX_IQ_IMBALANCE, | |
1682 | REG_OFDM0_XB_RX_IQ_IMBALANCE, | |
1683 | REG_OFDM0_ENERGY_CCA_THRES, | |
1684 | REG_OFDM0_AGCR_SSI_TABLE, | |
1685 | REG_OFDM0_XA_TX_IQ_IMBALANCE, | |
1686 | REG_OFDM0_XB_TX_IQ_IMBALANCE, | |
1687 | REG_OFDM0_XC_TX_AFE, | |
1688 | REG_OFDM0_XD_TX_AFE, | |
1689 | REG_OFDM0_RX_IQ_EXT_ANTA | |
1690 | }; | |
1691 | ||
1692 | static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) | |
1693 | { | |
1694 | struct usb_device *udev = priv->udev; | |
1695 | int len; | |
1696 | u8 data; | |
1697 | ||
1698 | mutex_lock(&priv->usb_buf_mutex); | |
1699 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
1700 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, | |
1701 | addr, 0, &priv->usb_buf.val8, sizeof(u8), | |
1702 | RTW_USB_CONTROL_MSG_TIMEOUT); | |
1703 | data = priv->usb_buf.val8; | |
1704 | mutex_unlock(&priv->usb_buf_mutex); | |
1705 | ||
1706 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) | |
1707 | dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", | |
1708 | __func__, addr, data, len); | |
1709 | return data; | |
1710 | } | |
1711 | ||
1712 | static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) | |
1713 | { | |
1714 | struct usb_device *udev = priv->udev; | |
1715 | int len; | |
1716 | u16 data; | |
1717 | ||
1718 | mutex_lock(&priv->usb_buf_mutex); | |
1719 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
1720 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, | |
1721 | addr, 0, &priv->usb_buf.val16, sizeof(u16), | |
1722 | RTW_USB_CONTROL_MSG_TIMEOUT); | |
1723 | data = le16_to_cpu(priv->usb_buf.val16); | |
1724 | mutex_unlock(&priv->usb_buf_mutex); | |
1725 | ||
1726 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) | |
1727 | dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", | |
1728 | __func__, addr, data, len); | |
1729 | return data; | |
1730 | } | |
1731 | ||
1732 | static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) | |
1733 | { | |
1734 | struct usb_device *udev = priv->udev; | |
1735 | int len; | |
1736 | u32 data; | |
1737 | ||
1738 | mutex_lock(&priv->usb_buf_mutex); | |
1739 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
1740 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, | |
1741 | addr, 0, &priv->usb_buf.val32, sizeof(u32), | |
1742 | RTW_USB_CONTROL_MSG_TIMEOUT); | |
1743 | data = le32_to_cpu(priv->usb_buf.val32); | |
1744 | mutex_unlock(&priv->usb_buf_mutex); | |
1745 | ||
1746 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) | |
1747 | dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", | |
1748 | __func__, addr, data, len); | |
1749 | return data; | |
1750 | } | |
1751 | ||
1752 | static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) | |
1753 | { | |
1754 | struct usb_device *udev = priv->udev; | |
1755 | int ret; | |
1756 | ||
1757 | mutex_lock(&priv->usb_buf_mutex); | |
1758 | priv->usb_buf.val8 = val; | |
1759 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), | |
1760 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, | |
1761 | addr, 0, &priv->usb_buf.val8, sizeof(u8), | |
1762 | RTW_USB_CONTROL_MSG_TIMEOUT); | |
1763 | ||
1764 | mutex_unlock(&priv->usb_buf_mutex); | |
1765 | ||
1766 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) | |
1767 | dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", | |
1768 | __func__, addr, val); | |
1769 | return ret; | |
1770 | } | |
1771 | ||
1772 | static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) | |
1773 | { | |
1774 | struct usb_device *udev = priv->udev; | |
1775 | int ret; | |
1776 | ||
1777 | mutex_lock(&priv->usb_buf_mutex); | |
1778 | priv->usb_buf.val16 = cpu_to_le16(val); | |
1779 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), | |
1780 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, | |
1781 | addr, 0, &priv->usb_buf.val16, sizeof(u16), | |
1782 | RTW_USB_CONTROL_MSG_TIMEOUT); | |
1783 | mutex_unlock(&priv->usb_buf_mutex); | |
1784 | ||
1785 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) | |
1786 | dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", | |
1787 | __func__, addr, val); | |
1788 | return ret; | |
1789 | } | |
1790 | ||
1791 | static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) | |
1792 | { | |
1793 | struct usb_device *udev = priv->udev; | |
1794 | int ret; | |
1795 | ||
1796 | mutex_lock(&priv->usb_buf_mutex); | |
1797 | priv->usb_buf.val32 = cpu_to_le32(val); | |
1798 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), | |
1799 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, | |
1800 | addr, 0, &priv->usb_buf.val32, sizeof(u32), | |
1801 | RTW_USB_CONTROL_MSG_TIMEOUT); | |
1802 | mutex_unlock(&priv->usb_buf_mutex); | |
1803 | ||
1804 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) | |
1805 | dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", | |
1806 | __func__, addr, val); | |
1807 | return ret; | |
1808 | } | |
1809 | ||
1810 | static int | |
1811 | rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) | |
1812 | { | |
1813 | struct usb_device *udev = priv->udev; | |
1814 | int blocksize = priv->fops->writeN_block_size; | |
1815 | int ret, i, count, remainder; | |
1816 | ||
1817 | count = len / blocksize; | |
1818 | remainder = len % blocksize; | |
1819 | ||
1820 | for (i = 0; i < count; i++) { | |
1821 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), | |
1822 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, | |
1823 | addr, 0, buf, blocksize, | |
1824 | RTW_USB_CONTROL_MSG_TIMEOUT); | |
1825 | if (ret != blocksize) | |
1826 | goto write_error; | |
1827 | ||
1828 | addr += blocksize; | |
1829 | buf += blocksize; | |
1830 | } | |
1831 | ||
1832 | if (remainder) { | |
1833 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), | |
1834 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, | |
1835 | addr, 0, buf, remainder, | |
1836 | RTW_USB_CONTROL_MSG_TIMEOUT); | |
1837 | if (ret != remainder) | |
1838 | goto write_error; | |
1839 | } | |
1840 | ||
1841 | return len; | |
1842 | ||
1843 | write_error: | |
1844 | dev_info(&udev->dev, | |
1845 | "%s: Failed to write block at addr: %04x size: %04x\n", | |
1846 | __func__, addr, blocksize); | |
1847 | return -EAGAIN; | |
1848 | } | |
1849 | ||
1850 | static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, | |
1851 | enum rtl8xxxu_rfpath path, u8 reg) | |
1852 | { | |
1853 | u32 hssia, val32, retval; | |
1854 | ||
1855 | hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); | |
1856 | if (path != RF_A) | |
1857 | val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); | |
1858 | else | |
1859 | val32 = hssia; | |
1860 | ||
1861 | val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; | |
1862 | val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); | |
1863 | val32 |= FPGA0_HSSI_PARM2_EDGE_READ; | |
1864 | hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; | |
1865 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); | |
1866 | ||
1867 | udelay(10); | |
1868 | ||
1869 | rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); | |
1870 | udelay(100); | |
1871 | ||
1872 | hssia |= FPGA0_HSSI_PARM2_EDGE_READ; | |
1873 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); | |
1874 | udelay(10); | |
1875 | ||
1876 | val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); | |
1877 | if (val32 & FPGA0_HSSI_PARM1_PI) | |
1878 | retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); | |
1879 | else | |
1880 | retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); | |
1881 | ||
1882 | retval &= 0xfffff; | |
1883 | ||
1884 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) | |
1885 | dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", | |
1886 | __func__, reg, retval); | |
1887 | return retval; | |
1888 | } | |
1889 | ||
22a31d45 JS |
1890 | /* |
1891 | * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can | |
1892 | * have write issues in high temperature conditions. We may have to | |
1893 | * retry writing them. | |
1894 | */ | |
26f1fad2 JS |
1895 | static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, |
1896 | enum rtl8xxxu_rfpath path, u8 reg, u32 data) | |
1897 | { | |
1898 | int ret, retval; | |
2949b9ee | 1899 | u32 dataaddr, val32; |
26f1fad2 JS |
1900 | |
1901 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) | |
1902 | dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", | |
1903 | __func__, reg, data); | |
1904 | ||
1905 | data &= FPGA0_LSSI_PARM_DATA_MASK; | |
1906 | dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; | |
1907 | ||
2949b9ee JS |
1908 | if (priv->rtl_chip == RTL8192E) { |
1909 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); | |
1910 | val32 &= ~0x20000; | |
1911 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); | |
1912 | } | |
1913 | ||
26f1fad2 JS |
1914 | /* Use XB for path B */ |
1915 | ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); | |
1916 | if (ret != sizeof(dataaddr)) | |
1917 | retval = -EIO; | |
1918 | else | |
1919 | retval = 0; | |
1920 | ||
1921 | udelay(1); | |
1922 | ||
2949b9ee JS |
1923 | if (priv->rtl_chip == RTL8192E) { |
1924 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); | |
1925 | val32 |= 0x20000; | |
1926 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); | |
1927 | } | |
1928 | ||
26f1fad2 JS |
1929 | return retval; |
1930 | } | |
1931 | ||
8da91571 JS |
1932 | static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, |
1933 | struct h2c_cmd *h2c, int len) | |
26f1fad2 JS |
1934 | { |
1935 | struct device *dev = &priv->udev->dev; | |
1936 | int mbox_nr, retry, retval = 0; | |
1937 | int mbox_reg, mbox_ext_reg; | |
1938 | u8 val8; | |
1939 | ||
1940 | mutex_lock(&priv->h2c_mutex); | |
1941 | ||
1942 | mbox_nr = priv->next_mbox; | |
1943 | mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); | |
ed35d094 JS |
1944 | mbox_ext_reg = priv->fops->mbox_ext_reg + |
1945 | (mbox_nr * priv->fops->mbox_ext_width); | |
26f1fad2 JS |
1946 | |
1947 | /* | |
1948 | * MBOX ready? | |
1949 | */ | |
1950 | retry = 100; | |
1951 | do { | |
1952 | val8 = rtl8xxxu_read8(priv, REG_HMTFR); | |
1953 | if (!(val8 & BIT(mbox_nr))) | |
1954 | break; | |
1955 | } while (retry--); | |
1956 | ||
1957 | if (!retry) { | |
c7a5a190 | 1958 | dev_info(dev, "%s: Mailbox busy\n", __func__); |
26f1fad2 JS |
1959 | retval = -EBUSY; |
1960 | goto error; | |
1961 | } | |
1962 | ||
1963 | /* | |
1964 | * Need to swap as it's being swapped again by rtl8xxxu_write16/32() | |
1965 | */ | |
8da91571 | 1966 | if (len > sizeof(u32)) { |
ed35d094 JS |
1967 | if (priv->fops->mbox_ext_width == 4) { |
1968 | rtl8xxxu_write32(priv, mbox_ext_reg, | |
1969 | le32_to_cpu(h2c->raw_wide.ext)); | |
1970 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) | |
1971 | dev_info(dev, "H2C_EXT %08x\n", | |
1972 | le32_to_cpu(h2c->raw_wide.ext)); | |
1973 | } else { | |
1974 | rtl8xxxu_write16(priv, mbox_ext_reg, | |
1975 | le16_to_cpu(h2c->raw.ext)); | |
1976 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) | |
1977 | dev_info(dev, "H2C_EXT %04x\n", | |
1978 | le16_to_cpu(h2c->raw.ext)); | |
1979 | } | |
26f1fad2 JS |
1980 | } |
1981 | rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); | |
1982 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) | |
1983 | dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); | |
1984 | ||
1985 | priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; | |
1986 | ||
1987 | error: | |
1988 | mutex_unlock(&priv->h2c_mutex); | |
1989 | return retval; | |
1990 | } | |
1991 | ||
394f1bd3 JS |
1992 | static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) |
1993 | { | |
1994 | struct h2c_cmd h2c; | |
1995 | int reqnum = 0; | |
1996 | ||
1997 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
1998 | h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; | |
1999 | h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); | |
2000 | h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; | |
2001 | h2c.bt_mp_oper.data = data; | |
2002 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); | |
2003 | ||
2004 | reqnum++; | |
2005 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
2006 | h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; | |
2007 | h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); | |
2008 | h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; | |
2009 | h2c.bt_mp_oper.addr = reg; | |
2010 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); | |
2011 | } | |
2012 | ||
26f1fad2 JS |
2013 | static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv) |
2014 | { | |
2015 | u8 val8; | |
2016 | u32 val32; | |
2017 | ||
2018 | val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); | |
2019 | val8 |= BIT(0) | BIT(3); | |
2020 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); | |
2021 | ||
2022 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); | |
2023 | val32 &= ~(BIT(4) | BIT(5)); | |
2024 | val32 |= BIT(3); | |
2025 | if (priv->rf_paths == 2) { | |
2026 | val32 &= ~(BIT(20) | BIT(21)); | |
2027 | val32 |= BIT(19); | |
2028 | } | |
2029 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); | |
2030 | ||
2031 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); | |
2032 | val32 &= ~OFDM_RF_PATH_TX_MASK; | |
2033 | if (priv->tx_paths == 2) | |
2034 | val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; | |
ba17d824 | 2035 | else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) |
26f1fad2 JS |
2036 | val32 |= OFDM_RF_PATH_TX_B; |
2037 | else | |
2038 | val32 |= OFDM_RF_PATH_TX_A; | |
2039 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); | |
2040 | ||
2041 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
2042 | val32 &= ~FPGA_RF_MODE_JAPAN; | |
2043 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
2044 | ||
2045 | if (priv->rf_paths == 2) | |
2046 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); | |
2047 | else | |
2048 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); | |
2049 | ||
2050 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); | |
2051 | if (priv->rf_paths == 2) | |
2052 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); | |
2053 | ||
2054 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); | |
2055 | } | |
2056 | ||
2057 | static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv) | |
2058 | { | |
2059 | u8 sps0; | |
2060 | u32 val32; | |
2061 | ||
2062 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); | |
2063 | ||
2064 | sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); | |
2065 | ||
2066 | /* RF RX code for preamble power saving */ | |
2067 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); | |
2068 | val32 &= ~(BIT(3) | BIT(4) | BIT(5)); | |
2069 | if (priv->rf_paths == 2) | |
2070 | val32 &= ~(BIT(19) | BIT(20) | BIT(21)); | |
2071 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); | |
2072 | ||
2073 | /* Disable TX for four paths */ | |
2074 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); | |
2075 | val32 &= ~OFDM_RF_PATH_TX_MASK; | |
2076 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); | |
2077 | ||
2078 | /* Enable power saving */ | |
2079 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
2080 | val32 |= FPGA_RF_MODE_JAPAN; | |
2081 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
2082 | ||
2083 | /* AFE control register to power down bits [30:22] */ | |
2084 | if (priv->rf_paths == 2) | |
2085 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); | |
2086 | else | |
2087 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); | |
2088 | ||
2089 | /* Power down RF module */ | |
2090 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); | |
2091 | if (priv->rf_paths == 2) | |
2092 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); | |
2093 | ||
2094 | sps0 &= ~(BIT(0) | BIT(3)); | |
2095 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); | |
2096 | } | |
2097 | ||
2098 | ||
2099 | static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv) | |
2100 | { | |
2101 | u8 val8; | |
2102 | ||
2103 | val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); | |
2104 | val8 &= ~BIT(6); | |
2105 | rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); | |
2106 | ||
2107 | rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); | |
2108 | val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); | |
2109 | val8 &= ~BIT(0); | |
2110 | rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); | |
2111 | } | |
2112 | ||
2113 | ||
2114 | /* | |
2115 | * The rtl8723a has 3 channel groups for it's efuse settings. It only | |
2116 | * supports the 2.4GHz band, so channels 1 - 14: | |
2117 | * group 0: channels 1 - 3 | |
2118 | * group 1: channels 4 - 9 | |
2119 | * group 2: channels 10 - 14 | |
2120 | * | |
2121 | * Note: We index from 0 in the code | |
2122 | */ | |
2123 | static int rtl8723a_channel_to_group(int channel) | |
2124 | { | |
2125 | int group; | |
2126 | ||
2127 | if (channel < 4) | |
2128 | group = 0; | |
2129 | else if (channel < 10) | |
2130 | group = 1; | |
2131 | else | |
2132 | group = 2; | |
2133 | ||
2134 | return group; | |
2135 | } | |
2136 | ||
9e24772a JS |
2137 | /* |
2138 | * Valid for rtl8723bu and rtl8192eu | |
2139 | */ | |
e796dab4 JS |
2140 | static int rtl8723b_channel_to_group(int channel) |
2141 | { | |
2142 | int group; | |
2143 | ||
2144 | if (channel < 3) | |
2145 | group = 0; | |
2146 | else if (channel < 6) | |
2147 | group = 1; | |
2148 | else if (channel < 9) | |
2149 | group = 2; | |
2150 | else if (channel < 12) | |
2151 | group = 3; | |
2152 | else | |
2153 | group = 4; | |
2154 | ||
2155 | return group; | |
2156 | } | |
2157 | ||
26f1fad2 JS |
2158 | static void rtl8723au_config_channel(struct ieee80211_hw *hw) |
2159 | { | |
2160 | struct rtl8xxxu_priv *priv = hw->priv; | |
2161 | u32 val32, rsr; | |
2162 | u8 val8, opmode; | |
2163 | bool ht = true; | |
2164 | int sec_ch_above, channel; | |
2165 | int i; | |
2166 | ||
2167 | opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); | |
2168 | rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); | |
2169 | channel = hw->conf.chandef.chan->hw_value; | |
2170 | ||
2171 | switch (hw->conf.chandef.width) { | |
2172 | case NL80211_CHAN_WIDTH_20_NOHT: | |
2173 | ht = false; | |
2174 | case NL80211_CHAN_WIDTH_20: | |
2175 | opmode |= BW_OPMODE_20MHZ; | |
2176 | rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); | |
2177 | ||
2178 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
2179 | val32 &= ~FPGA_RF_MODE; | |
2180 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
2181 | ||
2182 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); | |
2183 | val32 &= ~FPGA_RF_MODE; | |
2184 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); | |
2185 | ||
2186 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); | |
2187 | val32 |= FPGA0_ANALOG2_20MHZ; | |
2188 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); | |
2189 | break; | |
2190 | case NL80211_CHAN_WIDTH_40: | |
2191 | if (hw->conf.chandef.center_freq1 > | |
2192 | hw->conf.chandef.chan->center_freq) { | |
2193 | sec_ch_above = 1; | |
2194 | channel += 2; | |
2195 | } else { | |
2196 | sec_ch_above = 0; | |
2197 | channel -= 2; | |
2198 | } | |
2199 | ||
2200 | opmode &= ~BW_OPMODE_20MHZ; | |
2201 | rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); | |
2202 | rsr &= ~RSR_RSC_BANDWIDTH_40M; | |
2203 | if (sec_ch_above) | |
2204 | rsr |= RSR_RSC_UPPER_SUB_CHANNEL; | |
2205 | else | |
2206 | rsr |= RSR_RSC_LOWER_SUB_CHANNEL; | |
2207 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); | |
2208 | ||
2209 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
2210 | val32 |= FPGA_RF_MODE; | |
2211 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
2212 | ||
2213 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); | |
2214 | val32 |= FPGA_RF_MODE; | |
2215 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); | |
2216 | ||
2217 | /* | |
2218 | * Set Control channel to upper or lower. These settings | |
2219 | * are required only for 40MHz | |
2220 | */ | |
2221 | val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); | |
2222 | val32 &= ~CCK0_SIDEBAND; | |
2223 | if (!sec_ch_above) | |
2224 | val32 |= CCK0_SIDEBAND; | |
2225 | rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); | |
2226 | ||
2227 | val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); | |
2228 | val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ | |
2229 | if (sec_ch_above) | |
2230 | val32 |= OFDM_LSTF_PRIME_CH_LOW; | |
2231 | else | |
2232 | val32 |= OFDM_LSTF_PRIME_CH_HIGH; | |
2233 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); | |
2234 | ||
2235 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); | |
2236 | val32 &= ~FPGA0_ANALOG2_20MHZ; | |
2237 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); | |
2238 | ||
2239 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); | |
2240 | val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); | |
2241 | if (sec_ch_above) | |
2242 | val32 |= FPGA0_PS_UPPER_CHANNEL; | |
2243 | else | |
2244 | val32 |= FPGA0_PS_LOWER_CHANNEL; | |
2245 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); | |
2246 | break; | |
2247 | ||
2248 | default: | |
2249 | break; | |
2250 | } | |
2251 | ||
2252 | for (i = RF_A; i < priv->rf_paths; i++) { | |
2253 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); | |
2254 | val32 &= ~MODE_AG_CHANNEL_MASK; | |
2255 | val32 |= channel; | |
2256 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); | |
2257 | } | |
2258 | ||
2259 | if (ht) | |
2260 | val8 = 0x0e; | |
2261 | else | |
2262 | val8 = 0x0a; | |
2263 | ||
2264 | rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); | |
2265 | rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); | |
2266 | ||
2267 | rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); | |
2268 | rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); | |
2269 | ||
2270 | for (i = RF_A; i < priv->rf_paths; i++) { | |
2271 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); | |
2272 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) | |
2273 | val32 &= ~MODE_AG_CHANNEL_20MHZ; | |
2274 | else | |
2275 | val32 |= MODE_AG_CHANNEL_20MHZ; | |
2276 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); | |
2277 | } | |
2278 | } | |
2279 | ||
c3f9506f JS |
2280 | static void rtl8723bu_config_channel(struct ieee80211_hw *hw) |
2281 | { | |
2282 | struct rtl8xxxu_priv *priv = hw->priv; | |
2283 | u32 val32, rsr; | |
368633ce | 2284 | u8 val8, subchannel; |
c3f9506f JS |
2285 | u16 rf_mode_bw; |
2286 | bool ht = true; | |
2287 | int sec_ch_above, channel; | |
2288 | int i; | |
2289 | ||
2290 | rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); | |
2291 | rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; | |
2292 | rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); | |
2293 | channel = hw->conf.chandef.chan->hw_value; | |
2294 | ||
2295 | /* Hack */ | |
2296 | subchannel = 0; | |
2297 | ||
2298 | switch (hw->conf.chandef.width) { | |
2299 | case NL80211_CHAN_WIDTH_20_NOHT: | |
2300 | ht = false; | |
2301 | case NL80211_CHAN_WIDTH_20: | |
2302 | rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; | |
2303 | subchannel = 0; | |
2304 | ||
2305 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
2306 | val32 &= ~FPGA_RF_MODE; | |
2307 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
2308 | ||
2309 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); | |
2310 | val32 &= ~FPGA_RF_MODE; | |
2311 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); | |
2312 | ||
2313 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); | |
2314 | val32 &= ~(BIT(30) | BIT(31)); | |
2315 | rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); | |
2316 | ||
2317 | break; | |
2318 | case NL80211_CHAN_WIDTH_40: | |
2319 | rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; | |
2320 | ||
2321 | if (hw->conf.chandef.center_freq1 > | |
2322 | hw->conf.chandef.chan->center_freq) { | |
2323 | sec_ch_above = 1; | |
2324 | channel += 2; | |
2325 | } else { | |
2326 | sec_ch_above = 0; | |
2327 | channel -= 2; | |
2328 | } | |
2329 | ||
2330 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
2331 | val32 |= FPGA_RF_MODE; | |
2332 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
2333 | ||
2334 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); | |
2335 | val32 |= FPGA_RF_MODE; | |
2336 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); | |
2337 | ||
2338 | /* | |
2339 | * Set Control channel to upper or lower. These settings | |
2340 | * are required only for 40MHz | |
2341 | */ | |
2342 | val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); | |
2343 | val32 &= ~CCK0_SIDEBAND; | |
2344 | if (!sec_ch_above) | |
2345 | val32 |= CCK0_SIDEBAND; | |
2346 | rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); | |
2347 | ||
2348 | val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); | |
2349 | val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ | |
2350 | if (sec_ch_above) | |
2351 | val32 |= OFDM_LSTF_PRIME_CH_LOW; | |
2352 | else | |
2353 | val32 |= OFDM_LSTF_PRIME_CH_HIGH; | |
2354 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); | |
2355 | ||
2356 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); | |
2357 | val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); | |
2358 | if (sec_ch_above) | |
2359 | val32 |= FPGA0_PS_UPPER_CHANNEL; | |
2360 | else | |
2361 | val32 |= FPGA0_PS_LOWER_CHANNEL; | |
2362 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); | |
2363 | break; | |
2364 | case NL80211_CHAN_WIDTH_80: | |
2365 | rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; | |
2366 | break; | |
2367 | default: | |
2368 | break; | |
2369 | } | |
2370 | ||
2371 | for (i = RF_A; i < priv->rf_paths; i++) { | |
2372 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); | |
2373 | val32 &= ~MODE_AG_CHANNEL_MASK; | |
2374 | val32 |= channel; | |
2375 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); | |
2376 | } | |
2377 | ||
2378 | rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); | |
2379 | rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); | |
2380 | ||
2381 | if (ht) | |
2382 | val8 = 0x0e; | |
2383 | else | |
2384 | val8 = 0x0a; | |
2385 | ||
2386 | rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); | |
2387 | rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); | |
2388 | ||
2389 | rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); | |
2390 | rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); | |
2391 | ||
2392 | for (i = RF_A; i < priv->rf_paths; i++) { | |
2393 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); | |
2394 | val32 &= ~MODE_AG_BW_MASK; | |
2395 | switch(hw->conf.chandef.width) { | |
2396 | case NL80211_CHAN_WIDTH_80: | |
2397 | val32 |= MODE_AG_BW_80MHZ_8723B; | |
2398 | break; | |
2399 | case NL80211_CHAN_WIDTH_40: | |
2400 | val32 |= MODE_AG_BW_40MHZ_8723B; | |
2401 | break; | |
2402 | default: | |
2403 | val32 |= MODE_AG_BW_20MHZ_8723B; | |
2404 | break; | |
2405 | } | |
2406 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); | |
2407 | } | |
2408 | } | |
2409 | ||
26f1fad2 JS |
2410 | static void |
2411 | rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) | |
2412 | { | |
2413 | u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; | |
2414 | u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; | |
2415 | u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; | |
2416 | u8 val8; | |
2417 | int group, i; | |
2418 | ||
2419 | group = rtl8723a_channel_to_group(channel); | |
2420 | ||
2421 | cck[0] = priv->cck_tx_power_index_A[group]; | |
2422 | cck[1] = priv->cck_tx_power_index_B[group]; | |
2423 | ||
2424 | ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; | |
2425 | ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; | |
2426 | ||
2427 | ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; | |
2428 | ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; | |
2429 | ||
2430 | mcsbase[0] = ofdm[0]; | |
2431 | mcsbase[1] = ofdm[1]; | |
2432 | if (!ht40) { | |
2433 | mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; | |
2434 | mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; | |
2435 | } | |
2436 | ||
2437 | if (priv->tx_paths > 1) { | |
2438 | if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) | |
2439 | ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; | |
2440 | if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) | |
2441 | ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; | |
2442 | } | |
2443 | ||
2444 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) | |
2445 | dev_info(&priv->udev->dev, | |
2446 | "%s: Setting TX power CCK A: %02x, " | |
2447 | "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", | |
2448 | __func__, cck[0], cck[1], ofdm[0], ofdm[1]); | |
2449 | ||
2450 | for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { | |
2451 | if (cck[i] > RF6052_MAX_TX_PWR) | |
2452 | cck[i] = RF6052_MAX_TX_PWR; | |
2453 | if (ofdm[i] > RF6052_MAX_TX_PWR) | |
2454 | ofdm[i] = RF6052_MAX_TX_PWR; | |
2455 | } | |
2456 | ||
2457 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); | |
2458 | val32 &= 0xffff00ff; | |
2459 | val32 |= (cck[0] << 8); | |
2460 | rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); | |
2461 | ||
2462 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); | |
2463 | val32 &= 0xff; | |
2464 | val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); | |
2465 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); | |
2466 | ||
2467 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); | |
2468 | val32 &= 0xffffff00; | |
2469 | val32 |= cck[1]; | |
2470 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); | |
2471 | ||
2472 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); | |
2473 | val32 &= 0xff; | |
2474 | val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); | |
2475 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); | |
2476 | ||
2477 | ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | | |
2478 | ofdmbase[0] << 16 | ofdmbase[0] << 24; | |
2479 | ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | | |
2480 | ofdmbase[1] << 16 | ofdmbase[1] << 24; | |
2481 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a); | |
2482 | rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b); | |
2483 | ||
2484 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a); | |
2485 | rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b); | |
2486 | ||
2487 | mcs_a = mcsbase[0] | mcsbase[0] << 8 | | |
2488 | mcsbase[0] << 16 | mcsbase[0] << 24; | |
2489 | mcs_b = mcsbase[1] | mcsbase[1] << 8 | | |
2490 | mcsbase[1] << 16 | mcsbase[1] << 24; | |
2491 | ||
2492 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a); | |
2493 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b); | |
2494 | ||
2495 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a); | |
2496 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b); | |
2497 | ||
2498 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a); | |
2499 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b); | |
2500 | ||
2501 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a); | |
2502 | for (i = 0; i < 3; i++) { | |
2503 | if (i != 2) | |
2504 | val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; | |
2505 | else | |
2506 | val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; | |
2507 | rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); | |
2508 | } | |
2509 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b); | |
2510 | for (i = 0; i < 3; i++) { | |
2511 | if (i != 2) | |
2512 | val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; | |
2513 | else | |
2514 | val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; | |
2515 | rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); | |
2516 | } | |
2517 | } | |
2518 | ||
e796dab4 JS |
2519 | static void |
2520 | rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) | |
2521 | { | |
1d3cc44d JS |
2522 | u32 val32, ofdm, mcs; |
2523 | u8 cck, ofdmbase, mcsbase; | |
54bed43f | 2524 | int group, tx_idx; |
e796dab4 | 2525 | |
54bed43f | 2526 | tx_idx = 0; |
e796dab4 | 2527 | group = rtl8723b_channel_to_group(channel); |
54bed43f JS |
2528 | |
2529 | cck = priv->cck_tx_power_index_B[group]; | |
2530 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); | |
2531 | val32 &= 0xffff00ff; | |
2532 | val32 |= (cck << 8); | |
2533 | rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); | |
2534 | ||
2535 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); | |
2536 | val32 &= 0xff; | |
2537 | val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); | |
2538 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); | |
2539 | ||
2540 | ofdmbase = priv->ht40_1s_tx_power_index_B[group]; | |
2541 | ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; | |
2542 | ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; | |
2543 | ||
2544 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); | |
2545 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); | |
1d3cc44d JS |
2546 | |
2547 | mcsbase = priv->ht40_1s_tx_power_index_B[group]; | |
2548 | if (ht40) | |
2549 | mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; | |
2550 | else | |
2551 | mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; | |
2552 | mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; | |
2553 | ||
2554 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); | |
2555 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); | |
e796dab4 JS |
2556 | } |
2557 | ||
26f1fad2 JS |
2558 | static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, |
2559 | enum nl80211_iftype linktype) | |
2560 | { | |
a26703f3 | 2561 | u8 val8; |
26f1fad2 | 2562 | |
a26703f3 | 2563 | val8 = rtl8xxxu_read8(priv, REG_MSR); |
26f1fad2 JS |
2564 | val8 &= ~MSR_LINKTYPE_MASK; |
2565 | ||
2566 | switch (linktype) { | |
2567 | case NL80211_IFTYPE_UNSPECIFIED: | |
2568 | val8 |= MSR_LINKTYPE_NONE; | |
2569 | break; | |
2570 | case NL80211_IFTYPE_ADHOC: | |
2571 | val8 |= MSR_LINKTYPE_ADHOC; | |
2572 | break; | |
2573 | case NL80211_IFTYPE_STATION: | |
2574 | val8 |= MSR_LINKTYPE_STATION; | |
2575 | break; | |
2576 | case NL80211_IFTYPE_AP: | |
2577 | val8 |= MSR_LINKTYPE_AP; | |
2578 | break; | |
2579 | default: | |
2580 | goto out; | |
2581 | } | |
2582 | ||
2583 | rtl8xxxu_write8(priv, REG_MSR, val8); | |
2584 | out: | |
2585 | return; | |
2586 | } | |
2587 | ||
2588 | static void | |
2589 | rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) | |
2590 | { | |
2591 | u16 val16; | |
2592 | ||
2593 | val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & | |
2594 | RETRY_LIMIT_SHORT_MASK) | | |
2595 | ((long_retry << RETRY_LIMIT_LONG_SHIFT) & | |
2596 | RETRY_LIMIT_LONG_MASK); | |
2597 | ||
2598 | rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); | |
2599 | } | |
2600 | ||
2601 | static void | |
2602 | rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) | |
2603 | { | |
2604 | u16 val16; | |
2605 | ||
2606 | val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | | |
2607 | ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); | |
2608 | ||
2609 | rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); | |
2610 | } | |
2611 | ||
2612 | static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) | |
2613 | { | |
2614 | struct device *dev = &priv->udev->dev; | |
2615 | char *cut; | |
2616 | ||
2617 | switch (priv->chip_cut) { | |
2618 | case 0: | |
2619 | cut = "A"; | |
2620 | break; | |
2621 | case 1: | |
2622 | cut = "B"; | |
2623 | break; | |
0e5d435a JS |
2624 | case 2: |
2625 | cut = "C"; | |
2626 | break; | |
2627 | case 3: | |
2628 | cut = "D"; | |
2629 | break; | |
2630 | case 4: | |
2631 | cut = "E"; | |
2632 | break; | |
26f1fad2 JS |
2633 | default: |
2634 | cut = "unknown"; | |
2635 | } | |
2636 | ||
2637 | dev_info(dev, | |
2638 | "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", | |
0e5d435a JS |
2639 | priv->chip_name, cut, priv->chip_vendor, priv->tx_paths, |
2640 | priv->rx_paths, priv->ep_tx_count, priv->has_wifi, | |
2641 | priv->has_bluetooth, priv->has_gps, priv->hi_pa); | |
26f1fad2 JS |
2642 | |
2643 | dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); | |
2644 | } | |
2645 | ||
2646 | static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) | |
2647 | { | |
2648 | struct device *dev = &priv->udev->dev; | |
2649 | u32 val32, bonding; | |
2650 | u16 val16; | |
2651 | ||
2652 | val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); | |
2653 | priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >> | |
2654 | SYS_CFG_CHIP_VERSION_SHIFT; | |
2655 | if (val32 & SYS_CFG_TRP_VAUX_EN) { | |
2656 | dev_info(dev, "Unsupported test chip\n"); | |
2657 | return -ENOTSUPP; | |
2658 | } | |
2659 | ||
2660 | if (val32 & SYS_CFG_BT_FUNC) { | |
35a741fe JS |
2661 | if (priv->chip_cut >= 3) { |
2662 | sprintf(priv->chip_name, "8723BU"); | |
ba17d824 | 2663 | priv->rtl_chip = RTL8723B; |
35a741fe JS |
2664 | } else { |
2665 | sprintf(priv->chip_name, "8723AU"); | |
0e28b975 | 2666 | priv->usb_interrupts = 1; |
ba17d824 | 2667 | priv->rtl_chip = RTL8723A; |
35a741fe JS |
2668 | } |
2669 | ||
26f1fad2 JS |
2670 | priv->rf_paths = 1; |
2671 | priv->rx_paths = 1; | |
2672 | priv->tx_paths = 1; | |
26f1fad2 JS |
2673 | |
2674 | val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); | |
2675 | if (val32 & MULTI_WIFI_FUNC_EN) | |
2676 | priv->has_wifi = 1; | |
2677 | if (val32 & MULTI_BT_FUNC_EN) | |
2678 | priv->has_bluetooth = 1; | |
2679 | if (val32 & MULTI_GPS_FUNC_EN) | |
2680 | priv->has_gps = 1; | |
38451998 | 2681 | priv->is_multi_func = 1; |
26f1fad2 JS |
2682 | } else if (val32 & SYS_CFG_TYPE_ID) { |
2683 | bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); | |
2684 | bonding &= HPON_FSM_BONDING_MASK; | |
af13faff | 2685 | if (priv->fops->has_s0s1) { |
0e5d435a JS |
2686 | if (bonding == HPON_FSM_BONDING_1T2R) { |
2687 | sprintf(priv->chip_name, "8191EU"); | |
2688 | priv->rf_paths = 2; | |
2689 | priv->rx_paths = 2; | |
2690 | priv->tx_paths = 1; | |
ba17d824 | 2691 | priv->rtl_chip = RTL8191E; |
0e5d435a JS |
2692 | } else { |
2693 | sprintf(priv->chip_name, "8192EU"); | |
2694 | priv->rf_paths = 2; | |
2695 | priv->rx_paths = 2; | |
2696 | priv->tx_paths = 2; | |
ba17d824 | 2697 | priv->rtl_chip = RTL8192E; |
0e5d435a JS |
2698 | } |
2699 | } else if (bonding == HPON_FSM_BONDING_1T2R) { | |
26f1fad2 JS |
2700 | sprintf(priv->chip_name, "8191CU"); |
2701 | priv->rf_paths = 2; | |
2702 | priv->rx_paths = 2; | |
2703 | priv->tx_paths = 1; | |
0e28b975 | 2704 | priv->usb_interrupts = 1; |
ba17d824 | 2705 | priv->rtl_chip = RTL8191C; |
26f1fad2 JS |
2706 | } else { |
2707 | sprintf(priv->chip_name, "8192CU"); | |
2708 | priv->rf_paths = 2; | |
2709 | priv->rx_paths = 2; | |
2710 | priv->tx_paths = 2; | |
0e28b975 | 2711 | priv->usb_interrupts = 1; |
ba17d824 | 2712 | priv->rtl_chip = RTL8192C; |
26f1fad2 JS |
2713 | } |
2714 | priv->has_wifi = 1; | |
2715 | } else { | |
2716 | sprintf(priv->chip_name, "8188CU"); | |
2717 | priv->rf_paths = 1; | |
2718 | priv->rx_paths = 1; | |
2719 | priv->tx_paths = 1; | |
ba17d824 | 2720 | priv->rtl_chip = RTL8188C; |
0e28b975 | 2721 | priv->usb_interrupts = 1; |
26f1fad2 JS |
2722 | priv->has_wifi = 1; |
2723 | } | |
2724 | ||
ba17d824 JS |
2725 | switch (priv->rtl_chip) { |
2726 | case RTL8188E: | |
2727 | case RTL8192E: | |
2728 | case RTL8723B: | |
0e5d435a JS |
2729 | switch (val32 & SYS_CFG_VENDOR_EXT_MASK) { |
2730 | case SYS_CFG_VENDOR_ID_TSMC: | |
2731 | sprintf(priv->chip_vendor, "TSMC"); | |
2732 | break; | |
2733 | case SYS_CFG_VENDOR_ID_SMIC: | |
2734 | sprintf(priv->chip_vendor, "SMIC"); | |
2735 | priv->vendor_smic = 1; | |
2736 | break; | |
2737 | case SYS_CFG_VENDOR_ID_UMC: | |
2738 | sprintf(priv->chip_vendor, "UMC"); | |
2739 | priv->vendor_umc = 1; | |
2740 | break; | |
2741 | default: | |
2742 | sprintf(priv->chip_vendor, "unknown"); | |
2743 | } | |
2744 | break; | |
2745 | default: | |
2746 | if (val32 & SYS_CFG_VENDOR_ID) { | |
2747 | sprintf(priv->chip_vendor, "UMC"); | |
2748 | priv->vendor_umc = 1; | |
2749 | } else { | |
2750 | sprintf(priv->chip_vendor, "TSMC"); | |
2751 | } | |
2752 | } | |
26f1fad2 JS |
2753 | |
2754 | val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); | |
2755 | priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; | |
2756 | ||
2757 | val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); | |
2758 | if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { | |
2759 | priv->ep_tx_high_queue = 1; | |
2760 | priv->ep_tx_count++; | |
2761 | } | |
2762 | ||
2763 | if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { | |
2764 | priv->ep_tx_normal_queue = 1; | |
2765 | priv->ep_tx_count++; | |
2766 | } | |
2767 | ||
2768 | if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { | |
2769 | priv->ep_tx_low_queue = 1; | |
2770 | priv->ep_tx_count++; | |
2771 | } | |
2772 | ||
2773 | /* | |
2774 | * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX | |
2775 | */ | |
2776 | if (!priv->ep_tx_count) { | |
2777 | switch (priv->nr_out_eps) { | |
35a741fe | 2778 | case 4: |
26f1fad2 JS |
2779 | case 3: |
2780 | priv->ep_tx_low_queue = 1; | |
2781 | priv->ep_tx_count++; | |
2782 | case 2: | |
2783 | priv->ep_tx_normal_queue = 1; | |
2784 | priv->ep_tx_count++; | |
2785 | case 1: | |
2786 | priv->ep_tx_high_queue = 1; | |
2787 | priv->ep_tx_count++; | |
2788 | break; | |
2789 | default: | |
2790 | dev_info(dev, "Unsupported USB TX end-points\n"); | |
2791 | return -ENOTSUPP; | |
2792 | } | |
2793 | } | |
2794 | ||
2795 | return 0; | |
2796 | } | |
2797 | ||
2798 | static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv) | |
2799 | { | |
d38f1c37 JS |
2800 | struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723; |
2801 | ||
2802 | if (efuse->rtl_id != cpu_to_le16(0x8129)) | |
26f1fad2 JS |
2803 | return -EINVAL; |
2804 | ||
d38f1c37 | 2805 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
26f1fad2 JS |
2806 | |
2807 | memcpy(priv->cck_tx_power_index_A, | |
d38f1c37 | 2808 | efuse->cck_tx_power_index_A, |
3e84f938 | 2809 | sizeof(efuse->cck_tx_power_index_A)); |
26f1fad2 | 2810 | memcpy(priv->cck_tx_power_index_B, |
d38f1c37 | 2811 | efuse->cck_tx_power_index_B, |
3e84f938 | 2812 | sizeof(efuse->cck_tx_power_index_B)); |
26f1fad2 JS |
2813 | |
2814 | memcpy(priv->ht40_1s_tx_power_index_A, | |
d38f1c37 | 2815 | efuse->ht40_1s_tx_power_index_A, |
3e84f938 | 2816 | sizeof(efuse->ht40_1s_tx_power_index_A)); |
26f1fad2 | 2817 | memcpy(priv->ht40_1s_tx_power_index_B, |
d38f1c37 | 2818 | efuse->ht40_1s_tx_power_index_B, |
3e84f938 | 2819 | sizeof(efuse->ht40_1s_tx_power_index_B)); |
26f1fad2 JS |
2820 | |
2821 | memcpy(priv->ht20_tx_power_index_diff, | |
d38f1c37 | 2822 | efuse->ht20_tx_power_index_diff, |
3e84f938 | 2823 | sizeof(efuse->ht20_tx_power_index_diff)); |
26f1fad2 | 2824 | memcpy(priv->ofdm_tx_power_index_diff, |
d38f1c37 | 2825 | efuse->ofdm_tx_power_index_diff, |
3e84f938 | 2826 | sizeof(efuse->ofdm_tx_power_index_diff)); |
26f1fad2 JS |
2827 | |
2828 | memcpy(priv->ht40_max_power_offset, | |
d38f1c37 | 2829 | efuse->ht40_max_power_offset, |
3e84f938 | 2830 | sizeof(efuse->ht40_max_power_offset)); |
26f1fad2 | 2831 | memcpy(priv->ht20_max_power_offset, |
d38f1c37 | 2832 | efuse->ht20_max_power_offset, |
3e84f938 | 2833 | sizeof(efuse->ht20_max_power_offset)); |
26f1fad2 | 2834 | |
4ef22eb9 JS |
2835 | if (priv->efuse_wifi.efuse8723.version >= 0x01) { |
2836 | priv->has_xtalk = 1; | |
2837 | priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f; | |
2838 | } | |
26f1fad2 | 2839 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", |
d38f1c37 | 2840 | efuse->vendor_name); |
26f1fad2 | 2841 | dev_info(&priv->udev->dev, "Product: %.41s\n", |
d38f1c37 | 2842 | efuse->device_name); |
26f1fad2 JS |
2843 | return 0; |
2844 | } | |
2845 | ||
3c836d60 JS |
2846 | static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) |
2847 | { | |
b8ba8602 | 2848 | struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; |
3be26999 | 2849 | int i; |
b8ba8602 JS |
2850 | |
2851 | if (efuse->rtl_id != cpu_to_le16(0x8129)) | |
3c836d60 JS |
2852 | return -EINVAL; |
2853 | ||
b8ba8602 | 2854 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
3c836d60 | 2855 | |
3be26999 JS |
2856 | memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, |
2857 | sizeof(efuse->tx_power_index_A.cck_base)); | |
2858 | memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, | |
2859 | sizeof(efuse->tx_power_index_B.cck_base)); | |
2860 | ||
2861 | memcpy(priv->ht40_1s_tx_power_index_A, | |
2862 | efuse->tx_power_index_A.ht40_base, | |
2863 | sizeof(efuse->tx_power_index_A.ht40_base)); | |
2864 | memcpy(priv->ht40_1s_tx_power_index_B, | |
2865 | efuse->tx_power_index_B.ht40_base, | |
2866 | sizeof(efuse->tx_power_index_B.ht40_base)); | |
2867 | ||
2868 | priv->ofdm_tx_power_diff[0].a = | |
2869 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; | |
2870 | priv->ofdm_tx_power_diff[0].b = | |
2871 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.a; | |
2872 | ||
2873 | priv->ht20_tx_power_diff[0].a = | |
2874 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; | |
2875 | priv->ht20_tx_power_diff[0].b = | |
2876 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; | |
2877 | ||
2878 | priv->ht40_tx_power_diff[0].a = 0; | |
2879 | priv->ht40_tx_power_diff[0].b = 0; | |
2880 | ||
2881 | for (i = 1; i < RTL8723B_TX_COUNT; i++) { | |
2882 | priv->ofdm_tx_power_diff[i].a = | |
2883 | efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; | |
2884 | priv->ofdm_tx_power_diff[i].b = | |
2885 | efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; | |
2886 | ||
2887 | priv->ht20_tx_power_diff[i].a = | |
2888 | efuse->tx_power_index_A.pwr_diff[i - 1].ht20; | |
2889 | priv->ht20_tx_power_diff[i].b = | |
2890 | efuse->tx_power_index_B.pwr_diff[i - 1].ht20; | |
2891 | ||
2892 | priv->ht40_tx_power_diff[i].a = | |
2893 | efuse->tx_power_index_A.pwr_diff[i - 1].ht40; | |
2894 | priv->ht40_tx_power_diff[i].b = | |
2895 | efuse->tx_power_index_B.pwr_diff[i - 1].ht40; | |
2896 | } | |
2897 | ||
4ef22eb9 JS |
2898 | priv->has_xtalk = 1; |
2899 | priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; | |
2900 | ||
b8ba8602 JS |
2901 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); |
2902 | dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name); | |
3c836d60 JS |
2903 | |
2904 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { | |
2905 | int i; | |
2906 | unsigned char *raw = priv->efuse_wifi.raw; | |
2907 | ||
2908 | dev_info(&priv->udev->dev, | |
2909 | "%s: dumping efuse (0x%02zx bytes):\n", | |
2910 | __func__, sizeof(struct rtl8723bu_efuse)); | |
2911 | for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) { | |
2912 | dev_info(&priv->udev->dev, "%02x: " | |
2913 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", i, | |
2914 | raw[i], raw[i + 1], raw[i + 2], | |
2915 | raw[i + 3], raw[i + 4], raw[i + 5], | |
2916 | raw[i + 6], raw[i + 7]); | |
2917 | } | |
2918 | } | |
2919 | ||
2920 | return 0; | |
2921 | } | |
2922 | ||
c0963772 KV |
2923 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
2924 | ||
26f1fad2 JS |
2925 | static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv) |
2926 | { | |
49594441 | 2927 | struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192; |
26f1fad2 JS |
2928 | int i; |
2929 | ||
49594441 | 2930 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
26f1fad2 JS |
2931 | return -EINVAL; |
2932 | ||
49594441 | 2933 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
26f1fad2 JS |
2934 | |
2935 | memcpy(priv->cck_tx_power_index_A, | |
49594441 | 2936 | efuse->cck_tx_power_index_A, |
3e84f938 | 2937 | sizeof(efuse->cck_tx_power_index_A)); |
26f1fad2 | 2938 | memcpy(priv->cck_tx_power_index_B, |
49594441 | 2939 | efuse->cck_tx_power_index_B, |
3e84f938 | 2940 | sizeof(efuse->cck_tx_power_index_B)); |
26f1fad2 JS |
2941 | |
2942 | memcpy(priv->ht40_1s_tx_power_index_A, | |
49594441 | 2943 | efuse->ht40_1s_tx_power_index_A, |
3e84f938 | 2944 | sizeof(efuse->ht40_1s_tx_power_index_A)); |
26f1fad2 | 2945 | memcpy(priv->ht40_1s_tx_power_index_B, |
49594441 | 2946 | efuse->ht40_1s_tx_power_index_B, |
3e84f938 | 2947 | sizeof(efuse->ht40_1s_tx_power_index_B)); |
26f1fad2 | 2948 | memcpy(priv->ht40_2s_tx_power_index_diff, |
49594441 | 2949 | efuse->ht40_2s_tx_power_index_diff, |
3e84f938 | 2950 | sizeof(efuse->ht40_2s_tx_power_index_diff)); |
26f1fad2 JS |
2951 | |
2952 | memcpy(priv->ht20_tx_power_index_diff, | |
49594441 | 2953 | efuse->ht20_tx_power_index_diff, |
3e84f938 | 2954 | sizeof(efuse->ht20_tx_power_index_diff)); |
26f1fad2 | 2955 | memcpy(priv->ofdm_tx_power_index_diff, |
49594441 | 2956 | efuse->ofdm_tx_power_index_diff, |
3e84f938 | 2957 | sizeof(efuse->ofdm_tx_power_index_diff)); |
26f1fad2 JS |
2958 | |
2959 | memcpy(priv->ht40_max_power_offset, | |
49594441 | 2960 | efuse->ht40_max_power_offset, |
3e84f938 | 2961 | sizeof(efuse->ht40_max_power_offset)); |
26f1fad2 | 2962 | memcpy(priv->ht20_max_power_offset, |
49594441 | 2963 | efuse->ht20_max_power_offset, |
3e84f938 | 2964 | sizeof(efuse->ht20_max_power_offset)); |
26f1fad2 JS |
2965 | |
2966 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", | |
49594441 | 2967 | efuse->vendor_name); |
26f1fad2 | 2968 | dev_info(&priv->udev->dev, "Product: %.20s\n", |
49594441 | 2969 | efuse->device_name); |
26f1fad2 | 2970 | |
49594441 | 2971 | if (efuse->rf_regulatory & 0x20) { |
26f1fad2 JS |
2972 | sprintf(priv->chip_name, "8188RU"); |
2973 | priv->hi_pa = 1; | |
2974 | } | |
2975 | ||
2976 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { | |
2977 | unsigned char *raw = priv->efuse_wifi.raw; | |
2978 | ||
2979 | dev_info(&priv->udev->dev, | |
2980 | "%s: dumping efuse (0x%02zx bytes):\n", | |
2981 | __func__, sizeof(struct rtl8192cu_efuse)); | |
2982 | for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) { | |
2983 | dev_info(&priv->udev->dev, "%02x: " | |
2984 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", i, | |
2985 | raw[i], raw[i + 1], raw[i + 2], | |
2986 | raw[i + 3], raw[i + 4], raw[i + 5], | |
2987 | raw[i + 6], raw[i + 7]); | |
2988 | } | |
2989 | } | |
2990 | return 0; | |
2991 | } | |
2992 | ||
c0963772 KV |
2993 | #endif |
2994 | ||
3307d840 JS |
2995 | static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) |
2996 | { | |
b7dda34d | 2997 | struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; |
3307d840 JS |
2998 | int i; |
2999 | ||
b7dda34d | 3000 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
3307d840 JS |
3001 | return -EINVAL; |
3002 | ||
b7dda34d | 3003 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
3307d840 | 3004 | |
9e24772a JS |
3005 | memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, |
3006 | sizeof(efuse->tx_power_index_A.cck_base)); | |
3007 | memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, | |
3008 | sizeof(efuse->tx_power_index_B.cck_base)); | |
3009 | ||
3010 | memcpy(priv->ht40_1s_tx_power_index_A, | |
3011 | efuse->tx_power_index_A.ht40_base, | |
3012 | sizeof(efuse->tx_power_index_A.ht40_base)); | |
3013 | memcpy(priv->ht40_1s_tx_power_index_B, | |
3014 | efuse->tx_power_index_B.ht40_base, | |
3015 | sizeof(efuse->tx_power_index_B.ht40_base)); | |
3016 | ||
3017 | priv->ht20_tx_power_diff[0].a = | |
3018 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; | |
3019 | priv->ht20_tx_power_diff[0].b = | |
3020 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; | |
3021 | ||
3022 | priv->ht40_tx_power_diff[0].a = 0; | |
3023 | priv->ht40_tx_power_diff[0].b = 0; | |
3024 | ||
3025 | for (i = 1; i < RTL8723B_TX_COUNT; i++) { | |
3026 | priv->ofdm_tx_power_diff[i].a = | |
3027 | efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; | |
3028 | priv->ofdm_tx_power_diff[i].b = | |
3029 | efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; | |
3030 | ||
3031 | priv->ht20_tx_power_diff[i].a = | |
3032 | efuse->tx_power_index_A.pwr_diff[i - 1].ht20; | |
3033 | priv->ht20_tx_power_diff[i].b = | |
3034 | efuse->tx_power_index_B.pwr_diff[i - 1].ht20; | |
3035 | ||
3036 | priv->ht40_tx_power_diff[i].a = | |
3037 | efuse->tx_power_index_A.pwr_diff[i - 1].ht40; | |
3038 | priv->ht40_tx_power_diff[i].b = | |
3039 | efuse->tx_power_index_B.pwr_diff[i - 1].ht40; | |
3040 | } | |
3041 | ||
4ef22eb9 JS |
3042 | priv->has_xtalk = 1; |
3043 | priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; | |
3044 | ||
b7dda34d JS |
3045 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); |
3046 | dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name); | |
3047 | dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial); | |
3307d840 JS |
3048 | |
3049 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { | |
3050 | unsigned char *raw = priv->efuse_wifi.raw; | |
3051 | ||
3052 | dev_info(&priv->udev->dev, | |
3053 | "%s: dumping efuse (0x%02zx bytes):\n", | |
3054 | __func__, sizeof(struct rtl8192eu_efuse)); | |
3055 | for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) { | |
3056 | dev_info(&priv->udev->dev, "%02x: " | |
3057 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", i, | |
3058 | raw[i], raw[i + 1], raw[i + 2], | |
3059 | raw[i + 3], raw[i + 4], raw[i + 5], | |
3060 | raw[i + 6], raw[i + 7]); | |
3061 | } | |
3062 | } | |
ccfe1e85 JS |
3063 | /* |
3064 | * Temporarily disable 8192eu support | |
3065 | */ | |
3066 | return -EINVAL; | |
0e5d435a | 3067 | return 0; |
3307d840 JS |
3068 | } |
3069 | ||
26f1fad2 JS |
3070 | static int |
3071 | rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) | |
3072 | { | |
3073 | int i; | |
3074 | u8 val8; | |
3075 | u32 val32; | |
3076 | ||
3077 | /* Write Address */ | |
3078 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); | |
3079 | val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); | |
3080 | val8 &= 0xfc; | |
3081 | val8 |= (offset >> 8) & 0x03; | |
3082 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); | |
3083 | ||
3084 | val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); | |
3085 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); | |
3086 | ||
3087 | /* Poll for data read */ | |
3088 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); | |
3089 | for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { | |
3090 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); | |
3091 | if (val32 & BIT(31)) | |
3092 | break; | |
3093 | } | |
3094 | ||
3095 | if (i == RTL8XXXU_MAX_REG_POLL) | |
3096 | return -EIO; | |
3097 | ||
3098 | udelay(50); | |
3099 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); | |
3100 | ||
3101 | *data = val32 & 0xff; | |
3102 | return 0; | |
3103 | } | |
3104 | ||
3105 | static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) | |
3106 | { | |
3107 | struct device *dev = &priv->udev->dev; | |
3108 | int i, ret = 0; | |
3109 | u8 val8, word_mask, header, extheader; | |
3110 | u16 val16, efuse_addr, offset; | |
3111 | u32 val32; | |
3112 | ||
3113 | val16 = rtl8xxxu_read16(priv, REG_9346CR); | |
3114 | if (val16 & EEPROM_ENABLE) | |
3115 | priv->has_eeprom = 1; | |
3116 | if (val16 & EEPROM_BOOT) | |
3117 | priv->boot_eeprom = 1; | |
3118 | ||
38451998 JS |
3119 | if (priv->is_multi_func) { |
3120 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); | |
3121 | val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; | |
3122 | rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); | |
3123 | } | |
26f1fad2 JS |
3124 | |
3125 | dev_dbg(dev, "Booting from %s\n", | |
3126 | priv->boot_eeprom ? "EEPROM" : "EFUSE"); | |
3127 | ||
3128 | rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); | |
3129 | ||
3130 | /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ | |
3131 | val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); | |
3132 | if (!(val16 & SYS_ISO_PWC_EV12V)) { | |
3133 | val16 |= SYS_ISO_PWC_EV12V; | |
3134 | rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); | |
3135 | } | |
3136 | /* Reset: 0x0000[28], default valid */ | |
3137 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
3138 | if (!(val16 & SYS_FUNC_ELDR)) { | |
3139 | val16 |= SYS_FUNC_ELDR; | |
3140 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
3141 | } | |
3142 | ||
3143 | /* | |
3144 | * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid | |
3145 | */ | |
3146 | val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); | |
3147 | if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { | |
3148 | val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); | |
3149 | rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); | |
3150 | } | |
3151 | ||
3152 | /* Default value is 0xff */ | |
3307d840 | 3153 | memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); |
26f1fad2 JS |
3154 | |
3155 | efuse_addr = 0; | |
3156 | while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { | |
f6c47702 JS |
3157 | u16 map_addr; |
3158 | ||
26f1fad2 JS |
3159 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); |
3160 | if (ret || header == 0xff) | |
3161 | goto exit; | |
3162 | ||
3163 | if ((header & 0x1f) == 0x0f) { /* extended header */ | |
3164 | offset = (header & 0xe0) >> 5; | |
3165 | ||
3166 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, | |
3167 | &extheader); | |
3168 | if (ret) | |
3169 | goto exit; | |
3170 | /* All words disabled */ | |
3171 | if ((extheader & 0x0f) == 0x0f) | |
3172 | continue; | |
3173 | ||
3174 | offset |= ((extheader & 0xf0) >> 1); | |
3175 | word_mask = extheader & 0x0f; | |
3176 | } else { | |
3177 | offset = (header >> 4) & 0x0f; | |
3178 | word_mask = header & 0x0f; | |
3179 | } | |
3180 | ||
f6c47702 JS |
3181 | /* Get word enable value from PG header */ |
3182 | ||
3183 | /* We have 8 bits to indicate validity */ | |
3184 | map_addr = offset * 8; | |
3185 | if (map_addr >= EFUSE_MAP_LEN) { | |
3186 | dev_warn(dev, "%s: Illegal map_addr (%04x), " | |
3187 | "efuse corrupt!\n", | |
3188 | __func__, map_addr); | |
26f1fad2 JS |
3189 | ret = -EINVAL; |
3190 | goto exit; | |
3191 | } | |
f6c47702 JS |
3192 | for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { |
3193 | /* Check word enable condition in the section */ | |
32a39dd4 | 3194 | if (word_mask & BIT(i)) { |
f6c47702 | 3195 | map_addr += 2; |
32a39dd4 JS |
3196 | continue; |
3197 | } | |
3198 | ||
3199 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); | |
3200 | if (ret) | |
3201 | goto exit; | |
3202 | priv->efuse_wifi.raw[map_addr++] = val8; | |
3203 | ||
3204 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); | |
3205 | if (ret) | |
3206 | goto exit; | |
3207 | priv->efuse_wifi.raw[map_addr++] = val8; | |
f6c47702 | 3208 | } |
26f1fad2 JS |
3209 | } |
3210 | ||
3211 | exit: | |
3212 | rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); | |
3213 | ||
3214 | return ret; | |
3215 | } | |
3216 | ||
d48fe60e JS |
3217 | static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) |
3218 | { | |
3219 | u8 val8; | |
3220 | u16 sys_func; | |
3221 | ||
3222 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); | |
53b381c4 | 3223 | val8 &= ~BIT(0); |
d48fe60e | 3224 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
7d4ccb8b | 3225 | |
d48fe60e JS |
3226 | sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
3227 | sys_func &= ~SYS_FUNC_CPU_ENABLE; | |
3228 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); | |
7d4ccb8b | 3229 | |
d48fe60e | 3230 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
53b381c4 | 3231 | val8 |= BIT(0); |
d48fe60e | 3232 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
7d4ccb8b JS |
3233 | |
3234 | sys_func |= SYS_FUNC_CPU_ENABLE; | |
3235 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); | |
3236 | } | |
3237 | ||
3238 | static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) | |
3239 | { | |
3240 | u8 val8; | |
3241 | u16 sys_func; | |
3242 | ||
3243 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); | |
3244 | val8 &= ~BIT(1); | |
3245 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); | |
3246 | ||
3247 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); | |
3248 | val8 &= ~BIT(0); | |
3249 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); | |
3250 | ||
3251 | sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
3252 | sys_func &= ~SYS_FUNC_CPU_ENABLE; | |
3253 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); | |
3254 | ||
3255 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); | |
3256 | val8 &= ~BIT(1); | |
3257 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); | |
3258 | ||
3259 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); | |
3260 | val8 |= BIT(0); | |
3261 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); | |
3262 | ||
d48fe60e JS |
3263 | sys_func |= SYS_FUNC_CPU_ENABLE; |
3264 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); | |
3265 | } | |
3266 | ||
26f1fad2 JS |
3267 | static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) |
3268 | { | |
3269 | struct device *dev = &priv->udev->dev; | |
3270 | int ret = 0, i; | |
3271 | u32 val32; | |
3272 | ||
3273 | /* Poll checksum report */ | |
3274 | for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { | |
3275 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); | |
3276 | if (val32 & MCU_FW_DL_CSUM_REPORT) | |
3277 | break; | |
3278 | } | |
3279 | ||
3280 | if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { | |
3281 | dev_warn(dev, "Firmware checksum poll timed out\n"); | |
3282 | ret = -EAGAIN; | |
3283 | goto exit; | |
3284 | } | |
3285 | ||
3286 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); | |
3287 | val32 |= MCU_FW_DL_READY; | |
3288 | val32 &= ~MCU_WINT_INIT_READY; | |
3289 | rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); | |
3290 | ||
d48fe60e JS |
3291 | /* |
3292 | * Reset the 8051 in order for the firmware to start running, | |
3293 | * otherwise it won't come up on the 8192eu | |
3294 | */ | |
7d4ccb8b | 3295 | priv->fops->reset_8051(priv); |
d48fe60e | 3296 | |
26f1fad2 JS |
3297 | /* Wait for firmware to become ready */ |
3298 | for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { | |
3299 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); | |
3300 | if (val32 & MCU_WINT_INIT_READY) | |
3301 | break; | |
3302 | ||
3303 | udelay(100); | |
3304 | } | |
3305 | ||
3306 | if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { | |
3307 | dev_warn(dev, "Firmware failed to start\n"); | |
3308 | ret = -EAGAIN; | |
3309 | goto exit; | |
3310 | } | |
3311 | ||
3a4be6a0 JS |
3312 | /* |
3313 | * Init H2C command | |
3314 | */ | |
ba17d824 | 3315 | if (priv->rtl_chip == RTL8723B) |
3a4be6a0 | 3316 | rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); |
26f1fad2 JS |
3317 | exit: |
3318 | return ret; | |
3319 | } | |
3320 | ||
3321 | static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) | |
3322 | { | |
3323 | int pages, remainder, i, ret; | |
d48fe60e | 3324 | u8 val8; |
26f1fad2 JS |
3325 | u16 val16; |
3326 | u32 val32; | |
3327 | u8 *fwptr; | |
3328 | ||
3329 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); | |
3330 | val8 |= 4; | |
3331 | rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); | |
3332 | ||
3333 | /* 8051 enable */ | |
3334 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
43154f6f JS |
3335 | val16 |= SYS_FUNC_CPU_ENABLE; |
3336 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
26f1fad2 | 3337 | |
216202ae JS |
3338 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); |
3339 | if (val8 & MCU_FW_RAM_SEL) { | |
3340 | pr_info("do the RAM reset\n"); | |
3341 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); | |
7d4ccb8b | 3342 | priv->fops->reset_8051(priv); |
216202ae JS |
3343 | } |
3344 | ||
26f1fad2 JS |
3345 | /* MCU firmware download enable */ |
3346 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); | |
ef1c0499 JS |
3347 | val8 |= MCU_FW_DL_ENABLE; |
3348 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); | |
26f1fad2 JS |
3349 | |
3350 | /* 8051 reset */ | |
3351 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); | |
ef1c0499 JS |
3352 | val32 &= ~BIT(19); |
3353 | rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); | |
26f1fad2 JS |
3354 | |
3355 | /* Reset firmware download checksum */ | |
3356 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); | |
ef1c0499 JS |
3357 | val8 |= MCU_FW_DL_CSUM_REPORT; |
3358 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); | |
26f1fad2 JS |
3359 | |
3360 | pages = priv->fw_size / RTL_FW_PAGE_SIZE; | |
3361 | remainder = priv->fw_size % RTL_FW_PAGE_SIZE; | |
3362 | ||
3363 | fwptr = priv->fw_data->data; | |
3364 | ||
3365 | for (i = 0; i < pages; i++) { | |
3366 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; | |
ef1c0499 JS |
3367 | val8 |= i; |
3368 | rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); | |
26f1fad2 JS |
3369 | |
3370 | ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, | |
3371 | fwptr, RTL_FW_PAGE_SIZE); | |
3372 | if (ret != RTL_FW_PAGE_SIZE) { | |
3373 | ret = -EAGAIN; | |
3374 | goto fw_abort; | |
3375 | } | |
3376 | ||
3377 | fwptr += RTL_FW_PAGE_SIZE; | |
3378 | } | |
3379 | ||
3380 | if (remainder) { | |
3381 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; | |
ef1c0499 JS |
3382 | val8 |= i; |
3383 | rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); | |
26f1fad2 JS |
3384 | ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, |
3385 | fwptr, remainder); | |
3386 | if (ret != remainder) { | |
3387 | ret = -EAGAIN; | |
3388 | goto fw_abort; | |
3389 | } | |
3390 | } | |
3391 | ||
3392 | ret = 0; | |
3393 | fw_abort: | |
3394 | /* MCU firmware download disable */ | |
3395 | val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL); | |
ef1c0499 JS |
3396 | val16 &= ~MCU_FW_DL_ENABLE; |
3397 | rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16); | |
26f1fad2 JS |
3398 | |
3399 | return ret; | |
3400 | } | |
3401 | ||
3402 | static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name) | |
3403 | { | |
3404 | struct device *dev = &priv->udev->dev; | |
3405 | const struct firmware *fw; | |
3406 | int ret = 0; | |
3407 | u16 signature; | |
3408 | ||
3409 | dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); | |
3410 | if (request_firmware(&fw, fw_name, &priv->udev->dev)) { | |
3411 | dev_warn(dev, "request_firmware(%s) failed\n", fw_name); | |
3412 | ret = -EAGAIN; | |
3413 | goto exit; | |
3414 | } | |
3415 | if (!fw) { | |
3416 | dev_warn(dev, "Firmware data not available\n"); | |
3417 | ret = -EINVAL; | |
3418 | goto exit; | |
3419 | } | |
3420 | ||
3421 | priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); | |
98e27cbd TK |
3422 | if (!priv->fw_data) { |
3423 | ret = -ENOMEM; | |
3424 | goto exit; | |
3425 | } | |
26f1fad2 JS |
3426 | priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); |
3427 | ||
3428 | signature = le16_to_cpu(priv->fw_data->signature); | |
3429 | switch (signature & 0xfff0) { | |
0e5d435a | 3430 | case 0x92e0: |
26f1fad2 JS |
3431 | case 0x92c0: |
3432 | case 0x88c0: | |
35a741fe | 3433 | case 0x5300: |
26f1fad2 JS |
3434 | case 0x2300: |
3435 | break; | |
3436 | default: | |
3437 | ret = -EINVAL; | |
3438 | dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", | |
3439 | __func__, signature); | |
3440 | } | |
3441 | ||
3442 | dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", | |
3443 | le16_to_cpu(priv->fw_data->major_version), | |
3444 | priv->fw_data->minor_version, signature); | |
3445 | ||
3446 | exit: | |
3447 | release_firmware(fw); | |
3448 | return ret; | |
3449 | } | |
3450 | ||
3451 | static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv) | |
3452 | { | |
3453 | char *fw_name; | |
3454 | int ret; | |
3455 | ||
3456 | switch (priv->chip_cut) { | |
3457 | case 0: | |
3458 | fw_name = "rtlwifi/rtl8723aufw_A.bin"; | |
3459 | break; | |
3460 | case 1: | |
3461 | if (priv->enable_bluetooth) | |
3462 | fw_name = "rtlwifi/rtl8723aufw_B.bin"; | |
3463 | else | |
3464 | fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin"; | |
3465 | ||
3466 | break; | |
3467 | default: | |
3468 | return -EINVAL; | |
3469 | } | |
3470 | ||
3471 | ret = rtl8xxxu_load_firmware(priv, fw_name); | |
3472 | return ret; | |
3473 | } | |
3474 | ||
35a741fe JS |
3475 | static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) |
3476 | { | |
3477 | char *fw_name; | |
3478 | int ret; | |
3479 | ||
3480 | if (priv->enable_bluetooth) | |
3481 | fw_name = "rtlwifi/rtl8723bu_bt.bin"; | |
3482 | else | |
3483 | fw_name = "rtlwifi/rtl8723bu_nic.bin"; | |
3484 | ||
3485 | ret = rtl8xxxu_load_firmware(priv, fw_name); | |
3486 | return ret; | |
3487 | } | |
3488 | ||
c0963772 KV |
3489 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
3490 | ||
26f1fad2 JS |
3491 | static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv) |
3492 | { | |
3493 | char *fw_name; | |
3494 | int ret; | |
3495 | ||
3496 | if (!priv->vendor_umc) | |
3497 | fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; | |
ba17d824 | 3498 | else if (priv->chip_cut || priv->rtl_chip == RTL8192C) |
26f1fad2 JS |
3499 | fw_name = "rtlwifi/rtl8192cufw_B.bin"; |
3500 | else | |
3501 | fw_name = "rtlwifi/rtl8192cufw_A.bin"; | |
3502 | ||
3503 | ret = rtl8xxxu_load_firmware(priv, fw_name); | |
3504 | ||
3505 | return ret; | |
3506 | } | |
3507 | ||
c0963772 KV |
3508 | #endif |
3509 | ||
3307d840 JS |
3510 | static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) |
3511 | { | |
3512 | char *fw_name; | |
3513 | int ret; | |
3514 | ||
0e5d435a | 3515 | fw_name = "rtlwifi/rtl8192eu_nic.bin"; |
3307d840 JS |
3516 | |
3517 | ret = rtl8xxxu_load_firmware(priv, fw_name); | |
3518 | ||
3519 | return ret; | |
3520 | } | |
3521 | ||
26f1fad2 JS |
3522 | static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) |
3523 | { | |
3524 | u16 val16; | |
3525 | int i = 100; | |
3526 | ||
3527 | /* Inform 8051 to perform reset */ | |
3528 | rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); | |
3529 | ||
3530 | for (i = 100; i > 0; i--) { | |
3531 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
3532 | ||
3533 | if (!(val16 & SYS_FUNC_CPU_ENABLE)) { | |
3534 | dev_dbg(&priv->udev->dev, | |
3535 | "%s: Firmware self reset success!\n", __func__); | |
3536 | break; | |
3537 | } | |
3538 | udelay(50); | |
3539 | } | |
3540 | ||
3541 | if (!i) { | |
3542 | /* Force firmware reset */ | |
3543 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
3544 | val16 &= ~SYS_FUNC_CPU_ENABLE; | |
3545 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
3546 | } | |
3547 | } | |
3548 | ||
f0d9f5e9 JS |
3549 | static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) |
3550 | { | |
3551 | u32 val32; | |
3552 | ||
70bc1e24 | 3553 | val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); |
f0d9f5e9 | 3554 | val32 &= ~(BIT(20) | BIT(24)); |
70bc1e24 | 3555 | rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); |
f0d9f5e9 JS |
3556 | |
3557 | val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); | |
3558 | val32 &= ~BIT(4); | |
3a4be6a0 JS |
3559 | rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); |
3560 | ||
3561 | val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); | |
f0d9f5e9 JS |
3562 | val32 |= BIT(3); |
3563 | rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); | |
3564 | ||
3565 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); | |
f0d9f5e9 JS |
3566 | val32 |= BIT(24); |
3567 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); | |
3568 | ||
3a4be6a0 JS |
3569 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
3570 | val32 &= ~BIT(23); | |
3571 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); | |
3572 | ||
120e627f | 3573 | val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); |
f0d9f5e9 | 3574 | val32 |= (BIT(0) | BIT(1)); |
120e627f | 3575 | rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); |
f0d9f5e9 | 3576 | |
59b74397 | 3577 | val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); |
f0d9f5e9 JS |
3578 | val32 &= 0xffffff00; |
3579 | val32 |= 0x77; | |
59b74397 | 3580 | rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); |
3a4be6a0 JS |
3581 | |
3582 | val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); | |
3583 | val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; | |
3584 | rtl8xxxu_write32(priv, REG_PWR_DATA, val32); | |
f0d9f5e9 JS |
3585 | } |
3586 | ||
26f1fad2 | 3587 | static int |
c606e662 | 3588 | rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) |
26f1fad2 | 3589 | { |
c606e662 | 3590 | struct rtl8xxxu_reg8val *array = priv->fops->mactable; |
26f1fad2 JS |
3591 | int i, ret; |
3592 | u16 reg; | |
3593 | u8 val; | |
3594 | ||
3595 | for (i = 0; ; i++) { | |
3596 | reg = array[i].reg; | |
3597 | val = array[i].val; | |
3598 | ||
3599 | if (reg == 0xffff && val == 0xff) | |
3600 | break; | |
3601 | ||
3602 | ret = rtl8xxxu_write8(priv, reg, val); | |
3603 | if (ret != 1) { | |
3604 | dev_warn(&priv->udev->dev, | |
c606e662 JS |
3605 | "Failed to initialize MAC " |
3606 | "(reg: %04x, val %02x)\n", reg, val); | |
26f1fad2 JS |
3607 | return -EAGAIN; |
3608 | } | |
3609 | } | |
3610 | ||
8a59485c | 3611 | if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) |
8baf670b | 3612 | rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); |
26f1fad2 JS |
3613 | |
3614 | return 0; | |
3615 | } | |
3616 | ||
3617 | static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, | |
3618 | struct rtl8xxxu_reg32val *array) | |
3619 | { | |
3620 | int i, ret; | |
3621 | u16 reg; | |
3622 | u32 val; | |
3623 | ||
3624 | for (i = 0; ; i++) { | |
3625 | reg = array[i].reg; | |
3626 | val = array[i].val; | |
3627 | ||
3628 | if (reg == 0xffff && val == 0xffffffff) | |
3629 | break; | |
3630 | ||
3631 | ret = rtl8xxxu_write32(priv, reg, val); | |
3632 | if (ret != sizeof(val)) { | |
3633 | dev_warn(&priv->udev->dev, | |
3634 | "Failed to initialize PHY\n"); | |
3635 | return -EAGAIN; | |
3636 | } | |
3637 | udelay(1); | |
3638 | } | |
3639 | ||
3640 | return 0; | |
3641 | } | |
3642 | ||
3643 | /* | |
3644 | * Most of this is black magic retrieved from the old rtl8723au driver | |
3645 | */ | |
3646 | static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) | |
3647 | { | |
3648 | u8 val8, ldoa15, ldov12d, lpldo, ldohci12; | |
04313eb4 | 3649 | u16 val16; |
26f1fad2 JS |
3650 | u32 val32; |
3651 | ||
3652 | /* | |
3653 | * Todo: The vendor driver maintains a table of PHY register | |
3654 | * addresses, which is initialized here. Do we need this? | |
3655 | */ | |
3656 | ||
ba17d824 | 3657 | if (priv->rtl_chip == RTL8723B) { |
8baf670b JS |
3658 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
3659 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | | |
3660 | SYS_FUNC_DIO_RF; | |
3661 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
3662 | ||
3ca7b32c | 3663 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
444004bd JS |
3664 | } else if (priv->rtl_chip == RTL8192E) { |
3665 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
3666 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | | |
3667 | SYS_FUNC_DIO_RF; | |
3668 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
3ca7b32c JS |
3669 | } else { |
3670 | val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); | |
3671 | udelay(2); | |
3672 | val8 |= AFE_PLL_320_ENABLE; | |
3673 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); | |
3674 | udelay(2); | |
3675 | ||
3676 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); | |
3677 | udelay(2); | |
26f1fad2 | 3678 | |
8baf670b JS |
3679 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
3680 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; | |
3681 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
3682 | } | |
26f1fad2 | 3683 | |
2ca73dc7 | 3684 | if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) { |
04313eb4 JS |
3685 | /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */ |
3686 | val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); | |
3687 | val32 &= ~AFE_XTAL_RF_GATE; | |
3688 | if (priv->has_bluetooth) | |
3689 | val32 &= ~AFE_XTAL_BT_GATE; | |
3690 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); | |
3691 | } | |
26f1fad2 JS |
3692 | |
3693 | /* 6. 0x1f[7:0] = 0x07 */ | |
3694 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; | |
3695 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); | |
3696 | ||
abd71bdb | 3697 | if (priv->rtl_chip == RTL8723B) { |
8baf670b JS |
3698 | /* |
3699 | * Why? | |
3700 | */ | |
3701 | rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); | |
3702 | rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); | |
36c32588 | 3703 | rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); |
ae14c5d2 JS |
3704 | } else if (priv->rtl_chip == RTL8192E) { |
3705 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
3706 | val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF | | |
3707 | SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB); | |
3708 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
3709 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; | |
3710 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); | |
3711 | rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); | |
abd71bdb JS |
3712 | } else if (priv->hi_pa) |
3713 | rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); | |
3714 | else if (priv->tx_paths == 2) | |
3715 | rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); | |
3716 | else | |
26f1fad2 JS |
3717 | rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); |
3718 | ||
ba17d824 | 3719 | if (priv->rtl_chip == RTL8188C && priv->hi_pa && |
26f1fad2 JS |
3720 | priv->vendor_umc && priv->chip_cut == 1) |
3721 | rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); | |
3722 | ||
3723 | if (priv->tx_paths == 1 && priv->rx_paths == 2) { | |
3724 | /* | |
3725 | * For 1T2R boards, patch the registers. | |
3726 | * | |
3727 | * It looks like 8191/2 1T2R boards use path B for TX | |
3728 | */ | |
3729 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); | |
3730 | val32 &= ~(BIT(0) | BIT(1)); | |
3731 | val32 |= BIT(1); | |
3732 | rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); | |
3733 | ||
3734 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); | |
3735 | val32 &= ~0x300033; | |
3736 | val32 |= 0x200022; | |
3737 | rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); | |
3738 | ||
3739 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); | |
3740 | val32 &= 0xff000000; | |
3741 | val32 |= 0x45000000; | |
3742 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); | |
3743 | ||
3744 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); | |
3745 | val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); | |
3746 | val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | | |
3747 | OFDM_RF_PATH_TX_B); | |
3748 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); | |
3749 | ||
3750 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); | |
3751 | val32 &= ~(BIT(4) | BIT(5)); | |
3752 | val32 |= BIT(4); | |
3753 | rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); | |
3754 | ||
3755 | val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); | |
3756 | val32 &= ~(BIT(27) | BIT(26)); | |
3757 | val32 |= BIT(27); | |
3758 | rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); | |
3759 | ||
3760 | val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); | |
3761 | val32 &= ~(BIT(27) | BIT(26)); | |
3762 | val32 |= BIT(27); | |
3763 | rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); | |
3764 | ||
3765 | val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); | |
3766 | val32 &= ~(BIT(27) | BIT(26)); | |
3767 | val32 |= BIT(27); | |
3768 | rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); | |
3769 | ||
3770 | val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); | |
3771 | val32 &= ~(BIT(27) | BIT(26)); | |
3772 | val32 |= BIT(27); | |
3773 | rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); | |
3774 | ||
3775 | val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); | |
3776 | val32 &= ~(BIT(27) | BIT(26)); | |
3777 | val32 |= BIT(27); | |
3778 | rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); | |
3779 | } | |
3780 | ||
ba17d824 | 3781 | if (priv->rtl_chip == RTL8723B) |
b9f498e1 | 3782 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); |
e293278d JS |
3783 | else if (priv->rtl_chip == RTL8192E) { |
3784 | if (priv->hi_pa) | |
3785 | rtl8xxxu_init_phy_regs(priv, | |
3786 | rtl8xxx_agc_8192eu_highpa_table); | |
3787 | else | |
3788 | rtl8xxxu_init_phy_regs(priv, | |
3789 | rtl8xxx_agc_8192eu_std_table); | |
3790 | } else if (priv->hi_pa) | |
26f1fad2 JS |
3791 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); |
3792 | else | |
3793 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); | |
3794 | ||
4ef22eb9 | 3795 | if (priv->has_xtalk) { |
26f1fad2 JS |
3796 | val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); |
3797 | ||
4ef22eb9 | 3798 | val8 = priv->xtalk; |
26f1fad2 JS |
3799 | val32 &= 0xff000fff; |
3800 | val32 |= ((val8 | (val8 << 6)) << 12); | |
3801 | ||
3802 | rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); | |
3803 | } | |
3804 | ||
a069caa3 | 3805 | if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) { |
a0e262bc JS |
3806 | ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; |
3807 | ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); | |
3808 | ldohci12 = 0x57; | |
3809 | lpldo = 1; | |
3810 | val32 = (lpldo << 24) | (ldohci12 << 16) | | |
3811 | (ldov12d << 8) | ldoa15; | |
3812 | ||
3813 | rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); | |
3814 | } | |
26f1fad2 | 3815 | |
8a59485c JS |
3816 | if (priv->rtl_chip == RTL8192E) |
3817 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); | |
3818 | ||
26f1fad2 JS |
3819 | return 0; |
3820 | } | |
3821 | ||
3822 | static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, | |
3823 | struct rtl8xxxu_rfregval *array, | |
3824 | enum rtl8xxxu_rfpath path) | |
3825 | { | |
3826 | int i, ret; | |
3827 | u8 reg; | |
3828 | u32 val; | |
3829 | ||
3830 | for (i = 0; ; i++) { | |
3831 | reg = array[i].reg; | |
3832 | val = array[i].val; | |
3833 | ||
3834 | if (reg == 0xff && val == 0xffffffff) | |
3835 | break; | |
3836 | ||
3837 | switch (reg) { | |
3838 | case 0xfe: | |
3839 | msleep(50); | |
3840 | continue; | |
3841 | case 0xfd: | |
3842 | mdelay(5); | |
3843 | continue; | |
3844 | case 0xfc: | |
3845 | mdelay(1); | |
3846 | continue; | |
3847 | case 0xfb: | |
3848 | udelay(50); | |
3849 | continue; | |
3850 | case 0xfa: | |
3851 | udelay(5); | |
3852 | continue; | |
3853 | case 0xf9: | |
3854 | udelay(1); | |
3855 | continue; | |
3856 | } | |
3857 | ||
26f1fad2 JS |
3858 | ret = rtl8xxxu_write_rfreg(priv, path, reg, val); |
3859 | if (ret) { | |
3860 | dev_warn(&priv->udev->dev, | |
3861 | "Failed to initialize RF\n"); | |
3862 | return -EAGAIN; | |
3863 | } | |
3864 | udelay(1); | |
3865 | } | |
3866 | ||
3867 | return 0; | |
3868 | } | |
3869 | ||
3870 | static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, | |
3871 | struct rtl8xxxu_rfregval *table, | |
3872 | enum rtl8xxxu_rfpath path) | |
3873 | { | |
3874 | u32 val32; | |
3875 | u16 val16, rfsi_rfenv; | |
3876 | u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; | |
3877 | ||
3878 | switch (path) { | |
3879 | case RF_A: | |
3880 | reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; | |
3881 | reg_int_oe = REG_FPGA0_XA_RF_INT_OE; | |
3882 | reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; | |
3883 | break; | |
3884 | case RF_B: | |
3885 | reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; | |
3886 | reg_int_oe = REG_FPGA0_XB_RF_INT_OE; | |
3887 | reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; | |
3888 | break; | |
3889 | default: | |
3890 | dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", | |
3891 | __func__, path + 'A'); | |
3892 | return -EINVAL; | |
3893 | } | |
3894 | /* For path B, use XB */ | |
3895 | rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); | |
3896 | rfsi_rfenv &= FPGA0_RF_RFENV; | |
3897 | ||
3898 | /* | |
3899 | * These two we might be able to optimize into one | |
3900 | */ | |
3901 | val32 = rtl8xxxu_read32(priv, reg_int_oe); | |
3902 | val32 |= BIT(20); /* 0x10 << 16 */ | |
3903 | rtl8xxxu_write32(priv, reg_int_oe, val32); | |
3904 | udelay(1); | |
3905 | ||
3906 | val32 = rtl8xxxu_read32(priv, reg_int_oe); | |
3907 | val32 |= BIT(4); | |
3908 | rtl8xxxu_write32(priv, reg_int_oe, val32); | |
3909 | udelay(1); | |
3910 | ||
3911 | /* | |
3912 | * These two we might be able to optimize into one | |
3913 | */ | |
3914 | val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); | |
3915 | val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; | |
3916 | rtl8xxxu_write32(priv, reg_hssi_parm2, val32); | |
3917 | udelay(1); | |
3918 | ||
3919 | val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); | |
3920 | val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; | |
3921 | rtl8xxxu_write32(priv, reg_hssi_parm2, val32); | |
3922 | udelay(1); | |
3923 | ||
3924 | rtl8xxxu_init_rf_regs(priv, table, path); | |
3925 | ||
3926 | /* For path B, use XB */ | |
3927 | val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); | |
3928 | val16 &= ~FPGA0_RF_RFENV; | |
3929 | val16 |= rfsi_rfenv; | |
3930 | rtl8xxxu_write16(priv, reg_sw_ctrl, val16); | |
3931 | ||
3932 | return 0; | |
3933 | } | |
3934 | ||
3935 | static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) | |
3936 | { | |
3937 | int ret = -EBUSY; | |
3938 | int count = 0; | |
3939 | u32 value; | |
3940 | ||
3941 | value = LLT_OP_WRITE | address << 8 | data; | |
3942 | ||
3943 | rtl8xxxu_write32(priv, REG_LLT_INIT, value); | |
3944 | ||
3945 | do { | |
3946 | value = rtl8xxxu_read32(priv, REG_LLT_INIT); | |
3947 | if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { | |
3948 | ret = 0; | |
3949 | break; | |
3950 | } | |
3951 | } while (count++ < 20); | |
3952 | ||
3953 | return ret; | |
3954 | } | |
3955 | ||
3956 | static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page) | |
3957 | { | |
3958 | int ret; | |
3959 | int i; | |
3960 | ||
3961 | for (i = 0; i < last_tx_page; i++) { | |
3962 | ret = rtl8xxxu_llt_write(priv, i, i + 1); | |
3963 | if (ret) | |
3964 | goto exit; | |
3965 | } | |
3966 | ||
3967 | ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); | |
3968 | if (ret) | |
3969 | goto exit; | |
3970 | ||
3971 | /* Mark remaining pages as a ring buffer */ | |
3972 | for (i = last_tx_page + 1; i < 0xff; i++) { | |
3973 | ret = rtl8xxxu_llt_write(priv, i, (i + 1)); | |
3974 | if (ret) | |
3975 | goto exit; | |
3976 | } | |
3977 | ||
3978 | /* Let last entry point to the start entry of ring buffer */ | |
3979 | ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1); | |
3980 | if (ret) | |
3981 | goto exit; | |
3982 | ||
3983 | exit: | |
3984 | return ret; | |
3985 | } | |
3986 | ||
74b99bed JS |
3987 | static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page) |
3988 | { | |
3989 | u32 val32; | |
3990 | int ret = 0; | |
3991 | int i; | |
3992 | ||
3993 | val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); | |
74b99bed JS |
3994 | val32 |= AUTO_LLT_INIT_LLT; |
3995 | rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); | |
3996 | ||
3997 | for (i = 500; i; i--) { | |
3998 | val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); | |
3999 | if (!(val32 & AUTO_LLT_INIT_LLT)) | |
4000 | break; | |
4001 | usleep_range(2, 4); | |
4002 | } | |
4003 | ||
4de24819 | 4004 | if (!i) { |
74b99bed JS |
4005 | ret = -EBUSY; |
4006 | dev_warn(&priv->udev->dev, "LLT table init failed\n"); | |
4007 | } | |
74b99bed JS |
4008 | |
4009 | return ret; | |
4010 | } | |
4011 | ||
26f1fad2 JS |
4012 | static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) |
4013 | { | |
4014 | u16 val16, hi, lo; | |
4015 | u16 hiq, mgq, bkq, beq, viq, voq; | |
4016 | int hip, mgp, bkp, bep, vip, vop; | |
4017 | int ret = 0; | |
4018 | ||
4019 | switch (priv->ep_tx_count) { | |
4020 | case 1: | |
4021 | if (priv->ep_tx_high_queue) { | |
4022 | hi = TRXDMA_QUEUE_HIGH; | |
4023 | } else if (priv->ep_tx_low_queue) { | |
4024 | hi = TRXDMA_QUEUE_LOW; | |
4025 | } else if (priv->ep_tx_normal_queue) { | |
4026 | hi = TRXDMA_QUEUE_NORMAL; | |
4027 | } else { | |
4028 | hi = 0; | |
4029 | ret = -EINVAL; | |
4030 | } | |
4031 | ||
4032 | hiq = hi; | |
4033 | mgq = hi; | |
4034 | bkq = hi; | |
4035 | beq = hi; | |
4036 | viq = hi; | |
4037 | voq = hi; | |
4038 | ||
4039 | hip = 0; | |
4040 | mgp = 0; | |
4041 | bkp = 0; | |
4042 | bep = 0; | |
4043 | vip = 0; | |
4044 | vop = 0; | |
4045 | break; | |
4046 | case 2: | |
4047 | if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { | |
4048 | hi = TRXDMA_QUEUE_HIGH; | |
4049 | lo = TRXDMA_QUEUE_LOW; | |
4050 | } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { | |
4051 | hi = TRXDMA_QUEUE_NORMAL; | |
4052 | lo = TRXDMA_QUEUE_LOW; | |
4053 | } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { | |
4054 | hi = TRXDMA_QUEUE_HIGH; | |
4055 | lo = TRXDMA_QUEUE_NORMAL; | |
4056 | } else { | |
4057 | ret = -EINVAL; | |
4058 | hi = 0; | |
4059 | lo = 0; | |
4060 | } | |
4061 | ||
4062 | hiq = hi; | |
4063 | mgq = hi; | |
4064 | bkq = lo; | |
4065 | beq = lo; | |
4066 | viq = hi; | |
4067 | voq = hi; | |
4068 | ||
4069 | hip = 0; | |
4070 | mgp = 0; | |
4071 | bkp = 1; | |
4072 | bep = 1; | |
4073 | vip = 0; | |
4074 | vop = 0; | |
4075 | break; | |
4076 | case 3: | |
4077 | beq = TRXDMA_QUEUE_LOW; | |
4078 | bkq = TRXDMA_QUEUE_LOW; | |
4079 | viq = TRXDMA_QUEUE_NORMAL; | |
4080 | voq = TRXDMA_QUEUE_HIGH; | |
4081 | mgq = TRXDMA_QUEUE_HIGH; | |
4082 | hiq = TRXDMA_QUEUE_HIGH; | |
4083 | ||
4084 | hip = hiq ^ 3; | |
4085 | mgp = mgq ^ 3; | |
4086 | bkp = bkq ^ 3; | |
4087 | bep = beq ^ 3; | |
4088 | vip = viq ^ 3; | |
4089 | vop = viq ^ 3; | |
4090 | break; | |
4091 | default: | |
4092 | ret = -EINVAL; | |
4093 | } | |
4094 | ||
4095 | /* | |
4096 | * None of the vendor drivers are configuring the beacon | |
4097 | * queue here .... why? | |
4098 | */ | |
4099 | if (!ret) { | |
4100 | val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); | |
4101 | val16 &= 0x7; | |
4102 | val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | | |
4103 | (viq << TRXDMA_CTRL_VIQ_SHIFT) | | |
4104 | (beq << TRXDMA_CTRL_BEQ_SHIFT) | | |
4105 | (bkq << TRXDMA_CTRL_BKQ_SHIFT) | | |
4106 | (mgq << TRXDMA_CTRL_MGQ_SHIFT) | | |
4107 | (hiq << TRXDMA_CTRL_HIQ_SHIFT); | |
4108 | rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); | |
4109 | ||
4110 | priv->pipe_out[TXDESC_QUEUE_VO] = | |
4111 | usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); | |
4112 | priv->pipe_out[TXDESC_QUEUE_VI] = | |
4113 | usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); | |
4114 | priv->pipe_out[TXDESC_QUEUE_BE] = | |
4115 | usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); | |
4116 | priv->pipe_out[TXDESC_QUEUE_BK] = | |
4117 | usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); | |
4118 | priv->pipe_out[TXDESC_QUEUE_BEACON] = | |
4119 | usb_sndbulkpipe(priv->udev, priv->out_ep[0]); | |
4120 | priv->pipe_out[TXDESC_QUEUE_MGNT] = | |
4121 | usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); | |
4122 | priv->pipe_out[TXDESC_QUEUE_HIGH] = | |
4123 | usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); | |
4124 | priv->pipe_out[TXDESC_QUEUE_CMD] = | |
4125 | usb_sndbulkpipe(priv->udev, priv->out_ep[0]); | |
4126 | } | |
4127 | ||
4128 | return ret; | |
4129 | } | |
4130 | ||
4131 | static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, | |
4132 | bool iqk_ok, int result[][8], | |
4133 | int candidate, bool tx_only) | |
4134 | { | |
4135 | u32 oldval, x, tx0_a, reg; | |
4136 | int y, tx0_c; | |
4137 | u32 val32; | |
4138 | ||
4139 | if (!iqk_ok) | |
4140 | return; | |
4141 | ||
4142 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); | |
4143 | oldval = val32 >> 22; | |
4144 | ||
4145 | x = result[candidate][0]; | |
4146 | if ((x & 0x00000200) != 0) | |
4147 | x = x | 0xfffffc00; | |
4148 | tx0_a = (x * oldval) >> 8; | |
4149 | ||
4150 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); | |
4151 | val32 &= ~0x3ff; | |
4152 | val32 |= tx0_a; | |
4153 | rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); | |
4154 | ||
4155 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); | |
4156 | val32 &= ~BIT(31); | |
4157 | if ((x * oldval >> 7) & 0x1) | |
4158 | val32 |= BIT(31); | |
4159 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); | |
4160 | ||
4161 | y = result[candidate][1]; | |
4162 | if ((y & 0x00000200) != 0) | |
4163 | y = y | 0xfffffc00; | |
4164 | tx0_c = (y * oldval) >> 8; | |
4165 | ||
4166 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); | |
4167 | val32 &= ~0xf0000000; | |
4168 | val32 |= (((tx0_c & 0x3c0) >> 6) << 28); | |
4169 | rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); | |
4170 | ||
4171 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); | |
4172 | val32 &= ~0x003f0000; | |
4173 | val32 |= ((tx0_c & 0x3f) << 16); | |
4174 | rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); | |
4175 | ||
4176 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); | |
4177 | val32 &= ~BIT(29); | |
4178 | if ((y * oldval >> 7) & 0x1) | |
4179 | val32 |= BIT(29); | |
4180 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); | |
4181 | ||
4182 | if (tx_only) { | |
4183 | dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); | |
4184 | return; | |
4185 | } | |
4186 | ||
4187 | reg = result[candidate][2]; | |
4188 | ||
4189 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); | |
4190 | val32 &= ~0x3ff; | |
4191 | val32 |= (reg & 0x3ff); | |
4192 | rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); | |
4193 | ||
4194 | reg = result[candidate][3] & 0x3F; | |
4195 | ||
4196 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); | |
4197 | val32 &= ~0xfc00; | |
4198 | val32 |= ((reg << 10) & 0xfc00); | |
4199 | rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); | |
4200 | ||
4201 | reg = (result[candidate][3] >> 6) & 0xF; | |
4202 | ||
4203 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); | |
4204 | val32 &= ~0xf0000000; | |
4205 | val32 |= (reg << 28); | |
4206 | rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); | |
4207 | } | |
4208 | ||
4209 | static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, | |
4210 | bool iqk_ok, int result[][8], | |
4211 | int candidate, bool tx_only) | |
4212 | { | |
4213 | u32 oldval, x, tx1_a, reg; | |
4214 | int y, tx1_c; | |
4215 | u32 val32; | |
4216 | ||
4217 | if (!iqk_ok) | |
4218 | return; | |
4219 | ||
4220 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); | |
4221 | oldval = val32 >> 22; | |
4222 | ||
4223 | x = result[candidate][4]; | |
4224 | if ((x & 0x00000200) != 0) | |
4225 | x = x | 0xfffffc00; | |
4226 | tx1_a = (x * oldval) >> 8; | |
4227 | ||
4228 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); | |
4229 | val32 &= ~0x3ff; | |
4230 | val32 |= tx1_a; | |
4231 | rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); | |
4232 | ||
4233 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); | |
4234 | val32 &= ~BIT(27); | |
4235 | if ((x * oldval >> 7) & 0x1) | |
4236 | val32 |= BIT(27); | |
4237 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); | |
4238 | ||
4239 | y = result[candidate][5]; | |
4240 | if ((y & 0x00000200) != 0) | |
4241 | y = y | 0xfffffc00; | |
4242 | tx1_c = (y * oldval) >> 8; | |
4243 | ||
4244 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); | |
4245 | val32 &= ~0xf0000000; | |
4246 | val32 |= (((tx1_c & 0x3c0) >> 6) << 28); | |
4247 | rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); | |
4248 | ||
4249 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); | |
4250 | val32 &= ~0x003f0000; | |
4251 | val32 |= ((tx1_c & 0x3f) << 16); | |
4252 | rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); | |
4253 | ||
4254 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); | |
4255 | val32 &= ~BIT(25); | |
4256 | if ((y * oldval >> 7) & 0x1) | |
4257 | val32 |= BIT(25); | |
4258 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); | |
4259 | ||
4260 | if (tx_only) { | |
4261 | dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); | |
4262 | return; | |
4263 | } | |
4264 | ||
4265 | reg = result[candidate][6]; | |
4266 | ||
4267 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); | |
4268 | val32 &= ~0x3ff; | |
4269 | val32 |= (reg & 0x3ff); | |
4270 | rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); | |
4271 | ||
4272 | reg = result[candidate][7] & 0x3f; | |
4273 | ||
4274 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); | |
4275 | val32 &= ~0xfc00; | |
4276 | val32 |= ((reg << 10) & 0xfc00); | |
4277 | rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); | |
4278 | ||
4279 | reg = (result[candidate][7] >> 6) & 0xf; | |
4280 | ||
4281 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); | |
4282 | val32 &= ~0x0000f000; | |
4283 | val32 |= (reg << 12); | |
4284 | rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); | |
4285 | } | |
4286 | ||
4287 | #define MAX_TOLERANCE 5 | |
4288 | ||
4289 | static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, | |
4290 | int result[][8], int c1, int c2) | |
4291 | { | |
4292 | u32 i, j, diff, simubitmap, bound = 0; | |
4293 | int candidate[2] = {-1, -1}; /* for path A and path B */ | |
4294 | bool retval = true; | |
4295 | ||
4296 | if (priv->tx_paths > 1) | |
4297 | bound = 8; | |
4298 | else | |
4299 | bound = 4; | |
4300 | ||
4301 | simubitmap = 0; | |
4302 | ||
4303 | for (i = 0; i < bound; i++) { | |
4304 | diff = (result[c1][i] > result[c2][i]) ? | |
4305 | (result[c1][i] - result[c2][i]) : | |
4306 | (result[c2][i] - result[c1][i]); | |
4307 | if (diff > MAX_TOLERANCE) { | |
4308 | if ((i == 2 || i == 6) && !simubitmap) { | |
4309 | if (result[c1][i] + result[c1][i + 1] == 0) | |
4310 | candidate[(i / 4)] = c2; | |
4311 | else if (result[c2][i] + result[c2][i + 1] == 0) | |
4312 | candidate[(i / 4)] = c1; | |
4313 | else | |
4314 | simubitmap = simubitmap | (1 << i); | |
4315 | } else { | |
4316 | simubitmap = simubitmap | (1 << i); | |
4317 | } | |
4318 | } | |
4319 | } | |
4320 | ||
4321 | if (simubitmap == 0) { | |
4322 | for (i = 0; i < (bound / 4); i++) { | |
4323 | if (candidate[i] >= 0) { | |
4324 | for (j = i * 4; j < (i + 1) * 4 - 2; j++) | |
4325 | result[3][j] = result[candidate[i]][j]; | |
4326 | retval = false; | |
4327 | } | |
4328 | } | |
4329 | return retval; | |
4330 | } else if (!(simubitmap & 0x0f)) { | |
4331 | /* path A OK */ | |
4332 | for (i = 0; i < 4; i++) | |
4333 | result[3][i] = result[c1][i]; | |
4334 | } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { | |
4335 | /* path B OK */ | |
4336 | for (i = 4; i < 8; i++) | |
4337 | result[3][i] = result[c1][i]; | |
4338 | } | |
4339 | ||
4340 | return false; | |
4341 | } | |
4342 | ||
e1547c53 JS |
4343 | static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv, |
4344 | int result[][8], int c1, int c2) | |
4345 | { | |
4346 | u32 i, j, diff, simubitmap, bound = 0; | |
4347 | int candidate[2] = {-1, -1}; /* for path A and path B */ | |
4348 | int tmp1, tmp2; | |
4349 | bool retval = true; | |
4350 | ||
4351 | if (priv->tx_paths > 1) | |
4352 | bound = 8; | |
4353 | else | |
4354 | bound = 4; | |
4355 | ||
4356 | simubitmap = 0; | |
4357 | ||
4358 | for (i = 0; i < bound; i++) { | |
4359 | if (i & 1) { | |
4360 | if ((result[c1][i] & 0x00000200)) | |
4361 | tmp1 = result[c1][i] | 0xfffffc00; | |
4362 | else | |
4363 | tmp1 = result[c1][i]; | |
4364 | ||
4365 | if ((result[c2][i]& 0x00000200)) | |
4366 | tmp2 = result[c2][i] | 0xfffffc00; | |
4367 | else | |
4368 | tmp2 = result[c2][i]; | |
4369 | } else { | |
4370 | tmp1 = result[c1][i]; | |
4371 | tmp2 = result[c2][i]; | |
4372 | } | |
4373 | ||
4374 | diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); | |
4375 | ||
4376 | if (diff > MAX_TOLERANCE) { | |
4377 | if ((i == 2 || i == 6) && !simubitmap) { | |
4378 | if (result[c1][i] + result[c1][i + 1] == 0) | |
4379 | candidate[(i / 4)] = c2; | |
4380 | else if (result[c2][i] + result[c2][i + 1] == 0) | |
4381 | candidate[(i / 4)] = c1; | |
4382 | else | |
4383 | simubitmap = simubitmap | (1 << i); | |
4384 | } else { | |
4385 | simubitmap = simubitmap | (1 << i); | |
4386 | } | |
4387 | } | |
4388 | } | |
4389 | ||
4390 | if (simubitmap == 0) { | |
4391 | for (i = 0; i < (bound / 4); i++) { | |
4392 | if (candidate[i] >= 0) { | |
4393 | for (j = i * 4; j < (i + 1) * 4 - 2; j++) | |
4394 | result[3][j] = result[candidate[i]][j]; | |
4395 | retval = false; | |
4396 | } | |
4397 | } | |
4398 | return retval; | |
4399 | } else { | |
4400 | if (!(simubitmap & 0x03)) { | |
4401 | /* path A TX OK */ | |
4402 | for (i = 0; i < 2; i++) | |
4403 | result[3][i] = result[c1][i]; | |
4404 | } | |
4405 | ||
4406 | if (!(simubitmap & 0x0c)) { | |
4407 | /* path A RX OK */ | |
4408 | for (i = 2; i < 4; i++) | |
4409 | result[3][i] = result[c1][i]; | |
4410 | } | |
4411 | ||
4412 | if (!(simubitmap & 0x30) && priv->tx_paths > 1) { | |
4413 | /* path B RX OK */ | |
4414 | for (i = 4; i < 6; i++) | |
4415 | result[3][i] = result[c1][i]; | |
4416 | } | |
4417 | ||
4418 | if (!(simubitmap & 0x30) && priv->tx_paths > 1) { | |
4419 | /* path B RX OK */ | |
4420 | for (i = 6; i < 8; i++) | |
4421 | result[3][i] = result[c1][i]; | |
4422 | } | |
4423 | } | |
4424 | ||
4425 | return false; | |
4426 | } | |
4427 | ||
26f1fad2 JS |
4428 | static void |
4429 | rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) | |
4430 | { | |
4431 | int i; | |
4432 | ||
4433 | for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) | |
4434 | backup[i] = rtl8xxxu_read8(priv, reg[i]); | |
4435 | ||
4436 | backup[i] = rtl8xxxu_read32(priv, reg[i]); | |
4437 | } | |
4438 | ||
4439 | static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, | |
4440 | const u32 *reg, u32 *backup) | |
4441 | { | |
4442 | int i; | |
4443 | ||
4444 | for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) | |
4445 | rtl8xxxu_write8(priv, reg[i], backup[i]); | |
4446 | ||
4447 | rtl8xxxu_write32(priv, reg[i], backup[i]); | |
4448 | } | |
4449 | ||
4450 | static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, | |
4451 | u32 *backup, int count) | |
4452 | { | |
4453 | int i; | |
4454 | ||
4455 | for (i = 0; i < count; i++) | |
4456 | backup[i] = rtl8xxxu_read32(priv, regs[i]); | |
4457 | } | |
4458 | ||
4459 | static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, | |
4460 | u32 *backup, int count) | |
4461 | { | |
4462 | int i; | |
4463 | ||
4464 | for (i = 0; i < count; i++) | |
4465 | rtl8xxxu_write32(priv, regs[i], backup[i]); | |
4466 | } | |
4467 | ||
4468 | ||
4469 | static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, | |
4470 | bool path_a_on) | |
4471 | { | |
4472 | u32 path_on; | |
4473 | int i; | |
4474 | ||
26f1fad2 | 4475 | if (priv->tx_paths == 1) { |
8634af5e JS |
4476 | path_on = priv->fops->adda_1t_path_on; |
4477 | rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); | |
26f1fad2 | 4478 | } else { |
8634af5e JS |
4479 | path_on = path_a_on ? priv->fops->adda_2t_path_on_a : |
4480 | priv->fops->adda_2t_path_on_b; | |
4481 | ||
26f1fad2 JS |
4482 | rtl8xxxu_write32(priv, regs[0], path_on); |
4483 | } | |
4484 | ||
4485 | for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) | |
4486 | rtl8xxxu_write32(priv, regs[i], path_on); | |
4487 | } | |
4488 | ||
4489 | static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, | |
4490 | const u32 *regs, u32 *backup) | |
4491 | { | |
4492 | int i = 0; | |
4493 | ||
4494 | rtl8xxxu_write8(priv, regs[i], 0x3f); | |
4495 | ||
4496 | for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) | |
4497 | rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); | |
4498 | ||
4499 | rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); | |
4500 | } | |
4501 | ||
4502 | static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) | |
4503 | { | |
4504 | u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; | |
4505 | int result = 0; | |
4506 | ||
4507 | /* path-A IQK setting */ | |
4508 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); | |
4509 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); | |
4510 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); | |
4511 | ||
4512 | val32 = (priv->rf_paths > 1) ? 0x28160202 : | |
4513 | /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ | |
4514 | 0x28160502; | |
4515 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); | |
4516 | ||
4517 | /* path-B IQK setting */ | |
4518 | if (priv->rf_paths > 1) { | |
4519 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); | |
4520 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); | |
4521 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); | |
4522 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); | |
4523 | } | |
4524 | ||
4525 | /* LO calibration setting */ | |
4526 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); | |
4527 | ||
4528 | /* One shot, path A LOK & IQK */ | |
4529 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); | |
4530 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
4531 | ||
4532 | mdelay(1); | |
4533 | ||
4534 | /* Check failed */ | |
4535 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
4536 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); | |
4537 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); | |
4538 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); | |
4539 | ||
4540 | if (!(reg_eac & BIT(28)) && | |
4541 | ((reg_e94 & 0x03ff0000) != 0x01420000) && | |
4542 | ((reg_e9c & 0x03ff0000) != 0x00420000)) | |
4543 | result |= 0x01; | |
4544 | else /* If TX not OK, ignore RX */ | |
4545 | goto out; | |
4546 | ||
4547 | /* If TX is OK, check whether RX is OK */ | |
4548 | if (!(reg_eac & BIT(27)) && | |
4549 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && | |
4550 | ((reg_eac & 0x03ff0000) != 0x00360000)) | |
4551 | result |= 0x02; | |
4552 | else | |
4553 | dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", | |
4554 | __func__); | |
4555 | out: | |
4556 | return result; | |
4557 | } | |
4558 | ||
4559 | static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) | |
4560 | { | |
4561 | u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; | |
4562 | int result = 0; | |
4563 | ||
4564 | /* One shot, path B LOK & IQK */ | |
4565 | rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); | |
4566 | rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); | |
4567 | ||
4568 | mdelay(1); | |
4569 | ||
4570 | /* Check failed */ | |
4571 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
4572 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); | |
4573 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); | |
4574 | reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); | |
4575 | reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); | |
4576 | ||
4577 | if (!(reg_eac & BIT(31)) && | |
4578 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && | |
4579 | ((reg_ebc & 0x03ff0000) != 0x00420000)) | |
4580 | result |= 0x01; | |
4581 | else | |
4582 | goto out; | |
4583 | ||
4584 | if (!(reg_eac & BIT(30)) && | |
4585 | (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && | |
4586 | (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) | |
4587 | result |= 0x02; | |
4588 | else | |
4589 | dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", | |
4590 | __func__); | |
4591 | out: | |
4592 | return result; | |
4593 | } | |
4594 | ||
e1547c53 JS |
4595 | static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) |
4596 | { | |
4597 | u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; | |
4598 | int result = 0; | |
4599 | ||
4600 | path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); | |
4601 | ||
4602 | /* | |
4603 | * Leave IQK mode | |
4604 | */ | |
4605 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4606 | val32 &= 0x000000ff; | |
4607 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4608 | ||
4609 | /* | |
4610 | * Enable path A PA in TX IQK mode | |
4611 | */ | |
4612 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); | |
4613 | val32 |= 0x80000; | |
4614 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); | |
4615 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); | |
4616 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); | |
4617 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); | |
4618 | ||
4619 | /* | |
4620 | * Tx IQK setting | |
4621 | */ | |
4622 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); | |
4623 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
4624 | ||
4625 | /* path-A IQK setting */ | |
4626 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); | |
4627 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); | |
4628 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); | |
4629 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); | |
4630 | ||
4631 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); | |
4632 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); | |
4633 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); | |
4634 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); | |
4635 | ||
4636 | /* LO calibration setting */ | |
4637 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); | |
4638 | ||
4639 | /* | |
4640 | * Enter IQK mode | |
4641 | */ | |
4642 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4643 | val32 &= 0x000000ff; | |
4644 | val32 |= 0x80800000; | |
4645 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4646 | ||
4647 | /* | |
4648 | * The vendor driver indicates the USB module is always using | |
4649 | * S0S1 path 1 for the 8723bu. This may be different for 8192eu | |
4650 | */ | |
4651 | if (priv->rf_paths > 1) | |
4652 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); | |
4653 | else | |
4654 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); | |
4655 | ||
4656 | /* | |
4657 | * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. | |
4658 | * No trace of this in the 8192eu or 8188eu vendor drivers. | |
4659 | */ | |
4660 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); | |
4661 | ||
4662 | /* One shot, path A LOK & IQK */ | |
4663 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); | |
4664 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
4665 | ||
4666 | mdelay(1); | |
4667 | ||
4668 | /* Restore Ant Path */ | |
4669 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); | |
4670 | #ifdef RTL8723BU_BT | |
4671 | /* GNT_BT = 1 */ | |
4672 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); | |
4673 | #endif | |
4674 | ||
4675 | /* | |
4676 | * Leave IQK mode | |
4677 | */ | |
4678 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4679 | val32 &= 0x000000ff; | |
4680 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4681 | ||
4682 | /* Check failed */ | |
4683 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
4684 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); | |
4685 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); | |
4686 | ||
4687 | val32 = (reg_e9c >> 16) & 0x3ff; | |
4688 | if (val32 & 0x200) | |
4689 | val32 = 0x400 - val32; | |
4690 | ||
4691 | if (!(reg_eac & BIT(28)) && | |
4692 | ((reg_e94 & 0x03ff0000) != 0x01420000) && | |
4693 | ((reg_e9c & 0x03ff0000) != 0x00420000) && | |
4694 | ((reg_e94 & 0x03ff0000) < 0x01100000) && | |
4695 | ((reg_e94 & 0x03ff0000) > 0x00f00000) && | |
4696 | val32 < 0xf) | |
4697 | result |= 0x01; | |
4698 | else /* If TX not OK, ignore RX */ | |
4699 | goto out; | |
4700 | ||
4701 | out: | |
4702 | return result; | |
4703 | } | |
4704 | ||
4705 | static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) | |
4706 | { | |
4707 | u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; | |
4708 | int result = 0; | |
4709 | ||
4710 | path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); | |
4711 | ||
4712 | /* | |
4713 | * Leave IQK mode | |
4714 | */ | |
4715 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4716 | val32 &= 0x000000ff; | |
4717 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4718 | ||
4719 | /* | |
4720 | * Enable path A PA in TX IQK mode | |
4721 | */ | |
4722 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); | |
4723 | val32 |= 0x80000; | |
4724 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); | |
4725 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); | |
4726 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); | |
4727 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); | |
4728 | ||
4729 | /* | |
4730 | * Tx IQK setting | |
4731 | */ | |
4732 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); | |
4733 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
4734 | ||
4735 | /* path-A IQK setting */ | |
4736 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); | |
4737 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); | |
4738 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); | |
4739 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); | |
4740 | ||
4741 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); | |
4742 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); | |
4743 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); | |
4744 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); | |
4745 | ||
4746 | /* LO calibration setting */ | |
4747 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); | |
4748 | ||
4749 | /* | |
4750 | * Enter IQK mode | |
4751 | */ | |
4752 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4753 | val32 &= 0x000000ff; | |
4754 | val32 |= 0x80800000; | |
4755 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4756 | ||
4757 | /* | |
4758 | * The vendor driver indicates the USB module is always using | |
4759 | * S0S1 path 1 for the 8723bu. This may be different for 8192eu | |
4760 | */ | |
4761 | if (priv->rf_paths > 1) | |
4762 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); | |
4763 | else | |
4764 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); | |
4765 | ||
4766 | /* | |
4767 | * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. | |
4768 | * No trace of this in the 8192eu or 8188eu vendor drivers. | |
4769 | */ | |
4770 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); | |
4771 | ||
4772 | /* One shot, path A LOK & IQK */ | |
4773 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); | |
4774 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
4775 | ||
4776 | mdelay(1); | |
4777 | ||
4778 | /* Restore Ant Path */ | |
4779 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); | |
4780 | #ifdef RTL8723BU_BT | |
4781 | /* GNT_BT = 1 */ | |
4782 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); | |
4783 | #endif | |
4784 | ||
4785 | /* | |
4786 | * Leave IQK mode | |
4787 | */ | |
4788 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4789 | val32 &= 0x000000ff; | |
4790 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4791 | ||
4792 | /* Check failed */ | |
4793 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
4794 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); | |
4795 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); | |
4796 | ||
4797 | val32 = (reg_e9c >> 16) & 0x3ff; | |
4798 | if (val32 & 0x200) | |
4799 | val32 = 0x400 - val32; | |
4800 | ||
4801 | if (!(reg_eac & BIT(28)) && | |
4802 | ((reg_e94 & 0x03ff0000) != 0x01420000) && | |
4803 | ((reg_e9c & 0x03ff0000) != 0x00420000) && | |
4804 | ((reg_e94 & 0x03ff0000) < 0x01100000) && | |
4805 | ((reg_e94 & 0x03ff0000) > 0x00f00000) && | |
4806 | val32 < 0xf) | |
4807 | result |= 0x01; | |
4808 | else /* If TX not OK, ignore RX */ | |
4809 | goto out; | |
4810 | ||
4811 | val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | | |
4812 | ((reg_e9c & 0x3ff0000) >> 16); | |
4813 | rtl8xxxu_write32(priv, REG_TX_IQK, val32); | |
4814 | ||
4815 | /* | |
4816 | * Modify RX IQK mode | |
4817 | */ | |
4818 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4819 | val32 &= 0x000000ff; | |
4820 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4821 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); | |
4822 | val32 |= 0x80000; | |
4823 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); | |
4824 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); | |
4825 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); | |
4826 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); | |
4827 | ||
4828 | /* | |
4829 | * PA, PAD setting | |
4830 | */ | |
4831 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80); | |
4832 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); | |
4833 | ||
4834 | /* | |
4835 | * RX IQK setting | |
4836 | */ | |
4837 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
4838 | ||
4839 | /* path-A IQK setting */ | |
4840 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); | |
4841 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); | |
4842 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); | |
4843 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); | |
4844 | ||
4845 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); | |
4846 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); | |
4847 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); | |
4848 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); | |
4849 | ||
4850 | /* LO calibration setting */ | |
4851 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); | |
4852 | ||
4853 | /* | |
4854 | * Enter IQK mode | |
4855 | */ | |
4856 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4857 | val32 &= 0x000000ff; | |
4858 | val32 |= 0x80800000; | |
4859 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4860 | ||
4861 | if (priv->rf_paths > 1) | |
4862 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); | |
4863 | else | |
4864 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); | |
4865 | ||
4866 | /* | |
4867 | * Disable BT | |
4868 | */ | |
4869 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); | |
4870 | ||
4871 | /* One shot, path A LOK & IQK */ | |
4872 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); | |
4873 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
4874 | ||
4875 | mdelay(1); | |
4876 | ||
4877 | /* Restore Ant Path */ | |
4878 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); | |
4879 | #ifdef RTL8723BU_BT | |
4880 | /* GNT_BT = 1 */ | |
4881 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); | |
4882 | #endif | |
4883 | ||
4884 | /* | |
4885 | * Leave IQK mode | |
4886 | */ | |
4887 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4888 | val32 &= 0x000000ff; | |
4889 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4890 | ||
4891 | /* Check failed */ | |
4892 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
4893 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); | |
4894 | ||
4895 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780); | |
4896 | ||
4897 | val32 = (reg_eac >> 16) & 0x3ff; | |
4898 | if (val32 & 0x200) | |
4899 | val32 = 0x400 - val32; | |
4900 | ||
4901 | if (!(reg_eac & BIT(27)) && | |
4902 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && | |
4903 | ((reg_eac & 0x03ff0000) != 0x00360000) && | |
4904 | ((reg_ea4 & 0x03ff0000) < 0x01100000) && | |
4905 | ((reg_ea4 & 0x03ff0000) > 0x00f00000) && | |
4906 | val32 < 0xf) | |
4907 | result |= 0x02; | |
4908 | else /* If TX not OK, ignore RX */ | |
4909 | goto out; | |
4910 | out: | |
4911 | return result; | |
4912 | } | |
4913 | ||
4914 | #ifdef RTL8723BU_PATH_B | |
4915 | static int rtl8723bu_iqk_path_b(struct rtl8xxxu_priv *priv) | |
4916 | { | |
4917 | u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, path_sel; | |
4918 | int result = 0; | |
4919 | ||
4920 | path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); | |
4921 | ||
4922 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
4923 | val32 &= 0x000000ff; | |
4924 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
4925 | ||
4926 | /* One shot, path B LOK & IQK */ | |
4927 | rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); | |
4928 | rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); | |
4929 | ||
4930 | mdelay(1); | |
4931 | ||
4932 | /* Check failed */ | |
4933 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
4934 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); | |
4935 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); | |
4936 | reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); | |
4937 | reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); | |
4938 | ||
4939 | if (!(reg_eac & BIT(31)) && | |
4940 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && | |
4941 | ((reg_ebc & 0x03ff0000) != 0x00420000)) | |
4942 | result |= 0x01; | |
4943 | else | |
4944 | goto out; | |
4945 | ||
4946 | if (!(reg_eac & BIT(30)) && | |
4947 | (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && | |
4948 | (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) | |
4949 | result |= 0x02; | |
4950 | else | |
4951 | dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", | |
4952 | __func__); | |
4953 | out: | |
4954 | return result; | |
4955 | } | |
4956 | #endif | |
4957 | ||
f991f4e9 JS |
4958 | static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) |
4959 | { | |
4960 | u32 reg_eac, reg_e94, reg_e9c; | |
4961 | int result = 0; | |
4962 | ||
4963 | /* | |
4964 | * TX IQK | |
4965 | * PA/PAD controlled by 0x0 | |
4966 | */ | |
4967 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
4968 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180); | |
4969 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
4970 | ||
4971 | /* Path A IQK setting */ | |
4972 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); | |
4973 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); | |
4974 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); | |
4975 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); | |
4976 | ||
4977 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); | |
4978 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); | |
4979 | ||
4980 | /* LO calibration setting */ | |
4981 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); | |
4982 | ||
4983 | /* One shot, path A LOK & IQK */ | |
4984 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); | |
4985 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
4986 | ||
4987 | mdelay(10); | |
4988 | ||
4989 | /* Check failed */ | |
4990 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
4991 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); | |
4992 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); | |
4993 | ||
4994 | if (!(reg_eac & BIT(28)) && | |
4995 | ((reg_e94 & 0x03ff0000) != 0x01420000) && | |
4996 | ((reg_e9c & 0x03ff0000) != 0x00420000)) | |
4997 | result |= 0x01; | |
4998 | ||
4999 | return result; | |
5000 | } | |
5001 | ||
5002 | static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) | |
5003 | { | |
5004 | u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; | |
5005 | int result = 0; | |
5006 | ||
5007 | /* Leave IQK mode */ | |
5008 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); | |
5009 | ||
5010 | /* Enable path A PA in TX IQK mode */ | |
5011 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); | |
5012 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); | |
5013 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); | |
5014 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b); | |
5015 | ||
5016 | /* PA/PAD control by 0x56, and set = 0x0 */ | |
5017 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); | |
5018 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); | |
5019 | ||
5020 | /* Enter IQK mode */ | |
5021 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5022 | ||
5023 | /* TX IQK setting */ | |
5024 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); | |
5025 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
5026 | ||
5027 | /* path-A IQK setting */ | |
5028 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); | |
5029 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); | |
5030 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); | |
5031 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); | |
5032 | ||
5033 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); | |
5034 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f); | |
5035 | ||
5036 | /* LO calibration setting */ | |
5037 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); | |
5038 | ||
5039 | /* One shot, path A LOK & IQK */ | |
5040 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); | |
5041 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
5042 | ||
5043 | mdelay(10); | |
5044 | ||
5045 | /* Check failed */ | |
5046 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
5047 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); | |
5048 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); | |
5049 | ||
5050 | if (!(reg_eac & BIT(28)) && | |
5051 | ((reg_e94 & 0x03ff0000) != 0x01420000) && | |
5052 | ((reg_e9c & 0x03ff0000) != 0x00420000)) { | |
5053 | result |= 0x01; | |
5054 | } else { | |
5055 | /* PA/PAD controlled by 0x0 */ | |
5056 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5057 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); | |
5058 | goto out; | |
5059 | } | |
5060 | ||
5061 | val32 = 0x80007c00 | | |
5062 | (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); | |
5063 | rtl8xxxu_write32(priv, REG_TX_IQK, val32); | |
5064 | ||
5065 | /* Modify RX IQK mode table */ | |
5066 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5067 | ||
5068 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); | |
5069 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); | |
5070 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); | |
5071 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa); | |
5072 | ||
5073 | /* PA/PAD control by 0x56, and set = 0x0 */ | |
5074 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); | |
5075 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); | |
5076 | ||
5077 | /* Enter IQK mode */ | |
5078 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5079 | ||
5080 | /* IQK setting */ | |
5081 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
5082 | ||
5083 | /* Path A IQK setting */ | |
5084 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); | |
5085 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); | |
5086 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); | |
5087 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); | |
5088 | ||
5089 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); | |
5090 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); | |
5091 | ||
5092 | /* LO calibration setting */ | |
5093 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); | |
5094 | ||
5095 | /* One shot, path A LOK & IQK */ | |
5096 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); | |
5097 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
5098 | ||
5099 | mdelay(10); | |
5100 | ||
5101 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
5102 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); | |
5103 | ||
5104 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5105 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); | |
5106 | ||
5107 | if (!(reg_eac & BIT(27)) && | |
5108 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && | |
5109 | ((reg_eac & 0x03ff0000) != 0x00360000)) | |
5110 | result |= 0x02; | |
5111 | else | |
5112 | dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", | |
5113 | __func__); | |
5114 | ||
5115 | out: | |
5116 | return result; | |
5117 | } | |
5118 | ||
5119 | static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) | |
5120 | { | |
5121 | u32 reg_eac, reg_eb4, reg_ebc; | |
5122 | int result = 0; | |
5123 | ||
5124 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5125 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180); | |
5126 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5127 | ||
5128 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5129 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5130 | ||
5131 | /* Path B IQK setting */ | |
5132 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); | |
5133 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); | |
5134 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); | |
5135 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); | |
5136 | ||
5137 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2); | |
5138 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); | |
5139 | ||
5140 | /* LO calibration setting */ | |
5141 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911); | |
5142 | ||
5143 | /* One shot, path A LOK & IQK */ | |
5144 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); | |
5145 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
5146 | ||
5147 | mdelay(1); | |
5148 | ||
5149 | /* Check failed */ | |
5150 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
5151 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); | |
5152 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); | |
5153 | ||
5154 | if (!(reg_eac & BIT(31)) && | |
5155 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && | |
5156 | ((reg_ebc & 0x03ff0000) != 0x00420000)) | |
5157 | result |= 0x01; | |
5158 | else | |
5159 | dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", | |
5160 | __func__); | |
5161 | ||
5162 | return result; | |
5163 | } | |
5164 | ||
5165 | static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) | |
5166 | { | |
5167 | u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; | |
5168 | int result = 0; | |
5169 | ||
5170 | /* Leave IQK mode */ | |
5171 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5172 | ||
5173 | /* Enable path A PA in TX IQK mode */ | |
5174 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); | |
5175 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); | |
5176 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); | |
5177 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b); | |
5178 | ||
5179 | /* PA/PAD control by 0x56, and set = 0x0 */ | |
5180 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); | |
5181 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); | |
5182 | ||
5183 | /* Enter IQK mode */ | |
5184 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5185 | ||
5186 | /* TX IQK setting */ | |
5187 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); | |
5188 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
5189 | ||
5190 | /* path-A IQK setting */ | |
5191 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); | |
5192 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); | |
5193 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); | |
5194 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); | |
5195 | ||
5196 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f); | |
5197 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f); | |
5198 | ||
5199 | /* LO calibration setting */ | |
5200 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); | |
5201 | ||
5202 | /* One shot, path A LOK & IQK */ | |
5203 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); | |
5204 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
5205 | ||
5206 | mdelay(10); | |
5207 | ||
5208 | /* Check failed */ | |
5209 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
5210 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); | |
5211 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); | |
5212 | ||
5213 | if (!(reg_eac & BIT(31)) && | |
5214 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && | |
5215 | ((reg_ebc & 0x03ff0000) != 0x00420000)) { | |
5216 | result |= 0x01; | |
5217 | } else { | |
5218 | /* | |
5219 | * PA/PAD controlled by 0x0 | |
5220 | * Vendor driver restores RF_A here which I believe is a bug | |
5221 | */ | |
5222 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5223 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); | |
5224 | goto out; | |
5225 | } | |
5226 | ||
5227 | val32 = 0x80007c00 | | |
5228 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); | |
5229 | rtl8xxxu_write32(priv, REG_TX_IQK, val32); | |
5230 | ||
5231 | /* Modify RX IQK mode table */ | |
5232 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5233 | ||
5234 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); | |
5235 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); | |
5236 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); | |
5237 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa); | |
5238 | ||
5239 | /* PA/PAD control by 0x56, and set = 0x0 */ | |
5240 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); | |
5241 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); | |
5242 | ||
5243 | /* Enter IQK mode */ | |
5244 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5245 | ||
5246 | /* IQK setting */ | |
5247 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
5248 | ||
5249 | /* Path A IQK setting */ | |
5250 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); | |
5251 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); | |
5252 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); | |
5253 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); | |
5254 | ||
5255 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); | |
5256 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); | |
5257 | ||
5258 | /* LO calibration setting */ | |
5259 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); | |
5260 | ||
5261 | /* One shot, path A LOK & IQK */ | |
5262 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); | |
5263 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); | |
5264 | ||
5265 | mdelay(10); | |
5266 | ||
5267 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); | |
5268 | reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); | |
5269 | reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); | |
5270 | ||
5271 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5272 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); | |
5273 | ||
5274 | if (!(reg_eac & BIT(30)) && | |
5275 | ((reg_ec4 & 0x03ff0000) != 0x01320000) && | |
5276 | ((reg_ecc & 0x03ff0000) != 0x00360000)) | |
5277 | result |= 0x02; | |
5278 | else | |
5279 | dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", | |
5280 | __func__); | |
5281 | ||
5282 | out: | |
5283 | return result; | |
5284 | } | |
5285 | ||
26f1fad2 JS |
5286 | static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
5287 | int result[][8], int t) | |
5288 | { | |
5289 | struct device *dev = &priv->udev->dev; | |
5290 | u32 i, val32; | |
5291 | int path_a_ok, path_b_ok; | |
5292 | int retry = 2; | |
5293 | const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { | |
5294 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, | |
5295 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, | |
5296 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, | |
5297 | REG_TX_OFDM_BBON, REG_TX_TO_RX, | |
5298 | REG_TX_TO_TX, REG_RX_CCK, | |
5299 | REG_RX_OFDM, REG_RX_WAIT_RIFS, | |
5300 | REG_RX_TO_RX, REG_STANDBY, | |
5301 | REG_SLEEP, REG_PMPD_ANAEN | |
5302 | }; | |
5303 | const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { | |
5304 | REG_TXPAUSE, REG_BEACON_CTRL, | |
5305 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG | |
5306 | }; | |
5307 | const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { | |
5308 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, | |
5309 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, | |
5310 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, | |
5311 | REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE | |
5312 | }; | |
5313 | ||
5314 | /* | |
5315 | * Note: IQ calibration must be performed after loading | |
5316 | * PHY_REG.txt , and radio_a, radio_b.txt | |
5317 | */ | |
5318 | ||
5319 | if (t == 0) { | |
5320 | /* Save ADDA parameters, turn Path A ADDA on */ | |
5321 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, | |
5322 | RTL8XXXU_ADDA_REGS); | |
5323 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); | |
5324 | rtl8xxxu_save_regs(priv, iqk_bb_regs, | |
5325 | priv->bb_backup, RTL8XXXU_BB_REGS); | |
5326 | } | |
5327 | ||
5328 | rtl8xxxu_path_adda_on(priv, adda_regs, true); | |
5329 | ||
5330 | if (t == 0) { | |
5331 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); | |
5332 | if (val32 & FPGA0_HSSI_PARM1_PI) | |
5333 | priv->pi_enabled = 1; | |
5334 | } | |
5335 | ||
5336 | if (!priv->pi_enabled) { | |
5337 | /* Switch BB to PI mode to do IQ Calibration. */ | |
5338 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); | |
5339 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); | |
5340 | } | |
5341 | ||
5342 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
5343 | val32 &= ~FPGA_RF_MODE_CCK; | |
5344 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
5345 | ||
5346 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); | |
5347 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); | |
5348 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); | |
5349 | ||
5350 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); | |
5351 | val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); | |
5352 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); | |
5353 | ||
5354 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); | |
5355 | val32 &= ~BIT(10); | |
5356 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); | |
5357 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); | |
5358 | val32 &= ~BIT(10); | |
5359 | rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); | |
5360 | ||
5361 | if (priv->tx_paths > 1) { | |
5362 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); | |
5363 | rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); | |
5364 | } | |
5365 | ||
5366 | /* MAC settings */ | |
5367 | rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); | |
5368 | ||
5369 | /* Page B init */ | |
5370 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); | |
5371 | ||
5372 | if (priv->tx_paths > 1) | |
5373 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); | |
5374 | ||
5375 | /* IQ calibration setting */ | |
5376 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5377 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); | |
5378 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
5379 | ||
5380 | for (i = 0; i < retry; i++) { | |
5381 | path_a_ok = rtl8xxxu_iqk_path_a(priv); | |
5382 | if (path_a_ok == 0x03) { | |
5383 | val32 = rtl8xxxu_read32(priv, | |
5384 | REG_TX_POWER_BEFORE_IQK_A); | |
5385 | result[t][0] = (val32 >> 16) & 0x3ff; | |
5386 | val32 = rtl8xxxu_read32(priv, | |
5387 | REG_TX_POWER_AFTER_IQK_A); | |
5388 | result[t][1] = (val32 >> 16) & 0x3ff; | |
5389 | val32 = rtl8xxxu_read32(priv, | |
5390 | REG_RX_POWER_BEFORE_IQK_A_2); | |
5391 | result[t][2] = (val32 >> 16) & 0x3ff; | |
5392 | val32 = rtl8xxxu_read32(priv, | |
5393 | REG_RX_POWER_AFTER_IQK_A_2); | |
5394 | result[t][3] = (val32 >> 16) & 0x3ff; | |
5395 | break; | |
5396 | } else if (i == (retry - 1) && path_a_ok == 0x01) { | |
5397 | /* TX IQK OK */ | |
5398 | dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", | |
5399 | __func__); | |
5400 | ||
5401 | val32 = rtl8xxxu_read32(priv, | |
5402 | REG_TX_POWER_BEFORE_IQK_A); | |
5403 | result[t][0] = (val32 >> 16) & 0x3ff; | |
5404 | val32 = rtl8xxxu_read32(priv, | |
5405 | REG_TX_POWER_AFTER_IQK_A); | |
5406 | result[t][1] = (val32 >> 16) & 0x3ff; | |
5407 | } | |
5408 | } | |
5409 | ||
5410 | if (!path_a_ok) | |
5411 | dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); | |
5412 | ||
5413 | if (priv->tx_paths > 1) { | |
5414 | /* | |
5415 | * Path A into standby | |
5416 | */ | |
5417 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); | |
5418 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); | |
5419 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5420 | ||
5421 | /* Turn Path B ADDA on */ | |
5422 | rtl8xxxu_path_adda_on(priv, adda_regs, false); | |
5423 | ||
5424 | for (i = 0; i < retry; i++) { | |
5425 | path_b_ok = rtl8xxxu_iqk_path_b(priv); | |
5426 | if (path_b_ok == 0x03) { | |
5427 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); | |
5428 | result[t][4] = (val32 >> 16) & 0x3ff; | |
5429 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); | |
5430 | result[t][5] = (val32 >> 16) & 0x3ff; | |
5431 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); | |
5432 | result[t][6] = (val32 >> 16) & 0x3ff; | |
5433 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); | |
5434 | result[t][7] = (val32 >> 16) & 0x3ff; | |
5435 | break; | |
5436 | } else if (i == (retry - 1) && path_b_ok == 0x01) { | |
5437 | /* TX IQK OK */ | |
5438 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); | |
5439 | result[t][4] = (val32 >> 16) & 0x3ff; | |
5440 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); | |
5441 | result[t][5] = (val32 >> 16) & 0x3ff; | |
5442 | } | |
5443 | } | |
5444 | ||
5445 | if (!path_b_ok) | |
5446 | dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); | |
5447 | } | |
5448 | ||
5449 | /* Back to BB mode, load original value */ | |
5450 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); | |
5451 | ||
5452 | if (t) { | |
5453 | if (!priv->pi_enabled) { | |
5454 | /* | |
5455 | * Switch back BB to SI mode after finishing | |
5456 | * IQ Calibration | |
5457 | */ | |
5458 | val32 = 0x01000000; | |
5459 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); | |
5460 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); | |
5461 | } | |
5462 | ||
5463 | /* Reload ADDA power saving parameters */ | |
5464 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, | |
5465 | RTL8XXXU_ADDA_REGS); | |
5466 | ||
5467 | /* Reload MAC parameters */ | |
5468 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); | |
5469 | ||
5470 | /* Reload BB parameters */ | |
5471 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, | |
5472 | priv->bb_backup, RTL8XXXU_BB_REGS); | |
5473 | ||
5474 | /* Restore RX initial gain */ | |
5475 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); | |
5476 | ||
5477 | if (priv->tx_paths > 1) { | |
5478 | rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, | |
5479 | 0x00032ed3); | |
5480 | } | |
5481 | ||
5482 | /* Load 0xe30 IQC default value */ | |
5483 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); | |
5484 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); | |
5485 | } | |
5486 | } | |
5487 | ||
e1547c53 JS |
5488 | static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
5489 | int result[][8], int t) | |
5490 | { | |
5491 | struct device *dev = &priv->udev->dev; | |
5492 | u32 i, val32; | |
5493 | int path_a_ok /*, path_b_ok */; | |
5494 | int retry = 2; | |
5495 | const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { | |
5496 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, | |
5497 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, | |
5498 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, | |
5499 | REG_TX_OFDM_BBON, REG_TX_TO_RX, | |
5500 | REG_TX_TO_TX, REG_RX_CCK, | |
5501 | REG_RX_OFDM, REG_RX_WAIT_RIFS, | |
5502 | REG_RX_TO_RX, REG_STANDBY, | |
5503 | REG_SLEEP, REG_PMPD_ANAEN | |
5504 | }; | |
5505 | const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { | |
5506 | REG_TXPAUSE, REG_BEACON_CTRL, | |
5507 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG | |
5508 | }; | |
5509 | const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { | |
5510 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, | |
5511 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, | |
5512 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, | |
5513 | REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE | |
5514 | }; | |
5515 | u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; | |
5516 | u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; | |
5517 | ||
5518 | /* | |
5519 | * Note: IQ calibration must be performed after loading | |
5520 | * PHY_REG.txt , and radio_a, radio_b.txt | |
5521 | */ | |
5522 | ||
5523 | if (t == 0) { | |
5524 | /* Save ADDA parameters, turn Path A ADDA on */ | |
5525 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, | |
5526 | RTL8XXXU_ADDA_REGS); | |
5527 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); | |
5528 | rtl8xxxu_save_regs(priv, iqk_bb_regs, | |
5529 | priv->bb_backup, RTL8XXXU_BB_REGS); | |
5530 | } | |
5531 | ||
5532 | rtl8xxxu_path_adda_on(priv, adda_regs, true); | |
5533 | ||
5534 | /* MAC settings */ | |
5535 | rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); | |
5536 | ||
5537 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); | |
5538 | val32 |= 0x0f000000; | |
5539 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); | |
5540 | ||
5541 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); | |
5542 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); | |
5543 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); | |
5544 | ||
5545 | #ifdef RTL8723BU_PATH_B | |
5546 | /* Set RF mode to standby Path B */ | |
5547 | if (priv->tx_paths > 1) | |
5548 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x10000); | |
5549 | #endif | |
5550 | ||
5551 | #if 0 | |
5552 | /* Page B init */ | |
5553 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x0f600000); | |
5554 | ||
5555 | if (priv->tx_paths > 1) | |
5556 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x0f600000); | |
5557 | #endif | |
5558 | ||
5559 | /* | |
5560 | * RX IQ calibration setting for 8723B D cut large current issue | |
5561 | * when leaving IPS | |
5562 | */ | |
5563 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
5564 | val32 &= 0x000000ff; | |
5565 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
5566 | ||
5567 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); | |
5568 | val32 |= 0x80000; | |
5569 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); | |
5570 | ||
5571 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); | |
5572 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); | |
5573 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); | |
5574 | ||
5575 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); | |
5576 | val32 |= 0x20; | |
5577 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); | |
5578 | ||
5579 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); | |
5580 | ||
5581 | for (i = 0; i < retry; i++) { | |
5582 | path_a_ok = rtl8723bu_iqk_path_a(priv); | |
5583 | if (path_a_ok == 0x01) { | |
5584 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
5585 | val32 &= 0x000000ff; | |
5586 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
5587 | ||
5588 | #if 0 /* Only needed in restore case, we may need this when going to suspend */ | |
5589 | priv->RFCalibrateInfo.TxLOK[RF_A] = | |
5590 | rtl8xxxu_read_rfreg(priv, RF_A, | |
5591 | RF6052_REG_TXM_IDAC); | |
5592 | #endif | |
5593 | ||
5594 | val32 = rtl8xxxu_read32(priv, | |
5595 | REG_TX_POWER_BEFORE_IQK_A); | |
5596 | result[t][0] = (val32 >> 16) & 0x3ff; | |
5597 | val32 = rtl8xxxu_read32(priv, | |
5598 | REG_TX_POWER_AFTER_IQK_A); | |
5599 | result[t][1] = (val32 >> 16) & 0x3ff; | |
5600 | ||
5601 | break; | |
5602 | } | |
5603 | } | |
5604 | ||
5605 | if (!path_a_ok) | |
5606 | dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); | |
5607 | ||
5608 | for (i = 0; i < retry; i++) { | |
5609 | path_a_ok = rtl8723bu_rx_iqk_path_a(priv); | |
5610 | if (path_a_ok == 0x03) { | |
5611 | val32 = rtl8xxxu_read32(priv, | |
5612 | REG_RX_POWER_BEFORE_IQK_A_2); | |
5613 | result[t][2] = (val32 >> 16) & 0x3ff; | |
5614 | val32 = rtl8xxxu_read32(priv, | |
5615 | REG_RX_POWER_AFTER_IQK_A_2); | |
5616 | result[t][3] = (val32 >> 16) & 0x3ff; | |
5617 | ||
5618 | break; | |
5619 | } | |
5620 | } | |
5621 | ||
5622 | if (!path_a_ok) | |
5623 | dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); | |
5624 | ||
5625 | if (priv->tx_paths > 1) { | |
5626 | #if 1 | |
5627 | dev_warn(dev, "%s: Path B not supported\n", __func__); | |
5628 | #else | |
5629 | ||
5630 | /* | |
5631 | * Path A into standby | |
5632 | */ | |
5633 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
5634 | val32 &= 0x000000ff; | |
5635 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
5636 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); | |
5637 | ||
5638 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
5639 | val32 &= 0x000000ff; | |
5640 | val32 |= 0x80800000; | |
5641 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
5642 | ||
5643 | /* Turn Path B ADDA on */ | |
5644 | rtl8xxxu_path_adda_on(priv, adda_regs, false); | |
5645 | ||
5646 | for (i = 0; i < retry; i++) { | |
5647 | path_b_ok = rtl8xxxu_iqk_path_b(priv); | |
5648 | if (path_b_ok == 0x03) { | |
5649 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); | |
5650 | result[t][4] = (val32 >> 16) & 0x3ff; | |
5651 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); | |
5652 | result[t][5] = (val32 >> 16) & 0x3ff; | |
5653 | break; | |
5654 | } | |
5655 | } | |
5656 | ||
5657 | if (!path_b_ok) | |
5658 | dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); | |
5659 | ||
5660 | for (i = 0; i < retry; i++) { | |
5661 | path_b_ok = rtl8723bu_rx_iqk_path_b(priv); | |
5662 | if (path_a_ok == 0x03) { | |
5663 | val32 = rtl8xxxu_read32(priv, | |
5664 | REG_RX_POWER_BEFORE_IQK_B_2); | |
5665 | result[t][6] = (val32 >> 16) & 0x3ff; | |
5666 | val32 = rtl8xxxu_read32(priv, | |
5667 | REG_RX_POWER_AFTER_IQK_B_2); | |
5668 | result[t][7] = (val32 >> 16) & 0x3ff; | |
5669 | break; | |
5670 | } | |
5671 | } | |
5672 | ||
5673 | if (!path_b_ok) | |
5674 | dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); | |
5675 | #endif | |
5676 | } | |
5677 | ||
5678 | /* Back to BB mode, load original value */ | |
5679 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
5680 | val32 &= 0x000000ff; | |
5681 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
5682 | ||
5683 | if (t) { | |
5684 | /* Reload ADDA power saving parameters */ | |
5685 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, | |
5686 | RTL8XXXU_ADDA_REGS); | |
5687 | ||
5688 | /* Reload MAC parameters */ | |
5689 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); | |
5690 | ||
5691 | /* Reload BB parameters */ | |
5692 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, | |
5693 | priv->bb_backup, RTL8XXXU_BB_REGS); | |
5694 | ||
5695 | /* Restore RX initial gain */ | |
5696 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); | |
5697 | val32 &= 0xffffff00; | |
5698 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); | |
5699 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); | |
5700 | ||
5701 | if (priv->tx_paths > 1) { | |
5702 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); | |
5703 | val32 &= 0xffffff00; | |
5704 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, | |
5705 | val32 | 0x50); | |
5706 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, | |
5707 | val32 | xb_agc); | |
5708 | } | |
5709 | ||
5710 | /* Load 0xe30 IQC default value */ | |
5711 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); | |
5712 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); | |
5713 | } | |
5714 | } | |
5715 | ||
f991f4e9 JS |
5716 | static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
5717 | int result[][8], int t) | |
5718 | { | |
5719 | struct device *dev = &priv->udev->dev; | |
5720 | u32 i, val32; | |
5721 | int path_a_ok, path_b_ok; | |
5722 | int retry = 2; | |
5723 | const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { | |
5724 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, | |
5725 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, | |
5726 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, | |
5727 | REG_TX_OFDM_BBON, REG_TX_TO_RX, | |
5728 | REG_TX_TO_TX, REG_RX_CCK, | |
5729 | REG_RX_OFDM, REG_RX_WAIT_RIFS, | |
5730 | REG_RX_TO_RX, REG_STANDBY, | |
5731 | REG_SLEEP, REG_PMPD_ANAEN | |
5732 | }; | |
5733 | const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { | |
5734 | REG_TXPAUSE, REG_BEACON_CTRL, | |
5735 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG | |
5736 | }; | |
5737 | const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { | |
5738 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, | |
5739 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, | |
5740 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, | |
5741 | REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING | |
5742 | }; | |
5743 | u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; | |
5744 | u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; | |
5745 | ||
5746 | /* | |
5747 | * Note: IQ calibration must be performed after loading | |
5748 | * PHY_REG.txt , and radio_a, radio_b.txt | |
5749 | */ | |
5750 | ||
5751 | if (t == 0) { | |
5752 | /* Save ADDA parameters, turn Path A ADDA on */ | |
5753 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, | |
5754 | RTL8XXXU_ADDA_REGS); | |
5755 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); | |
5756 | rtl8xxxu_save_regs(priv, iqk_bb_regs, | |
5757 | priv->bb_backup, RTL8XXXU_BB_REGS); | |
5758 | } | |
5759 | ||
5760 | rtl8xxxu_path_adda_on(priv, adda_regs, true); | |
5761 | ||
5762 | /* MAC settings */ | |
5763 | rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); | |
5764 | ||
5765 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); | |
5766 | val32 |= 0x0f000000; | |
5767 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); | |
5768 | ||
5769 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); | |
5770 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); | |
5771 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); | |
5772 | ||
5773 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); | |
5774 | val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); | |
5775 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); | |
5776 | ||
5777 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); | |
5778 | val32 |= BIT(10); | |
5779 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); | |
5780 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); | |
5781 | val32 |= BIT(10); | |
5782 | rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); | |
5783 | ||
5784 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5785 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); | |
5786 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
5787 | ||
5788 | for (i = 0; i < retry; i++) { | |
5789 | path_a_ok = rtl8192eu_iqk_path_a(priv); | |
5790 | if (path_a_ok == 0x01) { | |
5791 | val32 = rtl8xxxu_read32(priv, | |
5792 | REG_TX_POWER_BEFORE_IQK_A); | |
5793 | result[t][0] = (val32 >> 16) & 0x3ff; | |
5794 | val32 = rtl8xxxu_read32(priv, | |
5795 | REG_TX_POWER_AFTER_IQK_A); | |
5796 | result[t][1] = (val32 >> 16) & 0x3ff; | |
5797 | ||
5798 | break; | |
5799 | } | |
5800 | } | |
5801 | ||
5802 | if (!path_a_ok) | |
5803 | dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); | |
5804 | ||
5805 | for (i = 0; i < retry; i++) { | |
5806 | path_a_ok = rtl8192eu_rx_iqk_path_a(priv); | |
5807 | if (path_a_ok == 0x03) { | |
5808 | val32 = rtl8xxxu_read32(priv, | |
5809 | REG_RX_POWER_BEFORE_IQK_A_2); | |
5810 | result[t][2] = (val32 >> 16) & 0x3ff; | |
5811 | val32 = rtl8xxxu_read32(priv, | |
5812 | REG_RX_POWER_AFTER_IQK_A_2); | |
5813 | result[t][3] = (val32 >> 16) & 0x3ff; | |
5814 | ||
5815 | break; | |
5816 | } | |
5817 | } | |
5818 | ||
5819 | if (!path_a_ok) | |
5820 | dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); | |
5821 | ||
5822 | if (priv->rf_paths > 1) { | |
5823 | dev_warn(dev, "%s: Path B ongoing\n", __func__); | |
5824 | ||
5825 | /* Path A into standby */ | |
5826 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5827 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); | |
5828 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5829 | ||
5830 | /* Turn Path B ADDA on */ | |
5831 | rtl8xxxu_path_adda_on(priv, adda_regs, false); | |
5832 | ||
5833 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); | |
5834 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); | |
5835 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); | |
5836 | ||
5837 | for (i = 0; i < retry; i++) { | |
5838 | path_b_ok = rtl8192eu_iqk_path_b(priv); | |
5839 | if (path_b_ok == 0x01) { | |
5840 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); | |
5841 | result[t][4] = (val32 >> 16) & 0x3ff; | |
5842 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); | |
5843 | result[t][5] = (val32 >> 16) & 0x3ff; | |
5844 | break; | |
5845 | } | |
5846 | } | |
5847 | ||
5848 | if (!path_b_ok) | |
5849 | dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); | |
5850 | ||
5851 | for (i = 0; i < retry; i++) { | |
5852 | path_b_ok = rtl8192eu_rx_iqk_path_b(priv); | |
5853 | if (path_a_ok == 0x03) { | |
5854 | val32 = rtl8xxxu_read32(priv, | |
5855 | REG_RX_POWER_BEFORE_IQK_B_2); | |
5856 | result[t][6] = (val32 >> 16) & 0x3ff; | |
5857 | val32 = rtl8xxxu_read32(priv, | |
5858 | REG_RX_POWER_AFTER_IQK_B_2); | |
5859 | result[t][7] = (val32 >> 16) & 0x3ff; | |
5860 | break; | |
5861 | } | |
5862 | } | |
5863 | ||
5864 | if (!path_b_ok) | |
5865 | dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); | |
5866 | } | |
5867 | ||
5868 | /* Back to BB mode, load original value */ | |
5869 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); | |
5870 | ||
5871 | if (t) { | |
5872 | /* Reload ADDA power saving parameters */ | |
5873 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, | |
5874 | RTL8XXXU_ADDA_REGS); | |
5875 | ||
5876 | /* Reload MAC parameters */ | |
5877 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); | |
5878 | ||
5879 | /* Reload BB parameters */ | |
5880 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, | |
5881 | priv->bb_backup, RTL8XXXU_BB_REGS); | |
5882 | ||
5883 | /* Restore RX initial gain */ | |
5884 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); | |
5885 | val32 &= 0xffffff00; | |
5886 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); | |
5887 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); | |
5888 | ||
5889 | if (priv->rf_paths > 1) { | |
5890 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); | |
5891 | val32 &= 0xffffff00; | |
5892 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, | |
5893 | val32 | 0x50); | |
5894 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, | |
5895 | val32 | xb_agc); | |
5896 | } | |
5897 | ||
5898 | /* Load 0xe30 IQC default value */ | |
5899 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); | |
5900 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); | |
5901 | } | |
5902 | } | |
5903 | ||
c7a5a190 JS |
5904 | static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) |
5905 | { | |
5906 | struct h2c_cmd h2c; | |
5907 | ||
5908 | if (priv->fops->mbox_ext_width < 4) | |
5909 | return; | |
5910 | ||
5911 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
5912 | h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; | |
5913 | h2c.bt_wlan_calibration.data = start; | |
5914 | ||
5915 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); | |
5916 | } | |
5917 | ||
e1547c53 | 5918 | static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
26f1fad2 JS |
5919 | { |
5920 | struct device *dev = &priv->udev->dev; | |
5921 | int result[4][8]; /* last is final result */ | |
5922 | int i, candidate; | |
5923 | bool path_a_ok, path_b_ok; | |
5924 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; | |
5925 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; | |
5926 | s32 reg_tmp = 0; | |
5927 | bool simu; | |
5928 | ||
c7a5a190 JS |
5929 | rtl8xxxu_prepare_calibrate(priv, 1); |
5930 | ||
26f1fad2 JS |
5931 | memset(result, 0, sizeof(result)); |
5932 | candidate = -1; | |
5933 | ||
5934 | path_a_ok = false; | |
5935 | path_b_ok = false; | |
5936 | ||
5937 | rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
5938 | ||
5939 | for (i = 0; i < 3; i++) { | |
5940 | rtl8xxxu_phy_iqcalibrate(priv, result, i); | |
5941 | ||
5942 | if (i == 1) { | |
5943 | simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); | |
5944 | if (simu) { | |
5945 | candidate = 0; | |
5946 | break; | |
5947 | } | |
5948 | } | |
5949 | ||
5950 | if (i == 2) { | |
5951 | simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); | |
5952 | if (simu) { | |
5953 | candidate = 0; | |
5954 | break; | |
5955 | } | |
5956 | ||
5957 | simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); | |
5958 | if (simu) { | |
5959 | candidate = 1; | |
5960 | } else { | |
5961 | for (i = 0; i < 8; i++) | |
5962 | reg_tmp += result[3][i]; | |
5963 | ||
5964 | if (reg_tmp) | |
5965 | candidate = 3; | |
5966 | else | |
5967 | candidate = -1; | |
5968 | } | |
5969 | } | |
5970 | } | |
5971 | ||
5972 | for (i = 0; i < 4; i++) { | |
5973 | reg_e94 = result[i][0]; | |
5974 | reg_e9c = result[i][1]; | |
5975 | reg_ea4 = result[i][2]; | |
5976 | reg_eac = result[i][3]; | |
5977 | reg_eb4 = result[i][4]; | |
5978 | reg_ebc = result[i][5]; | |
5979 | reg_ec4 = result[i][6]; | |
5980 | reg_ecc = result[i][7]; | |
5981 | } | |
5982 | ||
5983 | if (candidate >= 0) { | |
5984 | reg_e94 = result[candidate][0]; | |
5985 | priv->rege94 = reg_e94; | |
5986 | reg_e9c = result[candidate][1]; | |
5987 | priv->rege9c = reg_e9c; | |
5988 | reg_ea4 = result[candidate][2]; | |
5989 | reg_eac = result[candidate][3]; | |
5990 | reg_eb4 = result[candidate][4]; | |
5991 | priv->regeb4 = reg_eb4; | |
5992 | reg_ebc = result[candidate][5]; | |
5993 | priv->regebc = reg_ebc; | |
5994 | reg_ec4 = result[candidate][6]; | |
5995 | reg_ecc = result[candidate][7]; | |
5996 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); | |
5997 | dev_dbg(dev, | |
5998 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " | |
5999 | "ecc=%x\n ", __func__, reg_e94, reg_e9c, | |
6000 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); | |
6001 | path_a_ok = true; | |
6002 | path_b_ok = true; | |
6003 | } else { | |
6004 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; | |
6005 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; | |
6006 | } | |
6007 | ||
6008 | if (reg_e94 && candidate >= 0) | |
6009 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, | |
6010 | candidate, (reg_ea4 == 0)); | |
6011 | ||
6012 | if (priv->tx_paths > 1 && reg_eb4) | |
6013 | rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, | |
6014 | candidate, (reg_ec4 == 0)); | |
6015 | ||
6016 | rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg, | |
6017 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); | |
c7a5a190 JS |
6018 | |
6019 | rtl8xxxu_prepare_calibrate(priv, 0); | |
26f1fad2 JS |
6020 | } |
6021 | ||
e1547c53 JS |
6022 | static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
6023 | { | |
6024 | struct device *dev = &priv->udev->dev; | |
6025 | int result[4][8]; /* last is final result */ | |
6026 | int i, candidate; | |
6027 | bool path_a_ok, path_b_ok; | |
6028 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; | |
6029 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; | |
6030 | u32 val32, bt_control; | |
6031 | s32 reg_tmp = 0; | |
6032 | bool simu; | |
6033 | ||
6034 | rtl8xxxu_prepare_calibrate(priv, 1); | |
6035 | ||
6036 | memset(result, 0, sizeof(result)); | |
6037 | candidate = -1; | |
6038 | ||
6039 | path_a_ok = false; | |
6040 | path_b_ok = false; | |
6041 | ||
6042 | bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); | |
6043 | ||
6044 | for (i = 0; i < 3; i++) { | |
6045 | rtl8723bu_phy_iqcalibrate(priv, result, i); | |
6046 | ||
6047 | if (i == 1) { | |
6048 | simu = rtl8723bu_simularity_compare(priv, result, 0, 1); | |
6049 | if (simu) { | |
6050 | candidate = 0; | |
6051 | break; | |
6052 | } | |
6053 | } | |
6054 | ||
6055 | if (i == 2) { | |
6056 | simu = rtl8723bu_simularity_compare(priv, result, 0, 2); | |
6057 | if (simu) { | |
6058 | candidate = 0; | |
6059 | break; | |
6060 | } | |
6061 | ||
6062 | simu = rtl8723bu_simularity_compare(priv, result, 1, 2); | |
6063 | if (simu) { | |
6064 | candidate = 1; | |
6065 | } else { | |
6066 | for (i = 0; i < 8; i++) | |
6067 | reg_tmp += result[3][i]; | |
6068 | ||
6069 | if (reg_tmp) | |
6070 | candidate = 3; | |
6071 | else | |
6072 | candidate = -1; | |
6073 | } | |
6074 | } | |
6075 | } | |
6076 | ||
6077 | for (i = 0; i < 4; i++) { | |
6078 | reg_e94 = result[i][0]; | |
6079 | reg_e9c = result[i][1]; | |
6080 | reg_ea4 = result[i][2]; | |
6081 | reg_eac = result[i][3]; | |
6082 | reg_eb4 = result[i][4]; | |
6083 | reg_ebc = result[i][5]; | |
6084 | reg_ec4 = result[i][6]; | |
6085 | reg_ecc = result[i][7]; | |
6086 | } | |
6087 | ||
6088 | if (candidate >= 0) { | |
6089 | reg_e94 = result[candidate][0]; | |
6090 | priv->rege94 = reg_e94; | |
6091 | reg_e9c = result[candidate][1]; | |
6092 | priv->rege9c = reg_e9c; | |
6093 | reg_ea4 = result[candidate][2]; | |
6094 | reg_eac = result[candidate][3]; | |
6095 | reg_eb4 = result[candidate][4]; | |
6096 | priv->regeb4 = reg_eb4; | |
6097 | reg_ebc = result[candidate][5]; | |
6098 | priv->regebc = reg_ebc; | |
6099 | reg_ec4 = result[candidate][6]; | |
6100 | reg_ecc = result[candidate][7]; | |
6101 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); | |
6102 | dev_dbg(dev, | |
6103 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " | |
6104 | "ecc=%x\n ", __func__, reg_e94, reg_e9c, | |
6105 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); | |
6106 | path_a_ok = true; | |
6107 | path_b_ok = true; | |
6108 | } else { | |
6109 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; | |
6110 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; | |
6111 | } | |
6112 | ||
6113 | if (reg_e94 && candidate >= 0) | |
6114 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, | |
6115 | candidate, (reg_ea4 == 0)); | |
6116 | ||
6117 | if (priv->tx_paths > 1 && reg_eb4) | |
6118 | rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, | |
6119 | candidate, (reg_ec4 == 0)); | |
6120 | ||
6121 | rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg, | |
6122 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); | |
6123 | ||
6124 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); | |
6125 | ||
6126 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); | |
6127 | val32 |= 0x80000; | |
6128 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); | |
6129 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); | |
6130 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); | |
6131 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); | |
6132 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); | |
6133 | val32 |= 0x20; | |
6134 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); | |
6135 | rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); | |
6136 | ||
6137 | if (priv->rf_paths > 1) { | |
6138 | dev_dbg(dev, "%s: beware 2T not yet supported\n", __func__); | |
6139 | #ifdef RTL8723BU_PATH_B | |
6140 | if (RF_Path == 0x0) //S1 | |
6141 | ODM_SetIQCbyRFpath(pDM_Odm, 0); | |
6142 | else //S0 | |
6143 | ODM_SetIQCbyRFpath(pDM_Odm, 1); | |
6144 | #endif | |
6145 | } | |
6146 | rtl8xxxu_prepare_calibrate(priv, 0); | |
6147 | } | |
6148 | ||
f991f4e9 JS |
6149 | static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
6150 | { | |
6151 | struct device *dev = &priv->udev->dev; | |
6152 | int result[4][8]; /* last is final result */ | |
6153 | int i, candidate; | |
6154 | bool path_a_ok, path_b_ok; | |
6155 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; | |
6156 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; | |
6157 | bool simu; | |
6158 | ||
6159 | memset(result, 0, sizeof(result)); | |
6160 | candidate = -1; | |
6161 | ||
6162 | path_a_ok = false; | |
6163 | path_b_ok = false; | |
6164 | ||
6165 | for (i = 0; i < 3; i++) { | |
6166 | rtl8192eu_phy_iqcalibrate(priv, result, i); | |
6167 | ||
6168 | if (i == 1) { | |
6169 | simu = rtl8723bu_simularity_compare(priv, result, 0, 1); | |
6170 | if (simu) { | |
6171 | candidate = 0; | |
6172 | break; | |
6173 | } | |
6174 | } | |
6175 | ||
6176 | if (i == 2) { | |
6177 | simu = rtl8723bu_simularity_compare(priv, result, 0, 2); | |
6178 | if (simu) { | |
6179 | candidate = 0; | |
6180 | break; | |
6181 | } | |
6182 | ||
6183 | simu = rtl8723bu_simularity_compare(priv, result, 1, 2); | |
6184 | if (simu) | |
6185 | candidate = 1; | |
6186 | else | |
6187 | candidate = 3; | |
6188 | } | |
6189 | } | |
6190 | ||
6191 | for (i = 0; i < 4; i++) { | |
6192 | reg_e94 = result[i][0]; | |
6193 | reg_e9c = result[i][1]; | |
6194 | reg_ea4 = result[i][2]; | |
6195 | reg_eac = result[i][3]; | |
6196 | reg_eb4 = result[i][4]; | |
6197 | reg_ebc = result[i][5]; | |
6198 | reg_ec4 = result[i][6]; | |
6199 | reg_ecc = result[i][7]; | |
6200 | } | |
6201 | ||
6202 | if (candidate >= 0) { | |
6203 | reg_e94 = result[candidate][0]; | |
6204 | priv->rege94 = reg_e94; | |
6205 | reg_e9c = result[candidate][1]; | |
6206 | priv->rege9c = reg_e9c; | |
6207 | reg_ea4 = result[candidate][2]; | |
6208 | reg_eac = result[candidate][3]; | |
6209 | reg_eb4 = result[candidate][4]; | |
6210 | priv->regeb4 = reg_eb4; | |
6211 | reg_ebc = result[candidate][5]; | |
6212 | priv->regebc = reg_ebc; | |
6213 | reg_ec4 = result[candidate][6]; | |
6214 | reg_ecc = result[candidate][7]; | |
6215 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); | |
6216 | dev_dbg(dev, | |
6217 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " | |
6218 | "ecc=%x\n ", __func__, reg_e94, reg_e9c, | |
6219 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); | |
6220 | path_a_ok = true; | |
6221 | path_b_ok = true; | |
6222 | } else { | |
6223 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; | |
6224 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; | |
6225 | } | |
6226 | ||
6227 | if (reg_e94 && candidate >= 0) | |
6228 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, | |
6229 | candidate, (reg_ea4 == 0)); | |
6230 | ||
6231 | if (priv->rf_paths > 1) | |
6232 | rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, | |
6233 | candidate, (reg_ec4 == 0)); | |
6234 | ||
6235 | rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg, | |
6236 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); | |
6237 | } | |
6238 | ||
26f1fad2 JS |
6239 | static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) |
6240 | { | |
6241 | u32 val32; | |
6242 | u32 rf_amode, rf_bmode = 0, lstf; | |
6243 | ||
6244 | /* Check continuous TX and Packet TX */ | |
6245 | lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); | |
6246 | ||
6247 | if (lstf & OFDM_LSTF_MASK) { | |
6248 | /* Disable all continuous TX */ | |
6249 | val32 = lstf & ~OFDM_LSTF_MASK; | |
6250 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); | |
6251 | ||
6252 | /* Read original RF mode Path A */ | |
6253 | rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); | |
6254 | ||
6255 | /* Set RF mode to standby Path A */ | |
6256 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, | |
6257 | (rf_amode & 0x8ffff) | 0x10000); | |
6258 | ||
6259 | /* Path-B */ | |
6260 | if (priv->tx_paths > 1) { | |
6261 | rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, | |
6262 | RF6052_REG_AC); | |
6263 | ||
6264 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, | |
6265 | (rf_bmode & 0x8ffff) | 0x10000); | |
6266 | } | |
6267 | } else { | |
6268 | /* Deal with Packet TX case */ | |
6269 | /* block all queues */ | |
6270 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); | |
6271 | } | |
6272 | ||
6273 | /* Start LC calibration */ | |
0d698dec JS |
6274 | if (priv->fops->has_s0s1) |
6275 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); | |
26f1fad2 JS |
6276 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); |
6277 | val32 |= 0x08000; | |
6278 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); | |
6279 | ||
6280 | msleep(100); | |
6281 | ||
0d698dec JS |
6282 | if (priv->fops->has_s0s1) |
6283 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); | |
6284 | ||
26f1fad2 JS |
6285 | /* Restore original parameters */ |
6286 | if (lstf & OFDM_LSTF_MASK) { | |
6287 | /* Path-A */ | |
6288 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); | |
6289 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); | |
6290 | ||
6291 | /* Path-B */ | |
6292 | if (priv->tx_paths > 1) | |
6293 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, | |
6294 | rf_bmode); | |
6295 | } else /* Deal with Packet TX case */ | |
6296 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); | |
6297 | } | |
6298 | ||
6299 | static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) | |
6300 | { | |
6301 | int i; | |
6302 | u16 reg; | |
6303 | ||
6304 | reg = REG_MACID; | |
6305 | ||
6306 | for (i = 0; i < ETH_ALEN; i++) | |
6307 | rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); | |
6308 | ||
6309 | return 0; | |
6310 | } | |
6311 | ||
6312 | static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) | |
6313 | { | |
6314 | int i; | |
6315 | u16 reg; | |
6316 | ||
6317 | dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); | |
6318 | ||
6319 | reg = REG_BSSID; | |
6320 | ||
6321 | for (i = 0; i < ETH_ALEN; i++) | |
6322 | rtl8xxxu_write8(priv, reg + i, bssid[i]); | |
6323 | ||
6324 | return 0; | |
6325 | } | |
6326 | ||
6327 | static void | |
6328 | rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) | |
6329 | { | |
6330 | u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; | |
6331 | u8 max_agg = 0xf; | |
6332 | int i; | |
6333 | ||
6334 | ampdu_factor = 1 << (ampdu_factor + 2); | |
6335 | if (ampdu_factor > max_agg) | |
6336 | ampdu_factor = max_agg; | |
6337 | ||
6338 | for (i = 0; i < 4; i++) { | |
6339 | if ((vals[i] & 0xf0) > (ampdu_factor << 4)) | |
6340 | vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); | |
6341 | ||
6342 | if ((vals[i] & 0x0f) > ampdu_factor) | |
6343 | vals[i] = (vals[i] & 0xf0) | ampdu_factor; | |
6344 | ||
6345 | rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); | |
6346 | } | |
6347 | } | |
6348 | ||
6349 | static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) | |
6350 | { | |
6351 | u8 val8; | |
6352 | ||
6353 | val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); | |
6354 | val8 &= 0xf8; | |
6355 | val8 |= density; | |
6356 | rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); | |
6357 | } | |
6358 | ||
6359 | static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) | |
6360 | { | |
6361 | u8 val8; | |
6362 | int count, ret; | |
6363 | ||
6364 | /* Start of rtl8723AU_card_enable_flow */ | |
6365 | /* Act to Cardemu sequence*/ | |
6366 | /* Turn off RF */ | |
6367 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0); | |
6368 | ||
6369 | /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ | |
6370 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); | |
6371 | val8 &= ~LEDCFG2_DPDT_SELECT; | |
6372 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); | |
6373 | ||
6374 | /* 0x0005[1] = 1 turn off MAC by HW state machine*/ | |
6375 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6376 | val8 |= BIT(1); | |
6377 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6378 | ||
6379 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6380 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6381 | if ((val8 & BIT(1)) == 0) | |
6382 | break; | |
6383 | udelay(10); | |
6384 | } | |
6385 | ||
6386 | if (!count) { | |
6387 | dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", | |
6388 | __func__); | |
6389 | ret = -EBUSY; | |
6390 | goto exit; | |
6391 | } | |
6392 | ||
6393 | /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ | |
6394 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); | |
6395 | val8 |= SYS_ISO_ANALOG_IPS; | |
6396 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); | |
6397 | ||
6398 | /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ | |
6399 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); | |
6400 | val8 &= ~LDOA15_ENABLE; | |
6401 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); | |
6402 | ||
6403 | exit: | |
6404 | return ret; | |
6405 | } | |
6406 | ||
fe37d5f6 JS |
6407 | static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) |
6408 | { | |
6409 | u8 val8; | |
6410 | u16 val16; | |
6411 | u32 val32; | |
6412 | int count, ret; | |
6413 | ||
6414 | /* Turn off RF */ | |
6415 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0); | |
6416 | ||
6417 | /* Enable rising edge triggering interrupt */ | |
6418 | val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); | |
6419 | val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ; | |
6420 | rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); | |
6421 | ||
6422 | /* Release WLON reset 0x04[16]= 1*/ | |
6423 | val32 = rtl8xxxu_read32(priv, REG_GPIO_INTM); | |
6424 | val32 |= APS_FSMCO_WLON_RESET; | |
6425 | rtl8xxxu_write32(priv, REG_GPIO_INTM, val32); | |
6426 | ||
6427 | /* 0x0005[1] = 1 turn off MAC by HW state machine*/ | |
6428 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6429 | val8 |= BIT(1); | |
6430 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6431 | ||
6432 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6433 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6434 | if ((val8 & BIT(1)) == 0) | |
6435 | break; | |
6436 | udelay(10); | |
6437 | } | |
6438 | ||
6439 | if (!count) { | |
6440 | dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", | |
6441 | __func__); | |
6442 | ret = -EBUSY; | |
6443 | goto exit; | |
6444 | } | |
6445 | ||
6446 | /* Enable BT control XTAL setting */ | |
6447 | val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); | |
6448 | val8 &= ~AFE_MISC_WL_XTAL_CTRL; | |
6449 | rtl8xxxu_write8(priv, REG_AFE_MISC, val8); | |
6450 | ||
6451 | /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ | |
6452 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); | |
6453 | val8 |= SYS_ISO_ANALOG_IPS; | |
6454 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); | |
6455 | ||
6456 | /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ | |
6457 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); | |
6458 | val8 &= ~LDOA15_ENABLE; | |
6459 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); | |
6460 | ||
6461 | exit: | |
6462 | return ret; | |
6463 | } | |
6464 | ||
26f1fad2 JS |
6465 | static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) |
6466 | { | |
6467 | u8 val8; | |
6468 | u8 val32; | |
6469 | int count, ret; | |
6470 | ||
6471 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); | |
6472 | ||
6473 | /* | |
6474 | * Poll - wait for RX packet to complete | |
6475 | */ | |
6476 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6477 | val32 = rtl8xxxu_read32(priv, 0x5f8); | |
6478 | if (!val32) | |
6479 | break; | |
6480 | udelay(10); | |
6481 | } | |
6482 | ||
6483 | if (!count) { | |
6484 | dev_warn(&priv->udev->dev, | |
6485 | "%s: RX poll timed out (0x05f8)\n", __func__); | |
6486 | ret = -EBUSY; | |
6487 | goto exit; | |
6488 | } | |
6489 | ||
6490 | /* Disable CCK and OFDM, clock gated */ | |
6491 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); | |
6492 | val8 &= ~SYS_FUNC_BBRSTB; | |
6493 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); | |
6494 | ||
6495 | udelay(2); | |
6496 | ||
6497 | /* Reset baseband */ | |
6498 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); | |
6499 | val8 &= ~SYS_FUNC_BB_GLB_RSTN; | |
6500 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); | |
6501 | ||
6502 | /* Reset MAC TRX */ | |
6503 | val8 = rtl8xxxu_read8(priv, REG_CR); | |
6504 | val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; | |
6505 | rtl8xxxu_write8(priv, REG_CR, val8); | |
6506 | ||
6507 | /* Reset MAC TRX */ | |
6508 | val8 = rtl8xxxu_read8(priv, REG_CR + 1); | |
6509 | val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ | |
6510 | rtl8xxxu_write8(priv, REG_CR + 1, val8); | |
6511 | ||
6512 | /* Respond TX OK to scheduler */ | |
6513 | val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); | |
6514 | val8 |= DUAL_TSF_TX_OK; | |
6515 | rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); | |
6516 | ||
6517 | exit: | |
6518 | return ret; | |
6519 | } | |
6520 | ||
c05a9dbf | 6521 | static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv) |
26f1fad2 JS |
6522 | { |
6523 | u8 val8; | |
6524 | ||
6525 | /* Clear suspend enable and power down enable*/ | |
6526 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6527 | val8 &= ~(BIT(3) | BIT(7)); | |
6528 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6529 | ||
6530 | /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ | |
6531 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); | |
6532 | val8 &= ~BIT(0); | |
6533 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); | |
6534 | ||
6535 | /* 0x04[12:11] = 11 enable WL suspend*/ | |
6536 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6537 | val8 &= ~(BIT(3) | BIT(4)); | |
6538 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6539 | } | |
6540 | ||
c05a9dbf JS |
6541 | static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) |
6542 | { | |
6543 | u8 val8; | |
6544 | ||
6545 | /* Clear suspend enable and power down enable*/ | |
6546 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6547 | val8 &= ~(BIT(3) | BIT(4)); | |
6548 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6549 | } | |
6550 | ||
6551 | static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) | |
6552 | { | |
6553 | u8 val8; | |
6554 | u32 val32; | |
6555 | int count, ret = 0; | |
6556 | ||
6557 | /* disable HWPDN 0x04[15]=0*/ | |
6558 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6559 | val8 &= ~BIT(7); | |
6560 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6561 | ||
6562 | /* disable SW LPS 0x04[10]= 0 */ | |
6563 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6564 | val8 &= ~BIT(2); | |
6565 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6566 | ||
6567 | /* disable WL suspend*/ | |
6568 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6569 | val8 &= ~(BIT(3) | BIT(4)); | |
6570 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6571 | ||
6572 | /* wait till 0x04[17] = 1 power ready*/ | |
6573 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6574 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6575 | if (val32 & BIT(17)) | |
6576 | break; | |
6577 | ||
6578 | udelay(10); | |
6579 | } | |
6580 | ||
6581 | if (!count) { | |
6582 | ret = -EBUSY; | |
6583 | goto exit; | |
6584 | } | |
6585 | ||
6586 | /* We should be able to optimize the following three entries into one */ | |
6587 | ||
6588 | /* release WLON reset 0x04[16]= 1*/ | |
6589 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); | |
6590 | val8 |= BIT(0); | |
6591 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); | |
6592 | ||
6593 | /* set, then poll until 0 */ | |
6594 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6595 | val32 |= APS_FSMCO_MAC_ENABLE; | |
6596 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); | |
6597 | ||
6598 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6599 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6600 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { | |
6601 | ret = 0; | |
6602 | break; | |
6603 | } | |
6604 | udelay(10); | |
6605 | } | |
6606 | ||
6607 | if (!count) { | |
6608 | ret = -EBUSY; | |
6609 | goto exit; | |
6610 | } | |
6611 | ||
6612 | exit: | |
6613 | return ret; | |
6614 | } | |
6615 | ||
6616 | static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv) | |
26f1fad2 JS |
6617 | { |
6618 | u8 val8; | |
6619 | u32 val32; | |
6620 | int count, ret = 0; | |
6621 | ||
6622 | /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/ | |
6623 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); | |
6624 | val8 |= LDOA15_ENABLE; | |
6625 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); | |
6626 | ||
6627 | /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ | |
6628 | val8 = rtl8xxxu_read8(priv, 0x0067); | |
6629 | val8 &= ~BIT(4); | |
6630 | rtl8xxxu_write8(priv, 0x0067, val8); | |
6631 | ||
6632 | mdelay(1); | |
6633 | ||
6634 | /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ | |
6635 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); | |
6636 | val8 &= ~SYS_ISO_ANALOG_IPS; | |
6637 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); | |
6638 | ||
6639 | /* disable SW LPS 0x04[10]= 0 */ | |
6640 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6641 | val8 &= ~BIT(2); | |
6642 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6643 | ||
6644 | /* wait till 0x04[17] = 1 power ready*/ | |
6645 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6646 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6647 | if (val32 & BIT(17)) | |
6648 | break; | |
6649 | ||
6650 | udelay(10); | |
6651 | } | |
6652 | ||
6653 | if (!count) { | |
6654 | ret = -EBUSY; | |
6655 | goto exit; | |
6656 | } | |
6657 | ||
6658 | /* We should be able to optimize the following three entries into one */ | |
6659 | ||
6660 | /* release WLON reset 0x04[16]= 1*/ | |
6661 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); | |
6662 | val8 |= BIT(0); | |
6663 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); | |
6664 | ||
6665 | /* disable HWPDN 0x04[15]= 0*/ | |
6666 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6667 | val8 &= ~BIT(7); | |
6668 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6669 | ||
6670 | /* disable WL suspend*/ | |
6671 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6672 | val8 &= ~(BIT(3) | BIT(4)); | |
6673 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6674 | ||
6675 | /* set, then poll until 0 */ | |
6676 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6677 | val32 |= APS_FSMCO_MAC_ENABLE; | |
6678 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); | |
6679 | ||
6680 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6681 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6682 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { | |
6683 | ret = 0; | |
6684 | break; | |
6685 | } | |
6686 | udelay(10); | |
6687 | } | |
6688 | ||
6689 | if (!count) { | |
6690 | ret = -EBUSY; | |
6691 | goto exit; | |
6692 | } | |
6693 | ||
6694 | /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */ | |
6695 | /* | |
6696 | * Note: Vendor driver actually clears this bit, despite the | |
6697 | * documentation claims it's being set! | |
6698 | */ | |
6699 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); | |
6700 | val8 |= LEDCFG2_DPDT_SELECT; | |
6701 | val8 &= ~LEDCFG2_DPDT_SELECT; | |
6702 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); | |
6703 | ||
6704 | exit: | |
6705 | return ret; | |
6706 | } | |
6707 | ||
42836db1 JS |
6708 | static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) |
6709 | { | |
6710 | u8 val8; | |
6711 | u32 val32; | |
6712 | int count, ret = 0; | |
6713 | ||
6714 | /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */ | |
6715 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); | |
6716 | val8 |= LDOA15_ENABLE; | |
6717 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); | |
6718 | ||
6719 | /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ | |
6720 | val8 = rtl8xxxu_read8(priv, 0x0067); | |
6721 | val8 &= ~BIT(4); | |
6722 | rtl8xxxu_write8(priv, 0x0067, val8); | |
6723 | ||
6724 | mdelay(1); | |
6725 | ||
6726 | /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ | |
6727 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); | |
6728 | val8 &= ~SYS_ISO_ANALOG_IPS; | |
6729 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); | |
6730 | ||
6731 | /* Disable SW LPS 0x04[10]= 0 */ | |
6732 | val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); | |
6733 | val32 &= ~APS_FSMCO_SW_LPS; | |
6734 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); | |
6735 | ||
6736 | /* Wait until 0x04[17] = 1 power ready */ | |
6737 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6738 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6739 | if (val32 & BIT(17)) | |
6740 | break; | |
6741 | ||
6742 | udelay(10); | |
6743 | } | |
6744 | ||
6745 | if (!count) { | |
6746 | ret = -EBUSY; | |
6747 | goto exit; | |
6748 | } | |
6749 | ||
6750 | /* We should be able to optimize the following three entries into one */ | |
6751 | ||
6752 | /* Release WLON reset 0x04[16]= 1*/ | |
6753 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6754 | val32 |= APS_FSMCO_WLON_RESET; | |
6755 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); | |
6756 | ||
6757 | /* Disable HWPDN 0x04[15]= 0*/ | |
6758 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6759 | val32 &= ~APS_FSMCO_HW_POWERDOWN; | |
6760 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); | |
6761 | ||
6762 | /* Disable WL suspend*/ | |
6763 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6764 | val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); | |
6765 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); | |
6766 | ||
6767 | /* Set, then poll until 0 */ | |
6768 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6769 | val32 |= APS_FSMCO_MAC_ENABLE; | |
6770 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); | |
6771 | ||
6772 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { | |
6773 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); | |
6774 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { | |
6775 | ret = 0; | |
6776 | break; | |
6777 | } | |
6778 | udelay(10); | |
6779 | } | |
6780 | ||
6781 | if (!count) { | |
6782 | ret = -EBUSY; | |
6783 | goto exit; | |
6784 | } | |
6785 | ||
6786 | /* Enable WL control XTAL setting */ | |
6787 | val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); | |
6788 | val8 |= AFE_MISC_WL_XTAL_CTRL; | |
6789 | rtl8xxxu_write8(priv, REG_AFE_MISC, val8); | |
6790 | ||
6791 | /* Enable falling edge triggering interrupt */ | |
6792 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); | |
6793 | val8 |= BIT(1); | |
6794 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); | |
6795 | ||
6796 | /* Enable GPIO9 interrupt mode */ | |
6797 | val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); | |
6798 | val8 |= BIT(1); | |
6799 | rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); | |
6800 | ||
6801 | /* Enable GPIO9 input mode */ | |
6802 | val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); | |
6803 | val8 &= ~BIT(1); | |
6804 | rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); | |
6805 | ||
6806 | /* Enable HSISR GPIO[C:0] interrupt */ | |
6807 | val8 = rtl8xxxu_read8(priv, REG_HSIMR); | |
6808 | val8 |= BIT(0); | |
6809 | rtl8xxxu_write8(priv, REG_HSIMR, val8); | |
6810 | ||
6811 | /* Enable HSISR GPIO9 interrupt */ | |
6812 | val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); | |
6813 | val8 |= BIT(1); | |
6814 | rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); | |
6815 | ||
6816 | val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); | |
6817 | val8 |= MULTI_WIFI_HW_ROF_EN; | |
6818 | rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); | |
6819 | ||
6820 | /* For GPIO9 internal pull high setting BIT(14) */ | |
6821 | val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); | |
6822 | val8 |= BIT(6); | |
6823 | rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); | |
6824 | ||
6825 | exit: | |
6826 | return ret; | |
6827 | } | |
6828 | ||
26f1fad2 JS |
6829 | static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) |
6830 | { | |
6831 | u8 val8; | |
6832 | ||
6833 | /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ | |
6834 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); | |
6835 | ||
6836 | /* 0x04[12:11] = 01 enable WL suspend */ | |
6837 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6838 | val8 &= ~BIT(4); | |
6839 | val8 |= BIT(3); | |
6840 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6841 | ||
6842 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); | |
6843 | val8 |= BIT(7); | |
6844 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); | |
6845 | ||
6846 | /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ | |
6847 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); | |
6848 | val8 |= BIT(0); | |
6849 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); | |
6850 | ||
6851 | return 0; | |
6852 | } | |
6853 | ||
430b454c JS |
6854 | static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) |
6855 | { | |
145428ec | 6856 | struct device *dev = &priv->udev->dev; |
430b454c JS |
6857 | u32 val32; |
6858 | int retry, retval; | |
6859 | ||
6860 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); | |
6861 | ||
6862 | val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); | |
6863 | val32 |= RXPKT_NUM_RW_RELEASE_EN; | |
6864 | rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); | |
6865 | ||
6866 | retry = 100; | |
6867 | retval = -EBUSY; | |
6868 | ||
6869 | do { | |
6870 | val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); | |
6871 | if (val32 & RXPKT_NUM_RXDMA_IDLE) { | |
6872 | retval = 0; | |
6873 | break; | |
6874 | } | |
6875 | } while (retry--); | |
6876 | ||
6877 | rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); | |
6878 | rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); | |
6879 | mdelay(2); | |
145428ec JS |
6880 | |
6881 | if (!retry) | |
6882 | dev_warn(dev, "Failed to flush FIFO\n"); | |
430b454c JS |
6883 | |
6884 | return retval; | |
6885 | } | |
6886 | ||
26f1fad2 JS |
6887 | static int rtl8723au_power_on(struct rtl8xxxu_priv *priv) |
6888 | { | |
6889 | u8 val8; | |
6890 | u16 val16; | |
6891 | u32 val32; | |
6892 | int ret; | |
6893 | ||
6894 | /* | |
6895 | * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register | |
6896 | */ | |
6897 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); | |
6898 | ||
c05a9dbf | 6899 | rtl8723a_disabled_to_emu(priv); |
26f1fad2 | 6900 | |
c05a9dbf | 6901 | ret = rtl8723a_emu_to_active(priv); |
26f1fad2 JS |
6902 | if (ret) |
6903 | goto exit; | |
6904 | ||
6905 | /* | |
6906 | * 0x0004[19] = 1, reset 8051 | |
6907 | */ | |
6908 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); | |
6909 | val8 |= BIT(3); | |
6910 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); | |
6911 | ||
6912 | /* | |
6913 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block | |
6914 | * Set CR bit10 to enable 32k calibration. | |
6915 | */ | |
6916 | val16 = rtl8xxxu_read16(priv, REG_CR); | |
6917 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | | |
6918 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | | |
6919 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | | |
6920 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | | |
6921 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); | |
6922 | rtl8xxxu_write16(priv, REG_CR, val16); | |
6923 | ||
6924 | /* For EFuse PG */ | |
6925 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); | |
6926 | val32 &= ~(BIT(28) | BIT(29) | BIT(30)); | |
6927 | val32 |= (0x06 << 28); | |
6928 | rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); | |
6929 | exit: | |
6930 | return ret; | |
6931 | } | |
6932 | ||
42836db1 JS |
6933 | static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) |
6934 | { | |
6935 | u8 val8; | |
6936 | u16 val16; | |
6937 | u32 val32; | |
6938 | int ret; | |
6939 | ||
6940 | rtl8723a_disabled_to_emu(priv); | |
6941 | ||
6942 | ret = rtl8723b_emu_to_active(priv); | |
6943 | if (ret) | |
6944 | goto exit; | |
6945 | ||
6946 | /* | |
6947 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block | |
6948 | * Set CR bit10 to enable 32k calibration. | |
6949 | */ | |
6950 | val16 = rtl8xxxu_read16(priv, REG_CR); | |
6951 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | | |
6952 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | | |
6953 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | | |
6954 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | | |
6955 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); | |
6956 | rtl8xxxu_write16(priv, REG_CR, val16); | |
6957 | ||
6958 | /* | |
6959 | * BT coexist power on settings. This is identical for 1 and 2 | |
6960 | * antenna parts. | |
6961 | */ | |
6962 | rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); | |
6963 | ||
6964 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
6965 | val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN; | |
6966 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
6967 | ||
6968 | rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); | |
6969 | rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); | |
6970 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); | |
6971 | /* Antenna inverse */ | |
6972 | rtl8xxxu_write8(priv, 0xfe08, 0x01); | |
6973 | ||
6974 | val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); | |
6975 | val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; | |
6976 | rtl8xxxu_write16(priv, REG_PWR_DATA, val16); | |
6977 | ||
6978 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); | |
6979 | val32 |= LEDCFG0_DPDT_SELECT; | |
6980 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); | |
6981 | ||
6982 | val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); | |
6983 | val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA; | |
6984 | rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); | |
6985 | exit: | |
6986 | return ret; | |
6987 | } | |
6988 | ||
c0963772 KV |
6989 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
6990 | ||
26f1fad2 JS |
6991 | static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) |
6992 | { | |
6993 | u8 val8; | |
6994 | u16 val16; | |
6995 | u32 val32; | |
6996 | int i; | |
6997 | ||
6998 | for (i = 100; i; i--) { | |
6999 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO); | |
7000 | if (val8 & APS_FSMCO_PFM_ALDN) | |
7001 | break; | |
7002 | } | |
7003 | ||
7004 | if (!i) { | |
7005 | pr_info("%s: Poll failed\n", __func__); | |
7006 | return -ENODEV; | |
7007 | } | |
7008 | ||
7009 | /* | |
7010 | * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register | |
7011 | */ | |
7012 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); | |
7013 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b); | |
7014 | udelay(100); | |
7015 | ||
7016 | val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL); | |
7017 | if (!(val8 & LDOV12D_ENABLE)) { | |
7018 | pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8); | |
7019 | val8 |= LDOV12D_ENABLE; | |
7020 | rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8); | |
7021 | ||
7022 | udelay(100); | |
7023 | ||
7024 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); | |
7025 | val8 &= ~SYS_ISO_MD2PP; | |
7026 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); | |
7027 | } | |
7028 | ||
7029 | /* | |
7030 | * Auto enable WLAN | |
7031 | */ | |
7032 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); | |
7033 | val16 |= APS_FSMCO_MAC_ENABLE; | |
7034 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); | |
7035 | ||
7036 | for (i = 1000; i; i--) { | |
7037 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); | |
7038 | if (!(val16 & APS_FSMCO_MAC_ENABLE)) | |
7039 | break; | |
7040 | } | |
7041 | if (!i) { | |
7042 | pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__); | |
7043 | return -EBUSY; | |
7044 | } | |
7045 | ||
7046 | /* | |
7047 | * Enable radio, GPIO, LED | |
7048 | */ | |
7049 | val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN | | |
7050 | APS_FSMCO_PFM_ALDN; | |
7051 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); | |
7052 | ||
7053 | /* | |
7054 | * Release RF digital isolation | |
7055 | */ | |
7056 | val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); | |
7057 | val16 &= ~SYS_ISO_DIOR; | |
7058 | rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); | |
7059 | ||
7060 | val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); | |
7061 | val8 &= ~APSD_CTRL_OFF; | |
7062 | rtl8xxxu_write8(priv, REG_APSD_CTRL, val8); | |
7063 | for (i = 200; i; i--) { | |
7064 | val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); | |
7065 | if (!(val8 & APSD_CTRL_OFF_STATUS)) | |
7066 | break; | |
7067 | } | |
7068 | ||
7069 | if (!i) { | |
7070 | pr_info("%s: APSD_CTRL poll failed\n", __func__); | |
7071 | return -EBUSY; | |
7072 | } | |
7073 | ||
7074 | /* | |
7075 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block | |
7076 | */ | |
7077 | val16 = rtl8xxxu_read16(priv, REG_CR); | |
7078 | val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | | |
7079 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE | | |
7080 | CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE; | |
7081 | rtl8xxxu_write16(priv, REG_CR, val16); | |
7082 | ||
7083 | /* | |
7084 | * Workaround for 8188RU LNA power leakage problem. | |
7085 | */ | |
ba17d824 | 7086 | if (priv->rtl_chip == RTL8188C && priv->hi_pa) { |
26f1fad2 JS |
7087 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); |
7088 | val32 &= ~BIT(1); | |
7089 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); | |
7090 | } | |
7091 | return 0; | |
7092 | } | |
7093 | ||
c0963772 KV |
7094 | #endif |
7095 | ||
28e460b0 JS |
7096 | /* |
7097 | * This is needed for 8723bu as well, presumable | |
7098 | */ | |
7099 | static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) | |
7100 | { | |
7101 | u8 val8; | |
7102 | u32 val32; | |
7103 | ||
7104 | /* | |
7105 | * 40Mhz crystal source, MAC 0x28[2]=0 | |
7106 | */ | |
7107 | val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); | |
7108 | val8 &= 0xfb; | |
7109 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); | |
7110 | ||
7111 | val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); | |
7112 | val32 &= 0xfffffc7f; | |
7113 | rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); | |
7114 | ||
7115 | /* | |
7116 | * 92e AFE parameter | |
7117 | * AFE PLL KVCO selection, MAC 0x28[6]=1 | |
7118 | */ | |
7119 | val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); | |
7120 | val8 &= 0xbf; | |
7121 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); | |
7122 | ||
7123 | /* | |
7124 | * AFE PLL KVCO selection, MAC 0x78[21]=0 | |
7125 | */ | |
7126 | val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); | |
7127 | val32 &= 0xffdfffff; | |
7128 | rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); | |
7129 | } | |
7130 | ||
c05a9dbf JS |
7131 | static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) |
7132 | { | |
7133 | u16 val16; | |
7134 | u32 val32; | |
7135 | int ret; | |
7136 | ||
7137 | ret = 0; | |
7138 | ||
7139 | val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); | |
7140 | if (val32 & SYS_CFG_SPS_LDO_SEL) { | |
7141 | rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); | |
7142 | } else { | |
7143 | /* | |
7144 | * Raise 1.2V voltage | |
7145 | */ | |
7146 | val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); | |
7147 | val32 &= 0xff0fffff; | |
7148 | val32 |= 0x00500000; | |
7149 | rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); | |
7150 | rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); | |
7151 | } | |
7152 | ||
28e460b0 JS |
7153 | /* |
7154 | * Adjust AFE before enabling PLL | |
7155 | */ | |
7156 | rtl8192e_crystal_afe_adjust(priv); | |
c05a9dbf JS |
7157 | rtl8192e_disabled_to_emu(priv); |
7158 | ||
7159 | ret = rtl8192e_emu_to_active(priv); | |
7160 | if (ret) | |
7161 | goto exit; | |
7162 | ||
7163 | rtl8xxxu_write16(priv, REG_CR, 0x0000); | |
7164 | ||
7165 | /* | |
7166 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block | |
7167 | * Set CR bit10 to enable 32k calibration. | |
7168 | */ | |
7169 | val16 = rtl8xxxu_read16(priv, REG_CR); | |
7170 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | | |
7171 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | | |
7172 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | | |
7173 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | | |
7174 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); | |
7175 | rtl8xxxu_write16(priv, REG_CR, val16); | |
7176 | ||
7177 | exit: | |
7178 | return ret; | |
7179 | } | |
7180 | ||
26f1fad2 JS |
7181 | static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) |
7182 | { | |
7183 | u8 val8; | |
7184 | u16 val16; | |
7185 | u32 val32; | |
7186 | ||
7187 | /* | |
7188 | * Workaround for 8188RU LNA power leakage problem. | |
7189 | */ | |
ba17d824 | 7190 | if (priv->rtl_chip == RTL8188C && priv->hi_pa) { |
26f1fad2 JS |
7191 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); |
7192 | val32 |= BIT(1); | |
7193 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); | |
7194 | } | |
7195 | ||
430b454c JS |
7196 | rtl8xxxu_flush_fifo(priv); |
7197 | ||
26f1fad2 JS |
7198 | rtl8xxxu_active_to_lps(priv); |
7199 | ||
7200 | /* Turn off RF */ | |
7201 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); | |
7202 | ||
7203 | /* Reset Firmware if running in RAM */ | |
7204 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) | |
7205 | rtl8xxxu_firmware_self_reset(priv); | |
7206 | ||
7207 | /* Reset MCU */ | |
7208 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
7209 | val16 &= ~SYS_FUNC_CPU_ENABLE; | |
7210 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
7211 | ||
7212 | /* Reset MCU ready status */ | |
7213 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); | |
7214 | ||
7215 | rtl8xxxu_active_to_emu(priv); | |
7216 | rtl8xxxu_emu_to_disabled(priv); | |
7217 | ||
7218 | /* Reset MCU IO Wrapper */ | |
7219 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); | |
7220 | val8 &= ~BIT(0); | |
7221 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); | |
7222 | ||
7223 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); | |
7224 | val8 |= BIT(0); | |
7225 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); | |
7226 | ||
7227 | /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ | |
7228 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); | |
7229 | } | |
7230 | ||
fe37d5f6 JS |
7231 | static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) |
7232 | { | |
7233 | u8 val8; | |
7234 | u16 val16; | |
7235 | ||
430b454c JS |
7236 | rtl8xxxu_flush_fifo(priv); |
7237 | ||
fe37d5f6 JS |
7238 | /* |
7239 | * Disable TX report timer | |
7240 | */ | |
7241 | val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); | |
7242 | val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; | |
7243 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); | |
7244 | ||
7245 | rtl8xxxu_write16(priv, REG_CR, 0x0000); | |
7246 | ||
7247 | rtl8xxxu_active_to_lps(priv); | |
7248 | ||
7249 | /* Reset Firmware if running in RAM */ | |
7250 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) | |
7251 | rtl8xxxu_firmware_self_reset(priv); | |
7252 | ||
7253 | /* Reset MCU */ | |
7254 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); | |
7255 | val16 &= ~SYS_FUNC_CPU_ENABLE; | |
7256 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); | |
7257 | ||
7258 | /* Reset MCU ready status */ | |
7259 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); | |
7260 | ||
7261 | rtl8723bu_active_to_emu(priv); | |
7262 | rtl8xxxu_emu_to_disabled(priv); | |
7263 | } | |
7264 | ||
a3a5dac6 | 7265 | #ifdef NEED_PS_TDMA |
3ca7b32c JS |
7266 | static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, |
7267 | u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) | |
7268 | { | |
7269 | struct h2c_cmd h2c; | |
7270 | ||
7271 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
7272 | h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; | |
7273 | h2c.b_type_dma.data1 = arg1; | |
7274 | h2c.b_type_dma.data2 = arg2; | |
7275 | h2c.b_type_dma.data3 = arg3; | |
7276 | h2c.b_type_dma.data4 = arg4; | |
7277 | h2c.b_type_dma.data5 = arg5; | |
7278 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); | |
7279 | } | |
a3a5dac6 | 7280 | #endif |
3ca7b32c | 7281 | |
0290e7d0 | 7282 | static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) |
26f1fad2 | 7283 | { |
f37e9228 JS |
7284 | struct h2c_cmd h2c; |
7285 | u32 val32; | |
7286 | u8 val8; | |
7287 | ||
7288 | /* | |
7289 | * No indication anywhere as to what 0x0790 does. The 2 antenna | |
7290 | * vendor code preserves bits 6-7 here. | |
7291 | */ | |
7292 | rtl8xxxu_write8(priv, 0x0790, 0x05); | |
7293 | /* | |
7294 | * 0x0778 seems to be related to enabling the number of antennas | |
7295 | * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it | |
7296 | * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01 | |
7297 | */ | |
7298 | rtl8xxxu_write8(priv, 0x0778, 0x01); | |
7299 | ||
7300 | val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); | |
7301 | val8 |= BIT(5); | |
7302 | rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); | |
7303 | ||
7304 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); | |
7305 | ||
394f1bd3 JS |
7306 | rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ |
7307 | ||
f37e9228 JS |
7308 | /* |
7309 | * Set BT grant to low | |
7310 | */ | |
7311 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
7312 | h2c.bt_grant.cmd = H2C_8723B_BT_GRANT; | |
7313 | h2c.bt_grant.data = 0; | |
7314 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); | |
7315 | ||
7316 | /* | |
7317 | * WLAN action by PTA | |
7318 | */ | |
fc1c89b3 | 7319 | rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); |
f37e9228 JS |
7320 | |
7321 | /* | |
7322 | * BT select S0/S1 controlled by WiFi | |
7323 | */ | |
7324 | val8 = rtl8xxxu_read8(priv, 0x0067); | |
7325 | val8 |= BIT(5); | |
7326 | rtl8xxxu_write8(priv, 0x0067, val8); | |
7327 | ||
7328 | val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); | |
37f44dc7 | 7329 | val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; |
f37e9228 JS |
7330 | rtl8xxxu_write32(priv, REG_PWR_DATA, val32); |
7331 | ||
7332 | /* | |
7333 | * Bits 6/7 are marked in/out ... but for what? | |
7334 | */ | |
7335 | rtl8xxxu_write8(priv, 0x0974, 0xff); | |
7336 | ||
120e627f | 7337 | val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); |
f37e9228 | 7338 | val32 |= (BIT(0) | BIT(1)); |
120e627f | 7339 | rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); |
f37e9228 JS |
7340 | |
7341 | rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); | |
7342 | ||
7343 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); | |
7344 | val32 &= ~BIT(24); | |
7345 | val32 |= BIT(23); | |
7346 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); | |
7347 | ||
7348 | /* | |
7349 | * Fix external switch Main->S1, Aux->S0 | |
7350 | */ | |
7351 | val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); | |
7352 | val8 &= ~BIT(0); | |
7353 | rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); | |
7354 | ||
7355 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
7356 | h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV; | |
7357 | h2c.ant_sel_rsv.ant_inverse = 1; | |
7358 | h2c.ant_sel_rsv.int_switch_type = 0; | |
7359 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); | |
7360 | ||
7361 | /* | |
7362 | * 0x280, 0x00, 0x200, 0x80 - not clear | |
7363 | */ | |
3ca7b32c JS |
7364 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
7365 | ||
7366 | /* | |
7367 | * Software control, antenna at WiFi side | |
7368 | */ | |
a3a5dac6 | 7369 | #ifdef NEED_PS_TDMA |
a228a5db | 7370 | rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); |
a3a5dac6 JS |
7371 | #endif |
7372 | ||
7373 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); | |
7374 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); | |
7375 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); | |
7376 | rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); | |
3ca7b32c | 7377 | |
6b9eae01 JS |
7378 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
7379 | h2c.bt_info.cmd = H2C_8723B_BT_INFO; | |
7380 | h2c.bt_info.data = BIT(0); | |
7381 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); | |
7382 | ||
6b9eae01 JS |
7383 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
7384 | h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT; | |
7385 | h2c.ignore_wlan.data = 0; | |
7386 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); | |
26f1fad2 JS |
7387 | } |
7388 | ||
fc89a41f JS |
7389 | static void rtl8723b_disable_rf(struct rtl8xxxu_priv *priv) |
7390 | { | |
7391 | u32 val32; | |
7392 | ||
7393 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); | |
7394 | ||
7395 | val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); | |
7396 | val32 &= ~(BIT(22) | BIT(23)); | |
7397 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); | |
7398 | } | |
7399 | ||
3e88ca44 JS |
7400 | static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) |
7401 | { | |
7402 | u32 agg_rx; | |
7403 | u8 agg_ctrl; | |
7404 | ||
7405 | /* | |
7406 | * For now simply disable RX aggregation | |
7407 | */ | |
7408 | agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); | |
7409 | agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; | |
7410 | ||
7411 | agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); | |
7412 | agg_rx &= ~RXDMA_USB_AGG_ENABLE; | |
7413 | agg_rx &= ~0xff0f; | |
7414 | ||
7415 | rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); | |
7416 | rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); | |
7417 | } | |
7418 | ||
9c79bf95 JS |
7419 | static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) |
7420 | { | |
7421 | u32 val32; | |
7422 | ||
7423 | /* Time duration for NHM unit: 4us, 0x2710=40ms */ | |
7424 | rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); | |
7425 | rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); | |
7426 | rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); | |
7427 | rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); | |
7428 | /* TH8 */ | |
7429 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); | |
7430 | val32 |= 0xff; | |
7431 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); | |
7432 | /* Enable CCK */ | |
7433 | val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); | |
7434 | val32 |= BIT(8) | BIT(9) | BIT(10); | |
7435 | rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); | |
7436 | /* Max power amongst all RX antennas */ | |
7437 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); | |
7438 | val32 |= BIT(7); | |
7439 | rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); | |
7440 | } | |
7441 | ||
89c2a097 JS |
7442 | static void rtl8xxxu_old_init_queue_reserved_page(struct rtl8xxxu_priv *priv) |
7443 | { | |
7444 | u8 val8; | |
7445 | u32 val32; | |
7446 | ||
7447 | if (priv->ep_tx_normal_queue) | |
7448 | val8 = TX_PAGE_NUM_NORM_PQ; | |
7449 | else | |
7450 | val8 = 0; | |
7451 | ||
7452 | rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8); | |
7453 | ||
7454 | val32 = (TX_PAGE_NUM_PUBQ << RQPN_PUB_PQ_SHIFT) | RQPN_LOAD; | |
7455 | ||
7456 | if (priv->ep_tx_high_queue) | |
7457 | val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT); | |
7458 | if (priv->ep_tx_low_queue) | |
7459 | val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT); | |
7460 | ||
7461 | rtl8xxxu_write32(priv, REG_RQPN, val32); | |
7462 | } | |
7463 | ||
7464 | static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) | |
7465 | { | |
7466 | struct rtl8xxxu_fileops *fops = priv->fops; | |
7467 | u32 hq, lq, nq, eq, pubq; | |
7468 | u32 val32; | |
7469 | ||
7470 | hq = 0; | |
7471 | lq = 0; | |
7472 | nq = 0; | |
7473 | eq = 0; | |
7474 | pubq = 0; | |
7475 | ||
7476 | if (priv->ep_tx_high_queue) | |
7477 | hq = fops->page_num_hi; | |
7478 | if (priv->ep_tx_low_queue) | |
7479 | lq = fops->page_num_lo; | |
7480 | if (priv->ep_tx_normal_queue) | |
7481 | nq = fops->page_num_norm; | |
7482 | ||
7483 | val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); | |
7484 | rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); | |
7485 | ||
7486 | pubq = fops->total_page_num - hq - lq - nq; | |
7487 | ||
7488 | val32 = RQPN_LOAD; | |
7489 | val32 |= (hq << RQPN_HI_PQ_SHIFT); | |
7490 | val32 |= (lq << RQPN_LO_PQ_SHIFT); | |
7491 | val32 |= (pubq << RQPN_PUB_PQ_SHIFT); | |
7492 | ||
7493 | rtl8xxxu_write32(priv, REG_RQPN, val32); | |
7494 | } | |
7495 | ||
26f1fad2 JS |
7496 | static int rtl8xxxu_init_device(struct ieee80211_hw *hw) |
7497 | { | |
7498 | struct rtl8xxxu_priv *priv = hw->priv; | |
7499 | struct device *dev = &priv->udev->dev; | |
7500 | struct rtl8xxxu_rfregval *rftable; | |
7501 | bool macpower; | |
7502 | int ret; | |
7503 | u8 val8; | |
7504 | u16 val16; | |
7505 | u32 val32; | |
7506 | ||
7507 | /* Check if MAC is already powered on */ | |
7508 | val8 = rtl8xxxu_read8(priv, REG_CR); | |
7509 | ||
7510 | /* | |
7511 | * Fix 92DU-VC S3 hang with the reason is that secondary mac is not | |
7512 | * initialized. First MAC returns 0xea, second MAC returns 0x00 | |
7513 | */ | |
7514 | if (val8 == 0xea) | |
7515 | macpower = false; | |
7516 | else | |
7517 | macpower = true; | |
7518 | ||
7519 | ret = priv->fops->power_on(priv); | |
7520 | if (ret < 0) { | |
7521 | dev_warn(dev, "%s: Failed power on\n", __func__); | |
7522 | goto exit; | |
7523 | } | |
7524 | ||
07bb46be | 7525 | if (!macpower) { |
89c2a097 JS |
7526 | if (priv->fops->total_page_num) |
7527 | rtl8xxxu_init_queue_reserved_page(priv); | |
59b24dad | 7528 | else |
89c2a097 | 7529 | rtl8xxxu_old_init_queue_reserved_page(priv); |
07bb46be JS |
7530 | } |
7531 | ||
59b24dad JS |
7532 | ret = rtl8xxxu_init_queue_priority(priv); |
7533 | dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); | |
7534 | if (ret) | |
7535 | goto exit; | |
7536 | ||
7537 | /* | |
7538 | * Set RX page boundary | |
7539 | */ | |
7540 | if (priv->rtl_chip == RTL8723B) | |
7541 | rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3f7f); | |
7542 | else if (priv->rtl_chip == RTL8192E) | |
7543 | rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x3cff); | |
7544 | else | |
7545 | rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff); | |
7546 | ||
a47b9d47 JS |
7547 | ret = rtl8xxxu_download_firmware(priv); |
7548 | dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret); | |
7549 | if (ret) | |
7550 | goto exit; | |
7551 | ret = rtl8xxxu_start_firmware(priv); | |
7552 | dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret); | |
7553 | if (ret) | |
7554 | goto exit; | |
7555 | ||
6431ea00 JS |
7556 | /* Solve too many protocol error on USB bus */ |
7557 | /* Can't do this for 8188/8192 UMC A cut parts */ | |
ba17d824 JS |
7558 | if (priv->rtl_chip == RTL8723A || |
7559 | ((priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C || | |
7560 | priv->rtl_chip == RTL8188C) && | |
6431ea00 JS |
7561 | (priv->chip_cut || !priv->vendor_umc))) { |
7562 | rtl8xxxu_write8(priv, 0xfe40, 0xe6); | |
7563 | rtl8xxxu_write8(priv, 0xfe41, 0x94); | |
7564 | rtl8xxxu_write8(priv, 0xfe42, 0x80); | |
7565 | ||
7566 | rtl8xxxu_write8(priv, 0xfe40, 0xe0); | |
7567 | rtl8xxxu_write8(priv, 0xfe41, 0x19); | |
7568 | rtl8xxxu_write8(priv, 0xfe42, 0x80); | |
7569 | ||
7570 | rtl8xxxu_write8(priv, 0xfe40, 0xe5); | |
7571 | rtl8xxxu_write8(priv, 0xfe41, 0x91); | |
7572 | rtl8xxxu_write8(priv, 0xfe42, 0x80); | |
7573 | ||
7574 | rtl8xxxu_write8(priv, 0xfe40, 0xe2); | |
7575 | rtl8xxxu_write8(priv, 0xfe41, 0x81); | |
7576 | rtl8xxxu_write8(priv, 0xfe42, 0x80); | |
7577 | } | |
7578 | ||
f0d9f5e9 JS |
7579 | if (priv->fops->phy_init_antenna_selection) |
7580 | priv->fops->phy_init_antenna_selection(priv); | |
7581 | ||
c606e662 | 7582 | ret = rtl8xxxu_init_mac(priv); |
b7dd8ff9 | 7583 | |
26f1fad2 JS |
7584 | dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); |
7585 | if (ret) | |
7586 | goto exit; | |
7587 | ||
7588 | ret = rtl8xxxu_init_phy_bb(priv); | |
7589 | dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); | |
7590 | if (ret) | |
7591 | goto exit; | |
7592 | ||
ba17d824 JS |
7593 | switch(priv->rtl_chip) { |
7594 | case RTL8723A: | |
26f1fad2 JS |
7595 | rftable = rtl8723au_radioa_1t_init_table; |
7596 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); | |
7597 | break; | |
ba17d824 | 7598 | case RTL8723B: |
22a31d45 JS |
7599 | rftable = rtl8723bu_radioa_1t_init_table; |
7600 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); | |
5ac61789 JS |
7601 | /* |
7602 | * PHY LCK | |
7603 | */ | |
7604 | rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); | |
7605 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); | |
7606 | msleep(200); | |
7607 | rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); | |
22a31d45 | 7608 | break; |
ba17d824 | 7609 | case RTL8188C: |
26f1fad2 JS |
7610 | if (priv->hi_pa) |
7611 | rftable = rtl8188ru_radioa_1t_highpa_table; | |
7612 | else | |
7613 | rftable = rtl8192cu_radioa_1t_init_table; | |
7614 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); | |
7615 | break; | |
ba17d824 | 7616 | case RTL8191C: |
26f1fad2 JS |
7617 | rftable = rtl8192cu_radioa_1t_init_table; |
7618 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); | |
7619 | break; | |
ba17d824 | 7620 | case RTL8192C: |
26f1fad2 JS |
7621 | rftable = rtl8192cu_radioa_2t_init_table; |
7622 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); | |
7623 | if (ret) | |
7624 | break; | |
7625 | rftable = rtl8192cu_radiob_2t_init_table; | |
7626 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); | |
7627 | break; | |
19102f84 JS |
7628 | case RTL8192E: |
7629 | rftable = rtl8192eu_radioa_init_table; | |
7630 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); | |
7631 | if (ret) | |
7632 | break; | |
7633 | rftable = rtl8192eu_radiob_init_table; | |
7634 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); | |
7635 | break; | |
26f1fad2 JS |
7636 | default: |
7637 | ret = -EINVAL; | |
7638 | } | |
7639 | ||
7640 | if (ret) | |
7641 | goto exit; | |
7642 | ||
c157863d JS |
7643 | /* RFSW Control - clear bit 14 ?? */ |
7644 | if (priv->rtl_chip != RTL8723B) | |
7645 | rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); | |
7646 | /* 0x07000760 */ | |
7647 | if (priv->rtl_chip == RTL8192E) { | |
7648 | val32 = 0; | |
7649 | } else { | |
7650 | val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | | |
7651 | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE | | |
7652 | ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) << | |
7653 | FPGA0_RF_BD_CTRL_SHIFT); | |
7654 | } | |
7655 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); | |
7656 | /* 0x860[6:5]= 00 - why? - this sets antenna B */ | |
7657 | if (priv->rtl_chip != RTL8192E) | |
7658 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); | |
7659 | ||
7660 | priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A, | |
7661 | RF6052_REG_MODE_AG); | |
7662 | ||
2f109c8e JS |
7663 | /* |
7664 | * Chip specific quirks | |
7665 | */ | |
ba17d824 | 7666 | if (priv->rtl_chip == RTL8723A) { |
2f109c8e JS |
7667 | /* Fix USB interface interference issue */ |
7668 | rtl8xxxu_write8(priv, 0xfe40, 0xe0); | |
7669 | rtl8xxxu_write8(priv, 0xfe41, 0x8d); | |
7670 | rtl8xxxu_write8(priv, 0xfe42, 0x80); | |
7671 | rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); | |
7672 | ||
7673 | /* Reduce 80M spur */ | |
f30ed675 JS |
7674 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); |
7675 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); | |
7676 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); | |
7677 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); | |
2f109c8e JS |
7678 | } else { |
7679 | val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); | |
7680 | val32 |= TXDMA_OFFSET_DROP_DATA_EN; | |
7681 | rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); | |
f30ed675 | 7682 | } |
26f1fad2 | 7683 | |
f2a4163a | 7684 | if (!macpower) { |
1f1b20f1 JS |
7685 | /* |
7686 | * Set TX buffer boundary | |
7687 | */ | |
80805aa5 JS |
7688 | if (priv->rtl_chip == RTL8192E) |
7689 | val8 = TX_TOTAL_PAGE_NUM_8192E + 1; | |
7690 | else | |
7691 | val8 = TX_TOTAL_PAGE_NUM + 1; | |
1f1b20f1 | 7692 | |
ba17d824 | 7693 | if (priv->rtl_chip == RTL8723B) |
1f1b20f1 JS |
7694 | val8 -= 1; |
7695 | ||
7696 | rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); | |
7697 | rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); | |
7698 | rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); | |
7699 | rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); | |
7700 | rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); | |
7701 | } | |
7702 | ||
26f1fad2 JS |
7703 | /* |
7704 | * Transfer page size is always 128 | |
7705 | */ | |
ba17d824 | 7706 | if (priv->rtl_chip == RTL8723B) |
b87212ce JS |
7707 | val8 = (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_RX_SHIFT) | |
7708 | (PBP_PAGE_SIZE_256 << PBP_PAGE_SIZE_TX_SHIFT); | |
7709 | else | |
7710 | val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) | | |
7711 | (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT); | |
26f1fad2 JS |
7712 | rtl8xxxu_write8(priv, REG_PBP, val8); |
7713 | ||
59b24dad JS |
7714 | dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); |
7715 | if (!macpower) { | |
7716 | ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM); | |
7717 | if (ret) { | |
7718 | dev_warn(dev, "%s: LLT table init failed\n", __func__); | |
7719 | goto exit; | |
7720 | } | |
7721 | ||
7722 | /* | |
7723 | * Presumably this is for 8188EU as well | |
7724 | * Enable TX report and TX report timer | |
7725 | */ | |
7726 | if (priv->rtl_chip == RTL8723B) { | |
7727 | val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); | |
7728 | val8 |= TX_REPORT_CTRL_TIMER_ENABLE; | |
7729 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); | |
7730 | /* Set MAX RPT MACID */ | |
7731 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); | |
7732 | /* TX report Timer. Unit: 32us */ | |
7733 | rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); | |
7734 | ||
7735 | /* tmp ps ? */ | |
7736 | val8 = rtl8xxxu_read8(priv, 0xa3); | |
7737 | val8 &= 0xf8; | |
7738 | rtl8xxxu_write8(priv, 0xa3, val8); | |
7739 | } | |
7740 | } | |
7741 | ||
26f1fad2 JS |
7742 | /* |
7743 | * Unit in 8 bytes, not obvious what it is used for | |
7744 | */ | |
7745 | rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); | |
7746 | ||
57e5e2e6 JS |
7747 | if (priv->rtl_chip == RTL8192E) { |
7748 | rtl8xxxu_write32(priv, REG_HIMR0, 0x00); | |
7749 | rtl8xxxu_write32(priv, REG_HIMR1, 0x00); | |
7750 | } else { | |
7751 | /* | |
7752 | * Enable all interrupts - not obvious USB needs to do this | |
7753 | */ | |
7754 | rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); | |
7755 | rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); | |
7756 | } | |
26f1fad2 JS |
7757 | |
7758 | rtl8xxxu_set_mac(priv); | |
7759 | rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); | |
7760 | ||
7761 | /* | |
7762 | * Configure initial WMAC settings | |
7763 | */ | |
7764 | val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | | |
26f1fad2 JS |
7765 | RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | |
7766 | RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; | |
7767 | rtl8xxxu_write32(priv, REG_RCR, val32); | |
7768 | ||
7769 | /* | |
7770 | * Accept all multicast | |
7771 | */ | |
7772 | rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); | |
7773 | rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); | |
7774 | ||
7775 | /* | |
7776 | * Init adaptive controls | |
7777 | */ | |
7778 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); | |
7779 | val32 &= ~RESPONSE_RATE_BITMAP_ALL; | |
7780 | val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; | |
7781 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); | |
7782 | ||
7783 | /* CCK = 0x0a, OFDM = 0x10 */ | |
7784 | rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); | |
7785 | rtl8xxxu_set_retry(priv, 0x30, 0x30); | |
7786 | rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); | |
7787 | ||
7788 | /* | |
7789 | * Init EDCA | |
7790 | */ | |
7791 | rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); | |
7792 | ||
7793 | /* Set CCK SIFS */ | |
7794 | rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); | |
7795 | ||
7796 | /* Set OFDM SIFS */ | |
7797 | rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); | |
7798 | ||
7799 | /* TXOP */ | |
7800 | rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); | |
7801 | rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); | |
7802 | rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); | |
7803 | rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); | |
7804 | ||
7805 | /* Set data auto rate fallback retry count */ | |
7806 | rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); | |
7807 | rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); | |
7808 | rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); | |
7809 | rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); | |
7810 | ||
7811 | val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); | |
7812 | val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; | |
7813 | rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); | |
7814 | ||
7815 | /* Set ACK timeout */ | |
7816 | rtl8xxxu_write8(priv, REG_ACKTO, 0x40); | |
7817 | ||
7818 | /* | |
7819 | * Initialize beacon parameters | |
7820 | */ | |
7821 | val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); | |
7822 | rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); | |
7823 | rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); | |
7824 | rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); | |
7825 | rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); | |
7826 | rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); | |
7827 | ||
c3690604 JS |
7828 | /* |
7829 | * Initialize burst parameters | |
7830 | */ | |
ba17d824 | 7831 | if (priv->rtl_chip == RTL8723B) { |
c3690604 JS |
7832 | /* |
7833 | * For USB high speed set 512B packets | |
7834 | */ | |
7835 | val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); | |
7836 | val8 &= ~(BIT(4) | BIT(5)); | |
7837 | val8 |= BIT(4); | |
7838 | val8 |= BIT(1) | BIT(2) | BIT(3); | |
7839 | rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); | |
7840 | ||
7841 | /* | |
7842 | * For USB high speed set 512B packets | |
7843 | */ | |
7844 | val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); | |
7845 | val8 |= BIT(7); | |
7846 | rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); | |
7847 | ||
7848 | rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); | |
7849 | rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e); | |
7850 | rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); | |
7851 | rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); | |
7852 | rtl8xxxu_write8(priv, REG_PIFS, 0x00); | |
7853 | rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50); | |
7854 | rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50); | |
7855 | ||
7856 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); | |
7857 | val8 |= BIT(5) | BIT(6); | |
7858 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); | |
7859 | } | |
7860 | ||
3e88ca44 JS |
7861 | if (priv->fops->init_aggregation) |
7862 | priv->fops->init_aggregation(priv); | |
7863 | ||
26f1fad2 JS |
7864 | /* |
7865 | * Enable CCK and OFDM block | |
7866 | */ | |
7867 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
7868 | val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); | |
7869 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
7870 | ||
7871 | /* | |
7872 | * Invalidate all CAM entries - bit 30 is undocumented | |
7873 | */ | |
7874 | rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); | |
7875 | ||
7876 | /* | |
7877 | * Start out with default power levels for channel 6, 20MHz | |
7878 | */ | |
e796dab4 | 7879 | priv->fops->set_tx_power(priv, 1, false); |
26f1fad2 JS |
7880 | |
7881 | /* Let the 8051 take control of antenna setting */ | |
7882 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); | |
7883 | val8 |= LEDCFG2_DPDT_SELECT; | |
7884 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); | |
7885 | ||
7886 | rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); | |
7887 | ||
7888 | /* Disable BAR - not sure if this has any effect on USB */ | |
7889 | rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); | |
7890 | ||
7891 | rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); | |
7892 | ||
9c79bf95 JS |
7893 | if (priv->fops->init_statistics) |
7894 | priv->fops->init_statistics(priv); | |
7895 | ||
b052b7fc JS |
7896 | if (priv->rtl_chip == RTL8192E) { |
7897 | /* | |
7898 | * 0x4c6[3] 1: RTS BW = Data BW | |
7899 | * 0: RTS BW depends on CCA / secondary CCA result. | |
7900 | */ | |
7901 | val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); | |
7902 | val8 &= ~BIT(3); | |
7903 | rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); | |
7904 | /* | |
7905 | * Reset USB mode switch setting | |
7906 | */ | |
7907 | rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); | |
7908 | } | |
7909 | ||
fa0f2d48 JS |
7910 | rtl8723a_phy_lc_calibrate(priv); |
7911 | ||
e1547c53 | 7912 | priv->fops->phy_iq_calibrate(priv); |
26f1fad2 JS |
7913 | |
7914 | /* | |
7915 | * This should enable thermal meter | |
7916 | */ | |
72143b9e JS |
7917 | if (priv->fops->has_s0s1) |
7918 | rtl8xxxu_write_rfreg(priv, | |
7919 | RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); | |
7920 | else | |
7921 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); | |
26f1fad2 | 7922 | |
26f1fad2 JS |
7923 | /* Set NAV_UPPER to 30000us */ |
7924 | val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); | |
7925 | rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); | |
7926 | ||
ba17d824 | 7927 | if (priv->rtl_chip == RTL8723A) { |
4042e617 JS |
7928 | /* |
7929 | * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, | |
7930 | * but we need to find root cause. | |
7931 | * This is 8723au only. | |
7932 | */ | |
7933 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); | |
7934 | if ((val32 & 0xff000000) != 0x83000000) { | |
7935 | val32 |= FPGA_RF_MODE_CCK; | |
7936 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); | |
7937 | } | |
3021e51f JS |
7938 | } else if (priv->rtl_chip == RTL8192E) { |
7939 | rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); | |
26f1fad2 JS |
7940 | } |
7941 | ||
7942 | val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); | |
7943 | val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; | |
7944 | /* ack for xmit mgmt frames. */ | |
7945 | rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); | |
7946 | ||
e1394fe5 JS |
7947 | if (priv->rtl_chip == RTL8192E) { |
7948 | /* | |
7949 | * Fix LDPC rx hang issue. | |
7950 | */ | |
7951 | val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); | |
7952 | rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); | |
7953 | val32 &= 0xfff00fff; | |
7954 | val32 |= 0x0007e000; | |
7955 | rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); | |
7956 | } | |
26f1fad2 JS |
7957 | exit: |
7958 | return ret; | |
7959 | } | |
7960 | ||
7961 | static void rtl8xxxu_disable_device(struct ieee80211_hw *hw) | |
7962 | { | |
7963 | struct rtl8xxxu_priv *priv = hw->priv; | |
7964 | ||
fe37d5f6 | 7965 | priv->fops->power_off(priv); |
26f1fad2 JS |
7966 | } |
7967 | ||
7968 | static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, | |
7969 | struct ieee80211_key_conf *key, const u8 *mac) | |
7970 | { | |
7971 | u32 cmd, val32, addr, ctrl; | |
7972 | int j, i, tmp_debug; | |
7973 | ||
7974 | tmp_debug = rtl8xxxu_debug; | |
7975 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) | |
7976 | rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; | |
7977 | ||
7978 | /* | |
7979 | * This is a bit of a hack - the lower bits of the cipher | |
7980 | * suite selector happens to match the cipher index in the CAM | |
7981 | */ | |
7982 | addr = key->keyidx << CAM_CMD_KEY_SHIFT; | |
7983 | ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; | |
7984 | ||
7985 | for (j = 5; j >= 0; j--) { | |
7986 | switch (j) { | |
7987 | case 0: | |
7988 | val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); | |
7989 | break; | |
7990 | case 1: | |
7991 | val32 = mac[2] | (mac[3] << 8) | | |
7992 | (mac[4] << 16) | (mac[5] << 24); | |
7993 | break; | |
7994 | default: | |
7995 | i = (j - 2) << 2; | |
7996 | val32 = key->key[i] | (key->key[i + 1] << 8) | | |
7997 | key->key[i + 2] << 16 | key->key[i + 3] << 24; | |
7998 | break; | |
7999 | } | |
8000 | ||
8001 | rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); | |
8002 | cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); | |
8003 | rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); | |
8004 | udelay(100); | |
8005 | } | |
8006 | ||
8007 | rtl8xxxu_debug = tmp_debug; | |
8008 | } | |
8009 | ||
8010 | static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, | |
56e4374a | 8011 | struct ieee80211_vif *vif, const u8 *mac) |
26f1fad2 JS |
8012 | { |
8013 | struct rtl8xxxu_priv *priv = hw->priv; | |
8014 | u8 val8; | |
8015 | ||
8016 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); | |
8017 | val8 |= BEACON_DISABLE_TSF_UPDATE; | |
8018 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); | |
8019 | } | |
8020 | ||
8021 | static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, | |
8022 | struct ieee80211_vif *vif) | |
8023 | { | |
8024 | struct rtl8xxxu_priv *priv = hw->priv; | |
8025 | u8 val8; | |
8026 | ||
8027 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); | |
8028 | val8 &= ~BEACON_DISABLE_TSF_UPDATE; | |
8029 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); | |
8030 | } | |
8031 | ||
f653e690 JS |
8032 | static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv *priv, |
8033 | u32 ramask, int sgi) | |
26f1fad2 JS |
8034 | { |
8035 | struct h2c_cmd h2c; | |
8036 | ||
f653e690 JS |
8037 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
8038 | ||
26f1fad2 JS |
8039 | h2c.ramask.cmd = H2C_SET_RATE_MASK; |
8040 | h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); | |
8041 | h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); | |
8042 | ||
8043 | h2c.ramask.arg = 0x80; | |
8044 | if (sgi) | |
8045 | h2c.ramask.arg |= 0x20; | |
8046 | ||
7ff8c1ae | 8047 | dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", |
8da91571 JS |
8048 | __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); |
8049 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); | |
26f1fad2 JS |
8050 | } |
8051 | ||
f653e690 JS |
8052 | static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv *priv, |
8053 | u32 ramask, int sgi) | |
8054 | { | |
8055 | struct h2c_cmd h2c; | |
8056 | u8 bw = 0; | |
8057 | ||
8058 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
8059 | ||
8060 | h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; | |
8061 | h2c.b_macid_cfg.ramask0 = ramask & 0xff; | |
8062 | h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; | |
8063 | h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; | |
8064 | h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; | |
8065 | ||
8066 | h2c.ramask.arg = 0x80; | |
8067 | h2c.b_macid_cfg.data1 = 0; | |
8068 | if (sgi) | |
8069 | h2c.b_macid_cfg.data1 |= BIT(7); | |
8070 | ||
8071 | h2c.b_macid_cfg.data2 = bw; | |
8072 | ||
8073 | dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", | |
8074 | __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg)); | |
8075 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); | |
8076 | } | |
8077 | ||
7d794eaa JS |
8078 | static void rtl8723au_report_connect(struct rtl8xxxu_priv *priv, |
8079 | u8 macid, bool connect) | |
8080 | { | |
8081 | struct h2c_cmd h2c; | |
8082 | ||
8083 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
8084 | ||
8085 | h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; | |
8086 | ||
8087 | if (connect) | |
8088 | h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; | |
8089 | else | |
8090 | h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; | |
8091 | ||
8092 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); | |
8093 | } | |
8094 | ||
8095 | static void rtl8723bu_report_connect(struct rtl8xxxu_priv *priv, | |
8096 | u8 macid, bool connect) | |
8097 | { | |
8098 | struct h2c_cmd h2c; | |
8099 | ||
8100 | memset(&h2c, 0, sizeof(struct h2c_cmd)); | |
8101 | ||
8102 | h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; | |
8103 | if (connect) | |
8104 | h2c.media_status_rpt.parm |= BIT(0); | |
8105 | else | |
8106 | h2c.media_status_rpt.parm &= ~BIT(0); | |
8107 | ||
8108 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); | |
8109 | } | |
8110 | ||
26f1fad2 JS |
8111 | static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) |
8112 | { | |
8113 | u32 val32; | |
8114 | u8 rate_idx = 0; | |
8115 | ||
8116 | rate_cfg &= RESPONSE_RATE_BITMAP_ALL; | |
8117 | ||
8118 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); | |
8119 | val32 &= ~RESPONSE_RATE_BITMAP_ALL; | |
8120 | val32 |= rate_cfg; | |
8121 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); | |
8122 | ||
8123 | dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); | |
8124 | ||
8125 | while (rate_cfg) { | |
8126 | rate_cfg = (rate_cfg >> 1); | |
8127 | rate_idx++; | |
8128 | } | |
8129 | rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); | |
8130 | } | |
8131 | ||
8132 | static void | |
8133 | rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
8134 | struct ieee80211_bss_conf *bss_conf, u32 changed) | |
8135 | { | |
8136 | struct rtl8xxxu_priv *priv = hw->priv; | |
8137 | struct device *dev = &priv->udev->dev; | |
8138 | struct ieee80211_sta *sta; | |
8139 | u32 val32; | |
8140 | u8 val8; | |
8141 | ||
8142 | if (changed & BSS_CHANGED_ASSOC) { | |
26f1fad2 JS |
8143 | dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc); |
8144 | ||
26f1fad2 JS |
8145 | rtl8xxxu_set_linktype(priv, vif->type); |
8146 | ||
8147 | if (bss_conf->assoc) { | |
8148 | u32 ramask; | |
8149 | int sgi = 0; | |
8150 | ||
8151 | rcu_read_lock(); | |
8152 | sta = ieee80211_find_sta(vif, bss_conf->bssid); | |
8153 | if (!sta) { | |
8154 | dev_info(dev, "%s: ASSOC no sta found\n", | |
8155 | __func__); | |
8156 | rcu_read_unlock(); | |
8157 | goto error; | |
8158 | } | |
8159 | ||
8160 | if (sta->ht_cap.ht_supported) | |
8161 | dev_info(dev, "%s: HT supported\n", __func__); | |
8162 | if (sta->vht_cap.vht_supported) | |
8163 | dev_info(dev, "%s: VHT supported\n", __func__); | |
8164 | ||
8165 | /* TODO: Set bits 28-31 for rate adaptive id */ | |
8166 | ramask = (sta->supp_rates[0] & 0xfff) | | |
8167 | sta->ht_cap.mcs.rx_mask[0] << 12 | | |
8168 | sta->ht_cap.mcs.rx_mask[1] << 20; | |
8169 | if (sta->ht_cap.cap & | |
8170 | (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) | |
8171 | sgi = 1; | |
8172 | rcu_read_unlock(); | |
8173 | ||
f653e690 | 8174 | priv->fops->update_rate_mask(priv, ramask, sgi); |
26f1fad2 | 8175 | |
26f1fad2 JS |
8176 | rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); |
8177 | ||
8178 | rtl8723a_stop_tx_beacon(priv); | |
8179 | ||
8180 | /* joinbss sequence */ | |
8181 | rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, | |
8182 | 0xc000 | bss_conf->aid); | |
8183 | ||
7d794eaa | 8184 | priv->fops->report_connect(priv, 0, true); |
26f1fad2 | 8185 | } else { |
26f1fad2 JS |
8186 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
8187 | val8 |= BEACON_DISABLE_TSF_UPDATE; | |
8188 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); | |
8189 | ||
7d794eaa | 8190 | priv->fops->report_connect(priv, 0, false); |
26f1fad2 | 8191 | } |
26f1fad2 JS |
8192 | } |
8193 | ||
8194 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { | |
8195 | dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", | |
8196 | bss_conf->use_short_preamble); | |
8197 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); | |
8198 | if (bss_conf->use_short_preamble) | |
8199 | val32 |= RSR_ACK_SHORT_PREAMBLE; | |
8200 | else | |
8201 | val32 &= ~RSR_ACK_SHORT_PREAMBLE; | |
8202 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); | |
8203 | } | |
8204 | ||
8205 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
8206 | dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", | |
8207 | bss_conf->use_short_slot); | |
8208 | ||
8209 | if (bss_conf->use_short_slot) | |
8210 | val8 = 9; | |
8211 | else | |
8212 | val8 = 20; | |
8213 | rtl8xxxu_write8(priv, REG_SLOT, val8); | |
8214 | } | |
8215 | ||
8216 | if (changed & BSS_CHANGED_BSSID) { | |
8217 | dev_dbg(dev, "Changed BSSID!\n"); | |
8218 | rtl8xxxu_set_bssid(priv, bss_conf->bssid); | |
8219 | } | |
8220 | ||
8221 | if (changed & BSS_CHANGED_BASIC_RATES) { | |
8222 | dev_dbg(dev, "Changed BASIC_RATES!\n"); | |
8223 | rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); | |
8224 | } | |
8225 | error: | |
8226 | return; | |
8227 | } | |
8228 | ||
8229 | static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) | |
8230 | { | |
8231 | u32 rtlqueue; | |
8232 | ||
8233 | switch (queue) { | |
8234 | case IEEE80211_AC_VO: | |
8235 | rtlqueue = TXDESC_QUEUE_VO; | |
8236 | break; | |
8237 | case IEEE80211_AC_VI: | |
8238 | rtlqueue = TXDESC_QUEUE_VI; | |
8239 | break; | |
8240 | case IEEE80211_AC_BE: | |
8241 | rtlqueue = TXDESC_QUEUE_BE; | |
8242 | break; | |
8243 | case IEEE80211_AC_BK: | |
8244 | rtlqueue = TXDESC_QUEUE_BK; | |
8245 | break; | |
8246 | default: | |
8247 | rtlqueue = TXDESC_QUEUE_BE; | |
8248 | } | |
8249 | ||
8250 | return rtlqueue; | |
8251 | } | |
8252 | ||
8253 | static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb) | |
8254 | { | |
8255 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
8256 | u32 queue; | |
8257 | ||
8258 | if (ieee80211_is_mgmt(hdr->frame_control)) | |
8259 | queue = TXDESC_QUEUE_MGNT; | |
8260 | else | |
8261 | queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); | |
8262 | ||
8263 | return queue; | |
8264 | } | |
8265 | ||
179e1742 JS |
8266 | /* |
8267 | * Despite newer chips 8723b/8812/8821 having a larger TX descriptor | |
8268 | * format. The descriptor checksum is still only calculated over the | |
8269 | * initial 32 bytes of the descriptor! | |
8270 | */ | |
dbb2896b | 8271 | static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) |
26f1fad2 JS |
8272 | { |
8273 | __le16 *ptr = (__le16 *)tx_desc; | |
8274 | u16 csum = 0; | |
8275 | int i; | |
8276 | ||
8277 | /* | |
8278 | * Clear csum field before calculation, as the csum field is | |
8279 | * in the middle of the struct. | |
8280 | */ | |
8281 | tx_desc->csum = cpu_to_le16(0); | |
8282 | ||
dbb2896b | 8283 | for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) |
26f1fad2 JS |
8284 | csum = csum ^ le16_to_cpu(ptr[i]); |
8285 | ||
8286 | tx_desc->csum |= cpu_to_le16(csum); | |
8287 | } | |
8288 | ||
8289 | static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) | |
8290 | { | |
8291 | struct rtl8xxxu_tx_urb *tx_urb, *tmp; | |
8292 | unsigned long flags; | |
8293 | ||
8294 | spin_lock_irqsave(&priv->tx_urb_lock, flags); | |
8295 | list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { | |
8296 | list_del(&tx_urb->list); | |
8297 | priv->tx_urb_free_count--; | |
8298 | usb_free_urb(&tx_urb->urb); | |
8299 | } | |
8300 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); | |
8301 | } | |
8302 | ||
8303 | static struct rtl8xxxu_tx_urb * | |
8304 | rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) | |
8305 | { | |
8306 | struct rtl8xxxu_tx_urb *tx_urb; | |
8307 | unsigned long flags; | |
8308 | ||
8309 | spin_lock_irqsave(&priv->tx_urb_lock, flags); | |
8310 | tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, | |
8311 | struct rtl8xxxu_tx_urb, list); | |
8312 | if (tx_urb) { | |
8313 | list_del(&tx_urb->list); | |
8314 | priv->tx_urb_free_count--; | |
8315 | if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && | |
8316 | !priv->tx_stopped) { | |
8317 | priv->tx_stopped = true; | |
8318 | ieee80211_stop_queues(priv->hw); | |
8319 | } | |
8320 | } | |
8321 | ||
8322 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); | |
8323 | ||
8324 | return tx_urb; | |
8325 | } | |
8326 | ||
8327 | static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, | |
8328 | struct rtl8xxxu_tx_urb *tx_urb) | |
8329 | { | |
8330 | unsigned long flags; | |
8331 | ||
8332 | INIT_LIST_HEAD(&tx_urb->list); | |
8333 | ||
8334 | spin_lock_irqsave(&priv->tx_urb_lock, flags); | |
8335 | ||
8336 | list_add(&tx_urb->list, &priv->tx_urb_free_list); | |
8337 | priv->tx_urb_free_count++; | |
8338 | if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && | |
8339 | priv->tx_stopped) { | |
8340 | priv->tx_stopped = false; | |
8341 | ieee80211_wake_queues(priv->hw); | |
8342 | } | |
8343 | ||
8344 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); | |
8345 | } | |
8346 | ||
8347 | static void rtl8xxxu_tx_complete(struct urb *urb) | |
8348 | { | |
8349 | struct sk_buff *skb = (struct sk_buff *)urb->context; | |
8350 | struct ieee80211_tx_info *tx_info; | |
8351 | struct ieee80211_hw *hw; | |
179e1742 | 8352 | struct rtl8xxxu_priv *priv; |
26f1fad2 JS |
8353 | struct rtl8xxxu_tx_urb *tx_urb = |
8354 | container_of(urb, struct rtl8xxxu_tx_urb, urb); | |
8355 | ||
8356 | tx_info = IEEE80211_SKB_CB(skb); | |
8357 | hw = tx_info->rate_driver_data[0]; | |
179e1742 | 8358 | priv = hw->priv; |
26f1fad2 | 8359 | |
179e1742 | 8360 | skb_pull(skb, priv->fops->tx_desc_size); |
26f1fad2 JS |
8361 | |
8362 | ieee80211_tx_info_clear_status(tx_info); | |
8363 | tx_info->status.rates[0].idx = -1; | |
8364 | tx_info->status.rates[0].count = 0; | |
8365 | ||
8366 | if (!urb->status) | |
8367 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
8368 | ||
8369 | ieee80211_tx_status_irqsafe(hw, skb); | |
8370 | ||
179e1742 | 8371 | rtl8xxxu_free_tx_urb(priv, tx_urb); |
26f1fad2 JS |
8372 | } |
8373 | ||
8374 | static void rtl8xxxu_dump_action(struct device *dev, | |
8375 | struct ieee80211_hdr *hdr) | |
8376 | { | |
8377 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; | |
8378 | u16 cap, timeout; | |
8379 | ||
8380 | if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) | |
8381 | return; | |
8382 | ||
8383 | switch (mgmt->u.action.u.addba_resp.action_code) { | |
8384 | case WLAN_ACTION_ADDBA_RESP: | |
8385 | cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); | |
8386 | timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); | |
8387 | dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " | |
8388 | "timeout %i, tid %02x, buf_size %02x, policy %02x, " | |
8389 | "status %02x\n", | |
8390 | timeout, | |
8391 | (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, | |
8392 | (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, | |
8393 | (cap >> 1) & 0x1, | |
8394 | le16_to_cpu(mgmt->u.action.u.addba_resp.status)); | |
8395 | break; | |
8396 | case WLAN_ACTION_ADDBA_REQ: | |
8397 | cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); | |
8398 | timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); | |
8399 | dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " | |
8400 | "timeout %i, tid %02x, buf_size %02x, policy %02x\n", | |
8401 | timeout, | |
8402 | (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, | |
8403 | (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, | |
8404 | (cap >> 1) & 0x1); | |
8405 | break; | |
8406 | default: | |
8407 | dev_info(dev, "action frame %02x\n", | |
8408 | mgmt->u.action.u.addba_resp.action_code); | |
8409 | break; | |
8410 | } | |
8411 | } | |
8412 | ||
8413 | static void rtl8xxxu_tx(struct ieee80211_hw *hw, | |
8414 | struct ieee80211_tx_control *control, | |
8415 | struct sk_buff *skb) | |
8416 | { | |
8417 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
8418 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
8419 | struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); | |
8420 | struct rtl8xxxu_priv *priv = hw->priv; | |
dbb2896b JS |
8421 | struct rtl8xxxu_txdesc32 *tx_desc; |
8422 | struct rtl8xxxu_txdesc40 *tx_desc40; | |
26f1fad2 JS |
8423 | struct rtl8xxxu_tx_urb *tx_urb; |
8424 | struct ieee80211_sta *sta = NULL; | |
8425 | struct ieee80211_vif *vif = tx_info->control.vif; | |
8426 | struct device *dev = &priv->udev->dev; | |
8427 | u32 queue, rate; | |
8428 | u16 pktlen = skb->len; | |
8429 | u16 seq_number; | |
8430 | u16 rate_flag = tx_info->control.rates[0].flags; | |
179e1742 | 8431 | int tx_desc_size = priv->fops->tx_desc_size; |
26f1fad2 | 8432 | int ret; |
cc2646d4 | 8433 | bool usedesc40, ampdu_enable; |
26f1fad2 | 8434 | |
179e1742 | 8435 | if (skb_headroom(skb) < tx_desc_size) { |
26f1fad2 JS |
8436 | dev_warn(dev, |
8437 | "%s: Not enough headroom (%i) for tx descriptor\n", | |
8438 | __func__, skb_headroom(skb)); | |
8439 | goto error; | |
8440 | } | |
8441 | ||
179e1742 | 8442 | if (unlikely(skb->len > (65535 - tx_desc_size))) { |
26f1fad2 JS |
8443 | dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", |
8444 | __func__, skb->len); | |
8445 | goto error; | |
8446 | } | |
8447 | ||
8448 | tx_urb = rtl8xxxu_alloc_tx_urb(priv); | |
8449 | if (!tx_urb) { | |
8450 | dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); | |
8451 | goto error; | |
8452 | } | |
8453 | ||
8454 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) | |
8455 | dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n", | |
8456 | __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen); | |
8457 | ||
8458 | if (ieee80211_is_action(hdr->frame_control)) | |
8459 | rtl8xxxu_dump_action(dev, hdr); | |
8460 | ||
cc2646d4 | 8461 | usedesc40 = (tx_desc_size == 40); |
26f1fad2 JS |
8462 | tx_info->rate_driver_data[0] = hw; |
8463 | ||
8464 | if (control && control->sta) | |
8465 | sta = control->sta; | |
8466 | ||
dbb2896b | 8467 | tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size); |
26f1fad2 | 8468 | |
179e1742 | 8469 | memset(tx_desc, 0, tx_desc_size); |
26f1fad2 | 8470 | tx_desc->pkt_size = cpu_to_le16(pktlen); |
179e1742 | 8471 | tx_desc->pkt_offset = tx_desc_size; |
26f1fad2 JS |
8472 | |
8473 | tx_desc->txdw0 = | |
8474 | TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; | |
8475 | if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || | |
8476 | is_broadcast_ether_addr(ieee80211_get_DA(hdr))) | |
8477 | tx_desc->txdw0 |= TXDESC_BROADMULTICAST; | |
8478 | ||
8479 | queue = rtl8xxxu_queue_select(hw, skb); | |
8480 | tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); | |
8481 | ||
8482 | if (tx_info->control.hw_key) { | |
8483 | switch (tx_info->control.hw_key->cipher) { | |
8484 | case WLAN_CIPHER_SUITE_WEP40: | |
8485 | case WLAN_CIPHER_SUITE_WEP104: | |
8486 | case WLAN_CIPHER_SUITE_TKIP: | |
8487 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); | |
8488 | break; | |
8489 | case WLAN_CIPHER_SUITE_CCMP: | |
8490 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); | |
8491 | break; | |
8492 | default: | |
8493 | break; | |
8494 | } | |
8495 | } | |
8496 | ||
26f1fad2 | 8497 | /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ |
a40ace4f | 8498 | ampdu_enable = false; |
26f1fad2 JS |
8499 | if (ieee80211_is_data_qos(hdr->frame_control) && sta) { |
8500 | if (sta->ht_cap.ht_supported) { | |
8501 | u32 ampdu, val32; | |
8502 | ||
8503 | ampdu = (u32)sta->ht_cap.ampdu_density; | |
8504 | val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; | |
8505 | tx_desc->txdw2 |= cpu_to_le32(val32); | |
ce2d1dbb | 8506 | |
a40ace4f JS |
8507 | ampdu_enable = true; |
8508 | } | |
8509 | } | |
8510 | ||
4c683607 JS |
8511 | if (rate_flag & IEEE80211_TX_RC_MCS) |
8512 | rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; | |
8513 | else | |
8514 | rate = tx_rate->hw_value; | |
8515 | ||
cc2646d4 JS |
8516 | seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
8517 | if (!usedesc40) { | |
4c683607 JS |
8518 | tx_desc->txdw5 = cpu_to_le32(rate); |
8519 | ||
8520 | if (ieee80211_is_data(hdr->frame_control)) | |
8521 | tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); | |
8522 | ||
cc2646d4 | 8523 | tx_desc->txdw3 = |
33f37249 | 8524 | cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); |
cc2646d4 | 8525 | |
a40ace4f | 8526 | if (ampdu_enable) |
33f37249 | 8527 | tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); |
a40ace4f | 8528 | else |
33f37249 | 8529 | tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); |
4c683607 JS |
8530 | |
8531 | if (ieee80211_is_mgmt(hdr->frame_control)) { | |
8532 | tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value); | |
8533 | tx_desc->txdw4 |= | |
33f37249 | 8534 | cpu_to_le32(TXDESC32_USE_DRIVER_RATE); |
4c683607 | 8535 | tx_desc->txdw5 |= |
33f37249 | 8536 | cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); |
4c683607 | 8537 | tx_desc->txdw5 |= |
33f37249 | 8538 | cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); |
4c683607 JS |
8539 | } |
8540 | ||
8541 | if (ieee80211_is_data_qos(hdr->frame_control)) | |
33f37249 | 8542 | tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); |
4c683607 JS |
8543 | |
8544 | if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || | |
8545 | (sta && vif && vif->bss_conf.use_short_preamble)) | |
33f37249 | 8546 | tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); |
4c683607 JS |
8547 | |
8548 | if (rate_flag & IEEE80211_TX_RC_SHORT_GI || | |
8549 | (ieee80211_is_data_qos(hdr->frame_control) && | |
8550 | sta && sta->ht_cap.cap & | |
8551 | (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) { | |
1df1de34 | 8552 | tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); |
4c683607 JS |
8553 | } |
8554 | ||
8555 | if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) { | |
8556 | /* | |
8557 | * Use RTS rate 24M - does the mac80211 tell | |
8558 | * us which to use? | |
8559 | */ | |
8560 | tx_desc->txdw4 |= | |
8561 | cpu_to_le32(DESC_RATE_24M << | |
33f37249 | 8562 | TXDESC32_RTS_RATE_SHIFT); |
4c683607 | 8563 | tx_desc->txdw4 |= |
33f37249 JS |
8564 | cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); |
8565 | tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); | |
4c683607 | 8566 | } |
a40ace4f | 8567 | } else { |
dbb2896b | 8568 | tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc; |
cc2646d4 | 8569 | |
4c683607 JS |
8570 | tx_desc40->txdw4 = cpu_to_le32(rate); |
8571 | if (ieee80211_is_data(hdr->frame_control)) { | |
8572 | tx_desc->txdw4 |= | |
8573 | cpu_to_le32(0x1f << | |
33f37249 | 8574 | TXDESC40_DATA_RATE_FB_SHIFT); |
4c683607 JS |
8575 | } |
8576 | ||
cc2646d4 | 8577 | tx_desc40->txdw9 = |
33f37249 | 8578 | cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); |
cc2646d4 | 8579 | |
a40ace4f | 8580 | if (ampdu_enable) |
33f37249 | 8581 | tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); |
a40ace4f | 8582 | else |
33f37249 | 8583 | tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); |
26f1fad2 | 8584 | |
4c683607 JS |
8585 | if (ieee80211_is_mgmt(hdr->frame_control)) { |
8586 | tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value); | |
8587 | tx_desc40->txdw3 |= | |
33f37249 | 8588 | cpu_to_le32(TXDESC40_USE_DRIVER_RATE); |
4c683607 | 8589 | tx_desc40->txdw4 |= |
33f37249 | 8590 | cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); |
4c683607 | 8591 | tx_desc40->txdw4 |= |
33f37249 | 8592 | cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); |
4c683607 JS |
8593 | } |
8594 | ||
8595 | if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || | |
8596 | (sta && vif && vif->bss_conf.use_short_preamble)) | |
8597 | tx_desc40->txdw5 |= | |
33f37249 | 8598 | cpu_to_le32(TXDESC40_SHORT_PREAMBLE); |
4c683607 JS |
8599 | |
8600 | if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) { | |
8601 | /* | |
8602 | * Use RTS rate 24M - does the mac80211 tell | |
8603 | * us which to use? | |
8604 | */ | |
8605 | tx_desc->txdw4 |= | |
8606 | cpu_to_le32(DESC_RATE_24M << | |
33f37249 JS |
8607 | TXDESC40_RTS_RATE_SHIFT); |
8608 | tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); | |
8609 | tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); | |
4c683607 | 8610 | } |
6979494a | 8611 | } |
26f1fad2 JS |
8612 | |
8613 | rtl8xxxu_calc_tx_desc_csum(tx_desc); | |
8614 | ||
8615 | usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], | |
8616 | skb->data, skb->len, rtl8xxxu_tx_complete, skb); | |
8617 | ||
8618 | usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); | |
8619 | ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); | |
8620 | if (ret) { | |
8621 | usb_unanchor_urb(&tx_urb->urb); | |
8622 | rtl8xxxu_free_tx_urb(priv, tx_urb); | |
8623 | goto error; | |
8624 | } | |
8625 | return; | |
8626 | error: | |
8627 | dev_kfree_skb(skb); | |
8628 | } | |
8629 | ||
8630 | static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv, | |
8631 | struct ieee80211_rx_status *rx_status, | |
87957081 JS |
8632 | struct rtl8723au_phy_stats *phy_stats, |
8633 | u32 rxmcs) | |
26f1fad2 JS |
8634 | { |
8635 | if (phy_stats->sgi_en) | |
8636 | rx_status->flag |= RX_FLAG_SHORT_GI; | |
8637 | ||
87957081 | 8638 | if (rxmcs < DESC_RATE_6M) { |
26f1fad2 JS |
8639 | /* |
8640 | * Handle PHY stats for CCK rates | |
8641 | */ | |
8642 | u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; | |
8643 | ||
8644 | switch (cck_agc_rpt & 0xc0) { | |
8645 | case 0xc0: | |
8646 | rx_status->signal = -46 - (cck_agc_rpt & 0x3e); | |
8647 | break; | |
8648 | case 0x80: | |
8649 | rx_status->signal = -26 - (cck_agc_rpt & 0x3e); | |
8650 | break; | |
8651 | case 0x40: | |
8652 | rx_status->signal = -12 - (cck_agc_rpt & 0x3e); | |
8653 | break; | |
8654 | case 0x00: | |
8655 | rx_status->signal = 16 - (cck_agc_rpt & 0x3e); | |
8656 | break; | |
8657 | } | |
8658 | } else { | |
8659 | rx_status->signal = | |
8660 | (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; | |
8661 | } | |
8662 | } | |
8663 | ||
8664 | static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) | |
8665 | { | |
8666 | struct rtl8xxxu_rx_urb *rx_urb, *tmp; | |
8667 | unsigned long flags; | |
8668 | ||
8669 | spin_lock_irqsave(&priv->rx_urb_lock, flags); | |
8670 | ||
8671 | list_for_each_entry_safe(rx_urb, tmp, | |
8672 | &priv->rx_urb_pending_list, list) { | |
8673 | list_del(&rx_urb->list); | |
8674 | priv->rx_urb_pending_count--; | |
8675 | usb_free_urb(&rx_urb->urb); | |
8676 | } | |
8677 | ||
8678 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); | |
8679 | } | |
8680 | ||
8681 | static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, | |
8682 | struct rtl8xxxu_rx_urb *rx_urb) | |
8683 | { | |
8684 | struct sk_buff *skb; | |
8685 | unsigned long flags; | |
8686 | int pending = 0; | |
8687 | ||
8688 | spin_lock_irqsave(&priv->rx_urb_lock, flags); | |
8689 | ||
8690 | if (!priv->shutdown) { | |
8691 | list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); | |
8692 | priv->rx_urb_pending_count++; | |
8693 | pending = priv->rx_urb_pending_count; | |
8694 | } else { | |
8695 | skb = (struct sk_buff *)rx_urb->urb.context; | |
8696 | dev_kfree_skb(skb); | |
8697 | usb_free_urb(&rx_urb->urb); | |
8698 | } | |
8699 | ||
8700 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); | |
8701 | ||
8702 | if (pending > RTL8XXXU_RX_URB_PENDING_WATER) | |
8703 | schedule_work(&priv->rx_urb_wq); | |
8704 | } | |
8705 | ||
8706 | static void rtl8xxxu_rx_urb_work(struct work_struct *work) | |
8707 | { | |
8708 | struct rtl8xxxu_priv *priv; | |
8709 | struct rtl8xxxu_rx_urb *rx_urb, *tmp; | |
8710 | struct list_head local; | |
8711 | struct sk_buff *skb; | |
8712 | unsigned long flags; | |
8713 | int ret; | |
8714 | ||
8715 | priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); | |
8716 | INIT_LIST_HEAD(&local); | |
8717 | ||
8718 | spin_lock_irqsave(&priv->rx_urb_lock, flags); | |
8719 | ||
8720 | list_splice_init(&priv->rx_urb_pending_list, &local); | |
8721 | priv->rx_urb_pending_count = 0; | |
8722 | ||
8723 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); | |
8724 | ||
8725 | list_for_each_entry_safe(rx_urb, tmp, &local, list) { | |
8726 | list_del_init(&rx_urb->list); | |
8727 | ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); | |
8728 | /* | |
8729 | * If out of memory or temporary error, put it back on the | |
8730 | * queue and try again. Otherwise the device is dead/gone | |
8731 | * and we should drop it. | |
8732 | */ | |
8733 | switch (ret) { | |
8734 | case 0: | |
8735 | break; | |
8736 | case -ENOMEM: | |
8737 | case -EAGAIN: | |
8738 | rtl8xxxu_queue_rx_urb(priv, rx_urb); | |
8739 | break; | |
8740 | default: | |
8741 | pr_info("failed to requeue urb %i\n", ret); | |
8742 | skb = (struct sk_buff *)rx_urb->urb.context; | |
8743 | dev_kfree_skb(skb); | |
8744 | usb_free_urb(&rx_urb->urb); | |
8745 | } | |
8746 | } | |
8747 | } | |
8748 | ||
b18cdfdb JS |
8749 | static int rtl8723au_parse_rx_desc(struct rtl8xxxu_priv *priv, |
8750 | struct sk_buff *skb, | |
8751 | struct ieee80211_rx_status *rx_status) | |
8752 | { | |
8753 | struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data; | |
8754 | struct rtl8723au_phy_stats *phy_stats; | |
8755 | int drvinfo_sz, desc_shift; | |
8756 | ||
8757 | skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc)); | |
8758 | ||
8759 | phy_stats = (struct rtl8723au_phy_stats *)skb->data; | |
8760 | ||
8761 | drvinfo_sz = rx_desc->drvinfo_sz * 8; | |
8762 | desc_shift = rx_desc->shift; | |
8763 | skb_pull(skb, drvinfo_sz + desc_shift); | |
8764 | ||
8765 | if (rx_desc->phy_stats) | |
87957081 JS |
8766 | rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, |
8767 | rx_desc->rxmcs); | |
b18cdfdb JS |
8768 | |
8769 | rx_status->mactime = le32_to_cpu(rx_desc->tsfl); | |
8770 | rx_status->flag |= RX_FLAG_MACTIME_START; | |
8771 | ||
8772 | if (!rx_desc->swdec) | |
8773 | rx_status->flag |= RX_FLAG_DECRYPTED; | |
8774 | if (rx_desc->crc32) | |
8775 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | |
8776 | if (rx_desc->bw) | |
8777 | rx_status->flag |= RX_FLAG_40MHZ; | |
8778 | ||
8779 | if (rx_desc->rxht) { | |
8780 | rx_status->flag |= RX_FLAG_HT; | |
8781 | rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; | |
8782 | } else { | |
8783 | rx_status->rate_idx = rx_desc->rxmcs; | |
8784 | } | |
8785 | ||
8786 | return RX_TYPE_DATA_PKT; | |
8787 | } | |
8788 | ||
8789 | static int rtl8723bu_parse_rx_desc(struct rtl8xxxu_priv *priv, | |
8790 | struct sk_buff *skb, | |
8791 | struct ieee80211_rx_status *rx_status) | |
8792 | { | |
8793 | struct rtl8723bu_rx_desc *rx_desc = | |
8794 | (struct rtl8723bu_rx_desc *)skb->data; | |
8795 | struct rtl8723au_phy_stats *phy_stats; | |
8796 | int drvinfo_sz, desc_shift; | |
b18cdfdb JS |
8797 | |
8798 | skb_pull(skb, sizeof(struct rtl8723bu_rx_desc)); | |
8799 | ||
8800 | phy_stats = (struct rtl8723au_phy_stats *)skb->data; | |
8801 | ||
8802 | drvinfo_sz = rx_desc->drvinfo_sz * 8; | |
8803 | desc_shift = rx_desc->shift; | |
8804 | skb_pull(skb, drvinfo_sz + desc_shift); | |
8805 | ||
e975b87c JS |
8806 | if (rx_desc->rpt_sel) { |
8807 | struct device *dev = &priv->udev->dev; | |
8808 | dev_dbg(dev, "%s: C2H packet\n", __func__); | |
8809 | return RX_TYPE_C2H; | |
8810 | } | |
8811 | ||
87957081 JS |
8812 | if (rx_desc->phy_stats) |
8813 | rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, | |
8814 | rx_desc->rxmcs); | |
8815 | ||
b18cdfdb JS |
8816 | rx_status->mactime = le32_to_cpu(rx_desc->tsfl); |
8817 | rx_status->flag |= RX_FLAG_MACTIME_START; | |
8818 | ||
8819 | if (!rx_desc->swdec) | |
8820 | rx_status->flag |= RX_FLAG_DECRYPTED; | |
8821 | if (rx_desc->crc32) | |
8822 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | |
8823 | if (rx_desc->bw) | |
8824 | rx_status->flag |= RX_FLAG_40MHZ; | |
8825 | ||
8826 | if (rx_desc->rxmcs >= DESC_RATE_MCS0) { | |
8827 | rx_status->flag |= RX_FLAG_HT; | |
8828 | rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; | |
8829 | } else { | |
8830 | rx_status->rate_idx = rx_desc->rxmcs; | |
8831 | } | |
8832 | ||
e975b87c | 8833 | return RX_TYPE_DATA_PKT; |
b18cdfdb JS |
8834 | } |
8835 | ||
b2b43b78 JS |
8836 | static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, |
8837 | struct sk_buff *skb) | |
8838 | { | |
8839 | struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; | |
8840 | struct device *dev = &priv->udev->dev; | |
8841 | int len; | |
8842 | ||
8843 | len = skb->len - 2; | |
8844 | ||
5e00d503 JS |
8845 | dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", |
8846 | c2h->id, c2h->seq, len, c2h->bt_info.response_source); | |
b2b43b78 JS |
8847 | |
8848 | switch(c2h->id) { | |
8849 | case C2H_8723B_BT_INFO: | |
8850 | if (c2h->bt_info.response_source > | |
8851 | BT_INFO_SRC_8723B_BT_ACTIVE_SEND) | |
5e00d503 | 8852 | dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); |
b2b43b78 | 8853 | else |
5e00d503 | 8854 | dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); |
b2b43b78 JS |
8855 | |
8856 | if (c2h->bt_info.bt_has_reset) | |
5e00d503 | 8857 | dev_dbg(dev, "BT has been reset\n"); |
394f1bd3 | 8858 | if (c2h->bt_info.tx_rx_mask) |
5e00d503 | 8859 | dev_dbg(dev, "BT TRx mask\n"); |
b2b43b78 JS |
8860 | |
8861 | break; | |
394f1bd3 | 8862 | case C2H_8723B_BT_MP_INFO: |
5e00d503 JS |
8863 | dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", |
8864 | c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); | |
394f1bd3 | 8865 | break; |
55a18dd1 JS |
8866 | case C2H_8723B_RA_REPORT: |
8867 | dev_dbg(dev, | |
8868 | "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", | |
8869 | c2h->ra_report.rate, c2h->ra_report.dummy0_0, | |
8870 | c2h->ra_report.macid, c2h->ra_report.noisy_state); | |
8871 | break; | |
b2b43b78 | 8872 | default: |
739dc9f2 JS |
8873 | dev_info(dev, "Unhandled C2H event %02x seq %02x\n", |
8874 | c2h->id, c2h->seq); | |
8875 | print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, | |
8876 | 16, 1, c2h->raw.payload, len, false); | |
b2b43b78 JS |
8877 | break; |
8878 | } | |
8879 | } | |
8880 | ||
26f1fad2 JS |
8881 | static void rtl8xxxu_rx_complete(struct urb *urb) |
8882 | { | |
8883 | struct rtl8xxxu_rx_urb *rx_urb = | |
8884 | container_of(urb, struct rtl8xxxu_rx_urb, urb); | |
8885 | struct ieee80211_hw *hw = rx_urb->hw; | |
8886 | struct rtl8xxxu_priv *priv = hw->priv; | |
8887 | struct sk_buff *skb = (struct sk_buff *)urb->context; | |
26f1fad2 | 8888 | struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); |
26f1fad2 JS |
8889 | struct device *dev = &priv->udev->dev; |
8890 | __le32 *_rx_desc_le = (__le32 *)skb->data; | |
8891 | u32 *_rx_desc = (u32 *)skb->data; | |
b18cdfdb | 8892 | int rx_type, i; |
26f1fad2 JS |
8893 | |
8894 | for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++) | |
8895 | _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); | |
8896 | ||
26f1fad2 JS |
8897 | skb_put(skb, urb->actual_length); |
8898 | ||
8899 | if (urb->status == 0) { | |
26f1fad2 JS |
8900 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); |
8901 | ||
b18cdfdb | 8902 | rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status); |
26f1fad2 JS |
8903 | |
8904 | rx_status->freq = hw->conf.chandef.chan->center_freq; | |
8905 | rx_status->band = hw->conf.chandef.chan->band; | |
8906 | ||
b18cdfdb JS |
8907 | if (rx_type == RX_TYPE_DATA_PKT) |
8908 | ieee80211_rx_irqsafe(hw, skb); | |
b2b43b78 JS |
8909 | else { |
8910 | rtl8723bu_handle_c2h(priv, skb); | |
b18cdfdb | 8911 | dev_kfree_skb(skb); |
b2b43b78 | 8912 | } |
26f1fad2 | 8913 | |
26f1fad2 JS |
8914 | skb = NULL; |
8915 | rx_urb->urb.context = NULL; | |
8916 | rtl8xxxu_queue_rx_urb(priv, rx_urb); | |
8917 | } else { | |
8918 | dev_dbg(dev, "%s: status %i\n", __func__, urb->status); | |
8919 | goto cleanup; | |
8920 | } | |
8921 | return; | |
8922 | ||
8923 | cleanup: | |
8924 | usb_free_urb(urb); | |
8925 | dev_kfree_skb(skb); | |
8926 | return; | |
8927 | } | |
8928 | ||
8929 | static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, | |
8930 | struct rtl8xxxu_rx_urb *rx_urb) | |
8931 | { | |
8932 | struct sk_buff *skb; | |
8933 | int skb_size; | |
8934 | int ret; | |
8935 | ||
8936 | skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE; | |
8937 | skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); | |
8938 | if (!skb) | |
8939 | return -ENOMEM; | |
8940 | ||
8941 | memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc)); | |
8942 | usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, | |
8943 | skb_size, rtl8xxxu_rx_complete, skb); | |
8944 | usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); | |
8945 | ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); | |
8946 | if (ret) | |
8947 | usb_unanchor_urb(&rx_urb->urb); | |
8948 | return ret; | |
8949 | } | |
8950 | ||
8951 | static void rtl8xxxu_int_complete(struct urb *urb) | |
8952 | { | |
8953 | struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; | |
8954 | struct device *dev = &priv->udev->dev; | |
8955 | int ret; | |
8956 | ||
8957 | dev_dbg(dev, "%s: status %i\n", __func__, urb->status); | |
8958 | if (urb->status == 0) { | |
8959 | usb_anchor_urb(urb, &priv->int_anchor); | |
8960 | ret = usb_submit_urb(urb, GFP_ATOMIC); | |
8961 | if (ret) | |
8962 | usb_unanchor_urb(urb); | |
8963 | } else { | |
8964 | dev_info(dev, "%s: Error %i\n", __func__, urb->status); | |
8965 | } | |
8966 | } | |
8967 | ||
8968 | ||
8969 | static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) | |
8970 | { | |
8971 | struct rtl8xxxu_priv *priv = hw->priv; | |
8972 | struct urb *urb; | |
8973 | u32 val32; | |
8974 | int ret; | |
8975 | ||
8976 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
8977 | if (!urb) | |
8978 | return -ENOMEM; | |
8979 | ||
8980 | usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, | |
8981 | priv->int_buf, USB_INTR_CONTENT_LENGTH, | |
8982 | rtl8xxxu_int_complete, priv, 1); | |
8983 | usb_anchor_urb(urb, &priv->int_anchor); | |
8984 | ret = usb_submit_urb(urb, GFP_KERNEL); | |
8985 | if (ret) { | |
8986 | usb_unanchor_urb(urb); | |
8987 | goto error; | |
8988 | } | |
8989 | ||
8990 | val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); | |
8991 | val32 |= USB_HIMR_CPWM; | |
8992 | rtl8xxxu_write32(priv, REG_USB_HIMR, val32); | |
8993 | ||
8994 | error: | |
8995 | return ret; | |
8996 | } | |
8997 | ||
8998 | static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, | |
8999 | struct ieee80211_vif *vif) | |
9000 | { | |
9001 | struct rtl8xxxu_priv *priv = hw->priv; | |
9002 | int ret; | |
9003 | u8 val8; | |
9004 | ||
9005 | switch (vif->type) { | |
9006 | case NL80211_IFTYPE_STATION: | |
9007 | rtl8723a_stop_tx_beacon(priv); | |
9008 | ||
9009 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); | |
9010 | val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | | |
9011 | BEACON_DISABLE_TSF_UPDATE; | |
9012 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); | |
9013 | ret = 0; | |
9014 | break; | |
9015 | default: | |
9016 | ret = -EOPNOTSUPP; | |
9017 | } | |
9018 | ||
9019 | rtl8xxxu_set_linktype(priv, vif->type); | |
9020 | ||
9021 | return ret; | |
9022 | } | |
9023 | ||
9024 | static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, | |
9025 | struct ieee80211_vif *vif) | |
9026 | { | |
9027 | struct rtl8xxxu_priv *priv = hw->priv; | |
9028 | ||
9029 | dev_dbg(&priv->udev->dev, "%s\n", __func__); | |
9030 | } | |
9031 | ||
9032 | static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) | |
9033 | { | |
9034 | struct rtl8xxxu_priv *priv = hw->priv; | |
9035 | struct device *dev = &priv->udev->dev; | |
9036 | u16 val16; | |
9037 | int ret = 0, channel; | |
9038 | bool ht40; | |
9039 | ||
9040 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) | |
9041 | dev_info(dev, | |
9042 | "%s: channel: %i (changed %08x chandef.width %02x)\n", | |
9043 | __func__, hw->conf.chandef.chan->hw_value, | |
9044 | changed, hw->conf.chandef.width); | |
9045 | ||
9046 | if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { | |
9047 | val16 = ((hw->conf.long_frame_max_tx_count << | |
9048 | RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | | |
9049 | ((hw->conf.short_frame_max_tx_count << | |
9050 | RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); | |
9051 | rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); | |
9052 | } | |
9053 | ||
9054 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { | |
9055 | switch (hw->conf.chandef.width) { | |
9056 | case NL80211_CHAN_WIDTH_20_NOHT: | |
9057 | case NL80211_CHAN_WIDTH_20: | |
9058 | ht40 = false; | |
9059 | break; | |
9060 | case NL80211_CHAN_WIDTH_40: | |
9061 | ht40 = true; | |
9062 | break; | |
9063 | default: | |
9064 | ret = -ENOTSUPP; | |
9065 | goto exit; | |
9066 | } | |
9067 | ||
9068 | channel = hw->conf.chandef.chan->hw_value; | |
9069 | ||
e796dab4 | 9070 | priv->fops->set_tx_power(priv, channel, ht40); |
26f1fad2 | 9071 | |
1ea8e846 | 9072 | priv->fops->config_channel(hw); |
26f1fad2 JS |
9073 | } |
9074 | ||
9075 | exit: | |
9076 | return ret; | |
9077 | } | |
9078 | ||
9079 | static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, | |
9080 | struct ieee80211_vif *vif, u16 queue, | |
9081 | const struct ieee80211_tx_queue_params *param) | |
9082 | { | |
9083 | struct rtl8xxxu_priv *priv = hw->priv; | |
9084 | struct device *dev = &priv->udev->dev; | |
9085 | u32 val32; | |
9086 | u8 aifs, acm_ctrl, acm_bit; | |
9087 | ||
9088 | aifs = param->aifs; | |
9089 | ||
9090 | val32 = aifs | | |
9091 | fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | | |
9092 | fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | | |
9093 | (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; | |
9094 | ||
9095 | acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); | |
9096 | dev_dbg(dev, | |
9097 | "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", | |
9098 | __func__, queue, val32, param->acm, acm_ctrl); | |
9099 | ||
9100 | switch (queue) { | |
9101 | case IEEE80211_AC_VO: | |
9102 | acm_bit = ACM_HW_CTRL_VO; | |
9103 | rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); | |
9104 | break; | |
9105 | case IEEE80211_AC_VI: | |
9106 | acm_bit = ACM_HW_CTRL_VI; | |
9107 | rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); | |
9108 | break; | |
9109 | case IEEE80211_AC_BE: | |
9110 | acm_bit = ACM_HW_CTRL_BE; | |
9111 | rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); | |
9112 | break; | |
9113 | case IEEE80211_AC_BK: | |
9114 | acm_bit = ACM_HW_CTRL_BK; | |
9115 | rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); | |
9116 | break; | |
9117 | default: | |
9118 | acm_bit = 0; | |
9119 | break; | |
9120 | } | |
9121 | ||
9122 | if (param->acm) | |
9123 | acm_ctrl |= acm_bit; | |
9124 | else | |
9125 | acm_ctrl &= ~acm_bit; | |
9126 | rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); | |
9127 | ||
9128 | return 0; | |
9129 | } | |
9130 | ||
9131 | static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, | |
9132 | unsigned int changed_flags, | |
9133 | unsigned int *total_flags, u64 multicast) | |
9134 | { | |
9135 | struct rtl8xxxu_priv *priv = hw->priv; | |
3bed4bfa | 9136 | u32 rcr = rtl8xxxu_read32(priv, REG_RCR); |
26f1fad2 JS |
9137 | |
9138 | dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", | |
9139 | __func__, changed_flags, *total_flags); | |
9140 | ||
3bed4bfa BR |
9141 | /* |
9142 | * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) | |
9143 | */ | |
9144 | ||
9145 | if (*total_flags & FIF_FCSFAIL) | |
9146 | rcr |= RCR_ACCEPT_CRC32; | |
9147 | else | |
9148 | rcr &= ~RCR_ACCEPT_CRC32; | |
9149 | ||
9150 | /* | |
9151 | * FIF_PLCPFAIL not supported? | |
9152 | */ | |
9153 | ||
9154 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
9155 | rcr &= ~RCR_CHECK_BSSID_BEACON; | |
9156 | else | |
9157 | rcr |= RCR_CHECK_BSSID_BEACON; | |
9158 | ||
9159 | if (*total_flags & FIF_CONTROL) | |
9160 | rcr |= RCR_ACCEPT_CTRL_FRAME; | |
9161 | else | |
9162 | rcr &= ~RCR_ACCEPT_CTRL_FRAME; | |
9163 | ||
9164 | if (*total_flags & FIF_OTHER_BSS) { | |
9165 | rcr |= RCR_ACCEPT_AP; | |
9166 | rcr &= ~RCR_CHECK_BSSID_MATCH; | |
9167 | } else { | |
9168 | rcr &= ~RCR_ACCEPT_AP; | |
9169 | rcr |= RCR_CHECK_BSSID_MATCH; | |
9170 | } | |
9171 | ||
9172 | if (*total_flags & FIF_PSPOLL) | |
9173 | rcr |= RCR_ACCEPT_PM; | |
9174 | else | |
9175 | rcr &= ~RCR_ACCEPT_PM; | |
9176 | ||
9177 | /* | |
9178 | * FIF_PROBE_REQ ignored as probe requests always seem to be accepted | |
9179 | */ | |
9180 | ||
9181 | rtl8xxxu_write32(priv, REG_RCR, rcr); | |
9182 | ||
755bda11 JS |
9183 | *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | |
9184 | FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | | |
9185 | FIF_PROBE_REQ); | |
26f1fad2 JS |
9186 | } |
9187 | ||
9188 | static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) | |
9189 | { | |
9190 | if (rts > 2347) | |
9191 | return -EINVAL; | |
9192 | ||
9193 | return 0; | |
9194 | } | |
9195 | ||
9196 | static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, | |
9197 | struct ieee80211_vif *vif, | |
9198 | struct ieee80211_sta *sta, | |
9199 | struct ieee80211_key_conf *key) | |
9200 | { | |
9201 | struct rtl8xxxu_priv *priv = hw->priv; | |
9202 | struct device *dev = &priv->udev->dev; | |
9203 | u8 mac_addr[ETH_ALEN]; | |
9204 | u8 val8; | |
9205 | u16 val16; | |
9206 | u32 val32; | |
9207 | int retval = -EOPNOTSUPP; | |
9208 | ||
9209 | dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", | |
9210 | __func__, cmd, key->cipher, key->keyidx); | |
9211 | ||
9212 | if (vif->type != NL80211_IFTYPE_STATION) | |
9213 | return -EOPNOTSUPP; | |
9214 | ||
9215 | if (key->keyidx > 3) | |
9216 | return -EOPNOTSUPP; | |
9217 | ||
9218 | switch (key->cipher) { | |
9219 | case WLAN_CIPHER_SUITE_WEP40: | |
9220 | case WLAN_CIPHER_SUITE_WEP104: | |
9221 | ||
9222 | break; | |
9223 | case WLAN_CIPHER_SUITE_CCMP: | |
9224 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; | |
9225 | break; | |
9226 | case WLAN_CIPHER_SUITE_TKIP: | |
9227 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
9228 | default: | |
9229 | return -EOPNOTSUPP; | |
9230 | } | |
9231 | ||
9232 | if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { | |
9233 | dev_dbg(dev, "%s: pairwise key\n", __func__); | |
9234 | ether_addr_copy(mac_addr, sta->addr); | |
9235 | } else { | |
9236 | dev_dbg(dev, "%s: group key\n", __func__); | |
9237 | eth_broadcast_addr(mac_addr); | |
9238 | } | |
9239 | ||
9240 | val16 = rtl8xxxu_read16(priv, REG_CR); | |
9241 | val16 |= CR_SECURITY_ENABLE; | |
9242 | rtl8xxxu_write16(priv, REG_CR, val16); | |
9243 | ||
9244 | val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | | |
9245 | SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; | |
9246 | val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; | |
9247 | rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); | |
9248 | ||
9249 | switch (cmd) { | |
9250 | case SET_KEY: | |
9251 | key->hw_key_idx = key->keyidx; | |
9252 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
9253 | rtl8xxxu_cam_write(priv, key, mac_addr); | |
9254 | retval = 0; | |
9255 | break; | |
9256 | case DISABLE_KEY: | |
9257 | rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); | |
9258 | val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | | |
9259 | key->keyidx << CAM_CMD_KEY_SHIFT; | |
9260 | rtl8xxxu_write32(priv, REG_CAM_CMD, val32); | |
9261 | retval = 0; | |
9262 | break; | |
9263 | default: | |
9264 | dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); | |
9265 | } | |
9266 | ||
9267 | return retval; | |
9268 | } | |
9269 | ||
9270 | static int | |
9271 | rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, | |
50ea05ef | 9272 | struct ieee80211_ampdu_params *params) |
26f1fad2 JS |
9273 | { |
9274 | struct rtl8xxxu_priv *priv = hw->priv; | |
9275 | struct device *dev = &priv->udev->dev; | |
9276 | u8 ampdu_factor, ampdu_density; | |
50ea05ef SS |
9277 | struct ieee80211_sta *sta = params->sta; |
9278 | enum ieee80211_ampdu_mlme_action action = params->action; | |
26f1fad2 JS |
9279 | |
9280 | switch (action) { | |
9281 | case IEEE80211_AMPDU_TX_START: | |
9282 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); | |
9283 | ampdu_factor = sta->ht_cap.ampdu_factor; | |
9284 | ampdu_density = sta->ht_cap.ampdu_density; | |
9285 | rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); | |
9286 | rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); | |
9287 | dev_dbg(dev, | |
9288 | "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", | |
9289 | ampdu_factor, ampdu_density); | |
9290 | break; | |
9291 | case IEEE80211_AMPDU_TX_STOP_FLUSH: | |
9292 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__); | |
9293 | rtl8xxxu_set_ampdu_factor(priv, 0); | |
9294 | rtl8xxxu_set_ampdu_min_space(priv, 0); | |
9295 | break; | |
9296 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: | |
9297 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n", | |
9298 | __func__); | |
9299 | rtl8xxxu_set_ampdu_factor(priv, 0); | |
9300 | rtl8xxxu_set_ampdu_min_space(priv, 0); | |
9301 | break; | |
9302 | case IEEE80211_AMPDU_RX_START: | |
9303 | dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); | |
9304 | break; | |
9305 | case IEEE80211_AMPDU_RX_STOP: | |
9306 | dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); | |
9307 | break; | |
9308 | default: | |
9309 | break; | |
9310 | } | |
9311 | return 0; | |
9312 | } | |
9313 | ||
9314 | static int rtl8xxxu_start(struct ieee80211_hw *hw) | |
9315 | { | |
9316 | struct rtl8xxxu_priv *priv = hw->priv; | |
9317 | struct rtl8xxxu_rx_urb *rx_urb; | |
9318 | struct rtl8xxxu_tx_urb *tx_urb; | |
9319 | unsigned long flags; | |
9320 | int ret, i; | |
9321 | ||
9322 | ret = 0; | |
9323 | ||
9324 | init_usb_anchor(&priv->rx_anchor); | |
9325 | init_usb_anchor(&priv->tx_anchor); | |
9326 | init_usb_anchor(&priv->int_anchor); | |
9327 | ||
db08de94 | 9328 | priv->fops->enable_rf(priv); |
0e28b975 JS |
9329 | if (priv->usb_interrupts) { |
9330 | ret = rtl8xxxu_submit_int_urb(hw); | |
9331 | if (ret) | |
9332 | goto exit; | |
9333 | } | |
26f1fad2 JS |
9334 | |
9335 | for (i = 0; i < RTL8XXXU_TX_URBS; i++) { | |
9336 | tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); | |
9337 | if (!tx_urb) { | |
9338 | if (!i) | |
9339 | ret = -ENOMEM; | |
9340 | ||
9341 | goto error_out; | |
9342 | } | |
9343 | usb_init_urb(&tx_urb->urb); | |
9344 | INIT_LIST_HEAD(&tx_urb->list); | |
9345 | tx_urb->hw = hw; | |
9346 | list_add(&tx_urb->list, &priv->tx_urb_free_list); | |
9347 | priv->tx_urb_free_count++; | |
9348 | } | |
9349 | ||
9350 | priv->tx_stopped = false; | |
9351 | ||
9352 | spin_lock_irqsave(&priv->rx_urb_lock, flags); | |
9353 | priv->shutdown = false; | |
9354 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); | |
9355 | ||
9356 | for (i = 0; i < RTL8XXXU_RX_URBS; i++) { | |
9357 | rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); | |
9358 | if (!rx_urb) { | |
9359 | if (!i) | |
9360 | ret = -ENOMEM; | |
9361 | ||
9362 | goto error_out; | |
9363 | } | |
9364 | usb_init_urb(&rx_urb->urb); | |
9365 | INIT_LIST_HEAD(&rx_urb->list); | |
9366 | rx_urb->hw = hw; | |
9367 | ||
9368 | ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); | |
9369 | } | |
9370 | exit: | |
9371 | /* | |
c85ea115 | 9372 | * Accept all data and mgmt frames |
26f1fad2 | 9373 | */ |
c85ea115 | 9374 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); |
26f1fad2 JS |
9375 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); |
9376 | ||
9377 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e); | |
9378 | ||
9379 | return ret; | |
9380 | ||
9381 | error_out: | |
9382 | rtl8xxxu_free_tx_resources(priv); | |
9383 | /* | |
9384 | * Disable all data and mgmt frames | |
9385 | */ | |
9386 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); | |
9387 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); | |
9388 | ||
9389 | return ret; | |
9390 | } | |
9391 | ||
9392 | static void rtl8xxxu_stop(struct ieee80211_hw *hw) | |
9393 | { | |
9394 | struct rtl8xxxu_priv *priv = hw->priv; | |
9395 | unsigned long flags; | |
9396 | ||
9397 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); | |
9398 | ||
9399 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); | |
9400 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); | |
9401 | ||
9402 | spin_lock_irqsave(&priv->rx_urb_lock, flags); | |
9403 | priv->shutdown = true; | |
9404 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); | |
9405 | ||
9406 | usb_kill_anchored_urbs(&priv->rx_anchor); | |
9407 | usb_kill_anchored_urbs(&priv->tx_anchor); | |
0e28b975 JS |
9408 | if (priv->usb_interrupts) |
9409 | usb_kill_anchored_urbs(&priv->int_anchor); | |
26f1fad2 | 9410 | |
fc89a41f | 9411 | priv->fops->disable_rf(priv); |
26f1fad2 JS |
9412 | |
9413 | /* | |
9414 | * Disable interrupts | |
9415 | */ | |
0e28b975 JS |
9416 | if (priv->usb_interrupts) |
9417 | rtl8xxxu_write32(priv, REG_USB_HIMR, 0); | |
26f1fad2 JS |
9418 | |
9419 | rtl8xxxu_free_rx_resources(priv); | |
9420 | rtl8xxxu_free_tx_resources(priv); | |
9421 | } | |
9422 | ||
9423 | static const struct ieee80211_ops rtl8xxxu_ops = { | |
9424 | .tx = rtl8xxxu_tx, | |
9425 | .add_interface = rtl8xxxu_add_interface, | |
9426 | .remove_interface = rtl8xxxu_remove_interface, | |
9427 | .config = rtl8xxxu_config, | |
9428 | .conf_tx = rtl8xxxu_conf_tx, | |
9429 | .bss_info_changed = rtl8xxxu_bss_info_changed, | |
9430 | .configure_filter = rtl8xxxu_configure_filter, | |
9431 | .set_rts_threshold = rtl8xxxu_set_rts_threshold, | |
9432 | .start = rtl8xxxu_start, | |
9433 | .stop = rtl8xxxu_stop, | |
9434 | .sw_scan_start = rtl8xxxu_sw_scan_start, | |
9435 | .sw_scan_complete = rtl8xxxu_sw_scan_complete, | |
9436 | .set_key = rtl8xxxu_set_key, | |
9437 | .ampdu_action = rtl8xxxu_ampdu_action, | |
9438 | }; | |
9439 | ||
9440 | static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, | |
9441 | struct usb_interface *interface) | |
9442 | { | |
9443 | struct usb_interface_descriptor *interface_desc; | |
9444 | struct usb_host_interface *host_interface; | |
9445 | struct usb_endpoint_descriptor *endpoint; | |
9446 | struct device *dev = &priv->udev->dev; | |
9447 | int i, j = 0, endpoints; | |
9448 | u8 dir, xtype, num; | |
9449 | int ret = 0; | |
9450 | ||
9451 | host_interface = &interface->altsetting[0]; | |
9452 | interface_desc = &host_interface->desc; | |
9453 | endpoints = interface_desc->bNumEndpoints; | |
9454 | ||
9455 | for (i = 0; i < endpoints; i++) { | |
9456 | endpoint = &host_interface->endpoint[i].desc; | |
9457 | ||
9458 | dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; | |
9459 | num = usb_endpoint_num(endpoint); | |
9460 | xtype = usb_endpoint_type(endpoint); | |
9461 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) | |
9462 | dev_dbg(dev, | |
9463 | "%s: endpoint: dir %02x, # %02x, type %02x\n", | |
9464 | __func__, dir, num, xtype); | |
9465 | if (usb_endpoint_dir_in(endpoint) && | |
9466 | usb_endpoint_xfer_bulk(endpoint)) { | |
9467 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) | |
9468 | dev_dbg(dev, "%s: in endpoint num %i\n", | |
9469 | __func__, num); | |
9470 | ||
9471 | if (priv->pipe_in) { | |
9472 | dev_warn(dev, | |
9473 | "%s: Too many IN pipes\n", __func__); | |
9474 | ret = -EINVAL; | |
9475 | goto exit; | |
9476 | } | |
9477 | ||
9478 | priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); | |
9479 | } | |
9480 | ||
9481 | if (usb_endpoint_dir_in(endpoint) && | |
9482 | usb_endpoint_xfer_int(endpoint)) { | |
9483 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) | |
9484 | dev_dbg(dev, "%s: interrupt endpoint num %i\n", | |
9485 | __func__, num); | |
9486 | ||
9487 | if (priv->pipe_interrupt) { | |
9488 | dev_warn(dev, "%s: Too many INTERRUPT pipes\n", | |
9489 | __func__); | |
9490 | ret = -EINVAL; | |
9491 | goto exit; | |
9492 | } | |
9493 | ||
9494 | priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); | |
9495 | } | |
9496 | ||
9497 | if (usb_endpoint_dir_out(endpoint) && | |
9498 | usb_endpoint_xfer_bulk(endpoint)) { | |
9499 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) | |
9500 | dev_dbg(dev, "%s: out endpoint num %i\n", | |
9501 | __func__, num); | |
9502 | if (j >= RTL8XXXU_OUT_ENDPOINTS) { | |
9503 | dev_warn(dev, | |
9504 | "%s: Too many OUT pipes\n", __func__); | |
9505 | ret = -EINVAL; | |
9506 | goto exit; | |
9507 | } | |
9508 | priv->out_ep[j++] = num; | |
9509 | } | |
9510 | } | |
9511 | exit: | |
9512 | priv->nr_out_eps = j; | |
9513 | return ret; | |
9514 | } | |
9515 | ||
9516 | static int rtl8xxxu_probe(struct usb_interface *interface, | |
9517 | const struct usb_device_id *id) | |
9518 | { | |
9519 | struct rtl8xxxu_priv *priv; | |
9520 | struct ieee80211_hw *hw; | |
9521 | struct usb_device *udev; | |
9522 | struct ieee80211_supported_band *sband; | |
9523 | int ret = 0; | |
9524 | int untested = 1; | |
9525 | ||
9526 | udev = usb_get_dev(interface_to_usbdev(interface)); | |
9527 | ||
9528 | switch (id->idVendor) { | |
9529 | case USB_VENDOR_ID_REALTEK: | |
9530 | switch(id->idProduct) { | |
9531 | case 0x1724: | |
9532 | case 0x8176: | |
9533 | case 0x8178: | |
9534 | case 0x817f: | |
9535 | untested = 0; | |
9536 | break; | |
9537 | } | |
9538 | break; | |
9539 | case 0x7392: | |
9540 | if (id->idProduct == 0x7811) | |
9541 | untested = 0; | |
9542 | break; | |
9543 | default: | |
9544 | break; | |
9545 | } | |
9546 | ||
9547 | if (untested) { | |
eaa4d14c | 9548 | rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; |
26f1fad2 JS |
9549 | dev_info(&udev->dev, |
9550 | "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", | |
9551 | id->idVendor, id->idProduct); | |
9552 | dev_info(&udev->dev, | |
9553 | "Please report results to Jes.Sorensen@gmail.com\n"); | |
9554 | } | |
9555 | ||
9556 | hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); | |
9557 | if (!hw) { | |
9558 | ret = -ENOMEM; | |
9559 | goto exit; | |
9560 | } | |
9561 | ||
9562 | priv = hw->priv; | |
9563 | priv->hw = hw; | |
9564 | priv->udev = udev; | |
9565 | priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; | |
9566 | mutex_init(&priv->usb_buf_mutex); | |
9567 | mutex_init(&priv->h2c_mutex); | |
9568 | INIT_LIST_HEAD(&priv->tx_urb_free_list); | |
9569 | spin_lock_init(&priv->tx_urb_lock); | |
9570 | INIT_LIST_HEAD(&priv->rx_urb_pending_list); | |
9571 | spin_lock_init(&priv->rx_urb_lock); | |
9572 | INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); | |
9573 | ||
9574 | usb_set_intfdata(interface, hw); | |
9575 | ||
9576 | ret = rtl8xxxu_parse_usb(priv, interface); | |
9577 | if (ret) | |
9578 | goto exit; | |
9579 | ||
9580 | ret = rtl8xxxu_identify_chip(priv); | |
9581 | if (ret) { | |
9582 | dev_err(&udev->dev, "Fatal - failed to identify chip\n"); | |
9583 | goto exit; | |
9584 | } | |
9585 | ||
9586 | ret = rtl8xxxu_read_efuse(priv); | |
9587 | if (ret) { | |
9588 | dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); | |
9589 | goto exit; | |
9590 | } | |
9591 | ||
9592 | ret = priv->fops->parse_efuse(priv); | |
9593 | if (ret) { | |
9594 | dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); | |
9595 | goto exit; | |
9596 | } | |
9597 | ||
9598 | rtl8xxxu_print_chipinfo(priv); | |
9599 | ||
9600 | ret = priv->fops->load_firmware(priv); | |
9601 | if (ret) { | |
9602 | dev_err(&udev->dev, "Fatal - failed to load firmware\n"); | |
9603 | goto exit; | |
9604 | } | |
9605 | ||
9606 | ret = rtl8xxxu_init_device(hw); | |
9607 | ||
9608 | hw->wiphy->max_scan_ssids = 1; | |
9609 | hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; | |
9610 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); | |
9611 | hw->queues = 4; | |
9612 | ||
9613 | sband = &rtl8xxxu_supported_band; | |
9614 | sband->ht_cap.ht_supported = true; | |
9615 | sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; | |
9616 | sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; | |
9617 | sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; | |
9618 | memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); | |
9619 | sband->ht_cap.mcs.rx_mask[0] = 0xff; | |
9620 | sband->ht_cap.mcs.rx_mask[4] = 0x01; | |
9621 | if (priv->rf_paths > 1) { | |
9622 | sband->ht_cap.mcs.rx_mask[1] = 0xff; | |
9623 | sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; | |
9624 | } | |
9625 | sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
9626 | /* | |
9627 | * Some APs will negotiate HT20_40 in a noisy environment leading | |
9628 | * to miserable performance. Rather than defaulting to this, only | |
9629 | * enable it if explicitly requested at module load time. | |
9630 | */ | |
9631 | if (rtl8xxxu_ht40_2g) { | |
9632 | dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); | |
9633 | sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; | |
9634 | } | |
57fbcce3 | 9635 | hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; |
26f1fad2 JS |
9636 | |
9637 | hw->wiphy->rts_threshold = 2347; | |
9638 | ||
9639 | SET_IEEE80211_DEV(priv->hw, &interface->dev); | |
9640 | SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); | |
9641 | ||
179e1742 | 9642 | hw->extra_tx_headroom = priv->fops->tx_desc_size; |
26f1fad2 JS |
9643 | ieee80211_hw_set(hw, SIGNAL_DBM); |
9644 | /* | |
9645 | * The firmware handles rate control | |
9646 | */ | |
9647 | ieee80211_hw_set(hw, HAS_RATE_CONTROL); | |
9648 | ieee80211_hw_set(hw, AMPDU_AGGREGATION); | |
9649 | ||
9650 | ret = ieee80211_register_hw(priv->hw); | |
9651 | if (ret) { | |
9652 | dev_err(&udev->dev, "%s: Failed to register: %i\n", | |
9653 | __func__, ret); | |
9654 | goto exit; | |
9655 | } | |
9656 | ||
9657 | exit: | |
9658 | if (ret < 0) | |
9659 | usb_put_dev(udev); | |
9660 | return ret; | |
9661 | } | |
9662 | ||
9663 | static void rtl8xxxu_disconnect(struct usb_interface *interface) | |
9664 | { | |
9665 | struct rtl8xxxu_priv *priv; | |
9666 | struct ieee80211_hw *hw; | |
9667 | ||
9668 | hw = usb_get_intfdata(interface); | |
9669 | priv = hw->priv; | |
9670 | ||
9671 | rtl8xxxu_disable_device(hw); | |
9672 | usb_set_intfdata(interface, NULL); | |
9673 | ||
9674 | dev_info(&priv->udev->dev, "disconnecting\n"); | |
9675 | ||
9676 | ieee80211_unregister_hw(hw); | |
9677 | ||
9678 | kfree(priv->fw_data); | |
9679 | mutex_destroy(&priv->usb_buf_mutex); | |
9680 | mutex_destroy(&priv->h2c_mutex); | |
9681 | ||
9682 | usb_put_dev(priv->udev); | |
9683 | ieee80211_free_hw(hw); | |
9684 | } | |
9685 | ||
9686 | static struct rtl8xxxu_fileops rtl8723au_fops = { | |
9687 | .parse_efuse = rtl8723au_parse_efuse, | |
9688 | .load_firmware = rtl8723au_load_firmware, | |
9689 | .power_on = rtl8723au_power_on, | |
fe37d5f6 | 9690 | .power_off = rtl8xxxu_power_off, |
7d4ccb8b | 9691 | .reset_8051 = rtl8xxxu_reset_8051, |
74b99bed | 9692 | .llt_init = rtl8xxxu_init_llt_table, |
e1547c53 | 9693 | .phy_iq_calibrate = rtl8723au_phy_iq_calibrate, |
c3f9506f | 9694 | .config_channel = rtl8723au_config_channel, |
b18cdfdb | 9695 | .parse_rx_desc = rtl8723au_parse_rx_desc, |
db08de94 | 9696 | .enable_rf = rtl8723a_enable_rf, |
fc89a41f | 9697 | .disable_rf = rtl8723a_disable_rf, |
e796dab4 | 9698 | .set_tx_power = rtl8723a_set_tx_power, |
f653e690 | 9699 | .update_rate_mask = rtl8723au_update_rate_mask, |
7d794eaa | 9700 | .report_connect = rtl8723au_report_connect, |
26f1fad2 | 9701 | .writeN_block_size = 1024, |
ed35d094 JS |
9702 | .mbox_ext_reg = REG_HMBOX_EXT_0, |
9703 | .mbox_ext_width = 2, | |
dbb2896b | 9704 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), |
8634af5e JS |
9705 | .adda_1t_init = 0x0b1b25a0, |
9706 | .adda_1t_path_on = 0x0bdb25a0, | |
9707 | .adda_2t_path_on_a = 0x04db25a4, | |
9708 | .adda_2t_path_on_b = 0x0b1b25a4, | |
c606e662 | 9709 | .mactable = rtl8723a_mac_init_table, |
26f1fad2 JS |
9710 | }; |
9711 | ||
35a741fe | 9712 | static struct rtl8xxxu_fileops rtl8723bu_fops = { |
3c836d60 | 9713 | .parse_efuse = rtl8723bu_parse_efuse, |
35a741fe | 9714 | .load_firmware = rtl8723bu_load_firmware, |
42836db1 | 9715 | .power_on = rtl8723bu_power_on, |
fe37d5f6 | 9716 | .power_off = rtl8723bu_power_off, |
7d4ccb8b | 9717 | .reset_8051 = rtl8723bu_reset_8051, |
35a741fe | 9718 | .llt_init = rtl8xxxu_auto_llt_table, |
f0d9f5e9 | 9719 | .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, |
e1547c53 | 9720 | .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, |
c3f9506f | 9721 | .config_channel = rtl8723bu_config_channel, |
b18cdfdb | 9722 | .parse_rx_desc = rtl8723bu_parse_rx_desc, |
3e88ca44 | 9723 | .init_aggregation = rtl8723bu_init_aggregation, |
9c79bf95 | 9724 | .init_statistics = rtl8723bu_init_statistics, |
db08de94 | 9725 | .enable_rf = rtl8723b_enable_rf, |
fc89a41f | 9726 | .disable_rf = rtl8723b_disable_rf, |
e796dab4 | 9727 | .set_tx_power = rtl8723b_set_tx_power, |
f653e690 | 9728 | .update_rate_mask = rtl8723bu_update_rate_mask, |
7d794eaa | 9729 | .report_connect = rtl8723bu_report_connect, |
adfc0124 | 9730 | .writeN_block_size = 1024, |
ed35d094 JS |
9731 | .mbox_ext_reg = REG_HMBOX_EXT0_8723B, |
9732 | .mbox_ext_width = 4, | |
dbb2896b | 9733 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), |
0d698dec | 9734 | .has_s0s1 = 1, |
8634af5e JS |
9735 | .adda_1t_init = 0x01c00014, |
9736 | .adda_1t_path_on = 0x01c00014, | |
9737 | .adda_2t_path_on_a = 0x01c00014, | |
9738 | .adda_2t_path_on_b = 0x01c00014, | |
c606e662 | 9739 | .mactable = rtl8723b_mac_init_table, |
35a741fe JS |
9740 | }; |
9741 | ||
c0963772 KV |
9742 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
9743 | ||
26f1fad2 JS |
9744 | static struct rtl8xxxu_fileops rtl8192cu_fops = { |
9745 | .parse_efuse = rtl8192cu_parse_efuse, | |
9746 | .load_firmware = rtl8192cu_load_firmware, | |
9747 | .power_on = rtl8192cu_power_on, | |
fe37d5f6 | 9748 | .power_off = rtl8xxxu_power_off, |
7d4ccb8b | 9749 | .reset_8051 = rtl8xxxu_reset_8051, |
74b99bed | 9750 | .llt_init = rtl8xxxu_init_llt_table, |
e1547c53 | 9751 | .phy_iq_calibrate = rtl8723au_phy_iq_calibrate, |
c3f9506f | 9752 | .config_channel = rtl8723au_config_channel, |
b18cdfdb | 9753 | .parse_rx_desc = rtl8723au_parse_rx_desc, |
db08de94 | 9754 | .enable_rf = rtl8723a_enable_rf, |
fc89a41f | 9755 | .disable_rf = rtl8723a_disable_rf, |
e796dab4 | 9756 | .set_tx_power = rtl8723a_set_tx_power, |
f653e690 | 9757 | .update_rate_mask = rtl8723au_update_rate_mask, |
7d794eaa | 9758 | .report_connect = rtl8723au_report_connect, |
26f1fad2 | 9759 | .writeN_block_size = 128, |
ed35d094 JS |
9760 | .mbox_ext_reg = REG_HMBOX_EXT_0, |
9761 | .mbox_ext_width = 2, | |
dbb2896b | 9762 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), |
8634af5e JS |
9763 | .adda_1t_init = 0x0b1b25a0, |
9764 | .adda_1t_path_on = 0x0bdb25a0, | |
9765 | .adda_2t_path_on_a = 0x04db25a4, | |
9766 | .adda_2t_path_on_b = 0x0b1b25a4, | |
c606e662 | 9767 | .mactable = rtl8723a_mac_init_table, |
26f1fad2 JS |
9768 | }; |
9769 | ||
c0963772 KV |
9770 | #endif |
9771 | ||
3307d840 JS |
9772 | static struct rtl8xxxu_fileops rtl8192eu_fops = { |
9773 | .parse_efuse = rtl8192eu_parse_efuse, | |
9774 | .load_firmware = rtl8192eu_load_firmware, | |
c05a9dbf | 9775 | .power_on = rtl8192eu_power_on, |
fe37d5f6 | 9776 | .power_off = rtl8xxxu_power_off, |
7d4ccb8b | 9777 | .reset_8051 = rtl8xxxu_reset_8051, |
74b99bed | 9778 | .llt_init = rtl8xxxu_auto_llt_table, |
f991f4e9 | 9779 | .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate, |
c3f9506f | 9780 | .config_channel = rtl8723bu_config_channel, |
b18cdfdb | 9781 | .parse_rx_desc = rtl8723bu_parse_rx_desc, |
db08de94 | 9782 | .enable_rf = rtl8723b_enable_rf, |
fc89a41f | 9783 | .disable_rf = rtl8723b_disable_rf, |
e796dab4 | 9784 | .set_tx_power = rtl8723b_set_tx_power, |
91cbe4e7 JS |
9785 | .update_rate_mask = rtl8723bu_update_rate_mask, |
9786 | .report_connect = rtl8723bu_report_connect, | |
c05a9dbf | 9787 | .writeN_block_size = 128, |
ed35d094 JS |
9788 | .mbox_ext_reg = REG_HMBOX_EXT0_8723B, |
9789 | .mbox_ext_width = 4, | |
f3fc2511 | 9790 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), |
0d698dec | 9791 | .has_s0s1 = 1, |
8634af5e JS |
9792 | .adda_1t_init = 0x0fc01616, |
9793 | .adda_1t_path_on = 0x0fc01616, | |
9794 | .adda_2t_path_on_a = 0x0fc01616, | |
9795 | .adda_2t_path_on_b = 0x0fc01616, | |
c606e662 | 9796 | .mactable = rtl8192e_mac_init_table, |
89c2a097 JS |
9797 | .total_page_num = TX_TOTAL_PAGE_NUM_8192E, |
9798 | .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E, | |
9799 | .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E, | |
9800 | .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E, | |
3307d840 JS |
9801 | }; |
9802 | ||
26f1fad2 JS |
9803 | static struct usb_device_id dev_table[] = { |
9804 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), | |
9805 | .driver_info = (unsigned long)&rtl8723au_fops}, | |
9806 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), | |
9807 | .driver_info = (unsigned long)&rtl8723au_fops}, | |
9808 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), | |
9809 | .driver_info = (unsigned long)&rtl8723au_fops}, | |
3307d840 JS |
9810 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), |
9811 | .driver_info = (unsigned long)&rtl8192eu_fops}, | |
35a741fe JS |
9812 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), |
9813 | .driver_info = (unsigned long)&rtl8723bu_fops}, | |
033695bd KV |
9814 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
9815 | /* Still supported by rtlwifi */ | |
26f1fad2 JS |
9816 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), |
9817 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9818 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), | |
9819 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9820 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), | |
9821 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9822 | /* Tested by Larry Finger */ | |
9823 | {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), | |
9824 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
26f1fad2 JS |
9825 | /* Currently untested 8188 series devices */ |
9826 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), | |
9827 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9828 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), | |
9829 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9830 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), | |
9831 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9832 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), | |
9833 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9834 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), | |
9835 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9836 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), | |
9837 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9838 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), | |
9839 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9840 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), | |
9841 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9842 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), | |
9843 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9844 | {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), | |
9845 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9846 | {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), | |
9847 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9848 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), | |
9849 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9850 | {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), | |
9851 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9852 | {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), | |
9853 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9854 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), | |
9855 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9856 | {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), | |
9857 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9858 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), | |
9859 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9860 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), | |
9861 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9862 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), | |
9863 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9864 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), | |
9865 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9866 | {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), | |
9867 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9868 | {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), | |
9869 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9870 | {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), | |
9871 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9872 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), | |
9873 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9874 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), | |
9875 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9876 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), | |
9877 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9878 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), | |
9879 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9880 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), | |
9881 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9882 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), | |
9883 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9884 | {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), | |
9885 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9886 | {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), | |
9887 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9888 | {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), | |
9889 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9890 | {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), | |
9891 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
26f1fad2 JS |
9892 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), |
9893 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9894 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), | |
9895 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9896 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), | |
9897 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9898 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), | |
9899 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9900 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), | |
9901 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9902 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), | |
9903 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9904 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), | |
9905 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9906 | /* Currently untested 8192 series devices */ | |
9907 | {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), | |
9908 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9909 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), | |
9910 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9911 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), | |
9912 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9913 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), | |
9914 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9915 | {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), | |
9916 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9917 | {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), | |
9918 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9919 | {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), | |
9920 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9921 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), | |
9922 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9923 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), | |
9924 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9925 | {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), | |
9926 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9927 | {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), | |
9928 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9929 | {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), | |
9930 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9931 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), | |
9932 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9933 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), | |
9934 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9935 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), | |
9936 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9937 | {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), | |
9938 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9939 | {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), | |
9940 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9941 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), | |
9942 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9943 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), | |
9944 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9945 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), | |
9946 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9947 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), | |
9948 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9949 | {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), | |
9950 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9951 | {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), | |
9952 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9953 | {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), | |
9954 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9955 | {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), | |
9956 | .driver_info = (unsigned long)&rtl8192cu_fops}, | |
9957 | #endif | |
9958 | { } | |
9959 | }; | |
9960 | ||
9961 | static struct usb_driver rtl8xxxu_driver = { | |
9962 | .name = DRIVER_NAME, | |
9963 | .probe = rtl8xxxu_probe, | |
9964 | .disconnect = rtl8xxxu_disconnect, | |
9965 | .id_table = dev_table, | |
9966 | .disable_hub_initiated_lpm = 1, | |
9967 | }; | |
9968 | ||
9969 | static int __init rtl8xxxu_module_init(void) | |
9970 | { | |
9971 | int res; | |
9972 | ||
9973 | res = usb_register(&rtl8xxxu_driver); | |
9974 | if (res < 0) | |
9975 | pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res); | |
9976 | ||
9977 | return res; | |
9978 | } | |
9979 | ||
9980 | static void __exit rtl8xxxu_module_exit(void) | |
9981 | { | |
9982 | usb_deregister(&rtl8xxxu_driver); | |
9983 | } | |
9984 | ||
9985 | ||
9986 | MODULE_DEVICE_TABLE(usb, dev_table); | |
9987 | ||
9988 | module_init(rtl8xxxu_module_init); | |
9989 | module_exit(rtl8xxxu_module_exit); |