projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
rtl8xxxu: Set register 0xfe10 on rtl8192cu based parts
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
CommitLineData
26f1fad2
JS		 1/*
2 * RTL8XXXU mac80211 USB driver
3 *
eb188062 4 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
26f1fad2
JS		 5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
3307d840 45static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
b001e086 57MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
35a741fe
JS		 58MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
26f1fad2
JS		 60
61module_param_named(debug, rtl8xxxu_debug, int, 0600);
62MODULE_PARM_DESC(debug, "Set debug mask");
63module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
64MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
65
66#define USB_VENDOR_ID_REALTEK 0x0bda
67/* Minimum IEEE80211_MAX_FRAME_LEN */
68#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
69#define RTL8XXXU_RX_URBS 32
70#define RTL8XXXU_RX_URB_PENDING_WATER 8
71#define RTL8XXXU_TX_URBS 64
72#define RTL8XXXU_TX_URB_LOW_WATER 25
73#define RTL8XXXU_TX_URB_HIGH_WATER 32
74
75static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
76 struct rtl8xxxu_rx_urb *rx_urb);
77
78static struct ieee80211_rate rtl8xxxu_rates[] = {
79 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
80 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
81 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
82 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
83 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
84 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
85 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
86 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
87 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
88 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
89 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
90 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
91};
92
93static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
57fbcce3 94 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
26f1fad2 95 .hw_value = 1, .max_power = 30 },
57fbcce3 96 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
26f1fad2 97 .hw_value = 2, .max_power = 30 },
57fbcce3 98 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
26f1fad2 99 .hw_value = 3, .max_power = 30 },
57fbcce3 100 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
26f1fad2 101 .hw_value = 4, .max_power = 30 },
57fbcce3 102 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
26f1fad2 103 .hw_value = 5, .max_power = 30 },
57fbcce3 104 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
26f1fad2 105 .hw_value = 6, .max_power = 30 },
57fbcce3 106 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
26f1fad2 107 .hw_value = 7, .max_power = 30 },
57fbcce3 108 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
26f1fad2 109 .hw_value = 8, .max_power = 30 },
57fbcce3 110 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
26f1fad2 111 .hw_value = 9, .max_power = 30 },
57fbcce3 112 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
26f1fad2 113 .hw_value = 10, .max_power = 30 },
57fbcce3 114 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
26f1fad2 115 .hw_value = 11, .max_power = 30 },
57fbcce3 116 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
26f1fad2 117 .hw_value = 12, .max_power = 30 },
57fbcce3 118 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
26f1fad2 119 .hw_value = 13, .max_power = 30 },
57fbcce3 120 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
26f1fad2
JS		 121 .hw_value = 14, .max_power = 30 }
122};
123
124static struct ieee80211_supported_band rtl8xxxu_supported_band = {
125 .channels = rtl8xxxu_channels_2g,
126 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
127 .bitrates = rtl8xxxu_rates,
128 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
129};
130
131static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
132 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
133 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
134 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
135 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
136 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
137 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
138 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
139 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
140 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
141 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
142 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
143 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
144 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
145 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
146 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
147 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
148 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
149 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
150 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
151 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
152 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
153 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
154};
155
b7dd8ff9
JS		 156static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
157 {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
158 {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
159 {0x430, 0x00}, {0x431, 0x00},
160 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
161 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
162 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
163 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
164 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
165 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
166 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
167 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
168 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
169 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
170 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
171 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
172 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
173 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
174 {0x516, 0x0a}, {0x525, 0x4f},
175 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
176 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
177 {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
178 {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
179 {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
180 {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
181 {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
182 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
183 {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
184 {0xffff, 0xff},
185};
186
c606e662
JS		 187static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
188 {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
189 {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
190 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
191 {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
192 {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
193 {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
194 {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
195 {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
196 {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
197 {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
198 {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
199 {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
200 {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
201 {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
202 {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
203 {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
204 {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
205 {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
206 {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
207 {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
208 {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
209 {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
210 {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
211 {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
212 {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
213 {0x70b, 0x87},
214 {0xffff, 0xff},
215};
216
26f1fad2
JS		 217static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
218 {0x800, 0x80040000}, {0x804, 0x00000003},
219 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
220 {0x810, 0x10001331}, {0x814, 0x020c3d10},
221 {0x818, 0x02200385}, {0x81c, 0x00000000},
222 {0x820, 0x01000100}, {0x824, 0x00390004},
223 {0x828, 0x00000000}, {0x82c, 0x00000000},
224 {0x830, 0x00000000}, {0x834, 0x00000000},
225 {0x838, 0x00000000}, {0x83c, 0x00000000},
226 {0x840, 0x00010000}, {0x844, 0x00000000},
227 {0x848, 0x00000000}, {0x84c, 0x00000000},
228 {0x850, 0x00000000}, {0x854, 0x00000000},
229 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
230 {0x860, 0x66f60110}, {0x864, 0x061f0130},
231 {0x868, 0x00000000}, {0x86c, 0x32323200},
232 {0x870, 0x07000760}, {0x874, 0x22004000},
233 {0x878, 0x00000808}, {0x87c, 0x00000000},
234 {0x880, 0xc0083070}, {0x884, 0x000004d5},
235 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
236 {0x890, 0x00000800}, {0x894, 0xfffffffe},
237 {0x898, 0x40302010}, {0x89c, 0x00706050},
238 {0x900, 0x00000000}, {0x904, 0x00000023},
239 {0x908, 0x00000000}, {0x90c, 0x81121111},
240 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
241 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
242 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
243 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
244 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
245 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
246 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
247 {0xa78, 0x00000900},
248 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
249 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
250 {0xc10, 0x08800000}, {0xc14, 0x40000100},
251 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
252 {0xc20, 0x00000000}, {0xc24, 0x00000000},
253 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
254 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
255 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
256 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
257 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
258 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
259 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
260 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
261 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
262 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
263 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
264 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
265 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
266 {0xc90, 0x00121820}, {0xc94, 0x00000000},
267 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
268 {0xca0, 0x00000000}, {0xca4, 0x00000080},
269 {0xca8, 0x00000000}, {0xcac, 0x00000000},
270 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
271 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
272 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
273 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
274 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
275 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
276 {0xce0, 0x00222222}, {0xce4, 0x00000000},
277 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
278 {0xd00, 0x00080740}, {0xd04, 0x00020401},
279 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
280 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
281 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
282 {0xd30, 0x00000000}, {0xd34, 0x80608000},
283 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
284 {0xd40, 0x00000000}, {0xd44, 0x00000000},
285 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
286 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
287 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
288 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
289 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
290 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
291 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
292 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
293 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
294 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
295 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
296 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
297 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
298 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
299 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
300 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
301 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
302 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
303 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
304 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
305 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
306 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
307 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
308 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
309 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
310 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
311 {0xf00, 0x00000300},
312 {0xffff, 0xffffffff},
313};
314
36c32588
JS		 315static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
316 {0x800, 0x80040000}, {0x804, 0x00000003},
317 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
318 {0x810, 0x10001331}, {0x814, 0x020c3d10},
319 {0x818, 0x02200385}, {0x81c, 0x00000000},
320 {0x820, 0x01000100}, {0x824, 0x00190204},
321 {0x828, 0x00000000}, {0x82c, 0x00000000},
322 {0x830, 0x00000000}, {0x834, 0x00000000},
323 {0x838, 0x00000000}, {0x83c, 0x00000000},
324 {0x840, 0x00010000}, {0x844, 0x00000000},
325 {0x848, 0x00000000}, {0x84c, 0x00000000},
326 {0x850, 0x00000000}, {0x854, 0x00000000},
327 {0x858, 0x569a11a9}, {0x85c, 0x01000014},
328 {0x860, 0x66f60110}, {0x864, 0x061f0649},
329 {0x868, 0x00000000}, {0x86c, 0x27272700},
330 {0x870, 0x07000760}, {0x874, 0x25004000},
331 {0x878, 0x00000808}, {0x87c, 0x00000000},
332 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
333 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
334 {0x890, 0x00000800}, {0x894, 0xfffffffe},
335 {0x898, 0x40302010}, {0x89c, 0x00706050},
336 {0x900, 0x00000000}, {0x904, 0x00000023},
337 {0x908, 0x00000000}, {0x90c, 0x81121111},
338 {0x910, 0x00000002}, {0x914, 0x00000201},
339 {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
340 {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
341 {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
342 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
343 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
344 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
345 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
346 {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
347 {0xa80, 0x21806490}, {0xb2c, 0x00000000},
348 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
349 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
350 {0xc10, 0x08800000}, {0xc14, 0x40000100},
351 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
352 {0xc20, 0x00000000}, {0xc24, 0x00000000},
353 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
354 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
355 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
356 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
357 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
358 {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
359 {0xc58, 0x00013149}, {0xc5c, 0x00250492},
360 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
361 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
362 {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
363 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
364 {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
365 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
366 {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
367 {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
368 {0xca0, 0x00000000}, {0xca4, 0x000300a0},
369 {0xca8, 0x00000000}, {0xcac, 0x00000000},
370 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
371 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
372 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
373 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
374 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
375 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
376 {0xce0, 0x00222222}, {0xce4, 0x00000000},
377 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
378 {0xd00, 0x00000740}, {0xd04, 0x40020401},
379 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
380 {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
381 {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
382 {0xd30, 0x00000000}, {0xd34, 0x80608000},
383 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
384 {0xd40, 0x00000000}, {0xd44, 0x00000000},
385 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
386 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
387 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
388 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
389 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
390 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
391 {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
392 {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
393 {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
394 {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
395 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
396 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
397 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
398 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
399 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
400 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
401 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
402 {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
403 {0xe70, 0x00c00096}, {0xe74, 0x01000056},
404 {0xe78, 0x01000014}, {0xe7c, 0x01000056},
405 {0xe80, 0x01000014}, {0xe84, 0x00c00096},
406 {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
407 {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
408 {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
409 {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
410 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
411 {0xf00, 0x00000300},
412 {0x820, 0x01000100}, {0x800, 0x83040000},
413 {0xffff, 0xffffffff},
414};
415
26f1fad2
JS		 416static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
417 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
418 {0x800, 0x80040002}, {0x804, 0x00000003},
419 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
420 {0x810, 0x10000330}, {0x814, 0x020c3d10},
421 {0x818, 0x02200385}, {0x81c, 0x00000000},
422 {0x820, 0x01000100}, {0x824, 0x00390004},
423 {0x828, 0x01000100}, {0x82c, 0x00390004},
424 {0x830, 0x27272727}, {0x834, 0x27272727},
425 {0x838, 0x27272727}, {0x83c, 0x27272727},
426 {0x840, 0x00010000}, {0x844, 0x00010000},
427 {0x848, 0x27272727}, {0x84c, 0x27272727},
428 {0x850, 0x00000000}, {0x854, 0x00000000},
429 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
430 {0x860, 0x66e60230}, {0x864, 0x061f0130},
431 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
432 {0x870, 0x07000700}, {0x874, 0x22184000},
433 {0x878, 0x08080808}, {0x87c, 0x00000000},
434 {0x880, 0xc0083070}, {0x884, 0x000004d5},
435 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
436 {0x890, 0x00000800}, {0x894, 0xfffffffe},
437 {0x898, 0x40302010}, {0x89c, 0x00706050},
438 {0x900, 0x00000000}, {0x904, 0x00000023},
439 {0x908, 0x00000000}, {0x90c, 0x81121313},
440 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
441 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
442 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
443 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
444 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
445 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
446 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
447 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
448 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
449 {0xc10, 0x08800000}, {0xc14, 0x40000100},
450 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
451 {0xc20, 0x00000000}, {0xc24, 0x00000000},
452 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
453 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
454 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
455 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
456 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
457 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
458 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
459 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
460 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
461 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
462 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
463 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
464 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
465 {0xc90, 0x00121820}, {0xc94, 0x00000000},
466 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
467 {0xca0, 0x00000000}, {0xca4, 0x00000080},
468 {0xca8, 0x00000000}, {0xcac, 0x00000000},
469 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
470 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
471 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
472 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
473 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
474 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
475 {0xce0, 0x00222222}, {0xce4, 0x00000000},
476 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
477 {0xd00, 0x00080740}, {0xd04, 0x00020403},
478 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
479 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
480 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
481 {0xd30, 0x00000000}, {0xd34, 0x80608000},
482 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
483 {0xd40, 0x00000000}, {0xd44, 0x00000000},
484 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
485 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
486 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
487 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
488 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
489 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
490 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
491 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
492 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
493 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
494 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
495 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
496 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
497 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
498 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
499 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
500 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
501 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
502 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
503 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
504 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
505 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
506 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
507 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
508 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
509 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
510 {0xf00, 0x00000300},
511 {0xffff, 0xffffffff},
512};
513
514static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
515 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
516 {0x040, 0x000c0004}, {0x800, 0x80040000},
517 {0x804, 0x00000001}, {0x808, 0x0000fc00},
518 {0x80c, 0x0000000a}, {0x810, 0x10005388},
519 {0x814, 0x020c3d10}, {0x818, 0x02200385},
520 {0x81c, 0x00000000}, {0x820, 0x01000100},
521 {0x824, 0x00390204}, {0x828, 0x00000000},
522 {0x82c, 0x00000000}, {0x830, 0x00000000},
523 {0x834, 0x00000000}, {0x838, 0x00000000},
524 {0x83c, 0x00000000}, {0x840, 0x00010000},
525 {0x844, 0x00000000}, {0x848, 0x00000000},
526 {0x84c, 0x00000000}, {0x850, 0x00000000},
527 {0x854, 0x00000000}, {0x858, 0x569a569a},
528 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
529 {0x864, 0x061f0130}, {0x868, 0x00000000},
530 {0x86c, 0x20202000}, {0x870, 0x03000300},
531 {0x874, 0x22004000}, {0x878, 0x00000808},
532 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
533 {0x884, 0x000004d5}, {0x888, 0x00000000},
534 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
535 {0x894, 0xfffffffe}, {0x898, 0x40302010},
536 {0x89c, 0x00706050}, {0x900, 0x00000000},
537 {0x904, 0x00000023}, {0x908, 0x00000000},
538 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
539 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
540 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
541 {0xa14, 0x11144028}, {0xa18, 0x00881117},
542 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
543 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
544 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
545 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
546 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
547 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
548 {0xc14, 0x40000100}, {0xc18, 0x08800000},
549 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
550 {0xc24, 0x00000000}, {0xc28, 0x00000000},
551 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
552 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
553 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
554 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
555 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
556 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
557 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
558 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
559 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
560 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
561 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
562 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
563 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
564 {0xc94, 0x00000000}, {0xc98, 0x00121820},
565 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
566 {0xca4, 0x00000080}, {0xca8, 0x00000000},
567 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
568 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
569 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
570 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
571 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
572 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
573 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
574 {0xce4, 0x00000000}, {0xce8, 0x37644302},
575 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
576 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
577 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
578 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
579 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
580 {0xd34, 0x80608000}, {0xd38, 0x00000000},
581 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
582 {0xd44, 0x00000000}, {0xd48, 0x00000000},
583 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
584 {0xd54, 0x00000000}, {0xd58, 0x00000000},
585 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
586 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
587 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
588 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
589 {0xe00, 0x24242424}, {0xe04, 0x24242424},
590 {0xe08, 0x03902024}, {0xe10, 0x24242424},
591 {0xe14, 0x24242424}, {0xe18, 0x24242424},
592 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
593 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
594 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
595 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
596 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
597 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
598 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
599 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
600 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
601 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
602 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
603 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
604 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
605 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
606 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
607 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
608 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
609 {0xf00, 0x00000300},
610 {0xffff, 0xffffffff},
611};
612
ae14c5d2
JS		 613static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
614 {0x800, 0x80040000}, {0x804, 0x00000003},
615 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
616 {0x810, 0x10001331}, {0x814, 0x020c3d10},
617 {0x818, 0x02220385}, {0x81c, 0x00000000},
618 {0x820, 0x01000100}, {0x824, 0x00390204},
619 {0x828, 0x01000100}, {0x82c, 0x00390204},
620 {0x830, 0x32323232}, {0x834, 0x30303030},
621 {0x838, 0x30303030}, {0x83c, 0x30303030},
622 {0x840, 0x00010000}, {0x844, 0x00010000},
623 {0x848, 0x28282828}, {0x84c, 0x28282828},
624 {0x850, 0x00000000}, {0x854, 0x00000000},
625 {0x858, 0x009a009a}, {0x85c, 0x01000014},
626 {0x860, 0x66f60000}, {0x864, 0x061f0000},
627 {0x868, 0x30303030}, {0x86c, 0x30303030},
628 {0x870, 0x00000000}, {0x874, 0x55004200},
629 {0x878, 0x08080808}, {0x87c, 0x00000000},
630 {0x880, 0xb0000c1c}, {0x884, 0x00000001},
631 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
632 {0x890, 0x00000800}, {0x894, 0xfffffffe},
633 {0x898, 0x40302010}, {0x900, 0x00000000},
634 {0x904, 0x00000023}, {0x908, 0x00000000},
635 {0x90c, 0x81121313}, {0x910, 0x806c0001},
636 {0x914, 0x00000001}, {0x918, 0x00000000},
637 {0x91c, 0x00010000}, {0x924, 0x00000001},
638 {0x928, 0x00000000}, {0x92c, 0x00000000},
639 {0x930, 0x00000000}, {0x934, 0x00000000},
640 {0x938, 0x00000000}, {0x93c, 0x00000000},
641 {0x940, 0x00000000}, {0x944, 0x00000000},
642 {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
643 {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
644 {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
645 {0xa14, 0x1114d028}, {0xa18, 0x00881117},
646 {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
647 {0xa24, 0x090e1317}, {0xa28, 0x00000204},
648 {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
649 {0xa74, 0x00000007}, {0xa78, 0x00000900},
650 {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
651 {0xb38, 0x00000000}, {0xc00, 0x48071d40},
652 {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
653 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
654 {0xc14, 0x40000100}, {0xc18, 0x08800000},
655 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
656 {0xc24, 0x00000000}, {0xc28, 0x00000000},
657 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
658 {0xc34, 0x469652af}, {0xc38, 0x49795994},
659 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
660 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
661 {0xc4c, 0x007f037f},
662#ifdef EXT_PA_8192EU
663 /* External PA or external LNA */
664 {0xc50, 0x00340220},
665#else
666 {0xc50, 0x00340020},
667#endif
668 {0xc54, 0x0080801f},
669#ifdef EXT_PA_8192EU
670 /* External PA or external LNA */
671 {0xc58, 0x00000220},
672#else
673 {0xc58, 0x00000020},
674#endif
675 {0xc5c, 0x00248492}, {0xc60, 0x00000000},
676 {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
677 {0xc6c, 0x00000036}, {0xc70, 0x00000600},
678 {0xc74, 0x02013169}, {0xc78, 0x0000001f},
679 {0xc7c, 0x00b91612},
680#ifdef EXT_PA_8192EU
681 /* External PA or external LNA */
682 {0xc80, 0x2d4000b5},
683#else
684 {0xc80, 0x40000100},
685#endif
686 {0xc84, 0x21f60000},
687#ifdef EXT_PA_8192EU
688 /* External PA or external LNA */
689 {0xc88, 0x2d4000b5},
690#else
691 {0xc88, 0x40000100},
692#endif
693 {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
694 {0xc94, 0x00000000}, {0xc98, 0x00121820},
695 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
696 {0xca4, 0x000300a0}, {0xca8, 0x00000000},
697 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
698 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
699 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
700 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
701 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
702 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
703 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
704 {0xce4, 0x00040000}, {0xce8, 0x77644302},
705 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
706 {0xd04, 0x00020403}, {0xd08, 0x0000907f},
707 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
708 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
709 {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
710 {0xd30, 0x00000000}, {0xd34, 0x80608000},
711 {0xd38, 0x00000000}, {0xd3c, 0x00127353},
712 {0xd40, 0x00000000}, {0xd44, 0x00000000},
713 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
714 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
715 {0xd58, 0x00000282}, {0xd5c, 0x30032064},
716 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
717 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
718 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
719 {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
720 {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
721 {0xe00, 0x30303030}, {0xe04, 0x30303030},
722 {0xe08, 0x03903030}, {0xe10, 0x30303030},
723 {0xe14, 0x30303030}, {0xe18, 0x30303030},
724 {0xe1c, 0x30303030}, {0xe28, 0x00000000},
725 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
726 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
727 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
728 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
729 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
730 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
731 {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
732 {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
733 {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
734 {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
735 {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
736 {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
737 {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
738 {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
739 {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
740 {0xee8, 0x00000001}, {0xf14, 0x00000003},
741 {0xf4c, 0x00000000}, {0xf00, 0x00000300},
742 {0xffff, 0xffffffff},
743};
744
26f1fad2
JS		 745static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
746 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
747 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
748 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
749 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
750 {0xc78, 0x78080001}, {0xc78, 0x77090001},
751 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
752 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
753 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
754 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
755 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
756 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
757 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
758 {0xc78, 0x68180001}, {0xc78, 0x67190001},
759 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
760 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
761 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
762 {0xc78, 0x60200001}, {0xc78, 0x49210001},
763 {0xc78, 0x48220001}, {0xc78, 0x47230001},
764 {0xc78, 0x46240001}, {0xc78, 0x45250001},
765 {0xc78, 0x44260001}, {0xc78, 0x43270001},
766 {0xc78, 0x42280001}, {0xc78, 0x41290001},
767 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
768 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
769 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
770 {0xc78, 0x21300001}, {0xc78, 0x20310001},
771 {0xc78, 0x06320001}, {0xc78, 0x05330001},
772 {0xc78, 0x04340001}, {0xc78, 0x03350001},
773 {0xc78, 0x02360001}, {0xc78, 0x01370001},
774 {0xc78, 0x00380001}, {0xc78, 0x00390001},
775 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
776 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
777 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
778 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
779 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
780 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
781 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
782 {0xc78, 0x78480001}, {0xc78, 0x77490001},
783 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
784 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
785 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
786 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
787 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
788 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
789 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
790 {0xc78, 0x68580001}, {0xc78, 0x67590001},
791 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
792 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
793 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
794 {0xc78, 0x60600001}, {0xc78, 0x49610001},
795 {0xc78, 0x48620001}, {0xc78, 0x47630001},
796 {0xc78, 0x46640001}, {0xc78, 0x45650001},
797 {0xc78, 0x44660001}, {0xc78, 0x43670001},
798 {0xc78, 0x42680001}, {0xc78, 0x41690001},
799 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
800 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
801 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
802 {0xc78, 0x21700001}, {0xc78, 0x20710001},
803 {0xc78, 0x06720001}, {0xc78, 0x05730001},
804 {0xc78, 0x04740001}, {0xc78, 0x03750001},
805 {0xc78, 0x02760001}, {0xc78, 0x01770001},
806 {0xc78, 0x00780001}, {0xc78, 0x00790001},
807 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
808 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
809 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
810 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
811 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
812 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
813 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
814 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
815 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
816 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
817 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
818 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
819 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
820 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
821 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
822 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
823 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
824 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
825 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
826 {0xffff, 0xffffffff}
827};
828
829static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
830 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
831 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
832 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
833 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
834 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
835 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
836 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
837 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
838 {0xc78, 0x73100001}, {0xc78, 0x72110001},
839 {0xc78, 0x71120001}, {0xc78, 0x70130001},
840 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
841 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
842 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
843 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
844 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
845 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
846 {0xc78, 0x63200001}, {0xc78, 0x62210001},
847 {0xc78, 0x61220001}, {0xc78, 0x60230001},
848 {0xc78, 0x46240001}, {0xc78, 0x45250001},
849 {0xc78, 0x44260001}, {0xc78, 0x43270001},
850 {0xc78, 0x42280001}, {0xc78, 0x41290001},
851 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
852 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
853 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
854 {0xc78, 0x21300001}, {0xc78, 0x20310001},
855 {0xc78, 0x06320001}, {0xc78, 0x05330001},
856 {0xc78, 0x04340001}, {0xc78, 0x03350001},
857 {0xc78, 0x02360001}, {0xc78, 0x01370001},
858 {0xc78, 0x00380001}, {0xc78, 0x00390001},
859 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
860 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
861 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
862 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
863 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
864 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
865 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
866 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
867 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
868 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
869 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
870 {0xc78, 0x73500001}, {0xc78, 0x72510001},
871 {0xc78, 0x71520001}, {0xc78, 0x70530001},
872 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
873 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
874 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
875 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
876 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
877 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
878 {0xc78, 0x63600001}, {0xc78, 0x62610001},
879 {0xc78, 0x61620001}, {0xc78, 0x60630001},
880 {0xc78, 0x46640001}, {0xc78, 0x45650001},
881 {0xc78, 0x44660001}, {0xc78, 0x43670001},
882 {0xc78, 0x42680001}, {0xc78, 0x41690001},
883 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
884 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
885 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
886 {0xc78, 0x21700001}, {0xc78, 0x20710001},
887 {0xc78, 0x06720001}, {0xc78, 0x05730001},
888 {0xc78, 0x04740001}, {0xc78, 0x03750001},
889 {0xc78, 0x02760001}, {0xc78, 0x01770001},
890 {0xc78, 0x00780001}, {0xc78, 0x00790001},
891 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
892 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
893 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
894 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
895 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
896 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
897 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
898 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
899 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
900 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
901 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
902 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
903 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
904 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
905 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
906 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
907 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
908 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
909 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
910 {0xffff, 0xffffffff}
911};
912
b9f498e1
JS		 913static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
914 {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
915 {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
916 {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
917 {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
918 {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
919 {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
920 {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
921 {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
922 {0xc78, 0xed100001}, {0xc78, 0xec110001},
923 {0xc78, 0xeb120001}, {0xc78, 0xea130001},
924 {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
925 {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
926 {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
927 {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
928 {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
929 {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
930 {0xc78, 0x65200001}, {0xc78, 0x64210001},
931 {0xc78, 0x63220001}, {0xc78, 0x4a230001},
932 {0xc78, 0x49240001}, {0xc78, 0x48250001},
933 {0xc78, 0x47260001}, {0xc78, 0x46270001},
934 {0xc78, 0x45280001}, {0xc78, 0x44290001},
935 {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
936 {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
937 {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
938 {0xc78, 0x0a300001}, {0xc78, 0x09310001},
939 {0xc78, 0x08320001}, {0xc78, 0x07330001},
940 {0xc78, 0x06340001}, {0xc78, 0x05350001},
941 {0xc78, 0x04360001}, {0xc78, 0x03370001},
942 {0xc78, 0x02380001}, {0xc78, 0x01390001},
943 {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
944 {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
945 {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
946 {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
947 {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
948 {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
949 {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
950 {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
951 {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
952 {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
953 {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
954 {0xc78, 0xec500001}, {0xc78, 0xeb510001},
955 {0xc78, 0xea520001}, {0xc78, 0xe9530001},
956 {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
957 {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
958 {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
959 {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
960 {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
961 {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
962 {0xc78, 0x65600001}, {0xc78, 0x64610001},
963 {0xc78, 0x63620001}, {0xc78, 0x62630001},
964 {0xc78, 0x61640001}, {0xc78, 0x48650001},
965 {0xc78, 0x47660001}, {0xc78, 0x46670001},
966 {0xc78, 0x45680001}, {0xc78, 0x44690001},
967 {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
968 {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
969 {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
970 {0xc78, 0x24700001}, {0xc78, 0x09710001},
971 {0xc78, 0x08720001}, {0xc78, 0x07730001},
972 {0xc78, 0x06740001}, {0xc78, 0x05750001},
973 {0xc78, 0x04760001}, {0xc78, 0x03770001},
974 {0xc78, 0x02780001}, {0xc78, 0x01790001},
975 {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
976 {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
977 {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
978 {0xc50, 0x69553422},
979 {0xc50, 0x69553420},
980 {0x824, 0x00390204},
981 {0xffff, 0xffffffff}
982};
983
e293278d
JS		 984static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
985 {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
986 {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
987 {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
988 {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
989 {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
990 {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
991 {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
992 {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
993 {0xc78, 0xf0100001}, {0xc78, 0xef110001},
994 {0xc78, 0xee120001}, {0xc78, 0xed130001},
995 {0xc78, 0xec140001}, {0xc78, 0xeb150001},
996 {0xc78, 0xea160001}, {0xc78, 0xe9170001},
997 {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
998 {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
999 {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
1000 {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
1001 {0xc78, 0x04200001}, {0xc78, 0x03210001},
1002 {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
1003 {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
1004 {0xc78, 0xa6260001}, {0xc78, 0x85270001},
1005 {0xc78, 0x84280001}, {0xc78, 0x83290001},
1006 {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
1007 {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
1008 {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
1009 {0xc78, 0x65300001}, {0xc78, 0x64310001},
1010 {0xc78, 0x63320001}, {0xc78, 0x62330001},
1011 {0xc78, 0x61340001}, {0xc78, 0x45350001},
1012 {0xc78, 0x44360001}, {0xc78, 0x43370001},
1013 {0xc78, 0x42380001}, {0xc78, 0x41390001},
1014 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
1015 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
1016 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
1017 {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
1018 {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
1019 {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
1020 {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
1021 {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
1022 {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
1023 {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
1024 {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
1025 {0xc78, 0xf0500001}, {0xc78, 0xef510001},
1026 {0xc78, 0xee520001}, {0xc78, 0xed530001},
1027 {0xc78, 0xec540001}, {0xc78, 0xeb550001},
1028 {0xc78, 0xea560001}, {0xc78, 0xe9570001},
1029 {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
1030 {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
1031 {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
1032 {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
1033 {0xc78, 0x8a600001}, {0xc78, 0x89610001},
1034 {0xc78, 0x88620001}, {0xc78, 0x87630001},
1035 {0xc78, 0x86640001}, {0xc78, 0x85650001},
1036 {0xc78, 0x84660001}, {0xc78, 0x83670001},
1037 {0xc78, 0x82680001}, {0xc78, 0x6b690001},
1038 {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
1039 {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
1040 {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
1041 {0xc78, 0x64700001}, {0xc78, 0x63710001},
1042 {0xc78, 0x62720001}, {0xc78, 0x61730001},
1043 {0xc78, 0x49740001}, {0xc78, 0x48750001},
1044 {0xc78, 0x47760001}, {0xc78, 0x46770001},
1045 {0xc78, 0x45780001}, {0xc78, 0x44790001},
1046 {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
1047 {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
1048 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
1049 {0xc50, 0x00040022}, {0xc50, 0x00040020},
1050 {0xffff, 0xffffffff}
1051};
1052
1053static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
1054 {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
1055 {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
1056 {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
1057 {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
1058 {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
1059 {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
1060 {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
1061 {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
1062 {0xc78, 0xea100001}, {0xc78, 0xe9110001},
1063 {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
1064 {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
1065 {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
1066 {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
1067 {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
1068 {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
1069 {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
1070 {0xc78, 0x84200001}, {0xc78, 0x83210001},
1071 {0xc78, 0x82220001}, {0xc78, 0x6a230001},
1072 {0xc78, 0x69240001}, {0xc78, 0x68250001},
1073 {0xc78, 0x67260001}, {0xc78, 0x66270001},
1074 {0xc78, 0x65280001}, {0xc78, 0x64290001},
1075 {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
1076 {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
1077 {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
1078 {0xc78, 0x45300001}, {0xc78, 0x44310001},
1079 {0xc78, 0x43320001}, {0xc78, 0x42330001},
1080 {0xc78, 0x41340001}, {0xc78, 0x40350001},
1081 {0xc78, 0x40360001}, {0xc78, 0x40370001},
1082 {0xc78, 0x40380001}, {0xc78, 0x40390001},
1083 {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
1084 {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
1085 {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
1086 {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
1087 {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
1088 {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
1089 {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
1090 {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
1091 {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
1092 {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
1093 {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
1094 {0xc78, 0xea500001}, {0xc78, 0xe9510001},
1095 {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
1096 {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
1097 {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
1098 {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
1099 {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
1100 {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
1101 {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
1102 {0xc78, 0x84600001}, {0xc78, 0x83610001},
1103 {0xc78, 0x82620001}, {0xc78, 0x6a630001},
1104 {0xc78, 0x69640001}, {0xc78, 0x68650001},
1105 {0xc78, 0x67660001}, {0xc78, 0x66670001},
1106 {0xc78, 0x65680001}, {0xc78, 0x64690001},
1107 {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
1108 {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
1109 {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
1110 {0xc78, 0x45700001}, {0xc78, 0x44710001},
1111 {0xc78, 0x43720001}, {0xc78, 0x42730001},
1112 {0xc78, 0x41740001}, {0xc78, 0x40750001},
1113 {0xc78, 0x40760001}, {0xc78, 0x40770001},
1114 {0xc78, 0x40780001}, {0xc78, 0x40790001},
1115 {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
1116 {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
1117 {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
1118 {0xc50, 0x00040222}, {0xc50, 0x00040220},
1119 {0xffff, 0xffffffff}
1120};
1121
26f1fad2
JS		 1122static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
1123 {0x00, 0x00030159}, {0x01, 0x00031284},
1124 {0x02, 0x00098000}, {0x03, 0x00039c63},
1125 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1126 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
1127 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
1128 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1129 {0x19, 0x00000000}, {0x1a, 0x00030355},
1130 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1131 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
1132 {0x1f, 0x00000000}, {0x20, 0x0000b614},
1133 {0x21, 0x0006c000}, {0x22, 0x00000000},
1134 {0x23, 0x00001558}, {0x24, 0x00000060},
1135 {0x25, 0x00000483}, {0x26, 0x0004f000},
1136 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
1137 {0x29, 0x00004783}, {0x2a, 0x00000001},
1138 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1139 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1140 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1141 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1142 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1143 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1144 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1145 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1146 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1147 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1148 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1149 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1150 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1151 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1152 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1153 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1154 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1155 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1156 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1157 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1158 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1159 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1160 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1161 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1162 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1163 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1164 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1165 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1166 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1167 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1168 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1169 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1170 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1171 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1172 {0x10, 0x00000000}, {0x11, 0x00000000},
1173 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1174 {0x10, 0x0009000f}, {0x11, 0x00023100},
1175 {0x12, 0x00032000}, {0x12, 0x00071000},
1176 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1177 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1178 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1179 {0x13, 0x00018493}, {0x13, 0x0001429b},
1180 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1181 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1182 {0x13, 0x00000020}, {0x14, 0x0001944c},
1183 {0x14, 0x00059444}, {0x14, 0x0009944c},
1184 {0x14, 0x000d9444}, {0x15, 0x0000f474},
1185 {0x15, 0x0004f477}, {0x15, 0x0008f455},
1186 {0x15, 0x000cf455}, {0x16, 0x00000339},
1187 {0x16, 0x00040339}, {0x16, 0x00080339},
1188 {0x16, 0x000c0366}, {0x00, 0x00010159},
1189 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1190 {0xfe, 0x00000000}, {0x1f, 0x00000003},
1191 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1192 {0x1e, 0x00000247}, {0x1f, 0x00000000},
1193 {0x00, 0x00030159},
1194 {0xff, 0xffffffff}
1195};
1196
22a31d45
JS		 1197static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
1198 {0x00, 0x00010000}, {0xb0, 0x000dffe0},
1199 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1200 {0xfe, 0x00000000}, {0xb1, 0x00000018},
1201 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1202 {0xfe, 0x00000000}, {0xb2, 0x00084c00},
1203 {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
1204 {0xb7, 0x00000010}, {0xb8, 0x0000907f},
1205 {0x5c, 0x00000002}, {0x7c, 0x00000002},
1206 {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
1207 {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
1208 {0x1e, 0x00000000}, {0xdf, 0x00000780},
1209 {0x50, 0x00067435},
1210 /*
1211 * The 8723bu vendor driver indicates that bit 8 should be set in
1212 * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
1213 * they never actually check the package type - and just default
1214 * to not setting it.
1215 */
1216 {0x51, 0x0006b04e},
1217 {0x52, 0x000007d2}, {0x53, 0x00000000},
1218 {0x54, 0x00050400}, {0x55, 0x0004026e},
1219 {0xdd, 0x0000004c}, {0x70, 0x00067435},
1220 /*
1221 * 0x71 has same package type condition as for register 0x51
1222 */
1223 {0x71, 0x0006b04e},
1224 {0x72, 0x000007d2}, {0x73, 0x00000000},
1225 {0x74, 0x00050400}, {0x75, 0x0004026e},
1226 {0xef, 0x00000100}, {0x34, 0x0000add7},
1227 {0x35, 0x00005c00}, {0x34, 0x00009dd4},
1228 {0x35, 0x00005000}, {0x34, 0x00008dd1},
1229 {0x35, 0x00004400}, {0x34, 0x00007dce},
1230 {0x35, 0x00003800}, {0x34, 0x00006cd1},
1231 {0x35, 0x00004400}, {0x34, 0x00005cce},
1232 {0x35, 0x00003800}, {0x34, 0x000048ce},
1233 {0x35, 0x00004400}, {0x34, 0x000034ce},
1234 {0x35, 0x00003800}, {0x34, 0x00002451},
1235 {0x35, 0x00004400}, {0x34, 0x0000144e},
1236 {0x35, 0x00003800}, {0x34, 0x00000051},
1237 {0x35, 0x00004400}, {0xef, 0x00000000},
1238 {0xef, 0x00000100}, {0xed, 0x00000010},
1239 {0x44, 0x0000add7}, {0x44, 0x00009dd4},
1240 {0x44, 0x00008dd1}, {0x44, 0x00007dce},
1241 {0x44, 0x00006cc1}, {0x44, 0x00005cce},
1242 {0x44, 0x000044d1}, {0x44, 0x000034ce},
1243 {0x44, 0x00002451}, {0x44, 0x0000144e},
1244 {0x44, 0x00000051}, {0xef, 0x00000000},
1245 {0xed, 0x00000000}, {0x7f, 0x00020080},
1246 {0xef, 0x00002000}, {0x3b, 0x000380ef},
1247 {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
1248 {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
1249 {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
1250 {0x3b, 0x00000900}, {0xef, 0x00000000},
1251 {0xed, 0x00000001}, {0x40, 0x000380ef},
1252 {0x40, 0x000302fe}, {0x40, 0x00028ce6},
1253 {0x40, 0x000200bc}, {0x40, 0x000188a5},
1254 {0x40, 0x00010fbc}, {0x40, 0x00008f71},
1255 {0x40, 0x00000900}, {0xed, 0x00000000},
1256 {0x82, 0x00080000}, {0x83, 0x00008000},
1257 {0x84, 0x00048d80}, {0x85, 0x00068000},
1258 {0xa2, 0x00080000}, {0xa3, 0x00008000},
1259 {0xa4, 0x00048d80}, {0xa5, 0x00068000},
1260 {0xed, 0x00000002}, {0xef, 0x00000002},
1261 {0x56, 0x00000032}, {0x76, 0x00000032},
1262 {0x01, 0x00000780},
1263 {0xff, 0xffffffff}
1264};
1265
26f1fad2
JS		 1266static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
1267 {0x00, 0x00030159}, {0x01, 0x00031284},
1268 {0x02, 0x00098000}, {0x03, 0x00018c63},
1269 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1270 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1271 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1272 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1273 {0x19, 0x00000000}, {0x1a, 0x00010255},
1274 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1275 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1276 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1277 {0x21, 0x0006c000}, {0x22, 0x00000000},
1278 {0x23, 0x00001558}, {0x24, 0x00000060},
1279 {0x25, 0x00000483}, {0x26, 0x0004f000},
1280 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1281 {0x29, 0x00004783}, {0x2a, 0x00000001},
1282 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1283 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1284 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1285 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1286 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1287 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1288 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1289 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1290 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1291 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1292 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1293 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1294 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1295 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1296 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1297 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1298 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1299 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1300 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1301 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1302 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1303 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1304 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1305 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1306 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1307 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1308 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1309 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1310 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1311 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1312 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1313 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1314 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1315 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1316 {0x10, 0x00000000}, {0x11, 0x00000000},
1317 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1318 {0x10, 0x0009000f}, {0x11, 0x00023100},
1319 {0x12, 0x00032000}, {0x12, 0x00071000},
1320 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1321 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1322 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1323 {0x13, 0x00018493}, {0x13, 0x0001429b},
1324 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1325 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1326 {0x13, 0x00000020}, {0x14, 0x0001944c},
1327 {0x14, 0x00059444}, {0x14, 0x0009944c},
1328 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1329 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1330 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1331 {0x16, 0x000a0330}, {0x16, 0x00060330},
1332 {0x16, 0x00020330}, {0x00, 0x00010159},
1333 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1334 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1335 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1336 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1337 {0x00, 0x00030159},
1338 {0xff, 0xffffffff}
1339};
1340
1341static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
1342 {0x00, 0x00030159}, {0x01, 0x00031284},
1343 {0x02, 0x00098000}, {0x03, 0x00018c63},
1344 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1345 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1346 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1347 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1348 {0x12, 0x00032000}, {0x12, 0x00071000},
1349 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1350 {0x13, 0x000287af}, {0x13, 0x000244b7},
1351 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1352 {0x13, 0x00018493}, {0x13, 0x00014297},
1353 {0x13, 0x00010295}, {0x13, 0x0000c298},
1354 {0x13, 0x0000819c}, {0x13, 0x000040a8},
1355 {0x13, 0x0000001c}, {0x14, 0x0001944c},
1356 {0x14, 0x00059444}, {0x14, 0x0009944c},
1357 {0x14, 0x000d9444}, {0x15, 0x0000f424},
1358 {0x15, 0x0004f424}, {0x15, 0x0008f424},
1359 {0x15, 0x000cf424}, {0x16, 0x000e0330},
1360 {0x16, 0x000a0330}, {0x16, 0x00060330},
1361 {0x16, 0x00020330},
1362 {0xff, 0xffffffff}
1363};
1364
1365static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
1366 {0x00, 0x00030159}, {0x01, 0x00031284},
1367 {0x02, 0x00098000}, {0x03, 0x00018c63},
1368 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1369 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
1370 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
1371 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1372 {0x19, 0x00000000}, {0x1a, 0x00010255},
1373 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1374 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1375 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1376 {0x21, 0x0006c000}, {0x22, 0x00000000},
1377 {0x23, 0x00001558}, {0x24, 0x00000060},
1378 {0x25, 0x00000483}, {0x26, 0x0004f000},
1379 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
1380 {0x29, 0x00004783}, {0x2a, 0x00000001},
1381 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1382 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1383 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1384 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1385 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1386 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1387 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1388 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1389 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1390 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1391 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1392 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1393 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1394 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1395 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1396 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1397 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1398 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1399 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1400 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1401 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1402 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1403 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1404 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1405 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1406 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1407 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1408 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1409 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1410 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1411 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1412 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1413 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1414 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1415 {0x10, 0x00000000}, {0x11, 0x00000000},
1416 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1417 {0x10, 0x0009000f}, {0x11, 0x00023100},
1418 {0x12, 0x00032000}, {0x12, 0x00071000},
1419 {0x12, 0x000b0000}, {0x12, 0x000fc000},
1420 {0x13, 0x000287b3}, {0x13, 0x000244b7},
1421 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
1422 {0x13, 0x00018493}, {0x13, 0x0001429b},
1423 {0x13, 0x00010299}, {0x13, 0x0000c29c},
1424 {0x13, 0x000081a0}, {0x13, 0x000040ac},
1425 {0x13, 0x00000020}, {0x14, 0x0001944c},
1426 {0x14, 0x00059444}, {0x14, 0x0009944c},
1427 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1428 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1429 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1430 {0x16, 0x000a0330}, {0x16, 0x00060330},
1431 {0x16, 0x00020330}, {0x00, 0x00010159},
1432 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1433 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1434 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1435 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1436 {0x00, 0x00030159},
1437 {0xff, 0xffffffff}
1438};
1439
1440static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
1441 {0x00, 0x00030159}, {0x01, 0x00031284},
1442 {0x02, 0x00098000}, {0x03, 0x00018c63},
1443 {0x04, 0x000210e7}, {0x09, 0x0002044f},
1444 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
1445 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
1446 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
1447 {0x19, 0x00000000}, {0x1a, 0x00000255},
1448 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
1449 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
1450 {0x1f, 0x00080001}, {0x20, 0x0000b614},
1451 {0x21, 0x0006c000}, {0x22, 0x0000083c},
1452 {0x23, 0x00001558}, {0x24, 0x00000060},
1453 {0x25, 0x00000483}, {0x26, 0x0004f000},
1454 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
1455 {0x29, 0x00004783}, {0x2a, 0x00000001},
1456 {0x2b, 0x00021334}, {0x2a, 0x00000000},
1457 {0x2b, 0x00000054}, {0x2a, 0x00000001},
1458 {0x2b, 0x00000808}, {0x2b, 0x00053333},
1459 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
1460 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
1461 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
1462 {0x2b, 0x00000808}, {0x2b, 0x00063333},
1463 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
1464 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
1465 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
1466 {0x2b, 0x00000808}, {0x2b, 0x00073333},
1467 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
1468 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
1469 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
1470 {0x2b, 0x00000709}, {0x2b, 0x00063333},
1471 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
1472 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
1473 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
1474 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
1475 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
1476 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
1477 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
1478 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
1479 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
1480 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
1481 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
1482 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
1483 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
1484 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
1485 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
1486 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
1487 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
1488 {0x10, 0x0002000f}, {0x11, 0x000203f9},
1489 {0x10, 0x0003000f}, {0x11, 0x000ff500},
1490 {0x10, 0x00000000}, {0x11, 0x00000000},
1491 {0x10, 0x0008000f}, {0x11, 0x0003f100},
1492 {0x10, 0x0009000f}, {0x11, 0x00023100},
1493 {0x12, 0x000d8000}, {0x12, 0x00090000},
1494 {0x12, 0x00051000}, {0x12, 0x00012000},
1495 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
1496 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
1497 {0x13, 0x000183a4}, {0x13, 0x00014398},
1498 {0x13, 0x000101a4}, {0x13, 0x0000c198},
1499 {0x13, 0x000080a4}, {0x13, 0x00004098},
1500 {0x13, 0x00000000}, {0x14, 0x0001944c},
1501 {0x14, 0x00059444}, {0x14, 0x0009944c},
1502 {0x14, 0x000d9444}, {0x15, 0x0000f405},
1503 {0x15, 0x0004f405}, {0x15, 0x0008f405},
1504 {0x15, 0x000cf405}, {0x16, 0x000e0330},
1505 {0x16, 0x000a0330}, {0x16, 0x00060330},
1506 {0x16, 0x00020330}, {0x00, 0x00010159},
1507 {0x18, 0x0000f401}, {0xfe, 0x00000000},
1508 {0xfe, 0x00000000}, {0x1f, 0x00080003},
1509 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1510 {0x1e, 0x00044457}, {0x1f, 0x00080000},
1511 {0x00, 0x00030159},
1512 {0xff, 0xffffffff}
1513};
1514
19102f84
JS		 1515static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
1516 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1517 {0x00, 0x00030000}, {0x08, 0x00008400},
1518 {0x18, 0x00000407}, {0x19, 0x00000012},
1519 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1520 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1521 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1522 {0x57, 0x000d0000}, {0x58, 0x000be180},
1523 {0x67, 0x00001552}, {0x83, 0x00000000},
1524 {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
1525 {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
1526 {0xb5, 0x00008166}, {0xb6, 0x0000803e},
1527 {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
1528 {0xb9, 0x00080001}, {0xba, 0x00040001},
1529 {0xbb, 0x00000400}, {0xbf, 0x000c0000},
1530 {0xc2, 0x00002400}, {0xc3, 0x00000009},
1531 {0xc4, 0x00040c91}, {0xc5, 0x00099999},
1532 {0xc6, 0x000000a3}, {0xc7, 0x00088820},
1533 {0xc8, 0x00076c06}, {0xc9, 0x00000000},
1534 {0xca, 0x00080000}, {0xdf, 0x00000180},
1535 {0xef, 0x000001a0}, {0x51, 0x00069545},
1536 {0x52, 0x0007e45e}, {0x53, 0x00000071},
1537 {0x56, 0x00051ff3}, {0x35, 0x000000a8},
1538 {0x35, 0x000001e2}, {0x35, 0x000002a8},
1539 {0x36, 0x00001c24}, {0x36, 0x00009c24},
1540 {0x36, 0x00011c24}, {0x36, 0x00019c24},
1541 {0x18, 0x00000c07}, {0x5a, 0x00048000},
1542 {0x19, 0x000739d0},
1543#ifdef EXT_PA_8192EU
1544 /* External PA or external LNA */
1545 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1546 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1547 {0x34, 0x0000604a}, {0x34, 0x00005047},
1548 {0x34, 0x0000400a}, {0x34, 0x00003007},
1549 {0x34, 0x00002004}, {0x34, 0x00001001},
1550 {0x34, 0x00000000},
1551#else
1552 /* Regular */
1553 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1554 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1555 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1556 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1557 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1558 {0x34, 0x00000014},
1559#endif
1560 {0x00, 0x00030159},
1561 {0x84, 0x00068180},
1562 {0x86, 0x0000014e},
1563 {0x87, 0x00048e00},
1564 {0x8e, 0x00065540},
1565 {0x8f, 0x00088000},
1566 {0xef, 0x000020a0},
1567#ifdef EXT_PA_8192EU
1568 /* External PA or external LNA */
1569 {0x3b, 0x000f07b0},
1570#else
1571 {0x3b, 0x000f02b0},
1572#endif
1573 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1574 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1575 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1576 {0x3b, 0x0008f780},
1577#ifdef EXT_PA_8192EU
1578 /* External PA or external LNA */
1579 {0x3b, 0x000787b0},
1580#else
1581 {0x3b, 0x00078730},
1582#endif
1583 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1584 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1585 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1586 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1587 {0xfe, 0x00000000}, {0x18, 0x0000fc07},
1588 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1589 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1590 {0x1e, 0x00000001}, {0x1f, 0x00080000},
1591 {0x00, 0x00033e70},
1592 {0xff, 0xffffffff}
1593};
1594
1595static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
1596 {0x7f, 0x00000082}, {0x81, 0x0003fc00},
1597 {0x00, 0x00030000}, {0x08, 0x00008400},
1598 {0x18, 0x00000407}, {0x19, 0x00000012},
1599 {0x1b, 0x00000064}, {0x1e, 0x00080009},
1600 {0x1f, 0x00000880}, {0x2f, 0x0001a060},
1601 {0x3f, 0x00000000}, {0x42, 0x000060c0},
1602 {0x57, 0x000d0000}, {0x58, 0x000be180},
1603 {0x67, 0x00001552}, {0x7f, 0x00000082},
1604 {0x81, 0x0003f000}, {0x83, 0x00000000},
1605 {0xdf, 0x00000180}, {0xef, 0x000001a0},
1606 {0x51, 0x00069545}, {0x52, 0x0007e42e},
1607 {0x53, 0x00000071}, {0x56, 0x00051ff3},
1608 {0x35, 0x000000a8}, {0x35, 0x000001e0},
1609 {0x35, 0x000002a8}, {0x36, 0x00001ca8},
1610 {0x36, 0x00009c24}, {0x36, 0x00011c24},
1611 {0x36, 0x00019c24}, {0x18, 0x00000c07},
1612 {0x5a, 0x00048000}, {0x19, 0x000739d0},
1613#ifdef EXT_PA_8192EU
1614 /* External PA or external LNA */
1615 {0x34, 0x0000a093}, {0x34, 0x0000908f},
1616 {0x34, 0x0000808c}, {0x34, 0x0000704d},
1617 {0x34, 0x0000604a}, {0x34, 0x00005047},
1618 {0x34, 0x0000400a}, {0x34, 0x00003007},
1619 {0x34, 0x00002004}, {0x34, 0x00001001},
1620 {0x34, 0x00000000},
1621#else
1622 {0x34, 0x0000add7}, {0x34, 0x00009dd4},
1623 {0x34, 0x00008dd1}, {0x34, 0x00007dce},
1624 {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
1625 {0x34, 0x00004dc5}, {0x34, 0x000034cc},
1626 {0x34, 0x0000244f}, {0x34, 0x0000144c},
1627 {0x34, 0x00000014},
1628#endif
1629 {0x00, 0x00030159}, {0x84, 0x00068180},
1630 {0x86, 0x000000ce}, {0x87, 0x00048a00},
1631 {0x8e, 0x00065540}, {0x8f, 0x00088000},
1632 {0xef, 0x000020a0},
1633#ifdef EXT_PA_8192EU
1634 /* External PA or external LNA */
1635 {0x3b, 0x000f07b0},
1636#else
1637 {0x3b, 0x000f02b0},
1638#endif
1639
1640 {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
1641 {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
1642 {0x3b, 0x000a0080}, {0x3b, 0x00090080},
1643 {0x3b, 0x0008f780},
1644#ifdef EXT_PA_8192EU
1645 /* External PA or external LNA */
1646 {0x3b, 0x000787b0},
1647#else
1648 {0x3b, 0x00078730},
1649#endif
1650 {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
1651 {0x3b, 0x00040620}, {0x3b, 0x00037090},
1652 {0x3b, 0x00020080}, {0x3b, 0x0001f060},
1653 {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
1654 {0x00, 0x00010159}, {0xfe, 0x00000000},
1655 {0xfe, 0x00000000}, {0xfe, 0x00000000},
1656 {0xfe, 0x00000000}, {0x1e, 0x00000001},
1657 {0x1f, 0x00080000}, {0x00, 0x00033e70},
1658 {0xff, 0xffffffff}
1659};
1660
26f1fad2
JS		 1661static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
1662 { /* RF_A */
1663 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
1664 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
1665 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
1666 .hspiread = REG_HSPI_XA_READBACK,
1667 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
1668 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
1669 },
1670 { /* RF_B */
1671 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
1672 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
1673 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
1674 .hspiread = REG_HSPI_XB_READBACK,
1675 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
1676 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
1677 },
1678};
1679
1680static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
1681 REG_OFDM0_XA_RX_IQ_IMBALANCE,
1682 REG_OFDM0_XB_RX_IQ_IMBALANCE,
1683 REG_OFDM0_ENERGY_CCA_THRES,
1684 REG_OFDM0_AGCR_SSI_TABLE,
1685 REG_OFDM0_XA_TX_IQ_IMBALANCE,
1686 REG_OFDM0_XB_TX_IQ_IMBALANCE,
1687 REG_OFDM0_XC_TX_AFE,
1688 REG_OFDM0_XD_TX_AFE,
1689 REG_OFDM0_RX_IQ_EXT_ANTA
1690};
1691
1692static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
1693{
1694 struct usb_device *udev = priv->udev;
1695 int len;
1696 u8 data;
1697
1698 mutex_lock(&priv->usb_buf_mutex);
1699 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1700 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1701 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1702 RTW_USB_CONTROL_MSG_TIMEOUT);
1703 data = priv->usb_buf.val8;
1704 mutex_unlock(&priv->usb_buf_mutex);
1705
1706 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1707 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
1708 __func__, addr, data, len);
1709 return data;
1710}
1711
1712static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
1713{
1714 struct usb_device *udev = priv->udev;
1715 int len;
1716 u16 data;
1717
1718 mutex_lock(&priv->usb_buf_mutex);
1719 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1720 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1721 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1722 RTW_USB_CONTROL_MSG_TIMEOUT);
1723 data = le16_to_cpu(priv->usb_buf.val16);
1724 mutex_unlock(&priv->usb_buf_mutex);
1725
1726 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1727 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1728 __func__, addr, data, len);
1729 return data;
1730}
1731
1732static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1733{
1734 struct usb_device *udev = priv->udev;
1735 int len;
1736 u32 data;
1737
1738 mutex_lock(&priv->usb_buf_mutex);
1739 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1740 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1741 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1742 RTW_USB_CONTROL_MSG_TIMEOUT);
1743 data = le32_to_cpu(priv->usb_buf.val32);
1744 mutex_unlock(&priv->usb_buf_mutex);
1745
1746 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1747 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1748 __func__, addr, data, len);
1749 return data;
1750}
1751
1752static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1753{
1754 struct usb_device *udev = priv->udev;
1755 int ret;
1756
1757 mutex_lock(&priv->usb_buf_mutex);
1758 priv->usb_buf.val8 = val;
1759 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1760 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1761 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1762 RTW_USB_CONTROL_MSG_TIMEOUT);
1763
1764 mutex_unlock(&priv->usb_buf_mutex);
1765
1766 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1767 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1768 __func__, addr, val);
1769 return ret;
1770}
1771
1772static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1773{
1774 struct usb_device *udev = priv->udev;
1775 int ret;
1776
1777 mutex_lock(&priv->usb_buf_mutex);
1778 priv->usb_buf.val16 = cpu_to_le16(val);
1779 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1780 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1781 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1782 RTW_USB_CONTROL_MSG_TIMEOUT);
1783 mutex_unlock(&priv->usb_buf_mutex);
1784
1785 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1786 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1787 __func__, addr, val);
1788 return ret;
1789}
1790
1791static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1792{
1793 struct usb_device *udev = priv->udev;
1794 int ret;
1795
1796 mutex_lock(&priv->usb_buf_mutex);
1797 priv->usb_buf.val32 = cpu_to_le32(val);
1798 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1799 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1800 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1801 RTW_USB_CONTROL_MSG_TIMEOUT);
1802 mutex_unlock(&priv->usb_buf_mutex);
1803
1804 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1805 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1806 __func__, addr, val);
1807 return ret;
1808}
1809
1810static int
1811rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1812{
1813 struct usb_device *udev = priv->udev;
1814 int blocksize = priv->fops->writeN_block_size;
1815 int ret, i, count, remainder;
1816
1817 count = len / blocksize;
1818 remainder = len % blocksize;
1819
1820 for (i = 0; i < count; i++) {
1821 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1822 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1823 addr, 0, buf, blocksize,
1824 RTW_USB_CONTROL_MSG_TIMEOUT);
1825 if (ret != blocksize)
1826 goto write_error;
1827
1828 addr += blocksize;
1829 buf += blocksize;
1830 }
1831
1832 if (remainder) {
1833 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1834 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1835 addr, 0, buf, remainder,
1836 RTW_USB_CONTROL_MSG_TIMEOUT);
1837 if (ret != remainder)
1838 goto write_error;
1839 }
1840
1841 return len;
1842
1843write_error:
1844 dev_info(&udev->dev,
1845 "%s: Failed to write block at addr: %04x size: %04x\n",
1846 __func__, addr, blocksize);
1847 return -EAGAIN;
1848}
1849
1850static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1851 enum rtl8xxxu_rfpath path, u8 reg)
1852{
1853 u32 hssia, val32, retval;
1854
1855 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1856 if (path != RF_A)
1857 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1858 else
1859 val32 = hssia;
1860
1861 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1862 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1863 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1864 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1865 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1866
1867 udelay(10);
1868
1869 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1870 udelay(100);
1871
1872 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1873 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1874 udelay(10);
1875
1876 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1877 if (val32 & FPGA0_HSSI_PARM1_PI)
1878 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1879 else
1880 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1881
1882 retval &= 0xfffff;
1883
1884 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1885 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1886 __func__, reg, retval);
1887 return retval;
1888}
1889
22a31d45
JS		 1890/*
1891 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
1892 * have write issues in high temperature conditions. We may have to
1893 * retry writing them.
1894 */
26f1fad2
JS		 1895static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1896 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1897{
1898 int ret, retval;
2949b9ee 1899 u32 dataaddr, val32;
26f1fad2
JS		 1900
1901 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1902 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1903 __func__, reg, data);
1904
1905 data &= FPGA0_LSSI_PARM_DATA_MASK;
1906 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1907
2949b9ee
JS		 1908 if (priv->rtl_chip == RTL8192E) {
1909 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1910 val32 &= ~0x20000;
1911 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1912 }
1913
26f1fad2
JS		 1914 /* Use XB for path B */
1915 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1916 if (ret != sizeof(dataaddr))
1917 retval = -EIO;
1918 else
1919 retval = 0;
1920
1921 udelay(1);
1922
2949b9ee
JS		 1923 if (priv->rtl_chip == RTL8192E) {
1924 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1925 val32 |= 0x20000;
1926 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1927 }
1928
26f1fad2
JS		 1929 return retval;
1930}
1931
8da91571
JS		 1932static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv,
1933 struct h2c_cmd *h2c, int len)
26f1fad2
JS		 1934{
1935 struct device *dev = &priv->udev->dev;
1936 int mbox_nr, retry, retval = 0;
1937 int mbox_reg, mbox_ext_reg;
1938 u8 val8;
1939
1940 mutex_lock(&priv->h2c_mutex);
1941
1942 mbox_nr = priv->next_mbox;
1943 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
ed35d094
JS		 1944 mbox_ext_reg = priv->fops->mbox_ext_reg +
1945 (mbox_nr * priv->fops->mbox_ext_width);
26f1fad2
JS		 1946
1947 /*
1948 * MBOX ready?
1949 */
1950 retry = 100;
1951 do {
1952 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1953 if (!(val8 & BIT(mbox_nr)))
1954 break;
1955 } while (retry--);
1956
1957 if (!retry) {
c7a5a190 1958 dev_info(dev, "%s: Mailbox busy\n", __func__);
26f1fad2
JS		 1959 retval = -EBUSY;
1960 goto error;
1961 }
1962
1963 /*
1964 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1965 */
8da91571 1966 if (len > sizeof(u32)) {
ed35d094
JS		 1967 if (priv->fops->mbox_ext_width == 4) {
1968 rtl8xxxu_write32(priv, mbox_ext_reg,
1969 le32_to_cpu(h2c->raw_wide.ext));
1970 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1971 dev_info(dev, "H2C_EXT %08x\n",
1972 le32_to_cpu(h2c->raw_wide.ext));
1973 } else {
1974 rtl8xxxu_write16(priv, mbox_ext_reg,
1975 le16_to_cpu(h2c->raw.ext));
1976 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1977 dev_info(dev, "H2C_EXT %04x\n",
1978 le16_to_cpu(h2c->raw.ext));
1979 }
26f1fad2
JS		 1980 }
1981 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1982 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1983 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1984
1985 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1986
1987error:
1988 mutex_unlock(&priv->h2c_mutex);
1989 return retval;
1990}
1991
394f1bd3
JS		 1992static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
1993{
1994 struct h2c_cmd h2c;
1995 int reqnum = 0;
1996
1997 memset(&h2c, 0, sizeof(struct h2c_cmd));
1998 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
1999 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
2000 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
2001 h2c.bt_mp_oper.data = data;
2002 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
2003
2004 reqnum++;
2005 memset(&h2c, 0, sizeof(struct h2c_cmd));
2006 h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
2007 h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
2008 h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
2009 h2c.bt_mp_oper.addr = reg;
2010 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
2011}
2012
26f1fad2
JS		 2013static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
2014{
2015 u8 val8;
2016 u32 val32;
2017
2018 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
2019 val8 |= BIT(0) | BIT(3);
2020 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
2021
2022 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
2023 val32 &= ~(BIT(4) | BIT(5));
2024 val32 |= BIT(3);
2025 if (priv->rf_paths == 2) {
2026 val32 &= ~(BIT(20) | BIT(21));
2027 val32 |= BIT(19);
2028 }
2029 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
2030
2031 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2032 val32 &= ~OFDM_RF_PATH_TX_MASK;
2033 if (priv->tx_paths == 2)
2034 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
ba17d824 2035 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
26f1fad2
JS		 2036 val32 |= OFDM_RF_PATH_TX_B;
2037 else
2038 val32 |= OFDM_RF_PATH_TX_A;
2039 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2040
2041 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2042 val32 &= ~FPGA_RF_MODE_JAPAN;
2043 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2044
2045 if (priv->rf_paths == 2)
2046 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
2047 else
2048 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
2049
2050 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
2051 if (priv->rf_paths == 2)
2052 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
2053
2054 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
2055}
2056
2057static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
2058{
2059 u8 sps0;
2060 u32 val32;
2061
2062 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
2063
2064 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
2065
2066 /* RF RX code for preamble power saving */
2067 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
2068 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
2069 if (priv->rf_paths == 2)
2070 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
2071 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
2072
2073 /* Disable TX for four paths */
2074 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2075 val32 &= ~OFDM_RF_PATH_TX_MASK;
2076 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2077
2078 /* Enable power saving */
2079 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2080 val32 |= FPGA_RF_MODE_JAPAN;
2081 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2082
2083 /* AFE control register to power down bits [30:22] */
2084 if (priv->rf_paths == 2)
2085 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
2086 else
2087 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
2088
2089 /* Power down RF module */
2090 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
2091 if (priv->rf_paths == 2)
2092 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
2093
2094 sps0 &= ~(BIT(0) | BIT(3));
2095 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
2096}
2097
2098
2099static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
2100{
2101 u8 val8;
2102
2103 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
2104 val8 &= ~BIT(6);
2105 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
2106
2107 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
2108 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
2109 val8 &= ~BIT(0);
2110 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
2111}
2112
2113
2114/*
2115 * The rtl8723a has 3 channel groups for it's efuse settings. It only
2116 * supports the 2.4GHz band, so channels 1 - 14:
2117 * group 0: channels 1 - 3
2118 * group 1: channels 4 - 9
2119 * group 2: channels 10 - 14
2120 *
2121 * Note: We index from 0 in the code
2122 */
2123static int rtl8723a_channel_to_group(int channel)
2124{
2125 int group;
2126
2127 if (channel < 4)
2128 group = 0;
2129 else if (channel < 10)
2130 group = 1;
2131 else
2132 group = 2;
2133
2134 return group;
2135}
2136
9e24772a
JS		 2137/*
2138 * Valid for rtl8723bu and rtl8192eu
2139 */
e796dab4
JS		 2140static int rtl8723b_channel_to_group(int channel)
2141{
2142 int group;
2143
2144 if (channel < 3)
2145 group = 0;
2146 else if (channel < 6)
2147 group = 1;
2148 else if (channel < 9)
2149 group = 2;
2150 else if (channel < 12)
2151 group = 3;
2152 else
2153 group = 4;
2154
2155 return group;
2156}
2157
26f1fad2
JS		 2158static void rtl8723au_config_channel(struct ieee80211_hw *hw)
2159{
2160 struct rtl8xxxu_priv *priv = hw->priv;
2161 u32 val32, rsr;
2162 u8 val8, opmode;
2163 bool ht = true;
2164 int sec_ch_above, channel;
2165 int i;
2166
2167 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
2168 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
2169 channel = hw->conf.chandef.chan->hw_value;
2170
2171 switch (hw->conf.chandef.width) {
2172 case NL80211_CHAN_WIDTH_20_NOHT:
2173 ht = false;
2174 case NL80211_CHAN_WIDTH_20:
2175 opmode |= BW_OPMODE_20MHZ;
2176 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
2177
2178 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2179 val32 &= ~FPGA_RF_MODE;
2180 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2181
2182 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2183 val32 &= ~FPGA_RF_MODE;
2184 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2185
2186 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
2187 val32 |= FPGA0_ANALOG2_20MHZ;
2188 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
2189 break;
2190 case NL80211_CHAN_WIDTH_40:
2191 if (hw->conf.chandef.center_freq1 >
2192 hw->conf.chandef.chan->center_freq) {
2193 sec_ch_above = 1;
2194 channel += 2;
2195 } else {
2196 sec_ch_above = 0;
2197 channel -= 2;
2198 }
2199
2200 opmode &= ~BW_OPMODE_20MHZ;
2201 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
2202 rsr &= ~RSR_RSC_BANDWIDTH_40M;
2203 if (sec_ch_above)
2204 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
2205 else
2206 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
2207 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
2208
2209 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2210 val32 |= FPGA_RF_MODE;
2211 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2212
2213 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2214 val32 |= FPGA_RF_MODE;
2215 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2216
2217 /*
2218 * Set Control channel to upper or lower. These settings
2219 * are required only for 40MHz
2220 */
2221 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
2222 val32 &= ~CCK0_SIDEBAND;
2223 if (!sec_ch_above)
2224 val32 |= CCK0_SIDEBAND;
2225 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
2226
2227 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
2228 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
2229 if (sec_ch_above)
2230 val32 |= OFDM_LSTF_PRIME_CH_LOW;
2231 else
2232 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
2233 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
2234
2235 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
2236 val32 &= ~FPGA0_ANALOG2_20MHZ;
2237 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
2238
2239 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
2240 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
2241 if (sec_ch_above)
2242 val32 |= FPGA0_PS_UPPER_CHANNEL;
2243 else
2244 val32 |= FPGA0_PS_LOWER_CHANNEL;
2245 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
2246 break;
2247
2248 default:
2249 break;
2250 }
2251
2252 for (i = RF_A; i < priv->rf_paths; i++) {
2253 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2254 val32 &= ~MODE_AG_CHANNEL_MASK;
2255 val32 |= channel;
2256 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2257 }
2258
2259 if (ht)
2260 val8 = 0x0e;
2261 else
2262 val8 = 0x0a;
2263
2264 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
2265 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
2266
2267 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
2268 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
2269
2270 for (i = RF_A; i < priv->rf_paths; i++) {
2271 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2272 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
2273 val32 &= ~MODE_AG_CHANNEL_20MHZ;
2274 else
2275 val32 |= MODE_AG_CHANNEL_20MHZ;
2276 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2277 }
2278}
2279
c3f9506f
JS		 2280static void rtl8723bu_config_channel(struct ieee80211_hw *hw)
2281{
2282 struct rtl8xxxu_priv *priv = hw->priv;
2283 u32 val32, rsr;
368633ce 2284 u8 val8, subchannel;
c3f9506f
JS		 2285 u16 rf_mode_bw;
2286 bool ht = true;
2287 int sec_ch_above, channel;
2288 int i;
2289
2290 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
2291 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
2292 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
2293 channel = hw->conf.chandef.chan->hw_value;
2294
2295/* Hack */
2296 subchannel = 0;
2297
2298 switch (hw->conf.chandef.width) {
2299 case NL80211_CHAN_WIDTH_20_NOHT:
2300 ht = false;
2301 case NL80211_CHAN_WIDTH_20:
2302 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
2303 subchannel = 0;
2304
2305 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2306 val32 &= ~FPGA_RF_MODE;
2307 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2308
2309 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2310 val32 &= ~FPGA_RF_MODE;
2311 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2312
2313 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
2314 val32 &= ~(BIT(30) | BIT(31));
2315 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
2316
2317 break;
2318 case NL80211_CHAN_WIDTH_40:
2319 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
2320
2321 if (hw->conf.chandef.center_freq1 >
2322 hw->conf.chandef.chan->center_freq) {
2323 sec_ch_above = 1;
2324 channel += 2;
2325 } else {
2326 sec_ch_above = 0;
2327 channel -= 2;
2328 }
2329
2330 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
2331 val32 |= FPGA_RF_MODE;
2332 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
2333
2334 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
2335 val32 |= FPGA_RF_MODE;
2336 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
2337
2338 /*
2339 * Set Control channel to upper or lower. These settings
2340 * are required only for 40MHz
2341 */
2342 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
2343 val32 &= ~CCK0_SIDEBAND;
2344 if (!sec_ch_above)
2345 val32 |= CCK0_SIDEBAND;
2346 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
2347
2348 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
2349 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
2350 if (sec_ch_above)
2351 val32 |= OFDM_LSTF_PRIME_CH_LOW;
2352 else
2353 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
2354 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
2355
2356 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
2357 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
2358 if (sec_ch_above)
2359 val32 |= FPGA0_PS_UPPER_CHANNEL;
2360 else
2361 val32 |= FPGA0_PS_LOWER_CHANNEL;
2362 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
2363 break;
2364 case NL80211_CHAN_WIDTH_80:
2365 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
2366 break;
2367 default:
2368 break;
2369 }
2370
2371 for (i = RF_A; i < priv->rf_paths; i++) {
2372 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2373 val32 &= ~MODE_AG_CHANNEL_MASK;
2374 val32 |= channel;
2375 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2376 }
2377
2378 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
2379 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
2380
2381 if (ht)
2382 val8 = 0x0e;
2383 else
2384 val8 = 0x0a;
2385
2386 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
2387 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
2388
2389 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
2390 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
2391
2392 for (i = RF_A; i < priv->rf_paths; i++) {
2393 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
2394 val32 &= ~MODE_AG_BW_MASK;
2395 switch(hw->conf.chandef.width) {
2396 case NL80211_CHAN_WIDTH_80:
2397 val32 |= MODE_AG_BW_80MHZ_8723B;
2398 break;
2399 case NL80211_CHAN_WIDTH_40:
2400 val32 |= MODE_AG_BW_40MHZ_8723B;
2401 break;
2402 default:
2403 val32 |= MODE_AG_BW_20MHZ_8723B;
2404 break;
2405 }
2406 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
2407 }
2408}
2409
26f1fad2
JS		 2410static void
2411rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2412{
2413 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
2414 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
2415 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
2416 u8 val8;
2417 int group, i;
2418
2419 group = rtl8723a_channel_to_group(channel);
2420
2421 cck[0] = priv->cck_tx_power_index_A[group];
2422 cck[1] = priv->cck_tx_power_index_B[group];
2423
b591e982
JS		 2424 if (priv->hi_pa) {
2425 if (cck[0] > 0x20)
2426 cck[0] = 0x20;
2427 if (cck[1] > 0x20)
2428 cck[1] = 0x20;
2429 }
2430
26f1fad2
JS		 2431 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
2432 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
2433
2434 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
2435 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
2436
2437 mcsbase[0] = ofdm[0];
2438 mcsbase[1] = ofdm[1];
2439 if (!ht40) {
2440 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
2441 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
2442 }
2443
2444 if (priv->tx_paths > 1) {
2445 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
2446 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
2447 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
2448 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
2449 }
2450
2451 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
2452 dev_info(&priv->udev->dev,
2453 "%s: Setting TX power CCK A: %02x, "
2454 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
2455 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
2456
2457 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
2458 if (cck[i] > RF6052_MAX_TX_PWR)
2459 cck[i] = RF6052_MAX_TX_PWR;
2460 if (ofdm[i] > RF6052_MAX_TX_PWR)
2461 ofdm[i] = RF6052_MAX_TX_PWR;
2462 }
2463
2464 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2465 val32 &= 0xffff00ff;
2466 val32 |= (cck[0] << 8);
2467 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2468
2469 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2470 val32 &= 0xff;
2471 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
2472 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2473
2474 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2475 val32 &= 0xffffff00;
2476 val32 |= cck[1];
2477 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2478
2479 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2480 val32 &= 0xff;
2481 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
2482 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2483
2484 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
2485 ofdmbase[0] << 16 | ofdmbase[0] << 24;
2486 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
2487 ofdmbase[1] << 16 | ofdmbase[1] << 24;
2488 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
2489 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
2490
2491 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
2492 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
2493
2494 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
2495 mcsbase[0] << 16 | mcsbase[0] << 24;
2496 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
2497 mcsbase[1] << 16 | mcsbase[1] << 24;
2498
2499 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
2500 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
2501
2502 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
2503 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
2504
2505 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
2506 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
2507
2508 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
2509 for (i = 0; i < 3; i++) {
2510 if (i != 2)
2511 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
2512 else
2513 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
2514 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
2515 }
2516 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
2517 for (i = 0; i < 3; i++) {
2518 if (i != 2)
2519 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
2520 else
2521 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
2522 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
2523 }
2524}
2525
e796dab4
JS		 2526static void
2527rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2528{
1d3cc44d
JS		 2529 u32 val32, ofdm, mcs;
2530 u8 cck, ofdmbase, mcsbase;
54bed43f 2531 int group, tx_idx;
e796dab4 2532
54bed43f 2533 tx_idx = 0;
e796dab4 2534 group = rtl8723b_channel_to_group(channel);
54bed43f
JS		 2535
2536 cck = priv->cck_tx_power_index_B[group];
2537 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2538 val32 &= 0xffff00ff;
2539 val32 |= (cck << 8);
2540 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2541
2542 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2543 val32 &= 0xff;
2544 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2545 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2546
2547 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2548 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2549 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2550
2551 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2552 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
1d3cc44d
JS		 2553
2554 mcsbase = priv->ht40_1s_tx_power_index_B[group];
2555 if (ht40)
2556 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2557 else
2558 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2559 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2560
2561 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2562 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
e796dab4
JS		 2563}
2564
57e42a21
JS		 2565static void
2566rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
2567{
2568 u32 val32, ofdm, mcs;
2569 u8 cck, ofdmbase, mcsbase;
2570 int group, tx_idx;
2571
2572 tx_idx = 0;
2573 group = rtl8723b_channel_to_group(channel);
2574
2575 cck = priv->cck_tx_power_index_A[group];
2576
2577 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
2578 val32 &= 0xffff00ff;
2579 val32 |= (cck << 8);
2580 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
2581
2582 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2583 val32 &= 0xff;
2584 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2585 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2586
2587 ofdmbase = priv->ht40_1s_tx_power_index_A[group];
2588 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
2589 ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
2590
2591 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
2592 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
2593
2594 mcsbase = priv->ht40_1s_tx_power_index_A[group];
2595 if (ht40)
2596 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
2597 else
2598 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
2599 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2600
2601 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
2602 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
2603 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
2604 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
2605
2606 if (priv->tx_paths > 1) {
2607 cck = priv->cck_tx_power_index_B[group];
2608
2609 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
2610 val32 &= 0xff;
2611 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
2612 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
2613
2614 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
2615 val32 &= 0xffffff00;
2616 val32 |= cck;
2617 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
2618
2619 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
2620 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
2621 ofdm = ofdmbase | ofdmbase << 8 |
2622 ofdmbase << 16 | ofdmbase << 24;
2623
2624 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm);
2625 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm);
2626
2627 mcsbase = priv->ht40_1s_tx_power_index_B[group];
2628 if (ht40)
2629 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
2630 else
2631 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
2632 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
2633
2634 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs);
2635 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs);
2636 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs);
2637 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs);
2638 }
2639}
2640
26f1fad2
JS		 2641static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
2642 enum nl80211_iftype linktype)
2643{
a26703f3 2644 u8 val8;
26f1fad2 2645
a26703f3 2646 val8 = rtl8xxxu_read8(priv, REG_MSR);
26f1fad2
JS		 2647 val8 &= ~MSR_LINKTYPE_MASK;
2648
2649 switch (linktype) {
2650 case NL80211_IFTYPE_UNSPECIFIED:
2651 val8 |= MSR_LINKTYPE_NONE;
2652 break;
2653 case NL80211_IFTYPE_ADHOC:
2654 val8 |= MSR_LINKTYPE_ADHOC;
2655 break;
2656 case NL80211_IFTYPE_STATION:
2657 val8 |= MSR_LINKTYPE_STATION;
2658 break;
2659 case NL80211_IFTYPE_AP:
2660 val8 |= MSR_LINKTYPE_AP;
2661 break;
2662 default:
2663 goto out;
2664 }
2665
2666 rtl8xxxu_write8(priv, REG_MSR, val8);
2667out:
2668 return;
2669}
2670
2671static void
2672rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
2673{
2674 u16 val16;
2675
2676 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
2677 RETRY_LIMIT_SHORT_MASK) |
2678 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
2679 RETRY_LIMIT_LONG_MASK);
2680
2681 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
2682}
2683
2684static void
2685rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
2686{
2687 u16 val16;
2688
2689 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
2690 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
2691
2692 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
2693}
2694
2695static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
2696{
2697 struct device *dev = &priv->udev->dev;
2698 char *cut;
2699
2700 switch (priv->chip_cut) {
2701 case 0:
2702 cut = "A";
2703 break;
2704 case 1:
2705 cut = "B";
2706 break;
0e5d435a
JS		 2707 case 2:
2708 cut = "C";
2709 break;
2710 case 3:
2711 cut = "D";
2712 break;
2713 case 4:
2714 cut = "E";
2715 break;
26f1fad2
JS		 2716 default:
2717 cut = "unknown";
2718 }
2719
2720 dev_info(dev,
2721 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
0e5d435a
JS		 2722 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
2723 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
2724 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
26f1fad2
JS		 2725
2726 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
2727}
2728
2729static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
2730{
2731 struct device *dev = &priv->udev->dev;
2732 u32 val32, bonding;
2733 u16 val16;
2734
2735 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
2736 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
2737 SYS_CFG_CHIP_VERSION_SHIFT;
2738 if (val32 & SYS_CFG_TRP_VAUX_EN) {
2739 dev_info(dev, "Unsupported test chip\n");
2740 return -ENOTSUPP;
2741 }
2742
2743 if (val32 & SYS_CFG_BT_FUNC) {
35a741fe
JS		 2744 if (priv->chip_cut >= 3) {
2745 sprintf(priv->chip_name, "8723BU");
ba17d824 2746 priv->rtl_chip = RTL8723B;
35a741fe
JS		 2747 } else {
2748 sprintf(priv->chip_name, "8723AU");
0e28b975 2749 priv->usb_interrupts = 1;
ba17d824 2750 priv->rtl_chip = RTL8723A;
35a741fe
JS		 2751 }
2752
26f1fad2
JS		 2753 priv->rf_paths = 1;
2754 priv->rx_paths = 1;
2755 priv->tx_paths = 1;
26f1fad2
JS		 2756
2757 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
2758 if (val32 & MULTI_WIFI_FUNC_EN)
2759 priv->has_wifi = 1;
2760 if (val32 & MULTI_BT_FUNC_EN)
2761 priv->has_bluetooth = 1;
2762 if (val32 & MULTI_GPS_FUNC_EN)
2763 priv->has_gps = 1;
38451998 2764 priv->is_multi_func = 1;
26f1fad2
JS		 2765 } else if (val32 & SYS_CFG_TYPE_ID) {
2766 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
2767 bonding &= HPON_FSM_BONDING_MASK;
55c0b6ae
JS		 2768 if (priv->fops->tx_desc_size ==
2769 sizeof(struct rtl8xxxu_txdesc40)) {
0e5d435a
JS		 2770 if (bonding == HPON_FSM_BONDING_1T2R) {
2771 sprintf(priv->chip_name, "8191EU");
2772 priv->rf_paths = 2;
2773 priv->rx_paths = 2;
2774 priv->tx_paths = 1;
ba17d824 2775 priv->rtl_chip = RTL8191E;
0e5d435a
JS		 2776 } else {
2777 sprintf(priv->chip_name, "8192EU");
2778 priv->rf_paths = 2;
2779 priv->rx_paths = 2;
2780 priv->tx_paths = 2;
ba17d824 2781 priv->rtl_chip = RTL8192E;
0e5d435a
JS		 2782 }
2783 } else if (bonding == HPON_FSM_BONDING_1T2R) {
26f1fad2
JS		 2784 sprintf(priv->chip_name, "8191CU");
2785 priv->rf_paths = 2;
2786 priv->rx_paths = 2;
2787 priv->tx_paths = 1;
0e28b975 2788 priv->usb_interrupts = 1;
ba17d824 2789 priv->rtl_chip = RTL8191C;
26f1fad2
JS		 2790 } else {
2791 sprintf(priv->chip_name, "8192CU");
2792 priv->rf_paths = 2;
2793 priv->rx_paths = 2;
2794 priv->tx_paths = 2;
0e28b975 2795 priv->usb_interrupts = 1;
ba17d824 2796 priv->rtl_chip = RTL8192C;
26f1fad2
JS		 2797 }
2798 priv->has_wifi = 1;
2799 } else {
2800 sprintf(priv->chip_name, "8188CU");
2801 priv->rf_paths = 1;
2802 priv->rx_paths = 1;
2803 priv->tx_paths = 1;
ba17d824 2804 priv->rtl_chip = RTL8188C;
0e28b975 2805 priv->usb_interrupts = 1;
26f1fad2
JS		 2806 priv->has_wifi = 1;
2807 }
2808
ba17d824
JS		 2809 switch (priv->rtl_chip) {
2810 case RTL8188E:
2811 case RTL8192E:
2812 case RTL8723B:
0e5d435a
JS		 2813 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
2814 case SYS_CFG_VENDOR_ID_TSMC:
2815 sprintf(priv->chip_vendor, "TSMC");
2816 break;
2817 case SYS_CFG_VENDOR_ID_SMIC:
2818 sprintf(priv->chip_vendor, "SMIC");
2819 priv->vendor_smic = 1;
2820 break;
2821 case SYS_CFG_VENDOR_ID_UMC:
2822 sprintf(priv->chip_vendor, "UMC");
2823 priv->vendor_umc = 1;
2824 break;
2825 default:
2826 sprintf(priv->chip_vendor, "unknown");
2827 }
2828 break;
2829 default:
2830 if (val32 & SYS_CFG_VENDOR_ID) {
2831 sprintf(priv->chip_vendor, "UMC");
2832 priv->vendor_umc = 1;
2833 } else {
2834 sprintf(priv->chip_vendor, "TSMC");
2835 }
2836 }
26f1fad2
JS		 2837
2838 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
2839 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
2840
2841 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
2842 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
2843 priv->ep_tx_high_queue = 1;
2844 priv->ep_tx_count++;
2845 }
2846
2847 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
2848 priv->ep_tx_normal_queue = 1;
2849 priv->ep_tx_count++;
2850 }
2851
2852 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
2853 priv->ep_tx_low_queue = 1;
2854 priv->ep_tx_count++;
2855 }
2856
2857 /*
2858 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
2859 */
2860 if (!priv->ep_tx_count) {
2861 switch (priv->nr_out_eps) {
35a741fe 2862 case 4:
26f1fad2
JS		 2863 case 3:
2864 priv->ep_tx_low_queue = 1;
2865 priv->ep_tx_count++;
2866 case 2:
2867 priv->ep_tx_normal_queue = 1;
2868 priv->ep_tx_count++;
2869 case 1:
2870 priv->ep_tx_high_queue = 1;
2871 priv->ep_tx_count++;
2872 break;
2873 default:
2874 dev_info(dev, "Unsupported USB TX end-points\n");
2875 return -ENOTSUPP;
2876 }
2877 }
2878
2879 return 0;
2880}
2881
2882static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
2883{
d38f1c37
JS		 2884 struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
2885
2886 if (efuse->rtl_id != cpu_to_le16(0x8129))
26f1fad2
JS		 2887 return -EINVAL;
2888
d38f1c37 2889 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
26f1fad2
JS		 2890
2891 memcpy(priv->cck_tx_power_index_A,
d38f1c37 2892 efuse->cck_tx_power_index_A,
3e84f938 2893 sizeof(efuse->cck_tx_power_index_A));
26f1fad2 2894 memcpy(priv->cck_tx_power_index_B,
d38f1c37 2895 efuse->cck_tx_power_index_B,
3e84f938 2896 sizeof(efuse->cck_tx_power_index_B));
26f1fad2
JS		 2897
2898 memcpy(priv->ht40_1s_tx_power_index_A,
d38f1c37 2899 efuse->ht40_1s_tx_power_index_A,
3e84f938 2900 sizeof(efuse->ht40_1s_tx_power_index_A));
26f1fad2 2901 memcpy(priv->ht40_1s_tx_power_index_B,
d38f1c37 2902 efuse->ht40_1s_tx_power_index_B,
3e84f938 2903 sizeof(efuse->ht40_1s_tx_power_index_B));
26f1fad2
JS		 2904
2905 memcpy(priv->ht20_tx_power_index_diff,
d38f1c37 2906 efuse->ht20_tx_power_index_diff,
3e84f938 2907 sizeof(efuse->ht20_tx_power_index_diff));
26f1fad2 2908 memcpy(priv->ofdm_tx_power_index_diff,
d38f1c37 2909 efuse->ofdm_tx_power_index_diff,
3e84f938 2910 sizeof(efuse->ofdm_tx_power_index_diff));
26f1fad2
JS		 2911
2912 memcpy(priv->ht40_max_power_offset,
d38f1c37 2913 efuse->ht40_max_power_offset,
3e84f938 2914 sizeof(efuse->ht40_max_power_offset));
26f1fad2 2915 memcpy(priv->ht20_max_power_offset,
d38f1c37 2916 efuse->ht20_max_power_offset,
3e84f938 2917 sizeof(efuse->ht20_max_power_offset));
26f1fad2 2918
4ef22eb9
JS		 2919 if (priv->efuse_wifi.efuse8723.version >= 0x01) {
2920 priv->has_xtalk = 1;
2921 priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2922 }
26f1fad2 2923 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
d38f1c37 2924 efuse->vendor_name);
26f1fad2 2925 dev_info(&priv->udev->dev, "Product: %.41s\n",
d38f1c37 2926 efuse->device_name);
26f1fad2
JS		 2927 return 0;
2928}
2929
3c836d60
JS		 2930static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
2931{
b8ba8602 2932 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
3be26999 2933 int i;
b8ba8602
JS		 2934
2935 if (efuse->rtl_id != cpu_to_le16(0x8129))
3c836d60
JS		 2936 return -EINVAL;
2937
b8ba8602 2938 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
3c836d60 2939
3be26999
JS		 2940 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
2941 sizeof(efuse->tx_power_index_A.cck_base));
2942 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
2943 sizeof(efuse->tx_power_index_B.cck_base));
2944
2945 memcpy(priv->ht40_1s_tx_power_index_A,
2946 efuse->tx_power_index_A.ht40_base,
2947 sizeof(efuse->tx_power_index_A.ht40_base));
2948 memcpy(priv->ht40_1s_tx_power_index_B,
2949 efuse->tx_power_index_B.ht40_base,
2950 sizeof(efuse->tx_power_index_B.ht40_base));
2951
2952 priv->ofdm_tx_power_diff[0].a =
2953 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
2954 priv->ofdm_tx_power_diff[0].b =
2955 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
2956
2957 priv->ht20_tx_power_diff[0].a =
2958 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
2959 priv->ht20_tx_power_diff[0].b =
2960 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
2961
2962 priv->ht40_tx_power_diff[0].a = 0;
2963 priv->ht40_tx_power_diff[0].b = 0;
2964
2965 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
2966 priv->ofdm_tx_power_diff[i].a =
2967 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
2968 priv->ofdm_tx_power_diff[i].b =
2969 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
2970
2971 priv->ht20_tx_power_diff[i].a =
2972 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
2973 priv->ht20_tx_power_diff[i].b =
2974 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
2975
2976 priv->ht40_tx_power_diff[i].a =
2977 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
2978 priv->ht40_tx_power_diff[i].b =
2979 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
2980 }
2981
4ef22eb9
JS		 2982 priv->has_xtalk = 1;
2983 priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
2984
b8ba8602
JS		 2985 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
2986 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
3c836d60
JS		 2987
2988 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
2989 int i;
2990 unsigned char *raw = priv->efuse_wifi.raw;
2991
2992 dev_info(&priv->udev->dev,
2993 "%s: dumping efuse (0x%02zx bytes):\n",
2994 __func__, sizeof(struct rtl8723bu_efuse));
2995 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) {
2996 dev_info(&priv->udev->dev, "%02x: "
2997 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
2998 raw[i], raw[i + 1], raw[i + 2],
2999 raw[i + 3], raw[i + 4], raw[i + 5],
3000 raw[i + 6], raw[i + 7]);
3001 }
3002 }
3003
3004 return 0;
3005}
3006
c0963772
KV		 3007#ifdef CONFIG_RTL8XXXU_UNTESTED
3008
26f1fad2
JS		 3009static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
3010{
49594441 3011 struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192;
26f1fad2
JS		 3012 int i;
3013
49594441 3014 if (efuse->rtl_id != cpu_to_le16(0x8129))
26f1fad2
JS		 3015 return -EINVAL;
3016
49594441 3017 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
26f1fad2
JS		 3018
3019 memcpy(priv->cck_tx_power_index_A,
49594441 3020 efuse->cck_tx_power_index_A,
3e84f938 3021 sizeof(efuse->cck_tx_power_index_A));
26f1fad2 3022 memcpy(priv->cck_tx_power_index_B,
49594441 3023 efuse->cck_tx_power_index_B,
3e84f938 3024 sizeof(efuse->cck_tx_power_index_B));
26f1fad2
JS		 3025
3026 memcpy(priv->ht40_1s_tx_power_index_A,
49594441 3027 efuse->ht40_1s_tx_power_index_A,
3e84f938 3028 sizeof(efuse->ht40_1s_tx_power_index_A));
26f1fad2 3029 memcpy(priv->ht40_1s_tx_power_index_B,
49594441 3030 efuse->ht40_1s_tx_power_index_B,
3e84f938 3031 sizeof(efuse->ht40_1s_tx_power_index_B));
26f1fad2 3032 memcpy(priv->ht40_2s_tx_power_index_diff,
49594441 3033 efuse->ht40_2s_tx_power_index_diff,
3e84f938 3034 sizeof(efuse->ht40_2s_tx_power_index_diff));
26f1fad2
JS		 3035
3036 memcpy(priv->ht20_tx_power_index_diff,
49594441 3037 efuse->ht20_tx_power_index_diff,
3e84f938 3038 sizeof(efuse->ht20_tx_power_index_diff));
26f1fad2 3039 memcpy(priv->ofdm_tx_power_index_diff,
49594441 3040 efuse->ofdm_tx_power_index_diff,
3e84f938 3041 sizeof(efuse->ofdm_tx_power_index_diff));
26f1fad2
JS		 3042
3043 memcpy(priv->ht40_max_power_offset,
49594441 3044 efuse->ht40_max_power_offset,
3e84f938 3045 sizeof(efuse->ht40_max_power_offset));
26f1fad2 3046 memcpy(priv->ht20_max_power_offset,
49594441 3047 efuse->ht20_max_power_offset,
3e84f938 3048 sizeof(efuse->ht20_max_power_offset));
26f1fad2
JS		 3049
3050 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
49594441 3051 efuse->vendor_name);
26f1fad2 3052 dev_info(&priv->udev->dev, "Product: %.20s\n",
49594441 3053 efuse->device_name);
26f1fad2 3054
49594441 3055 if (efuse->rf_regulatory & 0x20) {
26f1fad2 3056 sprintf(priv->chip_name, "8188RU");
8d95c808 3057 priv->rtl_chip = RTL8188R;
26f1fad2
JS		 3058 priv->hi_pa = 1;
3059 }
3060
3061 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
3062 unsigned char *raw = priv->efuse_wifi.raw;
3063
3064 dev_info(&priv->udev->dev,
3065 "%s: dumping efuse (0x%02zx bytes):\n",
3066 __func__, sizeof(struct rtl8192cu_efuse));
3067 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
3068 dev_info(&priv->udev->dev, "%02x: "
3069 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
3070 raw[i], raw[i + 1], raw[i + 2],
3071 raw[i + 3], raw[i + 4], raw[i + 5],
3072 raw[i + 6], raw[i + 7]);
3073 }
3074 }
3075 return 0;
3076}
3077
c0963772
KV		 3078#endif
3079
3307d840
JS		 3080static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
3081{
b7dda34d 3082 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
3307d840
JS		 3083 int i;
3084
b7dda34d 3085 if (efuse->rtl_id != cpu_to_le16(0x8129))
3307d840
JS		 3086 return -EINVAL;
3087
b7dda34d 3088 ether_addr_copy(priv->mac_addr, efuse->mac_addr);
3307d840 3089
9e24772a
JS		 3090 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
3091 sizeof(efuse->tx_power_index_A.cck_base));
3092 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
3093 sizeof(efuse->tx_power_index_B.cck_base));
3094
3095 memcpy(priv->ht40_1s_tx_power_index_A,
3096 efuse->tx_power_index_A.ht40_base,
3097 sizeof(efuse->tx_power_index_A.ht40_base));
3098 memcpy(priv->ht40_1s_tx_power_index_B,
3099 efuse->tx_power_index_B.ht40_base,
3100 sizeof(efuse->tx_power_index_B.ht40_base));
3101
3102 priv->ht20_tx_power_diff[0].a =
3103 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
3104 priv->ht20_tx_power_diff[0].b =
3105 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
3106
3107 priv->ht40_tx_power_diff[0].a = 0;
3108 priv->ht40_tx_power_diff[0].b = 0;
3109
3110 for (i = 1; i < RTL8723B_TX_COUNT; i++) {
3111 priv->ofdm_tx_power_diff[i].a =
3112 efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
3113 priv->ofdm_tx_power_diff[i].b =
3114 efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
3115
3116 priv->ht20_tx_power_diff[i].a =
3117 efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
3118 priv->ht20_tx_power_diff[i].b =
3119 efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
3120
3121 priv->ht40_tx_power_diff[i].a =
3122 efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
3123 priv->ht40_tx_power_diff[i].b =
3124 efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
3125 }
3126
4ef22eb9
JS		 3127 priv->has_xtalk = 1;
3128 priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
3129
b7dda34d
JS		 3130 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
3131 dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name);
3132 dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial);
3307d840
JS		 3133
3134 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
3135 unsigned char *raw = priv->efuse_wifi.raw;
3136
3137 dev_info(&priv->udev->dev,
3138 "%s: dumping efuse (0x%02zx bytes):\n",
3139 __func__, sizeof(struct rtl8192eu_efuse));
3140 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
3141 dev_info(&priv->udev->dev, "%02x: "
3142 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
3143 raw[i], raw[i + 1], raw[i + 2],
3144 raw[i + 3], raw[i + 4], raw[i + 5],
3145 raw[i + 6], raw[i + 7]);
3146 }
3147 }
0e5d435a 3148 return 0;
3307d840
JS		 3149}
3150
26f1fad2
JS		 3151static int
3152rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
3153{
3154 int i;
3155 u8 val8;
3156 u32 val32;
3157
3158 /* Write Address */
3159 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
3160 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
3161 val8 &= 0xfc;
3162 val8 |= (offset >> 8) & 0x03;
3163 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
3164
3165 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
3166 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
3167
3168 /* Poll for data read */
3169 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3170 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
3171 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3172 if (val32 & BIT(31))
3173 break;
3174 }
3175
3176 if (i == RTL8XXXU_MAX_REG_POLL)
3177 return -EIO;
3178
3179 udelay(50);
3180 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3181
3182 *data = val32 & 0xff;
3183 return 0;
3184}
3185
3186static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
3187{
3188 struct device *dev = &priv->udev->dev;
3189 int i, ret = 0;
3190 u8 val8, word_mask, header, extheader;
3191 u16 val16, efuse_addr, offset;
3192 u32 val32;
3193
3194 val16 = rtl8xxxu_read16(priv, REG_9346CR);
3195 if (val16 & EEPROM_ENABLE)
3196 priv->has_eeprom = 1;
3197 if (val16 & EEPROM_BOOT)
3198 priv->boot_eeprom = 1;
3199
38451998
JS		 3200 if (priv->is_multi_func) {
3201 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
3202 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
3203 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
3204 }
26f1fad2
JS		 3205
3206 dev_dbg(dev, "Booting from %s\n",
3207 priv->boot_eeprom ? "EEPROM" : "EFUSE");
3208
3209 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
3210
3211 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
3212 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3213 if (!(val16 & SYS_ISO_PWC_EV12V)) {
3214 val16 |= SYS_ISO_PWC_EV12V;
3215 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3216 }
3217 /* Reset: 0x0000[28], default valid */
3218 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3219 if (!(val16 & SYS_FUNC_ELDR)) {
3220 val16 |= SYS_FUNC_ELDR;
3221 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3222 }
3223
3224 /*
3225 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
3226 */
3227 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
3228 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
3229 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
3230 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
3231 }
3232
3233 /* Default value is 0xff */
3307d840 3234 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
26f1fad2
JS		 3235
3236 efuse_addr = 0;
3237 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
f6c47702
JS		 3238 u16 map_addr;
3239
26f1fad2
JS		 3240 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
3241 if (ret || header == 0xff)
3242 goto exit;
3243
3244 if ((header & 0x1f) == 0x0f) { /* extended header */
3245 offset = (header & 0xe0) >> 5;
3246
3247 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
3248 &extheader);
3249 if (ret)
3250 goto exit;
3251 /* All words disabled */
3252 if ((extheader & 0x0f) == 0x0f)
3253 continue;
3254
3255 offset |= ((extheader & 0xf0) >> 1);
3256 word_mask = extheader & 0x0f;
3257 } else {
3258 offset = (header >> 4) & 0x0f;
3259 word_mask = header & 0x0f;
3260 }
3261
f6c47702
JS		 3262 /* Get word enable value from PG header */
3263
3264 /* We have 8 bits to indicate validity */
3265 map_addr = offset * 8;
3266 if (map_addr >= EFUSE_MAP_LEN) {
3267 dev_warn(dev, "%s: Illegal map_addr (%04x), "
3268 "efuse corrupt!\n",
3269 __func__, map_addr);
26f1fad2
JS		 3270 ret = -EINVAL;
3271 goto exit;
3272 }
f6c47702
JS		 3273 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
3274 /* Check word enable condition in the section */
32a39dd4 3275 if (word_mask & BIT(i)) {
f6c47702 3276 map_addr += 2;
32a39dd4
JS		 3277 continue;
3278 }
3279
3280 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
3281 if (ret)
3282 goto exit;
3283 priv->efuse_wifi.raw[map_addr++] = val8;
3284
3285 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
3286 if (ret)
3287 goto exit;
3288 priv->efuse_wifi.raw[map_addr++] = val8;
f6c47702 3289 }
26f1fad2
JS		 3290 }
3291
3292exit:
3293 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
3294
3295 return ret;
3296}
3297
d48fe60e
JS		 3298static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
3299{
3300 u8 val8;
3301 u16 sys_func;
3302
3303 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 3304 val8 &= ~BIT(0);
d48fe60e 3305 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7d4ccb8b 3306
d48fe60e
JS		 3307 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3308 sys_func &= ~SYS_FUNC_CPU_ENABLE;
3309 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
7d4ccb8b 3310
d48fe60e 3311 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 3312 val8 |= BIT(0);
d48fe60e 3313 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7d4ccb8b
JS		 3314
3315 sys_func |= SYS_FUNC_CPU_ENABLE;
3316 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3317}
3318
3319static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
3320{
3321 u8 val8;
3322 u16 sys_func;
3323
3324 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3325 val8 &= ~BIT(1);
3326 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
3327
3328 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3329 val8 &= ~BIT(0);
3330 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3331
3332 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3333 sys_func &= ~SYS_FUNC_CPU_ENABLE;
3334 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3335
3336 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3337 val8 &= ~BIT(1);
3338 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
3339
3340 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3341 val8 |= BIT(0);
3342 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3343
d48fe60e
JS		 3344 sys_func |= SYS_FUNC_CPU_ENABLE;
3345 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
3346}
3347
26f1fad2
JS		 3348static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
3349{
3350 struct device *dev = &priv->udev->dev;
3351 int ret = 0, i;
3352 u32 val32;
3353
3354 /* Poll checksum report */
3355 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
3356 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3357 if (val32 & MCU_FW_DL_CSUM_REPORT)
3358 break;
3359 }
3360
3361 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
3362 dev_warn(dev, "Firmware checksum poll timed out\n");
3363 ret = -EAGAIN;
3364 goto exit;
3365 }
3366
3367 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3368 val32 |= MCU_FW_DL_READY;
3369 val32 &= ~MCU_WINT_INIT_READY;
3370 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
3371
d48fe60e
JS		 3372 /*
3373 * Reset the 8051 in order for the firmware to start running,
3374 * otherwise it won't come up on the 8192eu
3375 */
7d4ccb8b 3376 priv->fops->reset_8051(priv);
d48fe60e 3377
26f1fad2
JS		 3378 /* Wait for firmware to become ready */
3379 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
3380 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
3381 if (val32 & MCU_WINT_INIT_READY)
3382 break;
3383
3384 udelay(100);
3385 }
3386
3387 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
3388 dev_warn(dev, "Firmware failed to start\n");
3389 ret = -EAGAIN;
3390 goto exit;
3391 }
3392
3a4be6a0
JS		 3393 /*
3394 * Init H2C command
3395 */
ba17d824 3396 if (priv->rtl_chip == RTL8723B)
3a4be6a0 3397 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
26f1fad2
JS		 3398exit:
3399 return ret;
3400}
3401
3402static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
3403{
3404 int pages, remainder, i, ret;
d48fe60e 3405 u8 val8;
26f1fad2
JS		 3406 u16 val16;
3407 u32 val32;
3408 u8 *fwptr;
3409
3410 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
3411 val8 |= 4;
3412 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
3413
3414 /* 8051 enable */
3415 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
43154f6f
JS		 3416 val16 |= SYS_FUNC_CPU_ENABLE;
3417 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 3418
216202ae
JS		 3419 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
3420 if (val8 & MCU_FW_RAM_SEL) {
3421 pr_info("do the RAM reset\n");
3422 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
7d4ccb8b 3423 priv->fops->reset_8051(priv);
216202ae
JS		 3424 }
3425
26f1fad2
JS		 3426 /* MCU firmware download enable */
3427 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 3428 val8 |= MCU_FW_DL_ENABLE;
3429 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 3430
3431 /* 8051 reset */
3432 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
ef1c0499
JS		 3433 val32 &= ~BIT(19);
3434 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
26f1fad2
JS		 3435
3436 /* Reset firmware download checksum */
3437 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 3438 val8 |= MCU_FW_DL_CSUM_REPORT;
3439 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 3440
3441 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
3442 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
3443
3444 fwptr = priv->fw_data->data;
3445
3446 for (i = 0; i < pages; i++) {
3447 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 3448 val8 |= i;
3449 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 3450
3451 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
3452 fwptr, RTL_FW_PAGE_SIZE);
3453 if (ret != RTL_FW_PAGE_SIZE) {
3454 ret = -EAGAIN;
3455 goto fw_abort;
3456 }
3457
3458 fwptr += RTL_FW_PAGE_SIZE;
3459 }
3460
3461 if (remainder) {
3462 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 3463 val8 |= i;
3464 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 3465 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
3466 fwptr, remainder);
3467 if (ret != remainder) {
3468 ret = -EAGAIN;
3469 goto fw_abort;
3470 }
3471 }
3472
3473 ret = 0;
3474fw_abort:
3475 /* MCU firmware download disable */
3476 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
ef1c0499
JS		 3477 val16 &= ~MCU_FW_DL_ENABLE;
3478 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
26f1fad2
JS		 3479
3480 return ret;
3481}
3482
3483static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
3484{
3485 struct device *dev = &priv->udev->dev;
3486 const struct firmware *fw;
3487 int ret = 0;
3488 u16 signature;
3489
3490 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
3491 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
3492 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
3493 ret = -EAGAIN;
3494 goto exit;
3495 }
3496 if (!fw) {
3497 dev_warn(dev, "Firmware data not available\n");
3498 ret = -EINVAL;
3499 goto exit;
3500 }
3501
3502 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
98e27cbd
TK		 3503 if (!priv->fw_data) {
3504 ret = -ENOMEM;
3505 goto exit;
3506 }
26f1fad2
JS		 3507 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
3508
3509 signature = le16_to_cpu(priv->fw_data->signature);
3510 switch (signature & 0xfff0) {
0e5d435a 3511 case 0x92e0:
26f1fad2
JS		 3512 case 0x92c0:
3513 case 0x88c0:
35a741fe 3514 case 0x5300:
26f1fad2
JS		 3515 case 0x2300:
3516 break;
3517 default:
3518 ret = -EINVAL;
3519 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
3520 __func__, signature);
3521 }
3522
3523 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
3524 le16_to_cpu(priv->fw_data->major_version),
3525 priv->fw_data->minor_version, signature);
3526
3527exit:
3528 release_firmware(fw);
3529 return ret;
3530}
3531
3532static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
3533{
3534 char *fw_name;
3535 int ret;
3536
3537 switch (priv->chip_cut) {
3538 case 0:
3539 fw_name = "rtlwifi/rtl8723aufw_A.bin";
3540 break;
3541 case 1:
3542 if (priv->enable_bluetooth)
3543 fw_name = "rtlwifi/rtl8723aufw_B.bin";
3544 else
3545 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
3546
3547 break;
3548 default:
3549 return -EINVAL;
3550 }
3551
3552 ret = rtl8xxxu_load_firmware(priv, fw_name);
3553 return ret;
3554}
3555
35a741fe
JS		 3556static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
3557{
3558 char *fw_name;
3559 int ret;
3560
3561 if (priv->enable_bluetooth)
3562 fw_name = "rtlwifi/rtl8723bu_bt.bin";
3563 else
3564 fw_name = "rtlwifi/rtl8723bu_nic.bin";
3565
3566 ret = rtl8xxxu_load_firmware(priv, fw_name);
3567 return ret;
3568}
3569
c0963772
KV		 3570#ifdef CONFIG_RTL8XXXU_UNTESTED
3571
26f1fad2
JS		 3572static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
3573{
3574 char *fw_name;
3575 int ret;
3576
3577 if (!priv->vendor_umc)
3578 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
ba17d824 3579 else if (priv->chip_cut || priv->rtl_chip == RTL8192C)
26f1fad2
JS		 3580 fw_name = "rtlwifi/rtl8192cufw_B.bin";
3581 else
3582 fw_name = "rtlwifi/rtl8192cufw_A.bin";
3583
3584 ret = rtl8xxxu_load_firmware(priv, fw_name);
3585
3586 return ret;
3587}
3588
c0963772
KV		 3589#endif
3590
3307d840
JS		 3591static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
3592{
3593 char *fw_name;
3594 int ret;
3595
0e5d435a 3596 fw_name = "rtlwifi/rtl8192eu_nic.bin";
3307d840
JS		 3597
3598 ret = rtl8xxxu_load_firmware(priv, fw_name);
3599
3600 return ret;
3601}
3602
26f1fad2
JS		 3603static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
3604{
3605 u16 val16;
3606 int i = 100;
3607
3608 /* Inform 8051 to perform reset */
3609 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
3610
3611 for (i = 100; i > 0; i--) {
3612 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3613
3614 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
3615 dev_dbg(&priv->udev->dev,
3616 "%s: Firmware self reset success!\n", __func__);
3617 break;
3618 }
3619 udelay(50);
3620 }
3621
3622 if (!i) {
3623 /* Force firmware reset */
3624 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3625 val16 &= ~SYS_FUNC_CPU_ENABLE;
3626 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3627 }
3628}
3629
f0d9f5e9
JS		 3630static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
3631{
3632 u32 val32;
3633
70bc1e24 3634 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1);
f0d9f5e9 3635 val32 &= ~(BIT(20) | BIT(24));
70bc1e24 3636 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32);
f0d9f5e9
JS		 3637
3638 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
3639 val32 &= ~BIT(4);
3a4be6a0
JS		 3640 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3641
3642 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
f0d9f5e9
JS		 3643 val32 |= BIT(3);
3644 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
3645
3646 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
f0d9f5e9
JS		 3647 val32 |= BIT(24);
3648 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3649
3a4be6a0
JS		 3650 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
3651 val32 &= ~BIT(23);
3652 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
3653
120e627f 3654 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
f0d9f5e9 3655 val32 |= (BIT(0) | BIT(1));
120e627f 3656 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
f0d9f5e9 3657
59b74397 3658 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
f0d9f5e9
JS		 3659 val32 &= 0xffffff00;
3660 val32 |= 0x77;
59b74397 3661 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
3a4be6a0
JS		 3662
3663 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
3664 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
3665 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
f0d9f5e9
JS		 3666}
3667
26f1fad2 3668static int
c606e662 3669rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
26f1fad2 3670{
c606e662 3671 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
26f1fad2
JS		 3672 int i, ret;
3673 u16 reg;
3674 u8 val;
3675
3676 for (i = 0; ; i++) {
3677 reg = array[i].reg;
3678 val = array[i].val;
3679
3680 if (reg == 0xffff && val == 0xff)
3681 break;
3682
3683 ret = rtl8xxxu_write8(priv, reg, val);
3684 if (ret != 1) {
3685 dev_warn(&priv->udev->dev,
c606e662
JS		 3686 "Failed to initialize MAC "
3687 "(reg: %04x, val %02x)\n", reg, val);
26f1fad2
JS		 3688 return -EAGAIN;
3689 }
3690 }
3691
8a59485c 3692 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
8baf670b 3693 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
26f1fad2
JS		 3694
3695 return 0;
3696}
3697
3698static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
3699 struct rtl8xxxu_reg32val *array)
3700{
3701 int i, ret;
3702 u16 reg;
3703 u32 val;
3704
3705 for (i = 0; ; i++) {
3706 reg = array[i].reg;
3707 val = array[i].val;
3708
3709 if (reg == 0xffff && val == 0xffffffff)
3710 break;
3711
3712 ret = rtl8xxxu_write32(priv, reg, val);
3713 if (ret != sizeof(val)) {
3714 dev_warn(&priv->udev->dev,
3715 "Failed to initialize PHY\n");
3716 return -EAGAIN;
3717 }
3718 udelay(1);
3719 }
3720
3721 return 0;
3722}
3723
cb877250 3724static void rtl8723au_init_phy_bb(struct rtl8xxxu_priv *priv)
26f1fad2 3725{
b84cac16 3726 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
04313eb4 3727 u16 val16;
26f1fad2
JS		 3728 u32 val32;
3729
cb877250
JS		 3730 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
3731 udelay(2);
3732 val8 |= AFE_PLL_320_ENABLE;
3733 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
3734 udelay(2);
3ca7b32c 3735
cb877250
JS		 3736 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
3737 udelay(2);
26f1fad2 3738
cb877250
JS		 3739 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3740 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
3741 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 3742
cb877250
JS		 3743 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
3744 val32 &= ~AFE_XTAL_RF_GATE;
3745 if (priv->has_bluetooth)
3746 val32 &= ~AFE_XTAL_BT_GATE;
3747 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
26f1fad2
JS		 3748
3749 /* 6. 0x1f[7:0] = 0x07 */
3750 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3751 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3752
cb877250 3753 if (priv->hi_pa)
abd71bdb
JS		 3754 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
3755 else if (priv->tx_paths == 2)
3756 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
3757 else
26f1fad2
JS		 3758 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
3759
78a84219 3760 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
26f1fad2
JS		 3761 priv->vendor_umc && priv->chip_cut == 1)
3762 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
c82f8d11
JS		 3763
3764 if (priv->hi_pa)
3765 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
3766 else
3767 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
b84cac16
JS		 3768
3769 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
3770 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
3771 ldohci12 = 0x57;
3772 lpldo = 1;
3773 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
3774 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
cb877250
JS		 3775}
3776
3777static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv)
3778{
3779 u8 val8;
3780 u16 val16;
3781
3782 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3783 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
3784 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3785
3786 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
3787
3788 /* 6. 0x1f[7:0] = 0x07 */
3789 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3790 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3791
3792 /* Why? */
3793 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
3794 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
3795 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
c82f8d11
JS		 3796
3797 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
cb877250
JS		 3798}
3799
3800static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv)
3801{
3802 u8 val8;
3803 u16 val16;
3804
3805 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3806 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
3807 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3808
3809 /* 6. 0x1f[7:0] = 0x07 */
3810 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3811 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3812
3813 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3814 val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |
3815 SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);
3816 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3817 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
3818 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
3819 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);
c82f8d11
JS		 3820
3821 if (priv->hi_pa)
3822 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table);
3823 else
3824 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table);
cb877250
JS		 3825}
3826
3827/*
3828 * Most of this is black magic retrieved from the old rtl8723au driver
3829 */
3830static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
3831{
b84cac16 3832 u8 val8;
cb877250
JS		 3833 u32 val32;
3834
3835 priv->fops->init_phy_bb(priv);
26f1fad2
JS		 3836
3837 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
3838 /*
3839 * For 1T2R boards, patch the registers.
3840 *
3841 * It looks like 8191/2 1T2R boards use path B for TX
3842 */
3843 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
3844 val32 &= ~(BIT(0) | BIT(1));
3845 val32 |= BIT(1);
3846 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
3847
3848 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
3849 val32 &= ~0x300033;
3850 val32 |= 0x200022;
3851 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
3852
3853 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
bd8fe40c 3854 val32 &= ~CCK0_AFE_RX_MASK;
9068308a 3855 val32 &= 0x00ffffff;
bd8fe40c
JS		 3856 val32 |= 0x40000000;
3857 val32 |= CCK0_AFE_RX_ANT_B;
26f1fad2
JS		 3858 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
3859
3860 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
3861 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
3862 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
3863 OFDM_RF_PATH_TX_B);
3864 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
3865
3866 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
3867 val32 &= ~(BIT(4) | BIT(5));
3868 val32 |= BIT(4);
3869 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
3870
3871 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
3872 val32 &= ~(BIT(27) | BIT(26));
3873 val32 |= BIT(27);
3874 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
3875
3876 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
3877 val32 &= ~(BIT(27) | BIT(26));
3878 val32 |= BIT(27);
3879 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
3880
3881 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
3882 val32 &= ~(BIT(27) | BIT(26));
3883 val32 |= BIT(27);
3884 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
3885
3886 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
3887 val32 &= ~(BIT(27) | BIT(26));
3888 val32 |= BIT(27);
3889 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
3890
3891 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
3892 val32 &= ~(BIT(27) | BIT(26));
3893 val32 |= BIT(27);
3894 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
3895 }
3896
4ef22eb9 3897 if (priv->has_xtalk) {
26f1fad2
JS		 3898 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
3899
4ef22eb9 3900 val8 = priv->xtalk;
26f1fad2
JS		 3901 val32 &= 0xff000fff;
3902 val32 |= ((val8 | (val8 << 6)) << 12);
3903
3904 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
3905 }
3906
8a59485c
JS		 3907 if (priv->rtl_chip == RTL8192E)
3908 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
3909
26f1fad2
JS		 3910 return 0;
3911}
3912
3913static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
3914 struct rtl8xxxu_rfregval *array,
3915 enum rtl8xxxu_rfpath path)
3916{
3917 int i, ret;
3918 u8 reg;
3919 u32 val;
3920
3921 for (i = 0; ; i++) {
3922 reg = array[i].reg;
3923 val = array[i].val;
3924
3925 if (reg == 0xff && val == 0xffffffff)
3926 break;
3927
3928 switch (reg) {
3929 case 0xfe:
3930 msleep(50);
3931 continue;
3932 case 0xfd:
3933 mdelay(5);
3934 continue;
3935 case 0xfc:
3936 mdelay(1);
3937 continue;
3938 case 0xfb:
3939 udelay(50);
3940 continue;
3941 case 0xfa:
3942 udelay(5);
3943 continue;
3944 case 0xf9:
3945 udelay(1);
3946 continue;
3947 }
3948
26f1fad2
JS		 3949 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
3950 if (ret) {
3951 dev_warn(&priv->udev->dev,
3952 "Failed to initialize RF\n");
3953 return -EAGAIN;
3954 }
3955 udelay(1);
3956 }
3957
3958 return 0;
3959}
3960
3961static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
3962 struct rtl8xxxu_rfregval *table,
3963 enum rtl8xxxu_rfpath path)
3964{
3965 u32 val32;
3966 u16 val16, rfsi_rfenv;
3967 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
3968
3969 switch (path) {
3970 case RF_A:
3971 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
3972 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
3973 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
3974 break;
3975 case RF_B:
3976 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
3977 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
3978 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
3979 break;
3980 default:
3981 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
3982 __func__, path + 'A');
3983 return -EINVAL;
3984 }
3985 /* For path B, use XB */
3986 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
3987 rfsi_rfenv &= FPGA0_RF_RFENV;
3988
3989 /*
3990 * These two we might be able to optimize into one
3991 */
3992 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3993 val32 |= BIT(20); /* 0x10 << 16 */
3994 rtl8xxxu_write32(priv, reg_int_oe, val32);
3995 udelay(1);
3996
3997 val32 = rtl8xxxu_read32(priv, reg_int_oe);
3998 val32 |= BIT(4);
3999 rtl8xxxu_write32(priv, reg_int_oe, val32);
4000 udelay(1);
4001
4002 /*
4003 * These two we might be able to optimize into one
4004 */
4005 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
4006 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
4007 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
4008 udelay(1);
4009
4010 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
4011 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
4012 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
4013 udelay(1);
4014
4015 rtl8xxxu_init_rf_regs(priv, table, path);
4016
4017 /* For path B, use XB */
4018 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
4019 val16 &= ~FPGA0_RF_RFENV;
4020 val16 |= rfsi_rfenv;
4021 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
4022
4023 return 0;
4024}
4025
4062b8ff
JS		 4026static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv)
4027{
4028 int ret;
4029
4030 ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A);
4031
4032 /* Reduce 80M spur */
4033 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4034 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4035 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4036 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4037
4038 return ret;
4039}
4040
4041static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
4042{
4043 int ret;
4044
4045 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A);
4046 /*
4047 * PHY LCK
4048 */
4049 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
4050 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
4051 msleep(200);
4052 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
4053
4054 return ret;
4055}
4056
4057#ifdef CONFIG_RTL8XXXU_UNTESTED
4058static int rtl8192cu_init_phy_rf(struct rtl8xxxu_priv *priv)
4059{
4060 struct rtl8xxxu_rfregval *rftable;
4061 int ret;
4062
8d95c808
JS		 4063 if (priv->rtl_chip == RTL8188R) {
4064 rftable = rtl8188ru_radioa_1t_highpa_table;
4062b8ff
JS		 4065 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4066 } else if (priv->rf_paths == 1) {
4067 rftable = rtl8192cu_radioa_1t_init_table;
4068 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4069 } else {
4070 rftable = rtl8192cu_radioa_2t_init_table;
4071 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4072 if (ret)
4073 goto exit;
4074 rftable = rtl8192cu_radiob_2t_init_table;
4075 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4076 }
4077
4078exit:
4079 return ret;
4080}
4081#endif
4082
4083static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv)
4084{
4085 int ret;
4086
4087 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A);
4088 if (ret)
4089 goto exit;
4090
4091 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B);
4092
4093exit:
4094 return ret;
4095}
4096
26f1fad2
JS		 4097static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
4098{
4099 int ret = -EBUSY;
4100 int count = 0;
4101 u32 value;
4102
4103 value = LLT_OP_WRITE | address << 8 | data;
4104
4105 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
4106
4107 do {
4108 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
4109 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
4110 ret = 0;
4111 break;
4112 }
4113 } while (count++ < 20);
4114
4115 return ret;
4116}
4117
4118static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
4119{
4120 int ret;
4121 int i;
4122
4123 for (i = 0; i < last_tx_page; i++) {
4124 ret = rtl8xxxu_llt_write(priv, i, i + 1);
4125 if (ret)
4126 goto exit;
4127 }
4128
4129 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
4130 if (ret)
4131 goto exit;
4132
4133 /* Mark remaining pages as a ring buffer */
4134 for (i = last_tx_page + 1; i < 0xff; i++) {
4135 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
4136 if (ret)
4137 goto exit;
4138 }
4139
4140 /* Let last entry point to the start entry of ring buffer */
4141 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
4142 if (ret)
4143 goto exit;
4144
4145exit:
4146 return ret;
4147}
4148
74b99bed
JS		 4149static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
4150{
4151 u32 val32;
4152 int ret = 0;
4153 int i;
4154
4155 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
74b99bed
JS		 4156 val32 |= AUTO_LLT_INIT_LLT;
4157 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
4158
4159 for (i = 500; i; i--) {
4160 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
4161 if (!(val32 & AUTO_LLT_INIT_LLT))
4162 break;
4163 usleep_range(2, 4);
4164 }
4165
4de24819 4166 if (!i) {
74b99bed
JS		 4167 ret = -EBUSY;
4168 dev_warn(&priv->udev->dev, "LLT table init failed\n");
4169 }
74b99bed
JS		 4170
4171 return ret;
4172}
4173
26f1fad2
JS		 4174static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
4175{
4176 u16 val16, hi, lo;
4177 u16 hiq, mgq, bkq, beq, viq, voq;
4178 int hip, mgp, bkp, bep, vip, vop;
4179 int ret = 0;
4180
4181 switch (priv->ep_tx_count) {
4182 case 1:
4183 if (priv->ep_tx_high_queue) {
4184 hi = TRXDMA_QUEUE_HIGH;
4185 } else if (priv->ep_tx_low_queue) {
4186 hi = TRXDMA_QUEUE_LOW;
4187 } else if (priv->ep_tx_normal_queue) {
4188 hi = TRXDMA_QUEUE_NORMAL;
4189 } else {
4190 hi = 0;
4191 ret = -EINVAL;
4192 }
4193
4194 hiq = hi;
4195 mgq = hi;
4196 bkq = hi;
4197 beq = hi;
4198 viq = hi;
4199 voq = hi;
4200
4201 hip = 0;
4202 mgp = 0;
4203 bkp = 0;
4204 bep = 0;
4205 vip = 0;
4206 vop = 0;
4207 break;
4208 case 2:
4209 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
4210 hi = TRXDMA_QUEUE_HIGH;
4211 lo = TRXDMA_QUEUE_LOW;
4212 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
4213 hi = TRXDMA_QUEUE_NORMAL;
4214 lo = TRXDMA_QUEUE_LOW;
4215 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
4216 hi = TRXDMA_QUEUE_HIGH;
4217 lo = TRXDMA_QUEUE_NORMAL;
4218 } else {
4219 ret = -EINVAL;
4220 hi = 0;
4221 lo = 0;
4222 }
4223
4224 hiq = hi;
4225 mgq = hi;
4226 bkq = lo;
4227 beq = lo;
4228 viq = hi;
4229 voq = hi;
4230
4231 hip = 0;
4232 mgp = 0;
4233 bkp = 1;
4234 bep = 1;
4235 vip = 0;
4236 vop = 0;
4237 break;
4238 case 3:
4239 beq = TRXDMA_QUEUE_LOW;
4240 bkq = TRXDMA_QUEUE_LOW;
4241 viq = TRXDMA_QUEUE_NORMAL;
4242 voq = TRXDMA_QUEUE_HIGH;
4243 mgq = TRXDMA_QUEUE_HIGH;
4244 hiq = TRXDMA_QUEUE_HIGH;
4245
4246 hip = hiq ^ 3;
4247 mgp = mgq ^ 3;
4248 bkp = bkq ^ 3;
4249 bep = beq ^ 3;
4250 vip = viq ^ 3;
4251 vop = viq ^ 3;
4252 break;
4253 default:
4254 ret = -EINVAL;
4255 }
4256
4257 /*
4258 * None of the vendor drivers are configuring the beacon
4259 * queue here .... why?
4260 */
4261 if (!ret) {
4262 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
4263 val16 &= 0x7;
4264 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
4265 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
4266 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
4267 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
4268 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
4269 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
4270 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
4271
4272 priv->pipe_out[TXDESC_QUEUE_VO] =
4273 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
4274 priv->pipe_out[TXDESC_QUEUE_VI] =
4275 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
4276 priv->pipe_out[TXDESC_QUEUE_BE] =
4277 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
4278 priv->pipe_out[TXDESC_QUEUE_BK] =
4279 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
4280 priv->pipe_out[TXDESC_QUEUE_BEACON] =
4281 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
4282 priv->pipe_out[TXDESC_QUEUE_MGNT] =
4283 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
4284 priv->pipe_out[TXDESC_QUEUE_HIGH] =
4285 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
4286 priv->pipe_out[TXDESC_QUEUE_CMD] =
4287 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
4288 }
4289
4290 return ret;
4291}
4292
4293static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
4294 bool iqk_ok, int result[][8],
4295 int candidate, bool tx_only)
4296{
4297 u32 oldval, x, tx0_a, reg;
4298 int y, tx0_c;
4299 u32 val32;
4300
4301 if (!iqk_ok)
4302 return;
4303
4304 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4305 oldval = val32 >> 22;
4306
4307 x = result[candidate][0];
4308 if ((x & 0x00000200) != 0)
4309 x = x | 0xfffffc00;
4310 tx0_a = (x * oldval) >> 8;
4311
4312 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4313 val32 &= ~0x3ff;
4314 val32 |= tx0_a;
4315 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
4316
4317 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4318 val32 &= ~BIT(31);
4319 if ((x * oldval >> 7) & 0x1)
4320 val32 |= BIT(31);
4321 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4322
4323 y = result[candidate][1];
4324 if ((y & 0x00000200) != 0)
4325 y = y | 0xfffffc00;
4326 tx0_c = (y * oldval) >> 8;
4327
4328 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
4329 val32 &= ~0xf0000000;
4330 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
4331 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
4332
4333 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
4334 val32 &= ~0x003f0000;
4335 val32 |= ((tx0_c & 0x3f) << 16);
4336 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
4337
4338 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4339 val32 &= ~BIT(29);
4340 if ((y * oldval >> 7) & 0x1)
4341 val32 |= BIT(29);
4342 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4343
4344 if (tx_only) {
4345 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
4346 return;
4347 }
4348
4349 reg = result[candidate][2];
4350
4351 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
4352 val32 &= ~0x3ff;
4353 val32 |= (reg & 0x3ff);
4354 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
4355
4356 reg = result[candidate][3] & 0x3F;
4357
4358 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
4359 val32 &= ~0xfc00;
4360 val32 |= ((reg << 10) & 0xfc00);
4361 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
4362
4363 reg = (result[candidate][3] >> 6) & 0xF;
4364
4365 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
4366 val32 &= ~0xf0000000;
4367 val32 |= (reg << 28);
4368 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
4369}
4370
4371static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
4372 bool iqk_ok, int result[][8],
4373 int candidate, bool tx_only)
4374{
4375 u32 oldval, x, tx1_a, reg;
4376 int y, tx1_c;
4377 u32 val32;
4378
4379 if (!iqk_ok)
4380 return;
4381
4382 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4383 oldval = val32 >> 22;
4384
4385 x = result[candidate][4];
4386 if ((x & 0x00000200) != 0)
4387 x = x | 0xfffffc00;
4388 tx1_a = (x * oldval) >> 8;
4389
4390 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4391 val32 &= ~0x3ff;
4392 val32 |= tx1_a;
4393 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
4394
4395 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4396 val32 &= ~BIT(27);
4397 if ((x * oldval >> 7) & 0x1)
4398 val32 |= BIT(27);
4399 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4400
4401 y = result[candidate][5];
4402 if ((y & 0x00000200) != 0)
4403 y = y | 0xfffffc00;
4404 tx1_c = (y * oldval) >> 8;
4405
4406 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
4407 val32 &= ~0xf0000000;
4408 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
4409 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
4410
4411 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
4412 val32 &= ~0x003f0000;
4413 val32 |= ((tx1_c & 0x3f) << 16);
4414 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
4415
4416 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
4417 val32 &= ~BIT(25);
4418 if ((y * oldval >> 7) & 0x1)
4419 val32 |= BIT(25);
4420 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
4421
4422 if (tx_only) {
4423 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
4424 return;
4425 }
4426
4427 reg = result[candidate][6];
4428
4429 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
4430 val32 &= ~0x3ff;
4431 val32 |= (reg & 0x3ff);
4432 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
4433
4434 reg = result[candidate][7] & 0x3f;
4435
4436 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
4437 val32 &= ~0xfc00;
4438 val32 |= ((reg << 10) & 0xfc00);
4439 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
4440
4441 reg = (result[candidate][7] >> 6) & 0xf;
4442
4443 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
4444 val32 &= ~0x0000f000;
4445 val32 |= (reg << 12);
4446 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
4447}
4448
4449#define MAX_TOLERANCE 5
4450
4451static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
4452 int result[][8], int c1, int c2)
4453{
4454 u32 i, j, diff, simubitmap, bound = 0;
4455 int candidate[2] = {-1, -1}; /* for path A and path B */
4456 bool retval = true;
4457
4458 if (priv->tx_paths > 1)
4459 bound = 8;
4460 else
4461 bound = 4;
4462
4463 simubitmap = 0;
4464
4465 for (i = 0; i < bound; i++) {
4466 diff = (result[c1][i] > result[c2][i]) ?
4467 (result[c1][i] - result[c2][i]) :
4468 (result[c2][i] - result[c1][i]);
4469 if (diff > MAX_TOLERANCE) {
4470 if ((i == 2 || i == 6) && !simubitmap) {
4471 if (result[c1][i] + result[c1][i + 1] == 0)
4472 candidate[(i / 4)] = c2;
4473 else if (result[c2][i] + result[c2][i + 1] == 0)
4474 candidate[(i / 4)] = c1;
4475 else
4476 simubitmap = simubitmap | (1 << i);
4477 } else {
4478 simubitmap = simubitmap | (1 << i);
4479 }
4480 }
4481 }
4482
4483 if (simubitmap == 0) {
4484 for (i = 0; i < (bound / 4); i++) {
4485 if (candidate[i] >= 0) {
4486 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
4487 result[3][j] = result[candidate[i]][j];
4488 retval = false;
4489 }
4490 }
4491 return retval;
4492 } else if (!(simubitmap & 0x0f)) {
4493 /* path A OK */
4494 for (i = 0; i < 4; i++)
4495 result[3][i] = result[c1][i];
4496 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
4497 /* path B OK */
4498 for (i = 4; i < 8; i++)
4499 result[3][i] = result[c1][i];
4500 }
4501
4502 return false;
4503}
4504
e1547c53
JS		 4505static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv,
4506 int result[][8], int c1, int c2)
4507{
4508 u32 i, j, diff, simubitmap, bound = 0;
4509 int candidate[2] = {-1, -1}; /* for path A and path B */
4510 int tmp1, tmp2;
4511 bool retval = true;
4512
4513 if (priv->tx_paths > 1)
4514 bound = 8;
4515 else
4516 bound = 4;
4517
4518 simubitmap = 0;
4519
4520 for (i = 0; i < bound; i++) {
4521 if (i & 1) {
4522 if ((result[c1][i] & 0x00000200))
4523 tmp1 = result[c1][i] | 0xfffffc00;
4524 else
4525 tmp1 = result[c1][i];
4526
4527 if ((result[c2][i]& 0x00000200))
4528 tmp2 = result[c2][i] | 0xfffffc00;
4529 else
4530 tmp2 = result[c2][i];
4531 } else {
4532 tmp1 = result[c1][i];
4533 tmp2 = result[c2][i];
4534 }
4535
4536 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
4537
4538 if (diff > MAX_TOLERANCE) {
4539 if ((i == 2 || i == 6) && !simubitmap) {
4540 if (result[c1][i] + result[c1][i + 1] == 0)
4541 candidate[(i / 4)] = c2;
4542 else if (result[c2][i] + result[c2][i + 1] == 0)
4543 candidate[(i / 4)] = c1;
4544 else
4545 simubitmap = simubitmap | (1 << i);
4546 } else {
4547 simubitmap = simubitmap | (1 << i);
4548 }
4549 }
4550 }
4551
4552 if (simubitmap == 0) {
4553 for (i = 0; i < (bound / 4); i++) {
4554 if (candidate[i] >= 0) {
4555 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
4556 result[3][j] = result[candidate[i]][j];
4557 retval = false;
4558 }
4559 }
4560 return retval;
4561 } else {
4562 if (!(simubitmap & 0x03)) {
4563 /* path A TX OK */
4564 for (i = 0; i < 2; i++)
4565 result[3][i] = result[c1][i];
4566 }
4567
4568 if (!(simubitmap & 0x0c)) {
4569 /* path A RX OK */
4570 for (i = 2; i < 4; i++)
4571 result[3][i] = result[c1][i];
4572 }
4573
4574 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4575 /* path B RX OK */
4576 for (i = 4; i < 6; i++)
4577 result[3][i] = result[c1][i];
4578 }
4579
4580 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
4581 /* path B RX OK */
4582 for (i = 6; i < 8; i++)
4583 result[3][i] = result[c1][i];
4584 }
4585 }
4586
4587 return false;
4588}
4589
26f1fad2
JS		 4590static void
4591rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
4592{
4593 int i;
4594
4595 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4596 backup[i] = rtl8xxxu_read8(priv, reg[i]);
4597
4598 backup[i] = rtl8xxxu_read32(priv, reg[i]);
4599}
4600
4601static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
4602 const u32 *reg, u32 *backup)
4603{
4604 int i;
4605
4606 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
4607 rtl8xxxu_write8(priv, reg[i], backup[i]);
4608
4609 rtl8xxxu_write32(priv, reg[i], backup[i]);
4610}
4611
4612static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4613 u32 *backup, int count)
4614{
4615 int i;
4616
4617 for (i = 0; i < count; i++)
4618 backup[i] = rtl8xxxu_read32(priv, regs[i]);
4619}
4620
4621static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
4622 u32 *backup, int count)
4623{
4624 int i;
4625
4626 for (i = 0; i < count; i++)
4627 rtl8xxxu_write32(priv, regs[i], backup[i]);
4628}
4629
4630
4631static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
4632 bool path_a_on)
4633{
4634 u32 path_on;
4635 int i;
4636
26f1fad2 4637 if (priv->tx_paths == 1) {
8634af5e
JS		 4638 path_on = priv->fops->adda_1t_path_on;
4639 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
26f1fad2 4640 } else {
8634af5e
JS		 4641 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
4642 priv->fops->adda_2t_path_on_b;
4643
26f1fad2
JS		 4644 rtl8xxxu_write32(priv, regs[0], path_on);
4645 }
4646
4647 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
4648 rtl8xxxu_write32(priv, regs[i], path_on);
4649}
4650
4651static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
4652 const u32 *regs, u32 *backup)
4653{
4654 int i = 0;
4655
4656 rtl8xxxu_write8(priv, regs[i], 0x3f);
4657
4658 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
4659 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
4660
4661 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
4662}
4663
4664static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
4665{
4666 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
4667 int result = 0;
4668
4669 /* path-A IQK setting */
4670 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
4671 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
4672 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
4673
4674 val32 = (priv->rf_paths > 1) ? 0x28160202 :
4675 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
4676 0x28160502;
4677 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
4678
4679 /* path-B IQK setting */
4680 if (priv->rf_paths > 1) {
4681 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
4682 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
4683 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
4684 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
4685 }
4686
4687 /* LO calibration setting */
4688 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
4689
4690 /* One shot, path A LOK & IQK */
4691 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4692 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4693
4694 mdelay(1);
4695
4696 /* Check failed */
4697 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4698 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4699 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4700 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
4701
4702 if (!(reg_eac & BIT(28)) &&
4703 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4704 ((reg_e9c & 0x03ff0000) != 0x00420000))
4705 result |= 0x01;
4706 else /* If TX not OK, ignore RX */
4707 goto out;
4708
4709 /* If TX is OK, check whether RX is OK */
4710 if (!(reg_eac & BIT(27)) &&
4711 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
4712 ((reg_eac & 0x03ff0000) != 0x00360000))
4713 result |= 0x02;
4714 else
4715 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
4716 __func__);
4717out:
4718 return result;
4719}
4720
4721static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
4722{
4723 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
4724 int result = 0;
4725
4726 /* One shot, path B LOK & IQK */
4727 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
4728 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
4729
4730 mdelay(1);
4731
4732 /* Check failed */
4733 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4734 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
4735 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
4736 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
4737 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
4738
4739 if (!(reg_eac & BIT(31)) &&
4740 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
4741 ((reg_ebc & 0x03ff0000) != 0x00420000))
4742 result |= 0x01;
4743 else
4744 goto out;
4745
4746 if (!(reg_eac & BIT(30)) &&
4747 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
4748 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
4749 result |= 0x02;
4750 else
4751 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
4752 __func__);
4753out:
4754 return result;
4755}
4756
e1547c53
JS		 4757static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
4758{
4759 u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
4760 int result = 0;
4761
4762 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4763
4764 /*
4765 * Leave IQK mode
4766 */
4767 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4768 val32 &= 0x000000ff;
4769 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4770
4771 /*
4772 * Enable path A PA in TX IQK mode
4773 */
4774 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4775 val32 |= 0x80000;
4776 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4777 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
4778 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
4779 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
4780
4781 /*
4782 * Tx IQK setting
4783 */
4784 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4785 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4786
4787 /* path-A IQK setting */
4788 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4789 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4790 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4791 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4792
4793 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
4794 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4795 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4796 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4797
4798 /* LO calibration setting */
4799 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
4800
4801 /*
4802 * Enter IQK mode
4803 */
4804 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4805 val32 &= 0x000000ff;
4806 val32 |= 0x80800000;
4807 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4808
4809 /*
4810 * The vendor driver indicates the USB module is always using
4811 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4812 */
4813 if (priv->rf_paths > 1)
4814 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4815 else
4816 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4817
4818 /*
4819 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4820 * No trace of this in the 8192eu or 8188eu vendor drivers.
4821 */
4822 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4823
4824 /* One shot, path A LOK & IQK */
4825 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4826 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4827
4828 mdelay(1);
4829
4830 /* Restore Ant Path */
4831 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4832#ifdef RTL8723BU_BT
4833 /* GNT_BT = 1 */
4834 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4835#endif
4836
4837 /*
4838 * Leave IQK mode
4839 */
4840 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4841 val32 &= 0x000000ff;
4842 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4843
4844 /* Check failed */
4845 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4846 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4847 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4848
4849 val32 = (reg_e9c >> 16) & 0x3ff;
4850 if (val32 & 0x200)
4851 val32 = 0x400 - val32;
4852
4853 if (!(reg_eac & BIT(28)) &&
4854 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4855 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4856 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4857 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4858 val32 < 0xf)
4859 result |= 0x01;
4860 else /* If TX not OK, ignore RX */
4861 goto out;
4862
4863out:
4864 return result;
4865}
4866
4867static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
4868{
4869 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
4870 int result = 0;
4871
4872 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
4873
4874 /*
4875 * Leave IQK mode
4876 */
4877 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4878 val32 &= 0x000000ff;
4879 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4880
4881 /*
4882 * Enable path A PA in TX IQK mode
4883 */
4884 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4885 val32 |= 0x80000;
4886 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4887 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4888 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4889 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
4890
4891 /*
4892 * Tx IQK setting
4893 */
4894 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
4895 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
4896
4897 /* path-A IQK setting */
4898 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
4899 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
4900 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
4901 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
4902
4903 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
4904 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
4905 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
4906 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
4907
4908 /* LO calibration setting */
4909 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
4910
4911 /*
4912 * Enter IQK mode
4913 */
4914 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4915 val32 &= 0x000000ff;
4916 val32 |= 0x80800000;
4917 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4918
4919 /*
4920 * The vendor driver indicates the USB module is always using
4921 * S0S1 path 1 for the 8723bu. This may be different for 8192eu
4922 */
4923 if (priv->rf_paths > 1)
4924 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
4925 else
4926 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
4927
4928 /*
4929 * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
4930 * No trace of this in the 8192eu or 8188eu vendor drivers.
4931 */
4932 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
4933
4934 /* One shot, path A LOK & IQK */
4935 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
4936 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
4937
4938 mdelay(1);
4939
4940 /* Restore Ant Path */
4941 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
4942#ifdef RTL8723BU_BT
4943 /* GNT_BT = 1 */
4944 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
4945#endif
4946
4947 /*
4948 * Leave IQK mode
4949 */
4950 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4951 val32 &= 0x000000ff;
4952 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4953
4954 /* Check failed */
4955 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
4956 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
4957 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
4958
4959 val32 = (reg_e9c >> 16) & 0x3ff;
4960 if (val32 & 0x200)
4961 val32 = 0x400 - val32;
4962
4963 if (!(reg_eac & BIT(28)) &&
4964 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
4965 ((reg_e9c & 0x03ff0000) != 0x00420000) &&
4966 ((reg_e94 & 0x03ff0000) < 0x01100000) &&
4967 ((reg_e94 & 0x03ff0000) > 0x00f00000) &&
4968 val32 < 0xf)
4969 result |= 0x01;
4970 else /* If TX not OK, ignore RX */
4971 goto out;
4972
4973 val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
4974 ((reg_e9c & 0x3ff0000) >> 16);
4975 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
4976
4977 /*
4978 * Modify RX IQK mode
4979 */
4980 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
4981 val32 &= 0x000000ff;
4982 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
4983 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
4984 val32 |= 0x80000;
4985 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
4986 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
4987 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
4988 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
4989
4990 /*
4991 * PA, PAD setting
4992 */
4993 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
4994 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
4995
4996 /*
4997 * RX IQK setting
4998 */
4999 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5000
5001 /* path-A IQK setting */
5002 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5003 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
5004 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5005 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5006
5007 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
5008 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
5009 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
5010 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
5011
5012 /* LO calibration setting */
5013 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
5014
5015 /*
5016 * Enter IQK mode
5017 */
5018 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5019 val32 &= 0x000000ff;
5020 val32 |= 0x80800000;
5021 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5022
5023 if (priv->rf_paths > 1)
5024 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
5025 else
5026 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
5027
5028 /*
5029 * Disable BT
5030 */
5031 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
5032
5033 /* One shot, path A LOK & IQK */
5034 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
5035 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5036
5037 mdelay(1);
5038
5039 /* Restore Ant Path */
5040 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
5041#ifdef RTL8723BU_BT
5042 /* GNT_BT = 1 */
5043 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
5044#endif
5045
5046 /*
5047 * Leave IQK mode
5048 */
5049 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5050 val32 &= 0x000000ff;
5051 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5052
5053 /* Check failed */
5054 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5055 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
5056
5057 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
5058
5059 val32 = (reg_eac >> 16) & 0x3ff;
5060 if (val32 & 0x200)
5061 val32 = 0x400 - val32;
5062
5063 if (!(reg_eac & BIT(27)) &&
5064 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
5065 ((reg_eac & 0x03ff0000) != 0x00360000) &&
5066 ((reg_ea4 & 0x03ff0000) < 0x01100000) &&
5067 ((reg_ea4 & 0x03ff0000) > 0x00f00000) &&
5068 val32 < 0xf)
5069 result |= 0x02;
5070 else /* If TX not OK, ignore RX */
5071 goto out;
5072out:
5073 return result;
5074}
5075
f991f4e9
JS		 5076static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)
5077{
5078 u32 reg_eac, reg_e94, reg_e9c;
5079 int result = 0;
5080
5081 /*
5082 * TX IQK
5083 * PA/PAD controlled by 0x0
5084 */
5085 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5086 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180);
5087 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5088
5089 /* Path A IQK setting */
5090 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
5091 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5092 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5093 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5094
5095 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303);
5096 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000);
5097
5098 /* LO calibration setting */
5099 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
5100
5101 /* One shot, path A LOK & IQK */
5102 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
5103 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5104
5105 mdelay(10);
5106
5107 /* Check failed */
5108 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5109 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
5110 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
5111
5112 if (!(reg_eac & BIT(28)) &&
5113 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
5114 ((reg_e9c & 0x03ff0000) != 0x00420000))
5115 result |= 0x01;
5116
5117 return result;
5118}
5119
5120static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
5121{
5122 u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
5123 int result = 0;
5124
5125 /* Leave IQK mode */
5126 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
5127
5128 /* Enable path A PA in TX IQK mode */
5129 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
5130 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
5131 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
5132 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);
5133
5134 /* PA/PAD control by 0x56, and set = 0x0 */
5135 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
5136 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
5137
5138 /* Enter IQK mode */
5139 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5140
5141 /* TX IQK setting */
5142 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5143 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5144
5145 /* path-A IQK setting */
5146 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
5147 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5148 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5149 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5150
5151 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
5152 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f);
5153
5154 /* LO calibration setting */
5155 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
5156
5157 /* One shot, path A LOK & IQK */
5158 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5159 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5160
5161 mdelay(10);
5162
5163 /* Check failed */
5164 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5165 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
5166 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
5167
5168 if (!(reg_eac & BIT(28)) &&
5169 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
5170 ((reg_e9c & 0x03ff0000) != 0x00420000)) {
5171 result |= 0x01;
5172 } else {
5173 /* PA/PAD controlled by 0x0 */
5174 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5175 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
5176 goto out;
5177 }
5178
5179 val32 = 0x80007c00 |
5180 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);
5181 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
5182
5183 /* Modify RX IQK mode table */
5184 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5185
5186 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
5187 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
5188 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
5189 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);
5190
5191 /* PA/PAD control by 0x56, and set = 0x0 */
5192 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
5193 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
5194
5195 /* Enter IQK mode */
5196 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5197
5198 /* IQK setting */
5199 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5200
5201 /* Path A IQK setting */
5202 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5203 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
5204 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5205 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5206
5207 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
5208 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
5209
5210 /* LO calibration setting */
5211 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
5212
5213 /* One shot, path A LOK & IQK */
5214 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5215 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5216
5217 mdelay(10);
5218
5219 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5220 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
5221
5222 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5223 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
5224
5225 if (!(reg_eac & BIT(27)) &&
5226 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
5227 ((reg_eac & 0x03ff0000) != 0x00360000))
5228 result |= 0x02;
5229 else
5230 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
5231 __func__);
5232
5233out:
5234 return result;
5235}
5236
5237static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)
5238{
5239 u32 reg_eac, reg_eb4, reg_ebc;
5240 int result = 0;
5241
5242 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5243 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180);
5244 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5245
5246 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5247 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5248
5249 /* Path B IQK setting */
5250 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5251 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5252 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
5253 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5254
5255 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2);
5256 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);
5257
5258 /* LO calibration setting */
5259 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911);
5260
5261 /* One shot, path A LOK & IQK */
5262 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5263 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5264
5265 mdelay(1);
5266
5267 /* Check failed */
5268 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5269 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5270 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5271
5272 if (!(reg_eac & BIT(31)) &&
5273 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
5274 ((reg_ebc & 0x03ff0000) != 0x00420000))
5275 result |= 0x01;
5276 else
5277 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
5278 __func__);
5279
5280 return result;
5281}
5282
5283static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
5284{
5285 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;
5286 int result = 0;
5287
5288 /* Leave IQK mode */
5289 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5290
5291 /* Enable path A PA in TX IQK mode */
5292 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
5293 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
5294 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
5295 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b);
5296
5297 /* PA/PAD control by 0x56, and set = 0x0 */
5298 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
5299 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
5300
5301 /* Enter IQK mode */
5302 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5303
5304 /* TX IQK setting */
5305 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5306 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5307
5308 /* path-A IQK setting */
5309 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5310 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5311 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
5312 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
5313
5314 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f);
5315 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f);
5316
5317 /* LO calibration setting */
5318 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
5319
5320 /* One shot, path A LOK & IQK */
5321 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5322 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5323
5324 mdelay(10);
5325
5326 /* Check failed */
5327 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5328 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5329 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5330
5331 if (!(reg_eac & BIT(31)) &&
5332 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
5333 ((reg_ebc & 0x03ff0000) != 0x00420000)) {
5334 result |= 0x01;
5335 } else {
5336 /*
5337 * PA/PAD controlled by 0x0
5338 * Vendor driver restores RF_A here which I believe is a bug
5339 */
5340 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5341 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
5342 goto out;
5343 }
5344
5345 val32 = 0x80007c00 |
5346 (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);
5347 rtl8xxxu_write32(priv, REG_TX_IQK, val32);
5348
5349 /* Modify RX IQK mode table */
5350 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5351
5352 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
5353 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
5354 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
5355 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa);
5356
5357 /* PA/PAD control by 0x56, and set = 0x0 */
5358 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
5359 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
5360
5361 /* Enter IQK mode */
5362 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5363
5364 /* IQK setting */
5365 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5366
5367 /* Path A IQK setting */
5368 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
5369 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
5370 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
5371 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);
5372
5373 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
5374 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
5375
5376 /* LO calibration setting */
5377 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
5378
5379 /* One shot, path A LOK & IQK */
5380 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
5381 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
5382
5383 mdelay(10);
5384
5385 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
5386 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
5387 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
5388
5389 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5390 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
5391
5392 if (!(reg_eac & BIT(30)) &&
5393 ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
5394 ((reg_ecc & 0x03ff0000) != 0x00360000))
5395 result |= 0x02;
5396 else
5397 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
5398 __func__);
5399
5400out:
5401 return result;
5402}
5403
26f1fad2
JS		 5404static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
5405 int result[][8], int t)
5406{
5407 struct device *dev = &priv->udev->dev;
5408 u32 i, val32;
5409 int path_a_ok, path_b_ok;
5410 int retry = 2;
5411 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
5412 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
5413 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
5414 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
5415 REG_TX_OFDM_BBON, REG_TX_TO_RX,
5416 REG_TX_TO_TX, REG_RX_CCK,
5417 REG_RX_OFDM, REG_RX_WAIT_RIFS,
5418 REG_RX_TO_RX, REG_STANDBY,
5419 REG_SLEEP, REG_PMPD_ANAEN
5420 };
5421 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
5422 REG_TXPAUSE, REG_BEACON_CTRL,
5423 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
5424 };
5425 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
5426 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
5427 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
5428 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
5429 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
5430 };
5431
5432 /*
5433 * Note: IQ calibration must be performed after loading
5434 * PHY_REG.txt , and radio_a, radio_b.txt
5435 */
5436
5437 if (t == 0) {
5438 /* Save ADDA parameters, turn Path A ADDA on */
5439 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
5440 RTL8XXXU_ADDA_REGS);
5441 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5442 rtl8xxxu_save_regs(priv, iqk_bb_regs,
5443 priv->bb_backup, RTL8XXXU_BB_REGS);
5444 }
5445
5446 rtl8xxxu_path_adda_on(priv, adda_regs, true);
5447
5448 if (t == 0) {
5449 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
5450 if (val32 & FPGA0_HSSI_PARM1_PI)
5451 priv->pi_enabled = 1;
5452 }
5453
5454 if (!priv->pi_enabled) {
5455 /* Switch BB to PI mode to do IQ Calibration. */
5456 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
5457 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
5458 }
5459
5460 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
5461 val32 &= ~FPGA_RF_MODE_CCK;
5462 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
5463
5464 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
5465 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
5466 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
5467
5468 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
5469 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
5470 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
5471
5472 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
5473 val32 &= ~BIT(10);
5474 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
5475 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
5476 val32 &= ~BIT(10);
5477 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
5478
5479 if (priv->tx_paths > 1) {
5480 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
5481 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
5482 }
5483
5484 /* MAC settings */
5485 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
5486
5487 /* Page B init */
5488 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
5489
5490 if (priv->tx_paths > 1)
5491 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
5492
5493 /* IQ calibration setting */
5494 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5495 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5496 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5497
5498 for (i = 0; i < retry; i++) {
5499 path_a_ok = rtl8xxxu_iqk_path_a(priv);
5500 if (path_a_ok == 0x03) {
5501 val32 = rtl8xxxu_read32(priv,
5502 REG_TX_POWER_BEFORE_IQK_A);
5503 result[t][0] = (val32 >> 16) & 0x3ff;
5504 val32 = rtl8xxxu_read32(priv,
5505 REG_TX_POWER_AFTER_IQK_A);
5506 result[t][1] = (val32 >> 16) & 0x3ff;
5507 val32 = rtl8xxxu_read32(priv,
5508 REG_RX_POWER_BEFORE_IQK_A_2);
5509 result[t][2] = (val32 >> 16) & 0x3ff;
5510 val32 = rtl8xxxu_read32(priv,
5511 REG_RX_POWER_AFTER_IQK_A_2);
5512 result[t][3] = (val32 >> 16) & 0x3ff;
5513 break;
5514 } else if (i == (retry - 1) && path_a_ok == 0x01) {
5515 /* TX IQK OK */
5516 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
5517 __func__);
5518
5519 val32 = rtl8xxxu_read32(priv,
5520 REG_TX_POWER_BEFORE_IQK_A);
5521 result[t][0] = (val32 >> 16) & 0x3ff;
5522 val32 = rtl8xxxu_read32(priv,
5523 REG_TX_POWER_AFTER_IQK_A);
5524 result[t][1] = (val32 >> 16) & 0x3ff;
5525 }
5526 }
5527
5528 if (!path_a_ok)
5529 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
5530
5531 if (priv->tx_paths > 1) {
5532 /*
5533 * Path A into standby
5534 */
5535 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
5536 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
5537 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5538
5539 /* Turn Path B ADDA on */
5540 rtl8xxxu_path_adda_on(priv, adda_regs, false);
5541
5542 for (i = 0; i < retry; i++) {
5543 path_b_ok = rtl8xxxu_iqk_path_b(priv);
5544 if (path_b_ok == 0x03) {
5545 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5546 result[t][4] = (val32 >> 16) & 0x3ff;
5547 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5548 result[t][5] = (val32 >> 16) & 0x3ff;
5549 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
5550 result[t][6] = (val32 >> 16) & 0x3ff;
5551 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
5552 result[t][7] = (val32 >> 16) & 0x3ff;
5553 break;
5554 } else if (i == (retry - 1) && path_b_ok == 0x01) {
5555 /* TX IQK OK */
5556 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5557 result[t][4] = (val32 >> 16) & 0x3ff;
5558 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5559 result[t][5] = (val32 >> 16) & 0x3ff;
5560 }
5561 }
5562
5563 if (!path_b_ok)
5564 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
5565 }
5566
5567 /* Back to BB mode, load original value */
5568 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
5569
5570 if (t) {
5571 if (!priv->pi_enabled) {
5572 /*
5573 * Switch back BB to SI mode after finishing
5574 * IQ Calibration
5575 */
5576 val32 = 0x01000000;
5577 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
5578 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
5579 }
5580
5581 /* Reload ADDA power saving parameters */
5582 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
5583 RTL8XXXU_ADDA_REGS);
5584
5585 /* Reload MAC parameters */
5586 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5587
5588 /* Reload BB parameters */
5589 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
5590 priv->bb_backup, RTL8XXXU_BB_REGS);
5591
5592 /* Restore RX initial gain */
5593 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
5594
5595 if (priv->tx_paths > 1) {
5596 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
5597 0x00032ed3);
5598 }
5599
5600 /* Load 0xe30 IQC default value */
5601 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
5602 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
5603 }
5604}
5605
e1547c53
JS		 5606static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
5607 int result[][8], int t)
5608{
5609 struct device *dev = &priv->udev->dev;
5610 u32 i, val32;
5611 int path_a_ok /*, path_b_ok */;
5612 int retry = 2;
5613 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
5614 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
5615 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
5616 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
5617 REG_TX_OFDM_BBON, REG_TX_TO_RX,
5618 REG_TX_TO_TX, REG_RX_CCK,
5619 REG_RX_OFDM, REG_RX_WAIT_RIFS,
5620 REG_RX_TO_RX, REG_STANDBY,
5621 REG_SLEEP, REG_PMPD_ANAEN
5622 };
5623 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
5624 REG_TXPAUSE, REG_BEACON_CTRL,
5625 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
5626 };
5627 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
5628 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
5629 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
5630 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
5631 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
5632 };
5633 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
5634 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
5635
5636 /*
5637 * Note: IQ calibration must be performed after loading
5638 * PHY_REG.txt , and radio_a, radio_b.txt
5639 */
5640
5641 if (t == 0) {
5642 /* Save ADDA parameters, turn Path A ADDA on */
5643 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
5644 RTL8XXXU_ADDA_REGS);
5645 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5646 rtl8xxxu_save_regs(priv, iqk_bb_regs,
5647 priv->bb_backup, RTL8XXXU_BB_REGS);
5648 }
5649
5650 rtl8xxxu_path_adda_on(priv, adda_regs, true);
5651
5652 /* MAC settings */
5653 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
5654
5655 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
5656 val32 |= 0x0f000000;
5657 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
5658
5659 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
5660 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
5661 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
5662
e1547c53
JS		 5663 /*
5664 * RX IQ calibration setting for 8723B D cut large current issue
5665 * when leaving IPS
5666 */
5667 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5668 val32 &= 0x000000ff;
5669 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5670
5671 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
5672 val32 |= 0x80000;
5673 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
5674
5675 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
5676 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
5677 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
5678
5679 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
5680 val32 |= 0x20;
5681 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
5682
5683 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
5684
5685 for (i = 0; i < retry; i++) {
5686 path_a_ok = rtl8723bu_iqk_path_a(priv);
5687 if (path_a_ok == 0x01) {
5688 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5689 val32 &= 0x000000ff;
5690 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5691
e1547c53
JS		 5692 val32 = rtl8xxxu_read32(priv,
5693 REG_TX_POWER_BEFORE_IQK_A);
5694 result[t][0] = (val32 >> 16) & 0x3ff;
5695 val32 = rtl8xxxu_read32(priv,
5696 REG_TX_POWER_AFTER_IQK_A);
5697 result[t][1] = (val32 >> 16) & 0x3ff;
5698
5699 break;
5700 }
5701 }
5702
5703 if (!path_a_ok)
5704 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
5705
5706 for (i = 0; i < retry; i++) {
5707 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
5708 if (path_a_ok == 0x03) {
5709 val32 = rtl8xxxu_read32(priv,
5710 REG_RX_POWER_BEFORE_IQK_A_2);
5711 result[t][2] = (val32 >> 16) & 0x3ff;
5712 val32 = rtl8xxxu_read32(priv,
5713 REG_RX_POWER_AFTER_IQK_A_2);
5714 result[t][3] = (val32 >> 16) & 0x3ff;
5715
5716 break;
5717 }
5718 }
5719
5720 if (!path_a_ok)
5721 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
5722
5723 if (priv->tx_paths > 1) {
5724#if 1
5725 dev_warn(dev, "%s: Path B not supported\n", __func__);
5726#else
5727
5728 /*
5729 * Path A into standby
5730 */
5731 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5732 val32 &= 0x000000ff;
5733 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5734 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
5735
5736 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5737 val32 &= 0x000000ff;
5738 val32 |= 0x80800000;
5739 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5740
5741 /* Turn Path B ADDA on */
5742 rtl8xxxu_path_adda_on(priv, adda_regs, false);
5743
5744 for (i = 0; i < retry; i++) {
5745 path_b_ok = rtl8xxxu_iqk_path_b(priv);
5746 if (path_b_ok == 0x03) {
5747 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5748 result[t][4] = (val32 >> 16) & 0x3ff;
5749 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5750 result[t][5] = (val32 >> 16) & 0x3ff;
5751 break;
5752 }
5753 }
5754
5755 if (!path_b_ok)
5756 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
5757
5758 for (i = 0; i < retry; i++) {
5759 path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
5760 if (path_a_ok == 0x03) {
5761 val32 = rtl8xxxu_read32(priv,
5762 REG_RX_POWER_BEFORE_IQK_B_2);
5763 result[t][6] = (val32 >> 16) & 0x3ff;
5764 val32 = rtl8xxxu_read32(priv,
5765 REG_RX_POWER_AFTER_IQK_B_2);
5766 result[t][7] = (val32 >> 16) & 0x3ff;
5767 break;
5768 }
5769 }
5770
5771 if (!path_b_ok)
5772 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
5773#endif
5774 }
5775
5776 /* Back to BB mode, load original value */
5777 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
5778 val32 &= 0x000000ff;
5779 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
5780
5781 if (t) {
5782 /* Reload ADDA power saving parameters */
5783 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
5784 RTL8XXXU_ADDA_REGS);
5785
5786 /* Reload MAC parameters */
5787 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5788
5789 /* Reload BB parameters */
5790 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
5791 priv->bb_backup, RTL8XXXU_BB_REGS);
5792
5793 /* Restore RX initial gain */
5794 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5795 val32 &= 0xffffff00;
5796 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
5797 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
5798
5799 if (priv->tx_paths > 1) {
5800 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
5801 val32 &= 0xffffff00;
5802 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5803 val32 | 0x50);
5804 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5805 val32 | xb_agc);
5806 }
5807
5808 /* Load 0xe30 IQC default value */
5809 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
5810 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
5811 }
5812}
5813
f991f4e9
JS		 5814static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
5815 int result[][8], int t)
5816{
5817 struct device *dev = &priv->udev->dev;
5818 u32 i, val32;
5819 int path_a_ok, path_b_ok;
5820 int retry = 2;
5821 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
5822 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
5823 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
5824 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
5825 REG_TX_OFDM_BBON, REG_TX_TO_RX,
5826 REG_TX_TO_TX, REG_RX_CCK,
5827 REG_RX_OFDM, REG_RX_WAIT_RIFS,
5828 REG_RX_TO_RX, REG_STANDBY,
5829 REG_SLEEP, REG_PMPD_ANAEN
5830 };
5831 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
5832 REG_TXPAUSE, REG_BEACON_CTRL,
5833 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
5834 };
5835 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
5836 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
5837 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
5838 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
5839 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING
5840 };
5841 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
5842 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
5843
5844 /*
5845 * Note: IQ calibration must be performed after loading
5846 * PHY_REG.txt , and radio_a, radio_b.txt
5847 */
5848
5849 if (t == 0) {
5850 /* Save ADDA parameters, turn Path A ADDA on */
5851 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
5852 RTL8XXXU_ADDA_REGS);
5853 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5854 rtl8xxxu_save_regs(priv, iqk_bb_regs,
5855 priv->bb_backup, RTL8XXXU_BB_REGS);
5856 }
5857
5858 rtl8xxxu_path_adda_on(priv, adda_regs, true);
5859
5860 /* MAC settings */
5861 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
5862
5863 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
5864 val32 |= 0x0f000000;
5865 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
5866
5867 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
5868 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
5869 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200);
5870
5871 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
5872 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
5873 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
5874
5875 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
5876 val32 |= BIT(10);
5877 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
5878 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
5879 val32 |= BIT(10);
5880 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
5881
5882 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5883 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5884 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5885
5886 for (i = 0; i < retry; i++) {
5887 path_a_ok = rtl8192eu_iqk_path_a(priv);
5888 if (path_a_ok == 0x01) {
5889 val32 = rtl8xxxu_read32(priv,
5890 REG_TX_POWER_BEFORE_IQK_A);
5891 result[t][0] = (val32 >> 16) & 0x3ff;
5892 val32 = rtl8xxxu_read32(priv,
5893 REG_TX_POWER_AFTER_IQK_A);
5894 result[t][1] = (val32 >> 16) & 0x3ff;
5895
5896 break;
5897 }
5898 }
5899
5900 if (!path_a_ok)
5901 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
5902
5903 for (i = 0; i < retry; i++) {
5904 path_a_ok = rtl8192eu_rx_iqk_path_a(priv);
5905 if (path_a_ok == 0x03) {
5906 val32 = rtl8xxxu_read32(priv,
5907 REG_RX_POWER_BEFORE_IQK_A_2);
5908 result[t][2] = (val32 >> 16) & 0x3ff;
5909 val32 = rtl8xxxu_read32(priv,
5910 REG_RX_POWER_AFTER_IQK_A_2);
5911 result[t][3] = (val32 >> 16) & 0x3ff;
5912
5913 break;
5914 }
5915 }
5916
5917 if (!path_a_ok)
5918 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
5919
5920 if (priv->rf_paths > 1) {
f991f4e9
JS		 5921 /* Path A into standby */
5922 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5923 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
5924 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5925
5926 /* Turn Path B ADDA on */
5927 rtl8xxxu_path_adda_on(priv, adda_regs, false);
5928
5929 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
5930 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
5931 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
5932
5933 for (i = 0; i < retry; i++) {
5934 path_b_ok = rtl8192eu_iqk_path_b(priv);
5935 if (path_b_ok == 0x01) {
5936 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
5937 result[t][4] = (val32 >> 16) & 0x3ff;
5938 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
5939 result[t][5] = (val32 >> 16) & 0x3ff;
5940 break;
5941 }
5942 }
5943
5944 if (!path_b_ok)
5945 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
5946
5947 for (i = 0; i < retry; i++) {
5948 path_b_ok = rtl8192eu_rx_iqk_path_b(priv);
5949 if (path_a_ok == 0x03) {
5950 val32 = rtl8xxxu_read32(priv,
5951 REG_RX_POWER_BEFORE_IQK_B_2);
5952 result[t][6] = (val32 >> 16) & 0x3ff;
5953 val32 = rtl8xxxu_read32(priv,
5954 REG_RX_POWER_AFTER_IQK_B_2);
5955 result[t][7] = (val32 >> 16) & 0x3ff;
5956 break;
5957 }
5958 }
5959
5960 if (!path_b_ok)
5961 dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
5962 }
5963
5964 /* Back to BB mode, load original value */
5965 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
5966
5967 if (t) {
5968 /* Reload ADDA power saving parameters */
5969 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
5970 RTL8XXXU_ADDA_REGS);
5971
5972 /* Reload MAC parameters */
5973 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
5974
5975 /* Reload BB parameters */
5976 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
5977 priv->bb_backup, RTL8XXXU_BB_REGS);
5978
5979 /* Restore RX initial gain */
5980 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
5981 val32 &= 0xffffff00;
5982 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
5983 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
5984
5985 if (priv->rf_paths > 1) {
5986 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
5987 val32 &= 0xffffff00;
5988 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5989 val32 | 0x50);
5990 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
5991 val32 | xb_agc);
5992 }
5993
5994 /* Load 0xe30 IQC default value */
5995 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
5996 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
5997 }
5998}
5999
c7a5a190
JS		 6000static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
6001{
6002 struct h2c_cmd h2c;
6003
6004 if (priv->fops->mbox_ext_width < 4)
6005 return;
6006
6007 memset(&h2c, 0, sizeof(struct h2c_cmd));
6008 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
6009 h2c.bt_wlan_calibration.data = start;
6010
6011 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
6012}
6013
e1547c53 6014static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 6015{
6016 struct device *dev = &priv->udev->dev;
6017 int result[4][8]; /* last is final result */
6018 int i, candidate;
6019 bool path_a_ok, path_b_ok;
6020 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
6021 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
6022 s32 reg_tmp = 0;
6023 bool simu;
6024
c7a5a190
JS		 6025 rtl8xxxu_prepare_calibrate(priv, 1);
6026
26f1fad2
JS		 6027 memset(result, 0, sizeof(result));
6028 candidate = -1;
6029
6030 path_a_ok = false;
6031 path_b_ok = false;
6032
6033 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
6034
6035 for (i = 0; i < 3; i++) {
6036 rtl8xxxu_phy_iqcalibrate(priv, result, i);
6037
6038 if (i == 1) {
6039 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
6040 if (simu) {
6041 candidate = 0;
6042 break;
6043 }
6044 }
6045
6046 if (i == 2) {
6047 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
6048 if (simu) {
6049 candidate = 0;
6050 break;
6051 }
6052
6053 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
6054 if (simu) {
6055 candidate = 1;
6056 } else {
6057 for (i = 0; i < 8; i++)
6058 reg_tmp += result[3][i];
6059
6060 if (reg_tmp)
6061 candidate = 3;
6062 else
6063 candidate = -1;
6064 }
6065 }
6066 }
6067
6068 for (i = 0; i < 4; i++) {
6069 reg_e94 = result[i][0];
6070 reg_e9c = result[i][1];
6071 reg_ea4 = result[i][2];
6072 reg_eac = result[i][3];
6073 reg_eb4 = result[i][4];
6074 reg_ebc = result[i][5];
6075 reg_ec4 = result[i][6];
6076 reg_ecc = result[i][7];
6077 }
6078
6079 if (candidate >= 0) {
6080 reg_e94 = result[candidate][0];
6081 priv->rege94 = reg_e94;
6082 reg_e9c = result[candidate][1];
6083 priv->rege9c = reg_e9c;
6084 reg_ea4 = result[candidate][2];
6085 reg_eac = result[candidate][3];
6086 reg_eb4 = result[candidate][4];
6087 priv->regeb4 = reg_eb4;
6088 reg_ebc = result[candidate][5];
6089 priv->regebc = reg_ebc;
6090 reg_ec4 = result[candidate][6];
6091 reg_ecc = result[candidate][7];
6092 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
6093 dev_dbg(dev,
6094 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6095 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
6096 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
6097 path_a_ok = true;
6098 path_b_ok = true;
6099 } else {
6100 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
6101 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
6102 }
6103
6104 if (reg_e94 && candidate >= 0)
6105 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
6106 candidate, (reg_ea4 == 0));
6107
6108 if (priv->tx_paths > 1 && reg_eb4)
6109 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
6110 candidate, (reg_ec4 == 0));
6111
6112 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
6113 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
c7a5a190
JS		 6114
6115 rtl8xxxu_prepare_calibrate(priv, 0);
26f1fad2
JS		 6116}
6117
e1547c53
JS		 6118static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
6119{
6120 struct device *dev = &priv->udev->dev;
6121 int result[4][8]; /* last is final result */
6122 int i, candidate;
6123 bool path_a_ok, path_b_ok;
6124 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
6125 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
6126 u32 val32, bt_control;
6127 s32 reg_tmp = 0;
6128 bool simu;
6129
6130 rtl8xxxu_prepare_calibrate(priv, 1);
6131
6132 memset(result, 0, sizeof(result));
6133 candidate = -1;
6134
6135 path_a_ok = false;
6136 path_b_ok = false;
6137
6138 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
6139
6140 for (i = 0; i < 3; i++) {
6141 rtl8723bu_phy_iqcalibrate(priv, result, i);
6142
6143 if (i == 1) {
6144 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
6145 if (simu) {
6146 candidate = 0;
6147 break;
6148 }
6149 }
6150
6151 if (i == 2) {
6152 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
6153 if (simu) {
6154 candidate = 0;
6155 break;
6156 }
6157
6158 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
6159 if (simu) {
6160 candidate = 1;
6161 } else {
6162 for (i = 0; i < 8; i++)
6163 reg_tmp += result[3][i];
6164
6165 if (reg_tmp)
6166 candidate = 3;
6167 else
6168 candidate = -1;
6169 }
6170 }
6171 }
6172
6173 for (i = 0; i < 4; i++) {
6174 reg_e94 = result[i][0];
6175 reg_e9c = result[i][1];
6176 reg_ea4 = result[i][2];
6177 reg_eac = result[i][3];
6178 reg_eb4 = result[i][4];
6179 reg_ebc = result[i][5];
6180 reg_ec4 = result[i][6];
6181 reg_ecc = result[i][7];
6182 }
6183
6184 if (candidate >= 0) {
6185 reg_e94 = result[candidate][0];
6186 priv->rege94 = reg_e94;
6187 reg_e9c = result[candidate][1];
6188 priv->rege9c = reg_e9c;
6189 reg_ea4 = result[candidate][2];
6190 reg_eac = result[candidate][3];
6191 reg_eb4 = result[candidate][4];
6192 priv->regeb4 = reg_eb4;
6193 reg_ebc = result[candidate][5];
6194 priv->regebc = reg_ebc;
6195 reg_ec4 = result[candidate][6];
6196 reg_ecc = result[candidate][7];
6197 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
6198 dev_dbg(dev,
6199 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6200 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
6201 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
6202 path_a_ok = true;
6203 path_b_ok = true;
6204 } else {
6205 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
6206 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
6207 }
6208
6209 if (reg_e94 && candidate >= 0)
6210 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
6211 candidate, (reg_ea4 == 0));
6212
6213 if (priv->tx_paths > 1 && reg_eb4)
6214 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
6215 candidate, (reg_ec4 == 0));
6216
6217 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
6218 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
6219
6220 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
6221
6222 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
6223 val32 |= 0x80000;
6224 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
6225 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
6226 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
6227 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
6228 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
6229 val32 |= 0x20;
6230 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
6231 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
6232
15f9dc99
JS		 6233 if (priv->rf_paths > 1)
6234 dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__);
6235
e1547c53
JS		 6236 rtl8xxxu_prepare_calibrate(priv, 0);
6237}
6238
f991f4e9
JS		 6239static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
6240{
6241 struct device *dev = &priv->udev->dev;
6242 int result[4][8]; /* last is final result */
6243 int i, candidate;
6244 bool path_a_ok, path_b_ok;
6245 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
6246 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
6247 bool simu;
6248
6249 memset(result, 0, sizeof(result));
6250 candidate = -1;
6251
6252 path_a_ok = false;
6253 path_b_ok = false;
6254
6255 for (i = 0; i < 3; i++) {
6256 rtl8192eu_phy_iqcalibrate(priv, result, i);
6257
6258 if (i == 1) {
6259 simu = rtl8723bu_simularity_compare(priv, result, 0, 1);
6260 if (simu) {
6261 candidate = 0;
6262 break;
6263 }
6264 }
6265
6266 if (i == 2) {
6267 simu = rtl8723bu_simularity_compare(priv, result, 0, 2);
6268 if (simu) {
6269 candidate = 0;
6270 break;
6271 }
6272
6273 simu = rtl8723bu_simularity_compare(priv, result, 1, 2);
6274 if (simu)
6275 candidate = 1;
6276 else
6277 candidate = 3;
6278 }
6279 }
6280
6281 for (i = 0; i < 4; i++) {
6282 reg_e94 = result[i][0];
6283 reg_e9c = result[i][1];
6284 reg_ea4 = result[i][2];
6285 reg_eac = result[i][3];
6286 reg_eb4 = result[i][4];
6287 reg_ebc = result[i][5];
6288 reg_ec4 = result[i][6];
6289 reg_ecc = result[i][7];
6290 }
6291
6292 if (candidate >= 0) {
6293 reg_e94 = result[candidate][0];
6294 priv->rege94 = reg_e94;
6295 reg_e9c = result[candidate][1];
6296 priv->rege9c = reg_e9c;
6297 reg_ea4 = result[candidate][2];
6298 reg_eac = result[candidate][3];
6299 reg_eb4 = result[candidate][4];
6300 priv->regeb4 = reg_eb4;
6301 reg_ebc = result[candidate][5];
6302 priv->regebc = reg_ebc;
6303 reg_ec4 = result[candidate][6];
6304 reg_ecc = result[candidate][7];
6305 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
6306 dev_dbg(dev,
6307 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
6308 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
6309 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
6310 path_a_ok = true;
6311 path_b_ok = true;
6312 } else {
6313 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
6314 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
6315 }
6316
6317 if (reg_e94 && candidate >= 0)
6318 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
6319 candidate, (reg_ea4 == 0));
6320
6321 if (priv->rf_paths > 1)
6322 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
6323 candidate, (reg_ec4 == 0));
6324
6325 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
6326 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
6327}
6328
26f1fad2
JS		 6329static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
6330{
6331 u32 val32;
6332 u32 rf_amode, rf_bmode = 0, lstf;
6333
6334 /* Check continuous TX and Packet TX */
6335 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
6336
6337 if (lstf & OFDM_LSTF_MASK) {
6338 /* Disable all continuous TX */
6339 val32 = lstf & ~OFDM_LSTF_MASK;
6340 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
6341
6342 /* Read original RF mode Path A */
6343 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
6344
6345 /* Set RF mode to standby Path A */
6346 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
6347 (rf_amode & 0x8ffff) | 0x10000);
6348
6349 /* Path-B */
6350 if (priv->tx_paths > 1) {
6351 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
6352 RF6052_REG_AC);
6353
6354 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
6355 (rf_bmode & 0x8ffff) | 0x10000);
6356 }
6357 } else {
6358 /* Deal with Packet TX case */
6359 /* block all queues */
6360 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6361 }
6362
6363 /* Start LC calibration */
0d698dec
JS		 6364 if (priv->fops->has_s0s1)
6365 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
26f1fad2
JS		 6366 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
6367 val32 |= 0x08000;
6368 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
6369
6370 msleep(100);
6371
0d698dec
JS		 6372 if (priv->fops->has_s0s1)
6373 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
6374
26f1fad2
JS		 6375 /* Restore original parameters */
6376 if (lstf & OFDM_LSTF_MASK) {
6377 /* Path-A */
6378 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
6379 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
6380
6381 /* Path-B */
6382 if (priv->tx_paths > 1)
6383 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
6384 rf_bmode);
6385 } else /* Deal with Packet TX case */
6386 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
6387}
6388
6389static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
6390{
6391 int i;
6392 u16 reg;
6393
6394 reg = REG_MACID;
6395
6396 for (i = 0; i < ETH_ALEN; i++)
6397 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
6398
6399 return 0;
6400}
6401
6402static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
6403{
6404 int i;
6405 u16 reg;
6406
6407 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
6408
6409 reg = REG_BSSID;
6410
6411 for (i = 0; i < ETH_ALEN; i++)
6412 rtl8xxxu_write8(priv, reg + i, bssid[i]);
6413
6414 return 0;
6415}
6416
6417static void
6418rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
6419{
6420 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
6421 u8 max_agg = 0xf;
6422 int i;
6423
6424 ampdu_factor = 1 << (ampdu_factor + 2);
6425 if (ampdu_factor > max_agg)
6426 ampdu_factor = max_agg;
6427
6428 for (i = 0; i < 4; i++) {
6429 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
6430 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
6431
6432 if ((vals[i] & 0x0f) > ampdu_factor)
6433 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
6434
6435 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
6436 }
6437}
6438
6439static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
6440{
6441 u8 val8;
6442
6443 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
6444 val8 &= 0xf8;
6445 val8 |= density;
6446 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
6447}
6448
6449static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
6450{
6451 u8 val8;
37ba4b62 6452 int count, ret = 0;
26f1fad2
JS		 6453
6454 /* Start of rtl8723AU_card_enable_flow */
6455 /* Act to Cardemu sequence*/
6456 /* Turn off RF */
6457 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
6458
6459 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
6460 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6461 val8 &= ~LEDCFG2_DPDT_SELECT;
6462 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6463
6464 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
6465 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6466 val8 |= BIT(1);
6467 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6468
6469 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6470 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6471 if ((val8 & BIT(1)) == 0)
6472 break;
6473 udelay(10);
6474 }
6475
6476 if (!count) {
6477 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
6478 __func__);
6479 ret = -EBUSY;
6480 goto exit;
6481 }
6482
6483 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
6484 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6485 val8 |= SYS_ISO_ANALOG_IPS;
6486 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6487
6488 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
6489 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6490 val8 &= ~LDOA15_ENABLE;
6491 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6492
6493exit:
6494 return ret;
6495}
6496
fe37d5f6
JS		 6497static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
6498{
6499 u8 val8;
6500 u16 val16;
6501 u32 val32;
37ba4b62 6502 int count, ret = 0;
fe37d5f6
JS		 6503
6504 /* Turn off RF */
6505 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
6506
6507 /* Enable rising edge triggering interrupt */
6508 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
6509 val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
6510 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
6511
6512 /* Release WLON reset 0x04[16]= 1*/
8e254960 6513 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
fe37d5f6 6514 val32 |= APS_FSMCO_WLON_RESET;
8e254960 6515 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
fe37d5f6
JS		 6516
6517 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
6518 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6519 val8 |= BIT(1);
6520 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6521
6522 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6523 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6524 if ((val8 & BIT(1)) == 0)
6525 break;
6526 udelay(10);
6527 }
6528
6529 if (!count) {
6530 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
6531 __func__);
6532 ret = -EBUSY;
6533 goto exit;
6534 }
6535
6536 /* Enable BT control XTAL setting */
6537 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
6538 val8 &= ~AFE_MISC_WL_XTAL_CTRL;
6539 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
6540
6541 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
6542 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6543 val8 |= SYS_ISO_ANALOG_IPS;
6544 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6545
6546 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
6547 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6548 val8 &= ~LDOA15_ENABLE;
6549 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6550
6551exit:
6552 return ret;
6553}
6554
26f1fad2
JS		 6555static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
6556{
6557 u8 val8;
6558 u8 val32;
37ba4b62 6559 int count, ret = 0;
26f1fad2
JS		 6560
6561 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6562
6563 /*
6564 * Poll - wait for RX packet to complete
6565 */
6566 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6567 val32 = rtl8xxxu_read32(priv, 0x5f8);
6568 if (!val32)
6569 break;
6570 udelay(10);
6571 }
6572
6573 if (!count) {
6574 dev_warn(&priv->udev->dev,
6575 "%s: RX poll timed out (0x05f8)\n", __func__);
6576 ret = -EBUSY;
6577 goto exit;
6578 }
6579
6580 /* Disable CCK and OFDM, clock gated */
6581 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
6582 val8 &= ~SYS_FUNC_BBRSTB;
6583 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
6584
6585 udelay(2);
6586
6587 /* Reset baseband */
6588 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
6589 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
6590 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
6591
6592 /* Reset MAC TRX */
6593 val8 = rtl8xxxu_read8(priv, REG_CR);
6594 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
6595 rtl8xxxu_write8(priv, REG_CR, val8);
6596
6597 /* Reset MAC TRX */
6598 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
6599 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
6600 rtl8xxxu_write8(priv, REG_CR + 1, val8);
6601
6602 /* Respond TX OK to scheduler */
6603 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
6604 val8 |= DUAL_TSF_TX_OK;
6605 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
6606
6607exit:
6608 return ret;
6609}
6610
c05a9dbf 6611static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 6612{
6613 u8 val8;
6614
6615 /* Clear suspend enable and power down enable*/
6616 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6617 val8 &= ~(BIT(3) | BIT(7));
6618 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6619
6620 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
6621 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
6622 val8 &= ~BIT(0);
6623 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
6624
6625 /* 0x04[12:11] = 11 enable WL suspend*/
6626 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6627 val8 &= ~(BIT(3) | BIT(4));
6628 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6629}
6630
c05a9dbf
JS		 6631static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
6632{
6633 u8 val8;
6634
6635 /* Clear suspend enable and power down enable*/
6636 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6637 val8 &= ~(BIT(3) | BIT(4));
6638 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6639}
6640
6641static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
6642{
6643 u8 val8;
6644 u32 val32;
6645 int count, ret = 0;
6646
6647 /* disable HWPDN 0x04[15]=0*/
6648 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6649 val8 &= ~BIT(7);
6650 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6651
6652 /* disable SW LPS 0x04[10]= 0 */
6653 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6654 val8 &= ~BIT(2);
6655 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6656
6657 /* disable WL suspend*/
6658 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6659 val8 &= ~(BIT(3) | BIT(4));
6660 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6661
6662 /* wait till 0x04[17] = 1 power ready*/
6663 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6664 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6665 if (val32 & BIT(17))
6666 break;
6667
6668 udelay(10);
6669 }
6670
6671 if (!count) {
6672 ret = -EBUSY;
6673 goto exit;
6674 }
6675
6676 /* We should be able to optimize the following three entries into one */
6677
6678 /* release WLON reset 0x04[16]= 1*/
6679 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
6680 val8 |= BIT(0);
6681 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
6682
6683 /* set, then poll until 0 */
6684 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6685 val32 |= APS_FSMCO_MAC_ENABLE;
6686 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6687
6688 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6689 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6690 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
6691 ret = 0;
6692 break;
6693 }
6694 udelay(10);
6695 }
6696
6697 if (!count) {
6698 ret = -EBUSY;
6699 goto exit;
6700 }
6701
6702exit:
6703 return ret;
6704}
6705
6706static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 6707{
6708 u8 val8;
6709 u32 val32;
6710 int count, ret = 0;
6711
6712 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
6713 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6714 val8 |= LDOA15_ENABLE;
6715 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6716
6717 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
6718 val8 = rtl8xxxu_read8(priv, 0x0067);
6719 val8 &= ~BIT(4);
6720 rtl8xxxu_write8(priv, 0x0067, val8);
6721
6722 mdelay(1);
6723
6724 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
6725 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6726 val8 &= ~SYS_ISO_ANALOG_IPS;
6727 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6728
6729 /* disable SW LPS 0x04[10]= 0 */
6730 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6731 val8 &= ~BIT(2);
6732 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6733
6734 /* wait till 0x04[17] = 1 power ready*/
6735 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6736 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6737 if (val32 & BIT(17))
6738 break;
6739
6740 udelay(10);
6741 }
6742
6743 if (!count) {
6744 ret = -EBUSY;
6745 goto exit;
6746 }
6747
6748 /* We should be able to optimize the following three entries into one */
6749
6750 /* release WLON reset 0x04[16]= 1*/
6751 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
6752 val8 |= BIT(0);
6753 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
6754
6755 /* disable HWPDN 0x04[15]= 0*/
6756 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6757 val8 &= ~BIT(7);
6758 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6759
6760 /* disable WL suspend*/
6761 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6762 val8 &= ~(BIT(3) | BIT(4));
6763 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6764
6765 /* set, then poll until 0 */
6766 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6767 val32 |= APS_FSMCO_MAC_ENABLE;
6768 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6769
6770 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6771 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6772 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
6773 ret = 0;
6774 break;
6775 }
6776 udelay(10);
6777 }
6778
6779 if (!count) {
6780 ret = -EBUSY;
6781 goto exit;
6782 }
6783
6784 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
6785 /*
6786 * Note: Vendor driver actually clears this bit, despite the
6787 * documentation claims it's being set!
6788 */
6789 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
6790 val8 |= LEDCFG2_DPDT_SELECT;
6791 val8 &= ~LEDCFG2_DPDT_SELECT;
6792 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
6793
6794exit:
6795 return ret;
6796}
6797
42836db1
JS		 6798static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
6799{
6800 u8 val8;
6801 u32 val32;
6802 int count, ret = 0;
6803
6804 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
6805 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
6806 val8 |= LDOA15_ENABLE;
6807 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
6808
6809 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
6810 val8 = rtl8xxxu_read8(priv, 0x0067);
6811 val8 &= ~BIT(4);
6812 rtl8xxxu_write8(priv, 0x0067, val8);
6813
6814 mdelay(1);
6815
6816 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
6817 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
6818 val8 &= ~SYS_ISO_ANALOG_IPS;
6819 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
6820
6821 /* Disable SW LPS 0x04[10]= 0 */
6822 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
6823 val32 &= ~APS_FSMCO_SW_LPS;
6824 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6825
6826 /* Wait until 0x04[17] = 1 power ready */
6827 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6828 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6829 if (val32 & BIT(17))
6830 break;
6831
6832 udelay(10);
6833 }
6834
6835 if (!count) {
6836 ret = -EBUSY;
6837 goto exit;
6838 }
6839
6840 /* We should be able to optimize the following three entries into one */
6841
6842 /* Release WLON reset 0x04[16]= 1*/
6843 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6844 val32 |= APS_FSMCO_WLON_RESET;
6845 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6846
6847 /* Disable HWPDN 0x04[15]= 0*/
6848 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6849 val32 &= ~APS_FSMCO_HW_POWERDOWN;
6850 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6851
6852 /* Disable WL suspend*/
6853 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6854 val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
6855 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6856
6857 /* Set, then poll until 0 */
6858 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6859 val32 |= APS_FSMCO_MAC_ENABLE;
6860 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
6861
6862 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
6863 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
6864 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
6865 ret = 0;
6866 break;
6867 }
6868 udelay(10);
6869 }
6870
6871 if (!count) {
6872 ret = -EBUSY;
6873 goto exit;
6874 }
6875
6876 /* Enable WL control XTAL setting */
6877 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
6878 val8 |= AFE_MISC_WL_XTAL_CTRL;
6879 rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
6880
6881 /* Enable falling edge triggering interrupt */
6882 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
6883 val8 |= BIT(1);
6884 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
6885
6886 /* Enable GPIO9 interrupt mode */
6887 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
6888 val8 |= BIT(1);
6889 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
6890
6891 /* Enable GPIO9 input mode */
6892 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
6893 val8 &= ~BIT(1);
6894 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
6895
6896 /* Enable HSISR GPIO[C:0] interrupt */
6897 val8 = rtl8xxxu_read8(priv, REG_HSIMR);
6898 val8 |= BIT(0);
6899 rtl8xxxu_write8(priv, REG_HSIMR, val8);
6900
6901 /* Enable HSISR GPIO9 interrupt */
6902 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
6903 val8 |= BIT(1);
6904 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
6905
6906 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
6907 val8 |= MULTI_WIFI_HW_ROF_EN;
6908 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
6909
6910 /* For GPIO9 internal pull high setting BIT(14) */
6911 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
6912 val8 |= BIT(6);
6913 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
6914
6915exit:
6916 return ret;
6917}
6918
26f1fad2
JS		 6919static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
6920{
6921 u8 val8;
6922
6923 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
6924 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
6925
6926 /* 0x04[12:11] = 01 enable WL suspend */
6927 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6928 val8 &= ~BIT(4);
6929 val8 |= BIT(3);
6930 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6931
6932 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
6933 val8 |= BIT(7);
6934 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
6935
6936 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
6937 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
6938 val8 |= BIT(0);
6939 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
6940
6941 return 0;
6942}
6943
430b454c
JS		 6944static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
6945{
145428ec 6946 struct device *dev = &priv->udev->dev;
430b454c
JS		 6947 u32 val32;
6948 int retry, retval;
6949
6950 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
6951
6952 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
6953 val32 |= RXPKT_NUM_RW_RELEASE_EN;
6954 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
6955
6956 retry = 100;
6957 retval = -EBUSY;
6958
6959 do {
6960 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
6961 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
6962 retval = 0;
6963 break;
6964 }
6965 } while (retry--);
6966
6967 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
6968 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
6969 mdelay(2);
145428ec
JS		 6970
6971 if (!retry)
6972 dev_warn(dev, "Failed to flush FIFO\n");
430b454c
JS		 6973
6974 return retval;
6975}
6976
747bf237
JS		 6977static void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
6978{
6979 /* Fix USB interface interference issue */
6980 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6981 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
6982 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6983 /*
6984 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
6985 * 8 and 5, for which I have found no documentation.
6986 */
6987 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
6988
6989 /*
6990 * Solve too many protocol error on USB bus.
6991 * Can't do this for 8188/8192 UMC A cut parts
6992 */
6993 if (!(!priv->chip_cut && priv->vendor_umc)) {
6994 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
6995 rtl8xxxu_write8(priv, 0xfe41, 0x94);
6996 rtl8xxxu_write8(priv, 0xfe42, 0x80);
6997
6998 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
6999 rtl8xxxu_write8(priv, 0xfe41, 0x19);
7000 rtl8xxxu_write8(priv, 0xfe42, 0x80);
7001
7002 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
7003 rtl8xxxu_write8(priv, 0xfe41, 0x91);
7004 rtl8xxxu_write8(priv, 0xfe42, 0x80);
7005
7006 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
7007 rtl8xxxu_write8(priv, 0xfe41, 0x81);
7008 rtl8xxxu_write8(priv, 0xfe42, 0x80);
7009 }
7010}
7011
7012static void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
7013{
7014 u32 val32;
7015
7016 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
7017 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
7018 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
7019}
7020
26f1fad2
JS		 7021static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
7022{
7023 u8 val8;
7024 u16 val16;
7025 u32 val32;
7026 int ret;
7027
7028 /*
7029 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
7030 */
7031 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
7032
c05a9dbf 7033 rtl8723a_disabled_to_emu(priv);
26f1fad2 7034
c05a9dbf 7035 ret = rtl8723a_emu_to_active(priv);
26f1fad2
JS		 7036 if (ret)
7037 goto exit;
7038
7039 /*
7040 * 0x0004[19] = 1, reset 8051
7041 */
7042 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
7043 val8 |= BIT(3);
7044 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
7045
7046 /*
7047 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7048 * Set CR bit10 to enable 32k calibration.
7049 */
7050 val16 = rtl8xxxu_read16(priv, REG_CR);
7051 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
7052 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
7053 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
7054 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
7055 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
7056 rtl8xxxu_write16(priv, REG_CR, val16);
7057
7058 /* For EFuse PG */
7059 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
7060 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
7061 val32 |= (0x06 << 28);
7062 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
7063exit:
7064 return ret;
7065}
7066
42836db1
JS		 7067static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
7068{
7069 u8 val8;
7070 u16 val16;
7071 u32 val32;
7072 int ret;
7073
7074 rtl8723a_disabled_to_emu(priv);
7075
7076 ret = rtl8723b_emu_to_active(priv);
7077 if (ret)
7078 goto exit;
7079
7080 /*
7081 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7082 * Set CR bit10 to enable 32k calibration.
7083 */
7084 val16 = rtl8xxxu_read16(priv, REG_CR);
7085 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
7086 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
7087 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
7088 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
7089 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
7090 rtl8xxxu_write16(priv, REG_CR, val16);
7091
7092 /*
7093 * BT coexist power on settings. This is identical for 1 and 2
7094 * antenna parts.
7095 */
7096 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
7097
7098 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
7099 val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
7100 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
7101
7102 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
7103 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
7104 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
7105 /* Antenna inverse */
7106 rtl8xxxu_write8(priv, 0xfe08, 0x01);
7107
7108 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
7109 val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
7110 rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
7111
7112 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
7113 val32 |= LEDCFG0_DPDT_SELECT;
7114 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
7115
7116 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
7117 val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
7118 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
7119exit:
7120 return ret;
7121}
7122
c0963772
KV		 7123#ifdef CONFIG_RTL8XXXU_UNTESTED
7124
26f1fad2
JS		 7125static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
7126{
7127 u8 val8;
7128 u16 val16;
7129 u32 val32;
7130 int i;
7131
7132 for (i = 100; i; i--) {
7133 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
7134 if (val8 & APS_FSMCO_PFM_ALDN)
7135 break;
7136 }
7137
7138 if (!i) {
7139 pr_info("%s: Poll failed\n", __func__);
7140 return -ENODEV;
7141 }
7142
7143 /*
7144 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
7145 */
7146 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
7147 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
7148 udelay(100);
7149
7150 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
7151 if (!(val8 & LDOV12D_ENABLE)) {
7152 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
7153 val8 |= LDOV12D_ENABLE;
7154 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
7155
7156 udelay(100);
7157
7158 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
7159 val8 &= ~SYS_ISO_MD2PP;
7160 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
7161 }
7162
7163 /*
7164 * Auto enable WLAN
7165 */
7166 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
7167 val16 |= APS_FSMCO_MAC_ENABLE;
7168 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
7169
7170 for (i = 1000; i; i--) {
7171 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
7172 if (!(val16 & APS_FSMCO_MAC_ENABLE))
7173 break;
7174 }
7175 if (!i) {
7176 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
7177 return -EBUSY;
7178 }
7179
7180 /*
7181 * Enable radio, GPIO, LED
7182 */
7183 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
7184 APS_FSMCO_PFM_ALDN;
7185 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
7186
7187 /*
7188 * Release RF digital isolation
7189 */
7190 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
7191 val16 &= ~SYS_ISO_DIOR;
7192 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
7193
7194 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
7195 val8 &= ~APSD_CTRL_OFF;
7196 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
7197 for (i = 200; i; i--) {
7198 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
7199 if (!(val8 & APSD_CTRL_OFF_STATUS))
7200 break;
7201 }
7202
7203 if (!i) {
7204 pr_info("%s: APSD_CTRL poll failed\n", __func__);
7205 return -EBUSY;
7206 }
7207
7208 /*
7209 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7210 */
7211 val16 = rtl8xxxu_read16(priv, REG_CR);
7212 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
7213 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
7214 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
7215 rtl8xxxu_write16(priv, REG_CR, val16);
7216
b9f9d699
JS		 7217 rtl8xxxu_write8(priv, 0xfe10, 0x19);
7218
26f1fad2
JS		 7219 /*
7220 * Workaround for 8188RU LNA power leakage problem.
7221 */
8d95c808 7222 if (priv->rtl_chip == RTL8188R) {
26f1fad2
JS		 7223 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
7224 val32 &= ~BIT(1);
7225 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
7226 }
7227 return 0;
7228}
7229
c0963772
KV		 7230#endif
7231
28e460b0
JS		 7232/*
7233 * This is needed for 8723bu as well, presumable
7234 */
7235static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)
7236{
7237 u8 val8;
7238 u32 val32;
7239
7240 /*
7241 * 40Mhz crystal source, MAC 0x28[2]=0
7242 */
7243 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
7244 val8 &= 0xfb;
7245 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
7246
7247 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
7248 val32 &= 0xfffffc7f;
7249 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
7250
7251 /*
7252 * 92e AFE parameter
7253 * AFE PLL KVCO selection, MAC 0x28[6]=1
7254 */
7255 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
7256 val8 &= 0xbf;
7257 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
7258
7259 /*
7260 * AFE PLL KVCO selection, MAC 0x78[21]=0
7261 */
7262 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
7263 val32 &= 0xffdfffff;
7264 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
7265}
7266
c05a9dbf
JS		 7267static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
7268{
7269 u16 val16;
7270 u32 val32;
7271 int ret;
7272
7273 ret = 0;
7274
7275 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
7276 if (val32 & SYS_CFG_SPS_LDO_SEL) {
7277 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
7278 } else {
7279 /*
7280 * Raise 1.2V voltage
7281 */
7282 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
7283 val32 &= 0xff0fffff;
7284 val32 |= 0x00500000;
7285 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
7286 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
7287 }
7288
28e460b0
JS		 7289 /*
7290 * Adjust AFE before enabling PLL
7291 */
7292 rtl8192e_crystal_afe_adjust(priv);
c05a9dbf
JS		 7293 rtl8192e_disabled_to_emu(priv);
7294
7295 ret = rtl8192e_emu_to_active(priv);
7296 if (ret)
7297 goto exit;
7298
7299 rtl8xxxu_write16(priv, REG_CR, 0x0000);
7300
7301 /*
7302 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
7303 * Set CR bit10 to enable 32k calibration.
7304 */
7305 val16 = rtl8xxxu_read16(priv, REG_CR);
7306 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
7307 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
7308 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
7309 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
7310 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
7311 rtl8xxxu_write16(priv, REG_CR, val16);
7312
7313exit:
7314 return ret;
7315}
7316
26f1fad2
JS		 7317static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
7318{
7319 u8 val8;
7320 u16 val16;
7321 u32 val32;
7322
7323 /*
7324 * Workaround for 8188RU LNA power leakage problem.
7325 */
8d95c808 7326 if (priv->rtl_chip == RTL8188R) {
26f1fad2
JS		 7327 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
7328 val32 |= BIT(1);
7329 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
7330 }
7331
430b454c
JS		 7332 rtl8xxxu_flush_fifo(priv);
7333
26f1fad2
JS		 7334 rtl8xxxu_active_to_lps(priv);
7335
7336 /* Turn off RF */
7337 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
7338
7339 /* Reset Firmware if running in RAM */
7340 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
7341 rtl8xxxu_firmware_self_reset(priv);
7342
7343 /* Reset MCU */
7344 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
7345 val16 &= ~SYS_FUNC_CPU_ENABLE;
7346 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
7347
7348 /* Reset MCU ready status */
7349 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
7350
7351 rtl8xxxu_active_to_emu(priv);
7352 rtl8xxxu_emu_to_disabled(priv);
7353
7354 /* Reset MCU IO Wrapper */
7355 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
7356 val8 &= ~BIT(0);
7357 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7358
7359 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
7360 val8 |= BIT(0);
7361 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7362
7363 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
7364 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
7365}
7366
fe37d5f6
JS		 7367static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
7368{
7369 u8 val8;
7370 u16 val16;
7371
430b454c
JS		 7372 rtl8xxxu_flush_fifo(priv);
7373
fe37d5f6
JS		 7374 /*
7375 * Disable TX report timer
7376 */
7377 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
7378 val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
7379 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
7380
8e254960 7381 rtl8xxxu_write8(priv, REG_CR, 0x0000);
fe37d5f6
JS		 7382
7383 rtl8xxxu_active_to_lps(priv);
7384
7385 /* Reset Firmware if running in RAM */
7386 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
7387 rtl8xxxu_firmware_self_reset(priv);
7388
7389 /* Reset MCU */
7390 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
7391 val16 &= ~SYS_FUNC_CPU_ENABLE;
7392 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
7393
7394 /* Reset MCU ready status */
7395 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
7396
7397 rtl8723bu_active_to_emu(priv);
8e254960
JS		 7398
7399 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
7400 val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */
7401 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
7402
7403 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
7404 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
7405 val8 |= BIT(0);
7406 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
fe37d5f6
JS		 7407}
7408
a3a5dac6 7409#ifdef NEED_PS_TDMA
3ca7b32c
JS		 7410static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
7411 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
7412{
7413 struct h2c_cmd h2c;
7414
7415 memset(&h2c, 0, sizeof(struct h2c_cmd));
7416 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
7417 h2c.b_type_dma.data1 = arg1;
7418 h2c.b_type_dma.data2 = arg2;
7419 h2c.b_type_dma.data3 = arg3;
7420 h2c.b_type_dma.data4 = arg4;
7421 h2c.b_type_dma.data5 = arg5;
7422 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
7423}
a3a5dac6 7424#endif
3ca7b32c 7425
0290e7d0 7426static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
26f1fad2 7427{
f37e9228
JS		 7428 struct h2c_cmd h2c;
7429 u32 val32;
7430 u8 val8;
7431
7432 /*
7433 * No indication anywhere as to what 0x0790 does. The 2 antenna
7434 * vendor code preserves bits 6-7 here.
7435 */
7436 rtl8xxxu_write8(priv, 0x0790, 0x05);
7437 /*
7438 * 0x0778 seems to be related to enabling the number of antennas
7439 * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
7440 * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
7441 */
7442 rtl8xxxu_write8(priv, 0x0778, 0x01);
7443
7444 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
7445 val8 |= BIT(5);
7446 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
7447
7448 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
7449
394f1bd3
JS		 7450 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
7451
f37e9228
JS		 7452 /*
7453 * Set BT grant to low
7454 */
7455 memset(&h2c, 0, sizeof(struct h2c_cmd));
7456 h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
7457 h2c.bt_grant.data = 0;
7458 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
7459
7460 /*
7461 * WLAN action by PTA
7462 */
fc1c89b3 7463 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
f37e9228
JS		 7464
7465 /*
7466 * BT select S0/S1 controlled by WiFi
7467 */
7468 val8 = rtl8xxxu_read8(priv, 0x0067);
7469 val8 |= BIT(5);
7470 rtl8xxxu_write8(priv, 0x0067, val8);
7471
7472 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
37f44dc7 7473 val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
f37e9228
JS		 7474 rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
7475
7476 /*
7477 * Bits 6/7 are marked in/out ... but for what?
7478 */
7479 rtl8xxxu_write8(priv, 0x0974, 0xff);
7480
120e627f 7481 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
f37e9228 7482 val32 |= (BIT(0) | BIT(1));
120e627f 7483 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
f37e9228
JS		 7484
7485 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
7486
7487 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
7488 val32 &= ~BIT(24);
7489 val32 |= BIT(23);
7490 rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
7491
7492 /*
7493 * Fix external switch Main->S1, Aux->S0
7494 */
7495 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
7496 val8 &= ~BIT(0);
7497 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
7498
7499 memset(&h2c, 0, sizeof(struct h2c_cmd));
7500 h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
7501 h2c.ant_sel_rsv.ant_inverse = 1;
7502 h2c.ant_sel_rsv.int_switch_type = 0;
7503 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
7504
7505 /*
7506 * 0x280, 0x00, 0x200, 0x80 - not clear
7507 */
3ca7b32c
JS		 7508 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
7509
7510 /*
7511 * Software control, antenna at WiFi side
7512 */
a3a5dac6 7513#ifdef NEED_PS_TDMA
a228a5db 7514 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
a3a5dac6
JS		 7515#endif
7516
7517 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
7518 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
7519 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
7520 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
3ca7b32c 7521
6b9eae01
JS		 7522 memset(&h2c, 0, sizeof(struct h2c_cmd));
7523 h2c.bt_info.cmd = H2C_8723B_BT_INFO;
7524 h2c.bt_info.data = BIT(0);
7525 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
7526
6b9eae01
JS		 7527 memset(&h2c, 0, sizeof(struct h2c_cmd));
7528 h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
7529 h2c.ignore_wlan.data = 0;
7530 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
26f1fad2
JS		 7531}
7532
fc89a41f
JS		 7533static void rtl8723b_disable_rf(struct rtl8xxxu_priv *priv)
7534{
7535 u32 val32;
7536
7537 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7538
7539 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
7540 val32 &= ~(BIT(22) | BIT(23));
7541 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
7542}
7543
3e88ca44
JS		 7544static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
7545{
7546 u32 agg_rx;
7547 u8 agg_ctrl;
7548
7549 /*
7550 * For now simply disable RX aggregation
7551 */
7552 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
7553 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
7554
7555 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
7556 agg_rx &= ~RXDMA_USB_AGG_ENABLE;
7557 agg_rx &= ~0xff0f;
7558
7559 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
7560 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
7561}
7562
9c79bf95
JS		 7563static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
7564{
7565 u32 val32;
7566
7567 /* Time duration for NHM unit: 4us, 0x2710=40ms */
7568 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
7569 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
7570 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
7571 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
7572 /* TH8 */
7573 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
7574 val32 |= 0xff;
7575 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
7576 /* Enable CCK */
7577 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
7578 val32 |= BIT(8) | BIT(9) | BIT(10);
7579 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
7580 /* Max power amongst all RX antennas */
7581 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
7582 val32 |= BIT(7);
7583 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
7584}
7585
89c2a097
JS		 7586static void rtl8xxxu_old_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
7587{
7588 u8 val8;
7589 u32 val32;
7590
7591 if (priv->ep_tx_normal_queue)
7592 val8 = TX_PAGE_NUM_NORM_PQ;
7593 else
7594 val8 = 0;
7595
7596 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
7597
7598 val32 = (TX_PAGE_NUM_PUBQ << RQPN_PUB_PQ_SHIFT) | RQPN_LOAD;
7599
7600 if (priv->ep_tx_high_queue)
7601 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
7602 if (priv->ep_tx_low_queue)
7603 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
7604
7605 rtl8xxxu_write32(priv, REG_RQPN, val32);
7606}
7607
7608static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
7609{
7610 struct rtl8xxxu_fileops *fops = priv->fops;
7611 u32 hq, lq, nq, eq, pubq;
7612 u32 val32;
7613
7614 hq = 0;
7615 lq = 0;
7616 nq = 0;
7617 eq = 0;
7618 pubq = 0;
7619
7620 if (priv->ep_tx_high_queue)
7621 hq = fops->page_num_hi;
7622 if (priv->ep_tx_low_queue)
7623 lq = fops->page_num_lo;
7624 if (priv->ep_tx_normal_queue)
7625 nq = fops->page_num_norm;
7626
7627 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
7628 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
7629
7630 pubq = fops->total_page_num - hq - lq - nq;
7631
7632 val32 = RQPN_LOAD;
7633 val32 |= (hq << RQPN_HI_PQ_SHIFT);
7634 val32 |= (lq << RQPN_LO_PQ_SHIFT);
7635 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
7636
7637 rtl8xxxu_write32(priv, REG_RQPN, val32);
7638}
7639
26f1fad2
JS		 7640static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
7641{
7642 struct rtl8xxxu_priv *priv = hw->priv;
7643 struct device *dev = &priv->udev->dev;
26f1fad2
JS		 7644 bool macpower;
7645 int ret;
7646 u8 val8;
7647 u16 val16;
7648 u32 val32;
7649
7650 /* Check if MAC is already powered on */
7651 val8 = rtl8xxxu_read8(priv, REG_CR);
7652
7653 /*
7654 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
7655 * initialized. First MAC returns 0xea, second MAC returns 0x00
7656 */
7657 if (val8 == 0xea)
7658 macpower = false;
7659 else
7660 macpower = true;
7661
7662 ret = priv->fops->power_on(priv);
7663 if (ret < 0) {
7664 dev_warn(dev, "%s: Failed power on\n", __func__);
7665 goto exit;
7666 }
7667
07bb46be 7668 if (!macpower) {
89c2a097
JS		 7669 if (priv->fops->total_page_num)
7670 rtl8xxxu_init_queue_reserved_page(priv);
59b24dad 7671 else
89c2a097 7672 rtl8xxxu_old_init_queue_reserved_page(priv);
07bb46be
JS		 7673 }
7674
59b24dad
JS		 7675 ret = rtl8xxxu_init_queue_priority(priv);
7676 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
7677 if (ret)
7678 goto exit;
7679
7680 /*
7681 * Set RX page boundary
7682 */
24e8e7ec 7683 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, priv->fops->trxff_boundary);
59b24dad 7684
a47b9d47
JS		 7685 ret = rtl8xxxu_download_firmware(priv);
7686 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
7687 if (ret)
7688 goto exit;
7689 ret = rtl8xxxu_start_firmware(priv);
7690 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
7691 if (ret)
7692 goto exit;
7693
f0d9f5e9
JS		 7694 if (priv->fops->phy_init_antenna_selection)
7695 priv->fops->phy_init_antenna_selection(priv);
7696
c606e662 7697 ret = rtl8xxxu_init_mac(priv);
b7dd8ff9 7698
26f1fad2
JS		 7699 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
7700 if (ret)
7701 goto exit;
7702
7703 ret = rtl8xxxu_init_phy_bb(priv);
7704 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
7705 if (ret)
7706 goto exit;
7707
4062b8ff 7708 ret = priv->fops->init_phy_rf(priv);
26f1fad2
JS		 7709 if (ret)
7710 goto exit;
7711
c157863d 7712 /* RFSW Control - clear bit 14 ?? */
b816901b 7713 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
c157863d 7714 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
31133da7
JS		 7715
7716 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
7717 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
7718 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
7719 FPGA0_RF_BD_CTRL_SHIFT);
7720
c157863d
JS		 7721 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
7722 /* 0x860[6:5]= 00 - why? - this sets antenna B */
7723 if (priv->rtl_chip != RTL8192E)
7724 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
7725
f2a4163a 7726 if (!macpower) {
1f1b20f1
JS		 7727 /*
7728 * Set TX buffer boundary
7729 */
80805aa5
JS		 7730 if (priv->rtl_chip == RTL8192E)
7731 val8 = TX_TOTAL_PAGE_NUM_8192E + 1;
7732 else
7733 val8 = TX_TOTAL_PAGE_NUM + 1;
1f1b20f1 7734
ba17d824 7735 if (priv->rtl_chip == RTL8723B)
1f1b20f1
JS		 7736 val8 -= 1;
7737
7738 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
7739 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
7740 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
7741 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
7742 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
7743 }
7744
26f1fad2 7745 /*
9b323ee9
JS		 7746 * The vendor drivers set PBP for all devices, except 8192e.
7747 * There is no explanation for this in any of the sources.
26f1fad2 7748 */
9b323ee9
JS		 7749 val8 = (priv->fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
7750 (priv->fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
2e7c7b34
JS		 7751 if (priv->rtl_chip != RTL8192E)
7752 rtl8xxxu_write8(priv, REG_PBP, val8);
26f1fad2 7753
59b24dad
JS		 7754 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
7755 if (!macpower) {
7756 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
7757 if (ret) {
7758 dev_warn(dev, "%s: LLT table init failed\n", __func__);
7759 goto exit;
7760 }
7761
0486e80b
JS		 7762 /*
7763 * Chip specific quirks
7764 */
747bf237 7765 priv->fops->usb_quirks(priv);
0486e80b 7766
59b24dad
JS		 7767 /*
7768 * Presumably this is for 8188EU as well
7769 * Enable TX report and TX report timer
7770 */
7771 if (priv->rtl_chip == RTL8723B) {
7772 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
7773 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
7774 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
7775 /* Set MAX RPT MACID */
7776 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
7777 /* TX report Timer. Unit: 32us */
7778 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
7779
7780 /* tmp ps ? */
7781 val8 = rtl8xxxu_read8(priv, 0xa3);
7782 val8 &= 0xf8;
7783 rtl8xxxu_write8(priv, 0xa3, val8);
7784 }
7785 }
7786
26f1fad2
JS		 7787 /*
7788 * Unit in 8 bytes, not obvious what it is used for
7789 */
7790 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
7791
57e5e2e6
JS		 7792 if (priv->rtl_chip == RTL8192E) {
7793 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
7794 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
7795 } else {
7796 /*
7797 * Enable all interrupts - not obvious USB needs to do this
7798 */
7799 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
7800 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
7801 }
26f1fad2
JS		 7802
7803 rtl8xxxu_set_mac(priv);
7804 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
7805
7806 /*
7807 * Configure initial WMAC settings
7808 */
7809 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
26f1fad2
JS		 7810 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
7811 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
7812 rtl8xxxu_write32(priv, REG_RCR, val32);
7813
7814 /*
7815 * Accept all multicast
7816 */
7817 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
7818 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
7819
7820 /*
7821 * Init adaptive controls
7822 */
7823 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
7824 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
7825 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
7826 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
7827
7828 /* CCK = 0x0a, OFDM = 0x10 */
7829 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
7830 rtl8xxxu_set_retry(priv, 0x30, 0x30);
7831 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
7832
7833 /*
7834 * Init EDCA
7835 */
7836 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
7837
7838 /* Set CCK SIFS */
7839 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
7840
7841 /* Set OFDM SIFS */
7842 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
7843
7844 /* TXOP */
7845 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
7846 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
7847 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
7848 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
7849
7850 /* Set data auto rate fallback retry count */
7851 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
7852 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
7853 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
7854 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
7855
7856 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
7857 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
7858 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
7859
7860 /* Set ACK timeout */
7861 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
7862
7863 /*
7864 * Initialize beacon parameters
7865 */
7866 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
7867 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
7868 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
7869 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
7870 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
7871 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
7872
c3690604
JS		 7873 /*
7874 * Initialize burst parameters
7875 */
ba17d824 7876 if (priv->rtl_chip == RTL8723B) {
c3690604
JS		 7877 /*
7878 * For USB high speed set 512B packets
7879 */
7880 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
7881 val8 &= ~(BIT(4) | BIT(5));
7882 val8 |= BIT(4);
7883 val8 |= BIT(1) | BIT(2) | BIT(3);
7884 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
7885
7886 /*
7887 * For USB high speed set 512B packets
7888 */
7889 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
7890 val8 |= BIT(7);
7891 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
7892
7893 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
7894 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
7895 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
7896 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
7897 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
7898 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
7899 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
7900
7901 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
7902 val8 |= BIT(5) | BIT(6);
7903 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
7904 }
7905
3e88ca44
JS		 7906 if (priv->fops->init_aggregation)
7907 priv->fops->init_aggregation(priv);
7908
26f1fad2
JS		 7909 /*
7910 * Enable CCK and OFDM block
7911 */
7912 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
7913 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
7914 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
7915
7916 /*
7917 * Invalidate all CAM entries - bit 30 is undocumented
7918 */
7919 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
7920
7921 /*
7922 * Start out with default power levels for channel 6, 20MHz
7923 */
e796dab4 7924 priv->fops->set_tx_power(priv, 1, false);
26f1fad2
JS		 7925
7926 /* Let the 8051 take control of antenna setting */
5bdb6b08
JS		 7927 if (priv->rtl_chip != RTL8192E) {
7928 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
7929 val8 |= LEDCFG2_DPDT_SELECT;
7930 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
7931 }
26f1fad2
JS		 7932
7933 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
7934
7935 /* Disable BAR - not sure if this has any effect on USB */
7936 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
7937
7938 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
7939
9c79bf95
JS		 7940 if (priv->fops->init_statistics)
7941 priv->fops->init_statistics(priv);
7942
b052b7fc
JS		 7943 if (priv->rtl_chip == RTL8192E) {
7944 /*
7945 * 0x4c6[3] 1: RTS BW = Data BW
7946 * 0: RTS BW depends on CCA / secondary CCA result.
7947 */
7948 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
7949 val8 &= ~BIT(3);
7950 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
7951 /*
7952 * Reset USB mode switch setting
7953 */
7954 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
7955 }
7956
fa0f2d48
JS		 7957 rtl8723a_phy_lc_calibrate(priv);
7958
e1547c53 7959 priv->fops->phy_iq_calibrate(priv);
26f1fad2
JS		 7960
7961 /*
7962 * This should enable thermal meter
7963 */
55c0b6ae 7964 if (priv->fops->tx_desc_size == sizeof(struct rtl8xxxu_txdesc40))
72143b9e
JS		 7965 rtl8xxxu_write_rfreg(priv,
7966 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
7967 else
7968 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
26f1fad2 7969
26f1fad2
JS		 7970 /* Set NAV_UPPER to 30000us */
7971 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
7972 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
7973
ba17d824 7974 if (priv->rtl_chip == RTL8723A) {
4042e617
JS		 7975 /*
7976 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
7977 * but we need to find root cause.
7978 * This is 8723au only.
7979 */
7980 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
7981 if ((val32 & 0xff000000) != 0x83000000) {
7982 val32 |= FPGA_RF_MODE_CCK;
7983 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
7984 }
3021e51f
JS		 7985 } else if (priv->rtl_chip == RTL8192E) {
7986 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
26f1fad2
JS		 7987 }
7988
7989 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
7990 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
7991 /* ack for xmit mgmt frames. */
7992 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
7993
e1394fe5
JS		 7994 if (priv->rtl_chip == RTL8192E) {
7995 /*
7996 * Fix LDPC rx hang issue.
7997 */
7998 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
7999 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
8000 val32 &= 0xfff00fff;
8001 val32 |= 0x0007e000;
46b37831 8002 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
e1394fe5 8003 }
26f1fad2
JS		 8004exit:
8005 return ret;
8006}
8007
26f1fad2
JS		 8008static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
8009 struct ieee80211_key_conf *key, const u8 *mac)
8010{
8011 u32 cmd, val32, addr, ctrl;
8012 int j, i, tmp_debug;
8013
8014 tmp_debug = rtl8xxxu_debug;
8015 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
8016 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
8017
8018 /*
8019 * This is a bit of a hack - the lower bits of the cipher
8020 * suite selector happens to match the cipher index in the CAM
8021 */
8022 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
8023 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
8024
8025 for (j = 5; j >= 0; j--) {
8026 switch (j) {
8027 case 0:
8028 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
8029 break;
8030 case 1:
8031 val32 = mac[2] | (mac[3] << 8) |
8032 (mac[4] << 16) | (mac[5] << 24);
8033 break;
8034 default:
8035 i = (j - 2) << 2;
8036 val32 = key->key[i] | (key->key[i + 1] << 8) |
8037 key->key[i + 2] << 16 | key->key[i + 3] << 24;
8038 break;
8039 }
8040
8041 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
8042 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
8043 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
8044 udelay(100);
8045 }
8046
8047 rtl8xxxu_debug = tmp_debug;
8048}
8049
8050static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
56e4374a 8051 struct ieee80211_vif *vif, const u8 *mac)
26f1fad2
JS		 8052{
8053 struct rtl8xxxu_priv *priv = hw->priv;
8054 u8 val8;
8055
8056 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
8057 val8 |= BEACON_DISABLE_TSF_UPDATE;
8058 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
8059}
8060
8061static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
8062 struct ieee80211_vif *vif)
8063{
8064 struct rtl8xxxu_priv *priv = hw->priv;
8065 u8 val8;
8066
8067 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
8068 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
8069 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
8070}
8071
f653e690
JS		 8072static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv *priv,
8073 u32 ramask, int sgi)
26f1fad2
JS		 8074{
8075 struct h2c_cmd h2c;
8076
f653e690
JS		 8077 memset(&h2c, 0, sizeof(struct h2c_cmd));
8078
26f1fad2
JS		 8079 h2c.ramask.cmd = H2C_SET_RATE_MASK;
8080 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
8081 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
8082
8083 h2c.ramask.arg = 0x80;
8084 if (sgi)
8085 h2c.ramask.arg |= 0x20;
8086
7ff8c1ae 8087 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
8da91571
JS		 8088 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
8089 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
26f1fad2
JS		 8090}
8091
f653e690
JS		 8092static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv *priv,
8093 u32 ramask, int sgi)
8094{
8095 struct h2c_cmd h2c;
8096 u8 bw = 0;
8097
8098 memset(&h2c, 0, sizeof(struct h2c_cmd));
8099
8100 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
8101 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
8102 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
8103 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
8104 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
8105
8106 h2c.ramask.arg = 0x80;
8107 h2c.b_macid_cfg.data1 = 0;
8108 if (sgi)
8109 h2c.b_macid_cfg.data1 |= BIT(7);
8110
8111 h2c.b_macid_cfg.data2 = bw;
8112
8113 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
8114 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
8115 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
8116}
8117
7d794eaa
JS		 8118static void rtl8723au_report_connect(struct rtl8xxxu_priv *priv,
8119 u8 macid, bool connect)
8120{
8121 struct h2c_cmd h2c;
8122
8123 memset(&h2c, 0, sizeof(struct h2c_cmd));
8124
8125 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
8126
8127 if (connect)
8128 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
8129 else
8130 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
8131
8132 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
8133}
8134
8135static void rtl8723bu_report_connect(struct rtl8xxxu_priv *priv,
8136 u8 macid, bool connect)
8137{
8138 struct h2c_cmd h2c;
8139
8140 memset(&h2c, 0, sizeof(struct h2c_cmd));
8141
8142 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
8143 if (connect)
8144 h2c.media_status_rpt.parm |= BIT(0);
8145 else
8146 h2c.media_status_rpt.parm &= ~BIT(0);
8147
8148 rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
8149}
8150
26f1fad2
JS		 8151static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
8152{
8153 u32 val32;
8154 u8 rate_idx = 0;
8155
8156 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
8157
8158 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
8159 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
8160 val32 |= rate_cfg;
8161 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
8162
8163 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
8164
8165 while (rate_cfg) {
8166 rate_cfg = (rate_cfg >> 1);
8167 rate_idx++;
8168 }
8169 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
8170}
8171
8172static void
8173rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
8174 struct ieee80211_bss_conf *bss_conf, u32 changed)
8175{
8176 struct rtl8xxxu_priv *priv = hw->priv;
8177 struct device *dev = &priv->udev->dev;
8178 struct ieee80211_sta *sta;
8179 u32 val32;
8180 u8 val8;
8181
8182 if (changed & BSS_CHANGED_ASSOC) {
26f1fad2
JS		 8183 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
8184
26f1fad2
JS		 8185 rtl8xxxu_set_linktype(priv, vif->type);
8186
8187 if (bss_conf->assoc) {
8188 u32 ramask;
8189 int sgi = 0;
8190
8191 rcu_read_lock();
8192 sta = ieee80211_find_sta(vif, bss_conf->bssid);
8193 if (!sta) {
8194 dev_info(dev, "%s: ASSOC no sta found\n",
8195 __func__);
8196 rcu_read_unlock();
8197 goto error;
8198 }
8199
8200 if (sta->ht_cap.ht_supported)
8201 dev_info(dev, "%s: HT supported\n", __func__);
8202 if (sta->vht_cap.vht_supported)
8203 dev_info(dev, "%s: VHT supported\n", __func__);
8204
8205 /* TODO: Set bits 28-31 for rate adaptive id */
8206 ramask = (sta->supp_rates[0] & 0xfff) |
8207 sta->ht_cap.mcs.rx_mask[0] << 12 |
8208 sta->ht_cap.mcs.rx_mask[1] << 20;
8209 if (sta->ht_cap.cap &
8210 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
8211 sgi = 1;
8212 rcu_read_unlock();
8213
f653e690 8214 priv->fops->update_rate_mask(priv, ramask, sgi);
26f1fad2 8215
26f1fad2
JS		 8216 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
8217
8218 rtl8723a_stop_tx_beacon(priv);
8219
8220 /* joinbss sequence */
8221 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
8222 0xc000 | bss_conf->aid);
8223
7d794eaa 8224 priv->fops->report_connect(priv, 0, true);
26f1fad2 8225 } else {
26f1fad2
JS		 8226 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
8227 val8 |= BEACON_DISABLE_TSF_UPDATE;
8228 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
8229
7d794eaa 8230 priv->fops->report_connect(priv, 0, false);
26f1fad2 8231 }
26f1fad2
JS		 8232 }
8233
8234 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
8235 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
8236 bss_conf->use_short_preamble);
8237 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
8238 if (bss_conf->use_short_preamble)
8239 val32 |= RSR_ACK_SHORT_PREAMBLE;
8240 else
8241 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
8242 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
8243 }
8244
8245 if (changed & BSS_CHANGED_ERP_SLOT) {
8246 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
8247 bss_conf->use_short_slot);
8248
8249 if (bss_conf->use_short_slot)
8250 val8 = 9;
8251 else
8252 val8 = 20;
8253 rtl8xxxu_write8(priv, REG_SLOT, val8);
8254 }
8255
8256 if (changed & BSS_CHANGED_BSSID) {
8257 dev_dbg(dev, "Changed BSSID!\n");
8258 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
8259 }
8260
8261 if (changed & BSS_CHANGED_BASIC_RATES) {
8262 dev_dbg(dev, "Changed BASIC_RATES!\n");
8263 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
8264 }
8265error:
8266 return;
8267}
8268
8269static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
8270{
8271 u32 rtlqueue;
8272
8273 switch (queue) {
8274 case IEEE80211_AC_VO:
8275 rtlqueue = TXDESC_QUEUE_VO;
8276 break;
8277 case IEEE80211_AC_VI:
8278 rtlqueue = TXDESC_QUEUE_VI;
8279 break;
8280 case IEEE80211_AC_BE:
8281 rtlqueue = TXDESC_QUEUE_BE;
8282 break;
8283 case IEEE80211_AC_BK:
8284 rtlqueue = TXDESC_QUEUE_BK;
8285 break;
8286 default:
8287 rtlqueue = TXDESC_QUEUE_BE;
8288 }
8289
8290 return rtlqueue;
8291}
8292
8293static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
8294{
8295 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8296 u32 queue;
8297
8298 if (ieee80211_is_mgmt(hdr->frame_control))
8299 queue = TXDESC_QUEUE_MGNT;
8300 else
8301 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
8302
8303 return queue;
8304}
8305
179e1742
JS		 8306/*
8307 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
8308 * format. The descriptor checksum is still only calculated over the
8309 * initial 32 bytes of the descriptor!
8310 */
dbb2896b 8311static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
26f1fad2
JS		 8312{
8313 __le16 *ptr = (__le16 *)tx_desc;
8314 u16 csum = 0;
8315 int i;
8316
8317 /*
8318 * Clear csum field before calculation, as the csum field is
8319 * in the middle of the struct.
8320 */
8321 tx_desc->csum = cpu_to_le16(0);
8322
dbb2896b 8323 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
26f1fad2
JS		 8324 csum = csum ^ le16_to_cpu(ptr[i]);
8325
8326 tx_desc->csum |= cpu_to_le16(csum);
8327}
8328
8329static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
8330{
8331 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
8332 unsigned long flags;
8333
8334 spin_lock_irqsave(&priv->tx_urb_lock, flags);
8335 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
8336 list_del(&tx_urb->list);
8337 priv->tx_urb_free_count--;
8338 usb_free_urb(&tx_urb->urb);
8339 }
8340 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
8341}
8342
8343static struct rtl8xxxu_tx_urb *
8344rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
8345{
8346 struct rtl8xxxu_tx_urb *tx_urb;
8347 unsigned long flags;
8348
8349 spin_lock_irqsave(&priv->tx_urb_lock, flags);
8350 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
8351 struct rtl8xxxu_tx_urb, list);
8352 if (tx_urb) {
8353 list_del(&tx_urb->list);
8354 priv->tx_urb_free_count--;
8355 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
8356 !priv->tx_stopped) {
8357 priv->tx_stopped = true;
8358 ieee80211_stop_queues(priv->hw);
8359 }
8360 }
8361
8362 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
8363
8364 return tx_urb;
8365}
8366
8367static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
8368 struct rtl8xxxu_tx_urb *tx_urb)
8369{
8370 unsigned long flags;
8371
8372 INIT_LIST_HEAD(&tx_urb->list);
8373
8374 spin_lock_irqsave(&priv->tx_urb_lock, flags);
8375
8376 list_add(&tx_urb->list, &priv->tx_urb_free_list);
8377 priv->tx_urb_free_count++;
8378 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
8379 priv->tx_stopped) {
8380 priv->tx_stopped = false;
8381 ieee80211_wake_queues(priv->hw);
8382 }
8383
8384 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
8385}
8386
8387static void rtl8xxxu_tx_complete(struct urb *urb)
8388{
8389 struct sk_buff *skb = (struct sk_buff *)urb->context;
8390 struct ieee80211_tx_info *tx_info;
8391 struct ieee80211_hw *hw;
179e1742 8392 struct rtl8xxxu_priv *priv;
26f1fad2
JS		 8393 struct rtl8xxxu_tx_urb *tx_urb =
8394 container_of(urb, struct rtl8xxxu_tx_urb, urb);
8395
8396 tx_info = IEEE80211_SKB_CB(skb);
8397 hw = tx_info->rate_driver_data[0];
179e1742 8398 priv = hw->priv;
26f1fad2 8399
179e1742 8400 skb_pull(skb, priv->fops->tx_desc_size);
26f1fad2
JS		 8401
8402 ieee80211_tx_info_clear_status(tx_info);
8403 tx_info->status.rates[0].idx = -1;
8404 tx_info->status.rates[0].count = 0;
8405
8406 if (!urb->status)
8407 tx_info->flags |= IEEE80211_TX_STAT_ACK;
8408
8409 ieee80211_tx_status_irqsafe(hw, skb);
8410
179e1742 8411 rtl8xxxu_free_tx_urb(priv, tx_urb);
26f1fad2
JS		 8412}
8413
8414static void rtl8xxxu_dump_action(struct device *dev,
8415 struct ieee80211_hdr *hdr)
8416{
8417 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
8418 u16 cap, timeout;
8419
8420 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
8421 return;
8422
8423 switch (mgmt->u.action.u.addba_resp.action_code) {
8424 case WLAN_ACTION_ADDBA_RESP:
8425 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
8426 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
8427 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
8428 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
8429 "status %02x\n",
8430 timeout,
8431 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
8432 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
8433 (cap >> 1) & 0x1,
8434 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
8435 break;
8436 case WLAN_ACTION_ADDBA_REQ:
8437 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
8438 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
8439 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
8440 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
8441 timeout,
8442 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
8443 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
8444 (cap >> 1) & 0x1);
8445 break;
8446 default:
8447 dev_info(dev, "action frame %02x\n",
8448 mgmt->u.action.u.addba_resp.action_code);
8449 break;
8450 }
8451}
8452
8453static void rtl8xxxu_tx(struct ieee80211_hw *hw,
8454 struct ieee80211_tx_control *control,
8455 struct sk_buff *skb)
8456{
8457 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
8458 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
8459 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
8460 struct rtl8xxxu_priv *priv = hw->priv;
dbb2896b
JS		 8461 struct rtl8xxxu_txdesc32 *tx_desc;
8462 struct rtl8xxxu_txdesc40 *tx_desc40;
26f1fad2
JS		 8463 struct rtl8xxxu_tx_urb *tx_urb;
8464 struct ieee80211_sta *sta = NULL;
8465 struct ieee80211_vif *vif = tx_info->control.vif;
8466 struct device *dev = &priv->udev->dev;
8467 u32 queue, rate;
8468 u16 pktlen = skb->len;
8469 u16 seq_number;
8470 u16 rate_flag = tx_info->control.rates[0].flags;
179e1742 8471 int tx_desc_size = priv->fops->tx_desc_size;
26f1fad2 8472 int ret;
cc2646d4 8473 bool usedesc40, ampdu_enable;
26f1fad2 8474
179e1742 8475 if (skb_headroom(skb) < tx_desc_size) {
26f1fad2
JS		 8476 dev_warn(dev,
8477 "%s: Not enough headroom (%i) for tx descriptor\n",
8478 __func__, skb_headroom(skb));
8479 goto error;
8480 }
8481
179e1742 8482 if (unlikely(skb->len > (65535 - tx_desc_size))) {
26f1fad2
JS		 8483 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
8484 __func__, skb->len);
8485 goto error;
8486 }
8487
8488 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
8489 if (!tx_urb) {
8490 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
8491 goto error;
8492 }
8493
8494 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
8495 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
8496 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
8497
8498 if (ieee80211_is_action(hdr->frame_control))
8499 rtl8xxxu_dump_action(dev, hdr);
8500
cc2646d4 8501 usedesc40 = (tx_desc_size == 40);
26f1fad2
JS		 8502 tx_info->rate_driver_data[0] = hw;
8503
8504 if (control && control->sta)
8505 sta = control->sta;
8506
dbb2896b 8507 tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size);
26f1fad2 8508
179e1742 8509 memset(tx_desc, 0, tx_desc_size);
26f1fad2 8510 tx_desc->pkt_size = cpu_to_le16(pktlen);
179e1742 8511 tx_desc->pkt_offset = tx_desc_size;
26f1fad2
JS		 8512
8513 tx_desc->txdw0 =
8514 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
8515 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
8516 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
8517 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
8518
8519 queue = rtl8xxxu_queue_select(hw, skb);
8520 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
8521
8522 if (tx_info->control.hw_key) {
8523 switch (tx_info->control.hw_key->cipher) {
8524 case WLAN_CIPHER_SUITE_WEP40:
8525 case WLAN_CIPHER_SUITE_WEP104:
8526 case WLAN_CIPHER_SUITE_TKIP:
8527 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
8528 break;
8529 case WLAN_CIPHER_SUITE_CCMP:
8530 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
8531 break;
8532 default:
8533 break;
8534 }
8535 }
8536
26f1fad2 8537 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
a40ace4f 8538 ampdu_enable = false;
26f1fad2
JS		 8539 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
8540 if (sta->ht_cap.ht_supported) {
8541 u32 ampdu, val32;
8542
8543 ampdu = (u32)sta->ht_cap.ampdu_density;
8544 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
8545 tx_desc->txdw2 |= cpu_to_le32(val32);
ce2d1dbb 8546
a40ace4f
JS		 8547 ampdu_enable = true;
8548 }
8549 }
8550
4c683607
JS		 8551 if (rate_flag & IEEE80211_TX_RC_MCS)
8552 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
8553 else
8554 rate = tx_rate->hw_value;
8555
cc2646d4
JS		 8556 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
8557 if (!usedesc40) {
4c683607
JS		 8558 tx_desc->txdw5 = cpu_to_le32(rate);
8559
8560 if (ieee80211_is_data(hdr->frame_control))
8561 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
8562
cc2646d4 8563 tx_desc->txdw3 =
33f37249 8564 cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
cc2646d4 8565
a40ace4f 8566 if (ampdu_enable)
33f37249 8567 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
a40ace4f 8568 else
33f37249 8569 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
4c683607
JS		 8570
8571 if (ieee80211_is_mgmt(hdr->frame_control)) {
8572 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
8573 tx_desc->txdw4 |=
33f37249 8574 cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
4c683607 8575 tx_desc->txdw5 |=
33f37249 8576 cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
4c683607 8577 tx_desc->txdw5 |=
33f37249 8578 cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
4c683607
JS		 8579 }
8580
8581 if (ieee80211_is_data_qos(hdr->frame_control))
33f37249 8582 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
4c683607
JS		 8583
8584 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
8585 (sta && vif && vif->bss_conf.use_short_preamble))
33f37249 8586 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
4c683607
JS		 8587
8588 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
8589 (ieee80211_is_data_qos(hdr->frame_control) &&
8590 sta && sta->ht_cap.cap &
8591 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
1df1de34 8592 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
4c683607
JS		 8593 }
8594
8595 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
8596 /*
8597 * Use RTS rate 24M - does the mac80211 tell
8598 * us which to use?
8599 */
8600 tx_desc->txdw4 |=
8601 cpu_to_le32(DESC_RATE_24M <<
33f37249 8602 TXDESC32_RTS_RATE_SHIFT);
4c683607 8603 tx_desc->txdw4 |=
33f37249
JS		 8604 cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
8605 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4c683607 8606 }
a40ace4f 8607 } else {
dbb2896b 8608 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc;
cc2646d4 8609
4c683607
JS		 8610 tx_desc40->txdw4 = cpu_to_le32(rate);
8611 if (ieee80211_is_data(hdr->frame_control)) {
8612 tx_desc->txdw4 |=
8613 cpu_to_le32(0x1f <<
33f37249 8614 TXDESC40_DATA_RATE_FB_SHIFT);
4c683607
JS		 8615 }
8616
cc2646d4 8617 tx_desc40->txdw9 =
33f37249 8618 cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
cc2646d4 8619
a40ace4f 8620 if (ampdu_enable)
33f37249 8621 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
a40ace4f 8622 else
33f37249 8623 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
26f1fad2 8624
4c683607
JS		 8625 if (ieee80211_is_mgmt(hdr->frame_control)) {
8626 tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value);
8627 tx_desc40->txdw3 |=
33f37249 8628 cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
4c683607 8629 tx_desc40->txdw4 |=
33f37249 8630 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
4c683607 8631 tx_desc40->txdw4 |=
33f37249 8632 cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
4c683607
JS		 8633 }
8634
8635 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
8636 (sta && vif && vif->bss_conf.use_short_preamble))
8637 tx_desc40->txdw5 |=
33f37249 8638 cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
4c683607
JS		 8639
8640 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
8641 /*
8642 * Use RTS rate 24M - does the mac80211 tell
8643 * us which to use?
8644 */
8645 tx_desc->txdw4 |=
8646 cpu_to_le32(DESC_RATE_24M <<
33f37249
JS		 8647 TXDESC40_RTS_RATE_SHIFT);
8648 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
8649 tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
4c683607 8650 }
6979494a 8651 }
26f1fad2
JS		 8652
8653 rtl8xxxu_calc_tx_desc_csum(tx_desc);
8654
8655 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
8656 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
8657
8658 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
8659 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
8660 if (ret) {
8661 usb_unanchor_urb(&tx_urb->urb);
8662 rtl8xxxu_free_tx_urb(priv, tx_urb);
8663 goto error;
8664 }
8665 return;
8666error:
8667 dev_kfree_skb(skb);
8668}
8669
8670static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
8671 struct ieee80211_rx_status *rx_status,
87957081
JS		 8672 struct rtl8723au_phy_stats *phy_stats,
8673 u32 rxmcs)
26f1fad2
JS		 8674{
8675 if (phy_stats->sgi_en)
8676 rx_status->flag |= RX_FLAG_SHORT_GI;
8677
87957081 8678 if (rxmcs < DESC_RATE_6M) {
26f1fad2
JS		 8679 /*
8680 * Handle PHY stats for CCK rates
8681 */
8682 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
8683
8684 switch (cck_agc_rpt & 0xc0) {
8685 case 0xc0:
8686 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
8687 break;
8688 case 0x80:
8689 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
8690 break;
8691 case 0x40:
8692 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
8693 break;
8694 case 0x00:
8695 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
8696 break;
8697 }
8698 } else {
8699 rx_status->signal =
8700 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
8701 }
8702}
8703
8704static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
8705{
8706 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
8707 unsigned long flags;
8708
8709 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8710
8711 list_for_each_entry_safe(rx_urb, tmp,
8712 &priv->rx_urb_pending_list, list) {
8713 list_del(&rx_urb->list);
8714 priv->rx_urb_pending_count--;
8715 usb_free_urb(&rx_urb->urb);
8716 }
8717
8718 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8719}
8720
8721static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
8722 struct rtl8xxxu_rx_urb *rx_urb)
8723{
8724 struct sk_buff *skb;
8725 unsigned long flags;
8726 int pending = 0;
8727
8728 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8729
8730 if (!priv->shutdown) {
8731 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
8732 priv->rx_urb_pending_count++;
8733 pending = priv->rx_urb_pending_count;
8734 } else {
8735 skb = (struct sk_buff *)rx_urb->urb.context;
8736 dev_kfree_skb(skb);
8737 usb_free_urb(&rx_urb->urb);
8738 }
8739
8740 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8741
8742 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
8743 schedule_work(&priv->rx_urb_wq);
8744}
8745
8746static void rtl8xxxu_rx_urb_work(struct work_struct *work)
8747{
8748 struct rtl8xxxu_priv *priv;
8749 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
8750 struct list_head local;
8751 struct sk_buff *skb;
8752 unsigned long flags;
8753 int ret;
8754
8755 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
8756 INIT_LIST_HEAD(&local);
8757
8758 spin_lock_irqsave(&priv->rx_urb_lock, flags);
8759
8760 list_splice_init(&priv->rx_urb_pending_list, &local);
8761 priv->rx_urb_pending_count = 0;
8762
8763 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
8764
8765 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
8766 list_del_init(&rx_urb->list);
8767 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
8768 /*
8769 * If out of memory or temporary error, put it back on the
8770 * queue and try again. Otherwise the device is dead/gone
8771 * and we should drop it.
8772 */
8773 switch (ret) {
8774 case 0:
8775 break;
8776 case -ENOMEM:
8777 case -EAGAIN:
8778 rtl8xxxu_queue_rx_urb(priv, rx_urb);
8779 break;
8780 default:
8781 pr_info("failed to requeue urb %i\n", ret);
8782 skb = (struct sk_buff *)rx_urb->urb.context;
8783 dev_kfree_skb(skb);
8784 usb_free_urb(&rx_urb->urb);
8785 }
8786 }
8787}
8788
a49c7ce1 8789static int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv,
b18cdfdb
JS		 8790 struct sk_buff *skb,
8791 struct ieee80211_rx_status *rx_status)
8792{
a49c7ce1
JS		 8793 struct rtl8xxxu_rxdesc16 *rx_desc =
8794 (struct rtl8xxxu_rxdesc16 *)skb->data;
b18cdfdb 8795 struct rtl8723au_phy_stats *phy_stats;
2cb79eb7
JS		 8796 __le32 *_rx_desc_le = (__le32 *)skb->data;
8797 u32 *_rx_desc = (u32 *)skb->data;
b18cdfdb 8798 int drvinfo_sz, desc_shift;
2cb79eb7
JS		 8799 int i;
8800
a49c7ce1 8801 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
2cb79eb7 8802 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
b18cdfdb 8803
a49c7ce1 8804 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
b18cdfdb
JS		 8805
8806 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
8807
8808 drvinfo_sz = rx_desc->drvinfo_sz * 8;
8809 desc_shift = rx_desc->shift;
8810 skb_pull(skb, drvinfo_sz + desc_shift);
8811
8812 if (rx_desc->phy_stats)
87957081
JS		 8813 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
8814 rx_desc->rxmcs);
b18cdfdb
JS		 8815
8816 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
8817 rx_status->flag |= RX_FLAG_MACTIME_START;
8818
8819 if (!rx_desc->swdec)
8820 rx_status->flag |= RX_FLAG_DECRYPTED;
8821 if (rx_desc->crc32)
8822 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
8823 if (rx_desc->bw)
8824 rx_status->flag |= RX_FLAG_40MHZ;
8825
8826 if (rx_desc->rxht) {
8827 rx_status->flag |= RX_FLAG_HT;
8828 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
8829 } else {
8830 rx_status->rate_idx = rx_desc->rxmcs;
8831 }
8832
8833 return RX_TYPE_DATA_PKT;
8834}
8835
a49c7ce1 8836static int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv,
b18cdfdb
JS		 8837 struct sk_buff *skb,
8838 struct ieee80211_rx_status *rx_status)
8839{
a49c7ce1
JS		 8840 struct rtl8xxxu_rxdesc24 *rx_desc =
8841 (struct rtl8xxxu_rxdesc24 *)skb->data;
b18cdfdb 8842 struct rtl8723au_phy_stats *phy_stats;
2cb79eb7
JS		 8843 __le32 *_rx_desc_le = (__le32 *)skb->data;
8844 u32 *_rx_desc = (u32 *)skb->data;
b18cdfdb 8845 int drvinfo_sz, desc_shift;
2cb79eb7
JS		 8846 int i;
8847
a49c7ce1 8848 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
2cb79eb7 8849 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
b18cdfdb 8850
a49c7ce1 8851 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
b18cdfdb
JS		 8852
8853 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
8854
8855 drvinfo_sz = rx_desc->drvinfo_sz * 8;
8856 desc_shift = rx_desc->shift;
8857 skb_pull(skb, drvinfo_sz + desc_shift);
8858
e975b87c
JS		 8859 if (rx_desc->rpt_sel) {
8860 struct device *dev = &priv->udev->dev;
8861 dev_dbg(dev, "%s: C2H packet\n", __func__);
8862 return RX_TYPE_C2H;
8863 }
8864
87957081
JS		 8865 if (rx_desc->phy_stats)
8866 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
8867 rx_desc->rxmcs);
8868
b18cdfdb
JS		 8869 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
8870 rx_status->flag |= RX_FLAG_MACTIME_START;
8871
8872 if (!rx_desc->swdec)
8873 rx_status->flag |= RX_FLAG_DECRYPTED;
8874 if (rx_desc->crc32)
8875 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
8876 if (rx_desc->bw)
8877 rx_status->flag |= RX_FLAG_40MHZ;
8878
8879 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
8880 rx_status->flag |= RX_FLAG_HT;
8881 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
8882 } else {
8883 rx_status->rate_idx = rx_desc->rxmcs;
8884 }
8885
e975b87c 8886 return RX_TYPE_DATA_PKT;
b18cdfdb
JS		 8887}
8888
b2b43b78
JS		 8889static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
8890 struct sk_buff *skb)
8891{
8892 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
8893 struct device *dev = &priv->udev->dev;
8894 int len;
8895
8896 len = skb->len - 2;
8897
5e00d503
JS		 8898 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
8899 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
b2b43b78
JS		 8900
8901 switch(c2h->id) {
8902 case C2H_8723B_BT_INFO:
8903 if (c2h->bt_info.response_source >
8904 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
5e00d503 8905 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
b2b43b78 8906 else
5e00d503 8907 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
b2b43b78
JS		 8908
8909 if (c2h->bt_info.bt_has_reset)
5e00d503 8910 dev_dbg(dev, "BT has been reset\n");
394f1bd3 8911 if (c2h->bt_info.tx_rx_mask)
5e00d503 8912 dev_dbg(dev, "BT TRx mask\n");
b2b43b78
JS		 8913
8914 break;
394f1bd3 8915 case C2H_8723B_BT_MP_INFO:
5e00d503
JS		 8916 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
8917 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
394f1bd3 8918 break;
55a18dd1
JS		 8919 case C2H_8723B_RA_REPORT:
8920 dev_dbg(dev,
8921 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
8922 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
8923 c2h->ra_report.macid, c2h->ra_report.noisy_state);
8924 break;
b2b43b78 8925 default:
739dc9f2
JS		 8926 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
8927 c2h->id, c2h->seq);
8928 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
8929 16, 1, c2h->raw.payload, len, false);
b2b43b78
JS		 8930 break;
8931 }
8932}
8933
26f1fad2
JS		 8934static void rtl8xxxu_rx_complete(struct urb *urb)
8935{
8936 struct rtl8xxxu_rx_urb *rx_urb =
8937 container_of(urb, struct rtl8xxxu_rx_urb, urb);
8938 struct ieee80211_hw *hw = rx_urb->hw;
8939 struct rtl8xxxu_priv *priv = hw->priv;
8940 struct sk_buff *skb = (struct sk_buff *)urb->context;
26f1fad2 8941 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
26f1fad2 8942 struct device *dev = &priv->udev->dev;
2cb79eb7 8943 int rx_type;
26f1fad2 8944
26f1fad2
JS		 8945 skb_put(skb, urb->actual_length);
8946
8947 if (urb->status == 0) {
26f1fad2
JS		 8948 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
8949
b18cdfdb 8950 rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status);
26f1fad2
JS		 8951
8952 rx_status->freq = hw->conf.chandef.chan->center_freq;
8953 rx_status->band = hw->conf.chandef.chan->band;
8954
b18cdfdb
JS		 8955 if (rx_type == RX_TYPE_DATA_PKT)
8956 ieee80211_rx_irqsafe(hw, skb);
b2b43b78
JS		 8957 else {
8958 rtl8723bu_handle_c2h(priv, skb);
b18cdfdb 8959 dev_kfree_skb(skb);
b2b43b78 8960 }
26f1fad2 8961
26f1fad2
JS		 8962 skb = NULL;
8963 rx_urb->urb.context = NULL;
8964 rtl8xxxu_queue_rx_urb(priv, rx_urb);
8965 } else {
8966 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
8967 goto cleanup;
8968 }
8969 return;
8970
8971cleanup:
8972 usb_free_urb(urb);
8973 dev_kfree_skb(skb);
8974 return;
8975}
8976
8977static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
8978 struct rtl8xxxu_rx_urb *rx_urb)
8979{
8980 struct sk_buff *skb;
8981 int skb_size;
a49c7ce1 8982 int ret, rx_desc_sz;
26f1fad2 8983
a49c7ce1
JS		 8984 rx_desc_sz = priv->fops->rx_desc_size;
8985 skb_size = rx_desc_sz + RTL_RX_BUFFER_SIZE;
26f1fad2
JS		 8986 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
8987 if (!skb)
8988 return -ENOMEM;
8989
a49c7ce1 8990 memset(skb->data, 0, rx_desc_sz);
26f1fad2
JS		 8991 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
8992 skb_size, rtl8xxxu_rx_complete, skb);
8993 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
8994 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
8995 if (ret)
8996 usb_unanchor_urb(&rx_urb->urb);
8997 return ret;
8998}
8999
9000static void rtl8xxxu_int_complete(struct urb *urb)
9001{
9002 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
9003 struct device *dev = &priv->udev->dev;
9004 int ret;
9005
9006 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
9007 if (urb->status == 0) {
9008 usb_anchor_urb(urb, &priv->int_anchor);
9009 ret = usb_submit_urb(urb, GFP_ATOMIC);
9010 if (ret)
9011 usb_unanchor_urb(urb);
9012 } else {
9013 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
9014 }
9015}
9016
9017
9018static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
9019{
9020 struct rtl8xxxu_priv *priv = hw->priv;
9021 struct urb *urb;
9022 u32 val32;
9023 int ret;
9024
9025 urb = usb_alloc_urb(0, GFP_KERNEL);
9026 if (!urb)
9027 return -ENOMEM;
9028
9029 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
9030 priv->int_buf, USB_INTR_CONTENT_LENGTH,
9031 rtl8xxxu_int_complete, priv, 1);
9032 usb_anchor_urb(urb, &priv->int_anchor);
9033 ret = usb_submit_urb(urb, GFP_KERNEL);
9034 if (ret) {
9035 usb_unanchor_urb(urb);
9036 goto error;
9037 }
9038
9039 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
9040 val32 |= USB_HIMR_CPWM;
9041 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
9042
9043error:
9044 return ret;
9045}
9046
9047static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
9048 struct ieee80211_vif *vif)
9049{
9050 struct rtl8xxxu_priv *priv = hw->priv;
9051 int ret;
9052 u8 val8;
9053
9054 switch (vif->type) {
9055 case NL80211_IFTYPE_STATION:
9056 rtl8723a_stop_tx_beacon(priv);
9057
9058 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
9059 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
9060 BEACON_DISABLE_TSF_UPDATE;
9061 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
9062 ret = 0;
9063 break;
9064 default:
9065 ret = -EOPNOTSUPP;
9066 }
9067
9068 rtl8xxxu_set_linktype(priv, vif->type);
9069
9070 return ret;
9071}
9072
9073static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
9074 struct ieee80211_vif *vif)
9075{
9076 struct rtl8xxxu_priv *priv = hw->priv;
9077
9078 dev_dbg(&priv->udev->dev, "%s\n", __func__);
9079}
9080
9081static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
9082{
9083 struct rtl8xxxu_priv *priv = hw->priv;
9084 struct device *dev = &priv->udev->dev;
9085 u16 val16;
9086 int ret = 0, channel;
9087 bool ht40;
9088
9089 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
9090 dev_info(dev,
9091 "%s: channel: %i (changed %08x chandef.width %02x)\n",
9092 __func__, hw->conf.chandef.chan->hw_value,
9093 changed, hw->conf.chandef.width);
9094
9095 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
9096 val16 = ((hw->conf.long_frame_max_tx_count <<
9097 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
9098 ((hw->conf.short_frame_max_tx_count <<
9099 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
9100 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
9101 }
9102
9103 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
9104 switch (hw->conf.chandef.width) {
9105 case NL80211_CHAN_WIDTH_20_NOHT:
9106 case NL80211_CHAN_WIDTH_20:
9107 ht40 = false;
9108 break;
9109 case NL80211_CHAN_WIDTH_40:
9110 ht40 = true;
9111 break;
9112 default:
9113 ret = -ENOTSUPP;
9114 goto exit;
9115 }
9116
9117 channel = hw->conf.chandef.chan->hw_value;
9118
e796dab4 9119 priv->fops->set_tx_power(priv, channel, ht40);
26f1fad2 9120
1ea8e846 9121 priv->fops->config_channel(hw);
26f1fad2
JS		 9122 }
9123
9124exit:
9125 return ret;
9126}
9127
9128static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
9129 struct ieee80211_vif *vif, u16 queue,
9130 const struct ieee80211_tx_queue_params *param)
9131{
9132 struct rtl8xxxu_priv *priv = hw->priv;
9133 struct device *dev = &priv->udev->dev;
9134 u32 val32;
9135 u8 aifs, acm_ctrl, acm_bit;
9136
9137 aifs = param->aifs;
9138
9139 val32 = aifs |
9140 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
9141 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
9142 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
9143
9144 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
9145 dev_dbg(dev,
9146 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
9147 __func__, queue, val32, param->acm, acm_ctrl);
9148
9149 switch (queue) {
9150 case IEEE80211_AC_VO:
9151 acm_bit = ACM_HW_CTRL_VO;
9152 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
9153 break;
9154 case IEEE80211_AC_VI:
9155 acm_bit = ACM_HW_CTRL_VI;
9156 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
9157 break;
9158 case IEEE80211_AC_BE:
9159 acm_bit = ACM_HW_CTRL_BE;
9160 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
9161 break;
9162 case IEEE80211_AC_BK:
9163 acm_bit = ACM_HW_CTRL_BK;
9164 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
9165 break;
9166 default:
9167 acm_bit = 0;
9168 break;
9169 }
9170
9171 if (param->acm)
9172 acm_ctrl |= acm_bit;
9173 else
9174 acm_ctrl &= ~acm_bit;
9175 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
9176
9177 return 0;
9178}
9179
9180static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
9181 unsigned int changed_flags,
9182 unsigned int *total_flags, u64 multicast)
9183{
9184 struct rtl8xxxu_priv *priv = hw->priv;
3bed4bfa 9185 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
26f1fad2
JS		 9186
9187 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
9188 __func__, changed_flags, *total_flags);
9189
3bed4bfa
BR		 9190 /*
9191 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
9192 */
9193
9194 if (*total_flags & FIF_FCSFAIL)
9195 rcr |= RCR_ACCEPT_CRC32;
9196 else
9197 rcr &= ~RCR_ACCEPT_CRC32;
9198
9199 /*
9200 * FIF_PLCPFAIL not supported?
9201 */
9202
9203 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
9204 rcr &= ~RCR_CHECK_BSSID_BEACON;
9205 else
9206 rcr |= RCR_CHECK_BSSID_BEACON;
9207
9208 if (*total_flags & FIF_CONTROL)
9209 rcr |= RCR_ACCEPT_CTRL_FRAME;
9210 else
9211 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
9212
9213 if (*total_flags & FIF_OTHER_BSS) {
9214 rcr |= RCR_ACCEPT_AP;
9215 rcr &= ~RCR_CHECK_BSSID_MATCH;
9216 } else {
9217 rcr &= ~RCR_ACCEPT_AP;
9218 rcr |= RCR_CHECK_BSSID_MATCH;
9219 }
9220
9221 if (*total_flags & FIF_PSPOLL)
9222 rcr |= RCR_ACCEPT_PM;
9223 else
9224 rcr &= ~RCR_ACCEPT_PM;
9225
9226 /*
9227 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
9228 */
9229
9230 rtl8xxxu_write32(priv, REG_RCR, rcr);
9231
755bda11
JS		 9232 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
9233 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
9234 FIF_PROBE_REQ);
26f1fad2
JS		 9235}
9236
9237static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
9238{
9239 if (rts > 2347)
9240 return -EINVAL;
9241
9242 return 0;
9243}
9244
9245static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
9246 struct ieee80211_vif *vif,
9247 struct ieee80211_sta *sta,
9248 struct ieee80211_key_conf *key)
9249{
9250 struct rtl8xxxu_priv *priv = hw->priv;
9251 struct device *dev = &priv->udev->dev;
9252 u8 mac_addr[ETH_ALEN];
9253 u8 val8;
9254 u16 val16;
9255 u32 val32;
9256 int retval = -EOPNOTSUPP;
9257
9258 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
9259 __func__, cmd, key->cipher, key->keyidx);
9260
9261 if (vif->type != NL80211_IFTYPE_STATION)
9262 return -EOPNOTSUPP;
9263
9264 if (key->keyidx > 3)
9265 return -EOPNOTSUPP;
9266
9267 switch (key->cipher) {
9268 case WLAN_CIPHER_SUITE_WEP40:
9269 case WLAN_CIPHER_SUITE_WEP104:
9270
9271 break;
9272 case WLAN_CIPHER_SUITE_CCMP:
9273 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
9274 break;
9275 case WLAN_CIPHER_SUITE_TKIP:
9276 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
9277 default:
9278 return -EOPNOTSUPP;
9279 }
9280
9281 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
9282 dev_dbg(dev, "%s: pairwise key\n", __func__);
9283 ether_addr_copy(mac_addr, sta->addr);
9284 } else {
9285 dev_dbg(dev, "%s: group key\n", __func__);
9286 eth_broadcast_addr(mac_addr);
9287 }
9288
9289 val16 = rtl8xxxu_read16(priv, REG_CR);
9290 val16 |= CR_SECURITY_ENABLE;
9291 rtl8xxxu_write16(priv, REG_CR, val16);
9292
9293 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
9294 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
9295 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
9296 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
9297
9298 switch (cmd) {
9299 case SET_KEY:
9300 key->hw_key_idx = key->keyidx;
9301 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
9302 rtl8xxxu_cam_write(priv, key, mac_addr);
9303 retval = 0;
9304 break;
9305 case DISABLE_KEY:
9306 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
9307 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
9308 key->keyidx << CAM_CMD_KEY_SHIFT;
9309 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
9310 retval = 0;
9311 break;
9312 default:
9313 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
9314 }
9315
9316 return retval;
9317}
9318
9319static int
9320rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 9321 struct ieee80211_ampdu_params *params)
26f1fad2
JS		 9322{
9323 struct rtl8xxxu_priv *priv = hw->priv;
9324 struct device *dev = &priv->udev->dev;
9325 u8 ampdu_factor, ampdu_density;
50ea05ef
SS		 9326 struct ieee80211_sta *sta = params->sta;
9327 enum ieee80211_ampdu_mlme_action action = params->action;
26f1fad2
JS		 9328
9329 switch (action) {
9330 case IEEE80211_AMPDU_TX_START:
9331 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
9332 ampdu_factor = sta->ht_cap.ampdu_factor;
9333 ampdu_density = sta->ht_cap.ampdu_density;
9334 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
9335 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
9336 dev_dbg(dev,
9337 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
9338 ampdu_factor, ampdu_density);
9339 break;
9340 case IEEE80211_AMPDU_TX_STOP_FLUSH:
9341 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
9342 rtl8xxxu_set_ampdu_factor(priv, 0);
9343 rtl8xxxu_set_ampdu_min_space(priv, 0);
9344 break;
9345 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
9346 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
9347 __func__);
9348 rtl8xxxu_set_ampdu_factor(priv, 0);
9349 rtl8xxxu_set_ampdu_min_space(priv, 0);
9350 break;
9351 case IEEE80211_AMPDU_RX_START:
9352 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
9353 break;
9354 case IEEE80211_AMPDU_RX_STOP:
9355 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
9356 break;
9357 default:
9358 break;
9359 }
9360 return 0;
9361}
9362
9363static int rtl8xxxu_start(struct ieee80211_hw *hw)
9364{
9365 struct rtl8xxxu_priv *priv = hw->priv;
9366 struct rtl8xxxu_rx_urb *rx_urb;
9367 struct rtl8xxxu_tx_urb *tx_urb;
9368 unsigned long flags;
9369 int ret, i;
9370
9371 ret = 0;
9372
9373 init_usb_anchor(&priv->rx_anchor);
9374 init_usb_anchor(&priv->tx_anchor);
9375 init_usb_anchor(&priv->int_anchor);
9376
db08de94 9377 priv->fops->enable_rf(priv);
0e28b975
JS		 9378 if (priv->usb_interrupts) {
9379 ret = rtl8xxxu_submit_int_urb(hw);
9380 if (ret)
9381 goto exit;
9382 }
26f1fad2
JS		 9383
9384 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
9385 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
9386 if (!tx_urb) {
9387 if (!i)
9388 ret = -ENOMEM;
9389
9390 goto error_out;
9391 }
9392 usb_init_urb(&tx_urb->urb);
9393 INIT_LIST_HEAD(&tx_urb->list);
9394 tx_urb->hw = hw;
9395 list_add(&tx_urb->list, &priv->tx_urb_free_list);
9396 priv->tx_urb_free_count++;
9397 }
9398
9399 priv->tx_stopped = false;
9400
9401 spin_lock_irqsave(&priv->rx_urb_lock, flags);
9402 priv->shutdown = false;
9403 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
9404
9405 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
9406 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
9407 if (!rx_urb) {
9408 if (!i)
9409 ret = -ENOMEM;
9410
9411 goto error_out;
9412 }
9413 usb_init_urb(&rx_urb->urb);
9414 INIT_LIST_HEAD(&rx_urb->list);
9415 rx_urb->hw = hw;
9416
9417 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
9418 }
9419exit:
9420 /*
c85ea115 9421 * Accept all data and mgmt frames
26f1fad2 9422 */
c85ea115 9423 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
26f1fad2
JS		 9424 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
9425
9426 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
9427
9428 return ret;
9429
9430error_out:
9431 rtl8xxxu_free_tx_resources(priv);
9432 /*
9433 * Disable all data and mgmt frames
9434 */
9435 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
9436 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
9437
9438 return ret;
9439}
9440
9441static void rtl8xxxu_stop(struct ieee80211_hw *hw)
9442{
9443 struct rtl8xxxu_priv *priv = hw->priv;
9444 unsigned long flags;
9445
9446 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
9447
9448 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
9449 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
9450
9451 spin_lock_irqsave(&priv->rx_urb_lock, flags);
9452 priv->shutdown = true;
9453 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
9454
9455 usb_kill_anchored_urbs(&priv->rx_anchor);
9456 usb_kill_anchored_urbs(&priv->tx_anchor);
0e28b975
JS		 9457 if (priv->usb_interrupts)
9458 usb_kill_anchored_urbs(&priv->int_anchor);
26f1fad2 9459
fc89a41f 9460 priv->fops->disable_rf(priv);
26f1fad2
JS		 9461
9462 /*
9463 * Disable interrupts
9464 */
0e28b975
JS		 9465 if (priv->usb_interrupts)
9466 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
26f1fad2
JS		 9467
9468 rtl8xxxu_free_rx_resources(priv);
9469 rtl8xxxu_free_tx_resources(priv);
9470}
9471
9472static const struct ieee80211_ops rtl8xxxu_ops = {
9473 .tx = rtl8xxxu_tx,
9474 .add_interface = rtl8xxxu_add_interface,
9475 .remove_interface = rtl8xxxu_remove_interface,
9476 .config = rtl8xxxu_config,
9477 .conf_tx = rtl8xxxu_conf_tx,
9478 .bss_info_changed = rtl8xxxu_bss_info_changed,
9479 .configure_filter = rtl8xxxu_configure_filter,
9480 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
9481 .start = rtl8xxxu_start,
9482 .stop = rtl8xxxu_stop,
9483 .sw_scan_start = rtl8xxxu_sw_scan_start,
9484 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
9485 .set_key = rtl8xxxu_set_key,
9486 .ampdu_action = rtl8xxxu_ampdu_action,
9487};
9488
9489static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
9490 struct usb_interface *interface)
9491{
9492 struct usb_interface_descriptor *interface_desc;
9493 struct usb_host_interface *host_interface;
9494 struct usb_endpoint_descriptor *endpoint;
9495 struct device *dev = &priv->udev->dev;
9496 int i, j = 0, endpoints;
9497 u8 dir, xtype, num;
9498 int ret = 0;
9499
9500 host_interface = &interface->altsetting[0];
9501 interface_desc = &host_interface->desc;
9502 endpoints = interface_desc->bNumEndpoints;
9503
9504 for (i = 0; i < endpoints; i++) {
9505 endpoint = &host_interface->endpoint[i].desc;
9506
9507 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
9508 num = usb_endpoint_num(endpoint);
9509 xtype = usb_endpoint_type(endpoint);
9510 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
9511 dev_dbg(dev,
9512 "%s: endpoint: dir %02x, # %02x, type %02x\n",
9513 __func__, dir, num, xtype);
9514 if (usb_endpoint_dir_in(endpoint) &&
9515 usb_endpoint_xfer_bulk(endpoint)) {
9516 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
9517 dev_dbg(dev, "%s: in endpoint num %i\n",
9518 __func__, num);
9519
9520 if (priv->pipe_in) {
9521 dev_warn(dev,
9522 "%s: Too many IN pipes\n", __func__);
9523 ret = -EINVAL;
9524 goto exit;
9525 }
9526
9527 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
9528 }
9529
9530 if (usb_endpoint_dir_in(endpoint) &&
9531 usb_endpoint_xfer_int(endpoint)) {
9532 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
9533 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
9534 __func__, num);
9535
9536 if (priv->pipe_interrupt) {
9537 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
9538 __func__);
9539 ret = -EINVAL;
9540 goto exit;
9541 }
9542
9543 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
9544 }
9545
9546 if (usb_endpoint_dir_out(endpoint) &&
9547 usb_endpoint_xfer_bulk(endpoint)) {
9548 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
9549 dev_dbg(dev, "%s: out endpoint num %i\n",
9550 __func__, num);
9551 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
9552 dev_warn(dev,
9553 "%s: Too many OUT pipes\n", __func__);
9554 ret = -EINVAL;
9555 goto exit;
9556 }
9557 priv->out_ep[j++] = num;
9558 }
9559 }
9560exit:
9561 priv->nr_out_eps = j;
9562 return ret;
9563}
9564
9565static int rtl8xxxu_probe(struct usb_interface *interface,
9566 const struct usb_device_id *id)
9567{
9568 struct rtl8xxxu_priv *priv;
9569 struct ieee80211_hw *hw;
9570 struct usb_device *udev;
9571 struct ieee80211_supported_band *sband;
9572 int ret = 0;
9573 int untested = 1;
9574
9575 udev = usb_get_dev(interface_to_usbdev(interface));
9576
9577 switch (id->idVendor) {
9578 case USB_VENDOR_ID_REALTEK:
9579 switch(id->idProduct) {
9580 case 0x1724:
9581 case 0x8176:
9582 case 0x8178:
9583 case 0x817f:
9584 untested = 0;
9585 break;
9586 }
9587 break;
9588 case 0x7392:
9589 if (id->idProduct == 0x7811)
9590 untested = 0;
9591 break;
e1d70c9b
JS		 9592 case 0x050d:
9593 if (id->idProduct == 0x1004)
9594 untested = 0;
9595 break;
26f1fad2
JS		 9596 default:
9597 break;
9598 }
9599
9600 if (untested) {
eaa4d14c 9601 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 9602 dev_info(&udev->dev,
9603 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
9604 id->idVendor, id->idProduct);
9605 dev_info(&udev->dev,
9606 "Please report results to Jes.Sorensen@gmail.com\n");
9607 }
9608
9609 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
9610 if (!hw) {
9611 ret = -ENOMEM;
9612 goto exit;
9613 }
9614
9615 priv = hw->priv;
9616 priv->hw = hw;
9617 priv->udev = udev;
9618 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
9619 mutex_init(&priv->usb_buf_mutex);
9620 mutex_init(&priv->h2c_mutex);
9621 INIT_LIST_HEAD(&priv->tx_urb_free_list);
9622 spin_lock_init(&priv->tx_urb_lock);
9623 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
9624 spin_lock_init(&priv->rx_urb_lock);
9625 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
9626
9627 usb_set_intfdata(interface, hw);
9628
9629 ret = rtl8xxxu_parse_usb(priv, interface);
9630 if (ret)
9631 goto exit;
9632
9633 ret = rtl8xxxu_identify_chip(priv);
9634 if (ret) {
9635 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
9636 goto exit;
9637 }
9638
9639 ret = rtl8xxxu_read_efuse(priv);
9640 if (ret) {
9641 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
9642 goto exit;
9643 }
9644
9645 ret = priv->fops->parse_efuse(priv);
9646 if (ret) {
9647 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
9648 goto exit;
9649 }
9650
9651 rtl8xxxu_print_chipinfo(priv);
9652
9653 ret = priv->fops->load_firmware(priv);
9654 if (ret) {
9655 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
9656 goto exit;
9657 }
9658
9659 ret = rtl8xxxu_init_device(hw);
9660
9661 hw->wiphy->max_scan_ssids = 1;
9662 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
9663 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
9664 hw->queues = 4;
9665
9666 sband = &rtl8xxxu_supported_band;
9667 sband->ht_cap.ht_supported = true;
9668 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
9669 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
9670 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
9671 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
9672 sband->ht_cap.mcs.rx_mask[0] = 0xff;
9673 sband->ht_cap.mcs.rx_mask[4] = 0x01;
9674 if (priv->rf_paths > 1) {
9675 sband->ht_cap.mcs.rx_mask[1] = 0xff;
9676 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
9677 }
9678 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
9679 /*
9680 * Some APs will negotiate HT20_40 in a noisy environment leading
9681 * to miserable performance. Rather than defaulting to this, only
9682 * enable it if explicitly requested at module load time.
9683 */
9684 if (rtl8xxxu_ht40_2g) {
9685 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
9686 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
9687 }
57fbcce3 9688 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
26f1fad2
JS		 9689
9690 hw->wiphy->rts_threshold = 2347;
9691
9692 SET_IEEE80211_DEV(priv->hw, &interface->dev);
9693 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
9694
179e1742 9695 hw->extra_tx_headroom = priv->fops->tx_desc_size;
26f1fad2
JS		 9696 ieee80211_hw_set(hw, SIGNAL_DBM);
9697 /*
9698 * The firmware handles rate control
9699 */
9700 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
9701 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
9702
9703 ret = ieee80211_register_hw(priv->hw);
9704 if (ret) {
9705 dev_err(&udev->dev, "%s: Failed to register: %i\n",
9706 __func__, ret);
9707 goto exit;
9708 }
9709
9710exit:
9711 if (ret < 0)
9712 usb_put_dev(udev);
9713 return ret;
9714}
9715
9716static void rtl8xxxu_disconnect(struct usb_interface *interface)
9717{
9718 struct rtl8xxxu_priv *priv;
9719 struct ieee80211_hw *hw;
9720
9721 hw = usb_get_intfdata(interface);
9722 priv = hw->priv;
9723
8cae2f1d
JS		 9724 ieee80211_unregister_hw(hw);
9725
9726 priv->fops->power_off(priv);
9727
26f1fad2
JS		 9728 usb_set_intfdata(interface, NULL);
9729
9730 dev_info(&priv->udev->dev, "disconnecting\n");
9731
26f1fad2
JS		 9732 kfree(priv->fw_data);
9733 mutex_destroy(&priv->usb_buf_mutex);
9734 mutex_destroy(&priv->h2c_mutex);
9735
9736 usb_put_dev(priv->udev);
9737 ieee80211_free_hw(hw);
9738}
9739
9740static struct rtl8xxxu_fileops rtl8723au_fops = {
9741 .parse_efuse = rtl8723au_parse_efuse,
9742 .load_firmware = rtl8723au_load_firmware,
9743 .power_on = rtl8723au_power_on,
fe37d5f6 9744 .power_off = rtl8xxxu_power_off,
7d4ccb8b 9745 .reset_8051 = rtl8xxxu_reset_8051,
74b99bed 9746 .llt_init = rtl8xxxu_init_llt_table,
cb877250 9747 .init_phy_bb = rtl8723au_init_phy_bb,
4062b8ff 9748 .init_phy_rf = rtl8723au_init_phy_rf,
e1547c53 9749 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
c3f9506f 9750 .config_channel = rtl8723au_config_channel,
a49c7ce1 9751 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
db08de94 9752 .enable_rf = rtl8723a_enable_rf,
fc89a41f 9753 .disable_rf = rtl8723a_disable_rf,
747bf237 9754 .usb_quirks = rtl8xxxu_gen1_usb_quirks,
e796dab4 9755 .set_tx_power = rtl8723a_set_tx_power,
f653e690 9756 .update_rate_mask = rtl8723au_update_rate_mask,
7d794eaa 9757 .report_connect = rtl8723au_report_connect,
26f1fad2 9758 .writeN_block_size = 1024,
ed35d094
JS		 9759 .mbox_ext_reg = REG_HMBOX_EXT_0,
9760 .mbox_ext_width = 2,
dbb2896b 9761 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
a49c7ce1 9762 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
8634af5e
JS		 9763 .adda_1t_init = 0x0b1b25a0,
9764 .adda_1t_path_on = 0x0bdb25a0,
9765 .adda_2t_path_on_a = 0x04db25a4,
9766 .adda_2t_path_on_b = 0x0b1b25a4,
24e8e7ec 9767 .trxff_boundary = 0x27ff,
9b323ee9
JS		 9768 .pbp_rx = PBP_PAGE_SIZE_128,
9769 .pbp_tx = PBP_PAGE_SIZE_128,
c606e662 9770 .mactable = rtl8723a_mac_init_table,
26f1fad2
JS		 9771};
9772
35a741fe 9773static struct rtl8xxxu_fileops rtl8723bu_fops = {
3c836d60 9774 .parse_efuse = rtl8723bu_parse_efuse,
35a741fe 9775 .load_firmware = rtl8723bu_load_firmware,
42836db1 9776 .power_on = rtl8723bu_power_on,
fe37d5f6 9777 .power_off = rtl8723bu_power_off,
7d4ccb8b 9778 .reset_8051 = rtl8723bu_reset_8051,
35a741fe 9779 .llt_init = rtl8xxxu_auto_llt_table,
cb877250 9780 .init_phy_bb = rtl8723bu_init_phy_bb,
4062b8ff 9781 .init_phy_rf = rtl8723bu_init_phy_rf,
f0d9f5e9 9782 .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
e1547c53 9783 .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
c3f9506f 9784 .config_channel = rtl8723bu_config_channel,
a49c7ce1 9785 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
3e88ca44 9786 .init_aggregation = rtl8723bu_init_aggregation,
9c79bf95 9787 .init_statistics = rtl8723bu_init_statistics,
db08de94 9788 .enable_rf = rtl8723b_enable_rf,
fc89a41f 9789 .disable_rf = rtl8723b_disable_rf,
747bf237 9790 .usb_quirks = rtl8xxxu_gen2_usb_quirks,
e796dab4 9791 .set_tx_power = rtl8723b_set_tx_power,
f653e690 9792 .update_rate_mask = rtl8723bu_update_rate_mask,
7d794eaa 9793 .report_connect = rtl8723bu_report_connect,
adfc0124 9794 .writeN_block_size = 1024,
ed35d094
JS		 9795 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
9796 .mbox_ext_width = 4,
dbb2896b 9797 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
a49c7ce1 9798 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
0d698dec 9799 .has_s0s1 = 1,
8634af5e
JS		 9800 .adda_1t_init = 0x01c00014,
9801 .adda_1t_path_on = 0x01c00014,
9802 .adda_2t_path_on_a = 0x01c00014,
9803 .adda_2t_path_on_b = 0x01c00014,
24e8e7ec 9804 .trxff_boundary = 0x3f7f,
9b323ee9
JS		 9805 .pbp_rx = PBP_PAGE_SIZE_256,
9806 .pbp_tx = PBP_PAGE_SIZE_256,
c606e662 9807 .mactable = rtl8723b_mac_init_table,
35a741fe
JS		 9808};
9809
c0963772
KV		 9810#ifdef CONFIG_RTL8XXXU_UNTESTED
9811
26f1fad2
JS		 9812static struct rtl8xxxu_fileops rtl8192cu_fops = {
9813 .parse_efuse = rtl8192cu_parse_efuse,
9814 .load_firmware = rtl8192cu_load_firmware,
9815 .power_on = rtl8192cu_power_on,
fe37d5f6 9816 .power_off = rtl8xxxu_power_off,
7d4ccb8b 9817 .reset_8051 = rtl8xxxu_reset_8051,
74b99bed 9818 .llt_init = rtl8xxxu_init_llt_table,
cb877250 9819 .init_phy_bb = rtl8723au_init_phy_bb,
4062b8ff 9820 .init_phy_rf = rtl8192cu_init_phy_rf,
e1547c53 9821 .phy_iq_calibrate = rtl8723au_phy_iq_calibrate,
c3f9506f 9822 .config_channel = rtl8723au_config_channel,
a49c7ce1 9823 .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
db08de94 9824 .enable_rf = rtl8723a_enable_rf,
fc89a41f 9825 .disable_rf = rtl8723a_disable_rf,
747bf237 9826 .usb_quirks = rtl8xxxu_gen1_usb_quirks,
e796dab4 9827 .set_tx_power = rtl8723a_set_tx_power,
f653e690 9828 .update_rate_mask = rtl8723au_update_rate_mask,
7d794eaa 9829 .report_connect = rtl8723au_report_connect,
26f1fad2 9830 .writeN_block_size = 128,
ed35d094
JS		 9831 .mbox_ext_reg = REG_HMBOX_EXT_0,
9832 .mbox_ext_width = 2,
dbb2896b 9833 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
a49c7ce1 9834 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
8634af5e
JS		 9835 .adda_1t_init = 0x0b1b25a0,
9836 .adda_1t_path_on = 0x0bdb25a0,
9837 .adda_2t_path_on_a = 0x04db25a4,
9838 .adda_2t_path_on_b = 0x0b1b25a4,
24e8e7ec 9839 .trxff_boundary = 0x27ff,
9b323ee9
JS		 9840 .pbp_rx = PBP_PAGE_SIZE_128,
9841 .pbp_tx = PBP_PAGE_SIZE_128,
c606e662 9842 .mactable = rtl8723a_mac_init_table,
26f1fad2
JS		 9843};
9844
c0963772
KV		 9845#endif
9846
3307d840
JS		 9847static struct rtl8xxxu_fileops rtl8192eu_fops = {
9848 .parse_efuse = rtl8192eu_parse_efuse,
9849 .load_firmware = rtl8192eu_load_firmware,
c05a9dbf 9850 .power_on = rtl8192eu_power_on,
fe37d5f6 9851 .power_off = rtl8xxxu_power_off,
7d4ccb8b 9852 .reset_8051 = rtl8xxxu_reset_8051,
74b99bed 9853 .llt_init = rtl8xxxu_auto_llt_table,
cb877250 9854 .init_phy_bb = rtl8192eu_init_phy_bb,
4062b8ff 9855 .init_phy_rf = rtl8192eu_init_phy_rf,
f991f4e9 9856 .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
c3f9506f 9857 .config_channel = rtl8723bu_config_channel,
a49c7ce1 9858 .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
db08de94 9859 .enable_rf = rtl8723b_enable_rf,
fc89a41f 9860 .disable_rf = rtl8723b_disable_rf,
747bf237 9861 .usb_quirks = rtl8xxxu_gen2_usb_quirks,
57e42a21 9862 .set_tx_power = rtl8192e_set_tx_power,
91cbe4e7
JS		 9863 .update_rate_mask = rtl8723bu_update_rate_mask,
9864 .report_connect = rtl8723bu_report_connect,
c05a9dbf 9865 .writeN_block_size = 128,
ed35d094
JS		 9866 .mbox_ext_reg = REG_HMBOX_EXT0_8723B,
9867 .mbox_ext_width = 4,
f3fc2511 9868 .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
a49c7ce1 9869 .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
55c0b6ae 9870 .has_s0s1 = 0,
8634af5e
JS		 9871 .adda_1t_init = 0x0fc01616,
9872 .adda_1t_path_on = 0x0fc01616,
9873 .adda_2t_path_on_a = 0x0fc01616,
9874 .adda_2t_path_on_b = 0x0fc01616,
24e8e7ec 9875 .trxff_boundary = 0x3cff,
c606e662 9876 .mactable = rtl8192e_mac_init_table,
89c2a097
JS		 9877 .total_page_num = TX_TOTAL_PAGE_NUM_8192E,
9878 .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E,
9879 .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E,
9880 .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E,
3307d840
JS		 9881};
9882
26f1fad2
JS		 9883static struct usb_device_id dev_table[] = {
9884{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
9885 .driver_info = (unsigned long)&rtl8723au_fops},
9886{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
9887 .driver_info = (unsigned long)&rtl8723au_fops},
9888{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
9889 .driver_info = (unsigned long)&rtl8723au_fops},
3307d840
JS		 9890{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
9891 .driver_info = (unsigned long)&rtl8192eu_fops},
35a741fe
JS		 9892{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
9893 .driver_info = (unsigned long)&rtl8723bu_fops},
033695bd
KV		 9894#ifdef CONFIG_RTL8XXXU_UNTESTED
9895/* Still supported by rtlwifi */
26f1fad2
JS		 9896{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
9897 .driver_info = (unsigned long)&rtl8192cu_fops},
9898{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
9899 .driver_info = (unsigned long)&rtl8192cu_fops},
9900{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
9901 .driver_info = (unsigned long)&rtl8192cu_fops},
9902/* Tested by Larry Finger */
9903{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
9904 .driver_info = (unsigned long)&rtl8192cu_fops},
e1d70c9b
JS		 9905/* Tested by Andrea Merello */
9906{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
9907 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 9908/* Currently untested 8188 series devices */
9909{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
9910 .driver_info = (unsigned long)&rtl8192cu_fops},
9911{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
9912 .driver_info = (unsigned long)&rtl8192cu_fops},
9913{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
9914 .driver_info = (unsigned long)&rtl8192cu_fops},
9915{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
9916 .driver_info = (unsigned long)&rtl8192cu_fops},
9917{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
9918 .driver_info = (unsigned long)&rtl8192cu_fops},
9919{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
9920 .driver_info = (unsigned long)&rtl8192cu_fops},
9921{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
9922 .driver_info = (unsigned long)&rtl8192cu_fops},
9923{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
9924 .driver_info = (unsigned long)&rtl8192cu_fops},
9925{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
9926 .driver_info = (unsigned long)&rtl8192cu_fops},
9927{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
9928 .driver_info = (unsigned long)&rtl8192cu_fops},
9929{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
9930 .driver_info = (unsigned long)&rtl8192cu_fops},
9931{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
9932 .driver_info = (unsigned long)&rtl8192cu_fops},
9933{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
9934 .driver_info = (unsigned long)&rtl8192cu_fops},
9935{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
9936 .driver_info = (unsigned long)&rtl8192cu_fops},
9937{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
9938 .driver_info = (unsigned long)&rtl8192cu_fops},
9939{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
9940 .driver_info = (unsigned long)&rtl8192cu_fops},
9941{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
9942 .driver_info = (unsigned long)&rtl8192cu_fops},
9943{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
9944 .driver_info = (unsigned long)&rtl8192cu_fops},
9945{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
9946 .driver_info = (unsigned long)&rtl8192cu_fops},
9947{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
9948 .driver_info = (unsigned long)&rtl8192cu_fops},
9949{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
9950 .driver_info = (unsigned long)&rtl8192cu_fops},
9951{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
9952 .driver_info = (unsigned long)&rtl8192cu_fops},
9953{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
9954 .driver_info = (unsigned long)&rtl8192cu_fops},
9955{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
9956 .driver_info = (unsigned long)&rtl8192cu_fops},
9957{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
9958 .driver_info = (unsigned long)&rtl8192cu_fops},
9959{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
9960 .driver_info = (unsigned long)&rtl8192cu_fops},
9961{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
9962 .driver_info = (unsigned long)&rtl8192cu_fops},
9963{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
9964 .driver_info = (unsigned long)&rtl8192cu_fops},
9965{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
9966 .driver_info = (unsigned long)&rtl8192cu_fops},
9967{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
9968 .driver_info = (unsigned long)&rtl8192cu_fops},
9969{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
9970 .driver_info = (unsigned long)&rtl8192cu_fops},
9971{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
9972 .driver_info = (unsigned long)&rtl8192cu_fops},
9973{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
9974 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 9975{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
9976 .driver_info = (unsigned long)&rtl8192cu_fops},
9977{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
9978 .driver_info = (unsigned long)&rtl8192cu_fops},
9979{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
9980 .driver_info = (unsigned long)&rtl8192cu_fops},
9981{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
9982 .driver_info = (unsigned long)&rtl8192cu_fops},
9983{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
9984 .driver_info = (unsigned long)&rtl8192cu_fops},
9985{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
9986 .driver_info = (unsigned long)&rtl8192cu_fops},
9987{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
9988 .driver_info = (unsigned long)&rtl8192cu_fops},
9989/* Currently untested 8192 series devices */
9990{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
9991 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 9992{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
9993 .driver_info = (unsigned long)&rtl8192cu_fops},
9994{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
9995 .driver_info = (unsigned long)&rtl8192cu_fops},
9996{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
9997 .driver_info = (unsigned long)&rtl8192cu_fops},
9998{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
9999 .driver_info = (unsigned long)&rtl8192cu_fops},
10000{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
10001 .driver_info = (unsigned long)&rtl8192cu_fops},
10002{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
10003 .driver_info = (unsigned long)&rtl8192cu_fops},
10004{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
10005 .driver_info = (unsigned long)&rtl8192cu_fops},
10006{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
10007 .driver_info = (unsigned long)&rtl8192cu_fops},
10008{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
10009 .driver_info = (unsigned long)&rtl8192cu_fops},
10010{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
10011 .driver_info = (unsigned long)&rtl8192cu_fops},
10012{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
10013 .driver_info = (unsigned long)&rtl8192cu_fops},
10014{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
10015 .driver_info = (unsigned long)&rtl8192cu_fops},
10016{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
10017 .driver_info = (unsigned long)&rtl8192cu_fops},
10018{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
10019 .driver_info = (unsigned long)&rtl8192cu_fops},
10020{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
10021 .driver_info = (unsigned long)&rtl8192cu_fops},
10022{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
10023 .driver_info = (unsigned long)&rtl8192cu_fops},
10024{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
10025 .driver_info = (unsigned long)&rtl8192cu_fops},
10026{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
10027 .driver_info = (unsigned long)&rtl8192cu_fops},
10028{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
10029 .driver_info = (unsigned long)&rtl8192cu_fops},
10030{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
10031 .driver_info = (unsigned long)&rtl8192cu_fops},
10032{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
10033 .driver_info = (unsigned long)&rtl8192cu_fops},
10034{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
10035 .driver_info = (unsigned long)&rtl8192cu_fops},
10036{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
10037 .driver_info = (unsigned long)&rtl8192cu_fops},
10038#endif
10039{ }
10040};
10041
10042static struct usb_driver rtl8xxxu_driver = {
10043 .name = DRIVER_NAME,
10044 .probe = rtl8xxxu_probe,
10045 .disconnect = rtl8xxxu_disconnect,
10046 .id_table = dev_table,
10047 .disable_hub_initiated_lpm = 1,
10048};
10049
10050static int __init rtl8xxxu_module_init(void)
10051{
10052 int res;
10053
10054 res = usb_register(&rtl8xxxu_driver);
10055 if (res < 0)
10056 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
10057
10058 return res;
10059}
10060
10061static void __exit rtl8xxxu_module_exit(void)
10062{
10063 usb_deregister(&rtl8xxxu_driver);
10064}
10065
10066
10067MODULE_DEVICE_TABLE(usb, dev_table);
10068
10069module_init(rtl8xxxu_module_init);
10070module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
This page took 0.741947 seconds and 5 git commands to generate.