Commit | Line | Data |
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26f1fad2 | 1 | /* |
eb188062 | 2 | * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com> |
26f1fad2 JS |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of version 2 of the GNU General Public License as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * Register definitions taken from original Realtek rtl8723au driver | |
14 | */ | |
15 | ||
16 | #include <asm/byteorder.h> | |
17 | ||
18 | #define RTL8XXXU_DEBUG_REG_WRITE 0x01 | |
19 | #define RTL8XXXU_DEBUG_REG_READ 0x02 | |
20 | #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04 | |
21 | #define RTL8XXXU_DEBUG_RFREG_READ 0x08 | |
22 | #define RTL8XXXU_DEBUG_CHANNEL 0x10 | |
23 | #define RTL8XXXU_DEBUG_TX 0x20 | |
24 | #define RTL8XXXU_DEBUG_TX_DUMP 0x40 | |
25 | #define RTL8XXXU_DEBUG_RX 0x80 | |
26 | #define RTL8XXXU_DEBUG_RX_DUMP 0x100 | |
27 | #define RTL8XXXU_DEBUG_USB 0x200 | |
28 | #define RTL8XXXU_DEBUG_KEY 0x400 | |
29 | #define RTL8XXXU_DEBUG_H2C 0x800 | |
30 | #define RTL8XXXU_DEBUG_ACTION 0x1000 | |
31 | #define RTL8XXXU_DEBUG_EFUSE 0x2000 | |
32 | ||
33 | #define RTW_USB_CONTROL_MSG_TIMEOUT 500 | |
34 | #define RTL8XXXU_MAX_REG_POLL 500 | |
35 | #define USB_INTR_CONTENT_LENGTH 56 | |
36 | ||
35a741fe | 37 | #define RTL8XXXU_OUT_ENDPOINTS 4 |
26f1fad2 JS |
38 | |
39 | #define REALTEK_USB_READ 0xc0 | |
40 | #define REALTEK_USB_WRITE 0x40 | |
41 | #define REALTEK_USB_CMD_REQ 0x05 | |
42 | #define REALTEK_USB_CMD_IDX 0x00 | |
43 | ||
44 | #define TX_TOTAL_PAGE_NUM 0xf8 | |
80805aa5 | 45 | #define TX_TOTAL_PAGE_NUM_8192E 0xf3 |
44abaa08 | 46 | #define TX_TOTAL_PAGE_NUM_8723B 0xf7 |
26f1fad2 JS |
47 | /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ |
48 | #define TX_PAGE_NUM_PUBQ 0xe7 | |
49 | #define TX_PAGE_NUM_HI_PQ 0x0c | |
50 | #define TX_PAGE_NUM_LO_PQ 0x02 | |
51 | #define TX_PAGE_NUM_NORM_PQ 0x02 | |
52 | ||
89c2a097 JS |
53 | #define TX_PAGE_NUM_PUBQ_8192E 0xe7 |
54 | #define TX_PAGE_NUM_HI_PQ_8192E 0x08 | |
55 | #define TX_PAGE_NUM_LO_PQ_8192E 0x0c | |
56 | #define TX_PAGE_NUM_NORM_PQ_8192E 0x00 | |
57 | ||
44abaa08 JS |
58 | #define TX_PAGE_NUM_PUBQ_8723B 0xe7 |
59 | #define TX_PAGE_NUM_HI_PQ_8723B 0x0c | |
60 | #define TX_PAGE_NUM_LO_PQ_8723B 0x02 | |
61 | #define TX_PAGE_NUM_NORM_PQ_8723B 0x02 | |
62 | ||
26f1fad2 JS |
63 | #define RTL_FW_PAGE_SIZE 4096 |
64 | #define RTL8XXXU_FIRMWARE_POLL_MAX 1000 | |
65 | ||
66 | #define RTL8723A_CHANNEL_GROUPS 3 | |
67 | #define RTL8723A_MAX_RF_PATHS 2 | |
21db9973 | 68 | #define RTL8723B_CHANNEL_GROUPS 6 |
3be26999 | 69 | #define RTL8723B_TX_COUNT 4 |
4a0d7db5 | 70 | #define RTL8723B_MAX_RF_PATHS 4 |
21db9973 | 71 | #define RTL8XXXU_MAX_CHANNEL_GROUPS 6 |
26f1fad2 JS |
72 | #define RF6052_MAX_TX_PWR 0x3f |
73 | ||
3307d840 JS |
74 | #define EFUSE_MAP_LEN 512 |
75 | #define EFUSE_MAX_SECTION_8723A 64 | |
26f1fad2 JS |
76 | #define EFUSE_REAL_CONTENT_LEN_8723A 512 |
77 | #define EFUSE_BT_MAP_LEN_8723A 1024 | |
78 | #define EFUSE_MAX_WORD_UNIT 4 | |
79 | ||
ba17d824 JS |
80 | enum rtl8xxxu_rtl_chip { |
81 | RTL8192S = 0x81920, | |
82 | RTL8191S = 0x81910, | |
83 | RTL8192C = 0x8192c, | |
84 | RTL8191C = 0x8191c, | |
85 | RTL8188C = 0x8188c, | |
86 | RTL8188R = 0x81889, | |
87 | RTL8192D = 0x8192d, | |
88 | RTL8723A = 0x8723a, | |
89 | RTL8188E = 0x8188e, | |
90 | RTL8812 = 0x88120, | |
91 | RTL8821 = 0x88210, | |
92 | RTL8192E = 0x8192e, | |
93 | RTL8191E = 0x8191e, | |
94 | RTL8723B = 0x8723b, | |
95 | RTL8814A = 0x8814a, | |
96 | RTL8881A = 0x8881a, | |
97 | RTL8821B = 0x8821b, | |
98 | RTL8822B = 0x8822b, | |
99 | RTL8703B = 0x8703b, | |
100 | RTL8195A = 0x8195a, | |
101 | RTL8188F = 0x8188f | |
102 | }; | |
103 | ||
b18cdfdb JS |
104 | enum rtl8xxxu_rx_type { |
105 | RX_TYPE_DATA_PKT = 0, | |
106 | RX_TYPE_C2H = 1, | |
107 | RX_TYPE_ERROR = -1 | |
108 | }; | |
109 | ||
a49c7ce1 | 110 | struct rtl8xxxu_rxdesc16 { |
26f1fad2 JS |
111 | #ifdef __LITTLE_ENDIAN |
112 | u32 pktlen:14; | |
113 | u32 crc32:1; | |
114 | u32 icverr:1; | |
115 | u32 drvinfo_sz:4; | |
116 | u32 security:3; | |
117 | u32 qos:1; | |
118 | u32 shift:2; | |
119 | u32 phy_stats:1; | |
120 | u32 swdec:1; | |
121 | u32 ls:1; | |
122 | u32 fs:1; | |
123 | u32 eor:1; | |
124 | u32 own:1; | |
125 | ||
126 | u32 macid:5; | |
127 | u32 tid:4; | |
128 | u32 hwrsvd:4; | |
129 | u32 amsdu:1; | |
130 | u32 paggr:1; | |
131 | u32 faggr:1; | |
132 | u32 a1fit:4; | |
133 | u32 a2fit:4; | |
134 | u32 pam:1; | |
135 | u32 pwr:1; | |
136 | u32 md:1; | |
137 | u32 mf:1; | |
138 | u32 type:2; | |
139 | u32 mc:1; | |
140 | u32 bc:1; | |
141 | ||
142 | u32 seq:12; | |
143 | u32 frag:4; | |
41892729 JS |
144 | u32 pkt_cnt:8; |
145 | u32 reserved:6; | |
26f1fad2 JS |
146 | u32 nextind:1; |
147 | u32 reserved0:1; | |
148 | ||
149 | u32 rxmcs:6; | |
150 | u32 rxht:1; | |
151 | u32 gf:1; | |
152 | u32 splcp:1; | |
153 | u32 bw:1; | |
154 | u32 htc:1; | |
155 | u32 eosp:1; | |
156 | u32 bssidfit:2; | |
157 | u32 reserved1:16; | |
158 | u32 unicastwake:1; | |
159 | u32 magicwake:1; | |
160 | ||
161 | u32 pattern0match:1; | |
162 | u32 pattern1match:1; | |
163 | u32 pattern2match:1; | |
164 | u32 pattern3match:1; | |
165 | u32 pattern4match:1; | |
166 | u32 pattern5match:1; | |
167 | u32 pattern6match:1; | |
168 | u32 pattern7match:1; | |
169 | u32 pattern8match:1; | |
170 | u32 pattern9match:1; | |
171 | u32 patternamatch:1; | |
172 | u32 patternbmatch:1; | |
173 | u32 patterncmatch:1; | |
174 | u32 reserved2:19; | |
175 | #else | |
176 | u32 own:1; | |
177 | u32 eor:1; | |
178 | u32 fs:1; | |
179 | u32 ls:1; | |
180 | u32 swdec:1; | |
181 | u32 phy_stats:1; | |
182 | u32 shift:2; | |
183 | u32 qos:1; | |
184 | u32 security:3; | |
185 | u32 drvinfo_sz:4; | |
186 | u32 icverr:1; | |
187 | u32 crc32:1; | |
188 | u32 pktlen:14; | |
189 | ||
190 | u32 bc:1; | |
191 | u32 mc:1; | |
192 | u32 type:2; | |
193 | u32 mf:1; | |
194 | u32 md:1; | |
195 | u32 pwr:1; | |
196 | u32 pam:1; | |
197 | u32 a2fit:4; | |
198 | u32 a1fit:4; | |
199 | u32 faggr:1; | |
200 | u32 paggr:1; | |
201 | u32 amsdu:1; | |
202 | u32 hwrsvd:4; | |
203 | u32 tid:4; | |
204 | u32 macid:5; | |
205 | ||
206 | u32 reserved0:1; | |
207 | u32 nextind:1; | |
41892729 JS |
208 | u32 reserved:6; |
209 | u32 pkt_cnt:8; | |
26f1fad2 JS |
210 | u32 frag:4; |
211 | u32 seq:12; | |
212 | ||
213 | u32 magicwake:1; | |
214 | u32 unicastwake:1; | |
215 | u32 reserved1:16; | |
216 | u32 bssidfit:2; | |
217 | u32 eosp:1; | |
218 | u32 htc:1; | |
219 | u32 bw:1; | |
220 | u32 splcp:1; | |
221 | u32 gf:1; | |
222 | u32 rxht:1; | |
223 | u32 rxmcs:6; | |
224 | ||
225 | u32 reserved2:19; | |
226 | u32 patterncmatch:1; | |
227 | u32 patternbmatch:1; | |
228 | u32 patternamatch:1; | |
229 | u32 pattern9match:1; | |
230 | u32 pattern8match:1; | |
231 | u32 pattern7match:1; | |
232 | u32 pattern6match:1; | |
233 | u32 pattern5match:1; | |
234 | u32 pattern4match:1; | |
235 | u32 pattern3match:1; | |
236 | u32 pattern2match:1; | |
237 | u32 pattern1match:1; | |
238 | u32 pattern0match:1; | |
239 | #endif | |
240 | __le32 tsfl; | |
241 | #if 0 | |
242 | u32 bassn:12; | |
243 | u32 bavld:1; | |
244 | u32 reserved3:19; | |
245 | #endif | |
246 | }; | |
247 | ||
a49c7ce1 | 248 | struct rtl8xxxu_rxdesc24 { |
a6c80d21 JS |
249 | #ifdef __LITTLE_ENDIAN |
250 | u32 pktlen:14; | |
251 | u32 crc32:1; | |
252 | u32 icverr:1; | |
253 | u32 drvinfo_sz:4; | |
254 | u32 security:3; | |
255 | u32 qos:1; | |
256 | u32 shift:2; | |
257 | u32 phy_stats:1; | |
258 | u32 swdec:1; | |
259 | u32 ls:1; | |
260 | u32 fs:1; | |
261 | u32 eor:1; | |
262 | u32 own:1; | |
263 | ||
264 | u32 macid:7; | |
265 | u32 dummy1_0:1; | |
266 | u32 tid:4; | |
267 | u32 dummy1_1:1; | |
268 | u32 amsdu:1; | |
269 | u32 rxid_match:1; | |
270 | u32 paggr:1; | |
271 | u32 a1fit:4; /* 16 */ | |
272 | u32 chkerr:1; | |
273 | u32 ipver:1; | |
274 | u32 tcpudp:1; | |
275 | u32 chkvld:1; | |
276 | u32 pam:1; | |
277 | u32 pwr:1; | |
278 | u32 more_data:1; | |
279 | u32 more_frag:1; | |
280 | u32 type:2; | |
281 | u32 mc:1; | |
282 | u32 bc:1; | |
283 | ||
284 | u32 seq:12; | |
285 | u32 frag:4; | |
286 | u32 rx_is_qos:1; /* 16 */ | |
287 | u32 dummy2_0:1; | |
288 | u32 wlanhd_iv_len:6; | |
289 | u32 dummy2_1:4; | |
290 | u32 rpt_sel:1; | |
291 | u32 dummy2_2:3; | |
292 | ||
293 | u32 rxmcs:7; | |
294 | u32 dummy3_0:3; | |
295 | u32 htc:1; | |
296 | u32 eosp:1; | |
297 | u32 bssidfit:2; | |
298 | u32 dummy3_1:2; | |
299 | u32 usb_agg_pktnum:8; /* 16 */ | |
300 | u32 dummy3_2:5; | |
301 | u32 pattern_match:1; | |
302 | u32 unicast_match:1; | |
303 | u32 magic_match:1; | |
304 | ||
305 | u32 splcp:1; | |
306 | u32 ldcp:1; | |
307 | u32 stbc:1; | |
308 | u32 dummy4_0:1; | |
309 | u32 bw:2; | |
310 | u32 dummy4_1:26; | |
311 | #else | |
312 | u32 own:1; | |
313 | u32 eor:1; | |
314 | u32 fs:1; | |
315 | u32 ls:1; | |
316 | u32 swdec:1; | |
317 | u32 phy_stats:1; | |
318 | u32 shift:2; | |
319 | u32 qos:1; | |
320 | u32 security:3; | |
321 | u32 drvinfo_sz:4; | |
322 | u32 icverr:1; | |
323 | u32 crc32:1; | |
324 | u32 pktlen:14; | |
325 | ||
326 | u32 bc:1; | |
327 | u32 mc:1; | |
328 | u32 type:2; | |
329 | u32 mf:1; | |
330 | u32 md:1; | |
331 | u32 pwr:1; | |
332 | u32 pam:1; | |
333 | u32 a2fit:4; | |
334 | u32 a1fit:4; | |
335 | u32 faggr:1; | |
336 | u32 paggr:1; | |
337 | u32 amsdu:1; | |
338 | u32 hwrsvd:4; | |
339 | u32 tid:4; | |
340 | u32 macid:5; | |
341 | ||
342 | u32 dummy2_2:3; | |
343 | u32 rpt_sel:1; | |
344 | u32 dummy2_1:4; | |
345 | u32 wlanhd_iv_len:6; | |
346 | u32 dummy2_0:1; | |
347 | u32 rx_is_qos:1; | |
348 | u32 frag:4; /* 16 */ | |
349 | u32 seq:12; | |
350 | ||
351 | u32 magic_match:1; | |
352 | u32 unicast_match:1; | |
353 | u32 pattern_match:1; | |
354 | u32 dummy3_2:5; | |
355 | u32 usb_agg_pktnum:8; | |
356 | u32 dummy3_1:2; /* 16 */ | |
357 | u32 bssidfit:2; | |
358 | u32 eosp:1; | |
359 | u32 htc:1; | |
360 | u32 dummy3_0:3; | |
361 | u32 rxmcs:7; | |
362 | ||
363 | u32 dumm4_1:26; | |
364 | u32 bw:2; | |
365 | u32 dummy4_0:1; | |
366 | u32 stbc:1; | |
367 | u32 ldcp:1; | |
368 | u32 splcp:1; | |
369 | #endif | |
370 | __le32 tsfl; | |
371 | }; | |
372 | ||
dbb2896b | 373 | struct rtl8xxxu_txdesc32 { |
26f1fad2 JS |
374 | __le16 pkt_size; |
375 | u8 pkt_offset; | |
376 | u8 txdw0; | |
377 | __le32 txdw1; | |
378 | __le32 txdw2; | |
379 | __le32 txdw3; | |
380 | __le32 txdw4; | |
381 | __le32 txdw5; | |
382 | __le32 txdw6; | |
383 | __le16 csum; | |
384 | __le16 txdw7; | |
385 | }; | |
386 | ||
dbb2896b | 387 | struct rtl8xxxu_txdesc40 { |
80491a1f JS |
388 | __le16 pkt_size; |
389 | u8 pkt_offset; | |
390 | u8 txdw0; | |
391 | __le32 txdw1; | |
392 | __le32 txdw2; | |
393 | __le32 txdw3; | |
394 | __le32 txdw4; | |
395 | __le32 txdw5; | |
396 | __le32 txdw6; | |
397 | __le16 csum; | |
398 | __le16 txdw7; | |
399 | __le32 txdw8; | |
400 | __le32 txdw9; | |
401 | }; | |
402 | ||
26f1fad2 JS |
403 | /* CCK Rates, TxHT = 0 */ |
404 | #define DESC_RATE_1M 0x00 | |
405 | #define DESC_RATE_2M 0x01 | |
406 | #define DESC_RATE_5_5M 0x02 | |
407 | #define DESC_RATE_11M 0x03 | |
408 | ||
409 | /* OFDM Rates, TxHT = 0 */ | |
410 | #define DESC_RATE_6M 0x04 | |
411 | #define DESC_RATE_9M 0x05 | |
412 | #define DESC_RATE_12M 0x06 | |
413 | #define DESC_RATE_18M 0x07 | |
414 | #define DESC_RATE_24M 0x08 | |
415 | #define DESC_RATE_36M 0x09 | |
416 | #define DESC_RATE_48M 0x0a | |
417 | #define DESC_RATE_54M 0x0b | |
418 | ||
419 | /* MCS Rates, TxHT = 1 */ | |
420 | #define DESC_RATE_MCS0 0x0c | |
421 | #define DESC_RATE_MCS1 0x0d | |
422 | #define DESC_RATE_MCS2 0x0e | |
423 | #define DESC_RATE_MCS3 0x0f | |
424 | #define DESC_RATE_MCS4 0x10 | |
425 | #define DESC_RATE_MCS5 0x11 | |
426 | #define DESC_RATE_MCS6 0x12 | |
427 | #define DESC_RATE_MCS7 0x13 | |
428 | #define DESC_RATE_MCS8 0x14 | |
429 | #define DESC_RATE_MCS9 0x15 | |
430 | #define DESC_RATE_MCS10 0x16 | |
431 | #define DESC_RATE_MCS11 0x17 | |
432 | #define DESC_RATE_MCS12 0x18 | |
433 | #define DESC_RATE_MCS13 0x19 | |
434 | #define DESC_RATE_MCS14 0x1a | |
435 | #define DESC_RATE_MCS15 0x1b | |
436 | #define DESC_RATE_MCS15_SG 0x1c | |
437 | #define DESC_RATE_MCS32 0x20 | |
438 | ||
439 | #define TXDESC_OFFSET_SZ 0 | |
440 | #define TXDESC_OFFSET_SHT 16 | |
441 | #if 0 | |
442 | #define TXDESC_BMC BIT(24) | |
443 | #define TXDESC_LSG BIT(26) | |
444 | #define TXDESC_FSG BIT(27) | |
445 | #define TXDESC_OWN BIT(31) | |
446 | #else | |
447 | #define TXDESC_BROADMULTICAST BIT(0) | |
0249258d | 448 | #define TXDESC_HTC BIT(1) |
26f1fad2 JS |
449 | #define TXDESC_LAST_SEGMENT BIT(2) |
450 | #define TXDESC_FIRST_SEGMENT BIT(3) | |
0249258d JS |
451 | #define TXDESC_LINIP BIT(4) |
452 | #define TXDESC_NO_ACM BIT(5) | |
453 | #define TXDESC_GF BIT(6) | |
26f1fad2 JS |
454 | #define TXDESC_OWN BIT(7) |
455 | #endif | |
456 | ||
457 | /* Word 1 */ | |
ce2d1dbb JS |
458 | /* |
459 | * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are | |
460 | * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. | |
461 | */ | |
26f1fad2 | 462 | #define TXDESC_PKT_OFFSET_SZ 0 |
33f37249 JS |
463 | #define TXDESC32_AGG_ENABLE BIT(5) |
464 | #define TXDESC32_AGG_BREAK BIT(6) | |
465 | #define TXDESC40_MACID_SHIFT 0 | |
466 | #define TXDESC40_MACID_MASK 0x00f0 | |
26f1fad2 JS |
467 | #define TXDESC_QUEUE_SHIFT 8 |
468 | #define TXDESC_QUEUE_MASK 0x1f00 | |
469 | #define TXDESC_QUEUE_BK 0x2 | |
470 | #define TXDESC_QUEUE_BE 0x0 | |
471 | #define TXDESC_QUEUE_VI 0x5 | |
472 | #define TXDESC_QUEUE_VO 0x7 | |
473 | #define TXDESC_QUEUE_BEACON 0x10 | |
474 | #define TXDESC_QUEUE_HIGH 0x11 | |
475 | #define TXDESC_QUEUE_MGNT 0x12 | |
476 | #define TXDESC_QUEUE_CMD 0x13 | |
477 | #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1) | |
33f37249 JS |
478 | #define TXDESC40_RDG_NAV_EXT BIT(13) |
479 | #define TXDESC40_LSIG_TXOP_ENABLE BIT(14) | |
480 | #define TXDESC40_PIFS BIT(15) | |
26f1fad2 JS |
481 | |
482 | #define DESC_RATE_ID_SHIFT 16 | |
483 | #define DESC_RATE_ID_MASK 0xf | |
484 | #define TXDESC_NAVUSEHDR BIT(20) | |
485 | #define TXDESC_SEC_RC4 0x00400000 | |
486 | #define TXDESC_SEC_AES 0x00c00000 | |
487 | #define TXDESC_PKT_OFFSET_SHIFT 26 | |
488 | #define TXDESC_AGG_EN BIT(29) | |
489 | #define TXDESC_HWPC BIT(31) | |
490 | ||
491 | /* Word 2 */ | |
33f37249 JS |
492 | #define TXDESC40_PAID_SHIFT 0 |
493 | #define TXDESC40_PAID_MASK 0x1ff | |
494 | #define TXDESC40_CCA_RTS_SHIFT 10 | |
495 | #define TXDESC40_CCA_RTS_MASK 0xc00 | |
496 | #define TXDESC40_AGG_ENABLE BIT(12) | |
497 | #define TXDESC40_RDG_ENABLE BIT(13) | |
498 | #define TXDESC40_AGG_BREAK BIT(16) | |
499 | #define TXDESC40_MORE_FRAG BIT(17) | |
500 | #define TXDESC40_RAW BIT(18) | |
501 | #define TXDESC32_ACK_REPORT BIT(19) | |
502 | #define TXDESC40_SPE_RPT BIT(19) | |
26f1fad2 | 503 | #define TXDESC_AMPDU_DENSITY_SHIFT 20 |
33f37249 | 504 | #define TXDESC40_BT_INT BIT(23) |
169bc5cb | 505 | #define TXDESC40_GID_SHIFT 24 |
26f1fad2 JS |
506 | |
507 | /* Word 3 */ | |
33f37249 JS |
508 | #define TXDESC40_USE_DRIVER_RATE BIT(8) |
509 | #define TXDESC40_CTS_SELF_ENABLE BIT(11) | |
510 | #define TXDESC40_RTS_CTS_ENABLE BIT(12) | |
511 | #define TXDESC40_HW_RTS_ENABLE BIT(13) | |
512 | #define TXDESC32_SEQ_SHIFT 16 | |
513 | #define TXDESC32_SEQ_MASK 0x0fff0000 | |
26f1fad2 JS |
514 | |
515 | /* Word 4 */ | |
33f37249 JS |
516 | #define TXDESC32_RTS_RATE_SHIFT 0 |
517 | #define TXDESC32_RTS_RATE_MASK 0x3f | |
518 | #define TXDESC32_QOS BIT(6) | |
519 | #define TXDESC32_HW_SEQ_ENABLE BIT(7) | |
520 | #define TXDESC32_USE_DRIVER_RATE BIT(8) | |
26f1fad2 | 521 | #define TXDESC_DISABLE_DATA_FB BIT(10) |
33f37249 JS |
522 | #define TXDESC32_CTS_SELF_ENABLE BIT(11) |
523 | #define TXDESC32_RTS_CTS_ENABLE BIT(12) | |
524 | #define TXDESC32_HW_RTS_ENABLE BIT(13) | |
26f1fad2 JS |
525 | #define TXDESC_PRIME_CH_OFF_LOWER BIT(20) |
526 | #define TXDESC_PRIME_CH_OFF_UPPER BIT(21) | |
33f37249 | 527 | #define TXDESC32_SHORT_PREAMBLE BIT(24) |
26f1fad2 JS |
528 | #define TXDESC_DATA_BW BIT(25) |
529 | #define TXDESC_RTS_DATA_BW BIT(27) | |
530 | #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28) | |
531 | #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29) | |
33f37249 JS |
532 | #define TXDESC40_DATA_RATE_FB_SHIFT 8 |
533 | #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00 | |
534 | #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17) | |
535 | #define TXDESC40_RETRY_LIMIT_SHIFT 18 | |
536 | #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000 | |
537 | #define TXDESC40_RTS_RATE_SHIFT 24 | |
538 | #define TXDESC40_RTS_RATE_MASK 0x3f000000 | |
26f1fad2 JS |
539 | |
540 | /* Word 5 */ | |
33f37249 | 541 | #define TXDESC40_SHORT_PREAMBLE BIT(4) |
1df1de34 | 542 | #define TXDESC32_SHORT_GI BIT(6) |
26f1fad2 | 543 | #define TXDESC_CCX_TAG BIT(7) |
33f37249 JS |
544 | #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17) |
545 | #define TXDESC32_RETRY_LIMIT_SHIFT 18 | |
546 | #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000 | |
26f1fad2 JS |
547 | |
548 | /* Word 6 */ | |
549 | #define TXDESC_MAX_AGG_SHIFT 11 | |
550 | ||
2098bfb5 | 551 | /* Word 8 */ |
33f37249 | 552 | #define TXDESC40_HW_SEQ_ENABLE BIT(15) |
2098bfb5 | 553 | |
cc2646d4 | 554 | /* Word 9 */ |
33f37249 JS |
555 | #define TXDESC40_SEQ_SHIFT 12 |
556 | #define TXDESC40_SEQ_MASK 0x00fff000 | |
cc2646d4 | 557 | |
26f1fad2 JS |
558 | struct phy_rx_agc_info { |
559 | #ifdef __LITTLE_ENDIAN | |
560 | u8 gain:7, trsw:1; | |
561 | #else | |
562 | u8 trsw:1, gain:7; | |
563 | #endif | |
564 | }; | |
565 | ||
566 | struct rtl8723au_phy_stats { | |
567 | struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS]; | |
568 | u8 ch_corr[RTL8723A_MAX_RF_PATHS]; | |
569 | u8 cck_sig_qual_ofdm_pwdb_all; | |
570 | u8 cck_agc_rpt_ofdm_cfosho_a; | |
571 | u8 cck_rpt_b_ofdm_cfosho_b; | |
572 | u8 reserved_1; | |
573 | u8 noise_power_db_msb; | |
574 | u8 path_cfotail[RTL8723A_MAX_RF_PATHS]; | |
575 | u8 pcts_mask[RTL8723A_MAX_RF_PATHS]; | |
576 | s8 stream_rxevm[RTL8723A_MAX_RF_PATHS]; | |
577 | u8 path_rxsnr[RTL8723A_MAX_RF_PATHS]; | |
578 | u8 noise_power_db_lsb; | |
579 | u8 reserved_2[3]; | |
580 | u8 stream_csi[RTL8723A_MAX_RF_PATHS]; | |
581 | u8 stream_target_csi[RTL8723A_MAX_RF_PATHS]; | |
582 | s8 sig_evm; | |
583 | u8 reserved_3; | |
584 | ||
585 | #ifdef __LITTLE_ENDIAN | |
586 | u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ | |
587 | u8 sgi_en:1; | |
588 | u8 rxsc:2; | |
589 | u8 idle_long:1; | |
590 | u8 r_ant_train_en:1; | |
591 | u8 antenna_select_b:1; | |
592 | u8 antenna_select:1; | |
593 | #else /* _BIG_ENDIAN_ */ | |
594 | u8 antenna_select:1; | |
595 | u8 antenna_select_b:1; | |
596 | u8 r_ant_train_en:1; | |
597 | u8 idle_long:1; | |
598 | u8 rxsc:2; | |
599 | u8 sgi_en:1; | |
600 | u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ | |
601 | #endif | |
602 | }; | |
603 | ||
604 | /* | |
605 | * Regs to backup | |
606 | */ | |
607 | #define RTL8XXXU_ADDA_REGS 16 | |
608 | #define RTL8XXXU_MAC_REGS 4 | |
609 | #define RTL8XXXU_BB_REGS 9 | |
610 | ||
611 | struct rtl8xxxu_firmware_header { | |
612 | __le16 signature; /* 92C0: test chip; 92C, | |
613 | 88C0: test chip; | |
614 | 88C1: MP A-cut; | |
615 | 92C1: MP A-cut */ | |
616 | u8 category; /* AP/NIC and USB/PCI */ | |
617 | u8 function; | |
618 | ||
619 | __le16 major_version; /* FW Version */ | |
620 | u8 minor_version; /* FW Subversion, default 0x00 */ | |
621 | u8 reserved1; | |
622 | ||
623 | u8 month; /* Release time Month field */ | |
624 | u8 date; /* Release time Date field */ | |
625 | u8 hour; /* Release time Hour field */ | |
626 | u8 minute; /* Release time Minute field */ | |
627 | ||
628 | __le16 ramcodesize; /* Size of RAM code */ | |
629 | u16 reserved2; | |
630 | ||
631 | __le32 svn_idx; /* SVN entry index */ | |
632 | u32 reserved3; | |
633 | ||
634 | u32 reserved4; | |
635 | u32 reserved5; | |
636 | ||
637 | u8 data[0]; | |
638 | }; | |
639 | ||
2fc0b8e5 JS |
640 | /* |
641 | * 8723au/8192cu/8188ru required base power index offset tables. | |
642 | */ | |
643 | struct rtl8xxxu_power_base { | |
644 | u32 reg_0e00; | |
645 | u32 reg_0e04; | |
646 | u32 reg_0e08; | |
647 | u32 reg_086c; | |
648 | ||
649 | u32 reg_0e10; | |
650 | u32 reg_0e14; | |
651 | u32 reg_0e18; | |
652 | u32 reg_0e1c; | |
653 | ||
654 | u32 reg_0830; | |
655 | u32 reg_0834; | |
656 | u32 reg_0838; | |
657 | u32 reg_086c_2; | |
658 | ||
659 | u32 reg_083c; | |
660 | u32 reg_0848; | |
661 | u32 reg_084c; | |
662 | u32 reg_0868; | |
663 | }; | |
664 | ||
26f1fad2 JS |
665 | /* |
666 | * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 | |
667 | */ | |
668 | struct rtl8723au_idx { | |
669 | #ifdef __LITTLE_ENDIAN | |
670 | int a:4; | |
671 | int b:4; | |
672 | #else | |
673 | int b:4; | |
674 | int a:4; | |
675 | #endif | |
676 | } __attribute__((packed)); | |
677 | ||
678 | struct rtl8723au_efuse { | |
679 | __le16 rtl_id; | |
680 | u8 res0[0xe]; | |
681 | u8 cck_tx_power_index_A[3]; /* 0x10 */ | |
682 | u8 cck_tx_power_index_B[3]; | |
683 | u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */ | |
684 | u8 ht40_1s_tx_power_index_B[3]; | |
685 | /* | |
686 | * The following entries are half-bytes split as: | |
687 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed | |
688 | */ | |
689 | struct rtl8723au_idx ht20_tx_power_index_diff[3]; | |
690 | struct rtl8723au_idx ofdm_tx_power_index_diff[3]; | |
691 | struct rtl8723au_idx ht40_max_power_offset[3]; | |
692 | struct rtl8723au_idx ht20_max_power_offset[3]; | |
693 | u8 channel_plan; /* 0x28 */ | |
694 | u8 tssi_a; | |
695 | u8 thermal_meter; | |
696 | u8 rf_regulatory; | |
697 | u8 rf_option_2; | |
698 | u8 rf_option_3; | |
699 | u8 rf_option_4; | |
700 | u8 res7; | |
701 | u8 version /* 0x30 */; | |
702 | u8 customer_id_major; | |
703 | u8 customer_id_minor; | |
704 | u8 xtal_k; | |
705 | u8 chipset; /* 0x34 */ | |
706 | u8 res8[0x82]; | |
707 | u8 vid; /* 0xb7 */ | |
708 | u8 res9; | |
709 | u8 pid; /* 0xb9 */ | |
710 | u8 res10[0x0c]; | |
711 | u8 mac_addr[ETH_ALEN]; /* 0xc6 */ | |
712 | u8 res11[2]; | |
713 | u8 vendor_name[7]; | |
714 | u8 res12[2]; | |
715 | u8 device_name[0x29]; /* 0xd7 */ | |
716 | }; | |
717 | ||
718 | struct rtl8192cu_efuse { | |
719 | __le16 rtl_id; | |
720 | __le16 hpon; | |
721 | u8 res0[2]; | |
722 | __le16 clk; | |
723 | __le16 testr; | |
724 | __le16 vid; | |
725 | __le16 did; | |
726 | __le16 svid; | |
727 | __le16 smid; /* 0x10 */ | |
728 | u8 res1[4]; | |
729 | u8 mac_addr[ETH_ALEN]; /* 0x16 */ | |
730 | u8 res2[2]; | |
731 | u8 vendor_name[7]; | |
732 | u8 res3[3]; | |
733 | u8 device_name[0x14]; /* 0x28 */ | |
734 | u8 res4[0x1e]; /* 0x3c */ | |
735 | u8 cck_tx_power_index_A[3]; /* 0x5a */ | |
736 | u8 cck_tx_power_index_B[3]; | |
737 | u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */ | |
738 | u8 ht40_1s_tx_power_index_B[3]; | |
739 | /* | |
740 | * The following entries are half-bytes split as: | |
741 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed | |
742 | */ | |
743 | struct rtl8723au_idx ht40_2s_tx_power_index_diff[3]; | |
744 | struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */ | |
745 | struct rtl8723au_idx ofdm_tx_power_index_diff[3]; | |
746 | struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */ | |
747 | struct rtl8723au_idx ht20_max_power_offset[3]; | |
748 | u8 channel_plan; /* 0x75 */ | |
749 | u8 tssi_a; | |
750 | u8 tssi_b; | |
751 | u8 thermal_meter; /* xtal_k */ /* 0x78 */ | |
752 | u8 rf_regulatory; | |
753 | u8 rf_option_2; | |
754 | u8 rf_option_3; | |
755 | u8 rf_option_4; | |
756 | u8 res5[1]; /* 0x7d */ | |
757 | u8 version; | |
758 | u8 customer_id; | |
759 | }; | |
760 | ||
3be26999 JS |
761 | struct rtl8723bu_pwr_idx { |
762 | #ifdef __LITTLE_ENDIAN | |
763 | int ht20:4; | |
764 | int ht40:4; | |
765 | int ofdm:4; | |
766 | int cck:4; | |
767 | #else | |
768 | int cck:4; | |
769 | int ofdm:4; | |
770 | int ht40:4; | |
771 | int ht20:4; | |
772 | #endif | |
773 | } __attribute__((packed)); | |
774 | ||
4a0d7db5 JS |
775 | struct rtl8723bu_efuse_tx_power { |
776 | u8 cck_base[6]; | |
777 | u8 ht40_base[5]; | |
778 | struct rtl8723au_idx ht20_ofdm_1s_diff; | |
3be26999 | 779 | struct rtl8723bu_pwr_idx pwr_diff[3]; |
4a0d7db5 JS |
780 | u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ |
781 | }; | |
782 | ||
3c836d60 JS |
783 | struct rtl8723bu_efuse { |
784 | __le16 rtl_id; | |
785 | u8 res0[0x0e]; | |
4a0d7db5 JS |
786 | struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */ |
787 | struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */ | |
788 | struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */ | |
789 | struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */ | |
3c836d60 JS |
790 | u8 channel_plan; /* 0xb8 */ |
791 | u8 xtal_k; | |
792 | u8 thermal_meter; | |
793 | u8 iqk_lck; | |
794 | u8 pa_type; /* 0xbc */ | |
795 | u8 lna_type_2g; /* 0xbd */ | |
796 | u8 res2[3]; | |
797 | u8 rf_board_option; | |
798 | u8 rf_feature_option; | |
799 | u8 rf_bt_setting; | |
800 | u8 eeprom_version; | |
801 | u8 eeprom_customer_id; | |
802 | u8 res3[2]; | |
803 | u8 tx_pwr_calibrate_rate; | |
804 | u8 rf_antenna_option; /* 0xc9 */ | |
805 | u8 rfe_option; | |
806 | u8 res4[9]; | |
807 | u8 usb_optional_function; | |
808 | u8 res5[0x1e]; | |
809 | u8 res6[2]; | |
810 | u8 serial[0x0b]; /* 0xf5 */ | |
811 | u8 vid; /* 0x100 */ | |
812 | u8 res7; | |
813 | u8 pid; | |
814 | u8 res8[4]; | |
815 | u8 mac_addr[ETH_ALEN]; /* 0x107 */ | |
816 | u8 res9[2]; | |
817 | u8 vendor_name[0x07]; | |
818 | u8 res10[2]; | |
22a31d45 JS |
819 | u8 device_name[0x14]; |
820 | u8 res11[0xcf]; | |
821 | u8 package_type; /* 0x1fb */ | |
822 | u8 res12[0x4]; | |
3c836d60 JS |
823 | }; |
824 | ||
e6f9a9c3 JS |
825 | struct rtl8192eu_efuse_tx_power { |
826 | u8 cck_base[6]; | |
827 | u8 ht40_base[5]; | |
828 | struct rtl8723au_idx ht20_ofdm_1s_diff; | |
9e24772a JS |
829 | struct rtl8723bu_pwr_idx pwr_diff[3]; |
830 | u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */ | |
e6f9a9c3 JS |
831 | }; |
832 | ||
3307d840 JS |
833 | struct rtl8192eu_efuse { |
834 | __le16 rtl_id; | |
835 | u8 res0[0x0e]; | |
e6f9a9c3 | 836 | struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */ |
9e24772a JS |
837 | struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */ |
838 | u8 res2[0x54]; | |
3307d840 JS |
839 | u8 channel_plan; /* 0xb8 */ |
840 | u8 xtal_k; | |
841 | u8 thermal_meter; | |
842 | u8 iqk_lck; | |
843 | u8 pa_type; /* 0xbc */ | |
844 | u8 lna_type_2g; /* 0xbd */ | |
9e24772a | 845 | u8 res3[1]; |
3307d840 | 846 | u8 lna_type_5g; /* 0xbf */ |
9e24772a | 847 | u8 res4[1]; |
3307d840 JS |
848 | u8 rf_board_option; |
849 | u8 rf_feature_option; | |
850 | u8 rf_bt_setting; | |
851 | u8 eeprom_version; | |
852 | u8 eeprom_customer_id; | |
9e24772a | 853 | u8 res5[3]; |
3307d840 | 854 | u8 rf_antenna_option; /* 0xc9 */ |
9e24772a | 855 | u8 res6[6]; |
3307d840 | 856 | u8 vid; /* 0xd0 */ |
9e24772a | 857 | u8 res7[1]; |
3307d840 | 858 | u8 pid; /* 0xd2 */ |
9e24772a | 859 | u8 res8[1]; |
3307d840 | 860 | u8 usb_optional_function; |
9e24772a | 861 | u8 res9[2]; |
3307d840 | 862 | u8 mac_addr[ETH_ALEN]; /* 0xd7 */ |
9e24772a | 863 | u8 res10[2]; |
3307d840 | 864 | u8 vendor_name[7]; |
9e24772a | 865 | u8 res11[2]; |
3307d840 | 866 | u8 device_name[0x0b]; /* 0xe8 */ |
9e24772a | 867 | u8 res12[2]; |
3307d840 | 868 | u8 serial[0x0b]; /* 0xf5 */ |
9e24772a | 869 | u8 res13[0x30]; |
3307d840 | 870 | u8 unknown[0x0d]; /* 0x130 */ |
9e24772a | 871 | u8 res14[0xc3]; |
3307d840 JS |
872 | }; |
873 | ||
26f1fad2 JS |
874 | struct rtl8xxxu_reg8val { |
875 | u16 reg; | |
876 | u8 val; | |
877 | }; | |
878 | ||
879 | struct rtl8xxxu_reg32val { | |
880 | u16 reg; | |
881 | u32 val; | |
882 | }; | |
883 | ||
884 | struct rtl8xxxu_rfregval { | |
885 | u8 reg; | |
886 | u32 val; | |
887 | }; | |
888 | ||
889 | enum rtl8xxxu_rfpath { | |
890 | RF_A = 0, | |
891 | RF_B = 1, | |
892 | }; | |
893 | ||
894 | struct rtl8xxxu_rfregs { | |
895 | u16 hssiparm1; | |
896 | u16 hssiparm2; | |
897 | u16 lssiparm; | |
898 | u16 hspiread; | |
899 | u16 lssiread; | |
900 | u16 rf_sw_ctrl; | |
901 | }; | |
902 | ||
903 | #define H2C_MAX_MBOX 4 | |
904 | #define H2C_EXT BIT(7) | |
26f1fad2 JS |
905 | #define H2C_JOIN_BSS_DISCONNECT 0 |
906 | #define H2C_JOIN_BSS_CONNECT 1 | |
d940c247 JS |
907 | |
908 | /* | |
909 | * H2C (firmware) commands differ between the older generation chips | |
910 | * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, | |
911 | * 8192[de]u, 8192eu, and 8812. | |
912 | */ | |
913 | enum h2c_cmd_8723a { | |
914 | H2C_SET_POWER_MODE = 1, | |
915 | H2C_JOIN_BSS_REPORT = 2, | |
916 | H2C_SET_RSSI = 5, | |
917 | H2C_SET_RATE_MASK = (6 | H2C_EXT), | |
918 | }; | |
919 | ||
920 | enum h2c_cmd_8723b { | |
921 | /* | |
922 | * Common Class: 000 | |
923 | */ | |
924 | H2C_8723B_RSVD_PAGE = 0x00, | |
925 | H2C_8723B_MEDIA_STATUS_RPT = 0x01, | |
926 | H2C_8723B_SCAN_ENABLE = 0x02, | |
927 | H2C_8723B_KEEP_ALIVE = 0x03, | |
928 | H2C_8723B_DISCON_DECISION = 0x04, | |
929 | H2C_8723B_PSD_OFFLOAD = 0x05, | |
930 | H2C_8723B_AP_OFFLOAD = 0x08, | |
931 | H2C_8723B_BCN_RSVDPAGE = 0x09, | |
932 | H2C_8723B_PROBERSP_RSVDPAGE = 0x0A, | |
933 | H2C_8723B_FCS_RSVDPAGE = 0x10, | |
934 | H2C_8723B_FCS_INFO = 0x11, | |
935 | H2C_8723B_AP_WOW_GPIO_CTRL = 0x13, | |
936 | ||
937 | /* | |
938 | * PoweSave Class: 001 | |
939 | */ | |
940 | H2C_8723B_SET_PWR_MODE = 0x20, | |
941 | H2C_8723B_PS_TUNING_PARA = 0x21, | |
942 | H2C_8723B_PS_TUNING_PARA2 = 0x22, | |
943 | H2C_8723B_P2P_LPS_PARAM = 0x23, | |
944 | H2C_8723B_P2P_PS_OFFLOAD = 0x24, | |
945 | H2C_8723B_PS_SCAN_ENABLE = 0x25, | |
946 | H2C_8723B_SAP_PS_ = 0x26, | |
947 | H2C_8723B_INACTIVE_PS_ = 0x27, | |
948 | H2C_8723B_FWLPS_IN_IPS_ = 0x28, | |
949 | ||
950 | /* | |
951 | * Dynamic Mechanism Class: 010 | |
952 | */ | |
80b30b2a | 953 | H2C_8723B_MACID_CFG_RAID = 0x40, |
d940c247 JS |
954 | H2C_8723B_TXBF = 0x41, |
955 | H2C_8723B_RSSI_SETTING = 0x42, | |
956 | H2C_8723B_AP_REQ_TXRPT = 0x43, | |
957 | H2C_8723B_INIT_RATE_COLLECT = 0x44, | |
958 | ||
959 | /* | |
960 | * BT Class: 011 | |
961 | */ | |
962 | H2C_8723B_B_TYPE_TDMA = 0x60, | |
963 | H2C_8723B_BT_INFO = 0x61, | |
964 | H2C_8723B_FORCE_BT_TXPWR = 0x62, | |
965 | H2C_8723B_BT_IGNORE_WLANACT = 0x63, | |
966 | H2C_8723B_DAC_SWING_VALUE = 0x64, | |
967 | H2C_8723B_ANT_SEL_RSV = 0x65, | |
968 | H2C_8723B_WL_OPMODE = 0x66, | |
969 | H2C_8723B_BT_MP_OPER = 0x67, | |
970 | H2C_8723B_BT_CONTROL = 0x68, | |
971 | H2C_8723B_BT_WIFI_CTRL = 0x69, | |
f37e9228 JS |
972 | H2C_8723B_BT_FW_PATCH = 0x6a, |
973 | H2C_8723B_BT_WLAN_CALIBRATION = 0x6d, | |
974 | H2C_8723B_BT_GRANT = 0x6e, | |
d940c247 JS |
975 | |
976 | /* | |
977 | * WOWLAN Class: 100 | |
978 | */ | |
979 | H2C_8723B_WOWLAN = 0x80, | |
980 | H2C_8723B_REMOTE_WAKE_CTRL = 0x81, | |
981 | H2C_8723B_AOAC_GLOBAL_INFO = 0x82, | |
982 | H2C_8723B_AOAC_RSVD_PAGE = 0x83, | |
983 | H2C_8723B_AOAC_RSVD_PAGE2 = 0x84, | |
984 | H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85, | |
985 | H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86, | |
986 | H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87, | |
987 | ||
988 | H2C_8723B_RESET_TSF = 0xC0, | |
989 | }; | |
990 | ||
26f1fad2 JS |
991 | |
992 | struct h2c_cmd { | |
993 | union { | |
994 | struct { | |
995 | u8 cmd; | |
ed35d094 | 996 | u8 data[7]; |
26f1fad2 JS |
997 | } __packed cmd; |
998 | struct { | |
999 | __le32 data; | |
1000 | __le16 ext; | |
1001 | } __packed raw; | |
ed35d094 JS |
1002 | struct { |
1003 | __le32 data; | |
1004 | __le32 ext; | |
1005 | } __packed raw_wide; | |
26f1fad2 JS |
1006 | struct { |
1007 | u8 cmd; | |
1008 | u8 data; | |
26f1fad2 JS |
1009 | } __packed joinbss; |
1010 | struct { | |
1011 | u8 cmd; | |
1012 | __le16 mask_hi; | |
1013 | u8 arg; | |
1014 | __le16 mask_lo; | |
1015 | } __packed ramask; | |
7d794eaa JS |
1016 | struct { |
1017 | u8 cmd; | |
1018 | u8 parm; | |
1019 | u8 macid; | |
1020 | u8 macid_end; | |
1021 | } __packed media_status_rpt; | |
80b30b2a JS |
1022 | struct { |
1023 | u8 cmd; | |
f653e690 JS |
1024 | u8 macid; |
1025 | /* | |
1026 | * [0:4] - RAID | |
1027 | * [7] - SGI | |
1028 | */ | |
80b30b2a | 1029 | u8 data1; |
f653e690 JS |
1030 | /* |
1031 | * [0:1] - Bandwidth | |
1032 | * [3] - No Update | |
1033 | * [4:5] - VHT enable | |
1034 | * [6] - DISPT | |
1035 | * [7] - DISRA | |
1036 | */ | |
80b30b2a | 1037 | u8 data2; |
f653e690 | 1038 | u8 ramask0; |
80b30b2a JS |
1039 | u8 ramask1; |
1040 | u8 ramask2; | |
1041 | u8 ramask3; | |
80b30b2a | 1042 | } __packed b_macid_cfg; |
3ca7b32c JS |
1043 | struct { |
1044 | u8 cmd; | |
1045 | u8 data1; | |
1046 | u8 data2; | |
1047 | u8 data3; | |
1048 | u8 data4; | |
1049 | u8 data5; | |
1050 | } __packed b_type_dma; | |
6b9eae01 JS |
1051 | struct { |
1052 | u8 cmd; | |
1053 | u8 data; | |
1054 | } __packed bt_info; | |
394f1bd3 JS |
1055 | struct { |
1056 | u8 cmd; | |
1057 | u8 operreq; | |
1058 | u8 opcode; | |
1059 | u8 data; | |
1060 | u8 addr; | |
1061 | } __packed bt_mp_oper; | |
c7a5a190 JS |
1062 | struct { |
1063 | u8 cmd; | |
1064 | u8 data; | |
1065 | } __packed bt_wlan_calibration; | |
7297f49c JS |
1066 | struct { |
1067 | u8 cmd; | |
1068 | u8 data; | |
1069 | } __packed ignore_wlan; | |
f37e9228 JS |
1070 | struct { |
1071 | u8 cmd; | |
1072 | u8 ant_inverse; | |
1073 | u8 int_switch_type; | |
1074 | } __packed ant_sel_rsv; | |
1075 | struct { | |
1076 | u8 cmd; | |
1077 | u8 data; | |
1078 | } __packed bt_grant; | |
26f1fad2 JS |
1079 | }; |
1080 | }; | |
1081 | ||
b2b43b78 JS |
1082 | enum c2h_evt_8723b { |
1083 | C2H_8723B_DEBUG = 0, | |
1084 | C2H_8723B_TSF = 1, | |
1085 | C2H_8723B_AP_RPT_RSP = 2, | |
1086 | C2H_8723B_CCX_TX_RPT = 3, | |
1087 | C2H_8723B_BT_RSSI = 4, | |
1088 | C2H_8723B_BT_OP_MODE = 5, | |
1089 | C2H_8723B_EXT_RA_RPT = 6, | |
1090 | C2H_8723B_BT_INFO = 9, | |
394f1bd3 JS |
1091 | C2H_8723B_HW_INFO_EXCH = 0x0a, |
1092 | C2H_8723B_BT_MP_INFO = 0x0b, | |
55a18dd1 | 1093 | C2H_8723B_RA_REPORT = 0x0c, |
b2b43b78 JS |
1094 | C2H_8723B_FW_DEBUG = 0xff, |
1095 | }; | |
1096 | ||
1097 | enum bt_info_src_8723b { | |
1098 | BT_INFO_SRC_8723B_WIFI_FW = 0x0, | |
1099 | BT_INFO_SRC_8723B_BT_RSP = 0x1, | |
1100 | BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2, | |
1101 | }; | |
1102 | ||
394f1bd3 JS |
1103 | enum bt_mp_oper_opcode_8723b { |
1104 | BT_MP_OP_GET_BT_VERSION = 0x00, | |
1105 | BT_MP_OP_RESET = 0x01, | |
1106 | BT_MP_OP_TEST_CTRL = 0x02, | |
1107 | BT_MP_OP_SET_BT_MODE = 0x03, | |
1108 | BT_MP_OP_SET_CHNL_TX_GAIN = 0x04, | |
1109 | BT_MP_OP_SET_PKT_TYPE_LEN = 0x05, | |
1110 | BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, | |
1111 | BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, | |
1112 | BT_MP_OP_SET_PKT_HEADER = 0x08, | |
1113 | BT_MP_OP_SET_WHITENCOEFF = 0x09, | |
1114 | BT_MP_OP_SET_BD_ADDR_L = 0x0a, | |
1115 | BT_MP_OP_SET_BD_ADDR_H = 0x0b, | |
1116 | BT_MP_OP_WRITE_REG_ADDR = 0x0c, | |
1117 | BT_MP_OP_WRITE_REG_VALUE = 0x0d, | |
1118 | BT_MP_OP_GET_BT_STATUS = 0x0e, | |
1119 | BT_MP_OP_GET_BD_ADDR_L = 0x0f, | |
1120 | BT_MP_OP_GET_BD_ADDR_H = 0x10, | |
1121 | BT_MP_OP_READ_REG = 0x11, | |
1122 | BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12, | |
1123 | BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13, | |
1124 | BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14, | |
1125 | BT_MP_OP_GET_RX_PKT_CNT_L = 0x15, | |
1126 | BT_MP_OP_GET_RX_PKT_CNT_H = 0x16, | |
1127 | BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17, | |
1128 | BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18, | |
1129 | BT_MP_OP_GET_RSSI = 0x19, | |
1130 | BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a, | |
1131 | BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b, | |
1132 | BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c, | |
1133 | BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d, | |
1134 | BT_MP_OP_GET_AFH_MAP_L = 0x1e, | |
1135 | BT_MP_OP_GET_AFH_MAP_M = 0x1f, | |
1136 | BT_MP_OP_GET_AFH_MAP_H = 0x20, | |
1137 | BT_MP_OP_GET_AFH_STATUS = 0x21, | |
1138 | BT_MP_OP_SET_TRACKING_INTERVAL = 0x22, | |
1139 | BT_MP_OP_SET_THERMAL_METER = 0x23, | |
1140 | BT_MP_OP_ENABLE_CFO_TRACKING = 0x24, | |
1141 | }; | |
1142 | ||
b2b43b78 JS |
1143 | struct rtl8723bu_c2h { |
1144 | u8 id; | |
1145 | u8 seq; | |
1146 | union { | |
1147 | struct { | |
1148 | u8 payload[0]; | |
1149 | } __packed raw; | |
394f1bd3 JS |
1150 | struct { |
1151 | u8 ext_id; | |
1152 | u8 status:4; | |
1153 | u8 retlen:4; | |
1154 | u8 opcode_ver:4; | |
1155 | u8 req_num:4; | |
1156 | u8 payload[2]; | |
1157 | } __packed bt_mp_info; | |
b2b43b78 JS |
1158 | struct { |
1159 | u8 response_source:4; | |
1160 | u8 dummy0_0:4; | |
1161 | ||
1162 | u8 bt_info; | |
1163 | ||
1164 | u8 retry_count:4; | |
1165 | u8 dummy2_0:1; | |
1166 | u8 bt_page:1; | |
1167 | u8 tx_rx_mask:1; | |
1168 | u8 dummy2_2:1; | |
1169 | ||
1170 | u8 rssi; | |
1171 | ||
1172 | u8 basic_rate:1; | |
1173 | u8 bt_has_reset:1; | |
1174 | u8 dummy4_1:1;; | |
1175 | u8 ignore_wlan:1; | |
1176 | u8 auto_report:1; | |
1177 | u8 dummy4_2:3; | |
1178 | ||
1179 | u8 a4; | |
1180 | u8 a5; | |
1181 | } __packed bt_info; | |
55a18dd1 JS |
1182 | struct { |
1183 | u8 rate:7; | |
1184 | u8 dummy0_0:1; | |
1185 | u8 macid; | |
1186 | u8 ldpc:1; | |
1187 | u8 txbf:1; | |
1188 | u8 noisy_state:1; | |
1189 | u8 dummy2_0:5; | |
1190 | u8 dummy3_0; | |
1191 | } __packed ra_report; | |
b2b43b78 JS |
1192 | }; |
1193 | }; | |
1194 | ||
26f1fad2 JS |
1195 | struct rtl8xxxu_fileops; |
1196 | ||
1197 | struct rtl8xxxu_priv { | |
1198 | struct ieee80211_hw *hw; | |
1199 | struct usb_device *udev; | |
1200 | struct rtl8xxxu_fileops *fops; | |
1201 | ||
1202 | spinlock_t tx_urb_lock; | |
1203 | struct list_head tx_urb_free_list; | |
1204 | int tx_urb_free_count; | |
1205 | bool tx_stopped; | |
1206 | ||
1207 | spinlock_t rx_urb_lock; | |
1208 | struct list_head rx_urb_pending_list; | |
1209 | int rx_urb_pending_count; | |
1210 | bool shutdown; | |
1211 | struct work_struct rx_urb_wq; | |
1212 | ||
1213 | u8 mac_addr[ETH_ALEN]; | |
1214 | char chip_name[8]; | |
0e5d435a | 1215 | char chip_vendor[8]; |
21db9973 JS |
1216 | u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; |
1217 | u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; | |
1218 | u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS]; | |
1219 | u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS]; | |
26f1fad2 JS |
1220 | /* |
1221 | * The following entries are half-bytes split as: | |
1222 | * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed | |
1223 | */ | |
21db9973 | 1224 | struct rtl8723au_idx ht40_2s_tx_power_index_diff[ |
3be26999 JS |
1225 | RTL8723A_CHANNEL_GROUPS]; |
1226 | struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; | |
1227 | struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS]; | |
1228 | struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS]; | |
1229 | struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS]; | |
1230 | /* | |
1231 | * Newer generation chips only keep power diffs per TX count, | |
1232 | * not per channel group. | |
1233 | */ | |
1234 | struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT]; | |
1235 | struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT]; | |
1236 | struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT]; | |
2fc0b8e5 | 1237 | struct rtl8xxxu_power_base *power_base; |
26f1fad2 JS |
1238 | u32 chip_cut:4; |
1239 | u32 rom_rev:4; | |
38451998 | 1240 | u32 is_multi_func:1; |
26f1fad2 JS |
1241 | u32 has_wifi:1; |
1242 | u32 has_bluetooth:1; | |
1243 | u32 enable_bluetooth:1; | |
1244 | u32 has_gps:1; | |
1245 | u32 hi_pa:1; | |
1246 | u32 vendor_umc:1; | |
0e5d435a | 1247 | u32 vendor_smic:1; |
26f1fad2 JS |
1248 | u32 has_polarity_ctrl:1; |
1249 | u32 has_eeprom:1; | |
1250 | u32 boot_eeprom:1; | |
0e28b975 | 1251 | u32 usb_interrupts:1; |
26f1fad2 JS |
1252 | u32 ep_tx_high_queue:1; |
1253 | u32 ep_tx_normal_queue:1; | |
1254 | u32 ep_tx_low_queue:1; | |
4ef22eb9 | 1255 | u32 has_xtalk:1; |
04319ae2 | 1256 | u32 rx_buf_aggregation:1; |
4ef22eb9 | 1257 | u8 xtalk; |
26f1fad2 JS |
1258 | unsigned int pipe_interrupt; |
1259 | unsigned int pipe_in; | |
1260 | unsigned int pipe_out[TXDESC_QUEUE_MAX]; | |
1261 | u8 out_ep[RTL8XXXU_OUT_ENDPOINTS]; | |
26f1fad2 JS |
1262 | u8 ep_tx_count; |
1263 | u8 rf_paths; | |
1264 | u8 rx_paths; | |
1265 | u8 tx_paths; | |
26f1fad2 JS |
1266 | u32 rege94; |
1267 | u32 rege9c; | |
1268 | u32 regeb4; | |
1269 | u32 regebc; | |
1270 | int next_mbox; | |
1271 | int nr_out_eps; | |
1272 | ||
1273 | struct mutex h2c_mutex; | |
1274 | ||
1275 | struct usb_anchor rx_anchor; | |
1276 | struct usb_anchor tx_anchor; | |
1277 | struct usb_anchor int_anchor; | |
1278 | struct rtl8xxxu_firmware_header *fw_data; | |
1279 | size_t fw_size; | |
1280 | struct mutex usb_buf_mutex; | |
1281 | union { | |
1282 | __le32 val32; | |
1283 | __le16 val16; | |
1284 | u8 val8; | |
1285 | } usb_buf; | |
1286 | union { | |
3307d840 | 1287 | u8 raw[EFUSE_MAP_LEN]; |
26f1fad2 | 1288 | struct rtl8723au_efuse efuse8723; |
3c836d60 | 1289 | struct rtl8723bu_efuse efuse8723bu; |
26f1fad2 | 1290 | struct rtl8192cu_efuse efuse8192; |
3307d840 | 1291 | struct rtl8192eu_efuse efuse8192eu; |
26f1fad2 JS |
1292 | } efuse_wifi; |
1293 | u32 adda_backup[RTL8XXXU_ADDA_REGS]; | |
1294 | u32 mac_backup[RTL8XXXU_MAC_REGS]; | |
1295 | u32 bb_backup[RTL8XXXU_BB_REGS]; | |
1296 | u32 bb_recovery_backup[RTL8XXXU_BB_REGS]; | |
ba17d824 | 1297 | enum rtl8xxxu_rtl_chip rtl_chip; |
26f1fad2 | 1298 | u8 pi_enabled:1; |
cabb550e | 1299 | u8 no_pape:1; |
26f1fad2 JS |
1300 | u8 int_buf[USB_INTR_CONTENT_LENGTH]; |
1301 | }; | |
1302 | ||
1303 | struct rtl8xxxu_rx_urb { | |
1304 | struct urb urb; | |
1305 | struct ieee80211_hw *hw; | |
1306 | struct list_head list; | |
1307 | }; | |
1308 | ||
1309 | struct rtl8xxxu_tx_urb { | |
1310 | struct urb urb; | |
1311 | struct ieee80211_hw *hw; | |
1312 | struct list_head list; | |
1313 | }; | |
1314 | ||
1315 | struct rtl8xxxu_fileops { | |
1316 | int (*parse_efuse) (struct rtl8xxxu_priv *priv); | |
1317 | int (*load_firmware) (struct rtl8xxxu_priv *priv); | |
1318 | int (*power_on) (struct rtl8xxxu_priv *priv); | |
fe37d5f6 | 1319 | void (*power_off) (struct rtl8xxxu_priv *priv); |
7d4ccb8b | 1320 | void (*reset_8051) (struct rtl8xxxu_priv *priv); |
74b99bed | 1321 | int (*llt_init) (struct rtl8xxxu_priv *priv, u8 last_tx_page); |
cb877250 | 1322 | void (*init_phy_bb) (struct rtl8xxxu_priv *priv); |
4062b8ff | 1323 | int (*init_phy_rf) (struct rtl8xxxu_priv *priv); |
f0d9f5e9 | 1324 | void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv); |
e1547c53 | 1325 | void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv); |
c3f9506f | 1326 | void (*config_channel) (struct ieee80211_hw *hw); |
2db125d4 | 1327 | int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb); |
3e88ca44 | 1328 | void (*init_aggregation) (struct rtl8xxxu_priv *priv); |
9c79bf95 | 1329 | void (*init_statistics) (struct rtl8xxxu_priv *priv); |
db08de94 | 1330 | void (*enable_rf) (struct rtl8xxxu_priv *priv); |
fc89a41f | 1331 | void (*disable_rf) (struct rtl8xxxu_priv *priv); |
747bf237 | 1332 | void (*usb_quirks) (struct rtl8xxxu_priv *priv); |
e796dab4 JS |
1333 | void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel, |
1334 | bool ht40); | |
f653e690 JS |
1335 | void (*update_rate_mask) (struct rtl8xxxu_priv *priv, |
1336 | u32 ramask, int sgi); | |
7d794eaa JS |
1337 | void (*report_connect) (struct rtl8xxxu_priv *priv, |
1338 | u8 macid, bool connect); | |
b59415c2 JS |
1339 | void (*fill_txdesc) (struct ieee80211_hdr *hdr, |
1340 | struct rtl8xxxu_txdesc32 *tx_desc, u32 rate, | |
1341 | u16 rate_flag, bool sgi, bool short_preamble, | |
1342 | bool ampdu_enable); | |
26f1fad2 | 1343 | int writeN_block_size; |
04319ae2 | 1344 | int rx_agg_buf_size; |
179e1742 | 1345 | char tx_desc_size; |
a49c7ce1 | 1346 | char rx_desc_size; |
ee675cc3 JS |
1347 | u8 has_s0s1:1; |
1348 | u8 has_tx_report:1; | |
eed145ab | 1349 | u8 gen2_thermal_meter:1; |
8634af5e JS |
1350 | u32 adda_1t_init; |
1351 | u32 adda_1t_path_on; | |
1352 | u32 adda_2t_path_on_a; | |
1353 | u32 adda_2t_path_on_b; | |
24e8e7ec | 1354 | u16 trxff_boundary; |
9b323ee9 JS |
1355 | u8 pbp_rx; |
1356 | u8 pbp_tx; | |
c606e662 | 1357 | struct rtl8xxxu_reg8val *mactable; |
89c2a097 JS |
1358 | u8 total_page_num; |
1359 | u8 page_num_hi; | |
1360 | u8 page_num_lo; | |
1361 | u8 page_num_norm; | |
26f1fad2 | 1362 | }; |
599119f6 JS |
1363 | |
1364 | extern int rtl8xxxu_debug; | |
1365 | ||
20e3b2e9 | 1366 | extern struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[]; |
599119f6 JS |
1367 | extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; |
1368 | u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); | |
1369 | u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); | |
1370 | u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); | |
1371 | int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); | |
1372 | int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); | |
1373 | int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); | |
1374 | u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, | |
1375 | enum rtl8xxxu_rfpath path, u8 reg); | |
1376 | int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, | |
1377 | enum rtl8xxxu_rfpath path, u8 reg, u32 data); | |
1378 | void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, | |
1379 | u32 *backup, int count); | |
1380 | void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, | |
1381 | u32 *backup, int count); | |
1382 | void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, | |
1383 | const u32 *reg, u32 *backup); | |
1384 | void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, | |
1385 | const u32 *reg, u32 *backup); | |
1386 | void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, | |
1387 | bool path_a_on); | |
1388 | void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, | |
1389 | const u32 *regs, u32 *backup); | |
1390 | void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, | |
1391 | int result[][8], int candidate, bool tx_only); | |
1392 | void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, | |
1393 | int result[][8], int candidate, bool tx_only); | |
1394 | int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, | |
1395 | struct rtl8xxxu_rfregval *table, | |
1396 | enum rtl8xxxu_rfpath path); | |
1397 | int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, | |
1398 | struct rtl8xxxu_reg32val *array); | |
1399 | int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name); | |
6c46ca3b | 1400 | void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); |
599119f6 JS |
1401 | void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); |
1402 | void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); | |
1403 | int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page); | |
27c7e89e | 1404 | void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); |
6c46ca3b | 1405 | int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); |
9c0343d4 JS |
1406 | int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, |
1407 | struct h2c_cmd *h2c, int len); | |
6c46ca3b | 1408 | int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); |
993dd9b4 | 1409 | void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); |
20e3b2e9 JS |
1410 | int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page); |
1411 | void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); | |
1412 | void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); | |
1413 | void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, | |
1414 | int channel, bool ht40); | |
1415 | void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); | |
599119f6 | 1416 | void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); |
20e3b2e9 | 1417 | void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); |
599119f6 | 1418 | void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); |
20e3b2e9 JS |
1419 | void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, |
1420 | u32 ramask, int sgi); | |
599119f6 JS |
1421 | void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, |
1422 | u32 ramask, int sgi); | |
20e3b2e9 JS |
1423 | void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, |
1424 | u8 macid, bool connect); | |
599119f6 JS |
1425 | void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, |
1426 | u8 macid, bool connect); | |
91dcbb71 | 1427 | void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); |
20e3b2e9 JS |
1428 | void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); |
1429 | void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); | |
599119f6 | 1430 | void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); |
2db125d4 JS |
1431 | int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); |
1432 | int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); | |
599119f6 JS |
1433 | int rtl8xxxu_gen2_channel_to_group(int channel); |
1434 | bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, | |
1435 | int result[][8], int c1, int c2); | |
b59415c2 JS |
1436 | void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hdr *hdr, |
1437 | struct rtl8xxxu_txdesc32 *tx_desc, u32 rate, | |
1438 | u16 rate_flag, bool sgi, bool short_preamble, | |
1439 | bool ampdu_enable); | |
1440 | void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hdr *hdr, | |
1441 | struct rtl8xxxu_txdesc32 *tx_desc32, u32 rate, | |
1442 | u16 rate_flag, bool sgi, bool short_preamble, | |
1443 | bool ampdu_enable); | |
599119f6 | 1444 | |
181725dd | 1445 | extern struct rtl8xxxu_fileops rtl8192cu_fops; |
599119f6 | 1446 | extern struct rtl8xxxu_fileops rtl8192eu_fops; |
20e3b2e9 | 1447 | extern struct rtl8xxxu_fileops rtl8723au_fops; |
6c46ca3b | 1448 | extern struct rtl8xxxu_fileops rtl8723bu_fops; |