Commit | Line | Data |
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0c817338 LF |
1 | /****************************************************************************** |
2 | * | |
a8d76066 | 3 | * Copyright(c) 2009-2012 Realtek Corporation. |
0c817338 LF |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program; if not, write to the Free Software Foundation, Inc., | |
16 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA | |
17 | * | |
18 | * The full GNU General Public License is included in this distribution in the | |
19 | * file called LICENSE. | |
20 | * | |
21 | * Contact Information: | |
22 | * wlanfae <wlanfae@realtek.com> | |
23 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
24 | * Hsinchu 300, Taiwan. | |
25 | * | |
26 | * Larry Finger <Larry.Finger@lwfinger.net> | |
27 | * | |
28 | *****************************************************************************/ | |
29 | ||
0c817338 | 30 | #include "wifi.h" |
d273bb20 | 31 | #include "core.h" |
0c817338 LF |
32 | #include "pci.h" |
33 | #include "base.h" | |
34 | #include "ps.h" | |
c7cfe38e | 35 | #include "efuse.h" |
38506ece | 36 | #include <linux/interrupt.h> |
d273bb20 | 37 | #include <linux/export.h> |
f11bbfd8 | 38 | #include <linux/kmemleak.h> |
6f334c2b LF |
39 | #include <linux/module.h> |
40 | ||
41 | MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>"); | |
42 | MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>"); | |
43 | MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>"); | |
44 | MODULE_LICENSE("GPL"); | |
45 | MODULE_DESCRIPTION("PCI basic driver for rtlwifi"); | |
0c817338 LF |
46 | |
47 | static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { | |
38506ece LF |
48 | INTEL_VENDOR_ID, |
49 | ATI_VENDOR_ID, | |
50 | AMD_VENDOR_ID, | |
51 | SIS_VENDOR_ID | |
0c817338 LF |
52 | }; |
53 | ||
c7cfe38e C |
54 | static const u8 ac_to_hwq[] = { |
55 | VO_QUEUE, | |
56 | VI_QUEUE, | |
57 | BE_QUEUE, | |
58 | BK_QUEUE | |
59 | }; | |
60 | ||
d3bb1429 | 61 | static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, |
c7cfe38e C |
62 | struct sk_buff *skb) |
63 | { | |
64 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
d3bb1429 | 65 | __le16 fc = rtl_get_fc(skb); |
c7cfe38e C |
66 | u8 queue_index = skb_get_queue_mapping(skb); |
67 | ||
68 | if (unlikely(ieee80211_is_beacon(fc))) | |
69 | return BEACON_QUEUE; | |
26634c4b | 70 | if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) |
c7cfe38e C |
71 | return MGNT_QUEUE; |
72 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) | |
73 | if (ieee80211_is_nullfunc(fc)) | |
74 | return HIGH_QUEUE; | |
75 | ||
76 | return ac_to_hwq[queue_index]; | |
77 | } | |
78 | ||
0c817338 LF |
79 | /* Update PCI dependent default settings*/ |
80 | static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw) | |
81 | { | |
82 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
83 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
84 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
85 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
86 | u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; | |
c7cfe38e | 87 | u8 init_aspm; |
0c817338 LF |
88 | |
89 | ppsc->reg_rfps_level = 0; | |
3db1cd5c | 90 | ppsc->support_aspm = false; |
0c817338 LF |
91 | |
92 | /*Update PCI ASPM setting */ | |
93 | ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; | |
94 | switch (rtlpci->const_pci_aspm) { | |
95 | case 0: | |
96 | /*No ASPM */ | |
97 | break; | |
98 | ||
99 | case 1: | |
100 | /*ASPM dynamically enabled/disable. */ | |
101 | ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; | |
102 | break; | |
103 | ||
104 | case 2: | |
105 | /*ASPM with Clock Req dynamically enabled/disable. */ | |
106 | ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | | |
107 | RT_RF_OFF_LEVL_CLK_REQ); | |
108 | break; | |
109 | ||
110 | case 3: | |
111 | /* | |
112 | * Always enable ASPM and Clock Req | |
113 | * from initialization to halt. | |
114 | * */ | |
115 | ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); | |
116 | ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | | |
117 | RT_RF_OFF_LEVL_CLK_REQ); | |
118 | break; | |
119 | ||
120 | case 4: | |
121 | /* | |
122 | * Always enable ASPM without Clock Req | |
123 | * from initialization to halt. | |
124 | * */ | |
125 | ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | | |
126 | RT_RF_OFF_LEVL_CLK_REQ); | |
127 | ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; | |
128 | break; | |
129 | } | |
130 | ||
131 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; | |
132 | ||
133 | /*Update Radio OFF setting */ | |
134 | switch (rtlpci->const_hwsw_rfoff_d3) { | |
135 | case 1: | |
136 | if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) | |
137 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; | |
138 | break; | |
139 | ||
140 | case 2: | |
141 | if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) | |
142 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; | |
143 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; | |
144 | break; | |
145 | ||
146 | case 3: | |
147 | ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; | |
148 | break; | |
149 | } | |
150 | ||
151 | /*Set HW definition to determine if it supports ASPM. */ | |
152 | switch (rtlpci->const_support_pciaspm) { | |
c7cfe38e C |
153 | case 0:{ |
154 | /*Not support ASPM. */ | |
155 | bool support_aspm = false; | |
156 | ppsc->support_aspm = support_aspm; | |
157 | break; | |
158 | } | |
159 | case 1:{ | |
160 | /*Support ASPM. */ | |
161 | bool support_aspm = true; | |
162 | bool support_backdoor = true; | |
163 | ppsc->support_aspm = support_aspm; | |
164 | ||
165 | /*if (priv->oem_id == RT_CID_TOSHIBA && | |
166 | !priv->ndis_adapter.amd_l1_patch) | |
167 | support_backdoor = false; */ | |
168 | ||
169 | ppsc->support_backdoor = support_backdoor; | |
170 | ||
171 | break; | |
172 | } | |
0c817338 LF |
173 | case 2: |
174 | /*ASPM value set by chipset. */ | |
c7cfe38e C |
175 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { |
176 | bool support_aspm = true; | |
177 | ppsc->support_aspm = support_aspm; | |
178 | } | |
0c817338 LF |
179 | break; |
180 | default: | |
181 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 182 | "switch case not processed\n"); |
0c817338 LF |
183 | break; |
184 | } | |
c7cfe38e C |
185 | |
186 | /* toshiba aspm issue, toshiba will set aspm selfly | |
187 | * so we should not set aspm in driver */ | |
188 | pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm); | |
189 | if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE && | |
190 | init_aspm == 0x43) | |
191 | ppsc->support_aspm = false; | |
192 | } | |
193 | ||
0c817338 LF |
194 | static bool _rtl_pci_platform_switch_device_pci_aspm( |
195 | struct ieee80211_hw *hw, | |
196 | u8 value) | |
197 | { | |
198 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
c7cfe38e C |
199 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
200 | ||
201 | if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE) | |
202 | value |= 0x40; | |
0c817338 | 203 | |
0c817338 LF |
204 | pci_write_config_byte(rtlpci->pdev, 0x80, value); |
205 | ||
32473284 | 206 | return false; |
0c817338 LF |
207 | } |
208 | ||
209 | /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/ | |
1d73c51a | 210 | static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value) |
0c817338 LF |
211 | { |
212 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
c7cfe38e | 213 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
0c817338 | 214 | |
0c817338 | 215 | pci_write_config_byte(rtlpci->pdev, 0x81, value); |
0c817338 | 216 | |
c7cfe38e C |
217 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) |
218 | udelay(100); | |
0c817338 LF |
219 | } |
220 | ||
221 | /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ | |
222 | static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) | |
223 | { | |
224 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
225 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
226 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
227 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
228 | u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; | |
0c817338 LF |
229 | u8 num4bytes = pcipriv->ndis_adapter.num4bytes; |
230 | /*Retrieve original configuration settings. */ | |
231 | u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg; | |
232 | u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter. | |
233 | pcibridge_linkctrlreg; | |
234 | u16 aspmlevel = 0; | |
32473284 | 235 | u8 tmp_u1b = 0; |
0c817338 | 236 | |
c7cfe38e C |
237 | if (!ppsc->support_aspm) |
238 | return; | |
239 | ||
0c817338 LF |
240 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { |
241 | RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, | |
f30d7507 | 242 | "PCI(Bridge) UNKNOWN\n"); |
0c817338 LF |
243 | |
244 | return; | |
245 | } | |
246 | ||
247 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { | |
248 | RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); | |
249 | _rtl_pci_switch_clk_req(hw, 0x0); | |
250 | } | |
251 | ||
32473284 LF |
252 | /*for promising device will in L0 state after an I/O. */ |
253 | pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b); | |
0c817338 LF |
254 | |
255 | /*Set corresponding value. */ | |
256 | aspmlevel |= BIT(0) | BIT(1); | |
257 | linkctrl_reg &= ~aspmlevel; | |
258 | pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); | |
259 | ||
260 | _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg); | |
261 | udelay(50); | |
262 | ||
263 | /*4 Disable Pci Bridge ASPM */ | |
886e14b6 LF |
264 | pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), |
265 | pcibridge_linkctrlreg); | |
0c817338 LF |
266 | |
267 | udelay(50); | |
0c817338 LF |
268 | } |
269 | ||
270 | /* | |
271 | *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for | |
272 | *power saving We should follow the sequence to enable | |
273 | *RTL8192SE first then enable Pci Bridge ASPM | |
274 | *or the system will show bluescreen. | |
275 | */ | |
276 | static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) | |
277 | { | |
278 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
279 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
280 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
281 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
0c817338 | 282 | u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; |
0c817338 LF |
283 | u8 num4bytes = pcipriv->ndis_adapter.num4bytes; |
284 | u16 aspmlevel; | |
285 | u8 u_pcibridge_aspmsetting; | |
286 | u8 u_device_aspmsetting; | |
287 | ||
c7cfe38e C |
288 | if (!ppsc->support_aspm) |
289 | return; | |
290 | ||
0c817338 LF |
291 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { |
292 | RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, | |
f30d7507 | 293 | "PCI(Bridge) UNKNOWN\n"); |
0c817338 LF |
294 | return; |
295 | } | |
296 | ||
297 | /*4 Enable Pci Bridge ASPM */ | |
0c817338 LF |
298 | |
299 | u_pcibridge_aspmsetting = | |
300 | pcipriv->ndis_adapter.pcibridge_linkctrlreg | | |
301 | rtlpci->const_hostpci_aspm_setting; | |
302 | ||
303 | if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) | |
304 | u_pcibridge_aspmsetting &= ~BIT(0); | |
305 | ||
886e14b6 LF |
306 | pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), |
307 | u_pcibridge_aspmsetting); | |
0c817338 LF |
308 | |
309 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
26634c4b | 310 | "PlatformEnableASPM(): Write reg[%x] = %x\n", |
f30d7507 JP |
311 | (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), |
312 | u_pcibridge_aspmsetting); | |
0c817338 LF |
313 | |
314 | udelay(50); | |
315 | ||
316 | /*Get ASPM level (with/without Clock Req) */ | |
317 | aspmlevel = rtlpci->const_devicepci_aspm_setting; | |
318 | u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg; | |
319 | ||
320 | /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/ | |
321 | /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */ | |
322 | ||
323 | u_device_aspmsetting |= aspmlevel; | |
324 | ||
325 | _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting); | |
326 | ||
327 | if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { | |
328 | _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level & | |
329 | RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); | |
330 | RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ); | |
331 | } | |
c7cfe38e | 332 | udelay(100); |
0c817338 LF |
333 | } |
334 | ||
335 | static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw) | |
336 | { | |
886e14b6 | 337 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
0c817338 LF |
338 | |
339 | bool status = false; | |
340 | u8 offset_e0; | |
341 | unsigned offset_e4; | |
342 | ||
886e14b6 | 343 | pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0); |
0c817338 | 344 | |
886e14b6 | 345 | pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0); |
0c817338 LF |
346 | |
347 | if (offset_e0 == 0xA0) { | |
886e14b6 | 348 | pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4); |
0c817338 LF |
349 | if (offset_e4 & BIT(23)) |
350 | status = true; | |
351 | } | |
352 | ||
353 | return status; | |
354 | } | |
355 | ||
26634c4b LF |
356 | static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, |
357 | struct rtl_priv **buddy_priv) | |
358 | { | |
359 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
360 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
361 | bool find_buddy_priv = false; | |
37c52934 | 362 | struct rtl_priv *tpriv; |
26634c4b LF |
363 | struct rtl_pci_priv *tpcipriv = NULL; |
364 | ||
365 | if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) { | |
366 | list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, | |
367 | list) { | |
37c52934 LF |
368 | tpcipriv = (struct rtl_pci_priv *)tpriv->priv; |
369 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
370 | "pcipriv->ndis_adapter.funcnumber %x\n", | |
371 | pcipriv->ndis_adapter.funcnumber); | |
372 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
373 | "tpcipriv->ndis_adapter.funcnumber %x\n", | |
374 | tpcipriv->ndis_adapter.funcnumber); | |
375 | ||
376 | if ((pcipriv->ndis_adapter.busnumber == | |
377 | tpcipriv->ndis_adapter.busnumber) && | |
378 | (pcipriv->ndis_adapter.devnumber == | |
379 | tpcipriv->ndis_adapter.devnumber) && | |
380 | (pcipriv->ndis_adapter.funcnumber != | |
381 | tpcipriv->ndis_adapter.funcnumber)) { | |
382 | find_buddy_priv = true; | |
383 | break; | |
26634c4b LF |
384 | } |
385 | } | |
386 | } | |
387 | ||
388 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
389 | "find_buddy_priv %d\n", find_buddy_priv); | |
390 | ||
391 | if (find_buddy_priv) | |
392 | *buddy_priv = tpriv; | |
393 | ||
394 | return find_buddy_priv; | |
395 | } | |
396 | ||
d3bb1429 | 397 | static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw) |
0c817338 LF |
398 | { |
399 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
886e14b6 | 400 | struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); |
0c817338 | 401 | u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset; |
0c817338 | 402 | u8 linkctrl_reg; |
c7cfe38e | 403 | u8 num4bbytes; |
0c817338 | 404 | |
c7cfe38e | 405 | num4bbytes = (capabilityoffset + 0x10) / 4; |
0c817338 LF |
406 | |
407 | /*Read Link Control Register */ | |
886e14b6 | 408 | pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg); |
0c817338 LF |
409 | |
410 | pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg; | |
411 | } | |
412 | ||
413 | static void rtl_pci_parse_configuration(struct pci_dev *pdev, | |
414 | struct ieee80211_hw *hw) | |
415 | { | |
416 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
417 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
418 | ||
419 | u8 tmp; | |
332badc3 | 420 | u16 linkctrl_reg; |
0c817338 LF |
421 | |
422 | /*Link Control Register */ | |
332badc3 JL |
423 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); |
424 | pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; | |
0c817338 | 425 | |
f30d7507 JP |
426 | RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", |
427 | pcipriv->ndis_adapter.linkctrl_reg); | |
0c817338 LF |
428 | |
429 | pci_read_config_byte(pdev, 0x98, &tmp); | |
430 | tmp |= BIT(4); | |
431 | pci_write_config_byte(pdev, 0x98, tmp); | |
432 | ||
433 | tmp = 0x17; | |
434 | pci_write_config_byte(pdev, 0x70f, tmp); | |
435 | } | |
436 | ||
c7cfe38e | 437 | static void rtl_pci_init_aspm(struct ieee80211_hw *hw) |
0c817338 LF |
438 | { |
439 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
440 | ||
441 | _rtl_pci_update_default_setting(hw); | |
442 | ||
443 | if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { | |
444 | /*Always enable ASPM & Clock Req. */ | |
445 | rtl_pci_enable_aspm(hw); | |
446 | RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM); | |
447 | } | |
448 | ||
449 | } | |
450 | ||
0c817338 LF |
451 | static void _rtl_pci_io_handler_init(struct device *dev, |
452 | struct ieee80211_hw *hw) | |
453 | { | |
454 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
455 | ||
456 | rtlpriv->io.dev = dev; | |
457 | ||
458 | rtlpriv->io.write8_async = pci_write8_async; | |
459 | rtlpriv->io.write16_async = pci_write16_async; | |
460 | rtlpriv->io.write32_async = pci_write32_async; | |
461 | ||
462 | rtlpriv->io.read8_sync = pci_read8_sync; | |
463 | rtlpriv->io.read16_sync = pci_read16_sync; | |
464 | rtlpriv->io.read32_sync = pci_read32_sync; | |
465 | ||
466 | } | |
467 | ||
c7cfe38e C |
468 | static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw, |
469 | struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid) | |
470 | { | |
471 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
472 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
26634c4b | 473 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
c7cfe38e | 474 | struct sk_buff *next_skb; |
26634c4b | 475 | u8 additionlen = FCS_LEN; |
c7cfe38e C |
476 | |
477 | /* here open is 4, wep/tkip is 8, aes is 12*/ | |
478 | if (info->control.hw_key) | |
479 | additionlen += info->control.hw_key->icv_len; | |
480 | ||
481 | /* The most skb num is 6 */ | |
482 | tcb_desc->empkt_num = 0; | |
483 | spin_lock_bh(&rtlpriv->locks.waitq_lock); | |
484 | skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) { | |
485 | struct ieee80211_tx_info *next_info; | |
486 | ||
487 | next_info = IEEE80211_SKB_CB(next_skb); | |
488 | if (next_info->flags & IEEE80211_TX_CTL_AMPDU) { | |
489 | tcb_desc->empkt_len[tcb_desc->empkt_num] = | |
490 | next_skb->len + additionlen; | |
491 | tcb_desc->empkt_num++; | |
492 | } else { | |
493 | break; | |
494 | } | |
495 | ||
496 | if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid], | |
497 | next_skb)) | |
498 | break; | |
499 | ||
26634c4b | 500 | if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num) |
c7cfe38e C |
501 | break; |
502 | } | |
503 | spin_unlock_bh(&rtlpriv->locks.waitq_lock); | |
504 | ||
505 | return true; | |
506 | } | |
507 | ||
508 | /* just for early mode now */ | |
509 | static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw) | |
510 | { | |
511 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
512 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
513 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
514 | struct sk_buff *skb = NULL; | |
515 | struct ieee80211_tx_info *info = NULL; | |
26634c4b | 516 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
fb914ebf | 517 | int tid; |
c7cfe38e C |
518 | |
519 | if (!rtlpriv->rtlhal.earlymode_enable) | |
520 | return; | |
521 | ||
26634c4b LF |
522 | if (rtlpriv->dm.supp_phymode_switch && |
523 | (rtlpriv->easy_concurrent_ctl.switch_in_process || | |
524 | (rtlpriv->buddy_priv && | |
525 | rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process))) | |
526 | return; | |
c7cfe38e C |
527 | /* we juse use em for BE/BK/VI/VO */ |
528 | for (tid = 7; tid >= 0; tid--) { | |
2a00def4 | 529 | u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)]; |
c7cfe38e C |
530 | struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue]; |
531 | while (!mac->act_scanning && | |
532 | rtlpriv->psc.rfpwr_state == ERFON) { | |
533 | struct rtl_tcb_desc tcb_desc; | |
534 | memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); | |
535 | ||
536 | spin_lock_bh(&rtlpriv->locks.waitq_lock); | |
537 | if (!skb_queue_empty(&mac->skb_waitq[tid]) && | |
26634c4b LF |
538 | (ring->entries - skb_queue_len(&ring->queue) > |
539 | rtlhal->max_earlymode_num)) { | |
c7cfe38e C |
540 | skb = skb_dequeue(&mac->skb_waitq[tid]); |
541 | } else { | |
542 | spin_unlock_bh(&rtlpriv->locks.waitq_lock); | |
543 | break; | |
544 | } | |
545 | spin_unlock_bh(&rtlpriv->locks.waitq_lock); | |
546 | ||
547 | /* Some macaddr can't do early mode. like | |
548 | * multicast/broadcast/no_qos data */ | |
549 | info = IEEE80211_SKB_CB(skb); | |
550 | if (info->flags & IEEE80211_TX_CTL_AMPDU) | |
551 | _rtl_update_earlymode_info(hw, skb, | |
552 | &tcb_desc, tid); | |
553 | ||
36323f81 | 554 | rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc); |
c7cfe38e C |
555 | } |
556 | } | |
557 | } | |
558 | ||
559 | ||
0c817338 LF |
560 | static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) |
561 | { | |
562 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
563 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
564 | ||
565 | struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; | |
566 | ||
567 | while (skb_queue_len(&ring->queue)) { | |
0c817338 LF |
568 | struct sk_buff *skb; |
569 | struct ieee80211_tx_info *info; | |
c7cfe38e C |
570 | __le16 fc; |
571 | u8 tid; | |
38506ece | 572 | u8 *entry; |
0c817338 | 573 | |
38506ece LF |
574 | if (rtlpriv->use_new_trx_flow) |
575 | entry = (u8 *)(&ring->buffer_desc[ring->idx]); | |
576 | else | |
577 | entry = (u8 *)(&ring->desc[ring->idx]); | |
0c817338 | 578 | |
d0311314 TT |
579 | if (rtlpriv->cfg->ops->get_available_desc && |
580 | rtlpriv->cfg->ops->get_available_desc(hw, prio) <= 1) { | |
581 | RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_DMESG, | |
582 | "no available desc!\n"); | |
583 | return; | |
584 | } | |
585 | ||
38506ece | 586 | if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx)) |
0c817338 LF |
587 | return; |
588 | ring->idx = (ring->idx + 1) % ring->entries; | |
589 | ||
590 | skb = __skb_dequeue(&ring->queue); | |
591 | pci_unmap_single(rtlpci->pdev, | |
d3bb1429 | 592 | rtlpriv->cfg->ops-> |
38506ece | 593 | get_desc((u8 *)entry, true, |
d3bb1429 | 594 | HW_DESC_TXBUFF_ADDR), |
0c817338 LF |
595 | skb->len, PCI_DMA_TODEVICE); |
596 | ||
c7cfe38e C |
597 | /* remove early mode header */ |
598 | if (rtlpriv->rtlhal.earlymode_enable) | |
599 | skb_pull(skb, EM_HDR_LEN); | |
600 | ||
0c817338 | 601 | RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, |
f30d7507 JP |
602 | "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", |
603 | ring->idx, | |
604 | skb_queue_len(&ring->queue), | |
38506ece | 605 | *(u16 *)(skb->data + 22)); |
0c817338 | 606 | |
c7cfe38e C |
607 | if (prio == TXCMD_QUEUE) { |
608 | dev_kfree_skb(skb); | |
609 | goto tx_status_ok; | |
610 | ||
611 | } | |
612 | ||
613 | /* for sw LPS, just after NULL skb send out, we can | |
26634c4b LF |
614 | * sure AP knows we are sleeping, we should not let |
615 | * rf sleep | |
616 | */ | |
c7cfe38e C |
617 | fc = rtl_get_fc(skb); |
618 | if (ieee80211_is_nullfunc(fc)) { | |
619 | if (ieee80211_has_pm(fc)) { | |
9c050440 | 620 | rtlpriv->mac80211.offchan_delay = true; |
3db1cd5c | 621 | rtlpriv->psc.state_inap = true; |
c7cfe38e | 622 | } else { |
3db1cd5c | 623 | rtlpriv->psc.state_inap = false; |
c7cfe38e C |
624 | } |
625 | } | |
26634c4b LF |
626 | if (ieee80211_is_action(fc)) { |
627 | struct ieee80211_mgmt *action_frame = | |
628 | (struct ieee80211_mgmt *)skb->data; | |
629 | if (action_frame->u.action.u.ht_smps.action == | |
630 | WLAN_HT_ACTION_SMPS) { | |
631 | dev_kfree_skb(skb); | |
632 | goto tx_status_ok; | |
633 | } | |
634 | } | |
c7cfe38e C |
635 | |
636 | /* update tid tx pkt num */ | |
637 | tid = rtl_get_tid(skb); | |
638 | if (tid <= 7) | |
639 | rtlpriv->link_info.tidtx_inperiod[tid]++; | |
640 | ||
0c817338 LF |
641 | info = IEEE80211_SKB_CB(skb); |
642 | ieee80211_tx_info_clear_status(info); | |
643 | ||
644 | info->flags |= IEEE80211_TX_STAT_ACK; | |
645 | /*info->status.rates[0].count = 1; */ | |
646 | ||
647 | ieee80211_tx_status_irqsafe(hw, skb); | |
648 | ||
d0311314 | 649 | if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { |
0c817338 | 650 | |
d0311314 | 651 | RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, |
4f4378de | 652 | "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", |
f30d7507 JP |
653 | prio, ring->idx, |
654 | skb_queue_len(&ring->queue)); | |
0c817338 LF |
655 | |
656 | ieee80211_wake_queue(hw, | |
657 | skb_get_queue_mapping | |
658 | (skb)); | |
659 | } | |
c7cfe38e | 660 | tx_status_ok: |
0c817338 LF |
661 | skb = NULL; |
662 | } | |
663 | ||
664 | if (((rtlpriv->link_info.num_rx_inperiod + | |
665 | rtlpriv->link_info.num_tx_inperiod) > 8) || | |
666 | (rtlpriv->link_info.num_rx_inperiod > 2)) { | |
a269913c LF |
667 | rtlpriv->enter_ps = false; |
668 | schedule_work(&rtlpriv->works.lps_change_work); | |
0c817338 LF |
669 | } |
670 | } | |
671 | ||
38506ece | 672 | static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw, |
e9538cf4 LF |
673 | struct sk_buff *new_skb, u8 *entry, |
674 | int rxring_idx, int desc_idx) | |
fd854772 MM |
675 | { |
676 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
38506ece LF |
677 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
678 | u32 bufferaddress; | |
679 | u8 tmp_one = 1; | |
680 | struct sk_buff *skb; | |
681 | ||
e9538cf4 LF |
682 | if (likely(new_skb)) { |
683 | skb = new_skb; | |
684 | goto remap; | |
685 | } | |
38506ece LF |
686 | skb = dev_alloc_skb(rtlpci->rxbuffersize); |
687 | if (!skb) | |
688 | return 0; | |
38506ece | 689 | |
e9538cf4 | 690 | remap: |
38506ece LF |
691 | /* just set skb->cb to mapping addr for pci_unmap_single use */ |
692 | *((dma_addr_t *)skb->cb) = | |
693 | pci_map_single(rtlpci->pdev, skb_tail_pointer(skb), | |
694 | rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); | |
695 | bufferaddress = *((dma_addr_t *)skb->cb); | |
696 | if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) | |
697 | return 0; | |
e9538cf4 | 698 | rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb; |
38506ece LF |
699 | if (rtlpriv->use_new_trx_flow) { |
700 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, | |
701 | HW_DESC_RX_PREPARE, | |
702 | (u8 *)&bufferaddress); | |
fd854772 | 703 | } else { |
38506ece LF |
704 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, |
705 | HW_DESC_RXBUFF_ADDR, | |
706 | (u8 *)&bufferaddress); | |
707 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, | |
708 | HW_DESC_RXPKT_LEN, | |
709 | (u8 *)&rtlpci->rxbuffersize); | |
710 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, | |
711 | HW_DESC_RXOWN, | |
712 | (u8 *)&tmp_one); | |
fd854772 | 713 | } |
38506ece LF |
714 | return 1; |
715 | } | |
fd854772 | 716 | |
38506ece LF |
717 | /* inorder to receive 8K AMSDU we have set skb to |
718 | * 9100bytes in init rx ring, but if this packet is | |
719 | * not a AMSDU, this large packet will be sent to | |
720 | * TCP/IP directly, this cause big packet ping fail | |
721 | * like: "ping -s 65507", so here we will realloc skb | |
722 | * based on the true size of packet, Mac80211 | |
723 | * Probably will do it better, but does not yet. | |
724 | * | |
725 | * Some platform will fail when alloc skb sometimes. | |
726 | * in this condition, we will send the old skb to | |
727 | * mac80211 directly, this will not cause any other | |
728 | * issues, but only this packet will be lost by TCP/IP | |
729 | */ | |
730 | static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw, | |
731 | struct sk_buff *skb, | |
732 | struct ieee80211_rx_status rx_status) | |
733 | { | |
734 | if (unlikely(!rtl_action_proc(hw, skb, false))) { | |
735 | dev_kfree_skb_any(skb); | |
736 | } else { | |
737 | struct sk_buff *uskb = NULL; | |
738 | u8 *pdata; | |
739 | ||
740 | uskb = dev_alloc_skb(skb->len + 128); | |
741 | if (likely(uskb)) { | |
742 | memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, | |
743 | sizeof(rx_status)); | |
744 | pdata = (u8 *)skb_put(uskb, skb->len); | |
745 | memcpy(pdata, skb->data, skb->len); | |
746 | dev_kfree_skb_any(skb); | |
747 | ieee80211_rx_irqsafe(hw, uskb); | |
748 | } else { | |
749 | ieee80211_rx_irqsafe(hw, skb); | |
750 | } | |
fd854772 | 751 | } |
38506ece | 752 | } |
fd854772 | 753 | |
38506ece LF |
754 | /*hsisr interrupt handler*/ |
755 | static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw) | |
756 | { | |
757 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
758 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
fd854772 | 759 | |
38506ece LF |
760 | rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR], |
761 | rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) | | |
762 | rtlpci->sys_irq_mask); | |
fd854772 MM |
763 | } |
764 | ||
0c817338 LF |
765 | static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) |
766 | { | |
767 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
768 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
38506ece | 769 | int rxring_idx = RTL_PCI_RX_MPDU_QUEUE; |
0c817338 LF |
770 | struct ieee80211_rx_status rx_status = { 0 }; |
771 | unsigned int count = rtlpci->rxringcount; | |
772 | u8 own; | |
773 | u8 tmp_one; | |
38506ece LF |
774 | bool unicast = false; |
775 | u8 hw_queue = 0; | |
776 | unsigned int rx_remained_cnt; | |
0c817338 LF |
777 | struct rtl_stats stats = { |
778 | .signal = 0, | |
0c817338 LF |
779 | .rate = 0, |
780 | }; | |
781 | ||
782 | /*RX NORMAL PKT */ | |
783 | while (count--) { | |
38506ece LF |
784 | struct ieee80211_hdr *hdr; |
785 | __le16 fc; | |
786 | u16 len; | |
787 | /*rx buffer descriptor */ | |
788 | struct rtl_rx_buffer_desc *buffer_desc = NULL; | |
789 | /*if use new trx flow, it means wifi info */ | |
790 | struct rtl_rx_desc *pdesc = NULL; | |
0c817338 | 791 | /*rx pkt */ |
38506ece LF |
792 | struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[ |
793 | rtlpci->rx_ring[rxring_idx].idx]; | |
e9538cf4 | 794 | struct sk_buff *new_skb; |
38506ece LF |
795 | |
796 | if (rtlpriv->use_new_trx_flow) { | |
797 | rx_remained_cnt = | |
798 | rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw, | |
799 | hw_queue); | |
d0311314 | 800 | if (rx_remained_cnt == 0) |
38506ece | 801 | return; |
f99551a2 LF |
802 | buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[ |
803 | rtlpci->rx_ring[rxring_idx].idx]; | |
804 | pdesc = (struct rtl_rx_desc *)skb->data; | |
38506ece LF |
805 | } else { /* rx descriptor */ |
806 | pdesc = &rtlpci->rx_ring[rxring_idx].desc[ | |
807 | rtlpci->rx_ring[rxring_idx].idx]; | |
808 | ||
809 | own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)pdesc, | |
810 | false, | |
811 | HW_DESC_OWN); | |
812 | if (own) /* wait data to be filled by hardware */ | |
813 | return; | |
814 | } | |
6633d649 | 815 | |
38506ece LF |
816 | /* Reaching this point means: data is filled already |
817 | * AAAAAAttention !!! | |
818 | * We can NOT access 'skb' before 'pci_unmap_single' | |
819 | */ | |
820 | pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), | |
821 | rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); | |
822 | ||
e9538cf4 LF |
823 | /* get a new skb - if fail, old one will be reused */ |
824 | new_skb = dev_alloc_skb(rtlpci->rxbuffersize); | |
aeb2d2a4 | 825 | if (unlikely(!new_skb)) |
e9538cf4 | 826 | goto no_new; |
38506ece | 827 | memset(&rx_status , 0 , sizeof(rx_status)); |
2c333366 | 828 | rtlpriv->cfg->ops->query_rx_desc(hw, &stats, |
38506ece | 829 | &rx_status, (u8 *)pdesc, skb); |
2c333366 | 830 | |
38506ece LF |
831 | if (rtlpriv->use_new_trx_flow) |
832 | rtlpriv->cfg->ops->rx_check_dma_ok(hw, | |
833 | (u8 *)buffer_desc, | |
834 | hw_queue); | |
8db8ddf1 | 835 | |
38506ece LF |
836 | len = rtlpriv->cfg->ops->get_desc((u8 *)pdesc, false, |
837 | HW_DESC_RXPKT_LEN); | |
2c333366 | 838 | |
38506ece LF |
839 | if (skb->end - skb->tail > len) { |
840 | skb_put(skb, len); | |
841 | if (rtlpriv->use_new_trx_flow) | |
842 | skb_reserve(skb, stats.rx_drvinfo_size + | |
843 | stats.rx_bufshift + 24); | |
844 | else | |
845 | skb_reserve(skb, stats.rx_drvinfo_size + | |
846 | stats.rx_bufshift); | |
38506ece LF |
847 | } else { |
848 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
849 | "skb->end - skb->tail = %d, len is %d\n", | |
850 | skb->end - skb->tail, len); | |
d0311314 TT |
851 | dev_kfree_skb_any(skb); |
852 | goto new_trx_end; | |
38506ece LF |
853 | } |
854 | /* handle command packet here */ | |
d1cd5ba4 | 855 | if (rtlpriv->cfg->ops->rx_command_packet && |
ce254243 | 856 | rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) { |
38506ece | 857 | dev_kfree_skb_any(skb); |
d0311314 | 858 | goto new_trx_end; |
38506ece | 859 | } |
2c333366 MM |
860 | |
861 | /* | |
862 | * NOTICE This can not be use for mac80211, | |
863 | * this is done in mac80211 code, | |
38506ece | 864 | * if done here sec DHCP will fail |
2c333366 MM |
865 | * skb_trim(skb, skb->len - 4); |
866 | */ | |
867 | ||
38506ece LF |
868 | hdr = rtl_get_hdr(skb); |
869 | fc = rtl_get_fc(skb); | |
870 | ||
871 | if (!stats.crc && !stats.hwerror) { | |
872 | memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, | |
873 | sizeof(rx_status)); | |
874 | ||
875 | if (is_broadcast_ether_addr(hdr->addr1)) { | |
876 | ;/*TODO*/ | |
877 | } else if (is_multicast_ether_addr(hdr->addr1)) { | |
878 | ;/*TODO*/ | |
879 | } else { | |
880 | unicast = true; | |
881 | rtlpriv->stats.rxbytesunicast += skb->len; | |
882 | } | |
cad737df | 883 | rtl_is_special_data(hw, skb, false, true); |
0c817338 | 884 | |
38506ece LF |
885 | if (ieee80211_is_data(fc)) { |
886 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX); | |
887 | if (unicast) | |
888 | rtlpriv->link_info.num_rx_inperiod++; | |
889 | } | |
890 | /* static bcn for roaming */ | |
891 | rtl_beacon_statistic(hw, skb); | |
892 | rtl_p2p_info(hw, (void *)skb->data, skb->len); | |
893 | /* for sw lps */ | |
894 | rtl_swlps_beacon(hw, (void *)skb->data, skb->len); | |
895 | rtl_recognize_peer(hw, (void *)skb->data, skb->len); | |
896 | if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) && | |
897 | (rtlpriv->rtlhal.current_bandtype == | |
898 | BAND_ON_2_4G) && | |
899 | (ieee80211_is_beacon(fc) || | |
900 | ieee80211_is_probe_resp(fc))) { | |
901 | dev_kfree_skb_any(skb); | |
902 | } else { | |
903 | _rtl_pci_rx_to_mac80211(hw, skb, rx_status); | |
904 | } | |
905 | } else { | |
906 | dev_kfree_skb_any(skb); | |
907 | } | |
d0311314 | 908 | new_trx_end: |
38506ece LF |
909 | if (rtlpriv->use_new_trx_flow) { |
910 | rtlpci->rx_ring[hw_queue].next_rx_rp += 1; | |
911 | rtlpci->rx_ring[hw_queue].next_rx_rp %= | |
912 | RTL_PCI_MAX_RX_COUNT; | |
913 | ||
914 | rx_remained_cnt--; | |
915 | rtl_write_word(rtlpriv, 0x3B4, | |
916 | rtlpci->rx_ring[hw_queue].next_rx_rp); | |
917 | } | |
2c333366 | 918 | if (((rtlpriv->link_info.num_rx_inperiod + |
a269913c LF |
919 | rtlpriv->link_info.num_tx_inperiod) > 8) || |
920 | (rtlpriv->link_info.num_rx_inperiod > 2)) { | |
921 | rtlpriv->enter_ps = false; | |
922 | schedule_work(&rtlpriv->works.lps_change_work); | |
2c333366 | 923 | } |
e9538cf4 LF |
924 | skb = new_skb; |
925 | no_new: | |
38506ece | 926 | if (rtlpriv->use_new_trx_flow) { |
e9538cf4 | 927 | _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc, |
38506ece | 928 | rxring_idx, |
e9538cf4 | 929 | rtlpci->rx_ring[rxring_idx].idx); |
38506ece | 930 | } else { |
e9538cf4 LF |
931 | _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc, |
932 | rxring_idx, | |
38506ece | 933 | rtlpci->rx_ring[rxring_idx].idx); |
38506ece LF |
934 | if (rtlpci->rx_ring[rxring_idx].idx == |
935 | rtlpci->rxringcount - 1) | |
936 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, | |
937 | false, | |
938 | HW_DESC_RXERO, | |
939 | (u8 *)&tmp_one); | |
940 | } | |
941 | rtlpci->rx_ring[rxring_idx].idx = | |
942 | (rtlpci->rx_ring[rxring_idx].idx + 1) % | |
943 | rtlpci->rxringcount; | |
0c817338 | 944 | } |
0c817338 LF |
945 | } |
946 | ||
0c817338 LF |
947 | static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) |
948 | { | |
949 | struct ieee80211_hw *hw = dev_id; | |
38506ece | 950 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); |
0c817338 | 951 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
c7cfe38e | 952 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); |
0c817338 LF |
953 | unsigned long flags; |
954 | u32 inta = 0; | |
955 | u32 intb = 0; | |
de2e56ce | 956 | irqreturn_t ret = IRQ_HANDLED; |
0c817338 | 957 | |
38506ece LF |
958 | if (rtlpci->irq_enabled == 0) |
959 | return ret; | |
960 | ||
961 | spin_lock_irqsave(&rtlpriv->locks.irq_th_lock , flags); | |
962 | rtlpriv->cfg->ops->disable_interrupt(hw); | |
0c817338 LF |
963 | |
964 | /*read ISR: 4/8bytes */ | |
965 | rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb); | |
966 | ||
967 | /*Shared IRQ or HW disappared */ | |
0529c6b8 | 968 | if (!inta || inta == 0xffff) |
0c817338 LF |
969 | goto done; |
970 | ||
971 | /*<1> beacon related */ | |
972 | if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) { | |
973 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 974 | "beacon ok interrupt!\n"); |
0c817338 LF |
975 | } |
976 | ||
977 | if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) { | |
978 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 979 | "beacon err interrupt!\n"); |
0c817338 LF |
980 | } |
981 | ||
982 | if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) { | |
f30d7507 | 983 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); |
0c817338 LF |
984 | } |
985 | ||
e6deaf81 | 986 | if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { |
0c817338 | 987 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, |
f30d7507 | 988 | "prepare beacon for interrupt!\n"); |
0c817338 LF |
989 | tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); |
990 | } | |
991 | ||
38506ece LF |
992 | /*<2> Tx related */ |
993 | if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) | |
f30d7507 | 994 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); |
0c817338 LF |
995 | |
996 | if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { | |
997 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 998 | "Manage ok interrupt!\n"); |
0c817338 LF |
999 | _rtl_pci_tx_isr(hw, MGNT_QUEUE); |
1000 | } | |
1001 | ||
1002 | if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { | |
1003 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 1004 | "HIGH_QUEUE ok interrupt!\n"); |
0c817338 LF |
1005 | _rtl_pci_tx_isr(hw, HIGH_QUEUE); |
1006 | } | |
1007 | ||
1008 | if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { | |
1009 | rtlpriv->link_info.num_tx_inperiod++; | |
1010 | ||
1011 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 1012 | "BK Tx OK interrupt!\n"); |
0c817338 LF |
1013 | _rtl_pci_tx_isr(hw, BK_QUEUE); |
1014 | } | |
1015 | ||
1016 | if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { | |
1017 | rtlpriv->link_info.num_tx_inperiod++; | |
1018 | ||
1019 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 1020 | "BE TX OK interrupt!\n"); |
0c817338 LF |
1021 | _rtl_pci_tx_isr(hw, BE_QUEUE); |
1022 | } | |
1023 | ||
1024 | if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { | |
1025 | rtlpriv->link_info.num_tx_inperiod++; | |
1026 | ||
1027 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 1028 | "VI TX OK interrupt!\n"); |
0c817338 LF |
1029 | _rtl_pci_tx_isr(hw, VI_QUEUE); |
1030 | } | |
1031 | ||
1032 | if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { | |
1033 | rtlpriv->link_info.num_tx_inperiod++; | |
1034 | ||
1035 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 1036 | "Vo TX OK interrupt!\n"); |
0c817338 LF |
1037 | _rtl_pci_tx_isr(hw, VO_QUEUE); |
1038 | } | |
1039 | ||
c7cfe38e C |
1040 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) { |
1041 | if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { | |
1042 | rtlpriv->link_info.num_tx_inperiod++; | |
1043 | ||
1044 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
f30d7507 | 1045 | "CMD TX OK interrupt!\n"); |
c7cfe38e C |
1046 | _rtl_pci_tx_isr(hw, TXCMD_QUEUE); |
1047 | } | |
1048 | } | |
1049 | ||
38506ece | 1050 | /*<3> Rx related */ |
0c817338 | 1051 | if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { |
f30d7507 | 1052 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); |
c7cfe38e | 1053 | _rtl_pci_rx_interrupt(hw); |
0c817338 LF |
1054 | } |
1055 | ||
1056 | if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { | |
1057 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 | 1058 | "rx descriptor unavailable!\n"); |
c7cfe38e | 1059 | _rtl_pci_rx_interrupt(hw); |
0c817338 LF |
1060 | } |
1061 | ||
38506ece | 1062 | if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { |
f30d7507 | 1063 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); |
c7cfe38e | 1064 | _rtl_pci_rx_interrupt(hw); |
0c817338 LF |
1065 | } |
1066 | ||
38506ece | 1067 | /*<4> fw related*/ |
26634c4b LF |
1068 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { |
1069 | if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { | |
1070 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
1071 | "firmware interrupt!\n"); | |
1072 | queue_delayed_work(rtlpriv->works.rtl_wq, | |
1073 | &rtlpriv->works.fwevt_wq, 0); | |
1074 | } | |
1075 | } | |
1076 | ||
38506ece LF |
1077 | /*<5> hsisr related*/ |
1078 | /* Only 8188EE & 8723BE Supported. | |
1079 | * If Other ICs Come in, System will corrupt, | |
1080 | * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR] | |
1081 | * are not initialized | |
1082 | */ | |
1083 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE || | |
1084 | rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { | |
1085 | if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { | |
1086 | RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, | |
1087 | "hsisr interrupt!\n"); | |
1088 | _rtl_pci_hs_interrupt(hw); | |
1089 | } | |
1090 | } | |
1091 | ||
c7cfe38e C |
1092 | if (rtlpriv->rtlhal.earlymode_enable) |
1093 | tasklet_schedule(&rtlpriv->works.irq_tasklet); | |
1094 | ||
0c817338 | 1095 | done: |
38506ece | 1096 | rtlpriv->cfg->ops->enable_interrupt(hw); |
0c817338 | 1097 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); |
de2e56ce | 1098 | return ret; |
0c817338 LF |
1099 | } |
1100 | ||
1101 | static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw) | |
1102 | { | |
c7cfe38e | 1103 | _rtl_pci_tx_chk_waitq(hw); |
0c817338 LF |
1104 | } |
1105 | ||
1106 | static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw) | |
1107 | { | |
1108 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1109 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1110 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
c7cfe38e | 1111 | struct rtl8192_tx_ring *ring = NULL; |
0c817338 LF |
1112 | struct ieee80211_hdr *hdr = NULL; |
1113 | struct ieee80211_tx_info *info = NULL; | |
1114 | struct sk_buff *pskb = NULL; | |
1115 | struct rtl_tx_desc *pdesc = NULL; | |
c7cfe38e | 1116 | struct rtl_tcb_desc tcb_desc; |
f3355dd9 LF |
1117 | /*This is for new trx flow*/ |
1118 | struct rtl_tx_buffer_desc *pbuffer_desc = NULL; | |
0c817338 | 1119 | u8 temp_one = 1; |
be0b5e63 | 1120 | u8 *entry; |
0c817338 | 1121 | |
c7cfe38e | 1122 | memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); |
0c817338 LF |
1123 | ring = &rtlpci->tx_ring[BEACON_QUEUE]; |
1124 | pskb = __skb_dequeue(&ring->queue); | |
be0b5e63 LF |
1125 | if (rtlpriv->use_new_trx_flow) |
1126 | entry = (u8 *)(&ring->buffer_desc[ring->idx]); | |
1127 | else | |
1128 | entry = (u8 *)(&ring->desc[ring->idx]); | |
1129 | if (pskb) { | |
1130 | pci_unmap_single(rtlpci->pdev, | |
1131 | rtlpriv->cfg->ops->get_desc( | |
1132 | (u8 *)entry, true, HW_DESC_TXBUFF_ADDR), | |
1133 | pskb->len, PCI_DMA_TODEVICE); | |
0c817338 | 1134 | kfree_skb(pskb); |
be0b5e63 | 1135 | } |
0c817338 LF |
1136 | |
1137 | /*NB: the beacon data buffer must be 32-bit aligned. */ | |
1138 | pskb = ieee80211_beacon_get(hw, mac->vif); | |
1139 | if (pskb == NULL) | |
1140 | return; | |
c7cfe38e | 1141 | hdr = rtl_get_hdr(pskb); |
0c817338 | 1142 | info = IEEE80211_SKB_CB(pskb); |
0c817338 | 1143 | pdesc = &ring->desc[0]; |
38506ece LF |
1144 | if (rtlpriv->use_new_trx_flow) |
1145 | pbuffer_desc = &ring->buffer_desc[0]; | |
1146 | ||
1147 | rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, | |
f3355dd9 LF |
1148 | (u8 *)pbuffer_desc, info, NULL, pskb, |
1149 | BEACON_QUEUE, &tcb_desc); | |
0c817338 LF |
1150 | |
1151 | __skb_queue_tail(&ring->queue, pskb); | |
1152 | ||
fb6eaf2c LF |
1153 | if (rtlpriv->use_new_trx_flow) { |
1154 | temp_one = 4; | |
1155 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true, | |
1156 | HW_DESC_OWN, (u8 *)&temp_one); | |
1157 | } else { | |
1158 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN, | |
1159 | &temp_one); | |
1160 | } | |
0c817338 LF |
1161 | return; |
1162 | } | |
1163 | ||
1164 | static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw) | |
1165 | { | |
1166 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
38506ece LF |
1167 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
1168 | struct rtl_hal *rtlhal = rtl_hal(rtlpriv); | |
0c817338 | 1169 | u8 i; |
38506ece LF |
1170 | u16 desc_num; |
1171 | ||
1172 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) | |
1173 | desc_num = TX_DESC_NUM_92E; | |
1174 | else | |
1175 | desc_num = RT_TXDESC_NUM; | |
0c817338 LF |
1176 | |
1177 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) | |
38506ece | 1178 | rtlpci->txringcount[i] = desc_num; |
0c817338 LF |
1179 | |
1180 | /* | |
1181 | *we just alloc 2 desc for beacon queue, | |
1182 | *because we just need first desc in hw beacon. | |
1183 | */ | |
1184 | rtlpci->txringcount[BEACON_QUEUE] = 2; | |
1185 | ||
38506ece | 1186 | /*BE queue need more descriptor for performance |
0c817338 LF |
1187 | *consideration or, No more tx desc will happen, |
1188 | *and may cause mac80211 mem leakage. | |
1189 | */ | |
38506ece LF |
1190 | if (!rtl_priv(hw)->use_new_trx_flow) |
1191 | rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE; | |
0c817338 LF |
1192 | |
1193 | rtlpci->rxbuffersize = 9100; /*2048/1024; */ | |
1194 | rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */ | |
1195 | } | |
1196 | ||
1197 | static void _rtl_pci_init_struct(struct ieee80211_hw *hw, | |
1198 | struct pci_dev *pdev) | |
1199 | { | |
1200 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1201 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); | |
1202 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1203 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
0c817338 LF |
1204 | |
1205 | rtlpci->up_first_time = true; | |
1206 | rtlpci->being_init_adapter = false; | |
1207 | ||
1208 | rtlhal->hw = hw; | |
1209 | rtlpci->pdev = pdev; | |
1210 | ||
0c817338 LF |
1211 | /*Tx/Rx related var */ |
1212 | _rtl_pci_init_trx_var(hw); | |
1213 | ||
37c52934 LF |
1214 | /*IBSS*/ |
1215 | mac->beacon_interval = 100; | |
0c817338 | 1216 | |
c7cfe38e C |
1217 | /*AMPDU*/ |
1218 | mac->min_space_cfg = 0; | |
0c817338 LF |
1219 | mac->max_mss_density = 0; |
1220 | /*set sane AMPDU defaults */ | |
1221 | mac->current_ampdu_density = 7; | |
1222 | mac->current_ampdu_factor = 3; | |
1223 | ||
c7cfe38e | 1224 | /*QOS*/ |
2cddad3c | 1225 | rtlpci->acm_method = EACMWAY2_SW; |
0c817338 LF |
1226 | |
1227 | /*task */ | |
1228 | tasklet_init(&rtlpriv->works.irq_tasklet, | |
1229 | (void (*)(unsigned long))_rtl_pci_irq_tasklet, | |
1230 | (unsigned long)hw); | |
1231 | tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet, | |
1232 | (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet, | |
1233 | (unsigned long)hw); | |
a269913c LF |
1234 | INIT_WORK(&rtlpriv->works.lps_change_work, |
1235 | rtl_lps_change_work_callback); | |
0c817338 LF |
1236 | } |
1237 | ||
1238 | static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, | |
1239 | unsigned int prio, unsigned int entries) | |
1240 | { | |
1241 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1242 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
38506ece LF |
1243 | struct rtl_tx_buffer_desc *buffer_desc; |
1244 | struct rtl_tx_desc *desc; | |
1245 | dma_addr_t buffer_desc_dma, desc_dma; | |
0c817338 LF |
1246 | u32 nextdescaddress; |
1247 | int i; | |
1248 | ||
38506ece LF |
1249 | /* alloc tx buffer desc for new trx flow*/ |
1250 | if (rtlpriv->use_new_trx_flow) { | |
1251 | buffer_desc = | |
1252 | pci_zalloc_consistent(rtlpci->pdev, | |
1253 | sizeof(*buffer_desc) * entries, | |
1254 | &buffer_desc_dma); | |
1255 | ||
1256 | if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) { | |
1257 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
1258 | "Cannot allocate TX ring (prio = %d)\n", | |
1259 | prio); | |
1260 | return -ENOMEM; | |
1261 | } | |
1262 | ||
1263 | rtlpci->tx_ring[prio].buffer_desc = buffer_desc; | |
1264 | rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma; | |
1265 | ||
1266 | rtlpci->tx_ring[prio].cur_tx_rp = 0; | |
1267 | rtlpci->tx_ring[prio].cur_tx_wp = 0; | |
1268 | rtlpci->tx_ring[prio].avl_desc = entries; | |
1269 | } | |
1270 | ||
1271 | /* alloc dma for this ring */ | |
1272 | desc = pci_zalloc_consistent(rtlpci->pdev, | |
1273 | sizeof(*desc) * entries, &desc_dma); | |
1274 | ||
1275 | if (!desc || (unsigned long)desc & 0xFF) { | |
0c817338 | 1276 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
f30d7507 | 1277 | "Cannot allocate TX ring (prio = %d)\n", prio); |
0c817338 LF |
1278 | return -ENOMEM; |
1279 | } | |
1280 | ||
38506ece LF |
1281 | rtlpci->tx_ring[prio].desc = desc; |
1282 | rtlpci->tx_ring[prio].dma = desc_dma; | |
1283 | ||
0c817338 LF |
1284 | rtlpci->tx_ring[prio].idx = 0; |
1285 | rtlpci->tx_ring[prio].entries = entries; | |
1286 | skb_queue_head_init(&rtlpci->tx_ring[prio].queue); | |
1287 | ||
f30d7507 | 1288 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", |
38506ece LF |
1289 | prio, desc); |
1290 | ||
1291 | /* init every desc in this ring */ | |
1292 | if (!rtlpriv->use_new_trx_flow) { | |
1293 | for (i = 0; i < entries; i++) { | |
1294 | nextdescaddress = (u32)desc_dma + | |
1295 | ((i + 1) % entries) * | |
1296 | sizeof(*desc); | |
1297 | ||
1298 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i], | |
1299 | true, | |
1300 | HW_DESC_TX_NEXTDESC_ADDR, | |
1301 | (u8 *)&nextdescaddress); | |
1302 | } | |
0c817338 | 1303 | } |
0c817338 LF |
1304 | return 0; |
1305 | } | |
1306 | ||
38506ece | 1307 | static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx) |
0c817338 LF |
1308 | { |
1309 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1310 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
38506ece | 1311 | int i; |
0c817338 | 1312 | |
38506ece LF |
1313 | if (rtlpriv->use_new_trx_flow) { |
1314 | struct rtl_rx_buffer_desc *entry = NULL; | |
1315 | /* alloc dma for this ring */ | |
1316 | rtlpci->rx_ring[rxring_idx].buffer_desc = | |
1317 | pci_zalloc_consistent(rtlpci->pdev, | |
1318 | sizeof(*rtlpci->rx_ring[rxring_idx]. | |
1319 | buffer_desc) * | |
1320 | rtlpci->rxringcount, | |
1321 | &rtlpci->rx_ring[rxring_idx].dma); | |
1322 | if (!rtlpci->rx_ring[rxring_idx].buffer_desc || | |
1323 | (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) { | |
0c817338 | 1324 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, |
f30d7507 | 1325 | "Cannot allocate RX ring\n"); |
0c817338 LF |
1326 | return -ENOMEM; |
1327 | } | |
1328 | ||
38506ece LF |
1329 | /* init every desc in this ring */ |
1330 | rtlpci->rx_ring[rxring_idx].idx = 0; | |
1331 | for (i = 0; i < rtlpci->rxringcount; i++) { | |
1332 | entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i]; | |
e9538cf4 | 1333 | if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, |
38506ece LF |
1334 | rxring_idx, i)) |
1335 | return -ENOMEM; | |
1336 | } | |
1337 | } else { | |
1338 | struct rtl_rx_desc *entry = NULL; | |
1339 | u8 tmp_one = 1; | |
1340 | /* alloc dma for this ring */ | |
1341 | rtlpci->rx_ring[rxring_idx].desc = | |
1342 | pci_zalloc_consistent(rtlpci->pdev, | |
1343 | sizeof(*rtlpci->rx_ring[rxring_idx]. | |
1344 | desc) * rtlpci->rxringcount, | |
1345 | &rtlpci->rx_ring[rxring_idx].dma); | |
1346 | if (!rtlpci->rx_ring[rxring_idx].desc || | |
1347 | (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) { | |
1348 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
1349 | "Cannot allocate RX ring\n"); | |
1350 | return -ENOMEM; | |
1351 | } | |
0c817338 | 1352 | |
38506ece LF |
1353 | /* init every desc in this ring */ |
1354 | rtlpci->rx_ring[rxring_idx].idx = 0; | |
0019a2c9 | 1355 | |
0c817338 | 1356 | for (i = 0; i < rtlpci->rxringcount; i++) { |
38506ece | 1357 | entry = &rtlpci->rx_ring[rxring_idx].desc[i]; |
e9538cf4 | 1358 | if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry, |
38506ece LF |
1359 | rxring_idx, i)) |
1360 | return -ENOMEM; | |
0c817338 LF |
1361 | } |
1362 | ||
f3355dd9 | 1363 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, |
2c208890 | 1364 | HW_DESC_RXERO, &tmp_one); |
0c817338 LF |
1365 | } |
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw, | |
1370 | unsigned int prio) | |
1371 | { | |
1372 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1373 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1374 | struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio]; | |
1375 | ||
38506ece | 1376 | /* free every desc in this ring */ |
0c817338 | 1377 | while (skb_queue_len(&ring->queue)) { |
38506ece | 1378 | u8 *entry; |
0c817338 LF |
1379 | struct sk_buff *skb = __skb_dequeue(&ring->queue); |
1380 | ||
38506ece LF |
1381 | if (rtlpriv->use_new_trx_flow) |
1382 | entry = (u8 *)(&ring->buffer_desc[ring->idx]); | |
1383 | else | |
1384 | entry = (u8 *)(&ring->desc[ring->idx]); | |
1385 | ||
0c817338 | 1386 | pci_unmap_single(rtlpci->pdev, |
d3bb1429 | 1387 | rtlpriv->cfg-> |
38506ece | 1388 | ops->get_desc((u8 *)entry, true, |
d3bb1429 | 1389 | HW_DESC_TXBUFF_ADDR), |
0c817338 LF |
1390 | skb->len, PCI_DMA_TODEVICE); |
1391 | kfree_skb(skb); | |
1392 | ring->idx = (ring->idx + 1) % ring->entries; | |
1393 | } | |
1394 | ||
38506ece LF |
1395 | /* free dma of this ring */ |
1396 | pci_free_consistent(rtlpci->pdev, | |
1397 | sizeof(*ring->desc) * ring->entries, | |
1398 | ring->desc, ring->dma); | |
1399 | ring->desc = NULL; | |
1400 | if (rtlpriv->use_new_trx_flow) { | |
7f66c2f9 | 1401 | pci_free_consistent(rtlpci->pdev, |
caea2172 | 1402 | sizeof(*ring->buffer_desc) * ring->entries, |
38506ece | 1403 | ring->buffer_desc, ring->buffer_desc_dma); |
caea2172 | 1404 | ring->buffer_desc = NULL; |
7f66c2f9 | 1405 | } |
0c817338 LF |
1406 | } |
1407 | ||
38506ece | 1408 | static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx) |
0c817338 | 1409 | { |
38506ece LF |
1410 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
1411 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1412 | int i; | |
0c817338 | 1413 | |
38506ece LF |
1414 | /* free every desc in this ring */ |
1415 | for (i = 0; i < rtlpci->rxringcount; i++) { | |
1416 | struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i]; | |
0c817338 | 1417 | |
38506ece LF |
1418 | if (!skb) |
1419 | continue; | |
1420 | pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb), | |
1421 | rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE); | |
1422 | kfree_skb(skb); | |
1423 | } | |
1424 | ||
1425 | /* free dma of this ring */ | |
1426 | if (rtlpriv->use_new_trx_flow) { | |
1427 | pci_free_consistent(rtlpci->pdev, | |
1428 | sizeof(*rtlpci->rx_ring[rxring_idx]. | |
1429 | buffer_desc) * rtlpci->rxringcount, | |
1430 | rtlpci->rx_ring[rxring_idx].buffer_desc, | |
1431 | rtlpci->rx_ring[rxring_idx].dma); | |
1432 | rtlpci->rx_ring[rxring_idx].buffer_desc = NULL; | |
1433 | } else { | |
1434 | pci_free_consistent(rtlpci->pdev, | |
1435 | sizeof(*rtlpci->rx_ring[rxring_idx].desc) * | |
1436 | rtlpci->rxringcount, | |
1437 | rtlpci->rx_ring[rxring_idx].desc, | |
1438 | rtlpci->rx_ring[rxring_idx].dma); | |
1439 | rtlpci->rx_ring[rxring_idx].desc = NULL; | |
0c817338 LF |
1440 | } |
1441 | } | |
1442 | ||
1443 | static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw) | |
1444 | { | |
1445 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1446 | int ret; | |
38506ece | 1447 | int i, rxring_idx; |
0c817338 | 1448 | |
38506ece LF |
1449 | /* rxring_idx 0:RX_MPDU_QUEUE |
1450 | * rxring_idx 1:RX_CMD_QUEUE | |
1451 | */ | |
1452 | for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { | |
1453 | ret = _rtl_pci_init_rx_ring(hw, rxring_idx); | |
1454 | if (ret) | |
1455 | return ret; | |
1456 | } | |
0c817338 LF |
1457 | |
1458 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { | |
1459 | ret = _rtl_pci_init_tx_ring(hw, i, | |
1460 | rtlpci->txringcount[i]); | |
1461 | if (ret) | |
1462 | goto err_free_rings; | |
1463 | } | |
1464 | ||
1465 | return 0; | |
1466 | ||
1467 | err_free_rings: | |
38506ece LF |
1468 | for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) |
1469 | _rtl_pci_free_rx_ring(hw, rxring_idx); | |
0c817338 LF |
1470 | |
1471 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) | |
38506ece LF |
1472 | if (rtlpci->tx_ring[i].desc || |
1473 | rtlpci->tx_ring[i].buffer_desc) | |
0c817338 LF |
1474 | _rtl_pci_free_tx_ring(hw, i); |
1475 | ||
1476 | return 1; | |
1477 | } | |
1478 | ||
1479 | static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw) | |
1480 | { | |
38506ece | 1481 | u32 i, rxring_idx; |
0c817338 LF |
1482 | |
1483 | /*free rx rings */ | |
38506ece LF |
1484 | for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) |
1485 | _rtl_pci_free_rx_ring(hw, rxring_idx); | |
0c817338 LF |
1486 | |
1487 | /*free tx rings */ | |
1488 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) | |
1489 | _rtl_pci_free_tx_ring(hw, i); | |
1490 | ||
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw) | |
1495 | { | |
1496 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1497 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
38506ece | 1498 | int i, rxring_idx; |
0c817338 LF |
1499 | unsigned long flags; |
1500 | u8 tmp_one = 1; | |
38506ece LF |
1501 | u32 bufferaddress; |
1502 | /* rxring_idx 0:RX_MPDU_QUEUE */ | |
1503 | /* rxring_idx 1:RX_CMD_QUEUE */ | |
1504 | for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) { | |
1505 | /* force the rx_ring[RX_MPDU_QUEUE/ | |
1506 | * RX_CMD_QUEUE].idx to the first one | |
1507 | *new trx flow, do nothing | |
1508 | */ | |
1509 | if (!rtlpriv->use_new_trx_flow && | |
1510 | rtlpci->rx_ring[rxring_idx].desc) { | |
0c817338 LF |
1511 | struct rtl_rx_desc *entry = NULL; |
1512 | ||
38506ece | 1513 | rtlpci->rx_ring[rxring_idx].idx = 0; |
0c817338 | 1514 | for (i = 0; i < rtlpci->rxringcount; i++) { |
38506ece LF |
1515 | entry = &rtlpci->rx_ring[rxring_idx].desc[i]; |
1516 | bufferaddress = | |
1517 | rtlpriv->cfg->ops->get_desc((u8 *)entry, | |
1518 | false , HW_DESC_RXBUFF_ADDR); | |
1519 | memset((u8 *)entry , 0 , | |
1520 | sizeof(*rtlpci->rx_ring | |
1521 | [rxring_idx].desc));/*clear one entry*/ | |
1522 | if (rtlpriv->use_new_trx_flow) { | |
1523 | rtlpriv->cfg->ops->set_desc(hw, | |
1524 | (u8 *)entry, false, | |
1525 | HW_DESC_RX_PREPARE, | |
1526 | (u8 *)&bufferaddress); | |
1527 | } else { | |
1528 | rtlpriv->cfg->ops->set_desc(hw, | |
1529 | (u8 *)entry, false, | |
1530 | HW_DESC_RXBUFF_ADDR, | |
1531 | (u8 *)&bufferaddress); | |
1532 | rtlpriv->cfg->ops->set_desc(hw, | |
1533 | (u8 *)entry, false, | |
1534 | HW_DESC_RXPKT_LEN, | |
1535 | (u8 *)&rtlpci->rxbuffersize); | |
1536 | rtlpriv->cfg->ops->set_desc(hw, | |
1537 | (u8 *)entry, false, | |
1538 | HW_DESC_RXOWN, | |
1539 | (u8 *)&tmp_one); | |
1540 | } | |
0c817338 | 1541 | } |
38506ece LF |
1542 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false, |
1543 | HW_DESC_RXERO, (u8 *)&tmp_one); | |
0c817338 | 1544 | } |
38506ece | 1545 | rtlpci->rx_ring[rxring_idx].idx = 0; |
0c817338 LF |
1546 | } |
1547 | ||
1548 | /* | |
1549 | *after reset, release previous pending packet, | |
1550 | *and force the tx idx to the first one | |
1551 | */ | |
38506ece | 1552 | spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); |
0c817338 | 1553 | for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) { |
38506ece LF |
1554 | if (rtlpci->tx_ring[i].desc || |
1555 | rtlpci->tx_ring[i].buffer_desc) { | |
0c817338 LF |
1556 | struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i]; |
1557 | ||
1558 | while (skb_queue_len(&ring->queue)) { | |
38506ece LF |
1559 | u8 *entry; |
1560 | struct sk_buff *skb = | |
1561 | __skb_dequeue(&ring->queue); | |
1562 | if (rtlpriv->use_new_trx_flow) | |
1563 | entry = (u8 *)(&ring->buffer_desc | |
1564 | [ring->idx]); | |
1565 | else | |
1566 | entry = (u8 *)(&ring->desc[ring->idx]); | |
0c817338 LF |
1567 | |
1568 | pci_unmap_single(rtlpci->pdev, | |
d3bb1429 | 1569 | rtlpriv->cfg->ops-> |
0c817338 LF |
1570 | get_desc((u8 *) |
1571 | entry, | |
1572 | true, | |
d3bb1429 | 1573 | HW_DESC_TXBUFF_ADDR), |
0c817338 | 1574 | skb->len, PCI_DMA_TODEVICE); |
cf968937 | 1575 | dev_kfree_skb_irq(skb); |
38506ece | 1576 | ring->idx = (ring->idx + 1) % ring->entries; |
0c817338 LF |
1577 | } |
1578 | ring->idx = 0; | |
1579 | } | |
1580 | } | |
38506ece | 1581 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); |
0c817338 | 1582 | |
0c817338 LF |
1583 | return 0; |
1584 | } | |
1585 | ||
c7cfe38e | 1586 | static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw, |
36323f81 | 1587 | struct ieee80211_sta *sta, |
c7cfe38e | 1588 | struct sk_buff *skb) |
0c817338 | 1589 | { |
c7cfe38e | 1590 | struct rtl_priv *rtlpriv = rtl_priv(hw); |
c7cfe38e C |
1591 | struct rtl_sta_info *sta_entry = NULL; |
1592 | u8 tid = rtl_get_tid(skb); | |
0f015453 | 1593 | __le16 fc = rtl_get_fc(skb); |
c7cfe38e C |
1594 | |
1595 | if (!sta) | |
1596 | return false; | |
1597 | sta_entry = (struct rtl_sta_info *)sta->drv_priv; | |
1598 | ||
1599 | if (!rtlpriv->rtlhal.earlymode_enable) | |
1600 | return false; | |
0f015453 LF |
1601 | if (ieee80211_is_nullfunc(fc)) |
1602 | return false; | |
1603 | if (ieee80211_is_qos_nullfunc(fc)) | |
1604 | return false; | |
1605 | if (ieee80211_is_pspoll(fc)) | |
1606 | return false; | |
c7cfe38e C |
1607 | if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL) |
1608 | return false; | |
1609 | if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE) | |
1610 | return false; | |
1611 | if (tid > 7) | |
1612 | return false; | |
1613 | ||
1614 | /* maybe every tid should be checked */ | |
1615 | if (!rtlpriv->link_info.higher_busytxtraffic[tid]) | |
1616 | return false; | |
1617 | ||
1618 | spin_lock_bh(&rtlpriv->locks.waitq_lock); | |
1619 | skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb); | |
1620 | spin_unlock_bh(&rtlpriv->locks.waitq_lock); | |
0c817338 | 1621 | |
c7cfe38e | 1622 | return true; |
0c817338 LF |
1623 | } |
1624 | ||
36323f81 TH |
1625 | static int rtl_pci_tx(struct ieee80211_hw *hw, |
1626 | struct ieee80211_sta *sta, | |
1627 | struct sk_buff *skb, | |
1628 | struct rtl_tcb_desc *ptcb_desc) | |
0c817338 LF |
1629 | { |
1630 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
c7cfe38e | 1631 | struct rtl_sta_info *sta_entry = NULL; |
0c817338 LF |
1632 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
1633 | struct rtl8192_tx_ring *ring; | |
1634 | struct rtl_tx_desc *pdesc; | |
f3355dd9 | 1635 | struct rtl_tx_buffer_desc *ptx_bd_desc = NULL; |
38506ece | 1636 | u16 idx; |
c7cfe38e | 1637 | u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb); |
0c817338 | 1638 | unsigned long flags; |
c7cfe38e C |
1639 | struct ieee80211_hdr *hdr = rtl_get_hdr(skb); |
1640 | __le16 fc = rtl_get_fc(skb); | |
0c817338 LF |
1641 | u8 *pda_addr = hdr->addr1; |
1642 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1643 | /*ssn */ | |
0c817338 LF |
1644 | u8 tid = 0; |
1645 | u16 seq_number = 0; | |
1646 | u8 own; | |
1647 | u8 temp_one = 1; | |
1648 | ||
0f015453 LF |
1649 | if (ieee80211_is_mgmt(fc)) |
1650 | rtl_tx_mgmt_proc(hw, skb); | |
c7cfe38e C |
1651 | |
1652 | if (rtlpriv->psc.sw_ps_enabled) { | |
1653 | if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) && | |
1654 | !ieee80211_has_pm(fc)) | |
1655 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); | |
1656 | } | |
0c817338 | 1657 | |
c7cfe38e | 1658 | rtl_action_proc(hw, skb, true); |
0c817338 LF |
1659 | |
1660 | if (is_multicast_ether_addr(pda_addr)) | |
1661 | rtlpriv->stats.txbytesmulticast += skb->len; | |
1662 | else if (is_broadcast_ether_addr(pda_addr)) | |
1663 | rtlpriv->stats.txbytesbroadcast += skb->len; | |
1664 | else | |
1665 | rtlpriv->stats.txbytesunicast += skb->len; | |
1666 | ||
1667 | spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags); | |
0c817338 | 1668 | ring = &rtlpci->tx_ring[hw_queue]; |
38506ece LF |
1669 | if (hw_queue != BEACON_QUEUE) { |
1670 | if (rtlpriv->use_new_trx_flow) | |
1671 | idx = ring->cur_tx_wp; | |
1672 | else | |
1673 | idx = (ring->idx + skb_queue_len(&ring->queue)) % | |
1674 | ring->entries; | |
1675 | } else { | |
0c817338 | 1676 | idx = 0; |
38506ece | 1677 | } |
0c817338 LF |
1678 | |
1679 | pdesc = &ring->desc[idx]; | |
f3355dd9 LF |
1680 | if (rtlpriv->use_new_trx_flow) { |
1681 | ptx_bd_desc = &ring->buffer_desc[idx]; | |
1682 | } else { | |
1683 | own = (u8) rtlpriv->cfg->ops->get_desc((u8 *)pdesc, | |
1684 | true, HW_DESC_OWN); | |
0c817338 | 1685 | |
f3355dd9 LF |
1686 | if ((own == 1) && (hw_queue != BEACON_QUEUE)) { |
1687 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
4f4378de | 1688 | "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", |
f3355dd9 LF |
1689 | hw_queue, ring->idx, idx, |
1690 | skb_queue_len(&ring->queue)); | |
0c817338 | 1691 | |
f3355dd9 LF |
1692 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, |
1693 | flags); | |
1694 | return skb->len; | |
1695 | } | |
0c817338 LF |
1696 | } |
1697 | ||
d0311314 TT |
1698 | if (rtlpriv->cfg->ops->get_available_desc && |
1699 | rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { | |
1700 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
1701 | "get_available_desc fail\n"); | |
1702 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, | |
1703 | flags); | |
1704 | return skb->len; | |
1705 | } | |
1706 | ||
0c817338 | 1707 | if (ieee80211_is_data_qos(fc)) { |
c7cfe38e C |
1708 | tid = rtl_get_tid(skb); |
1709 | if (sta) { | |
1710 | sta_entry = (struct rtl_sta_info *)sta->drv_priv; | |
1711 | seq_number = (le16_to_cpu(hdr->seq_ctrl) & | |
1712 | IEEE80211_SCTL_SEQ) >> 4; | |
1713 | seq_number += 1; | |
1714 | ||
1715 | if (!ieee80211_has_morefrags(hdr->frame_control)) | |
1716 | sta_entry->tids[tid].seq_number = seq_number; | |
1717 | } | |
0c817338 LF |
1718 | } |
1719 | ||
1720 | if (ieee80211_is_data(fc)) | |
1721 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX); | |
1722 | ||
c7cfe38e | 1723 | rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, |
f3355dd9 | 1724 | (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc); |
0c817338 LF |
1725 | |
1726 | __skb_queue_tail(&ring->queue, skb); | |
1727 | ||
f3355dd9 LF |
1728 | if (rtlpriv->use_new_trx_flow) { |
1729 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, | |
9cb76aa9 | 1730 | HW_DESC_OWN, &hw_queue); |
f3355dd9 LF |
1731 | } else { |
1732 | rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, | |
9cb76aa9 | 1733 | HW_DESC_OWN, &temp_one); |
f3355dd9 | 1734 | } |
0c817338 LF |
1735 | |
1736 | if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && | |
1737 | hw_queue != BEACON_QUEUE) { | |
0c817338 | 1738 | RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, |
4f4378de | 1739 | "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", |
f30d7507 JP |
1740 | hw_queue, ring->idx, idx, |
1741 | skb_queue_len(&ring->queue)); | |
0c817338 LF |
1742 | |
1743 | ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); | |
1744 | } | |
1745 | ||
1746 | spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); | |
1747 | ||
1748 | rtlpriv->cfg->ops->tx_polling(hw, hw_queue); | |
1749 | ||
1750 | return 0; | |
1751 | } | |
1752 | ||
38506ece | 1753 | static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop) |
c7cfe38e C |
1754 | { |
1755 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1756 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1757 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
26634c4b | 1758 | struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); |
c7cfe38e C |
1759 | u16 i = 0; |
1760 | int queue_id; | |
1761 | struct rtl8192_tx_ring *ring; | |
1762 | ||
26634c4b LF |
1763 | if (mac->skip_scan) |
1764 | return; | |
1765 | ||
c7cfe38e C |
1766 | for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) { |
1767 | u32 queue_len; | |
38506ece LF |
1768 | |
1769 | if (((queues >> queue_id) & 0x1) == 0) { | |
1770 | queue_id--; | |
1771 | continue; | |
1772 | } | |
c7cfe38e C |
1773 | ring = &pcipriv->dev.tx_ring[queue_id]; |
1774 | queue_len = skb_queue_len(&ring->queue); | |
1775 | if (queue_len == 0 || queue_id == BEACON_QUEUE || | |
1776 | queue_id == TXCMD_QUEUE) { | |
1777 | queue_id--; | |
1778 | continue; | |
1779 | } else { | |
1780 | msleep(20); | |
1781 | i++; | |
1782 | } | |
1783 | ||
1784 | /* we just wait 1s for all queues */ | |
1785 | if (rtlpriv->psc.rfpwr_state == ERFOFF || | |
1786 | is_hal_stop(rtlhal) || i >= 200) | |
1787 | return; | |
1788 | } | |
1789 | } | |
1790 | ||
d3bb1429 | 1791 | static void rtl_pci_deinit(struct ieee80211_hw *hw) |
0c817338 LF |
1792 | { |
1793 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1794 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1795 | ||
1796 | _rtl_pci_deinit_trx_ring(hw); | |
1797 | ||
1798 | synchronize_irq(rtlpci->pdev->irq); | |
1799 | tasklet_kill(&rtlpriv->works.irq_tasklet); | |
a269913c | 1800 | cancel_work_sync(&rtlpriv->works.lps_change_work); |
0c817338 LF |
1801 | |
1802 | flush_workqueue(rtlpriv->works.rtl_wq); | |
1803 | destroy_workqueue(rtlpriv->works.rtl_wq); | |
1804 | ||
1805 | } | |
1806 | ||
d3bb1429 | 1807 | static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) |
0c817338 LF |
1808 | { |
1809 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1810 | int err; | |
1811 | ||
1812 | _rtl_pci_init_struct(hw, pdev); | |
1813 | ||
1814 | err = _rtl_pci_init_trx_ring(hw); | |
1815 | if (err) { | |
1816 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 1817 | "tx ring initialization failed\n"); |
12325280 | 1818 | return err; |
0c817338 LF |
1819 | } |
1820 | ||
12325280 | 1821 | return 0; |
0c817338 LF |
1822 | } |
1823 | ||
d3bb1429 | 1824 | static int rtl_pci_start(struct ieee80211_hw *hw) |
0c817338 LF |
1825 | { |
1826 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1827 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1828 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1829 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
1830 | ||
1831 | int err; | |
1832 | ||
1833 | rtl_pci_reset_trx_ring(hw); | |
1834 | ||
1835 | rtlpci->driver_is_goingto_unload = false; | |
08054200 LF |
1836 | if (rtlpriv->cfg->ops->get_btc_status && |
1837 | rtlpriv->cfg->ops->get_btc_status()) { | |
38506ece LF |
1838 | rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv); |
1839 | rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv); | |
1840 | } | |
0c817338 LF |
1841 | err = rtlpriv->cfg->ops->hw_init(hw); |
1842 | if (err) { | |
1843 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 | 1844 | "Failed to config hardware!\n"); |
0c817338 LF |
1845 | return err; |
1846 | } | |
1847 | ||
1848 | rtlpriv->cfg->ops->enable_interrupt(hw); | |
f30d7507 | 1849 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); |
0c817338 LF |
1850 | |
1851 | rtl_init_rx_config(hw); | |
1852 | ||
fb914ebf | 1853 | /*should be after adapter start and interrupt enable. */ |
0c817338 LF |
1854 | set_hal_start(rtlhal); |
1855 | ||
1856 | RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC); | |
1857 | ||
1858 | rtlpci->up_first_time = false; | |
1859 | ||
38506ece | 1860 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "rtl_pci_start OK\n"); |
0c817338 LF |
1861 | return 0; |
1862 | } | |
1863 | ||
d3bb1429 | 1864 | static void rtl_pci_stop(struct ieee80211_hw *hw) |
0c817338 LF |
1865 | { |
1866 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1867 | struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); | |
1868 | struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); | |
1869 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1870 | unsigned long flags; | |
1871 | u8 RFInProgressTimeOut = 0; | |
1872 | ||
38506ece LF |
1873 | if (rtlpriv->cfg->ops->get_btc_status()) |
1874 | rtlpriv->btcoexist.btc_ops->btc_halt_notify(); | |
1875 | ||
0c817338 | 1876 | /* |
fb914ebf | 1877 | *should be before disable interrupt&adapter |
0c817338 LF |
1878 | *and will do it immediately. |
1879 | */ | |
1880 | set_hal_stop(rtlhal); | |
1881 | ||
9278db62 | 1882 | rtlpci->driver_is_goingto_unload = true; |
0c817338 | 1883 | rtlpriv->cfg->ops->disable_interrupt(hw); |
a269913c | 1884 | cancel_work_sync(&rtlpriv->works.lps_change_work); |
0c817338 LF |
1885 | |
1886 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); | |
1887 | while (ppsc->rfchange_inprogress) { | |
1888 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); | |
1889 | if (RFInProgressTimeOut > 100) { | |
1890 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); | |
1891 | break; | |
1892 | } | |
1893 | mdelay(1); | |
1894 | RFInProgressTimeOut++; | |
1895 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); | |
1896 | } | |
1897 | ppsc->rfchange_inprogress = true; | |
1898 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); | |
1899 | ||
0c817338 | 1900 | rtlpriv->cfg->ops->hw_disable(hw); |
b0302aba LF |
1901 | /* some things are not needed if firmware not available */ |
1902 | if (!rtlpriv->max_fw_size) | |
1903 | return; | |
0c817338 LF |
1904 | rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); |
1905 | ||
1906 | spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags); | |
1907 | ppsc->rfchange_inprogress = false; | |
1908 | spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags); | |
1909 | ||
1910 | rtl_pci_enable_aspm(hw); | |
1911 | } | |
1912 | ||
1913 | static bool _rtl_pci_find_adapter(struct pci_dev *pdev, | |
1914 | struct ieee80211_hw *hw) | |
1915 | { | |
1916 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
1917 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
1918 | struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); | |
1919 | struct pci_dev *bridge_pdev = pdev->bus->self; | |
1920 | u16 venderid; | |
1921 | u16 deviceid; | |
c7cfe38e | 1922 | u8 revisionid; |
0c817338 LF |
1923 | u16 irqline; |
1924 | u8 tmp; | |
1925 | ||
fc7707a4 | 1926 | pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; |
0c817338 LF |
1927 | venderid = pdev->vendor; |
1928 | deviceid = pdev->device; | |
c7cfe38e | 1929 | pci_read_config_byte(pdev, 0x8, &revisionid); |
0c817338 LF |
1930 | pci_read_config_word(pdev, 0x3C, &irqline); |
1931 | ||
fa7ccfb1 LF |
1932 | /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses |
1933 | * r8192e_pci, and RTL8192SE, which uses this driver. If the | |
1934 | * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then | |
1935 | * the correct driver is r8192e_pci, thus this routine should | |
1936 | * return false. | |
1937 | */ | |
1938 | if (deviceid == RTL_PCI_8192SE_DID && | |
1939 | revisionid == RTL_PCI_REVISION_ID_8192PCIE) | |
1940 | return false; | |
1941 | ||
0c817338 LF |
1942 | if (deviceid == RTL_PCI_8192_DID || |
1943 | deviceid == RTL_PCI_0044_DID || | |
1944 | deviceid == RTL_PCI_0047_DID || | |
1945 | deviceid == RTL_PCI_8192SE_DID || | |
1946 | deviceid == RTL_PCI_8174_DID || | |
1947 | deviceid == RTL_PCI_8173_DID || | |
1948 | deviceid == RTL_PCI_8172_DID || | |
1949 | deviceid == RTL_PCI_8171_DID) { | |
c7cfe38e | 1950 | switch (revisionid) { |
0c817338 LF |
1951 | case RTL_PCI_REVISION_ID_8192PCIE: |
1952 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1953 | "8192 PCI-E is found - vid/did=%x/%x\n", |
1954 | venderid, deviceid); | |
0c817338 | 1955 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; |
0f015453 | 1956 | return false; |
0c817338 LF |
1957 | case RTL_PCI_REVISION_ID_8192SE: |
1958 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1959 | "8192SE is found - vid/did=%x/%x\n", |
1960 | venderid, deviceid); | |
0c817338 LF |
1961 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; |
1962 | break; | |
1963 | default: | |
1964 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
1965 | "Err: Unknown device - vid/did=%x/%x\n", |
1966 | venderid, deviceid); | |
0c817338 LF |
1967 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; |
1968 | break; | |
1969 | ||
1970 | } | |
0f015453 LF |
1971 | } else if (deviceid == RTL_PCI_8723AE_DID) { |
1972 | rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; | |
1973 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
1974 | "8723AE PCI-E is found - " | |
1975 | "vid/did=%x/%x\n", venderid, deviceid); | |
0c817338 LF |
1976 | } else if (deviceid == RTL_PCI_8192CET_DID || |
1977 | deviceid == RTL_PCI_8192CE_DID || | |
1978 | deviceid == RTL_PCI_8191CE_DID || | |
1979 | deviceid == RTL_PCI_8188CE_DID) { | |
1980 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; | |
1981 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1982 | "8192C PCI-E is found - vid/did=%x/%x\n", |
1983 | venderid, deviceid); | |
c7cfe38e C |
1984 | } else if (deviceid == RTL_PCI_8192DE_DID || |
1985 | deviceid == RTL_PCI_8192DE_DID2) { | |
1986 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; | |
1987 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
1988 | "8192D PCI-E is found - vid/did=%x/%x\n", |
1989 | venderid, deviceid); | |
5c69177d LF |
1990 | } else if (deviceid == RTL_PCI_8188EE_DID) { |
1991 | rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; | |
1992 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
1993 | "Find adapter, Hardware type is 8188EE\n"); | |
38506ece LF |
1994 | } else if (deviceid == RTL_PCI_8723BE_DID) { |
1995 | rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; | |
1996 | RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, | |
1997 | "Find adapter, Hardware type is 8723BE\n"); | |
1998 | } else if (deviceid == RTL_PCI_8192EE_DID) { | |
1999 | rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; | |
2000 | RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, | |
2001 | "Find adapter, Hardware type is 8192EE\n"); | |
2002 | } else if (deviceid == RTL_PCI_8821AE_DID) { | |
2003 | rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; | |
2004 | RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, | |
2005 | "Find adapter, Hardware type is 8821AE\n"); | |
2006 | } else if (deviceid == RTL_PCI_8812AE_DID) { | |
2007 | rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; | |
2008 | RT_TRACE(rtlpriv, COMP_INIT , DBG_LOUD, | |
2009 | "Find adapter, Hardware type is 8812AE\n"); | |
0c817338 LF |
2010 | } else { |
2011 | RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, | |
f30d7507 JP |
2012 | "Err: Unknown device - vid/did=%x/%x\n", |
2013 | venderid, deviceid); | |
0c817338 LF |
2014 | |
2015 | rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; | |
2016 | } | |
2017 | ||
c7cfe38e C |
2018 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { |
2019 | if (revisionid == 0 || revisionid == 1) { | |
2020 | if (revisionid == 0) { | |
f30d7507 JP |
2021 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, |
2022 | "Find 92DE MAC0\n"); | |
c7cfe38e C |
2023 | rtlhal->interfaceindex = 0; |
2024 | } else if (revisionid == 1) { | |
2025 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 | 2026 | "Find 92DE MAC1\n"); |
c7cfe38e C |
2027 | rtlhal->interfaceindex = 1; |
2028 | } | |
2029 | } else { | |
2030 | RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, | |
f30d7507 JP |
2031 | "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", |
2032 | venderid, deviceid, revisionid); | |
c7cfe38e C |
2033 | rtlhal->interfaceindex = 0; |
2034 | } | |
2035 | } | |
38506ece LF |
2036 | |
2037 | /* 92ee use new trx flow */ | |
2038 | if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE) | |
2039 | rtlpriv->use_new_trx_flow = true; | |
2040 | else | |
2041 | rtlpriv->use_new_trx_flow = false; | |
2042 | ||
0c817338 LF |
2043 | /*find bus info */ |
2044 | pcipriv->ndis_adapter.busnumber = pdev->bus->number; | |
2045 | pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn); | |
2046 | pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn); | |
2047 | ||
38506ece LF |
2048 | /*find bridge info */ |
2049 | pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; | |
26634c4b LF |
2050 | /* some ARM have no bridge_pdev and will crash here |
2051 | * so we should check if bridge_pdev is NULL | |
2052 | */ | |
b6b67df3 LF |
2053 | if (bridge_pdev) { |
2054 | /*find bridge info if available */ | |
2055 | pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor; | |
2056 | for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { | |
2057 | if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { | |
2058 | pcipriv->ndis_adapter.pcibridge_vendor = tmp; | |
2059 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
2060 | "Pci Bridge Vendor is found index: %d\n", |
2061 | tmp); | |
b6b67df3 LF |
2062 | break; |
2063 | } | |
0c817338 LF |
2064 | } |
2065 | } | |
2066 | ||
2067 | if (pcipriv->ndis_adapter.pcibridge_vendor != | |
2068 | PCI_BRIDGE_VENDOR_UNKNOWN) { | |
2069 | pcipriv->ndis_adapter.pcibridge_busnum = | |
2070 | bridge_pdev->bus->number; | |
2071 | pcipriv->ndis_adapter.pcibridge_devnum = | |
2072 | PCI_SLOT(bridge_pdev->devfn); | |
2073 | pcipriv->ndis_adapter.pcibridge_funcnum = | |
2074 | PCI_FUNC(bridge_pdev->devfn); | |
c7cfe38e C |
2075 | pcipriv->ndis_adapter.pcibridge_pciehdr_offset = |
2076 | pci_pcie_cap(bridge_pdev); | |
0c817338 LF |
2077 | pcipriv->ndis_adapter.num4bytes = |
2078 | (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4; | |
2079 | ||
2080 | rtl_pci_get_linkcontrol_field(hw); | |
2081 | ||
2082 | if (pcipriv->ndis_adapter.pcibridge_vendor == | |
2083 | PCI_BRIDGE_VENDOR_AMD) { | |
2084 | pcipriv->ndis_adapter.amd_l1_patch = | |
2085 | rtl_pci_get_amd_l1_patch(hw); | |
2086 | } | |
2087 | } | |
2088 | ||
2089 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
2090 | "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", |
2091 | pcipriv->ndis_adapter.busnumber, | |
2092 | pcipriv->ndis_adapter.devnumber, | |
2093 | pcipriv->ndis_adapter.funcnumber, | |
2094 | pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); | |
0c817338 LF |
2095 | |
2096 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
2097 | "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", |
2098 | pcipriv->ndis_adapter.pcibridge_busnum, | |
2099 | pcipriv->ndis_adapter.pcibridge_devnum, | |
2100 | pcipriv->ndis_adapter.pcibridge_funcnum, | |
2101 | pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], | |
2102 | pcipriv->ndis_adapter.pcibridge_pciehdr_offset, | |
2103 | pcipriv->ndis_adapter.pcibridge_linkctrlreg, | |
2104 | pcipriv->ndis_adapter.amd_l1_patch); | |
0c817338 LF |
2105 | |
2106 | rtl_pci_parse_configuration(pdev, hw); | |
26634c4b | 2107 | list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); |
0c817338 LF |
2108 | |
2109 | return true; | |
2110 | } | |
2111 | ||
94010fa0 AL |
2112 | static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) |
2113 | { | |
2114 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2115 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
2116 | struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); | |
2117 | int ret; | |
2118 | ||
2119 | ret = pci_enable_msi(rtlpci->pdev); | |
2120 | if (ret < 0) | |
2121 | return ret; | |
2122 | ||
2123 | ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, | |
2124 | IRQF_SHARED, KBUILD_MODNAME, hw); | |
2125 | if (ret < 0) { | |
2126 | pci_disable_msi(rtlpci->pdev); | |
2127 | return ret; | |
2128 | } | |
2129 | ||
2130 | rtlpci->using_msi = true; | |
2131 | ||
2132 | RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, | |
2133 | "MSI Interrupt Mode!\n"); | |
2134 | return 0; | |
2135 | } | |
2136 | ||
2137 | static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) | |
2138 | { | |
2139 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2140 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
2141 | struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); | |
2142 | int ret; | |
2143 | ||
2144 | ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt, | |
2145 | IRQF_SHARED, KBUILD_MODNAME, hw); | |
2146 | if (ret < 0) | |
2147 | return ret; | |
2148 | ||
2149 | rtlpci->using_msi = false; | |
2150 | RT_TRACE(rtlpriv, COMP_INIT|COMP_INTR, DBG_DMESG, | |
2151 | "Pin-based Interrupt Mode!\n"); | |
2152 | return 0; | |
2153 | } | |
2154 | ||
2155 | static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw) | |
2156 | { | |
2157 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
2158 | struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); | |
2159 | int ret; | |
2160 | ||
2161 | if (rtlpci->msi_support) { | |
2162 | ret = rtl_pci_intr_mode_msi(hw); | |
2163 | if (ret < 0) | |
2164 | ret = rtl_pci_intr_mode_legacy(hw); | |
2165 | } else { | |
2166 | ret = rtl_pci_intr_mode_legacy(hw); | |
2167 | } | |
2168 | return ret; | |
2169 | } | |
2170 | ||
9e2ff36b | 2171 | int rtl_pci_probe(struct pci_dev *pdev, |
0c817338 LF |
2172 | const struct pci_device_id *id) |
2173 | { | |
2174 | struct ieee80211_hw *hw = NULL; | |
2175 | ||
2176 | struct rtl_priv *rtlpriv = NULL; | |
2177 | struct rtl_pci_priv *pcipriv = NULL; | |
2178 | struct rtl_pci *rtlpci; | |
2179 | unsigned long pmem_start, pmem_len, pmem_flags; | |
2180 | int err; | |
2181 | ||
2182 | err = pci_enable_device(pdev); | |
2183 | if (err) { | |
9d833ed7 JP |
2184 | RT_ASSERT(false, "%s : Cannot enable new PCI device\n", |
2185 | pci_name(pdev)); | |
0c817338 LF |
2186 | return err; |
2187 | } | |
2188 | ||
2189 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
2190 | if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { | |
9d833ed7 JP |
2191 | RT_ASSERT(false, |
2192 | "Unable to obtain 32bit DMA for consistent allocations\n"); | |
3d86b930 TG |
2193 | err = -ENOMEM; |
2194 | goto fail1; | |
0c817338 LF |
2195 | } |
2196 | } | |
2197 | ||
2198 | pci_set_master(pdev); | |
2199 | ||
2200 | hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) + | |
2201 | sizeof(struct rtl_priv), &rtl_ops); | |
2202 | if (!hw) { | |
2203 | RT_ASSERT(false, | |
9d833ed7 | 2204 | "%s : ieee80211 alloc failed\n", pci_name(pdev)); |
0c817338 LF |
2205 | err = -ENOMEM; |
2206 | goto fail1; | |
2207 | } | |
2208 | ||
2209 | SET_IEEE80211_DEV(hw, &pdev->dev); | |
2210 | pci_set_drvdata(pdev, hw); | |
2211 | ||
2212 | rtlpriv = hw->priv; | |
26634c4b | 2213 | rtlpriv->hw = hw; |
0c817338 LF |
2214 | pcipriv = (void *)rtlpriv->priv; |
2215 | pcipriv->dev.pdev = pdev; | |
b0302aba | 2216 | init_completion(&rtlpriv->firmware_loading_complete); |
38506ece LF |
2217 | /*proximity init here*/ |
2218 | rtlpriv->proximity.proxim_on = false; | |
2219 | ||
2220 | pcipriv = (void *)rtlpriv->priv; | |
2221 | pcipriv->dev.pdev = pdev; | |
0c817338 | 2222 | |
c7cfe38e C |
2223 | /* init cfg & intf_ops */ |
2224 | rtlpriv->rtlhal.interface = INTF_PCI; | |
2225 | rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data); | |
2226 | rtlpriv->intf_ops = &rtl_pci_ops; | |
6f334c2b | 2227 | rtlpriv->glb_var = &rtl_global_var; |
c7cfe38e | 2228 | |
0c817338 LF |
2229 | /* |
2230 | *init dbgp flags before all | |
2231 | *other functions, because we will | |
2232 | *use it in other funtions like | |
2233 | *RT_TRACE/RT_PRINT/RTL_PRINT_DATA | |
2234 | *you can not use these macro | |
2235 | *before this | |
2236 | */ | |
2237 | rtl_dbgp_flag_init(hw); | |
2238 | ||
2239 | /* MEM map */ | |
2240 | err = pci_request_regions(pdev, KBUILD_MODNAME); | |
2241 | if (err) { | |
9d833ed7 | 2242 | RT_ASSERT(false, "Can't obtain PCI resources\n"); |
3d86b930 | 2243 | goto fail1; |
0c817338 LF |
2244 | } |
2245 | ||
c7cfe38e C |
2246 | pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id); |
2247 | pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id); | |
2248 | pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id); | |
0c817338 LF |
2249 | |
2250 | /*shared mem start */ | |
2251 | rtlpriv->io.pci_mem_start = | |
c7cfe38e C |
2252 | (unsigned long)pci_iomap(pdev, |
2253 | rtlpriv->cfg->bar_id, pmem_len); | |
0c817338 | 2254 | if (rtlpriv->io.pci_mem_start == 0) { |
9d833ed7 | 2255 | RT_ASSERT(false, "Can't map PCI mem\n"); |
3d86b930 | 2256 | err = -ENOMEM; |
0c817338 LF |
2257 | goto fail2; |
2258 | } | |
2259 | ||
2260 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
2261 | "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", |
2262 | pmem_start, pmem_len, pmem_flags, | |
2263 | rtlpriv->io.pci_mem_start); | |
0c817338 LF |
2264 | |
2265 | /* Disable Clk Request */ | |
2266 | pci_write_config_byte(pdev, 0x81, 0); | |
2267 | /* leave D3 mode */ | |
2268 | pci_write_config_byte(pdev, 0x44, 0); | |
2269 | pci_write_config_byte(pdev, 0x04, 0x06); | |
2270 | pci_write_config_byte(pdev, 0x04, 0x07); | |
2271 | ||
0c817338 | 2272 | /* find adapter */ |
3d86b930 TG |
2273 | if (!_rtl_pci_find_adapter(pdev, hw)) { |
2274 | err = -ENODEV; | |
fa7ccfb1 | 2275 | goto fail3; |
3d86b930 | 2276 | } |
0c817338 LF |
2277 | |
2278 | /* Init IO handler */ | |
2279 | _rtl_pci_io_handler_init(&pdev->dev, hw); | |
2280 | ||
2281 | /*like read eeprom and so on */ | |
2282 | rtlpriv->cfg->ops->read_eeprom_info(hw); | |
2283 | ||
7d63a5f9 LF |
2284 | if (rtlpriv->cfg->ops->init_sw_vars(hw)) { |
2285 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n"); | |
2286 | err = -ENODEV; | |
2287 | goto fail3; | |
2288 | } | |
2289 | rtlpriv->cfg->ops->init_sw_leds(hw); | |
2290 | ||
2291 | /*aspm */ | |
2292 | rtl_pci_init_aspm(hw); | |
2293 | ||
0c817338 LF |
2294 | /* Init mac80211 sw */ |
2295 | err = rtl_init_core(hw); | |
2296 | if (err) { | |
2297 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 2298 | "Can't allocate sw for mac80211\n"); |
0c817338 LF |
2299 | goto fail3; |
2300 | } | |
2301 | ||
2302 | /* Init PCI sw */ | |
12325280 | 2303 | err = rtl_pci_init(hw, pdev); |
0c817338 | 2304 | if (err) { |
f30d7507 | 2305 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n"); |
0c817338 LF |
2306 | goto fail3; |
2307 | } | |
2308 | ||
38506ece LF |
2309 | err = ieee80211_register_hw(hw); |
2310 | if (err) { | |
2311 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
2312 | "Can't register mac80211 hw.\n"); | |
574e02ab LF |
2313 | err = -ENODEV; |
2314 | goto fail3; | |
2315 | } | |
38506ece | 2316 | rtlpriv->mac80211.mac80211_registered = 1; |
574e02ab | 2317 | |
0c817338 LF |
2318 | err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group); |
2319 | if (err) { | |
2320 | RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, | |
f30d7507 | 2321 | "failed to create sysfs device attributes\n"); |
0c817338 LF |
2322 | goto fail3; |
2323 | } | |
2324 | ||
38506ece LF |
2325 | /*init rfkill */ |
2326 | rtl_init_rfkill(hw); /* Init PCI sw */ | |
2327 | ||
0c817338 | 2328 | rtlpci = rtl_pcidev(pcipriv); |
94010fa0 | 2329 | err = rtl_pci_intr_mode_decide(hw); |
0c817338 LF |
2330 | if (err) { |
2331 | RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, | |
f30d7507 JP |
2332 | "%s: failed to register IRQ handler\n", |
2333 | wiphy_name(hw->wiphy)); | |
0c817338 | 2334 | goto fail3; |
0c817338 | 2335 | } |
b0302aba | 2336 | rtlpci->irq_alloc = 1; |
0c817338 | 2337 | |
38506ece | 2338 | set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); |
0c817338 LF |
2339 | return 0; |
2340 | ||
2341 | fail3: | |
38506ece | 2342 | pci_set_drvdata(pdev, NULL); |
0c817338 | 2343 | rtl_deinit_core(hw); |
0c817338 LF |
2344 | |
2345 | if (rtlpriv->io.pci_mem_start != 0) | |
62e63975 | 2346 | pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); |
0c817338 LF |
2347 | |
2348 | fail2: | |
2349 | pci_release_regions(pdev); | |
b0302aba | 2350 | complete(&rtlpriv->firmware_loading_complete); |
0c817338 LF |
2351 | |
2352 | fail1: | |
3d86b930 TG |
2353 | if (hw) |
2354 | ieee80211_free_hw(hw); | |
0c817338 LF |
2355 | pci_disable_device(pdev); |
2356 | ||
3d86b930 | 2357 | return err; |
0c817338 LF |
2358 | |
2359 | } | |
2360 | EXPORT_SYMBOL(rtl_pci_probe); | |
2361 | ||
2362 | void rtl_pci_disconnect(struct pci_dev *pdev) | |
2363 | { | |
2364 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
2365 | struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw); | |
2366 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2367 | struct rtl_pci *rtlpci = rtl_pcidev(pcipriv); | |
2368 | struct rtl_mac *rtlmac = rtl_mac(rtlpriv); | |
2369 | ||
b0302aba LF |
2370 | /* just in case driver is removed before firmware callback */ |
2371 | wait_for_completion(&rtlpriv->firmware_loading_complete); | |
0c817338 LF |
2372 | clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status); |
2373 | ||
2374 | sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group); | |
2375 | ||
2376 | /*ieee80211_unregister_hw will call ops_stop */ | |
2377 | if (rtlmac->mac80211_registered == 1) { | |
2378 | ieee80211_unregister_hw(hw); | |
2379 | rtlmac->mac80211_registered = 0; | |
2380 | } else { | |
2381 | rtl_deinit_deferred_work(hw); | |
2382 | rtlpriv->intf_ops->adapter_stop(hw); | |
2383 | } | |
44eb65cf | 2384 | rtlpriv->cfg->ops->disable_interrupt(hw); |
0c817338 LF |
2385 | |
2386 | /*deinit rfkill */ | |
2387 | rtl_deinit_rfkill(hw); | |
2388 | ||
2389 | rtl_pci_deinit(hw); | |
2390 | rtl_deinit_core(hw); | |
0c817338 LF |
2391 | rtlpriv->cfg->ops->deinit_sw_vars(hw); |
2392 | ||
2393 | if (rtlpci->irq_alloc) { | |
2394 | free_irq(rtlpci->pdev->irq, hw); | |
2395 | rtlpci->irq_alloc = 0; | |
2396 | } | |
2397 | ||
94010fa0 AL |
2398 | if (rtlpci->using_msi) |
2399 | pci_disable_msi(rtlpci->pdev); | |
2400 | ||
26634c4b | 2401 | list_del(&rtlpriv->list); |
0c817338 | 2402 | if (rtlpriv->io.pci_mem_start != 0) { |
62e63975 | 2403 | pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start); |
0c817338 LF |
2404 | pci_release_regions(pdev); |
2405 | } | |
2406 | ||
2407 | pci_disable_device(pdev); | |
c7cfe38e C |
2408 | |
2409 | rtl_pci_disable_aspm(hw); | |
2410 | ||
38506ece LF |
2411 | pci_set_drvdata(pdev, NULL); |
2412 | ||
0c817338 LF |
2413 | ieee80211_free_hw(hw); |
2414 | } | |
2415 | EXPORT_SYMBOL(rtl_pci_disconnect); | |
2416 | ||
244a77e9 | 2417 | #ifdef CONFIG_PM_SLEEP |
0c817338 LF |
2418 | /*************************************** |
2419 | kernel pci power state define: | |
2420 | PCI_D0 ((pci_power_t __force) 0) | |
2421 | PCI_D1 ((pci_power_t __force) 1) | |
2422 | PCI_D2 ((pci_power_t __force) 2) | |
2423 | PCI_D3hot ((pci_power_t __force) 3) | |
2424 | PCI_D3cold ((pci_power_t __force) 4) | |
2425 | PCI_UNKNOWN ((pci_power_t __force) 5) | |
2426 | ||
2427 | This function is called when system | |
2428 | goes into suspend state mac80211 will | |
2429 | call rtl_mac_stop() from the mac80211 | |
2430 | suspend function first, So there is | |
2431 | no need to call hw_disable here. | |
2432 | ****************************************/ | |
603be388 | 2433 | int rtl_pci_suspend(struct device *dev) |
0c817338 | 2434 | { |
603be388 | 2435 | struct pci_dev *pdev = to_pci_dev(dev); |
c7cfe38e C |
2436 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
2437 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
2438 | ||
2439 | rtlpriv->cfg->ops->hw_suspend(hw); | |
2440 | rtl_deinit_rfkill(hw); | |
2441 | ||
0c817338 LF |
2442 | return 0; |
2443 | } | |
2444 | EXPORT_SYMBOL(rtl_pci_suspend); | |
2445 | ||
603be388 | 2446 | int rtl_pci_resume(struct device *dev) |
0c817338 | 2447 | { |
603be388 | 2448 | struct pci_dev *pdev = to_pci_dev(dev); |
c7cfe38e C |
2449 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
2450 | struct rtl_priv *rtlpriv = rtl_priv(hw); | |
0c817338 | 2451 | |
c7cfe38e C |
2452 | rtlpriv->cfg->ops->hw_resume(hw); |
2453 | rtl_init_rfkill(hw); | |
0c817338 LF |
2454 | return 0; |
2455 | } | |
2456 | EXPORT_SYMBOL(rtl_pci_resume); | |
244a77e9 | 2457 | #endif /* CONFIG_PM_SLEEP */ |
0c817338 | 2458 | |
1bfcfdcc | 2459 | const struct rtl_intf_ops rtl_pci_ops = { |
c7cfe38e | 2460 | .read_efuse_byte = read_efuse_byte, |
0c817338 LF |
2461 | .adapter_start = rtl_pci_start, |
2462 | .adapter_stop = rtl_pci_stop, | |
26634c4b | 2463 | .check_buddy_priv = rtl_pci_check_buddy_priv, |
0c817338 | 2464 | .adapter_tx = rtl_pci_tx, |
c7cfe38e | 2465 | .flush = rtl_pci_flush, |
0c817338 | 2466 | .reset_trx_ring = rtl_pci_reset_trx_ring, |
c7cfe38e | 2467 | .waitq_insert = rtl_pci_tx_chk_waitq_insert, |
0c817338 LF |
2468 | |
2469 | .disable_aspm = rtl_pci_disable_aspm, | |
2470 | .enable_aspm = rtl_pci_enable_aspm, | |
2471 | }; |