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1 | /****************************************************************************** |
2 | * | |
3 | * Copyright(c) 2009-2012 Realtek Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of version 2 of the GNU General Public License as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * The full GNU General Public License is included in this distribution in the | |
15 | * file called LICENSE. | |
16 | * | |
17 | * Contact Information: | |
18 | * wlanfae <wlanfae@realtek.com> | |
19 | * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, | |
20 | * Hsinchu 300, Taiwan. | |
21 | * | |
22 | * Larry Finger <Larry.Finger@lwfinger.net> | |
23 | * | |
24 | *****************************************************************************/ | |
25 | ||
26 | #ifndef __RTL8723E_PWRSEQCMD_H__ | |
27 | #define __RTL8723E_PWRSEQCMD_H__ | |
28 | ||
29 | #include "wifi.h" | |
30 | /*--------------------------------------------- | |
31 | * 3 The value of cmd: 4 bits | |
32 | *--------------------------------------------- | |
33 | */ | |
34 | #define PWR_CMD_READ 0x00 | |
35 | #define PWR_CMD_WRITE 0x01 | |
36 | #define PWR_CMD_POLLING 0x02 | |
37 | #define PWR_CMD_DELAY 0x03 | |
38 | #define PWR_CMD_END 0x04 | |
39 | ||
40 | /* define the base address of each block */ | |
41 | #define PWR_BASEADDR_MAC 0x00 | |
42 | #define PWR_BASEADDR_USB 0x01 | |
43 | #define PWR_BASEADDR_PCIE 0x02 | |
44 | #define PWR_BASEADDR_SDIO 0x03 | |
45 | ||
46 | #define PWR_INTF_SDIO_MSK BIT(0) | |
47 | #define PWR_INTF_USB_MSK BIT(1) | |
48 | #define PWR_INTF_PCI_MSK BIT(2) | |
49 | #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) | |
50 | ||
51 | #define PWR_FAB_TSMC_MSK BIT(0) | |
52 | #define PWR_FAB_UMC_MSK BIT(1) | |
53 | #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) | |
54 | ||
55 | #define PWR_CUT_TESTCHIP_MSK BIT(0) | |
56 | #define PWR_CUT_A_MSK BIT(1) | |
57 | #define PWR_CUT_B_MSK BIT(2) | |
58 | #define PWR_CUT_C_MSK BIT(3) | |
59 | #define PWR_CUT_D_MSK BIT(4) | |
60 | #define PWR_CUT_E_MSK BIT(5) | |
61 | #define PWR_CUT_F_MSK BIT(6) | |
62 | #define PWR_CUT_G_MSK BIT(7) | |
63 | #define PWR_CUT_ALL_MSK 0xFF | |
64 | ||
65 | enum pwrseq_delay_unit { | |
66 | PWRSEQ_DELAY_US, | |
67 | PWRSEQ_DELAY_MS, | |
68 | }; | |
69 | ||
70 | struct wlan_pwr_cfg { | |
71 | u16 offset; | |
72 | u8 cut_msk; | |
73 | u8 fab_msk:4; | |
74 | u8 interface_msk:4; | |
75 | u8 base:4; | |
76 | u8 cmd:4; | |
77 | u8 msk; | |
78 | u8 value; | |
79 | }; | |
80 | ||
81 | #define GET_PWR_CFG_OFFSET(__PWR_CMD) (__PWR_CMD.offset) | |
82 | #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) (__PWR_CMD.cut_msk) | |
83 | #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) (__PWR_CMD.fab_msk) | |
84 | #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) (__PWR_CMD.interface_msk) | |
85 | #define GET_PWR_CFG_BASE(__PWR_CMD) (__PWR_CMD.base) | |
86 | #define GET_PWR_CFG_CMD(__PWR_CMD) (__PWR_CMD.cmd) | |
87 | #define GET_PWR_CFG_MASK(__PWR_CMD) (__PWR_CMD.msk) | |
88 | #define GET_PWR_CFG_VALUE(__PWR_CMD) (__PWR_CMD.value) | |
89 | ||
90 | bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, | |
91 | u8 fab_version, u8 interface_type, | |
92 | struct wlan_pwr_cfg pwrcfgcmd[]); | |
93 | ||
94 | #endif |