[deliverable/linux.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192ce / phy.h

/******************************************************************************
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#ifndef __RTL92C_PHY_H__
#define __RTL92C_PHY_H__

#define MAX_PRECMD_CNT			16
#define MAX_RFDEPENDCMD_CNT		16
#define MAX_POSTCMD_CNT			16

#define MAX_DOZE_WAITING_TIMES_9x	64

#define RT_CANNOT_IO(hw)		false
#define HIGHPOWER_RADIOA_ARRAYLEN	22

#define MAX_TOLERANCE			5

#define	APK_BB_REG_NUM			5
#define	APK_AFE_REG_NUM			16
#define	APK_CURVE_REG_NUM		4
#define	PATH_NUM			2

#define LOOP_LIMIT			5
#define MAX_STALL_TIME			50
#define AntennaDiversityValue		0x80
#define MAX_TXPWR_IDX_NMODE_92S		63
#define Reset_Cnt_Limit			3

#define IQK_ADDA_REG_NUM		16
#define IQK_MAC_REG_NUM			4

#define IQK_DELAY_TIME			1

#define RF90_PATH_MAX			2

#define CT_OFFSET_MAC_ADDR		0X16

#define CT_OFFSET_CCK_TX_PWR_IDX	0x5A
#define CT_OFFSET_HT401S_TX_PWR_IDX	0x60
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF	0x66
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF	0x69
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF	0x6C

#define CT_OFFSET_HT40_MAX_PWR_OFFSET	0x6F
#define CT_OFFSET_HT20_MAX_PWR_OFFSET	0x72

#define CT_OFFSET_CHANNEL_PLAH		0x75
#define CT_OFFSET_THERMAL_METER		0x78
#define CT_OFFSET_RF_OPTION		0x79
#define CT_OFFSET_VERSION		0x7E
#define CT_OFFSET_CUSTOMER_ID		0x7F

#define RTL92C_MAX_PATH_NUM		2

bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
			   u32 data);
u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
			    u32 regaddr, u32 bitmask);
void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
			    u32 regaddr, u32 bitmask, u32 data);
bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw);
bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
					  enum radio_path rfpath);
void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel);
void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
					  long power_indbm);
void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
			    enum nl80211_channel_type ch_type);
void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval);
void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
					  enum radio_path rfpath);
bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
				       u32 rfpath);
bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
				    enum rf_pwrstate rfpwr_state);
void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
void rtl92c_phy_set_io(struct ieee80211_hw *hw);
void rtl92c_bb_block_on(struct ieee80211_hw *hw);
u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw, enum radio_path rfpath,
			       u32 offset);
u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
				  enum radio_path rfpath, u32 offset);
u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
				 enum radio_path rfpath, u32 offset, u32 data);
void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
				    enum radio_path rfpath, u32 offset,
				    u32 data);
void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
					    u32 regaddr, u32 bitmask, u32 data);
bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
				   enum rf_pwrstate rfpwr_state);
bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
					    u8 configtype);
bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
					      u8 configtype);
void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw);

#endif
Commit	Line	Data
0c817338 LF	1	/******************************************************************************
0c817338 LF	2	*
9003a4ab	3	* Copyright(c) 2009-2012 Realtek Corporation.
0c817338 LF	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*
	28	*****************************************************************************/
	29
	30	#ifndef __RTL92C_PHY_H__
	31	#define __RTL92C_PHY_H__
	32
	33	#define MAX_PRECMD_CNT 16
	34	#define MAX_RFDEPENDCMD_CNT 16
	35	#define MAX_POSTCMD_CNT 16
	36
	37	#define MAX_DOZE_WAITING_TIMES_9x 64
	38
	39	#define RT_CANNOT_IO(hw) false
	40	#define HIGHPOWER_RADIOA_ARRAYLEN 22
	41
	42	#define MAX_TOLERANCE 5
0c817338 LF	43
	44	#define APK_BB_REG_NUM 5
	45	#define APK_AFE_REG_NUM 16
	46	#define APK_CURVE_REG_NUM 4
	47	#define PATH_NUM 2
	48
	49	#define LOOP_LIMIT 5
	50	#define MAX_STALL_TIME 50
	51	#define AntennaDiversityValue 0x80
	52	#define MAX_TXPWR_IDX_NMODE_92S 63
	53	#define Reset_Cnt_Limit 3
	54
	55	#define IQK_ADDA_REG_NUM 16
	56	#define IQK_MAC_REG_NUM 4
	57
e0b5a507 C	58	#define IQK_DELAY_TIME 1
e0b5a507 C	59
0c817338	60	#define RF90_PATH_MAX 2
0c817338 LF	61
	62	#define CT_OFFSET_MAC_ADDR 0X16
	63
	64	#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
	65	#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
	66	#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
	67	#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
	68	#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
	69
	70	#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
	71	#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
	72
	73	#define CT_OFFSET_CHANNEL_PLAH 0x75
	74	#define CT_OFFSET_THERMAL_METER 0x78
	75	#define CT_OFFSET_RF_OPTION 0x79
	76	#define CT_OFFSET_VERSION 0x7E
	77	#define CT_OFFSET_CUSTOMER_ID 0x7F
	78
	79	#define RTL92C_MAX_PATH_NUM 2
e0b5a507	80
e0b5a507	81	bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
a958df5d JP	82	u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
	83	void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
	84	u32 data);
	85	u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
	86	u32 regaddr, u32 bitmask);
	87	void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
	88	u32 regaddr, u32 bitmask, u32 data);
e0b5a507	89	bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
1472d3a8	90	bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw);
e0b5a507 C	91	bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
e0b5a507 C	92	bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
a958df5d	93	enum radio_path rfpath);
e0b5a507	94	void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
a958df5d	95	void rtl92c_phy_get_txpower_level(struct ieee80211_hw hw, long powerlevel);
e0b5a507 C	96	void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
e0b5a507 C	97	bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
0c817338	98	long power_indbm);
e0b5a507	99	void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
a958df5d	100	enum nl80211_channel_type ch_type);
e0b5a507 C	101	void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
	102	u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
	103	void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
a958df5d	104	void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval);
0c817338 LF	105	void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
0c817338 LF	106	void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
e0b5a507	107	void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
0c817338 LF	108	void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
	109	bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
	110	enum radio_path rfpath);
e0b5a507	111	bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
7009deab	112	u32 rfpath);
1472d3a8	113	bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
a958df5d	114	enum rf_pwrstate rfpwr_state);
0c817338 LF	115	void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
	116	bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
	117	void rtl92c_phy_set_io(struct ieee80211_hw *hw);
7ea47240	118	void rtl92c_bb_block_on(struct ieee80211_hw *hw);
a958df5d JP	119	u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw, enum radio_path rfpath,
a958df5d JP	120	u32 offset);
1472d3a8	121	u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
a958df5d	122	enum radio_path rfpath, u32 offset);
1472d3a8 LF	123	u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
1472d3a8 LF	124	void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
a958df5d	125	enum radio_path rfpath, u32 offset, u32 data);
1472d3a8	126	void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
a958df5d JP	127	enum radio_path rfpath, u32 offset,
a958df5d JP	128	u32 data);
1472d3a8	129	void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
a958df5d	130	u32 regaddr, u32 bitmask, u32 data);
1472d3a8 LF	131	bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
	132	void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
	133	bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
	134	void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
e0b5a507 C	135	bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
e0b5a507 C	136	enum rf_pwrstate rfpwr_state);
d3bb1429 LF	137	bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
	138	u8 configtype);
	139	bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
	140	u8 configtype);
099fb8ab	141	void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
0c817338 LF	142
0c817338 LF	143	#endif