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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...
[deliverable/linux.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192cu / phy.c
CommitLineData
f0a39ae7
G		 1/******************************************************************************
2 *
c1d6604d 3 * Copyright(c) 2009-2012 Realtek Corporation.
f0a39ae7
G		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
25b13dbc 33#include "../core.h"
f0a39ae7
G		 34#include "reg.h"
35#include "def.h"
36#include "phy.h"
9f087a92 37#include "../rtl8192c/phy_common.h"
f0a39ae7
G		 38#include "rf.h"
39#include "dm.h"
9f087a92
LF		 40#include "../rtl8192c/dm_common.h"
41#include "../rtl8192c/fw_common.h"
f0a39ae7
G		 42#include "table.h"
43
1472d3a8 44u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
d3bb1429 45 enum radio_path rfpath, u32 regaddr, u32 bitmask)
f0a39ae7
G		 46{
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 u32 original_value, readback_value, bitshift;
49 struct rtl_phy *rtlphy = &(rtlpriv->phy);
50
f30d7507
JP		 51 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
52 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
53 regaddr, rfpath, bitmask);
f0a39ae7
G		 54 if (rtlphy->rf_mode != RF_OP_BY_FW) {
55 original_value = _rtl92c_phy_rf_serial_read(hw,
56 rfpath, regaddr);
57 } else {
58 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
59 rfpath, regaddr);
60 }
61 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
62 readback_value = (original_value & bitmask) >> bitshift;
63 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507
JP		 64 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
65 regaddr, rfpath, bitmask, original_value);
f0a39ae7
G		 66 return readback_value;
67}
68
1472d3a8 69void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
d3bb1429
LF		 70 enum radio_path rfpath,
71 u32 regaddr, u32 bitmask, u32 data)
f0a39ae7
G		 72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_phy *rtlphy = &(rtlpriv->phy);
75 u32 original_value, bitshift;
76
77 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
f30d7507
JP		 78 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
79 regaddr, bitmask, data, rfpath);
f0a39ae7
G		 80 if (rtlphy->rf_mode != RF_OP_BY_FW) {
81 if (bitmask != RFREG_OFFSET_MASK) {
82 original_value = _rtl92c_phy_rf_serial_read(hw,
83 rfpath,
84 regaddr);
85 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
86 data =
87 ((original_value & (~bitmask)) |
88 (data << bitshift));
89 }
90 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
91 } else {
92 if (bitmask != RFREG_OFFSET_MASK) {
93 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
94 rfpath,
95 regaddr);
96 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
97 data =
98 ((original_value & (~bitmask)) |
99 (data << bitshift));
100 }
101 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
102 }
f30d7507
JP		 103 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
104 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
105 regaddr, bitmask, data, rfpath);
f0a39ae7
G		 106}
107
1472d3a8 108bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw)
f0a39ae7
G		 109{
110 bool rtstatus;
f0a39ae7 111
1472d3a8 112 rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw);
f0a39ae7
G		 113 return rtstatus;
114}
115
1472d3a8 116bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
f0a39ae7
G		 117{
118 bool rtstatus = true;
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
f0a39ae7 120 u16 regval;
8a719208 121 u32 regval32;
f0a39ae7
G		 122 u8 b_reg_hwparafile = 1;
123
124 _rtl92c_phy_init_bb_rf_register_definition(hw);
125 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
126 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
127 BIT(0) | BIT(1));
128 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
129 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
130 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
f5372e94
TY		 131 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
132 FEN_BB_GLB_RSTn | FEN_BBRSTB);
8a719208
MCA		 133 regval32 = rtl_read_dword(rtlpriv, 0x87c);
134 rtl_write_dword(rtlpriv, 0x87c, regval32 & (~BIT(31)));
f5372e94 135 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
f0a39ae7
G		 136 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
137 if (b_reg_hwparafile == 1)
138 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
139 return rtstatus;
140}
141
1472d3a8 142bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
f0a39ae7
G		 143{
144 struct rtl_priv *rtlpriv = rtl_priv(hw);
145 struct rtl_phy *rtlphy = &(rtlpriv->phy);
146 u32 i;
147 u32 arraylength;
148 u32 *ptrarray;
149
f30d7507 150 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
f0a39ae7
G		 151 arraylength = rtlphy->hwparam_tables[MAC_REG].length ;
152 ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
8657f9c4 153 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CUMAC_2T_ARRAY\n");
f0a39ae7
G		 154 for (i = 0; i < arraylength; i = i + 2)
155 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
156 return true;
157}
158
1472d3a8 159bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
d3bb1429 160 u8 configtype)
f0a39ae7
G		 161{
162 int i;
163 u32 *phy_regarray_table;
164 u32 *agctab_array_table;
165 u16 phy_reg_arraylen, agctab_arraylen;
166 struct rtl_priv *rtlpriv = rtl_priv(hw);
167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
168 struct rtl_phy *rtlphy = &(rtlpriv->phy);
169
170 if (IS_92C_SERIAL(rtlhal->version)) {
171 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
172 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_2T].pdata;
173 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
174 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
175 } else {
176 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
177 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_1T].pdata;
178 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
179 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
180 }
181 if (configtype == BASEBAND_CONFIG_PHY_REG) {
182 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
25b13dbc 183 rtl_addr_delay(phy_regarray_table[i]);
f0a39ae7
G		 184 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
185 phy_regarray_table[i + 1]);
186 udelay(1);
187 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507
JP		 188 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
189 phy_regarray_table[i],
190 phy_regarray_table[i + 1]);
f0a39ae7 191 }
f0a39ae7
G		 192 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
193 for (i = 0; i < agctab_arraylen; i = i + 2) {
194 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
195 agctab_array_table[i + 1]);
196 udelay(1);
197 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
f30d7507
JP		 198 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
199 agctab_array_table[i],
200 agctab_array_table[i + 1]);
f0a39ae7
G		 201 }
202 }
203 return true;
204}
205
1472d3a8 206bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
d3bb1429 207 u8 configtype)
f0a39ae7
G		 208{
209 struct rtl_priv *rtlpriv = rtl_priv(hw);
210 struct rtl_phy *rtlphy = &(rtlpriv->phy);
211 int i;
212 u32 *phy_regarray_table_pg;
213 u16 phy_regarray_pg_len;
214
215 rtlphy->pwrgroup_cnt = 0;
216 phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
217 phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
218 if (configtype == BASEBAND_CONFIG_PHY_REG) {
219 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
25b13dbc 220 rtl_addr_delay(phy_regarray_table_pg[i]);
f0a39ae7
G		 221 _rtl92c_store_pwrIndex_diffrate_offset(hw,
222 phy_regarray_table_pg[i],
223 phy_regarray_table_pg[i + 1],
224 phy_regarray_table_pg[i + 2]);
225 }
226 } else {
227 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
f30d7507 228 "configtype != BaseBand_Config_PHY_REG\n");
f0a39ae7
G		 229 }
230 return true;
231}
232
1472d3a8 233bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
f0a39ae7
G		 234 enum radio_path rfpath)
235{
236 int i;
237 u32 *radioa_array_table;
238 u32 *radiob_array_table;
239 u16 radioa_arraylen, radiob_arraylen;
240 struct rtl_priv *rtlpriv = rtl_priv(hw);
241 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
242 struct rtl_phy *rtlphy = &(rtlpriv->phy);
243
244 if (IS_92C_SERIAL(rtlhal->version)) {
245 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
246 radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
247 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
248 radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
249 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
8657f9c4 250 "Radio_A:RTL8192CURADIOA_2TARRAY\n");
f0a39ae7 251 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
8657f9c4 252 "Radio_B:RTL8192CU_RADIOB_2TARRAY\n");
f0a39ae7
G		 253 } else {
254 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
255 radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
256 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
257 radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
258 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
8657f9c4 259 "Radio_A:RTL8192CU_RADIOA_1TARRAY\n");
f0a39ae7 260 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
8657f9c4 261 "Radio_B:RTL8192CU_RADIOB_1TARRAY\n");
f0a39ae7 262 }
f30d7507 263 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
f0a39ae7
G		 264 switch (rfpath) {
265 case RF90_PATH_A:
266 for (i = 0; i < radioa_arraylen; i = i + 2) {
25b13dbc
LF		 267 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
268 RFREG_OFFSET_MASK,
269 radioa_array_table[i + 1]);
f0a39ae7 270 }
f0a39ae7
G		 271 break;
272 case RF90_PATH_B:
273 for (i = 0; i < radiob_arraylen; i = i + 2) {
25b13dbc
LF		 274 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
275 RFREG_OFFSET_MASK,
276 radiob_array_table[i + 1]);
f0a39ae7
G		 277 }
278 break;
279 case RF90_PATH_C:
280 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 281 "switch case not processed\n");
f0a39ae7
G		 282 break;
283 case RF90_PATH_D:
284 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 285 "switch case not processed\n");
f0a39ae7 286 break;
25b13dbc
LF		 287 default:
288 break;
f0a39ae7
G		 289 }
290 return true;
291}
292
1472d3a8 293void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
f0a39ae7
G		 294{
295 struct rtl_priv *rtlpriv = rtl_priv(hw);
296 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
297 struct rtl_phy *rtlphy = &(rtlpriv->phy);
298 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
299 u8 reg_bw_opmode;
300 u8 reg_prsr_rsc;
301
f30d7507
JP		 302 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
303 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
304 "20MHz" : "40MHz");
f0a39ae7
G		 305 if (is_hal_stop(rtlhal)) {
306 rtlphy->set_bwmode_inprogress = false;
307 return;
308 }
309 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
310 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
311 switch (rtlphy->current_chan_bw) {
312 case HT_CHANNEL_WIDTH_20:
313 reg_bw_opmode |= BW_OPMODE_20MHZ;
314 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
315 break;
316 case HT_CHANNEL_WIDTH_20_40:
317 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
318 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
319 reg_prsr_rsc =
320 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
321 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
322 break;
323 default:
324 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 325 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
f0a39ae7
G		 326 break;
327 }
328 switch (rtlphy->current_chan_bw) {
329 case HT_CHANNEL_WIDTH_20:
330 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
331 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
332 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
333 break;
334 case HT_CHANNEL_WIDTH_20_40:
335 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
336 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
337 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
338 (mac->cur_40_prime_sc >> 1));
339 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
340 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
341 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
342 (mac->cur_40_prime_sc ==
343 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
344 break;
345 default:
346 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 347 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
f0a39ae7
G		 348 break;
349 }
1472d3a8 350 rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
f0a39ae7 351 rtlphy->set_bwmode_inprogress = false;
f30d7507 352 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
f0a39ae7
G		 353}
354
1472d3a8 355void rtl92cu_bb_block_on(struct ieee80211_hw *hw)
f0a39ae7
G		 356{
357 struct rtl_priv *rtlpriv = rtl_priv(hw);
358
359 mutex_lock(&rtlpriv->io.bb_mutex);
360 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
361 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
362 mutex_unlock(&rtlpriv->io.bb_mutex);
363}
364
1472d3a8 365void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
f0a39ae7
G		 366{
367 u8 tmpreg;
368 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
369 struct rtl_priv *rtlpriv = rtl_priv(hw);
370
371 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
372
373 if ((tmpreg & 0x70) != 0)
374 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
375 else
376 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
377
378 if ((tmpreg & 0x70) != 0) {
379 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
380 if (is2t)
381 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
382 MASK12BITS);
383 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
384 (rf_a_mode & 0x8FFFF) | 0x10000);
385 if (is2t)
386 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
387 (rf_b_mode & 0x8FFFF) | 0x10000);
388 }
389 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
390 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
391 mdelay(100);
392 if ((tmpreg & 0x70) != 0) {
393 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
394 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
395 if (is2t)
396 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
397 rf_b_mode);
398 } else {
399 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
400 }
401}
402
d3bb1429 403static bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
f0a39ae7
G		 404 enum rf_pwrstate rfpwr_state)
405{
406 struct rtl_priv *rtlpriv = rtl_priv(hw);
407 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
408 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
409 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
410 bool bresult = true;
411 u8 i, queue_id;
412 struct rtl8192_tx_ring *ring = NULL;
413
f0a39ae7
G		 414 switch (rfpwr_state) {
415 case ERFON:
416 if ((ppsc->rfpwr_state == ERFOFF) &&
417 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
418 bool rtstatus;
419 u32 InitializeCount = 0;
420
421 do {
422 InitializeCount++;
423 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 424 "IPS Set eRf nic enable\n");
f0a39ae7 425 rtstatus = rtl_ps_enable_nic(hw);
23677ce3 426 } while (!rtstatus && (InitializeCount < 10));
f0a39ae7
G		 427 RT_CLEAR_PS_LEVEL(ppsc,
428 RT_RF_OFF_LEVL_HALT_NIC);
429 } else {
430 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507
JP		 431 "Set ERFON sleeped:%d ms\n",
432 jiffies_to_msecs(jiffies -
433 ppsc->last_sleep_jiffies));
f0a39ae7
G		 434 ppsc->last_awake_jiffies = jiffies;
435 rtl92ce_phy_set_rf_on(hw);
436 }
437 if (mac->link_state == MAC80211_LINKED) {
438 rtlpriv->cfg->ops->led_control(hw,
439 LED_CTL_LINK);
440 } else {
441 rtlpriv->cfg->ops->led_control(hw,
442 LED_CTL_NO_LINK);
443 }
444 break;
445 case ERFOFF:
446 for (queue_id = 0, i = 0;
447 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
448 ring = &pcipriv->dev.tx_ring[queue_id];
449 if (skb_queue_len(&ring->queue) == 0 ||
450 queue_id == BEACON_QUEUE) {
451 queue_id++;
452 continue;
453 } else {
454 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 455 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
456 i + 1,
457 queue_id,
458 skb_queue_len(&ring->queue));
f0a39ae7
G		 459 udelay(10);
460 i++;
461 }
462 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
463 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 464 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
465 MAX_DOZE_WAITING_TIMES_9x,
466 queue_id,
467 skb_queue_len(&ring->queue));
f0a39ae7
G		 468 break;
469 }
470 }
471 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
472 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507 473 "IPS Set eRf nic disable\n");
f0a39ae7
G		 474 rtl_ps_disable_nic(hw);
475 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
476 } else {
477 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
478 rtlpriv->cfg->ops->led_control(hw,
479 LED_CTL_NO_LINK);
480 } else {
481 rtlpriv->cfg->ops->led_control(hw,
482 LED_CTL_POWER_OFF);
483 }
484 }
485 break;
486 case ERFSLEEP:
487 if (ppsc->rfpwr_state == ERFOFF)
91ddff8a 488 return false;
f0a39ae7
G		 489 for (queue_id = 0, i = 0;
490 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
491 ring = &pcipriv->dev.tx_ring[queue_id];
492 if (skb_queue_len(&ring->queue) == 0) {
493 queue_id++;
494 continue;
495 } else {
496 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 497 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
498 i + 1, queue_id,
499 skb_queue_len(&ring->queue));
f0a39ae7
G		 500 udelay(10);
501 i++;
502 }
503 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
504 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
f30d7507
JP		 505 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
506 MAX_DOZE_WAITING_TIMES_9x,
507 queue_id,
508 skb_queue_len(&ring->queue));
f0a39ae7
G		 509 break;
510 }
511 }
512 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
f30d7507
JP		 513 "Set ERFSLEEP awaked:%d ms\n",
514 jiffies_to_msecs(jiffies - ppsc->last_awake_jiffies));
f0a39ae7 515 ppsc->last_sleep_jiffies = jiffies;
1472d3a8 516 _rtl92c_phy_set_rf_sleep(hw);
f0a39ae7
G		 517 break;
518 default:
519 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
f30d7507 520 "switch case not processed\n");
f0a39ae7
G		 521 bresult = false;
522 break;
523 }
524 if (bresult)
525 ppsc->rfpwr_state = rfpwr_state;
f0a39ae7
G		 526 return bresult;
527}
528
1472d3a8 529bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
d3bb1429 530 enum rf_pwrstate rfpwr_state)
f0a39ae7
G		 531{
532 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
533 bool bresult = false;
534
535 if (rfpwr_state == ppsc->rfpwr_state)
536 return bresult;
1472d3a8 537 bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state);
f0a39ae7
G		 538 return bresult;
539}
Linux kernel - Deliverables
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