[deliverable/linux.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192de / phy.h

/******************************************************************************
 *
 * Copyright(c) 2009-2012  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#ifndef __RTL92D_PHY_H__
#define __RTL92D_PHY_H__

#define MAX_PRECMD_CNT				16
#define MAX_RFDEPENDCMD_CNT			16
#define MAX_POSTCMD_CNT				16

#define MAX_DOZE_WAITING_TIMES_9x		64

#define RT_CANNOT_IO(hw)			false
#define HIGHPOWER_RADIOA_ARRAYLEN		22

#define MAX_TOLERANCE				5

#define	APK_BB_REG_NUM				5
#define	APK_AFE_REG_NUM				16
#define	APK_CURVE_REG_NUM			4
#define	PATH_NUM				2

#define LOOP_LIMIT				5
#define MAX_STALL_TIME				50
#define ANTENNA_DIVERSITY_VALUE			0x80
#define MAX_TXPWR_IDX_NMODE_92S			63
#define RESET_CNT_LIMIT				3

#define IQK_ADDA_REG_NUM			16
#define IQK_BB_REG_NUM				10
#define IQK_BB_REG_NUM_test			6
#define IQK_MAC_REG_NUM				4
#define RX_INDEX_MAPPING_NUM			15

#define IQK_DELAY_TIME				1

#define CT_OFFSET_MAC_ADDR			0X16

#define CT_OFFSET_CCK_TX_PWR_IDX		0x5A
#define CT_OFFSET_HT401S_TX_PWR_IDX		0x60
#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF	0x66
#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF		0x69
#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF		0x6C

#define CT_OFFSET_HT40_MAX_PWR_OFFSET		0x6F
#define CT_OFFSET_HT20_MAX_PWR_OFFSET		0x72

#define CT_OFFSET_CHANNEL_PLAH			0x75
#define CT_OFFSET_THERMAL_METER			0x78
#define CT_OFFSET_RF_OPTION			0x79
#define CT_OFFSET_VERSION			0x7E
#define CT_OFFSET_CUSTOMER_ID			0x7F

enum swchnlcmd_id {
	CMDID_END,
	CMDID_SET_TXPOWEROWER_LEVEL,
	CMDID_BBREGWRITE10,
	CMDID_WRITEPORT_ULONG,
	CMDID_WRITEPORT_USHORT,
	CMDID_WRITEPORT_UCHAR,
	CMDID_RF_WRITEREG,
};

struct swchnlcmd {
	enum swchnlcmd_id cmdid;
	u32 para1;
	u32 para2;
	u32 msdelay;
};

enum baseband_config_type {
	BASEBAND_CONFIG_PHY_REG = 0,
	BASEBAND_CONFIG_AGC_TAB = 1,
};

enum rf_content {
	radioa_txt = 0,
	radiob_txt = 1,
	radioc_txt = 2,
	radiod_txt = 3
};

static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
						     unsigned long *flag)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	if (rtlpriv->rtlhal.interfaceindex == 1)
		spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
}

static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
						     unsigned long *flag)
{
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	if (rtlpriv->rtlhal.interfaceindex == 1)
		spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
			*flag);
}

u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
			    u32 regaddr, u32 bitmask);
void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
			   u32 regaddr, u32 bitmask, u32 data);
u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
			    enum radio_path rfpath, u32 regaddr,
			    u32 bitmask);
void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
			   enum radio_path rfpath, u32 regaddr,
			   u32 bitmask, u32 data);
bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
					  enum radio_path rfpath);
void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
			    enum nl80211_channel_type ch_type);
u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
					  enum rf_content content,
					  enum radio_path rfpath);
bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
				   enum rf_pwrstate rfpwr_state);

void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
				       unsigned long *flag);
void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
				       unsigned long *flag);
u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);

#endif
Commit	Line	Data
7274a8c2 CL	1	/******************************************************************************
7274a8c2 CL	2	*
6a57b08e	3	* Copyright(c) 2009-2012 Realtek Corporation.
7274a8c2 CL	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of version 2 of the GNU General Public License as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	17	*
	18	* The full GNU General Public License is included in this distribution in the
	19	* file called LICENSE.
	20	*
	21	* Contact Information:
	22	* wlanfae <wlanfae@realtek.com>
	23	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	24	* Hsinchu 300, Taiwan.
	25	*
	26	* Larry Finger <Larry.Finger@lwfinger.net>
	27	*
	28	*****************************************************************************/
	29
	30	#ifndef __RTL92D_PHY_H__
	31	#define __RTL92D_PHY_H__
	32
	33	#define MAX_PRECMD_CNT 16
	34	#define MAX_RFDEPENDCMD_CNT 16
	35	#define MAX_POSTCMD_CNT 16
	36
	37	#define MAX_DOZE_WAITING_TIMES_9x 64
	38
	39	#define RT_CANNOT_IO(hw) false
	40	#define HIGHPOWER_RADIOA_ARRAYLEN 22
	41
7274a8c2	42	#define MAX_TOLERANCE 5
7274a8c2 CL	43
	44	#define APK_BB_REG_NUM 5
	45	#define APK_AFE_REG_NUM 16
	46	#define APK_CURVE_REG_NUM 4
	47	#define PATH_NUM 2
	48
	49	#define LOOP_LIMIT 5
	50	#define MAX_STALL_TIME 50
	51	#define ANTENNA_DIVERSITY_VALUE 0x80
	52	#define MAX_TXPWR_IDX_NMODE_92S 63
	53	#define RESET_CNT_LIMIT 3
	54
	55	#define IQK_ADDA_REG_NUM 16
	56	#define IQK_BB_REG_NUM 10
	57	#define IQK_BB_REG_NUM_test 6
	58	#define IQK_MAC_REG_NUM 4
	59	#define RX_INDEX_MAPPING_NUM 15
	60
	61	#define IQK_DELAY_TIME 1
	62
	63	#define CT_OFFSET_MAC_ADDR 0X16
	64
	65	#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
	66	#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
	67	#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
	68	#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
	69	#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
	70
	71	#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
	72	#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
	73
	74	#define CT_OFFSET_CHANNEL_PLAH 0x75
	75	#define CT_OFFSET_THERMAL_METER 0x78
	76	#define CT_OFFSET_RF_OPTION 0x79
	77	#define CT_OFFSET_VERSION 0x7E
	78	#define CT_OFFSET_CUSTOMER_ID 0x7F
	79
	80	enum swchnlcmd_id {
	81	CMDID_END,
	82	CMDID_SET_TXPOWEROWER_LEVEL,
	83	CMDID_BBREGWRITE10,
	84	CMDID_WRITEPORT_ULONG,
	85	CMDID_WRITEPORT_USHORT,
	86	CMDID_WRITEPORT_UCHAR,
	87	CMDID_RF_WRITEREG,
	88	};
	89
	90	struct swchnlcmd {
	91	enum swchnlcmd_id cmdid;
	92	u32 para1;
	93	u32 para2;
	94	u32 msdelay;
	95	};
	96
	97	enum baseband_config_type {
	98	BASEBAND_CONFIG_PHY_REG = 0,
	99	BASEBAND_CONFIG_AGC_TAB = 1,
	100	};
	101
	102	enum rf_content {
	103	radioa_txt = 0,
	104	radiob_txt = 1,
	105	radioc_txt = 2,
	106	radiod_txt = 3
107	};
108
109	static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
110	unsigned long *flag)
111	{
112	struct rtl_priv *rtlpriv = rtl_priv(hw);
113
114	if (rtlpriv->rtlhal.interfaceindex == 1)
115	spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
116	}
117
118	static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
119	unsigned long *flag)
120	{
121	struct rtl_priv *rtlpriv = rtl_priv(hw);
122
123	if (rtlpriv->rtlhal.interfaceindex == 1)
124	spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
125	*flag);
126	}
127
7009deab	128	u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
a958df5d	129	u32 regaddr, u32 bitmask);
7009deab	130	void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
a958df5d	131	u32 regaddr, u32 bitmask, u32 data);
7009deab DM	132	u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
	133	enum radio_path rfpath, u32 regaddr,
	134	u32 bitmask);
	135	void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
	136	enum radio_path rfpath, u32 regaddr,
	137	u32 bitmask, u32 data);
a958df5d JP	138	bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
	139	bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
	140	bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
	141	bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
	142	enum radio_path rfpath);
	143	void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
	144	void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
a958df5d JP	145	void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
	146	enum nl80211_channel_type ch_type);
	147	u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
7274a8c2 CL	148	bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
	149	enum rf_content content,
	150	enum radio_path rfpath);
	151	bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
a958df5d JP	152	bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
a958df5d JP	153	enum rf_pwrstate rfpwr_state);
7274a8c2 CL	154
	155	void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
	156	void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
	157	u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
	158	void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
	159	void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
	160	bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
	161	void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
	162	void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
	163	void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
	164	void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
	165	void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
	166	void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
	167	unsigned long *flag);
	168	void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
	169	unsigned long *flag);
	170	u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
	171	void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
7274a8c2 CL	172
7274a8c2 CL	173	#endif