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Merge tag 'libnvdimm-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm...
[deliverable/linux.git] / drivers / net / wireless / realtek / rtlwifi / rtl8723be / pwrseq.h
CommitLineData
a619d1ab
LF		 1/******************************************************************************
2 *
3 * Copyright(c) 2009-2014 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#ifndef __RTL8723BE_PWRSEQ_H__
27#define __RTL8723BE_PWRSEQ_H__
28
5c99f04f
LF		 29#include "../pwrseqcmd.h"
30/**
31 * Check document WM-20130425-JackieLau-RTL8723B_Power_Architecture v05.vsd
a619d1ab
LF		 32 * There are 6 HW Power States:
33 * 0: POFF--Power Off
34 * 1: PDN--Power Down
35 * 2: CARDEMU--Card Emulation
36 * 3: ACT--Active Mode
37 * 4: LPS--Low Power State
38 * 5: SUS--Suspend
39 *
5c99f04f 40 * The transision from different states are defined below
a619d1ab
LF		 41 * TRANS_CARDEMU_TO_ACT
42 * TRANS_ACT_TO_CARDEMU
43 * TRANS_CARDEMU_TO_SUS
44 * TRANS_SUS_TO_CARDEMU
45 * TRANS_CARDEMU_TO_PDN
46 * TRANS_ACT_TO_LPS
47 * TRANS_LPS_TO_ACT
48 *
49 * TRANS_END
50 */
51#define RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS 23
52#define RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS 15
53#define RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS 15
54#define RTL8723B_TRANS_SUS_TO_CARDEMU_STEPS 15
55#define RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS 15
56#define RTL8723B_TRANS_PDN_TO_CARDEMU_STEPS 15
57#define RTL8723B_TRANS_ACT_TO_LPS_STEPS 15
58#define RTL8723B_TRANS_LPS_TO_ACT_STEPS 15
59#define RTL8723B_TRANS_END_STEPS 1
60
61#define RTL8723B_TRANS_CARDEMU_TO_ACT \
5c99f04f
LF		 62 /* format */ \
63 /* comments here */ \
64 /* {offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value}, */\
65 /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
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LF		 66 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
67 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
68 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
5c99f04f 69 /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
a619d1ab
LF		 70 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
71 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
72 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
5c99f04f 73 /*Delay 1ms*/ \
a619d1ab
LF		 74 {0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
75 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
76 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS}, \
5c99f04f 77 /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
a619d1ab
LF		 78 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
79 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
80 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), 0}, \
5c99f04f 81 /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[11]=0*/ \
a619d1ab
LF		 82 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
83 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)|BIT(2)), 0}, \
5c99f04f 84 /* Disable USB suspend */ \
a619d1ab 85 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
5c99f04f
LF		 86 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , BIT(0)}, \
87 /* wait till 0x04[17] = 1 power ready*/ \
a619d1ab
LF		 88 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
89 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
5c99f04f 90 /* Enable USB suspend */ \
a619d1ab 91 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
5c99f04f
LF		 92 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) , 0}, \
93 /* release WLON reset 0x04[16]=1*/ \
a619d1ab
LF		 94 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
95 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
5c99f04f 96 /* disable HWPDN 0x04[15]=0*/ \
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LF		 97 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
98 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
5c99f04f 99 /* disable WL suspend*/ \
a619d1ab
LF		 100 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
101 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT(4)|BIT(3)), 0}, \
5c99f04f 102 /* polling until return 0*/ \
a619d1ab
LF		 103 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
104 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
105 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
106 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
5c99f04f 107 /* Enable WL control XTAL setting*/ \
a619d1ab
LF		 108 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
109 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)}, \
5c99f04f 110 /*Enable falling edge triggering interrupt*/ \
a619d1ab
LF		 111 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
112 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
5c99f04f 113 /*Enable GPIO9 interrupt mode*/ \
a619d1ab
LF		 114 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
5c99f04f 116 /*Enable GPIO9 input mode*/ \
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LF		 117 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
5c99f04f 119 /*Enable HSISR GPIO[C:0] interrupt*/ \
a619d1ab
LF		 120 {0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
121 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
5c99f04f 122 /*Enable HSISR GPIO9 interrupt*/ \
a619d1ab
LF		 123 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
124 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
5c99f04f 125 /*For GPIO9 internal pull high setting by test chip*/ \
a619d1ab
LF		 126 {0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
127 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3), BIT(3)}, \
5c99f04f 128 /*For GPIO9 internal pull high setting*/ \
a619d1ab
LF		 129 {0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), BIT(6)},
131
132#define RTL8723B_TRANS_ACT_TO_CARDEMU \
5c99f04f
LF		 133 /* format */ \
134 /* comments here */ \
135 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
136 /*0x1F[7:0] = 0 turn off RF*/ \
a619d1ab
LF		 137 {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
138 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
5c99f04f
LF		 139 /*0x4C[24] = 0x4F[0] = 0, */ \
140 /*switch DPDT_SEL_P output from register 0x65[2] */ \
a619d1ab
LF		 141 {0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
142 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
5c99f04f 143 /*Enable rising edge triggering interrupt*/ \
a619d1ab
LF		 144 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
145 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
5c99f04f 146 /*0x04[9] = 1 turn off MAC by HW state machine*/ \
a619d1ab
LF		 147 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
148 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
5c99f04f 149 /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
a619d1ab
LF		 150 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
151 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
5c99f04f 152 /* Enable BT control XTAL setting*/ \
a619d1ab
LF		 153 {0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
154 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6), 0}, \
5c99f04f 155 /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
a619d1ab
LF		 156 {0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
157 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
158 PWR_CMD_WRITE, BIT(5), BIT(5)}, \
5c99f04f 159 /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
a619d1ab
LF		 160 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
161 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
162 PWR_CMD_WRITE, BIT(0), 0},
163
164#define RTL8723B_TRANS_CARDEMU_TO_SUS \
5c99f04f
LF		 165 /* format */ \
166 /* comments here */ \
167 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value },*/\
168 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
a619d1ab
LF		 169 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), (BIT(4) | BIT(3))}, \
5c99f04f 171 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
a619d1ab
LF		 172 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
173 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
174 PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
5c99f04f 175 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
a619d1ab
LF		 176 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
5c99f04f 178 /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
a619d1ab
LF		 179 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
180 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
5c99f04f 181 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
a619d1ab
LF		 182 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
183 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},\
5c99f04f 184 /*Set SDIO suspend local register*/ \
a619d1ab
LF		 185 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
186 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
5c99f04f 187 /*wait power state to suspend*/ \
a619d1ab
LF		 188 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
189 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
190
191#define RTL8723B_TRANS_SUS_TO_CARDEMU \
5c99f04f
LF		 192 /* format */ \
193 /* comments here */ \
194 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
195 /*clear suspend enable and power down enable*/ \
a619d1ab
LF		 196 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
197 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
5c99f04f 198 /*Set SDIO suspend local register*/ \
a619d1ab
LF		 199 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
200 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
5c99f04f 201 /*wait power state to suspend*/ \
a619d1ab
LF		 202 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
203 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
5c99f04f 204 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
a619d1ab
LF		 205 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
206 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
5c99f04f 207 /*0x04[12:11] = 2b'01enable WL suspend*/ \
a619d1ab
LF		 208 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
209 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0},
210
211#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \
5c99f04f
LF		 212 /* format */ \
213 /* comments here */ \
214 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
215 /*0x07=0x20 , SOP option to disable BG/MB*/ \
a619d1ab
LF		 216 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
217 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20}, \
5c99f04f 218 /*0x04[12:11] = 2b'01 enable WL suspend*/ \
a619d1ab
LF		 219 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
220 PWR_INTF_USB_MSK | PWR_INTF_SDIO_MSK, \
221 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), BIT(3)}, \
5c99f04f 222 /*0x04[10] = 1, enable SW LPS*/ \
a619d1ab
LF		 223 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
224 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(2), BIT(2)}, \
5c99f04f 225 /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
a619d1ab
LF		 226 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
227 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 1}, \
5c99f04f 228 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
a619d1ab
LF		 229 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
230 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
5c99f04f 231 /*Set SDIO suspend local register*/ \
a619d1ab
LF		 232 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
233 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
5c99f04f 234 /*wait power state to suspend*/ \
a619d1ab
LF		 235 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
236 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0},
237
238#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \
5c99f04f
LF		 239 /* format */ \
240 /* comments here */ \
241 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
242 /*clear suspend enable and power down enable*/ \
a619d1ab
LF		 243 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
244 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, \
5c99f04f 245 /*Set SDIO suspend local register*/ \
a619d1ab
LF		 246 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
247 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
5c99f04f 248 /*wait power state to suspend*/ \
a619d1ab
LF		 249 {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
250 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
5c99f04f 251 /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
a619d1ab
LF		 252 {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
5c99f04f 254 /*0x04[12:11] = 2b'01enable WL suspend*/ \
a619d1ab
LF		 255 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
256 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3)|BIT(4), 0}, \
5c99f04f 257 /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
a619d1ab
LF		 258 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
5c99f04f 260 /*PCIe DMA start*/ \
a619d1ab
LF		 261 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
263
264#define RTL8723B_TRANS_CARDEMU_TO_PDN \
5c99f04f
LF		 265 /* format */ \
266 /* comments here */ \
267 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
268 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
a619d1ab
LF		 269 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
270 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
5c99f04f 271 /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
a619d1ab
LF		 272 {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
273 PWR_INTF_SDIO_MSK | PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, \
274 PWR_CMD_WRITE, 0xFF, 0x20}, \
5c99f04f 275 /* 0x04[16] = 0*/ \
a619d1ab
LF		 276 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
277 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
5c99f04f 278 /* 0x04[15] = 1*/ \
a619d1ab
LF		 279 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
280 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)},
281
282#define RTL8723B_TRANS_PDN_TO_CARDEMU \
5c99f04f
LF		 283 /* format */ \
284 /* comments here */ \
285 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
286 /* 0x04[15] = 0*/ \
a619d1ab
LF		 287 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0},
289
290#define RTL8723B_TRANS_ACT_TO_LPS \
5c99f04f
LF		 291 /* format */ \
292 /* comments here */ \
293 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
294 /*PCIe DMA stop*/ \
a619d1ab
LF		 295 {0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
296 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
5c99f04f 297 /*Tx Pause*/ \
a619d1ab
LF		 298 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
299 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
5c99f04f 300 /*Should be zero if no packet is transmitting*/ \
a619d1ab
LF		 301 {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
302 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
5c99f04f 303 /*Should be zero if no packet is transmitting*/ \
a619d1ab
LF		 304 {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
305 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
5c99f04f 306 /*Should be zero if no packet is transmitting*/ \
a619d1ab
LF		 307 {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
308 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
5c99f04f 309 /*Should be zero if no packet is transmitting*/ \
a619d1ab
LF		 310 {0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
311 PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
5c99f04f 312 /*CCK and OFDM are disabled,and clock are gated*/ \
a619d1ab
LF		 313 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
314 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
5c99f04f 315 /*Delay 1us*/ \
a619d1ab
LF		 316 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
317 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
5c99f04f 318 /*Whole BB is reset*/ \
a619d1ab
LF		 319 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
320 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
5c99f04f 321 /*Reset MAC TRX*/ \
a619d1ab
LF		 322 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
323 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03}, \
5c99f04f 324 /*check if removed later*/ \
a619d1ab
LF		 325 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
326 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0}, \
5c99f04f 327 /*When driver enter Sus/ Disable, enable LOP for BT*/ \
a619d1ab
LF		 328 {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
329 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00}, \
5c99f04f 330 /*Respond TxOK to scheduler*/ \
a619d1ab
LF		 331 {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
332 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)},
333
334#define RTL8723B_TRANS_LPS_TO_ACT \
5c99f04f
LF		 335 /* format */ \
336 /* comments here */ \
337 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
338 /*SDIO RPWM*/ \
a619d1ab 339 {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
5c99f04f
LF		 340 PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, \
341 /*USB RPWM*/ \
a619d1ab
LF		 342 {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
343 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
5c99f04f 344 /*PCIe RPWM*/ \
a619d1ab
LF		 345 {0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
346 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, \
5c99f04f 347 /*Delay*/ \
a619d1ab
LF		 348 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
349 PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
5c99f04f 350 /*. 0x08[4] = 0 switch TSF to 40M*/ \
a619d1ab
LF		 351 {0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
352 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
5c99f04f 353 /*Polling 0x109[7]=0 TSF in 40M*/ \
a619d1ab 354 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
5c99f04f
LF		 355 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
356 /*. 0x29[7:6] = 2b'00 enable BB clock*/ \
a619d1ab
LF		 357 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
358 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6)|BIT(7), 0}, \
5c99f04f 359 /*. 0x101[1] = 1*/ \
a619d1ab
LF		 360 {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
361 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
5c99f04f 362 /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
a619d1ab
LF		 363 {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
364 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
5c99f04f 365 /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
a619d1ab
LF		 366 {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
367 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
5c99f04f 368 /*. 0x522 = 0*/ \
a619d1ab
LF		 369 {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
370 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},
371
372#define RTL8723B_TRANS_END \
5c99f04f
LF		 373 /* format */ \
374 /* comments here */ \
375 /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, */\
a619d1ab
LF		 376 {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, 0, \
377 PWR_CMD_END, 0, 0},
378
379extern struct wlan_pwr_cfg rtl8723B_power_on_flow
380 [RTL8723B_TRANS_CARDEMU_TO_ACT_STEPS +
381 RTL8723B_TRANS_END_STEPS];
382extern struct wlan_pwr_cfg rtl8723B_radio_off_flow
383 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
384 RTL8723B_TRANS_END_STEPS];
385extern struct wlan_pwr_cfg rtl8723B_card_disable_flow
386 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
387 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
388 RTL8723B_TRANS_END_STEPS];
389extern struct wlan_pwr_cfg rtl8723B_card_enable_flow
390 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
391 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
392 RTL8723B_TRANS_END_STEPS];
393extern struct wlan_pwr_cfg rtl8723B_suspend_flow
394 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
395 RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
396 RTL8723B_TRANS_END_STEPS];
397extern struct wlan_pwr_cfg rtl8723B_resume_flow
398 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
399 RTL8723B_TRANS_CARDEMU_TO_SUS_STEPS +
400 RTL8723B_TRANS_END_STEPS];
401extern struct wlan_pwr_cfg rtl8723B_hwpdn_flow
402 [RTL8723B_TRANS_ACT_TO_CARDEMU_STEPS +
403 RTL8723B_TRANS_CARDEMU_TO_PDN_STEPS +
404 RTL8723B_TRANS_END_STEPS];
405extern struct wlan_pwr_cfg rtl8723B_enter_lps_flow
406 [RTL8723B_TRANS_ACT_TO_LPS_STEPS +
407 RTL8723B_TRANS_END_STEPS];
408extern struct wlan_pwr_cfg rtl8723B_leave_lps_flow
409 [RTL8723B_TRANS_LPS_TO_ACT_STEPS +
410 RTL8723B_TRANS_END_STEPS];
411
412/* RTL8723 Power Configuration CMDs for PCIe interface */
413#define RTL8723_NIC_PWR_ON_FLOW rtl8723B_power_on_flow
414#define RTL8723_NIC_RF_OFF_FLOW rtl8723B_radio_off_flow
415#define RTL8723_NIC_DISABLE_FLOW rtl8723B_card_disable_flow
416#define RTL8723_NIC_ENABLE_FLOW rtl8723B_card_enable_flow
417#define RTL8723_NIC_SUSPEND_FLOW rtl8723B_suspend_flow
418#define RTL8723_NIC_RESUME_FLOW rtl8723B_resume_flow
419#define RTL8723_NIC_PDN_FLOW rtl8723B_hwpdn_flow
420#define RTL8723_NIC_LPS_ENTER_FLOW rtl8723B_enter_lps_flow
421#define RTL8723_NIC_LPS_LEAVE_FLOW rtl8723B_leave_lps_flow
422
423#endif
Linux kernel - Deliverables
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