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Merge tag 'sound-3.4' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
9c9a0d14 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
5a0e3ad6 34#include <linux/slab.h>
95ea3627
ID		 35
36#include "rt2x00.h"
37#include "rt2x00pci.h"
38#include "rt2400pci.h"
39
40/*
41 * Register access.
42 * All access to the CSR registers will go through the methods
43 * rt2x00pci_register_read and rt2x00pci_register_write.
44 * BBP and RF register require indirect register access,
45 * and use the CSR registers BBPCSR and RFCSR to achieve this.
46 * These indirect registers work with busy bits,
47 * and we will try maximal REGISTER_BUSY_COUNT times to access
48 * the register while taking a REGISTER_BUSY_DELAY us delay
f5a9987d 49 * between each attempt. When the busy bit is still set at that time,
95ea3627
ID		 50 * the access attempt is considered to have failed,
51 * and we will print an error.
52 */
c9c3b1a5
ID		 53#define WAIT_FOR_BBP(__dev, __reg) \
54 rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
55#define WAIT_FOR_RF(__dev, __reg) \
56 rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
95ea3627 57
0e14f6d3 58static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 59 const unsigned int word, const u8 value)
60{
61 u32 reg;
62
8ff48a8b
ID		 63 mutex_lock(&rt2x00dev->csr_mutex);
64
95ea3627 65 /*
c9c3b1a5
ID		 66 * Wait until the BBP becomes available, afterwards we
67 * can safely write the new data into the register.
95ea3627 68 */
c9c3b1a5
ID		 69 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
70 reg = 0;
71 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
72 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
73 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
74 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
75
76 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
77 }
8ff48a8b 78
8ff48a8b 79 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 80}
81
0e14f6d3 82static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 83 const unsigned int word, u8 *value)
84{
85 u32 reg;
86
8ff48a8b
ID		 87 mutex_lock(&rt2x00dev->csr_mutex);
88
95ea3627 89 /*
c9c3b1a5
ID		 90 * Wait until the BBP becomes available, afterwards we
91 * can safely write the read request into the register.
92 * After the data has been written, we wait until hardware
93 * returns the correct value, if at any time the register
94 * doesn't become available in time, reg will be 0xffffffff
95 * which means we return 0xff to the caller.
95ea3627 96 */
c9c3b1a5
ID		 97 if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
98 reg = 0;
99 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
100 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
101 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
95ea3627 102
c9c3b1a5 103 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
95ea3627 104
c9c3b1a5
ID		 105 WAIT_FOR_BBP(rt2x00dev, &reg);
106 }
95ea3627
ID		 107
108 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
8ff48a8b
ID		 109
110 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 111}
112
0e14f6d3 113static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 114 const unsigned int word, const u32 value)
115{
116 u32 reg;
95ea3627 117
8ff48a8b
ID		 118 mutex_lock(&rt2x00dev->csr_mutex);
119
c9c3b1a5
ID		 120 /*
121 * Wait until the RF becomes available, afterwards we
122 * can safely write the new data into the register.
123 */
124 if (WAIT_FOR_RF(rt2x00dev, &reg)) {
125 reg = 0;
126 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
127 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
128 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
129 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
130
131 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
132 rt2x00_rf_write(rt2x00dev, word, value);
95ea3627
ID		 133 }
134
8ff48a8b 135 mutex_unlock(&rt2x00dev->csr_mutex);
95ea3627
ID		 136}
137
138static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
139{
140 struct rt2x00_dev *rt2x00dev = eeprom->data;
141 u32 reg;
142
143 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
144
145 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
146 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
147 eeprom->reg_data_clock =
148 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
149 eeprom->reg_chip_select =
150 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
151}
152
153static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
154{
155 struct rt2x00_dev *rt2x00dev = eeprom->data;
156 u32 reg = 0;
157
158 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
159 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
160 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
161 !!eeprom->reg_data_clock);
162 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
163 !!eeprom->reg_chip_select);
164
165 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
166}
167
168#ifdef CONFIG_RT2X00_LIB_DEBUGFS
95ea3627
ID		 169static const struct rt2x00debug rt2400pci_rt2x00debug = {
170 .owner = THIS_MODULE,
171 .csr = {
743b97ca
ID		 172 .read = rt2x00pci_register_read,
173 .write = rt2x00pci_register_write,
174 .flags = RT2X00DEBUGFS_OFFSET,
175 .word_base = CSR_REG_BASE,
95ea3627
ID		 176 .word_size = sizeof(u32),
177 .word_count = CSR_REG_SIZE / sizeof(u32),
178 },
179 .eeprom = {
180 .read = rt2x00_eeprom_read,
181 .write = rt2x00_eeprom_write,
743b97ca 182 .word_base = EEPROM_BASE,
95ea3627
ID		 183 .word_size = sizeof(u16),
184 .word_count = EEPROM_SIZE / sizeof(u16),
185 },
186 .bbp = {
187 .read = rt2400pci_bbp_read,
188 .write = rt2400pci_bbp_write,
743b97ca 189 .word_base = BBP_BASE,
95ea3627
ID		 190 .word_size = sizeof(u8),
191 .word_count = BBP_SIZE / sizeof(u8),
192 },
193 .rf = {
194 .read = rt2x00_rf_read,
195 .write = rt2400pci_rf_write,
743b97ca 196 .word_base = RF_BASE,
95ea3627
ID		 197 .word_size = sizeof(u32),
198 .word_count = RF_SIZE / sizeof(u32),
199 },
200};
201#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
202
95ea3627
ID		 203static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
204{
205 u32 reg;
206
207 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
208 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
209}
95ea3627 210
771fd565 211#ifdef CONFIG_RT2X00_LIB_LEDS
a2e1d52a 212static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 213 enum led_brightness brightness)
214{
215 struct rt2x00_led *led =
216 container_of(led_cdev, struct rt2x00_led, led_dev);
217 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 218 u32 reg;
219
220 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
221
a2e1d52a 222 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 223 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 224 else if (led->type == LED_TYPE_ACTIVITY)
225 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 226
227 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
228}
a2e1d52a
ID		 229
230static int rt2400pci_blink_set(struct led_classdev *led_cdev,
231 unsigned long *delay_on,
232 unsigned long *delay_off)
233{
234 struct rt2x00_led *led =
235 container_of(led_cdev, struct rt2x00_led, led_dev);
236 u32 reg;
237
238 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
239 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
240 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
241 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
242
243 return 0;
244}
475433be
ID		 245
246static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
247 struct rt2x00_led *led,
248 enum led_type type)
249{
250 led->rt2x00dev = rt2x00dev;
251 led->type = type;
252 led->led_dev.brightness_set = rt2400pci_brightness_set;
253 led->led_dev.blink_set = rt2400pci_blink_set;
254 led->flags = LED_INITIALIZED;
255}
771fd565 256#endif /* CONFIG_RT2X00_LIB_LEDS */
a9450b70 257
95ea3627
ID		 258/*
259 * Configuration handlers.
260 */
3a643d24
ID		 261static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
262 const unsigned int filter_flags)
263{
264 u32 reg;
265
266 /*
267 * Start configuration steps.
268 * Note that the version error will always be dropped
269 * since there is no filter for it at this time.
270 */
271 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
272 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
273 !(filter_flags & FIF_FCSFAIL));
274 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
275 !(filter_flags & FIF_PLCPFAIL));
276 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
277 !(filter_flags & FIF_CONTROL));
278 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
279 !(filter_flags & FIF_PROMISC_IN_BSS));
280 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 281 !(filter_flags & FIF_PROMISC_IN_BSS) &&
282 !rt2x00dev->intf_ap_count);
3a643d24
ID		 283 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
284 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
285}
286
6bb40dd1
ID		 287static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
288 struct rt2x00_intf *intf,
289 struct rt2x00intf_conf *conf,
290 const unsigned int flags)
95ea3627 291{
6bb40dd1
ID		 292 unsigned int bcn_preload;
293 u32 reg;
95ea3627 294
6bb40dd1 295 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 296 /*
297 * Enable beacon config
298 */
bad13639 299 bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
6bb40dd1
ID		 300 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
301 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
302 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 303
6bb40dd1
ID		 304 /*
305 * Enable synchronisation.
306 */
307 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
6bb40dd1
ID		 308 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
309 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
310 }
95ea3627 311
6bb40dd1
ID		 312 if (flags & CONFIG_UPDATE_MAC)
313 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
314 conf->mac, sizeof(conf->mac));
95ea3627 315
6bb40dd1
ID		 316 if (flags & CONFIG_UPDATE_BSSID)
317 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
318 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 319}
320
3a643d24 321static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
02044643
HS		 322 struct rt2x00lib_erp *erp,
323 u32 changed)
95ea3627 324{
5c58ee51 325 int preamble_mask;
95ea3627 326 u32 reg;
95ea3627 327
5c58ee51
ID		 328 /*
329 * When short preamble is enabled, we should set bit 0x08
330 */
02044643
HS		 331 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
332 preamble_mask = erp->short_preamble << 3;
333
334 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
335 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
336 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
337 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
338 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
339 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
340
341 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
342 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
343 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
344 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
345 GET_DURATION(ACK_SIZE, 10));
346 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
347
348 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
349 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
350 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
351 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
352 GET_DURATION(ACK_SIZE, 20));
353 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
354
355 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
356 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
357 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
358 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
359 GET_DURATION(ACK_SIZE, 55));
360 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
361
362 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
363 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
364 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
365 rt2x00_set_field32(&reg, ARCSR2_LENGTH,
366 GET_DURATION(ACK_SIZE, 110));
367 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
368 }
369
370 if (changed & BSS_CHANGED_BASIC_RATES)
371 rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);
372
373 if (changed & BSS_CHANGED_ERP_SLOT) {
374 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
375 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
376 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
377
378 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
379 rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
380 rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
381 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
382
383 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
384 rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
385 rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
386 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
387 }
388
389 if (changed & BSS_CHANGED_BEACON_INT) {
390 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
391 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
392 erp->beacon_int * 16);
393 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
394 erp->beacon_int * 16);
395 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
396 }
95ea3627
ID		 397}
398
e4ea1c40
ID		 399static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
400 struct antenna_setup *ant)
95ea3627 401{
e4ea1c40
ID		 402 u8 r1;
403 u8 r4;
404
405 /*
406 * We should never come here because rt2x00lib is supposed
407 * to catch this and send us the correct antenna explicitely.
408 */
409 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
410 ant->tx == ANTENNA_SW_DIVERSITY);
411
412 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
413 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
414
415 /*
416 * Configure the TX antenna.
417 */
418 switch (ant->tx) {
419 case ANTENNA_HW_DIVERSITY:
420 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
421 break;
422 case ANTENNA_A:
423 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
424 break;
425 case ANTENNA_B:
426 default:
427 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
428 break;
429 }
430
431 /*
432 * Configure the RX antenna.
433 */
434 switch (ant->rx) {
435 case ANTENNA_HW_DIVERSITY:
436 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
437 break;
438 case ANTENNA_A:
439 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
440 break;
441 case ANTENNA_B:
442 default:
443 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
444 break;
445 }
446
447 rt2400pci_bbp_write(rt2x00dev, 4, r4);
448 rt2400pci_bbp_write(rt2x00dev, 1, r1);
95ea3627
ID		 449}
450
451static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 452 struct rf_channel *rf)
95ea3627 453{
95ea3627
ID		 454 /*
455 * Switch on tuning bits.
456 */
5c58ee51
ID		 457 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
458 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 459
5c58ee51
ID		 460 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
461 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
462 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 463
464 /*
465 * RF2420 chipset don't need any additional actions.
466 */
5122d898 467 if (rt2x00_rf(rt2x00dev, RF2420))
95ea3627
ID		 468 return;
469
470 /*
471 * For the RT2421 chipsets we need to write an invalid
472 * reference clock rate to activate auto_tune.
473 * After that we set the value back to the correct channel.
474 */
5c58ee51 475 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 476 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 477 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 478
479 msleep(1);
480
5c58ee51
ID		 481 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
482 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
483 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 484
485 msleep(1);
486
487 /*
488 * Switch off tuning bits.
489 */
5c58ee51
ID		 490 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
491 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 492
5c58ee51
ID		 493 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
494 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 495
496 /*
497 * Clear false CRC during channel switch.
498 */
5c58ee51 499 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 500}
501
502static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
503{
504 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
505}
506
e4ea1c40
ID		 507static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
508 struct rt2x00lib_conf *libconf)
95ea3627 509{
e4ea1c40 510 u32 reg;
95ea3627 511
e4ea1c40
ID		 512 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
513 rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
514 libconf->conf->long_frame_max_tx_count);
515 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
516 libconf->conf->short_frame_max_tx_count);
517 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
95ea3627
ID		 518}
519
7d7f19cc
ID		 520static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
521 struct rt2x00lib_conf *libconf)
522{
523 enum dev_state state =
524 (libconf->conf->flags & IEEE80211_CONF_PS) ?
525 STATE_SLEEP : STATE_AWAKE;
526 u32 reg;
527
528 if (state == STATE_SLEEP) {
529 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
530 rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
6b347bff 531 (rt2x00dev->beacon_int - 20) * 16);
7d7f19cc
ID		 532 rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
533 libconf->conf->listen_interval - 1);
534
535 /* We must first disable autowake before it can be enabled */
536 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
537 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
538
539 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
540 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
5731858d
GW		 541 } else {
542 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
543 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
544 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
7d7f19cc
ID		 545 }
546
547 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
548}
549
95ea3627 550static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 551 struct rt2x00lib_conf *libconf,
552 const unsigned int flags)
95ea3627 553{
e4ea1c40 554 if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
5c58ee51 555 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
e4ea1c40 556 if (flags & IEEE80211_CONF_CHANGE_POWER)
5c58ee51
ID		 557 rt2400pci_config_txpower(rt2x00dev,
558 libconf->conf->power_level);
e4ea1c40
ID		 559 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
560 rt2400pci_config_retry_limit(rt2x00dev, libconf);
7d7f19cc
ID		 561 if (flags & IEEE80211_CONF_CHANGE_PS)
562 rt2400pci_config_ps(rt2x00dev, libconf);
95ea3627
ID		 563}
564
565static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 566 const int cw_min, const int cw_max)
95ea3627
ID		 567{
568 u32 reg;
569
570 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 571 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
572 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 573 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
574}
575
95ea3627
ID		 576/*
577 * Link tuning
578 */
ebcf26da
ID		 579static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
580 struct link_qual *qual)
95ea3627
ID		 581{
582 u32 reg;
583 u8 bbp;
584
585 /*
586 * Update FCS error count from register.
587 */
588 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 589 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 590
591 /*
592 * Update False CCA count from register.
593 */
594 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 595 qual->false_cca = bbp;
95ea3627
ID		 596}
597
5352ff65
ID		 598static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
599 struct link_qual *qual, u8 vgc_level)
eb20b4e8 600{
223dcc26
ID		 601 if (qual->vgc_level_reg != vgc_level) {
602 rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
603 qual->vgc_level = vgc_level;
604 qual->vgc_level_reg = vgc_level;
605 }
eb20b4e8
ID		 606}
607
5352ff65
ID		 608static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
609 struct link_qual *qual)
95ea3627 610{
5352ff65 611 rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
95ea3627
ID		 612}
613
5352ff65
ID		 614static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
615 struct link_qual *qual, const u32 count)
95ea3627 616{
95ea3627
ID		 617 /*
618 * The link tuner should not run longer then 60 seconds,
619 * and should run once every 2 seconds.
620 */
5352ff65 621 if (count > 60 || !(count & 1))
95ea3627
ID		 622 return;
623
624 /*
625 * Base r13 link tuning on the false cca count.
626 */
5352ff65
ID		 627 if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
628 rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
629 else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
630 rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
95ea3627
ID		 631}
632
5450b7e2
ID		 633/*
634 * Queue handlers.
635 */
636static void rt2400pci_start_queue(struct data_queue *queue)
637{
638 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
639 u32 reg;
640
641 switch (queue->qid) {
642 case QID_RX:
643 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
644 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
645 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
646 break;
647 case QID_BEACON:
648 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
649 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
650 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
651 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
652 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
653 break;
654 default:
655 break;
656 }
657}
658
659static void rt2400pci_kick_queue(struct data_queue *queue)
660{
661 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
662 u32 reg;
663
664 switch (queue->qid) {
f615e9a3 665 case QID_AC_VO:
5450b7e2
ID		 666 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
667 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
668 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
669 break;
f615e9a3 670 case QID_AC_VI:
5450b7e2
ID		 671 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
672 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
673 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
674 break;
675 case QID_ATIM:
676 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
677 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
678 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
679 break;
680 default:
681 break;
682 }
683}
684
685static void rt2400pci_stop_queue(struct data_queue *queue)
686{
687 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
688 u32 reg;
689
690 switch (queue->qid) {
f615e9a3
ID		 691 case QID_AC_VO:
692 case QID_AC_VI:
5450b7e2
ID		 693 case QID_ATIM:
694 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
695 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
696 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
697 break;
698 case QID_RX:
699 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
700 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
701 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
702 break;
703 case QID_BEACON:
704 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
705 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
706 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
707 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
708 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bcf3cfd0
HS		 709
710 /*
711 * Wait for possibly running tbtt tasklets.
712 */
abc11994 713 tasklet_kill(&rt2x00dev->tbtt_tasklet);
5450b7e2
ID		 714 break;
715 default:
716 break;
717 }
718}
719
95ea3627
ID		 720/*
721 * Initialization functions.
722 */
798b7adb 723static bool rt2400pci_get_entry_state(struct queue_entry *entry)
95ea3627 724{
b8be63ff 725 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 726 u32 word;
727
798b7adb
ID		 728 if (entry->queue->qid == QID_RX) {
729 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 730
798b7adb
ID		 731 return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
732 } else {
733 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627 734
798b7adb
ID		 735 return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
736 rt2x00_get_field32(word, TXD_W0_VALID));
737 }
95ea3627
ID		 738}
739
798b7adb 740static void rt2400pci_clear_entry(struct queue_entry *entry)
95ea3627 741{
b8be63ff 742 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
798b7adb 743 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 744 u32 word;
745
798b7adb
ID		 746 if (entry->queue->qid == QID_RX) {
747 rt2x00_desc_read(entry_priv->desc, 2, &word);
748 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
749 rt2x00_desc_write(entry_priv->desc, 2, word);
750
751 rt2x00_desc_read(entry_priv->desc, 1, &word);
752 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
753 rt2x00_desc_write(entry_priv->desc, 1, word);
754
755 rt2x00_desc_read(entry_priv->desc, 0, &word);
756 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
757 rt2x00_desc_write(entry_priv->desc, 0, word);
758 } else {
759 rt2x00_desc_read(entry_priv->desc, 0, &word);
760 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
761 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
762 rt2x00_desc_write(entry_priv->desc, 0, word);
763 }
95ea3627
ID		 764}
765
181d6902 766static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 767{
b8be63ff 768 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 769 u32 reg;
770
95ea3627
ID		 771 /*
772 * Initialize registers.
773 */
774 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 775 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
776 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
e74df4a7 777 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
181d6902 778 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 779 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
780
b8be63ff 781 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 782 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 783 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 784 entry_priv->desc_dma);
95ea3627
ID		 785 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
786
b8be63ff 787 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 788 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 789 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 790 entry_priv->desc_dma);
95ea3627
ID		 791 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
792
e74df4a7 793 entry_priv = rt2x00dev->atim->entries[0].priv_data;
95ea3627 794 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 795 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 796 entry_priv->desc_dma);
95ea3627
ID		 797 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
798
e74df4a7 799 entry_priv = rt2x00dev->bcn->entries[0].priv_data;
95ea3627 800 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 801 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 802 entry_priv->desc_dma);
95ea3627
ID		 803 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
804
805 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
806 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 807 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 808 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
809
b8be63ff 810 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 811 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 812 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
813 entry_priv->desc_dma);
95ea3627
ID		 814 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
815
816 return 0;
817}
818
819static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
820{
821 u32 reg;
822
823 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
824 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
825 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
826 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
827
828 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
829 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
830 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
831 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
832 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
833
834 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
835 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
836 (rt2x00dev->rx->data_size / 128));
837 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
838
1f909162
ID		 839 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
840 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
841 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
842 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
843 rt2x00_set_field32(&reg, CSR14_TCFP, 0);
844 rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
845 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
846 rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
847 rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
848 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
849
95ea3627
ID		 850 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
851
852 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
853 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
854 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
855 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
856 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
857 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
858
859 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
860 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
861 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
862 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
863 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
864 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
865 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
866 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
867
868 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
869
870 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
871 return -EBUSY;
872
873 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
874 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
875
876 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
877 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
878 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
879
880 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
881 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
882 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
883 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
884 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
885 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
886
887 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
888 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
889 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
890 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
891 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
892
893 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
894 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
895 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
896 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
897
898 /*
899 * We must clear the FCS and FIFO error count.
900 * These registers are cleared on read,
901 * so we may pass a useless variable to store the value.
902 */
903 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
904 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
905
906 return 0;
907}
908
2b08da3f 909static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 910{
911 unsigned int i;
95ea3627
ID		 912 u8 value;
913
914 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
915 rt2400pci_bbp_read(rt2x00dev, 0, &value);
916 if ((value != 0xff) && (value != 0x00))
2b08da3f 917 return 0;
95ea3627
ID		 918 udelay(REGISTER_BUSY_DELAY);
919 }
920
921 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
922 return -EACCES;
2b08da3f
ID		 923}
924
925static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
926{
927 unsigned int i;
928 u16 eeprom;
929 u8 reg_id;
930 u8 value;
931
932 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
933 return -EACCES;
95ea3627 934
95ea3627
ID		 935 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
936 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
937 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
938 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
939 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
940 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
941 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
942 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
943 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
944 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
945 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
946 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
947 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
948 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
949
95ea3627
ID		 950 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
951 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
952
953 if (eeprom != 0xffff && eeprom != 0x0000) {
954 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
955 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 956 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
957 }
958 }
95ea3627
ID		 959
960 return 0;
961}
962
963/*
964 * Device state switch handlers.
965 */
95ea3627
ID		 966static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
967 enum dev_state state)
968{
b550911a 969 int mask = (state == STATE_RADIO_IRQ_OFF);
95ea3627 970 u32 reg;
bcf3cfd0 971 unsigned long flags;
95ea3627
ID		 972
973 /*
974 * When interrupts are being enabled, the interrupt registers
975 * should clear the register to assure a clean state.
976 */
977 if (state == STATE_RADIO_IRQ_ON) {
978 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
979 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
980 }
981
982 /*
983 * Only toggle the interrupts bits we are going to use.
984 * Non-checked interrupt bits are disabled by default.
985 */
bcf3cfd0
HS		 986 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
987
95ea3627
ID		 988 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
989 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
990 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
991 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
992 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
993 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
994 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0
HS		 995
996 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
997
998 if (state == STATE_RADIO_IRQ_OFF) {
999 /*
1000 * Ensure that all tasklets are finished before
1001 * disabling the interrupts.
1002 */
abc11994
HS		 1003 tasklet_kill(&rt2x00dev->txstatus_tasklet);
1004 tasklet_kill(&rt2x00dev->rxdone_tasklet);
1005 tasklet_kill(&rt2x00dev->tbtt_tasklet);
bcf3cfd0 1006 }
95ea3627
ID		 1007}
1008
1009static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1010{
1011 /*
1012 * Initialize all registers.
1013 */
2b08da3f
ID		 1014 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
1015 rt2400pci_init_registers(rt2x00dev) ||
1016 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 1017 return -EIO;
95ea3627 1018
95ea3627
ID		 1019 return 0;
1020}
1021
1022static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1023{
95ea3627 1024 /*
a2c9b652 1025 * Disable power
95ea3627 1026 */
a2c9b652 1027 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
95ea3627
ID		 1028}
1029
1030static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
1031 enum dev_state state)
1032{
9655a6ec 1033 u32 reg, reg2;
95ea3627
ID		 1034 unsigned int i;
1035 char put_to_sleep;
1036 char bbp_state;
1037 char rf_state;
1038
1039 put_to_sleep = (state != STATE_AWAKE);
1040
1041 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1042 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1043 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1044 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1045 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1046 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1047
1048 /*
1049 * Device is not guaranteed to be in the requested state yet.
1050 * We must wait until the register indicates that the
1051 * device has entered the correct state.
1052 */
1053 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
9655a6ec
GW		 1054 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
1055 bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
1056 rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
95ea3627
ID		 1057 if (bbp_state == state && rf_state == state)
1058 return 0;
9655a6ec 1059 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
95ea3627
ID		 1060 msleep(10);
1061 }
1062
95ea3627
ID		 1063 return -EBUSY;
1064}
1065
1066static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1067 enum dev_state state)
1068{
1069 int retval = 0;
1070
1071 switch (state) {
1072 case STATE_RADIO_ON:
1073 retval = rt2400pci_enable_radio(rt2x00dev);
1074 break;
1075 case STATE_RADIO_OFF:
1076 rt2400pci_disable_radio(rt2x00dev);
1077 break;
2b08da3f
ID		 1078 case STATE_RADIO_IRQ_ON:
1079 case STATE_RADIO_IRQ_OFF:
1080 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 1081 break;
1082 case STATE_DEEP_SLEEP:
1083 case STATE_SLEEP:
1084 case STATE_STANDBY:
1085 case STATE_AWAKE:
1086 retval = rt2400pci_set_state(rt2x00dev, state);
1087 break;
1088 default:
1089 retval = -ENOTSUPP;
1090 break;
1091 }
1092
2b08da3f
ID		 1093 if (unlikely(retval))
1094 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1095 state, retval);
1096
95ea3627
ID		 1097 return retval;
1098}
1099
1100/*
1101 * TX descriptor initialization
1102 */
93331458 1103static void rt2400pci_write_tx_desc(struct queue_entry *entry,
61486e0f 1104 struct txentry_desc *txdesc)
95ea3627 1105{
93331458
ID		 1106 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1107 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
85b7a8b3 1108 __le32 *txd = entry_priv->desc;
95ea3627 1109 u32 word;
95ea3627
ID		 1110
1111 /*
1112 * Start writing the descriptor words.
1113 */
85b7a8b3 1114 rt2x00_desc_read(txd, 1, &word);
c4da0048 1115 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
85b7a8b3 1116 rt2x00_desc_write(txd, 1, word);
4de36fe5 1117
95ea3627 1118 rt2x00_desc_read(txd, 2, &word);
df624ca5
GW		 1119 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1120 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
95ea3627
ID		 1121 rt2x00_desc_write(txd, 2, word);
1122
1123 rt2x00_desc_read(txd, 3, &word);
26a1d07f 1124 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
49da2605
ID		 1125 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1126 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
26a1d07f 1127 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
49da2605
ID		 1128 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1129 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1130 rt2x00_desc_write(txd, 3, word);
1131
1132 rt2x00_desc_read(txd, 4, &word);
26a1d07f
HS		 1133 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
1134 txdesc->u.plcp.length_low);
49da2605
ID		 1135 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1136 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
26a1d07f
HS		 1137 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
1138 txdesc->u.plcp.length_high);
49da2605
ID		 1139 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1140 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1141 rt2x00_desc_write(txd, 4, word);
1142
e01f1ec3
GW		 1143 /*
1144 * Writing TXD word 0 must the last to prevent a race condition with
1145 * the device, whereby the device may take hold of the TXD before we
1146 * finished updating it.
1147 */
95ea3627
ID		 1148 rt2x00_desc_read(txd, 0, &word);
1149 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1150 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1151 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1152 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1153 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1154 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1155 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1156 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1157 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902 1158 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
2517794b 1159 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
95ea3627 1160 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1161 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627 1162 rt2x00_desc_write(txd, 0, word);
85b7a8b3
GW		 1163
1164 /*
1165 * Register descriptor details in skb frame descriptor.
1166 */
1167 skbdesc->desc = txd;
1168 skbdesc->desc_len = TXD_DESC_SIZE;
95ea3627
ID		 1169}
1170
1171/*
1172 * TX data initialization
1173 */
f224f4ef
GW		 1174static void rt2400pci_write_beacon(struct queue_entry *entry,
1175 struct txentry_desc *txdesc)
bd88a781
ID		 1176{
1177 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
bd88a781
ID		 1178 u32 reg;
1179
1180 /*
1181 * Disable beaconing while we are reloading the beacon data,
1182 * otherwise we might be sending out invalid data.
1183 */
1184 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
bd88a781
ID		 1185 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1186 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1187
fa69560f 1188 rt2x00queue_map_txskb(entry);
bd88a781 1189
5c3b685c
GW		 1190 /*
1191 * Write the TX descriptor for the beacon.
1192 */
93331458 1193 rt2400pci_write_tx_desc(entry, txdesc);
5c3b685c
GW		 1194
1195 /*
1196 * Dump beacon to userspace through debugfs.
1197 */
1198 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
d61cb266
GW		 1199
1200 /*
1201 * Enable beaconing again.
1202 */
d61cb266
GW		 1203 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1204 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
bd88a781
ID		 1205}
1206
95ea3627
ID		 1207/*
1208 * RX control handlers
1209 */
181d6902
ID		 1210static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1211 struct rxdone_entry_desc *rxdesc)
95ea3627 1212{
ae73e58e 1213 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
b8be63ff 1214 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1215 u32 word0;
1216 u32 word2;
89993890 1217 u32 word3;
ae73e58e
ID		 1218 u32 word4;
1219 u64 tsf;
1220 u32 rx_low;
1221 u32 rx_high;
95ea3627 1222
b8be63ff
ID		 1223 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1224 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1225 rt2x00_desc_read(entry_priv->desc, 3, &word3);
ae73e58e 1226 rt2x00_desc_read(entry_priv->desc, 4, &word4);
95ea3627 1227
4150c572 1228 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1229 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1230 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1231 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1232
ae73e58e
ID		 1233 /*
1234 * We only get the lower 32bits from the timestamp,
1235 * to get the full 64bits we must complement it with
1236 * the timestamp from get_tsf().
1237 * Note that when a wraparound of the lower 32bits
1238 * has occurred between the frame arrival and the get_tsf()
1239 * call, we must decrease the higher 32bits with 1 to get
1240 * to correct value.
1241 */
37a41b4a 1242 tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
ae73e58e
ID		 1243 rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
1244 rx_high = upper_32_bits(tsf);
1245
1246 if ((u32)tsf <= rx_low)
1247 rx_high--;
1248
95ea3627
ID		 1249 /*
1250 * Obtain the status about this packet.
8ed09854
ID		 1251 * The signal is the PLCP value, and needs to be stripped
1252 * of the preamble bit (0x08).
95ea3627 1253 */
ae73e58e 1254 rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
8ed09854 1255 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1256 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1257 entry->queue->rt2x00dev->rssi_offset;
181d6902 1258 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1259
dec13b6b 1260 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1261 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1262 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1263}
1264
1265/*
1266 * Interrupt functions.
1267 */
181d6902 1268static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1269 const enum data_queue_qid queue_idx)
95ea3627 1270{
61c6e489 1271 struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
b8be63ff 1272 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1273 struct queue_entry *entry;
1274 struct txdone_entry_desc txdesc;
95ea3627 1275 u32 word;
95ea3627 1276
181d6902
ID		 1277 while (!rt2x00queue_empty(queue)) {
1278 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1279 entry_priv = entry->priv_data;
1280 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1281
1282 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1283 !rt2x00_get_field32(word, TXD_W0_VALID))
1284 break;
1285
1286 /*
1287 * Obtain the status about this packet.
1288 */
fb55f4d1
ID		 1289 txdesc.flags = 0;
1290 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1291 case 0: /* Success */
1292 case 1: /* Success with retry */
1293 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1294 break;
1295 case 2: /* Failure, excessive retries */
1296 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1297 /* Don't break, this is a failed frame! */
1298 default: /* Failure */
1299 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1300 }
181d6902 1301 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1302
e513a0b6 1303 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1304 }
95ea3627
ID		 1305}
1306
7a5a681a
HS		 1307static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
1308 struct rt2x00_field32 irq_field)
95ea3627 1309{
bcf3cfd0 1310 u32 reg;
95ea3627
ID		 1311
1312 /*
bcf3cfd0
HS		 1313 * Enable a single interrupt. The interrupt mask register
1314 * access needs locking.
95ea3627 1315 */
0aa13b2e 1316 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1317
bcf3cfd0
HS		 1318 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1319 rt2x00_set_field32(&reg, irq_field, 0);
1320 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
95ea3627 1321
0aa13b2e 1322 spin_unlock_irq(&rt2x00dev->irqmask_lock);
bcf3cfd0 1323}
95ea3627 1324
bcf3cfd0
HS		 1325static void rt2400pci_txstatus_tasklet(unsigned long data)
1326{
1327 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1328 u32 reg;
95ea3627
ID		 1329
1330 /*
bcf3cfd0 1331 * Handle all tx queues.
95ea3627 1332 */
bcf3cfd0
HS		 1333 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1334 rt2400pci_txdone(rt2x00dev, QID_AC_VO);
1335 rt2400pci_txdone(rt2x00dev, QID_AC_VI);
95ea3627
ID		 1336
1337 /*
bcf3cfd0 1338 * Enable all TXDONE interrupts again.
95ea3627 1339 */
abc11994
HS		 1340 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
1341 spin_lock_irq(&rt2x00dev->irqmask_lock);
95ea3627 1342
abc11994
HS		 1343 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1344 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
1345 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
1346 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
1347 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
bcf3cfd0 1348
abc11994
HS		 1349 spin_unlock_irq(&rt2x00dev->irqmask_lock);
1350 }
bcf3cfd0
HS		 1351}
1352
1353static void rt2400pci_tbtt_tasklet(unsigned long data)
1354{
1355 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1356 rt2x00lib_beacondone(rt2x00dev);
abc11994
HS		 1357 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1358 rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
bcf3cfd0
HS		 1359}
1360
1361static void rt2400pci_rxdone_tasklet(unsigned long data)
1362{
1363 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
16638937
HS		 1364 if (rt2x00pci_rxdone(rt2x00dev))
1365 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
abc11994 1366 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
16638937 1367 rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
95ea3627
ID		 1368}
1369
78e256c9
HS		 1370static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1371{
1372 struct rt2x00_dev *rt2x00dev = dev_instance;
bcf3cfd0 1373 u32 reg, mask;
78e256c9
HS		 1374
1375 /*
1376 * Get the interrupt sources & saved to local variable.
1377 * Write register value back to clear pending interrupts.
1378 */
1379 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1380 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1381
1382 if (!reg)
1383 return IRQ_NONE;
1384
1385 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1386 return IRQ_HANDLED;
1387
bcf3cfd0
HS		 1388 mask = reg;
1389
1390 /*
1391 * Schedule tasklets for interrupt handling.
1392 */
1393 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1394 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
1395
1396 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1397 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1398
1399 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
1400 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
1401 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
1402 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
1403 /*
1404 * Mask out all txdone interrupts.
1405 */
1406 rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
1407 rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
1408 rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
1409 }
78e256c9 1410
bcf3cfd0
HS		 1411 /*
1412 * Disable all interrupts for which a tasklet was scheduled right now,
1413 * the tasklet will reenable the appropriate interrupts.
1414 */
0aa13b2e 1415 spin_lock(&rt2x00dev->irqmask_lock);
78e256c9 1416
bcf3cfd0
HS		 1417 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1418 reg |= mask;
1419 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1420
0aa13b2e 1421 spin_unlock(&rt2x00dev->irqmask_lock);
bcf3cfd0
HS		 1422
1423
1424
1425 return IRQ_HANDLED;
78e256c9
HS		 1426}
1427
95ea3627
ID		 1428/*
1429 * Device probe functions.
1430 */
1431static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1432{
1433 struct eeprom_93cx6 eeprom;
1434 u32 reg;
1435 u16 word;
1436 u8 *mac;
1437
1438 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1439
1440 eeprom.data = rt2x00dev;
1441 eeprom.register_read = rt2400pci_eepromregister_read;
1442 eeprom.register_write = rt2400pci_eepromregister_write;
1443 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1444 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1445 eeprom.reg_data_in = 0;
1446 eeprom.reg_data_out = 0;
1447 eeprom.reg_data_clock = 0;
1448 eeprom.reg_chip_select = 0;
1449
1450 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1451 EEPROM_SIZE / sizeof(u16));
1452
1453 /*
1454 * Start validation of the data that has been read.
1455 */
1456 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1457 if (!is_valid_ether_addr(mac)) {
1458 random_ether_addr(mac);
e174961c 1459 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
95ea3627
ID		 1460 }
1461
1462 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1463 if (word == 0xffff) {
1464 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1465 return -EINVAL;
1466 }
1467
1468 return 0;
1469}
1470
1471static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1472{
1473 u32 reg;
1474 u16 value;
1475 u16 eeprom;
1476
1477 /*
1478 * Read EEPROM word for configuration.
1479 */
1480 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1481
1482 /*
1483 * Identify RF chipset.
1484 */
1485 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1486 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
49e721ec
GW		 1487 rt2x00_set_chip(rt2x00dev, RT2460, value,
1488 rt2x00_get_field32(reg, CSR0_REVISION));
95ea3627 1489
5122d898 1490 if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
95ea3627
ID		 1491 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1492 return -ENODEV;
1493 }
1494
1495 /*
1496 * Identify default antenna configuration.
1497 */
addc81bd 1498 rt2x00dev->default_ant.tx =
95ea3627 1499 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1500 rt2x00dev->default_ant.rx =
95ea3627
ID		 1501 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1502
addc81bd
ID		 1503 /*
1504 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1505 * I am not 100% sure about this, but the legacy drivers do not
1506 * indicate antenna swapping in software is required when
1507 * diversity is enabled.
1508 */
1509 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1510 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1511 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1512 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1513
95ea3627
ID		 1514 /*
1515 * Store led mode, for correct led behaviour.
1516 */
771fd565 1517#ifdef CONFIG_RT2X00_LIB_LEDS
a9450b70
ID		 1518 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1519
475433be 1520 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
3d3e451f
ID		 1521 if (value == LED_MODE_TXRX_ACTIVITY ||
1522 value == LED_MODE_DEFAULT ||
1523 value == LED_MODE_ASUS)
475433be
ID		 1524 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1525 LED_TYPE_ACTIVITY);
771fd565 1526#endif /* CONFIG_RT2X00_LIB_LEDS */
95ea3627
ID		 1527
1528 /*
1529 * Detect if this device has an hardware controlled radio.
1530 */
1531 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
7dab73b3 1532 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
95ea3627
ID		 1533
1534 /*
1535 * Check if the BBP tuning should be enabled.
1536 */
27df2a9c 1537 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
7dab73b3 1538 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
95ea3627
ID		 1539
1540 return 0;
1541}
1542
1543/*
1544 * RF value list for RF2420 & RF2421
1545 * Supports: 2.4 GHz
1546 */
8c5e7a5f 1547static const struct rf_channel rf_vals_b[] = {
95ea3627
ID		 1548 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1549 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1550 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1551 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1552 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1553 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1554 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1555 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1556 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1557 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1558 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1559 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1560 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1561 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1562};
1563
8c5e7a5f 1564static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 1565{
1566 struct hw_mode_spec *spec = &rt2x00dev->spec;
8c5e7a5f
ID		 1567 struct channel_info *info;
1568 char *tx_power;
95ea3627
ID		 1569 unsigned int i;
1570
1571 /*
1572 * Initialize all hw fields.
1573 */
566bfe5a 1574 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
4be8c387
JB		 1575 IEEE80211_HW_SIGNAL_DBM |
1576 IEEE80211_HW_SUPPORTS_PS |
1577 IEEE80211_HW_PS_NULLFUNC_STACK;
95ea3627 1578
14a3bf89 1579 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1580 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1581 rt2x00_eeprom_addr(rt2x00dev,
1582 EEPROM_MAC_ADDR_0));
1583
95ea3627
ID		 1584 /*
1585 * Initialize hw_mode information.
1586 */
31562e80
ID		 1587 spec->supported_bands = SUPPORT_BAND_2GHZ;
1588 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627 1589
8c5e7a5f
ID		 1590 spec->num_channels = ARRAY_SIZE(rf_vals_b);
1591 spec->channels = rf_vals_b;
1592
1593 /*
1594 * Create channel information array
1595 */
baeb2ffa 1596 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
8c5e7a5f
ID		 1597 if (!info)
1598 return -ENOMEM;
1599
1600 spec->channels_info = info;
1601
1602 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
8d1331b3
ID		 1603 for (i = 0; i < 14; i++) {
1604 info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
1605 info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
1606 }
8c5e7a5f
ID		 1607
1608 return 0;
95ea3627
ID		 1609}
1610
1611static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1612{
1613 int retval;
1614
1615 /*
1616 * Allocate eeprom data.
1617 */
1618 retval = rt2400pci_validate_eeprom(rt2x00dev);
1619 if (retval)
1620 return retval;
1621
1622 retval = rt2400pci_init_eeprom(rt2x00dev);
1623 if (retval)
1624 return retval;
1625
1626 /*
1627 * Initialize hw specifications.
1628 */
8c5e7a5f
ID		 1629 retval = rt2400pci_probe_hw_mode(rt2x00dev);
1630 if (retval)
1631 return retval;
95ea3627
ID		 1632
1633 /*
c4da0048 1634 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1635 */
7dab73b3
ID		 1636 __set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
1637 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1638 __set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
95ea3627
ID		 1639
1640 /*
1641 * Set the rssi offset.
1642 */
1643 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1644
1645 return 0;
1646}
1647
1648/*
1649 * IEEE80211 stack callback functions.
1650 */
8a3a3c85
EP		 1651static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1652 struct ieee80211_vif *vif, u16 queue,
95ea3627
ID		 1653 const struct ieee80211_tx_queue_params *params)
1654{
1655 struct rt2x00_dev *rt2x00dev = hw->priv;
1656
1657 /*
1658 * We don't support variating cw_min and cw_max variables
1659 * per queue. So by default we only configure the TX queue,
1660 * and ignore all other configurations.
1661 */
e100bb64 1662 if (queue != 0)
95ea3627
ID		 1663 return -EINVAL;
1664
8a3a3c85 1665 if (rt2x00mac_conf_tx(hw, vif, queue, params))
95ea3627
ID		 1666 return -EINVAL;
1667
1668 /*
1669 * Write configuration to register.
1670 */
181d6902
ID		 1671 rt2400pci_config_cw(rt2x00dev,
1672 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1673
1674 return 0;
1675}
1676
37a41b4a
EP		 1677static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
1678 struct ieee80211_vif *vif)
95ea3627
ID		 1679{
1680 struct rt2x00_dev *rt2x00dev = hw->priv;
1681 u64 tsf;
1682 u32 reg;
1683
1684 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1685 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1686 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1687 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1688
1689 return tsf;
1690}
1691
95ea3627
ID		 1692static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1693{
1694 struct rt2x00_dev *rt2x00dev = hw->priv;
1695 u32 reg;
1696
1697 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1698 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1699}
1700
1701static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1702 .tx = rt2x00mac_tx,
4150c572
JB		 1703 .start = rt2x00mac_start,
1704 .stop = rt2x00mac_stop,
95ea3627
ID		 1705 .add_interface = rt2x00mac_add_interface,
1706 .remove_interface = rt2x00mac_remove_interface,
1707 .config = rt2x00mac_config,
3a643d24 1708 .configure_filter = rt2x00mac_configure_filter,
d8147f9d
ID		 1709 .sw_scan_start = rt2x00mac_sw_scan_start,
1710 .sw_scan_complete = rt2x00mac_sw_scan_complete,
95ea3627 1711 .get_stats = rt2x00mac_get_stats,
471b3efd 1712 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627 1713 .conf_tx = rt2400pci_conf_tx,
95ea3627 1714 .get_tsf = rt2400pci_get_tsf,
95ea3627 1715 .tx_last_beacon = rt2400pci_tx_last_beacon,
e47a5cdd 1716 .rfkill_poll = rt2x00mac_rfkill_poll,
f44df18c 1717 .flush = rt2x00mac_flush,
0ed7b3c0
ID		 1718 .set_antenna = rt2x00mac_set_antenna,
1719 .get_antenna = rt2x00mac_get_antenna,
e7dee444 1720 .get_ringparam = rt2x00mac_get_ringparam,
5f0dd296 1721 .tx_frames_pending = rt2x00mac_tx_frames_pending,
95ea3627
ID		 1722};
1723
1724static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1725 .irq_handler = rt2400pci_interrupt,
bcf3cfd0
HS		 1726 .txstatus_tasklet = rt2400pci_txstatus_tasklet,
1727 .tbtt_tasklet = rt2400pci_tbtt_tasklet,
1728 .rxdone_tasklet = rt2400pci_rxdone_tasklet,
95ea3627
ID		 1729 .probe_hw = rt2400pci_probe_hw,
1730 .initialize = rt2x00pci_initialize,
1731 .uninitialize = rt2x00pci_uninitialize,
798b7adb
ID		 1732 .get_entry_state = rt2400pci_get_entry_state,
1733 .clear_entry = rt2400pci_clear_entry,
95ea3627 1734 .set_device_state = rt2400pci_set_device_state,
95ea3627 1735 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1736 .link_stats = rt2400pci_link_stats,
1737 .reset_tuner = rt2400pci_reset_tuner,
1738 .link_tuner = rt2400pci_link_tuner,
dbba306f
ID		 1739 .start_queue = rt2400pci_start_queue,
1740 .kick_queue = rt2400pci_kick_queue,
1741 .stop_queue = rt2400pci_stop_queue,
152a5992 1742 .flush_queue = rt2x00pci_flush_queue,
95ea3627 1743 .write_tx_desc = rt2400pci_write_tx_desc,
bd88a781 1744 .write_beacon = rt2400pci_write_beacon,
95ea3627 1745 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1746 .config_filter = rt2400pci_config_filter,
6bb40dd1 1747 .config_intf = rt2400pci_config_intf,
72810379 1748 .config_erp = rt2400pci_config_erp,
e4ea1c40 1749 .config_ant = rt2400pci_config_ant,
95ea3627
ID		 1750 .config = rt2400pci_config,
1751};
1752
181d6902 1753static const struct data_queue_desc rt2400pci_queue_rx = {
efd2f271 1754 .entry_num = 24,
181d6902
ID		 1755 .data_size = DATA_FRAME_SIZE,
1756 .desc_size = RXD_DESC_SIZE,
b8be63ff 1757 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1758};
1759
1760static const struct data_queue_desc rt2400pci_queue_tx = {
efd2f271 1761 .entry_num = 24,
181d6902
ID		 1762 .data_size = DATA_FRAME_SIZE,
1763 .desc_size = TXD_DESC_SIZE,
b8be63ff 1764 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1765};
1766
1767static const struct data_queue_desc rt2400pci_queue_bcn = {
efd2f271 1768 .entry_num = 1,
181d6902
ID		 1769 .data_size = MGMT_FRAME_SIZE,
1770 .desc_size = TXD_DESC_SIZE,
b8be63ff 1771 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1772};
1773
1774static const struct data_queue_desc rt2400pci_queue_atim = {
efd2f271 1775 .entry_num = 8,
181d6902
ID		 1776 .data_size = DATA_FRAME_SIZE,
1777 .desc_size = TXD_DESC_SIZE,
b8be63ff 1778 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1779};
1780
95ea3627 1781static const struct rt2x00_ops rt2400pci_ops = {
04d0362e
GW		 1782 .name = KBUILD_MODNAME,
1783 .max_sta_intf = 1,
1784 .max_ap_intf = 1,
1785 .eeprom_size = EEPROM_SIZE,
1786 .rf_size = RF_SIZE,
1787 .tx_queues = NUM_TX_QUEUES,
e6218cc4 1788 .extra_tx_headroom = 0,
04d0362e
GW		 1789 .rx = &rt2400pci_queue_rx,
1790 .tx = &rt2400pci_queue_tx,
1791 .bcn = &rt2400pci_queue_bcn,
1792 .atim = &rt2400pci_queue_atim,
1793 .lib = &rt2400pci_rt2x00_ops,
1794 .hw = &rt2400pci_mac80211_ops,
95ea3627 1795#ifdef CONFIG_RT2X00_LIB_DEBUGFS
04d0362e 1796 .debugfs = &rt2400pci_rt2x00debug,
95ea3627
ID		 1797#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1798};
1799
1800/*
1801 * RT2400pci module information.
1802 */
a3aa1884 1803static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
e01ae27f 1804 { PCI_DEVICE(0x1814, 0x0101) },
95ea3627
ID		 1805 { 0, }
1806};
1807
e01ae27f 1808
95ea3627
ID		 1809MODULE_AUTHOR(DRV_PROJECT);
1810MODULE_VERSION(DRV_VERSION);
1811MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1812MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1813MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1814MODULE_LICENSE("GPL");
1815
e01ae27f
GW		 1816static int rt2400pci_probe(struct pci_dev *pci_dev,
1817 const struct pci_device_id *id)
1818{
1819 return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
1820}
1821
95ea3627 1822static struct pci_driver rt2400pci_driver = {
2360157c 1823 .name = KBUILD_MODNAME,
95ea3627 1824 .id_table = rt2400pci_device_table,
e01ae27f 1825 .probe = rt2400pci_probe,
95ea3627
ID		 1826 .remove = __devexit_p(rt2x00pci_remove),
1827 .suspend = rt2x00pci_suspend,
1828 .resume = rt2x00pci_resume,
1829};
1830
1831static int __init rt2400pci_init(void)
1832{
1833 return pci_register_driver(&rt2400pci_driver);
1834}
1835
1836static void __exit rt2400pci_exit(void)
1837{
1838 pci_unregister_driver(&rt2400pci_driver);
1839}
1840
1841module_init(rt2400pci_init);
1842module_exit(rt2400pci_exit);
Linux kernel - Deliverables
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