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rt2x00: Driver requiring firmware should select crc algo
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 244#endif /* CONFIG_RT2400PCI_RFKILL */
245
246/*
247 * Configuration handlers.
248 */
4abee4bb
ID		 249static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
250 __le32 *mac)
95ea3627 251{
4abee4bb
ID		 252 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
253 (2 * sizeof(__le32)));
95ea3627
ID		 254}
255
4abee4bb
ID		 256static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
257 __le32 *bssid)
95ea3627 258{
4abee4bb
ID		 259 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
260 (2 * sizeof(__le32)));
95ea3627
ID		 261}
262
feb24691
ID		 263static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
264 const int tsf_sync)
95ea3627
ID		 265{
266 u32 reg;
267
268 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
269
95ea3627
ID		 270 /*
271 * Enable beacon config
272 */
273 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
274 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
a137e202 275 PREAMBLE + get_duration(IEEE80211_HEADER, 20));
95ea3627
ID		 276 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
277
278 /*
279 * Enable synchronisation.
280 */
281 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
4150c572 282 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
3867705b 283 rt2x00_set_field32(&reg, CSR14_TBCN, (tsf_sync == TSF_SYNC_BEACON));
95ea3627 284 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
feb24691 285 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
95ea3627
ID		 286 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
287}
288
5c58ee51
ID		 289static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
290 const int short_preamble,
291 const int ack_timeout,
292 const int ack_consume_time)
95ea3627 293{
5c58ee51 294 int preamble_mask;
95ea3627 295 u32 reg;
95ea3627 296
5c58ee51
ID		 297 /*
298 * When short preamble is enabled, we should set bit 0x08
299 */
300 preamble_mask = short_preamble << 3;
95ea3627
ID		 301
302 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
5c58ee51
ID		 303 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
304 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
95ea3627
ID		 305 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
306
95ea3627 307 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 308 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 309 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
310 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
311 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
312
313 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 314 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 315 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
316 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
317 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
318
319 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 320 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 321 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
322 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
323 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
324
325 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 326 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 327 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
328 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
329 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
330}
331
332static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 333 const int basic_rate_mask)
95ea3627 334{
5c58ee51 335 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 336}
337
338static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 339 struct rf_channel *rf)
95ea3627 340{
95ea3627
ID		 341 /*
342 * Switch on tuning bits.
343 */
5c58ee51
ID		 344 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
345 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 346
5c58ee51
ID		 347 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
348 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
349 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 350
351 /*
352 * RF2420 chipset don't need any additional actions.
353 */
354 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
355 return;
356
357 /*
358 * For the RT2421 chipsets we need to write an invalid
359 * reference clock rate to activate auto_tune.
360 * After that we set the value back to the correct channel.
361 */
5c58ee51 362 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 363 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 364 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 365
366 msleep(1);
367
5c58ee51
ID		 368 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
369 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
370 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 371
372 msleep(1);
373
374 /*
375 * Switch off tuning bits.
376 */
5c58ee51
ID		 377 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
378 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 379
5c58ee51
ID		 380 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
381 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 382
383 /*
384 * Clear false CRC during channel switch.
385 */
5c58ee51 386 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 387}
388
389static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
390{
391 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
392}
393
394static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 395 struct antenna_setup *ant)
95ea3627
ID		 396{
397 u8 r1;
398 u8 r4;
399
400 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
401 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
402
403 /*
404 * Configure the TX antenna.
405 */
addc81bd 406 switch (ant->tx) {
95ea3627
ID		 407 case ANTENNA_HW_DIVERSITY:
408 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
409 break;
410 case ANTENNA_A:
411 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
412 break;
39e75857
ID		 413 case ANTENNA_SW_DIVERSITY:
414 /*
415 * NOTE: We should never come here because rt2x00lib is
416 * supposed to catch this and send us the correct antenna
417 * explicitely. However we are nog going to bug about this.
418 * Instead, just default to antenna B.
419 */
95ea3627
ID		 420 case ANTENNA_B:
421 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
422 break;
423 }
424
425 /*
426 * Configure the RX antenna.
427 */
addc81bd 428 switch (ant->rx) {
95ea3627
ID		 429 case ANTENNA_HW_DIVERSITY:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
431 break;
432 case ANTENNA_A:
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
434 break;
39e75857
ID		 435 case ANTENNA_SW_DIVERSITY:
436 /*
437 * NOTE: We should never come here because rt2x00lib is
438 * supposed to catch this and send us the correct antenna
439 * explicitely. However we are nog going to bug about this.
440 * Instead, just default to antenna B.
441 */
95ea3627
ID		 442 case ANTENNA_B:
443 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
444 break;
445 }
446
447 rt2400pci_bbp_write(rt2x00dev, 4, r4);
448 rt2400pci_bbp_write(rt2x00dev, 1, r1);
449}
450
451static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 452 struct rt2x00lib_conf *libconf)
95ea3627
ID		 453{
454 u32 reg;
455
456 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 457 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 458 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
459
460 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 461 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
462 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 463 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
464
465 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 466 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
467 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 468 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
469
470 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
471 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
472 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
473 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
474
475 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 476 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
477 libconf->conf->beacon_int * 16);
478 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
479 libconf->conf->beacon_int * 16);
95ea3627
ID		 480 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
481}
482
483static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
484 const unsigned int flags,
5c58ee51 485 struct rt2x00lib_conf *libconf)
95ea3627 486{
95ea3627 487 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 488 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 489 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 490 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 491 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 492 rt2400pci_config_txpower(rt2x00dev,
493 libconf->conf->power_level);
95ea3627 494 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 495 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 496 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 497 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 498}
499
500static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 501 const int cw_min, const int cw_max)
95ea3627
ID		 502{
503 u32 reg;
504
505 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 506 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
507 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 508 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
509}
510
511/*
512 * LED functions.
513 */
514static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
515{
516 u32 reg;
517
518 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
519
520 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
521 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
ddc827f9
ID		 522 rt2x00_set_field32(&reg, LEDCSR_LINK,
523 (rt2x00dev->led_mode != LED_MODE_ASUS));
524 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY,
525 (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
95ea3627
ID		 526 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
527}
528
529static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
530{
531 u32 reg;
532
533 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
534 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
535 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
536 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
537}
538
539/*
540 * Link tuning
541 */
ebcf26da
ID		 542static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
543 struct link_qual *qual)
95ea3627
ID		 544{
545 u32 reg;
546 u8 bbp;
547
548 /*
549 * Update FCS error count from register.
550 */
551 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 552 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 553
554 /*
555 * Update False CCA count from register.
556 */
557 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 558 qual->false_cca = bbp;
95ea3627
ID		 559}
560
561static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
562{
563 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
564 rt2x00dev->link.vgc_level = 0x08;
565}
566
567static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
568{
569 u8 reg;
570
571 /*
572 * The link tuner should not run longer then 60 seconds,
573 * and should run once every 2 seconds.
574 */
575 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
576 return;
577
578 /*
579 * Base r13 link tuning on the false cca count.
580 */
581 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
582
ebcf26da 583 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 584 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
585 rt2x00dev->link.vgc_level = reg;
ebcf26da 586 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 587 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
588 rt2x00dev->link.vgc_level = reg;
589 }
590}
591
592/*
593 * Initialization functions.
594 */
837e7f24 595static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 596 struct queue_entry *entry)
95ea3627 597{
181d6902 598 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 599 u32 word;
600
181d6902
ID		 601 rt2x00_desc_read(priv_rx->desc, 2, &word);
602 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->queue->data_size);
603 rt2x00_desc_write(priv_rx->desc, 2, word);
95ea3627 604
181d6902
ID		 605 rt2x00_desc_read(priv_rx->desc, 1, &word);
606 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
607 rt2x00_desc_write(priv_rx->desc, 1, word);
95ea3627 608
181d6902 609 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 610 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 611 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 612}
613
837e7f24 614static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 615 struct queue_entry *entry)
95ea3627 616{
181d6902 617 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 618 u32 word;
619
181d6902
ID		 620 rt2x00_desc_read(priv_tx->desc, 1, &word);
621 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
622 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 623
181d6902
ID		 624 rt2x00_desc_read(priv_tx->desc, 2, &word);
625 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
626 entry->queue->data_size);
627 rt2x00_desc_write(priv_tx->desc, 2, word);
95ea3627 628
181d6902 629 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 630 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
631 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 632 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 633}
634
181d6902 635static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 636{
181d6902
ID		 637 struct queue_entry_priv_pci_rx *priv_rx;
638 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 639 u32 reg;
640
95ea3627
ID		 641 /*
642 * Initialize registers.
643 */
644 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 645 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
646 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
647 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
648 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 649 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
650
181d6902 651 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 652 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
181d6902 653 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 654 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
655
181d6902 656 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 657 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
181d6902 658 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 659 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
660
181d6902 661 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 662 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
181d6902 663 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 664 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
665
181d6902 666 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 667 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
181d6902 668 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 669 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
670
671 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
672 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 673 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 674 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
675
181d6902 676 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 677 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
181d6902 678 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 679 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
680
681 return 0;
682}
683
684static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
685{
686 u32 reg;
687
688 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
689 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
690 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
691 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
692
693 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
694 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
695 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
696 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
697 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
698
699 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
700 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
701 (rt2x00dev->rx->data_size / 128));
702 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
703
704 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
705
706 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
707 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
708 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
709 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
710 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
711 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
712
713 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
714 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
715 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
716 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
717 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
718 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
719 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
720 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
721
722 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
723
724 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
725 return -EBUSY;
726
727 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
728 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
729
730 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
731 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
732 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
733
734 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
735 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
736 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
737 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
738 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
739 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
740
741 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
742 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
743 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
744 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
745 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
746
747 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
748 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
749 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
750 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
751
752 /*
753 * We must clear the FCS and FIFO error count.
754 * These registers are cleared on read,
755 * so we may pass a useless variable to store the value.
756 */
757 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
758 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
759
760 return 0;
761}
762
763static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
764{
765 unsigned int i;
766 u16 eeprom;
767 u8 reg_id;
768 u8 value;
769
770 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
771 rt2400pci_bbp_read(rt2x00dev, 0, &value);
772 if ((value != 0xff) && (value != 0x00))
773 goto continue_csr_init;
774 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
775 udelay(REGISTER_BUSY_DELAY);
776 }
777
778 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
779 return -EACCES;
780
781continue_csr_init:
782 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
783 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
784 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
785 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
786 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
787 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
788 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
789 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
790 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
791 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
792 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
793 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
794 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
795 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
796
797 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
798 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
799 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
800
801 if (eeprom != 0xffff && eeprom != 0x0000) {
802 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
803 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
804 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
805 reg_id, value);
806 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
807 }
808 }
809 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
810
811 return 0;
812}
813
814/*
815 * Device state switch handlers.
816 */
817static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
818 enum dev_state state)
819{
820 u32 reg;
821
822 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
823 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
824 state == STATE_RADIO_RX_OFF);
825 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
826}
827
828static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
829 enum dev_state state)
830{
831 int mask = (state == STATE_RADIO_IRQ_OFF);
832 u32 reg;
833
834 /*
835 * When interrupts are being enabled, the interrupt registers
836 * should clear the register to assure a clean state.
837 */
838 if (state == STATE_RADIO_IRQ_ON) {
839 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
840 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
841 }
842
843 /*
844 * Only toggle the interrupts bits we are going to use.
845 * Non-checked interrupt bits are disabled by default.
846 */
847 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
848 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
849 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
850 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
851 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
852 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
853 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
854}
855
856static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
857{
858 /*
859 * Initialize all registers.
860 */
181d6902 861 if (rt2400pci_init_queues(rt2x00dev) ||
95ea3627
ID		 862 rt2400pci_init_registers(rt2x00dev) ||
863 rt2400pci_init_bbp(rt2x00dev)) {
864 ERROR(rt2x00dev, "Register initialization failed.\n");
865 return -EIO;
866 }
867
868 /*
869 * Enable interrupts.
870 */
871 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
872
873 /*
874 * Enable LED
875 */
876 rt2400pci_enable_led(rt2x00dev);
877
878 return 0;
879}
880
881static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
882{
883 u32 reg;
884
885 /*
886 * Disable LED
887 */
888 rt2400pci_disable_led(rt2x00dev);
889
890 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
891
892 /*
893 * Disable synchronisation.
894 */
895 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
896
897 /*
898 * Cancel RX and TX.
899 */
900 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
901 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
902 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
903
904 /*
905 * Disable interrupts.
906 */
907 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
908}
909
910static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
911 enum dev_state state)
912{
913 u32 reg;
914 unsigned int i;
915 char put_to_sleep;
916 char bbp_state;
917 char rf_state;
918
919 put_to_sleep = (state != STATE_AWAKE);
920
921 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
922 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
923 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
924 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
925 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
926 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
927
928 /*
929 * Device is not guaranteed to be in the requested state yet.
930 * We must wait until the register indicates that the
931 * device has entered the correct state.
932 */
933 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
934 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
935 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
936 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
937 if (bbp_state == state && rf_state == state)
938 return 0;
939 msleep(10);
940 }
941
942 NOTICE(rt2x00dev, "Device failed to enter state %d, "
943 "current device state: bbp %d and rf %d.\n",
944 state, bbp_state, rf_state);
945
946 return -EBUSY;
947}
948
949static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
950 enum dev_state state)
951{
952 int retval = 0;
953
954 switch (state) {
955 case STATE_RADIO_ON:
956 retval = rt2400pci_enable_radio(rt2x00dev);
957 break;
958 case STATE_RADIO_OFF:
959 rt2400pci_disable_radio(rt2x00dev);
960 break;
961 case STATE_RADIO_RX_ON:
61667d8d
ID		 962 case STATE_RADIO_RX_ON_LINK:
963 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
964 break;
95ea3627 965 case STATE_RADIO_RX_OFF:
61667d8d
ID		 966 case STATE_RADIO_RX_OFF_LINK:
967 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 968 break;
969 case STATE_DEEP_SLEEP:
970 case STATE_SLEEP:
971 case STATE_STANDBY:
972 case STATE_AWAKE:
973 retval = rt2400pci_set_state(rt2x00dev, state);
974 break;
975 default:
976 retval = -ENOTSUPP;
977 break;
978 }
979
980 return retval;
981}
982
983/*
984 * TX descriptor initialization
985 */
986static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 987 struct sk_buff *skb,
181d6902 988 struct txentry_desc *txdesc,
95ea3627
ID		 989 struct ieee80211_tx_control *control)
990{
181d6902 991 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 992 __le32 *txd = skbdesc->desc;
95ea3627 993 u32 word;
95ea3627
ID		 994
995 /*
996 * Start writing the descriptor words.
997 */
998 rt2x00_desc_read(txd, 2, &word);
dd3193e1 999 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 1000 rt2x00_desc_write(txd, 2, word);
1001
1002 rt2x00_desc_read(txd, 3, &word);
181d6902 1003 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1004 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1005 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1006 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1007 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1008 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1009 rt2x00_desc_write(txd, 3, word);
1010
1011 rt2x00_desc_read(txd, 4, &word);
181d6902 1012 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1013 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1014 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1015 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1016 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1017 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1018 rt2x00_desc_write(txd, 4, word);
1019
1020 rt2x00_desc_read(txd, 0, &word);
1021 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1022 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1023 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1024 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1025 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1026 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1027 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1028 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1029 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1030 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1031 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1032 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1033 !!(control->flags &
1034 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1035 rt2x00_desc_write(txd, 0, word);
1036}
1037
1038/*
1039 * TX data initialization
1040 */
1041static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1042 unsigned int queue)
1043{
1044 u32 reg;
1045
1046 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1047 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1048 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1049 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1050 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1051 }
1052 return;
1053 }
1054
1055 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1056 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1057 (queue == IEEE80211_TX_QUEUE_DATA0));
1058 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1059 (queue == IEEE80211_TX_QUEUE_DATA1));
1060 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1061 (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
95ea3627
ID		 1062 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1063}
1064
1065/*
1066 * RX control handlers
1067 */
181d6902
ID		 1068static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1069 struct rxdone_entry_desc *rxdesc)
95ea3627 1070{
181d6902 1071 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1072 u32 word0;
1073 u32 word2;
1074
181d6902
ID		 1075 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1076 rt2x00_desc_read(priv_rx->desc, 2, &word2);
95ea3627 1077
181d6902 1078 rxdesc->flags = 0;
4150c572 1079 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1080 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1081 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1082 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1083
1084 /*
1085 * Obtain the status about this packet.
1086 */
181d6902
ID		 1087 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1088 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1089 entry->queue->rt2x00dev->rssi_offset;
1090 rxdesc->ofdm = 0;
1091 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1092 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1093}
1094
1095/*
1096 * Interrupt functions.
1097 */
181d6902
ID		 1098static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1099 const enum ieee80211_tx_queue queue_idx)
95ea3627 1100{
181d6902
ID		 1101 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1102 struct queue_entry_priv_pci_tx *priv_tx;
1103 struct queue_entry *entry;
1104 struct txdone_entry_desc txdesc;
95ea3627 1105 u32 word;
95ea3627 1106
181d6902
ID		 1107 while (!rt2x00queue_empty(queue)) {
1108 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1109 priv_tx = entry->priv_data;
1110 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1111
1112 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1113 !rt2x00_get_field32(word, TXD_W0_VALID))
1114 break;
1115
1116 /*
1117 * Obtain the status about this packet.
1118 */
181d6902
ID		 1119 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1120 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1121
181d6902 1122 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1123 }
95ea3627
ID		 1124}
1125
1126static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1127{
1128 struct rt2x00_dev *rt2x00dev = dev_instance;
1129 u32 reg;
1130
1131 /*
1132 * Get the interrupt sources & saved to local variable.
1133 * Write register value back to clear pending interrupts.
1134 */
1135 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1136 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1137
1138 if (!reg)
1139 return IRQ_NONE;
1140
1141 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1142 return IRQ_HANDLED;
1143
1144 /*
1145 * Handle interrupts, walk through all bits
1146 * and run the tasks, the bits are checked in order of
1147 * priority.
1148 */
1149
1150 /*
1151 * 1 - Beacon timer expired interrupt.
1152 */
1153 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1154 rt2x00lib_beacondone(rt2x00dev);
1155
1156 /*
1157 * 2 - Rx ring done interrupt.
1158 */
1159 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1160 rt2x00pci_rxdone(rt2x00dev);
1161
1162 /*
1163 * 3 - Atim ring transmit done interrupt.
1164 */
1165 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1166 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1167
1168 /*
1169 * 4 - Priority ring transmit done interrupt.
1170 */
1171 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1172 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1173
1174 /*
1175 * 5 - Tx ring transmit done interrupt.
1176 */
1177 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1178 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1179
1180 return IRQ_HANDLED;
1181}
1182
1183/*
1184 * Device probe functions.
1185 */
1186static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1187{
1188 struct eeprom_93cx6 eeprom;
1189 u32 reg;
1190 u16 word;
1191 u8 *mac;
1192
1193 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1194
1195 eeprom.data = rt2x00dev;
1196 eeprom.register_read = rt2400pci_eepromregister_read;
1197 eeprom.register_write = rt2400pci_eepromregister_write;
1198 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1199 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1200 eeprom.reg_data_in = 0;
1201 eeprom.reg_data_out = 0;
1202 eeprom.reg_data_clock = 0;
1203 eeprom.reg_chip_select = 0;
1204
1205 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1206 EEPROM_SIZE / sizeof(u16));
1207
1208 /*
1209 * Start validation of the data that has been read.
1210 */
1211 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1212 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1213 DECLARE_MAC_BUF(macbuf);
1214
95ea3627 1215 random_ether_addr(mac);
0795af57 1216 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1217 }
1218
1219 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1220 if (word == 0xffff) {
1221 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1222 return -EINVAL;
1223 }
1224
1225 return 0;
1226}
1227
1228static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1229{
1230 u32 reg;
1231 u16 value;
1232 u16 eeprom;
1233
1234 /*
1235 * Read EEPROM word for configuration.
1236 */
1237 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1238
1239 /*
1240 * Identify RF chipset.
1241 */
1242 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1243 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1244 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1245
1246 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1247 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1248 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1249 return -ENODEV;
1250 }
1251
1252 /*
1253 * Identify default antenna configuration.
1254 */
addc81bd 1255 rt2x00dev->default_ant.tx =
95ea3627 1256 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1257 rt2x00dev->default_ant.rx =
95ea3627
ID		 1258 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1259
addc81bd
ID		 1260 /*
1261 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1262 * I am not 100% sure about this, but the legacy drivers do not
1263 * indicate antenna swapping in software is required when
1264 * diversity is enabled.
1265 */
1266 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1267 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1268 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1269 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1270
95ea3627
ID		 1271 /*
1272 * Store led mode, for correct led behaviour.
1273 */
1274 rt2x00dev->led_mode =
1275 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1276
1277 /*
1278 * Detect if this device has an hardware controlled radio.
1279 */
81873e9c 1280#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1281 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1282 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1283#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1284
1285 /*
1286 * Check if the BBP tuning should be enabled.
1287 */
1288 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1289 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1290
1291 return 0;
1292}
1293
1294/*
1295 * RF value list for RF2420 & RF2421
1296 * Supports: 2.4 GHz
1297 */
1298static const struct rf_channel rf_vals_bg[] = {
1299 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1300 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1301 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1302 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1303 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1304 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1305 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1306 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1307 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1308 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1309 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1310 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1311 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1312 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1313};
1314
1315static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1316{
1317 struct hw_mode_spec *spec = &rt2x00dev->spec;
1318 u8 *txpower;
1319 unsigned int i;
1320
1321 /*
1322 * Initialize all hw fields.
1323 */
4150c572 1324 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1325 rt2x00dev->hw->extra_tx_headroom = 0;
1326 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1327 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1328 rt2x00dev->hw->queues = 2;
1329
1330 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1331 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1332 rt2x00_eeprom_addr(rt2x00dev,
1333 EEPROM_MAC_ADDR_0));
1334
1335 /*
1336 * Convert tx_power array in eeprom.
1337 */
1338 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1339 for (i = 0; i < 14; i++)
1340 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1341
1342 /*
1343 * Initialize hw_mode information.
1344 */
1345 spec->num_modes = 1;
1346 spec->num_rates = 4;
1347 spec->tx_power_a = NULL;
1348 spec->tx_power_bg = txpower;
1349 spec->tx_power_default = DEFAULT_TXPOWER;
1350
1351 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1352 spec->channels = rf_vals_bg;
1353}
1354
1355static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1356{
1357 int retval;
1358
1359 /*
1360 * Allocate eeprom data.
1361 */
1362 retval = rt2400pci_validate_eeprom(rt2x00dev);
1363 if (retval)
1364 return retval;
1365
1366 retval = rt2400pci_init_eeprom(rt2x00dev);
1367 if (retval)
1368 return retval;
1369
1370 /*
1371 * Initialize hw specifications.
1372 */
1373 rt2400pci_probe_hw_mode(rt2x00dev);
1374
1375 /*
181d6902 1376 * This device requires the atim queue
95ea3627 1377 */
181d6902 1378 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1379
1380 /*
1381 * Set the rssi offset.
1382 */
1383 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1384
1385 return 0;
1386}
1387
1388/*
1389 * IEEE80211 stack callback functions.
1390 */
4150c572
JB		 1391static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1392 unsigned int changed_flags,
1393 unsigned int *total_flags,
1394 int mc_count,
1395 struct dev_addr_list *mc_list)
1396{
1397 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1398 u32 reg;
1399
1400 /*
1401 * Mask off any flags we are going to ignore from
1402 * the total_flags field.
1403 */
1404 *total_flags &=
1405 FIF_ALLMULTI |
1406 FIF_FCSFAIL |
1407 FIF_PLCPFAIL |
1408 FIF_CONTROL |
1409 FIF_OTHER_BSS |
1410 FIF_PROMISC_IN_BSS;
1411
1412 /*
1413 * Apply some rules to the filters:
1414 * - Some filters imply different filters to be set.
1415 * - Some things we can't filter out at all.
4150c572
JB		 1416 */
1417 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1418 if (*total_flags & FIF_OTHER_BSS ||
1419 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1420 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1421
1422 /*
1423 * Check if there is any work left for us.
1424 */
3c4f2085 1425 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1426 return;
3c4f2085 1427 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1428
1429 /*
1430 * Start configuration steps.
1431 * Note that the version error will always be dropped
1432 * since there is no filter for it at this time.
1433 */
1434 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1435 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1436 !(*total_flags & FIF_FCSFAIL));
1437 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1438 !(*total_flags & FIF_PLCPFAIL));
1439 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1440 !(*total_flags & FIF_CONTROL));
1441 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1442 !(*total_flags & FIF_PROMISC_IN_BSS));
1443 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1444 !(*total_flags & FIF_PROMISC_IN_BSS));
1445 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1446 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1447}
1448
95ea3627
ID		 1449static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1450 u32 short_retry, u32 long_retry)
1451{
1452 struct rt2x00_dev *rt2x00dev = hw->priv;
1453 u32 reg;
1454
1455 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1456 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1457 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1458 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1459
1460 return 0;
1461}
1462
1463static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1464 int queue,
1465 const struct ieee80211_tx_queue_params *params)
1466{
1467 struct rt2x00_dev *rt2x00dev = hw->priv;
1468
1469 /*
1470 * We don't support variating cw_min and cw_max variables
1471 * per queue. So by default we only configure the TX queue,
1472 * and ignore all other configurations.
1473 */
1474 if (queue != IEEE80211_TX_QUEUE_DATA0)
1475 return -EINVAL;
1476
1477 if (rt2x00mac_conf_tx(hw, queue, params))
1478 return -EINVAL;
1479
1480 /*
1481 * Write configuration to register.
1482 */
181d6902
ID		 1483 rt2400pci_config_cw(rt2x00dev,
1484 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1485
1486 return 0;
1487}
1488
1489static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1490{
1491 struct rt2x00_dev *rt2x00dev = hw->priv;
1492 u64 tsf;
1493 u32 reg;
1494
1495 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1496 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1497 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1498 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1499
1500 return tsf;
1501}
1502
1503static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1504{
1505 struct rt2x00_dev *rt2x00dev = hw->priv;
1506
1507 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1508 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1509}
1510
1511static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1512{
1513 struct rt2x00_dev *rt2x00dev = hw->priv;
1514 u32 reg;
1515
1516 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1517 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1518}
1519
1520static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1521 .tx = rt2x00mac_tx,
4150c572
JB		 1522 .start = rt2x00mac_start,
1523 .stop = rt2x00mac_stop,
95ea3627
ID		 1524 .add_interface = rt2x00mac_add_interface,
1525 .remove_interface = rt2x00mac_remove_interface,
1526 .config = rt2x00mac_config,
1527 .config_interface = rt2x00mac_config_interface,
4150c572 1528 .configure_filter = rt2400pci_configure_filter,
95ea3627
ID		 1529 .get_stats = rt2x00mac_get_stats,
1530 .set_retry_limit = rt2400pci_set_retry_limit,
471b3efd 1531 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1532 .conf_tx = rt2400pci_conf_tx,
1533 .get_tx_stats = rt2x00mac_get_tx_stats,
1534 .get_tsf = rt2400pci_get_tsf,
1535 .reset_tsf = rt2400pci_reset_tsf,
1536 .beacon_update = rt2x00pci_beacon_update,
1537 .tx_last_beacon = rt2400pci_tx_last_beacon,
1538};
1539
1540static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1541 .irq_handler = rt2400pci_interrupt,
1542 .probe_hw = rt2400pci_probe_hw,
1543 .initialize = rt2x00pci_initialize,
1544 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1545 .init_rxentry = rt2400pci_init_rxentry,
1546 .init_txentry = rt2400pci_init_txentry,
95ea3627 1547 .set_device_state = rt2400pci_set_device_state,
95ea3627 1548 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1549 .link_stats = rt2400pci_link_stats,
1550 .reset_tuner = rt2400pci_reset_tuner,
1551 .link_tuner = rt2400pci_link_tuner,
1552 .write_tx_desc = rt2400pci_write_tx_desc,
1553 .write_tx_data = rt2x00pci_write_tx_data,
1554 .kick_tx_queue = rt2400pci_kick_tx_queue,
1555 .fill_rxdone = rt2400pci_fill_rxdone,
1556 .config_mac_addr = rt2400pci_config_mac_addr,
1557 .config_bssid = rt2400pci_config_bssid,
95ea3627 1558 .config_type = rt2400pci_config_type,
5c58ee51 1559 .config_preamble = rt2400pci_config_preamble,
95ea3627
ID		 1560 .config = rt2400pci_config,
1561};
1562
181d6902
ID		 1563static const struct data_queue_desc rt2400pci_queue_rx = {
1564 .entry_num = RX_ENTRIES,
1565 .data_size = DATA_FRAME_SIZE,
1566 .desc_size = RXD_DESC_SIZE,
1567 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1568};
1569
1570static const struct data_queue_desc rt2400pci_queue_tx = {
1571 .entry_num = TX_ENTRIES,
1572 .data_size = DATA_FRAME_SIZE,
1573 .desc_size = TXD_DESC_SIZE,
1574 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1575};
1576
1577static const struct data_queue_desc rt2400pci_queue_bcn = {
1578 .entry_num = BEACON_ENTRIES,
1579 .data_size = MGMT_FRAME_SIZE,
1580 .desc_size = TXD_DESC_SIZE,
1581 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1582};
1583
1584static const struct data_queue_desc rt2400pci_queue_atim = {
1585 .entry_num = ATIM_ENTRIES,
1586 .data_size = DATA_FRAME_SIZE,
1587 .desc_size = TXD_DESC_SIZE,
1588 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1589};
1590
95ea3627 1591static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1592 .name = KBUILD_MODNAME,
95ea3627
ID		 1593 .eeprom_size = EEPROM_SIZE,
1594 .rf_size = RF_SIZE,
181d6902
ID		 1595 .rx = &rt2400pci_queue_rx,
1596 .tx = &rt2400pci_queue_tx,
1597 .bcn = &rt2400pci_queue_bcn,
1598 .atim = &rt2400pci_queue_atim,
95ea3627
ID		 1599 .lib = &rt2400pci_rt2x00_ops,
1600 .hw = &rt2400pci_mac80211_ops,
1601#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1602 .debugfs = &rt2400pci_rt2x00debug,
1603#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1604};
1605
1606/*
1607 * RT2400pci module information.
1608 */
1609static struct pci_device_id rt2400pci_device_table[] = {
1610 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1611 { 0, }
1612};
1613
1614MODULE_AUTHOR(DRV_PROJECT);
1615MODULE_VERSION(DRV_VERSION);
1616MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1617MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1618MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1619MODULE_LICENSE("GPL");
1620
1621static struct pci_driver rt2400pci_driver = {
2360157c 1622 .name = KBUILD_MODNAME,
95ea3627
ID		 1623 .id_table = rt2400pci_device_table,
1624 .probe = rt2x00pci_probe,
1625 .remove = __devexit_p(rt2x00pci_remove),
1626 .suspend = rt2x00pci_suspend,
1627 .resume = rt2x00pci_resume,
1628};
1629
1630static int __init rt2400pci_init(void)
1631{
1632 return pci_register_driver(&rt2400pci_driver);
1633}
1634
1635static void __exit rt2400pci_exit(void)
1636{
1637 pci_unregister_driver(&rt2400pci_driver);
1638}
1639
1640module_init(rt2400pci_init);
1641module_exit(rt2400pci_exit);
Linux kernel - Deliverables
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