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rt2x00: Make use of MAC80211_LED_TRIGGERS
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 244#endif /* CONFIG_RT2400PCI_RFKILL */
245
a9450b70
ID		 246#ifdef CONFIG_RT2400PCI_LEDS
247static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
256
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265}
266#else
267#define rt2400pci_led_brightness NULL
268#endif /* CONFIG_RT2400PCI_LEDS */
269
95ea3627
ID		 270/*
271 * Configuration handlers.
272 */
6bb40dd1
ID		 273static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
95ea3627 277{
6bb40dd1
ID		 278 unsigned int bcn_preload;
279 u32 reg;
95ea3627 280
6bb40dd1
ID		 281 if (flags & CONFIG_UPDATE_TYPE) {
282 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
95ea3627 283
6bb40dd1
ID		 284 /*
285 * Enable beacon config
286 */
287 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
288 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
289 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
290 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 291
6bb40dd1
ID		 292 /*
293 * Enable synchronisation.
294 */
295 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
296 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
297 rt2x00_set_field32(&reg, CSR14_TBCN,
298 (conf->sync == TSF_SYNC_BEACON));
299 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
300 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
301 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
302 }
95ea3627 303
6bb40dd1
ID		 304 if (flags & CONFIG_UPDATE_MAC)
305 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
306 conf->mac, sizeof(conf->mac));
95ea3627 307
6bb40dd1
ID		 308 if (flags & CONFIG_UPDATE_BSSID)
309 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
310 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 311}
312
6bb40dd1
ID		 313static int rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
314 const int short_preamble,
315 const int ack_timeout,
316 const int ack_consume_time)
95ea3627 317{
5c58ee51 318 int preamble_mask;
95ea3627 319 u32 reg;
95ea3627 320
5c58ee51
ID		 321 /*
322 * When short preamble is enabled, we should set bit 0x08
323 */
324 preamble_mask = short_preamble << 3;
95ea3627
ID		 325
326 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
5c58ee51
ID		 327 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
328 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
95ea3627
ID		 329 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
330
95ea3627 331 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 332 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 333 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
334 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
335 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
336
337 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 338 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 339 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
340 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
341 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
342
343 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 344 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 345 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
346 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
347 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
348
349 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 350 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 351 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
352 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
353 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
6bb40dd1
ID		 354
355 return 0;
95ea3627
ID		 356}
357
358static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 359 const int basic_rate_mask)
95ea3627 360{
5c58ee51 361 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 362}
363
364static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 365 struct rf_channel *rf)
95ea3627 366{
95ea3627
ID		 367 /*
368 * Switch on tuning bits.
369 */
5c58ee51
ID		 370 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
371 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 372
5c58ee51
ID		 373 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
374 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
375 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 376
377 /*
378 * RF2420 chipset don't need any additional actions.
379 */
380 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
381 return;
382
383 /*
384 * For the RT2421 chipsets we need to write an invalid
385 * reference clock rate to activate auto_tune.
386 * After that we set the value back to the correct channel.
387 */
5c58ee51 388 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 389 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 390 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 391
392 msleep(1);
393
5c58ee51
ID		 394 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
395 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
396 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 397
398 msleep(1);
399
400 /*
401 * Switch off tuning bits.
402 */
5c58ee51
ID		 403 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
404 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 405
5c58ee51
ID		 406 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
407 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 408
409 /*
410 * Clear false CRC during channel switch.
411 */
5c58ee51 412 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 413}
414
415static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
416{
417 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
418}
419
420static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 421 struct antenna_setup *ant)
95ea3627
ID		 422{
423 u8 r1;
424 u8 r4;
425
426 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
427 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
428
429 /*
430 * Configure the TX antenna.
431 */
addc81bd 432 switch (ant->tx) {
95ea3627
ID		 433 case ANTENNA_HW_DIVERSITY:
434 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
435 break;
436 case ANTENNA_A:
437 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
438 break;
39e75857
ID		 439 case ANTENNA_SW_DIVERSITY:
440 /*
441 * NOTE: We should never come here because rt2x00lib is
442 * supposed to catch this and send us the correct antenna
443 * explicitely. However we are nog going to bug about this.
444 * Instead, just default to antenna B.
445 */
95ea3627
ID		 446 case ANTENNA_B:
447 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
448 break;
449 }
450
451 /*
452 * Configure the RX antenna.
453 */
addc81bd 454 switch (ant->rx) {
95ea3627
ID		 455 case ANTENNA_HW_DIVERSITY:
456 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
457 break;
458 case ANTENNA_A:
459 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
460 break;
39e75857
ID		 461 case ANTENNA_SW_DIVERSITY:
462 /*
463 * NOTE: We should never come here because rt2x00lib is
464 * supposed to catch this and send us the correct antenna
465 * explicitely. However we are nog going to bug about this.
466 * Instead, just default to antenna B.
467 */
95ea3627
ID		 468 case ANTENNA_B:
469 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
470 break;
471 }
472
473 rt2400pci_bbp_write(rt2x00dev, 4, r4);
474 rt2400pci_bbp_write(rt2x00dev, 1, r1);
475}
476
477static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 478 struct rt2x00lib_conf *libconf)
95ea3627
ID		 479{
480 u32 reg;
481
482 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 483 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 484 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
485
486 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 487 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
488 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 489 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
490
491 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 492 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
493 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 494 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
495
496 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
497 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
498 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
499 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
500
501 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 502 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
503 libconf->conf->beacon_int * 16);
504 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
505 libconf->conf->beacon_int * 16);
95ea3627
ID		 506 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
507}
508
509static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 510 struct rt2x00lib_conf *libconf,
511 const unsigned int flags)
95ea3627 512{
95ea3627 513 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 514 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 515 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 516 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 517 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 518 rt2400pci_config_txpower(rt2x00dev,
519 libconf->conf->power_level);
95ea3627 520 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 521 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 522 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 523 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 524}
525
526static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 527 const int cw_min, const int cw_max)
95ea3627
ID		 528{
529 u32 reg;
530
531 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 532 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
533 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 534 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
535}
536
95ea3627
ID		 537/*
538 * Link tuning
539 */
ebcf26da
ID		 540static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
541 struct link_qual *qual)
95ea3627
ID		 542{
543 u32 reg;
544 u8 bbp;
545
546 /*
547 * Update FCS error count from register.
548 */
549 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 550 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 551
552 /*
553 * Update False CCA count from register.
554 */
555 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 556 qual->false_cca = bbp;
95ea3627
ID		 557}
558
559static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
560{
561 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
562 rt2x00dev->link.vgc_level = 0x08;
563}
564
565static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
566{
567 u8 reg;
568
569 /*
570 * The link tuner should not run longer then 60 seconds,
571 * and should run once every 2 seconds.
572 */
573 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
574 return;
575
576 /*
577 * Base r13 link tuning on the false cca count.
578 */
579 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
580
ebcf26da 581 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 582 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
583 rt2x00dev->link.vgc_level = reg;
ebcf26da 584 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 585 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
586 rt2x00dev->link.vgc_level = reg;
587 }
588}
589
590/*
591 * Initialization functions.
592 */
837e7f24 593static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 594 struct queue_entry *entry)
95ea3627 595{
181d6902 596 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 597 u32 word;
598
181d6902
ID		 599 rt2x00_desc_read(priv_rx->desc, 2, &word);
600 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->queue->data_size);
601 rt2x00_desc_write(priv_rx->desc, 2, word);
95ea3627 602
181d6902
ID		 603 rt2x00_desc_read(priv_rx->desc, 1, &word);
604 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->dma);
605 rt2x00_desc_write(priv_rx->desc, 1, word);
95ea3627 606
181d6902 607 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 608 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 609 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 610}
611
837e7f24 612static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 613 struct queue_entry *entry)
95ea3627 614{
181d6902 615 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 616 u32 word;
617
181d6902
ID		 618 rt2x00_desc_read(priv_tx->desc, 1, &word);
619 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->dma);
620 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 621
181d6902
ID		 622 rt2x00_desc_read(priv_tx->desc, 2, &word);
623 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
624 entry->queue->data_size);
625 rt2x00_desc_write(priv_tx->desc, 2, word);
95ea3627 626
181d6902 627 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 628 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
629 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 630 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 631}
632
181d6902 633static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 634{
181d6902
ID		 635 struct queue_entry_priv_pci_rx *priv_rx;
636 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 637 u32 reg;
638
95ea3627
ID		 639 /*
640 * Initialize registers.
641 */
642 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 643 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
644 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
645 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
646 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 647 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
648
181d6902 649 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 650 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
181d6902 651 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 652 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
653
181d6902 654 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 655 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
181d6902 656 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 657 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
658
181d6902 659 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 660 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
181d6902 661 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 662 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
663
181d6902 664 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 665 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
181d6902 666 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 667 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
668
669 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
670 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 671 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 672 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
673
181d6902 674 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 675 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
181d6902 676 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_tx->dma);
95ea3627
ID		 677 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
678
679 return 0;
680}
681
682static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
683{
684 u32 reg;
685
686 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
687 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
688 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
689 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
690
691 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
692 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
693 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
694 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
695 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
696
697 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
698 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
699 (rt2x00dev->rx->data_size / 128));
700 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
701
a9450b70
ID		 702 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
703 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
704 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
705 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
706
95ea3627
ID		 707 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
708
709 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
710 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
711 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
712 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
713 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
714 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
715
716 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
717 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
718 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
719 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
720 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
721 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
722 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
723 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
724
725 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
726
727 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
728 return -EBUSY;
729
730 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
731 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
732
733 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
734 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
735 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
736
737 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
738 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
739 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
740 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
741 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
742 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
743
744 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
745 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
746 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
747 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
748 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
749
750 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
751 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
752 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
753 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
754
755 /*
756 * We must clear the FCS and FIFO error count.
757 * These registers are cleared on read,
758 * so we may pass a useless variable to store the value.
759 */
760 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
761 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
762
763 return 0;
764}
765
766static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
767{
768 unsigned int i;
769 u16 eeprom;
770 u8 reg_id;
771 u8 value;
772
773 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
774 rt2400pci_bbp_read(rt2x00dev, 0, &value);
775 if ((value != 0xff) && (value != 0x00))
776 goto continue_csr_init;
777 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
778 udelay(REGISTER_BUSY_DELAY);
779 }
780
781 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
782 return -EACCES;
783
784continue_csr_init:
785 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
786 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
787 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
788 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
789 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
790 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
791 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
792 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
793 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
794 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
795 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
796 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
797 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
798 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
799
800 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
801 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
802 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
803
804 if (eeprom != 0xffff && eeprom != 0x0000) {
805 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
806 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
807 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
808 reg_id, value);
809 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
810 }
811 }
812 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
813
814 return 0;
815}
816
817/*
818 * Device state switch handlers.
819 */
820static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
821 enum dev_state state)
822{
823 u32 reg;
824
825 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
826 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
827 state == STATE_RADIO_RX_OFF);
828 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
829}
830
831static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
832 enum dev_state state)
833{
834 int mask = (state == STATE_RADIO_IRQ_OFF);
835 u32 reg;
836
837 /*
838 * When interrupts are being enabled, the interrupt registers
839 * should clear the register to assure a clean state.
840 */
841 if (state == STATE_RADIO_IRQ_ON) {
842 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
843 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
844 }
845
846 /*
847 * Only toggle the interrupts bits we are going to use.
848 * Non-checked interrupt bits are disabled by default.
849 */
850 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
851 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
852 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
853 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
854 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
855 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
856 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
857}
858
859static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
860{
861 /*
862 * Initialize all registers.
863 */
181d6902 864 if (rt2400pci_init_queues(rt2x00dev) ||
95ea3627
ID		 865 rt2400pci_init_registers(rt2x00dev) ||
866 rt2400pci_init_bbp(rt2x00dev)) {
867 ERROR(rt2x00dev, "Register initialization failed.\n");
868 return -EIO;
869 }
870
871 /*
872 * Enable interrupts.
873 */
874 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
875
95ea3627
ID		 876 return 0;
877}
878
879static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
880{
881 u32 reg;
882
95ea3627
ID		 883 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
884
885 /*
886 * Disable synchronisation.
887 */
888 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
889
890 /*
891 * Cancel RX and TX.
892 */
893 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
894 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
895 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
896
897 /*
898 * Disable interrupts.
899 */
900 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
901}
902
903static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
904 enum dev_state state)
905{
906 u32 reg;
907 unsigned int i;
908 char put_to_sleep;
909 char bbp_state;
910 char rf_state;
911
912 put_to_sleep = (state != STATE_AWAKE);
913
914 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
915 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
916 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
917 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
918 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
919 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
920
921 /*
922 * Device is not guaranteed to be in the requested state yet.
923 * We must wait until the register indicates that the
924 * device has entered the correct state.
925 */
926 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
927 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
928 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
929 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
930 if (bbp_state == state && rf_state == state)
931 return 0;
932 msleep(10);
933 }
934
935 NOTICE(rt2x00dev, "Device failed to enter state %d, "
936 "current device state: bbp %d and rf %d.\n",
937 state, bbp_state, rf_state);
938
939 return -EBUSY;
940}
941
942static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
943 enum dev_state state)
944{
945 int retval = 0;
946
947 switch (state) {
948 case STATE_RADIO_ON:
949 retval = rt2400pci_enable_radio(rt2x00dev);
950 break;
951 case STATE_RADIO_OFF:
952 rt2400pci_disable_radio(rt2x00dev);
953 break;
954 case STATE_RADIO_RX_ON:
61667d8d
ID		 955 case STATE_RADIO_RX_ON_LINK:
956 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
957 break;
95ea3627 958 case STATE_RADIO_RX_OFF:
61667d8d
ID		 959 case STATE_RADIO_RX_OFF_LINK:
960 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 961 break;
962 case STATE_DEEP_SLEEP:
963 case STATE_SLEEP:
964 case STATE_STANDBY:
965 case STATE_AWAKE:
966 retval = rt2400pci_set_state(rt2x00dev, state);
967 break;
968 default:
969 retval = -ENOTSUPP;
970 break;
971 }
972
973 return retval;
974}
975
976/*
977 * TX descriptor initialization
978 */
979static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 980 struct sk_buff *skb,
181d6902 981 struct txentry_desc *txdesc,
95ea3627
ID		 982 struct ieee80211_tx_control *control)
983{
181d6902 984 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 985 __le32 *txd = skbdesc->desc;
95ea3627 986 u32 word;
95ea3627
ID		 987
988 /*
989 * Start writing the descriptor words.
990 */
991 rt2x00_desc_read(txd, 2, &word);
dd3193e1 992 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 993 rt2x00_desc_write(txd, 2, word);
994
995 rt2x00_desc_read(txd, 3, &word);
181d6902 996 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 997 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
998 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 999 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1000 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1001 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1002 rt2x00_desc_write(txd, 3, word);
1003
1004 rt2x00_desc_read(txd, 4, &word);
181d6902 1005 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1006 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1007 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1008 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1009 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1010 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1011 rt2x00_desc_write(txd, 4, word);
1012
1013 rt2x00_desc_read(txd, 0, &word);
1014 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1015 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1016 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1017 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1018 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1019 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1020 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1021 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1022 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1023 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1024 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1025 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1026 !!(control->flags &
1027 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1028 rt2x00_desc_write(txd, 0, word);
1029}
1030
1031/*
1032 * TX data initialization
1033 */
1034static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1035 const unsigned int queue)
95ea3627
ID		 1036{
1037 u32 reg;
1038
5957da4c 1039 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1040 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1041 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1042 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1043 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1044 }
1045 return;
1046 }
1047
1048 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1049 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1050 (queue == IEEE80211_TX_QUEUE_DATA0));
1051 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1052 (queue == IEEE80211_TX_QUEUE_DATA1));
1053 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
5957da4c 1054 (queue == RT2X00_BCN_QUEUE_ATIM));
95ea3627
ID		 1055 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1056}
1057
1058/*
1059 * RX control handlers
1060 */
181d6902
ID		 1061static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1062 struct rxdone_entry_desc *rxdesc)
95ea3627 1063{
181d6902 1064 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1065 u32 word0;
1066 u32 word2;
1067
181d6902
ID		 1068 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1069 rt2x00_desc_read(priv_rx->desc, 2, &word2);
95ea3627 1070
181d6902 1071 rxdesc->flags = 0;
4150c572 1072 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1073 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1074 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1075 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1076
1077 /*
1078 * Obtain the status about this packet.
1079 */
181d6902
ID		 1080 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1081 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1082 entry->queue->rt2x00dev->rssi_offset;
1083 rxdesc->ofdm = 0;
1084 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1085 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1086}
1087
1088/*
1089 * Interrupt functions.
1090 */
181d6902
ID		 1091static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1092 const enum ieee80211_tx_queue queue_idx)
95ea3627 1093{
181d6902
ID		 1094 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1095 struct queue_entry_priv_pci_tx *priv_tx;
1096 struct queue_entry *entry;
1097 struct txdone_entry_desc txdesc;
95ea3627 1098 u32 word;
95ea3627 1099
181d6902
ID		 1100 while (!rt2x00queue_empty(queue)) {
1101 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1102 priv_tx = entry->priv_data;
1103 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1104
1105 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1106 !rt2x00_get_field32(word, TXD_W0_VALID))
1107 break;
1108
1109 /*
1110 * Obtain the status about this packet.
1111 */
181d6902
ID		 1112 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1113 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1114
181d6902 1115 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1116 }
95ea3627
ID		 1117}
1118
1119static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1120{
1121 struct rt2x00_dev *rt2x00dev = dev_instance;
1122 u32 reg;
1123
1124 /*
1125 * Get the interrupt sources & saved to local variable.
1126 * Write register value back to clear pending interrupts.
1127 */
1128 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1129 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1130
1131 if (!reg)
1132 return IRQ_NONE;
1133
1134 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1135 return IRQ_HANDLED;
1136
1137 /*
1138 * Handle interrupts, walk through all bits
1139 * and run the tasks, the bits are checked in order of
1140 * priority.
1141 */
1142
1143 /*
1144 * 1 - Beacon timer expired interrupt.
1145 */
1146 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1147 rt2x00lib_beacondone(rt2x00dev);
1148
1149 /*
1150 * 2 - Rx ring done interrupt.
1151 */
1152 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1153 rt2x00pci_rxdone(rt2x00dev);
1154
1155 /*
1156 * 3 - Atim ring transmit done interrupt.
1157 */
1158 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
5957da4c 1159 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
95ea3627
ID		 1160
1161 /*
1162 * 4 - Priority ring transmit done interrupt.
1163 */
1164 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1165 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1166
1167 /*
1168 * 5 - Tx ring transmit done interrupt.
1169 */
1170 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1171 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1172
1173 return IRQ_HANDLED;
1174}
1175
1176/*
1177 * Device probe functions.
1178 */
1179static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1180{
1181 struct eeprom_93cx6 eeprom;
1182 u32 reg;
1183 u16 word;
1184 u8 *mac;
1185
1186 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1187
1188 eeprom.data = rt2x00dev;
1189 eeprom.register_read = rt2400pci_eepromregister_read;
1190 eeprom.register_write = rt2400pci_eepromregister_write;
1191 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1192 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1193 eeprom.reg_data_in = 0;
1194 eeprom.reg_data_out = 0;
1195 eeprom.reg_data_clock = 0;
1196 eeprom.reg_chip_select = 0;
1197
1198 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1199 EEPROM_SIZE / sizeof(u16));
1200
1201 /*
1202 * Start validation of the data that has been read.
1203 */
1204 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1205 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1206 DECLARE_MAC_BUF(macbuf);
1207
95ea3627 1208 random_ether_addr(mac);
0795af57 1209 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1210 }
1211
1212 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1213 if (word == 0xffff) {
1214 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1215 return -EINVAL;
1216 }
1217
1218 return 0;
1219}
1220
1221static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1222{
1223 u32 reg;
1224 u16 value;
1225 u16 eeprom;
1226
1227 /*
1228 * Read EEPROM word for configuration.
1229 */
1230 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1231
1232 /*
1233 * Identify RF chipset.
1234 */
1235 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1236 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1237 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1238
1239 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1240 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1241 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1242 return -ENODEV;
1243 }
1244
1245 /*
1246 * Identify default antenna configuration.
1247 */
addc81bd 1248 rt2x00dev->default_ant.tx =
95ea3627 1249 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1250 rt2x00dev->default_ant.rx =
95ea3627
ID		 1251 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1252
addc81bd
ID		 1253 /*
1254 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1255 * I am not 100% sure about this, but the legacy drivers do not
1256 * indicate antenna swapping in software is required when
1257 * diversity is enabled.
1258 */
1259 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1260 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1261 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1262 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1263
95ea3627
ID		 1264 /*
1265 * Store led mode, for correct led behaviour.
1266 */
a9450b70
ID		 1267#ifdef CONFIG_RT2400PCI_LEDS
1268 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1269
1270 switch (value) {
1271 case LED_MODE_ASUS:
1272 case LED_MODE_ALPHA:
1273 case LED_MODE_DEFAULT:
1274 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1275 break;
1276 case LED_MODE_TXRX_ACTIVITY:
1277 rt2x00dev->led_flags =
1278 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1279 break;
1280 case LED_MODE_SIGNAL_STRENGTH:
1281 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1282 break;
1283 }
1284#endif /* CONFIG_RT2400PCI_LEDS */
95ea3627
ID		 1285
1286 /*
1287 * Detect if this device has an hardware controlled radio.
1288 */
81873e9c 1289#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1290 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1291 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1292#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1293
1294 /*
1295 * Check if the BBP tuning should be enabled.
1296 */
1297 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1298 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1299
1300 return 0;
1301}
1302
1303/*
1304 * RF value list for RF2420 & RF2421
1305 * Supports: 2.4 GHz
1306 */
1307static const struct rf_channel rf_vals_bg[] = {
1308 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1309 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1310 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1311 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1312 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1313 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1314 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1315 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1316 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1317 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1318 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1319 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1320 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1321 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1322};
1323
1324static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1325{
1326 struct hw_mode_spec *spec = &rt2x00dev->spec;
1327 u8 *txpower;
1328 unsigned int i;
1329
1330 /*
1331 * Initialize all hw fields.
1332 */
4150c572 1333 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1334 rt2x00dev->hw->extra_tx_headroom = 0;
1335 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1336 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1337 rt2x00dev->hw->queues = 2;
1338
1339 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1340 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1341 rt2x00_eeprom_addr(rt2x00dev,
1342 EEPROM_MAC_ADDR_0));
1343
1344 /*
1345 * Convert tx_power array in eeprom.
1346 */
1347 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1348 for (i = 0; i < 14; i++)
1349 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1350
1351 /*
1352 * Initialize hw_mode information.
1353 */
1354 spec->num_modes = 1;
1355 spec->num_rates = 4;
1356 spec->tx_power_a = NULL;
1357 spec->tx_power_bg = txpower;
1358 spec->tx_power_default = DEFAULT_TXPOWER;
1359
1360 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1361 spec->channels = rf_vals_bg;
1362}
1363
1364static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1365{
1366 int retval;
1367
1368 /*
1369 * Allocate eeprom data.
1370 */
1371 retval = rt2400pci_validate_eeprom(rt2x00dev);
1372 if (retval)
1373 return retval;
1374
1375 retval = rt2400pci_init_eeprom(rt2x00dev);
1376 if (retval)
1377 return retval;
1378
1379 /*
1380 * Initialize hw specifications.
1381 */
1382 rt2400pci_probe_hw_mode(rt2x00dev);
1383
1384 /*
181d6902 1385 * This device requires the atim queue
95ea3627 1386 */
181d6902 1387 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1388
1389 /*
1390 * Set the rssi offset.
1391 */
1392 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1393
1394 return 0;
1395}
1396
1397/*
1398 * IEEE80211 stack callback functions.
1399 */
4150c572
JB		 1400static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1401 unsigned int changed_flags,
1402 unsigned int *total_flags,
1403 int mc_count,
1404 struct dev_addr_list *mc_list)
1405{
1406 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1407 u32 reg;
1408
1409 /*
1410 * Mask off any flags we are going to ignore from
1411 * the total_flags field.
1412 */
1413 *total_flags &=
1414 FIF_ALLMULTI |
1415 FIF_FCSFAIL |
1416 FIF_PLCPFAIL |
1417 FIF_CONTROL |
1418 FIF_OTHER_BSS |
1419 FIF_PROMISC_IN_BSS;
1420
1421 /*
1422 * Apply some rules to the filters:
1423 * - Some filters imply different filters to be set.
1424 * - Some things we can't filter out at all.
4150c572
JB		 1425 */
1426 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1427 if (*total_flags & FIF_OTHER_BSS ||
1428 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1429 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1430
1431 /*
1432 * Check if there is any work left for us.
1433 */
3c4f2085 1434 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1435 return;
3c4f2085 1436 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1437
1438 /*
1439 * Start configuration steps.
1440 * Note that the version error will always be dropped
1441 * since there is no filter for it at this time.
1442 */
1443 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1444 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1445 !(*total_flags & FIF_FCSFAIL));
1446 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1447 !(*total_flags & FIF_PLCPFAIL));
1448 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1449 !(*total_flags & FIF_CONTROL));
1450 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1451 !(*total_flags & FIF_PROMISC_IN_BSS));
1452 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1453 !(*total_flags & FIF_PROMISC_IN_BSS));
1454 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1455 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1456}
1457
95ea3627
ID		 1458static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1459 u32 short_retry, u32 long_retry)
1460{
1461 struct rt2x00_dev *rt2x00dev = hw->priv;
1462 u32 reg;
1463
1464 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1465 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1466 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1467 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1468
1469 return 0;
1470}
1471
1472static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1473 int queue,
1474 const struct ieee80211_tx_queue_params *params)
1475{
1476 struct rt2x00_dev *rt2x00dev = hw->priv;
1477
1478 /*
1479 * We don't support variating cw_min and cw_max variables
1480 * per queue. So by default we only configure the TX queue,
1481 * and ignore all other configurations.
1482 */
1483 if (queue != IEEE80211_TX_QUEUE_DATA0)
1484 return -EINVAL;
1485
1486 if (rt2x00mac_conf_tx(hw, queue, params))
1487 return -EINVAL;
1488
1489 /*
1490 * Write configuration to register.
1491 */
181d6902
ID		 1492 rt2400pci_config_cw(rt2x00dev,
1493 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1494
1495 return 0;
1496}
1497
1498static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1499{
1500 struct rt2x00_dev *rt2x00dev = hw->priv;
1501 u64 tsf;
1502 u32 reg;
1503
1504 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1505 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1506 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1507 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1508
1509 return tsf;
1510}
1511
1512static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1513{
1514 struct rt2x00_dev *rt2x00dev = hw->priv;
1515
1516 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1517 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1518}
1519
5957da4c
ID		 1520static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1521 struct ieee80211_tx_control *control)
1522{
1523 struct rt2x00_dev *rt2x00dev = hw->priv;
1524 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1525 struct queue_entry_priv_pci_tx *priv_tx;
1526 struct skb_frame_desc *skbdesc;
1527
1528 if (unlikely(!intf->beacon))
1529 return -ENOBUFS;
1530
1531 priv_tx = intf->beacon->priv_data;
1532
1533 /*
1534 * Fill in skb descriptor
1535 */
1536 skbdesc = get_skb_frame_desc(skb);
1537 memset(skbdesc, 0, sizeof(*skbdesc));
1538 skbdesc->data = skb->data;
1539 skbdesc->data_len = skb->len;
1540 skbdesc->desc = priv_tx->desc;
1541 skbdesc->desc_len = intf->beacon->queue->desc_size;
1542 skbdesc->entry = intf->beacon;
1543
1544 /*
1545 * mac80211 doesn't provide the control->queue variable
1546 * for beacons. Set our own queue identification so
1547 * it can be used during descriptor initialization.
1548 */
1549 control->queue = RT2X00_BCN_QUEUE_BEACON;
1550 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1551
1552 /*
1553 * Enable beacon generation.
1554 * Write entire beacon with descriptor to register,
1555 * and kick the beacon generator.
1556 */
1557 memcpy(priv_tx->data, skb->data, skb->len);
1558 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1559
1560 return 0;
1561}
1562
95ea3627
ID		 1563static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1564{
1565 struct rt2x00_dev *rt2x00dev = hw->priv;
1566 u32 reg;
1567
1568 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1569 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1570}
1571
1572static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1573 .tx = rt2x00mac_tx,
4150c572
JB		 1574 .start = rt2x00mac_start,
1575 .stop = rt2x00mac_stop,
95ea3627
ID		 1576 .add_interface = rt2x00mac_add_interface,
1577 .remove_interface = rt2x00mac_remove_interface,
1578 .config = rt2x00mac_config,
1579 .config_interface = rt2x00mac_config_interface,
4150c572 1580 .configure_filter = rt2400pci_configure_filter,
95ea3627
ID		 1581 .get_stats = rt2x00mac_get_stats,
1582 .set_retry_limit = rt2400pci_set_retry_limit,
471b3efd 1583 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1584 .conf_tx = rt2400pci_conf_tx,
1585 .get_tx_stats = rt2x00mac_get_tx_stats,
1586 .get_tsf = rt2400pci_get_tsf,
1587 .reset_tsf = rt2400pci_reset_tsf,
5957da4c 1588 .beacon_update = rt2400pci_beacon_update,
95ea3627
ID		 1589 .tx_last_beacon = rt2400pci_tx_last_beacon,
1590};
1591
1592static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1593 .irq_handler = rt2400pci_interrupt,
1594 .probe_hw = rt2400pci_probe_hw,
1595 .initialize = rt2x00pci_initialize,
1596 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1597 .init_rxentry = rt2400pci_init_rxentry,
1598 .init_txentry = rt2400pci_init_txentry,
95ea3627 1599 .set_device_state = rt2400pci_set_device_state,
95ea3627 1600 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1601 .link_stats = rt2400pci_link_stats,
1602 .reset_tuner = rt2400pci_reset_tuner,
1603 .link_tuner = rt2400pci_link_tuner,
a9450b70 1604 .led_brightness = rt2400pci_led_brightness,
95ea3627
ID		 1605 .write_tx_desc = rt2400pci_write_tx_desc,
1606 .write_tx_data = rt2x00pci_write_tx_data,
1607 .kick_tx_queue = rt2400pci_kick_tx_queue,
1608 .fill_rxdone = rt2400pci_fill_rxdone,
6bb40dd1 1609 .config_intf = rt2400pci_config_intf,
5c58ee51 1610 .config_preamble = rt2400pci_config_preamble,
95ea3627
ID		 1611 .config = rt2400pci_config,
1612};
1613
181d6902
ID		 1614static const struct data_queue_desc rt2400pci_queue_rx = {
1615 .entry_num = RX_ENTRIES,
1616 .data_size = DATA_FRAME_SIZE,
1617 .desc_size = RXD_DESC_SIZE,
1618 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1619};
1620
1621static const struct data_queue_desc rt2400pci_queue_tx = {
1622 .entry_num = TX_ENTRIES,
1623 .data_size = DATA_FRAME_SIZE,
1624 .desc_size = TXD_DESC_SIZE,
1625 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1626};
1627
1628static const struct data_queue_desc rt2400pci_queue_bcn = {
1629 .entry_num = BEACON_ENTRIES,
1630 .data_size = MGMT_FRAME_SIZE,
1631 .desc_size = TXD_DESC_SIZE,
1632 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1633};
1634
1635static const struct data_queue_desc rt2400pci_queue_atim = {
1636 .entry_num = ATIM_ENTRIES,
1637 .data_size = DATA_FRAME_SIZE,
1638 .desc_size = TXD_DESC_SIZE,
1639 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1640};
1641
95ea3627 1642static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1643 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1644 .max_sta_intf = 1,
1645 .max_ap_intf = 1,
95ea3627
ID		 1646 .eeprom_size = EEPROM_SIZE,
1647 .rf_size = RF_SIZE,
181d6902
ID		 1648 .rx = &rt2400pci_queue_rx,
1649 .tx = &rt2400pci_queue_tx,
1650 .bcn = &rt2400pci_queue_bcn,
1651 .atim = &rt2400pci_queue_atim,
95ea3627
ID		 1652 .lib = &rt2400pci_rt2x00_ops,
1653 .hw = &rt2400pci_mac80211_ops,
1654#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1655 .debugfs = &rt2400pci_rt2x00debug,
1656#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1657};
1658
1659/*
1660 * RT2400pci module information.
1661 */
1662static struct pci_device_id rt2400pci_device_table[] = {
1663 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1664 { 0, }
1665};
1666
1667MODULE_AUTHOR(DRV_PROJECT);
1668MODULE_VERSION(DRV_VERSION);
1669MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1670MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1671MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1672MODULE_LICENSE("GPL");
1673
1674static struct pci_driver rt2400pci_driver = {
2360157c 1675 .name = KBUILD_MODNAME,
95ea3627
ID		 1676 .id_table = rt2400pci_device_table,
1677 .probe = rt2x00pci_probe,
1678 .remove = __devexit_p(rt2x00pci_remove),
1679 .suspend = rt2x00pci_suspend,
1680 .resume = rt2x00pci_resume,
1681};
1682
1683static int __init rt2400pci_init(void)
1684{
1685 return pci_register_driver(&rt2400pci_driver);
1686}
1687
1688static void __exit rt2400pci_exit(void)
1689{
1690 pci_unregister_driver(&rt2400pci_driver);
1691}
1692
1693module_init(rt2400pci_init);
1694module_exit(rt2400pci_exit);
Linux kernel - Deliverables
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