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rt2x00: Cleanup symbol exports
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 244#endif /* CONFIG_RT2400PCI_RFKILL */
245
a9450b70 246#ifdef CONFIG_RT2400PCI_LEDS
a2e1d52a 247static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
a2e1d52a 257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263}
a2e1d52a
ID		 264
265static int rt2400pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268{
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279}
475433be
ID		 280
281static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
282 struct rt2x00_led *led,
283 enum led_type type)
284{
285 led->rt2x00dev = rt2x00dev;
286 led->type = type;
287 led->led_dev.brightness_set = rt2400pci_brightness_set;
288 led->led_dev.blink_set = rt2400pci_blink_set;
289 led->flags = LED_INITIALIZED;
290}
a9450b70
ID		 291#endif /* CONFIG_RT2400PCI_LEDS */
292
95ea3627
ID		 293/*
294 * Configuration handlers.
295 */
3a643d24
ID		 296static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
297 const unsigned int filter_flags)
298{
299 u32 reg;
300
301 /*
302 * Start configuration steps.
303 * Note that the version error will always be dropped
304 * since there is no filter for it at this time.
305 */
306 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
307 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
308 !(filter_flags & FIF_FCSFAIL));
309 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
310 !(filter_flags & FIF_PLCPFAIL));
311 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
312 !(filter_flags & FIF_CONTROL));
313 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
314 !(filter_flags & FIF_PROMISC_IN_BSS));
315 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 316 !(filter_flags & FIF_PROMISC_IN_BSS) &&
317 !rt2x00dev->intf_ap_count);
3a643d24
ID		 318 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
319 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
320}
321
6bb40dd1
ID		 322static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
323 struct rt2x00_intf *intf,
324 struct rt2x00intf_conf *conf,
325 const unsigned int flags)
95ea3627 326{
6bb40dd1
ID		 327 unsigned int bcn_preload;
328 u32 reg;
95ea3627 329
6bb40dd1 330 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 331 /*
332 * Enable beacon config
333 */
334 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
335 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
336 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
337 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 338
6bb40dd1
ID		 339 /*
340 * Enable synchronisation.
341 */
342 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 343 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 344 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 345 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 346 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
347 }
95ea3627 348
6bb40dd1
ID		 349 if (flags & CONFIG_UPDATE_MAC)
350 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
351 conf->mac, sizeof(conf->mac));
95ea3627 352
6bb40dd1
ID		 353 if (flags & CONFIG_UPDATE_BSSID)
354 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
355 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 356}
357
3a643d24
ID		 358static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
359 struct rt2x00lib_erp *erp)
95ea3627 360{
5c58ee51 361 int preamble_mask;
95ea3627 362 u32 reg;
95ea3627 363
5c58ee51
ID		 364 /*
365 * When short preamble is enabled, we should set bit 0x08
366 */
72810379 367 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 368
369 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 370 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
371 erp->ack_timeout);
372 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
373 erp->ack_consume_time);
95ea3627
ID		 374 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
375
95ea3627 376 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 377 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627
ID		 378 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
379 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
380 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
381
382 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 383 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 384 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
385 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
386 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
387
388 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 389 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 390 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
391 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
392 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
393
394 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 395 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 396 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
397 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
398 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
399}
400
401static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 402 const int basic_rate_mask)
95ea3627 403{
5c58ee51 404 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 405}
406
407static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 408 struct rf_channel *rf)
95ea3627 409{
95ea3627
ID		 410 /*
411 * Switch on tuning bits.
412 */
5c58ee51
ID		 413 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
414 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 415
5c58ee51
ID		 416 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
417 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
418 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 419
420 /*
421 * RF2420 chipset don't need any additional actions.
422 */
423 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
424 return;
425
426 /*
427 * For the RT2421 chipsets we need to write an invalid
428 * reference clock rate to activate auto_tune.
429 * After that we set the value back to the correct channel.
430 */
5c58ee51 431 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 432 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 433 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 434
435 msleep(1);
436
5c58ee51
ID		 437 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
438 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
439 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 440
441 msleep(1);
442
443 /*
444 * Switch off tuning bits.
445 */
5c58ee51
ID		 446 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
447 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 448
5c58ee51
ID		 449 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
450 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 451
452 /*
453 * Clear false CRC during channel switch.
454 */
5c58ee51 455 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 456}
457
458static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
459{
460 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
461}
462
463static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 464 struct antenna_setup *ant)
95ea3627
ID		 465{
466 u8 r1;
467 u8 r4;
468
a4fe07d9
ID		 469 /*
470 * We should never come here because rt2x00lib is supposed
471 * to catch this and send us the correct antenna explicitely.
472 */
473 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
474 ant->tx == ANTENNA_SW_DIVERSITY);
475
95ea3627
ID		 476 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
477 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
478
479 /*
480 * Configure the TX antenna.
481 */
addc81bd 482 switch (ant->tx) {
95ea3627
ID		 483 case ANTENNA_HW_DIVERSITY:
484 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
485 break;
486 case ANTENNA_A:
487 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
488 break;
489 case ANTENNA_B:
a4fe07d9 490 default:
95ea3627
ID		 491 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
492 break;
493 }
494
495 /*
496 * Configure the RX antenna.
497 */
addc81bd 498 switch (ant->rx) {
95ea3627
ID		 499 case ANTENNA_HW_DIVERSITY:
500 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
501 break;
502 case ANTENNA_A:
503 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
504 break;
505 case ANTENNA_B:
a4fe07d9 506 default:
95ea3627
ID		 507 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
508 break;
509 }
510
511 rt2400pci_bbp_write(rt2x00dev, 4, r4);
512 rt2400pci_bbp_write(rt2x00dev, 1, r1);
513}
514
515static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 516 struct rt2x00lib_conf *libconf)
95ea3627
ID		 517{
518 u32 reg;
519
520 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 521 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 522 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
523
524 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 525 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
526 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 527 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
528
529 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 530 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
531 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 532 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
533
534 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
535 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
536 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
537 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
538
539 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 540 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
541 libconf->conf->beacon_int * 16);
542 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
543 libconf->conf->beacon_int * 16);
95ea3627
ID		 544 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
545}
546
547static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 548 struct rt2x00lib_conf *libconf,
549 const unsigned int flags)
95ea3627 550{
95ea3627 551 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 552 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 553 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 554 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 555 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 556 rt2400pci_config_txpower(rt2x00dev,
557 libconf->conf->power_level);
95ea3627 558 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 559 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 560 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 561 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 562}
563
564static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 565 const int cw_min, const int cw_max)
95ea3627
ID		 566{
567 u32 reg;
568
569 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 570 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
571 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 572 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
573}
574
95ea3627
ID		 575/*
576 * Link tuning
577 */
ebcf26da
ID		 578static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
579 struct link_qual *qual)
95ea3627
ID		 580{
581 u32 reg;
582 u8 bbp;
583
584 /*
585 * Update FCS error count from register.
586 */
587 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 588 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 589
590 /*
591 * Update False CCA count from register.
592 */
593 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 594 qual->false_cca = bbp;
95ea3627
ID		 595}
596
597static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
598{
599 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
600 rt2x00dev->link.vgc_level = 0x08;
601}
602
603static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
604{
605 u8 reg;
606
607 /*
608 * The link tuner should not run longer then 60 seconds,
609 * and should run once every 2 seconds.
610 */
611 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
612 return;
613
614 /*
615 * Base r13 link tuning on the false cca count.
616 */
617 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
618
ebcf26da 619 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 620 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
621 rt2x00dev->link.vgc_level = reg;
ebcf26da 622 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 623 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
624 rt2x00dev->link.vgc_level = reg;
625 }
626}
627
628/*
629 * Initialization functions.
630 */
837e7f24 631static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 632 struct queue_entry *entry)
95ea3627 633{
b8be63ff 634 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
c4da0048 635 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
95ea3627
ID		 636 u32 word;
637
b8be63ff 638 rt2x00_desc_read(entry_priv->desc, 2, &word);
c4da0048 639 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
b8be63ff 640 rt2x00_desc_write(entry_priv->desc, 2, word);
95ea3627 641
b8be63ff 642 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 643 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
b8be63ff 644 rt2x00_desc_write(entry_priv->desc, 1, word);
95ea3627 645
b8be63ff 646 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24 647 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
b8be63ff 648 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 649}
650
837e7f24 651static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 652 struct queue_entry *entry)
95ea3627 653{
b8be63ff 654 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 655 u32 word;
656
b8be63ff 657 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24
ID		 658 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
659 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
b8be63ff 660 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 661}
662
181d6902 663static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 664{
b8be63ff 665 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 666 u32 reg;
667
95ea3627
ID		 668 /*
669 * Initialize registers.
670 */
671 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 672 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
673 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
674 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
675 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 676 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
677
b8be63ff 678 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 679 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 680 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 681 entry_priv->desc_dma);
95ea3627
ID		 682 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
683
b8be63ff 684 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 685 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 686 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 687 entry_priv->desc_dma);
95ea3627
ID		 688 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
689
b8be63ff 690 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 691 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 692 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 693 entry_priv->desc_dma);
95ea3627
ID		 694 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
695
b8be63ff 696 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 697 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 698 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 699 entry_priv->desc_dma);
95ea3627
ID		 700 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
701
702 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
703 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 704 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 705 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
706
b8be63ff 707 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 708 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 709 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
710 entry_priv->desc_dma);
95ea3627
ID		 711 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
712
713 return 0;
714}
715
716static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
717{
718 u32 reg;
719
720 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
721 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
722 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
723 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
724
725 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
726 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
727 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
728 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
729 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
730
731 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
732 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
733 (rt2x00dev->rx->data_size / 128));
734 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
735
736 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
737
738 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
739 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
740 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
741 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
742 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
743 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
744
745 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
746 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
747 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
748 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
749 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
750 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
751 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
752 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
753
754 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
755
756 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
757 return -EBUSY;
758
759 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
760 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
761
762 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
763 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
764 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
765
766 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
767 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
768 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
769 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
770 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
771 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
772
773 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
774 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
775 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
776 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
777 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
778
779 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
780 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
781 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
782 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
783
784 /*
785 * We must clear the FCS and FIFO error count.
786 * These registers are cleared on read,
787 * so we may pass a useless variable to store the value.
788 */
789 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
790 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
791
792 return 0;
793}
794
2b08da3f 795static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 796{
797 unsigned int i;
95ea3627
ID		 798 u8 value;
799
800 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
801 rt2400pci_bbp_read(rt2x00dev, 0, &value);
802 if ((value != 0xff) && (value != 0x00))
2b08da3f 803 return 0;
95ea3627
ID		 804 udelay(REGISTER_BUSY_DELAY);
805 }
806
807 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
808 return -EACCES;
2b08da3f
ID		 809}
810
811static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
812{
813 unsigned int i;
814 u16 eeprom;
815 u8 reg_id;
816 u8 value;
817
818 if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
819 return -EACCES;
95ea3627 820
95ea3627
ID		 821 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
822 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
823 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
824 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
825 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
826 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
827 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
828 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
829 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
830 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
831 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
832 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
833 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
834 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
835
95ea3627
ID		 836 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
837 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
838
839 if (eeprom != 0xffff && eeprom != 0x0000) {
840 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
841 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 842 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
843 }
844 }
95ea3627
ID		 845
846 return 0;
847}
848
849/*
850 * Device state switch handlers.
851 */
852static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
853 enum dev_state state)
854{
855 u32 reg;
856
857 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
858 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
2b08da3f
ID		 859 (state == STATE_RADIO_RX_OFF) ||
860 (state == STATE_RADIO_RX_OFF_LINK));
95ea3627
ID		 861 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
862}
863
864static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
865 enum dev_state state)
866{
867 int mask = (state == STATE_RADIO_IRQ_OFF);
868 u32 reg;
869
870 /*
871 * When interrupts are being enabled, the interrupt registers
872 * should clear the register to assure a clean state.
873 */
874 if (state == STATE_RADIO_IRQ_ON) {
875 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
876 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
877 }
878
879 /*
880 * Only toggle the interrupts bits we are going to use.
881 * Non-checked interrupt bits are disabled by default.
882 */
883 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
884 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
885 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
886 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
887 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
888 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
889 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
890}
891
892static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
893{
894 /*
895 * Initialize all registers.
896 */
2b08da3f
ID		 897 if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
898 rt2400pci_init_registers(rt2x00dev) ||
899 rt2400pci_init_bbp(rt2x00dev)))
95ea3627 900 return -EIO;
95ea3627 901
95ea3627
ID		 902 return 0;
903}
904
905static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
906{
907 u32 reg;
908
95ea3627
ID		 909 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
910
911 /*
912 * Disable synchronisation.
913 */
914 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
915
916 /*
917 * Cancel RX and TX.
918 */
919 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
920 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
921 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
95ea3627
ID		 922}
923
924static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
925 enum dev_state state)
926{
927 u32 reg;
928 unsigned int i;
929 char put_to_sleep;
930 char bbp_state;
931 char rf_state;
932
933 put_to_sleep = (state != STATE_AWAKE);
934
935 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
936 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
937 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
938 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
939 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
940 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
941
942 /*
943 * Device is not guaranteed to be in the requested state yet.
944 * We must wait until the register indicates that the
945 * device has entered the correct state.
946 */
947 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
948 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
949 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
950 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
951 if (bbp_state == state && rf_state == state)
952 return 0;
953 msleep(10);
954 }
955
95ea3627
ID		 956 return -EBUSY;
957}
958
959static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
960 enum dev_state state)
961{
962 int retval = 0;
963
964 switch (state) {
965 case STATE_RADIO_ON:
966 retval = rt2400pci_enable_radio(rt2x00dev);
967 break;
968 case STATE_RADIO_OFF:
969 rt2400pci_disable_radio(rt2x00dev);
970 break;
971 case STATE_RADIO_RX_ON:
61667d8d 972 case STATE_RADIO_RX_ON_LINK:
95ea3627 973 case STATE_RADIO_RX_OFF:
61667d8d 974 case STATE_RADIO_RX_OFF_LINK:
2b08da3f
ID		 975 rt2400pci_toggle_rx(rt2x00dev, state);
976 break;
977 case STATE_RADIO_IRQ_ON:
978 case STATE_RADIO_IRQ_OFF:
979 rt2400pci_toggle_irq(rt2x00dev, state);
95ea3627
ID		 980 break;
981 case STATE_DEEP_SLEEP:
982 case STATE_SLEEP:
983 case STATE_STANDBY:
984 case STATE_AWAKE:
985 retval = rt2400pci_set_state(rt2x00dev, state);
986 break;
987 default:
988 retval = -ENOTSUPP;
989 break;
990 }
991
2b08da3f
ID		 992 if (unlikely(retval))
993 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
994 state, retval);
995
95ea3627
ID		 996 return retval;
997}
998
999/*
1000 * TX descriptor initialization
1001 */
1002static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 1003 struct sk_buff *skb,
61486e0f 1004 struct txentry_desc *txdesc)
95ea3627 1005{
181d6902 1006 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 1007 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
dd3193e1 1008 __le32 *txd = skbdesc->desc;
95ea3627 1009 u32 word;
95ea3627
ID		 1010
1011 /*
1012 * Start writing the descriptor words.
1013 */
4de36fe5 1014 rt2x00_desc_read(entry_priv->desc, 1, &word);
c4da0048 1015 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
4de36fe5
GW		 1016 rt2x00_desc_write(entry_priv->desc, 1, word);
1017
95ea3627 1018 rt2x00_desc_read(txd, 2, &word);
d56d453a
GW		 1019 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len);
1020 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len);
95ea3627
ID		 1021 rt2x00_desc_write(txd, 2, word);
1022
1023 rt2x00_desc_read(txd, 3, &word);
181d6902 1024 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1025 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1026 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1027 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1028 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1029 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1030 rt2x00_desc_write(txd, 3, word);
1031
1032 rt2x00_desc_read(txd, 4, &word);
181d6902 1033 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1034 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1035 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1036 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1037 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1038 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1039 rt2x00_desc_write(txd, 4, word);
1040
1041 rt2x00_desc_read(txd, 0, &word);
1042 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1043 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1044 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1045 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1046 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1047 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1048 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1049 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1050 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1051 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1052 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1053 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1054 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627
ID		 1055 rt2x00_desc_write(txd, 0, word);
1056}
1057
1058/*
1059 * TX data initialization
1060 */
1061static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1062 const enum data_queue_qid queue)
95ea3627
ID		 1063{
1064 u32 reg;
1065
e58c6aca 1066 if (queue == QID_BEACON) {
95ea3627
ID		 1067 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1068 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1069 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1070 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1071 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1072 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1073 }
1074 return;
1075 }
1076
1077 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1078 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1079 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1080 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1081 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1082}
1083
1084/*
1085 * RX control handlers
1086 */
181d6902
ID		 1087static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1088 struct rxdone_entry_desc *rxdesc)
95ea3627 1089{
b8be63ff 1090 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1091 u32 word0;
1092 u32 word2;
89993890 1093 u32 word3;
95ea3627 1094
b8be63ff
ID		 1095 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1096 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1097 rt2x00_desc_read(entry_priv->desc, 3, &word3);
95ea3627 1098
4150c572 1099 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1100 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1101 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1102 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1103
1104 /*
1105 * Obtain the status about this packet.
8ed09854
ID		 1106 * The signal is the PLCP value, and needs to be stripped
1107 * of the preamble bit (0x08).
95ea3627 1108 */
8ed09854 1109 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1110 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1111 entry->queue->rt2x00dev->rssi_offset;
181d6902 1112 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1113
dec13b6b 1114 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1115 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1116 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1117}
1118
1119/*
1120 * Interrupt functions.
1121 */
181d6902 1122static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1123 const enum data_queue_qid queue_idx)
95ea3627 1124{
181d6902 1125 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1126 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1127 struct queue_entry *entry;
1128 struct txdone_entry_desc txdesc;
95ea3627 1129 u32 word;
95ea3627 1130
181d6902
ID		 1131 while (!rt2x00queue_empty(queue)) {
1132 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1133 entry_priv = entry->priv_data;
1134 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1135
1136 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1137 !rt2x00_get_field32(word, TXD_W0_VALID))
1138 break;
1139
1140 /*
1141 * Obtain the status about this packet.
1142 */
fb55f4d1
ID		 1143 txdesc.flags = 0;
1144 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1145 case 0: /* Success */
1146 case 1: /* Success with retry */
1147 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1148 break;
1149 case 2: /* Failure, excessive retries */
1150 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1151 /* Don't break, this is a failed frame! */
1152 default: /* Failure */
1153 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1154 }
181d6902 1155 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1156
d74f5ba4 1157 rt2x00lib_txdone(entry, &txdesc);
95ea3627 1158 }
95ea3627
ID		 1159}
1160
1161static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1162{
1163 struct rt2x00_dev *rt2x00dev = dev_instance;
1164 u32 reg;
1165
1166 /*
1167 * Get the interrupt sources & saved to local variable.
1168 * Write register value back to clear pending interrupts.
1169 */
1170 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1171 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1172
1173 if (!reg)
1174 return IRQ_NONE;
1175
1176 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1177 return IRQ_HANDLED;
1178
1179 /*
1180 * Handle interrupts, walk through all bits
1181 * and run the tasks, the bits are checked in order of
1182 * priority.
1183 */
1184
1185 /*
1186 * 1 - Beacon timer expired interrupt.
1187 */
1188 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1189 rt2x00lib_beacondone(rt2x00dev);
1190
1191 /*
1192 * 2 - Rx ring done interrupt.
1193 */
1194 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1195 rt2x00pci_rxdone(rt2x00dev);
1196
1197 /*
1198 * 3 - Atim ring transmit done interrupt.
1199 */
1200 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1201 rt2400pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1202
1203 /*
1204 * 4 - Priority ring transmit done interrupt.
1205 */
1206 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1207 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1208
1209 /*
1210 * 5 - Tx ring transmit done interrupt.
1211 */
1212 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1213 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1214
1215 return IRQ_HANDLED;
1216}
1217
1218/*
1219 * Device probe functions.
1220 */
1221static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1222{
1223 struct eeprom_93cx6 eeprom;
1224 u32 reg;
1225 u16 word;
1226 u8 *mac;
1227
1228 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1229
1230 eeprom.data = rt2x00dev;
1231 eeprom.register_read = rt2400pci_eepromregister_read;
1232 eeprom.register_write = rt2400pci_eepromregister_write;
1233 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1234 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1235 eeprom.reg_data_in = 0;
1236 eeprom.reg_data_out = 0;
1237 eeprom.reg_data_clock = 0;
1238 eeprom.reg_chip_select = 0;
1239
1240 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1241 EEPROM_SIZE / sizeof(u16));
1242
1243 /*
1244 * Start validation of the data that has been read.
1245 */
1246 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1247 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1248 DECLARE_MAC_BUF(macbuf);
1249
95ea3627 1250 random_ether_addr(mac);
0795af57 1251 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1252 }
1253
1254 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1255 if (word == 0xffff) {
1256 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1257 return -EINVAL;
1258 }
1259
1260 return 0;
1261}
1262
1263static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1264{
1265 u32 reg;
1266 u16 value;
1267 u16 eeprom;
1268
1269 /*
1270 * Read EEPROM word for configuration.
1271 */
1272 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1273
1274 /*
1275 * Identify RF chipset.
1276 */
1277 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1278 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1279 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1280
1281 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1282 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1283 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1284 return -ENODEV;
1285 }
1286
1287 /*
1288 * Identify default antenna configuration.
1289 */
addc81bd 1290 rt2x00dev->default_ant.tx =
95ea3627 1291 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1292 rt2x00dev->default_ant.rx =
95ea3627
ID		 1293 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1294
addc81bd
ID		 1295 /*
1296 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1297 * I am not 100% sure about this, but the legacy drivers do not
1298 * indicate antenna swapping in software is required when
1299 * diversity is enabled.
1300 */
1301 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1302 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1303 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1304 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1305
95ea3627
ID		 1306 /*
1307 * Store led mode, for correct led behaviour.
1308 */
a9450b70
ID		 1309#ifdef CONFIG_RT2400PCI_LEDS
1310 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1311
475433be
ID		 1312 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1313 if (value == LED_MODE_TXRX_ACTIVITY)
1314 rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
1315 LED_TYPE_ACTIVITY);
a9450b70 1316#endif /* CONFIG_RT2400PCI_LEDS */
95ea3627
ID		 1317
1318 /*
1319 * Detect if this device has an hardware controlled radio.
1320 */
81873e9c 1321#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1322 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1323 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1324#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1325
1326 /*
1327 * Check if the BBP tuning should be enabled.
1328 */
1329 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1330 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1331
1332 return 0;
1333}
1334
1335/*
1336 * RF value list for RF2420 & RF2421
1337 * Supports: 2.4 GHz
1338 */
1339static const struct rf_channel rf_vals_bg[] = {
1340 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1341 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1342 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1343 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1344 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1345 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1346 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1347 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1348 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1349 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1350 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1351 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1352 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1353 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1354};
1355
1356static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1357{
1358 struct hw_mode_spec *spec = &rt2x00dev->spec;
1359 u8 *txpower;
1360 unsigned int i;
1361
1362 /*
1363 * Initialize all hw fields.
1364 */
566bfe5a
BR		 1365 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1366 IEEE80211_HW_SIGNAL_DBM;
95ea3627 1367 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627 1368
14a3bf89 1369 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
95ea3627
ID		 1370 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1371 rt2x00_eeprom_addr(rt2x00dev,
1372 EEPROM_MAC_ADDR_0));
1373
1374 /*
1375 * Convert tx_power array in eeprom.
1376 */
1377 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1378 for (i = 0; i < 14; i++)
1379 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1380
1381 /*
1382 * Initialize hw_mode information.
1383 */
31562e80
ID		 1384 spec->supported_bands = SUPPORT_BAND_2GHZ;
1385 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627
ID		 1386 spec->tx_power_a = NULL;
1387 spec->tx_power_bg = txpower;
1388 spec->tx_power_default = DEFAULT_TXPOWER;
1389
1390 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1391 spec->channels = rf_vals_bg;
1392}
1393
1394static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1395{
1396 int retval;
1397
1398 /*
1399 * Allocate eeprom data.
1400 */
1401 retval = rt2400pci_validate_eeprom(rt2x00dev);
1402 if (retval)
1403 return retval;
1404
1405 retval = rt2400pci_init_eeprom(rt2x00dev);
1406 if (retval)
1407 return retval;
1408
1409 /*
1410 * Initialize hw specifications.
1411 */
1412 rt2400pci_probe_hw_mode(rt2x00dev);
1413
1414 /*
c4da0048 1415 * This device requires the atim queue and DMA-mapped skbs.
95ea3627 1416 */
181d6902 1417 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
c4da0048 1418 __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
95ea3627
ID		 1419
1420 /*
1421 * Set the rssi offset.
1422 */
1423 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1424
1425 return 0;
1426}
1427
1428/*
1429 * IEEE80211 stack callback functions.
1430 */
1431static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1432 u32 short_retry, u32 long_retry)
1433{
1434 struct rt2x00_dev *rt2x00dev = hw->priv;
1435 u32 reg;
1436
1437 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1438 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1439 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1440 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1441
1442 return 0;
1443}
1444
e100bb64 1445static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
95ea3627
ID		 1446 const struct ieee80211_tx_queue_params *params)
1447{
1448 struct rt2x00_dev *rt2x00dev = hw->priv;
1449
1450 /*
1451 * We don't support variating cw_min and cw_max variables
1452 * per queue. So by default we only configure the TX queue,
1453 * and ignore all other configurations.
1454 */
e100bb64 1455 if (queue != 0)
95ea3627
ID		 1456 return -EINVAL;
1457
1458 if (rt2x00mac_conf_tx(hw, queue, params))
1459 return -EINVAL;
1460
1461 /*
1462 * Write configuration to register.
1463 */
181d6902
ID		 1464 rt2400pci_config_cw(rt2x00dev,
1465 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1466
1467 return 0;
1468}
1469
1470static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1471{
1472 struct rt2x00_dev *rt2x00dev = hw->priv;
1473 u64 tsf;
1474 u32 reg;
1475
1476 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1477 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1478 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1479 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1480
1481 return tsf;
1482}
1483
e039fa4a 1484static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
5957da4c
ID		 1485{
1486 struct rt2x00_dev *rt2x00dev = hw->priv;
e039fa4a
JB		 1487 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1488 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
b8be63ff 1489 struct queue_entry_priv_pci *entry_priv;
5957da4c 1490 struct skb_frame_desc *skbdesc;
7050ec82 1491 struct txentry_desc txdesc;
8af244cc 1492 u32 reg;
5957da4c
ID		 1493
1494 if (unlikely(!intf->beacon))
1495 return -ENOBUFS;
b8be63ff 1496 entry_priv = intf->beacon->priv_data;
5957da4c 1497
7050ec82
ID		 1498 /*
1499 * Copy all TX descriptor information into txdesc,
1500 * after that we are free to use the skb->cb array
1501 * for our information.
1502 */
1503 intf->beacon->skb = skb;
e039fa4a 1504 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
7050ec82 1505
5957da4c
ID		 1506 /*
1507 * Fill in skb descriptor
1508 */
1509 skbdesc = get_skb_frame_desc(skb);
1510 memset(skbdesc, 0, sizeof(*skbdesc));
b8be63ff 1511 skbdesc->desc = entry_priv->desc;
5957da4c
ID		 1512 skbdesc->desc_len = intf->beacon->queue->desc_size;
1513 skbdesc->entry = intf->beacon;
1514
8af244cc
ID		 1515 /*
1516 * Disable beaconing while we are reloading the beacon data,
1517 * otherwise we might be sending out invalid data.
1518 */
1519 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1520 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1521 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1522 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1523 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1524
5957da4c
ID		 1525 /*
1526 * Enable beacon generation.
1527 * Write entire beacon with descriptor to register,
1528 * and kick the beacon generator.
1529 */
c4da0048 1530 rt2x00queue_map_txskb(rt2x00dev, intf->beacon->skb);
7050ec82 1531 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
e58c6aca 1532 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
5957da4c
ID		 1533
1534 return 0;
1535}
1536
95ea3627
ID		 1537static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1538{
1539 struct rt2x00_dev *rt2x00dev = hw->priv;
1540 u32 reg;
1541
1542 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1543 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1544}
1545
1546static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1547 .tx = rt2x00mac_tx,
4150c572
JB		 1548 .start = rt2x00mac_start,
1549 .stop = rt2x00mac_stop,
95ea3627
ID		 1550 .add_interface = rt2x00mac_add_interface,
1551 .remove_interface = rt2x00mac_remove_interface,
1552 .config = rt2x00mac_config,
1553 .config_interface = rt2x00mac_config_interface,
3a643d24 1554 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 1555 .get_stats = rt2x00mac_get_stats,
1556 .set_retry_limit = rt2400pci_set_retry_limit,
471b3efd 1557 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1558 .conf_tx = rt2400pci_conf_tx,
1559 .get_tx_stats = rt2x00mac_get_tx_stats,
1560 .get_tsf = rt2400pci_get_tsf,
5957da4c 1561 .beacon_update = rt2400pci_beacon_update,
95ea3627
ID		 1562 .tx_last_beacon = rt2400pci_tx_last_beacon,
1563};
1564
1565static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1566 .irq_handler = rt2400pci_interrupt,
1567 .probe_hw = rt2400pci_probe_hw,
1568 .initialize = rt2x00pci_initialize,
1569 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1570 .init_rxentry = rt2400pci_init_rxentry,
1571 .init_txentry = rt2400pci_init_txentry,
95ea3627 1572 .set_device_state = rt2400pci_set_device_state,
95ea3627 1573 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1574 .link_stats = rt2400pci_link_stats,
1575 .reset_tuner = rt2400pci_reset_tuner,
1576 .link_tuner = rt2400pci_link_tuner,
1577 .write_tx_desc = rt2400pci_write_tx_desc,
1578 .write_tx_data = rt2x00pci_write_tx_data,
1579 .kick_tx_queue = rt2400pci_kick_tx_queue,
1580 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1581 .config_filter = rt2400pci_config_filter,
6bb40dd1 1582 .config_intf = rt2400pci_config_intf,
72810379 1583 .config_erp = rt2400pci_config_erp,
95ea3627
ID		 1584 .config = rt2400pci_config,
1585};
1586
181d6902
ID		 1587static const struct data_queue_desc rt2400pci_queue_rx = {
1588 .entry_num = RX_ENTRIES,
1589 .data_size = DATA_FRAME_SIZE,
1590 .desc_size = RXD_DESC_SIZE,
b8be63ff 1591 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1592};
1593
1594static const struct data_queue_desc rt2400pci_queue_tx = {
1595 .entry_num = TX_ENTRIES,
1596 .data_size = DATA_FRAME_SIZE,
1597 .desc_size = TXD_DESC_SIZE,
b8be63ff 1598 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1599};
1600
1601static const struct data_queue_desc rt2400pci_queue_bcn = {
1602 .entry_num = BEACON_ENTRIES,
1603 .data_size = MGMT_FRAME_SIZE,
1604 .desc_size = TXD_DESC_SIZE,
b8be63ff 1605 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1606};
1607
1608static const struct data_queue_desc rt2400pci_queue_atim = {
1609 .entry_num = ATIM_ENTRIES,
1610 .data_size = DATA_FRAME_SIZE,
1611 .desc_size = TXD_DESC_SIZE,
b8be63ff 1612 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1613};
1614
95ea3627 1615static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1616 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1617 .max_sta_intf = 1,
1618 .max_ap_intf = 1,
95ea3627
ID		 1619 .eeprom_size = EEPROM_SIZE,
1620 .rf_size = RF_SIZE,
61448f88 1621 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 1622 .rx = &rt2400pci_queue_rx,
1623 .tx = &rt2400pci_queue_tx,
1624 .bcn = &rt2400pci_queue_bcn,
1625 .atim = &rt2400pci_queue_atim,
95ea3627
ID		 1626 .lib = &rt2400pci_rt2x00_ops,
1627 .hw = &rt2400pci_mac80211_ops,
1628#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1629 .debugfs = &rt2400pci_rt2x00debug,
1630#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1631};
1632
1633/*
1634 * RT2400pci module information.
1635 */
1636static struct pci_device_id rt2400pci_device_table[] = {
1637 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1638 { 0, }
1639};
1640
1641MODULE_AUTHOR(DRV_PROJECT);
1642MODULE_VERSION(DRV_VERSION);
1643MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1644MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1645MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1646MODULE_LICENSE("GPL");
1647
1648static struct pci_driver rt2400pci_driver = {
2360157c 1649 .name = KBUILD_MODNAME,
95ea3627
ID		 1650 .id_table = rt2400pci_device_table,
1651 .probe = rt2x00pci_probe,
1652 .remove = __devexit_p(rt2x00pci_remove),
1653 .suspend = rt2x00pci_suspend,
1654 .resume = rt2x00pci_resume,
1655};
1656
1657static int __init rt2400pci_init(void)
1658{
1659 return pci_register_driver(&rt2400pci_driver);
1660}
1661
1662static void __exit rt2400pci_exit(void)
1663{
1664 pci_unregister_driver(&rt2400pci_driver);
1665}
1666
1667module_init(rt2400pci_init);
1668module_exit(rt2400pci_exit);
Linux kernel - Deliverables
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