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rt2x00: Fix RX DMA ring initialization
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 244#endif /* CONFIG_RT2400PCI_RFKILL */
245
a9450b70
ID		 246#ifdef CONFIG_RT2400PCI_LEDS
247static void rt2400pci_led_brightness(struct led_classdev *led_cdev,
248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
253 unsigned int activity =
254 led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
255 u32 reg;
256
257 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
258
259 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
260 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
261 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
262 }
263
264 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
265}
266#else
267#define rt2400pci_led_brightness NULL
268#endif /* CONFIG_RT2400PCI_LEDS */
269
95ea3627
ID		 270/*
271 * Configuration handlers.
272 */
6bb40dd1
ID		 273static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
274 struct rt2x00_intf *intf,
275 struct rt2x00intf_conf *conf,
276 const unsigned int flags)
95ea3627 277{
6bb40dd1
ID		 278 unsigned int bcn_preload;
279 u32 reg;
95ea3627 280
6bb40dd1 281 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 282 /*
283 * Enable beacon config
284 */
285 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
286 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
287 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
288 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 289
6bb40dd1
ID		 290 /*
291 * Enable synchronisation.
292 */
293 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 294 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 295 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 296 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 297 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
298 }
95ea3627 299
6bb40dd1
ID		 300 if (flags & CONFIG_UPDATE_MAC)
301 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
302 conf->mac, sizeof(conf->mac));
95ea3627 303
6bb40dd1
ID		 304 if (flags & CONFIG_UPDATE_BSSID)
305 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
306 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 307}
308
72810379
ID		 309static int rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
310 struct rt2x00lib_erp *erp)
95ea3627 311{
5c58ee51 312 int preamble_mask;
95ea3627 313 u32 reg;
95ea3627 314
5c58ee51
ID		 315 /*
316 * When short preamble is enabled, we should set bit 0x08
317 */
72810379 318 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 319
320 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 321 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
322 erp->ack_timeout);
323 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
324 erp->ack_consume_time);
95ea3627
ID		 325 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
326
95ea3627 327 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
5c58ee51 328 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
95ea3627
ID		 329 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
330 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
331 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
332
333 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 334 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 335 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
336 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
337 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
338
339 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 340 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 341 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
342 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
343 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
344
345 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 346 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 347 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
348 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
349 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
6bb40dd1
ID		 350
351 return 0;
95ea3627
ID		 352}
353
354static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 355 const int basic_rate_mask)
95ea3627 356{
5c58ee51 357 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 358}
359
360static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 361 struct rf_channel *rf)
95ea3627 362{
95ea3627
ID		 363 /*
364 * Switch on tuning bits.
365 */
5c58ee51
ID		 366 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
367 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 368
5c58ee51
ID		 369 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
370 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
371 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 372
373 /*
374 * RF2420 chipset don't need any additional actions.
375 */
376 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
377 return;
378
379 /*
380 * For the RT2421 chipsets we need to write an invalid
381 * reference clock rate to activate auto_tune.
382 * After that we set the value back to the correct channel.
383 */
5c58ee51 384 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 385 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 386 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 387
388 msleep(1);
389
5c58ee51
ID		 390 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
391 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
392 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 393
394 msleep(1);
395
396 /*
397 * Switch off tuning bits.
398 */
5c58ee51
ID		 399 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
400 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 401
5c58ee51
ID		 402 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
403 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 404
405 /*
406 * Clear false CRC during channel switch.
407 */
5c58ee51 408 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 409}
410
411static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
412{
413 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
414}
415
416static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 417 struct antenna_setup *ant)
95ea3627
ID		 418{
419 u8 r1;
420 u8 r4;
421
a4fe07d9
ID		 422 /*
423 * We should never come here because rt2x00lib is supposed
424 * to catch this and send us the correct antenna explicitely.
425 */
426 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
427 ant->tx == ANTENNA_SW_DIVERSITY);
428
95ea3627
ID		 429 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
430 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
431
432 /*
433 * Configure the TX antenna.
434 */
addc81bd 435 switch (ant->tx) {
95ea3627
ID		 436 case ANTENNA_HW_DIVERSITY:
437 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
438 break;
439 case ANTENNA_A:
440 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
441 break;
442 case ANTENNA_B:
a4fe07d9 443 default:
95ea3627
ID		 444 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
445 break;
446 }
447
448 /*
449 * Configure the RX antenna.
450 */
addc81bd 451 switch (ant->rx) {
95ea3627
ID		 452 case ANTENNA_HW_DIVERSITY:
453 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
454 break;
455 case ANTENNA_A:
456 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
457 break;
458 case ANTENNA_B:
a4fe07d9 459 default:
95ea3627
ID		 460 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
461 break;
462 }
463
464 rt2400pci_bbp_write(rt2x00dev, 4, r4);
465 rt2400pci_bbp_write(rt2x00dev, 1, r1);
466}
467
468static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 469 struct rt2x00lib_conf *libconf)
95ea3627
ID		 470{
471 u32 reg;
472
473 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 474 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 475 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
476
477 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 478 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
479 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 480 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
481
482 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 483 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
484 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 485 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
486
487 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
488 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
489 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
490 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
491
492 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 493 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
494 libconf->conf->beacon_int * 16);
495 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
496 libconf->conf->beacon_int * 16);
95ea3627
ID		 497 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
498}
499
500static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 501 struct rt2x00lib_conf *libconf,
502 const unsigned int flags)
95ea3627 503{
95ea3627 504 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 505 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 506 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 507 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 508 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 509 rt2400pci_config_txpower(rt2x00dev,
510 libconf->conf->power_level);
95ea3627 511 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 512 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 513 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 514 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 515}
516
517static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 518 const int cw_min, const int cw_max)
95ea3627
ID		 519{
520 u32 reg;
521
522 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 523 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
524 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 525 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
526}
527
95ea3627
ID		 528/*
529 * Link tuning
530 */
ebcf26da
ID		 531static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
532 struct link_qual *qual)
95ea3627
ID		 533{
534 u32 reg;
535 u8 bbp;
536
537 /*
538 * Update FCS error count from register.
539 */
540 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 541 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 542
543 /*
544 * Update False CCA count from register.
545 */
546 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 547 qual->false_cca = bbp;
95ea3627
ID		 548}
549
550static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
551{
552 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
553 rt2x00dev->link.vgc_level = 0x08;
554}
555
556static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
557{
558 u8 reg;
559
560 /*
561 * The link tuner should not run longer then 60 seconds,
562 * and should run once every 2 seconds.
563 */
564 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
565 return;
566
567 /*
568 * Base r13 link tuning on the false cca count.
569 */
570 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
571
ebcf26da 572 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 573 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
574 rt2x00dev->link.vgc_level = reg;
ebcf26da 575 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 576 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
577 rt2x00dev->link.vgc_level = reg;
578 }
579}
580
581/*
582 * Initialization functions.
583 */
837e7f24 584static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 585 struct queue_entry *entry)
95ea3627 586{
181d6902 587 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 588 u32 word;
589
181d6902 590 rt2x00_desc_read(priv_rx->desc, 2, &word);
30b3a23c
ID		 591 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
592 entry->queue->data_size);
181d6902 593 rt2x00_desc_write(priv_rx->desc, 2, word);
95ea3627 594
181d6902 595 rt2x00_desc_read(priv_rx->desc, 1, &word);
30b3a23c 596 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
181d6902 597 rt2x00_desc_write(priv_rx->desc, 1, word);
95ea3627 598
181d6902 599 rt2x00_desc_read(priv_rx->desc, 0, &word);
837e7f24 600 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
181d6902 601 rt2x00_desc_write(priv_rx->desc, 0, word);
95ea3627
ID		 602}
603
837e7f24 604static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 605 struct queue_entry *entry)
95ea3627 606{
181d6902 607 struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
95ea3627
ID		 608 u32 word;
609
181d6902 610 rt2x00_desc_read(priv_tx->desc, 1, &word);
30b3a23c 611 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
181d6902 612 rt2x00_desc_write(priv_tx->desc, 1, word);
95ea3627 613
181d6902
ID		 614 rt2x00_desc_read(priv_tx->desc, 2, &word);
615 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
616 entry->queue->data_size);
617 rt2x00_desc_write(priv_tx->desc, 2, word);
95ea3627 618
181d6902 619 rt2x00_desc_read(priv_tx->desc, 0, &word);
837e7f24
ID		 620 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
621 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
181d6902 622 rt2x00_desc_write(priv_tx->desc, 0, word);
95ea3627
ID		 623}
624
181d6902 625static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 626{
181d6902
ID		 627 struct queue_entry_priv_pci_rx *priv_rx;
628 struct queue_entry_priv_pci_tx *priv_tx;
95ea3627
ID		 629 u32 reg;
630
95ea3627
ID		 631 /*
632 * Initialize registers.
633 */
634 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 635 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
636 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
637 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
638 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 639 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
640
181d6902 641 priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 642 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c
ID		 643 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
644 priv_tx->desc_dma);
95ea3627
ID		 645 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
646
181d6902 647 priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 648 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c
ID		 649 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
650 priv_tx->desc_dma);
95ea3627
ID		 651 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
652
181d6902 653 priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 654 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c
ID		 655 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
656 priv_tx->desc_dma);
95ea3627
ID		 657 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
658
181d6902 659 priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 660 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c
ID		 661 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
662 priv_tx->desc_dma);
95ea3627
ID		 663 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
664
665 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
666 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 667 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 668 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
669
181d6902 670 priv_rx = rt2x00dev->rx->entries[0].priv_data;
95ea3627 671 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
dac37d72 672 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
95ea3627
ID		 673 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
674
675 return 0;
676}
677
678static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
679{
680 u32 reg;
681
682 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
683 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
684 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
685 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
686
687 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
688 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
689 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
690 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
691 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
692
693 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
694 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
695 (rt2x00dev->rx->data_size / 128));
696 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
697
a9450b70
ID		 698 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
699 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
700 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
701 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
702
95ea3627
ID		 703 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
704
705 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
706 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
707 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
708 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
709 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
710 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
711
712 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
713 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
714 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
715 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
716 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
717 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
718 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
719 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
720
721 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
722
723 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
724 return -EBUSY;
725
726 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
727 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
728
729 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
730 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
731 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
732
733 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
734 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
735 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
736 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
737 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
738 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
739
740 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
741 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
742 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
743 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
744 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
745
746 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
747 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
748 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
749 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
750
751 /*
752 * We must clear the FCS and FIFO error count.
753 * These registers are cleared on read,
754 * so we may pass a useless variable to store the value.
755 */
756 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
757 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
758
759 return 0;
760}
761
762static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
763{
764 unsigned int i;
765 u16 eeprom;
766 u8 reg_id;
767 u8 value;
768
769 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
770 rt2400pci_bbp_read(rt2x00dev, 0, &value);
771 if ((value != 0xff) && (value != 0x00))
772 goto continue_csr_init;
773 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
774 udelay(REGISTER_BUSY_DELAY);
775 }
776
777 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
778 return -EACCES;
779
780continue_csr_init:
781 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
782 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
783 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
784 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
785 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
786 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
787 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
788 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
789 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
790 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
791 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
792 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
793 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
794 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
795
95ea3627
ID		 796 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
797 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
798
799 if (eeprom != 0xffff && eeprom != 0x0000) {
800 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
801 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 802 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
803 }
804 }
95ea3627
ID		 805
806 return 0;
807}
808
809/*
810 * Device state switch handlers.
811 */
812static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
813 enum dev_state state)
814{
815 u32 reg;
816
817 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
818 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
819 state == STATE_RADIO_RX_OFF);
820 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
821}
822
823static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
824 enum dev_state state)
825{
826 int mask = (state == STATE_RADIO_IRQ_OFF);
827 u32 reg;
828
829 /*
830 * When interrupts are being enabled, the interrupt registers
831 * should clear the register to assure a clean state.
832 */
833 if (state == STATE_RADIO_IRQ_ON) {
834 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
835 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
836 }
837
838 /*
839 * Only toggle the interrupts bits we are going to use.
840 * Non-checked interrupt bits are disabled by default.
841 */
842 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
843 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
844 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
845 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
846 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
847 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
848 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
849}
850
851static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
852{
853 /*
854 * Initialize all registers.
855 */
181d6902 856 if (rt2400pci_init_queues(rt2x00dev) ||
95ea3627
ID		 857 rt2400pci_init_registers(rt2x00dev) ||
858 rt2400pci_init_bbp(rt2x00dev)) {
859 ERROR(rt2x00dev, "Register initialization failed.\n");
860 return -EIO;
861 }
862
863 /*
864 * Enable interrupts.
865 */
866 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
867
95ea3627
ID		 868 return 0;
869}
870
871static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
872{
873 u32 reg;
874
95ea3627
ID		 875 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
876
877 /*
878 * Disable synchronisation.
879 */
880 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
881
882 /*
883 * Cancel RX and TX.
884 */
885 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
886 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
887 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
888
889 /*
890 * Disable interrupts.
891 */
892 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
893}
894
895static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
896 enum dev_state state)
897{
898 u32 reg;
899 unsigned int i;
900 char put_to_sleep;
901 char bbp_state;
902 char rf_state;
903
904 put_to_sleep = (state != STATE_AWAKE);
905
906 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
907 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
908 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
909 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
910 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
911 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
912
913 /*
914 * Device is not guaranteed to be in the requested state yet.
915 * We must wait until the register indicates that the
916 * device has entered the correct state.
917 */
918 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
919 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
920 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
921 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
922 if (bbp_state == state && rf_state == state)
923 return 0;
924 msleep(10);
925 }
926
927 NOTICE(rt2x00dev, "Device failed to enter state %d, "
928 "current device state: bbp %d and rf %d.\n",
929 state, bbp_state, rf_state);
930
931 return -EBUSY;
932}
933
934static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
935 enum dev_state state)
936{
937 int retval = 0;
938
939 switch (state) {
940 case STATE_RADIO_ON:
941 retval = rt2400pci_enable_radio(rt2x00dev);
942 break;
943 case STATE_RADIO_OFF:
944 rt2400pci_disable_radio(rt2x00dev);
945 break;
946 case STATE_RADIO_RX_ON:
61667d8d
ID		 947 case STATE_RADIO_RX_ON_LINK:
948 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
949 break;
95ea3627 950 case STATE_RADIO_RX_OFF:
61667d8d
ID		 951 case STATE_RADIO_RX_OFF_LINK:
952 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 953 break;
954 case STATE_DEEP_SLEEP:
955 case STATE_SLEEP:
956 case STATE_STANDBY:
957 case STATE_AWAKE:
958 retval = rt2400pci_set_state(rt2x00dev, state);
959 break;
960 default:
961 retval = -ENOTSUPP;
962 break;
963 }
964
965 return retval;
966}
967
968/*
969 * TX descriptor initialization
970 */
971static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 972 struct sk_buff *skb,
181d6902 973 struct txentry_desc *txdesc,
95ea3627
ID		 974 struct ieee80211_tx_control *control)
975{
181d6902 976 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
dd3193e1 977 __le32 *txd = skbdesc->desc;
95ea3627 978 u32 word;
95ea3627
ID		 979
980 /*
981 * Start writing the descriptor words.
982 */
983 rt2x00_desc_read(txd, 2, &word);
dd3193e1 984 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 985 rt2x00_desc_write(txd, 2, word);
986
987 rt2x00_desc_read(txd, 3, &word);
181d6902 988 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 989 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
990 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 991 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 992 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
993 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 994 rt2x00_desc_write(txd, 3, word);
995
996 rt2x00_desc_read(txd, 4, &word);
181d6902 997 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 998 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
999 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1000 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1001 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1002 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1003 rt2x00_desc_write(txd, 4, word);
1004
1005 rt2x00_desc_read(txd, 0, &word);
1006 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1007 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1008 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1009 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1010 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1011 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1012 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1013 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1014 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1015 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1016 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627
ID		 1017 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1018 !!(control->flags &
1019 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1020 rt2x00_desc_write(txd, 0, word);
1021}
1022
1023/*
1024 * TX data initialization
1025 */
1026static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
5957da4c 1027 const unsigned int queue)
95ea3627
ID		 1028{
1029 u32 reg;
1030
5957da4c 1031 if (queue == RT2X00_BCN_QUEUE_BEACON) {
95ea3627
ID		 1032 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1033 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1034 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1035 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1036 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1037 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1038 }
1039 return;
1040 }
1041
1042 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
ddc827f9
ID		 1043 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1044 (queue == IEEE80211_TX_QUEUE_DATA0));
1045 rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1046 (queue == IEEE80211_TX_QUEUE_DATA1));
1047 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
5957da4c 1048 (queue == RT2X00_BCN_QUEUE_ATIM));
95ea3627
ID		 1049 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1050}
1051
1052/*
1053 * RX control handlers
1054 */
181d6902
ID		 1055static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1056 struct rxdone_entry_desc *rxdesc)
95ea3627 1057{
181d6902 1058 struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
95ea3627
ID		 1059 u32 word0;
1060 u32 word2;
1061
181d6902
ID		 1062 rt2x00_desc_read(priv_rx->desc, 0, &word0);
1063 rt2x00_desc_read(priv_rx->desc, 2, &word2);
95ea3627 1064
181d6902 1065 rxdesc->flags = 0;
4150c572 1066 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1067 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1068 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1069 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1070
1071 /*
1072 * Obtain the status about this packet.
1073 */
181d6902
ID		 1074 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1075 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1076 entry->queue->rt2x00dev->rssi_offset;
1077 rxdesc->ofdm = 0;
1078 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1079 rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
95ea3627
ID		 1080}
1081
1082/*
1083 * Interrupt functions.
1084 */
181d6902
ID		 1085static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1086 const enum ieee80211_tx_queue queue_idx)
95ea3627 1087{
181d6902
ID		 1088 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1089 struct queue_entry_priv_pci_tx *priv_tx;
1090 struct queue_entry *entry;
1091 struct txdone_entry_desc txdesc;
95ea3627 1092 u32 word;
95ea3627 1093
181d6902
ID		 1094 while (!rt2x00queue_empty(queue)) {
1095 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1096 priv_tx = entry->priv_data;
1097 rt2x00_desc_read(priv_tx->desc, 0, &word);
95ea3627
ID		 1098
1099 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1100 !rt2x00_get_field32(word, TXD_W0_VALID))
1101 break;
1102
1103 /*
1104 * Obtain the status about this packet.
1105 */
181d6902
ID		 1106 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1107 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1108
181d6902 1109 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1110 }
95ea3627
ID		 1111}
1112
1113static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1114{
1115 struct rt2x00_dev *rt2x00dev = dev_instance;
1116 u32 reg;
1117
1118 /*
1119 * Get the interrupt sources & saved to local variable.
1120 * Write register value back to clear pending interrupts.
1121 */
1122 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1123 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1124
1125 if (!reg)
1126 return IRQ_NONE;
1127
1128 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1129 return IRQ_HANDLED;
1130
1131 /*
1132 * Handle interrupts, walk through all bits
1133 * and run the tasks, the bits are checked in order of
1134 * priority.
1135 */
1136
1137 /*
1138 * 1 - Beacon timer expired interrupt.
1139 */
1140 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1141 rt2x00lib_beacondone(rt2x00dev);
1142
1143 /*
1144 * 2 - Rx ring done interrupt.
1145 */
1146 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1147 rt2x00pci_rxdone(rt2x00dev);
1148
1149 /*
1150 * 3 - Atim ring transmit done interrupt.
1151 */
1152 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
5957da4c 1153 rt2400pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
95ea3627
ID		 1154
1155 /*
1156 * 4 - Priority ring transmit done interrupt.
1157 */
1158 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1159 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1160
1161 /*
1162 * 5 - Tx ring transmit done interrupt.
1163 */
1164 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1165 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1166
1167 return IRQ_HANDLED;
1168}
1169
1170/*
1171 * Device probe functions.
1172 */
1173static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1174{
1175 struct eeprom_93cx6 eeprom;
1176 u32 reg;
1177 u16 word;
1178 u8 *mac;
1179
1180 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1181
1182 eeprom.data = rt2x00dev;
1183 eeprom.register_read = rt2400pci_eepromregister_read;
1184 eeprom.register_write = rt2400pci_eepromregister_write;
1185 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1186 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1187 eeprom.reg_data_in = 0;
1188 eeprom.reg_data_out = 0;
1189 eeprom.reg_data_clock = 0;
1190 eeprom.reg_chip_select = 0;
1191
1192 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1193 EEPROM_SIZE / sizeof(u16));
1194
1195 /*
1196 * Start validation of the data that has been read.
1197 */
1198 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1199 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1200 DECLARE_MAC_BUF(macbuf);
1201
95ea3627 1202 random_ether_addr(mac);
0795af57 1203 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1204 }
1205
1206 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1207 if (word == 0xffff) {
1208 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1209 return -EINVAL;
1210 }
1211
1212 return 0;
1213}
1214
1215static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1216{
1217 u32 reg;
1218 u16 value;
1219 u16 eeprom;
1220
1221 /*
1222 * Read EEPROM word for configuration.
1223 */
1224 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1225
1226 /*
1227 * Identify RF chipset.
1228 */
1229 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1230 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1231 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1232
1233 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1234 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1235 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1236 return -ENODEV;
1237 }
1238
1239 /*
1240 * Identify default antenna configuration.
1241 */
addc81bd 1242 rt2x00dev->default_ant.tx =
95ea3627 1243 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1244 rt2x00dev->default_ant.rx =
95ea3627
ID		 1245 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1246
addc81bd
ID		 1247 /*
1248 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1249 * I am not 100% sure about this, but the legacy drivers do not
1250 * indicate antenna swapping in software is required when
1251 * diversity is enabled.
1252 */
1253 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1254 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1255 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1256 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1257
95ea3627
ID		 1258 /*
1259 * Store led mode, for correct led behaviour.
1260 */
a9450b70
ID		 1261#ifdef CONFIG_RT2400PCI_LEDS
1262 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1263
1264 switch (value) {
1265 case LED_MODE_ASUS:
1266 case LED_MODE_ALPHA:
1267 case LED_MODE_DEFAULT:
1268 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1269 break;
1270 case LED_MODE_TXRX_ACTIVITY:
1271 rt2x00dev->led_flags =
1272 LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1273 break;
1274 case LED_MODE_SIGNAL_STRENGTH:
1275 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1276 break;
1277 }
1278#endif /* CONFIG_RT2400PCI_LEDS */
95ea3627
ID		 1279
1280 /*
1281 * Detect if this device has an hardware controlled radio.
1282 */
81873e9c 1283#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1284 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1285 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1286#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1287
1288 /*
1289 * Check if the BBP tuning should be enabled.
1290 */
1291 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1292 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1293
1294 return 0;
1295}
1296
1297/*
1298 * RF value list for RF2420 & RF2421
1299 * Supports: 2.4 GHz
1300 */
1301static const struct rf_channel rf_vals_bg[] = {
1302 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1303 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1304 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1305 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1306 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1307 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1308 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1309 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1310 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1311 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1312 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1313 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1314 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1315 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1316};
1317
1318static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1319{
1320 struct hw_mode_spec *spec = &rt2x00dev->spec;
1321 u8 *txpower;
1322 unsigned int i;
1323
1324 /*
1325 * Initialize all hw fields.
1326 */
4150c572 1327 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1328 rt2x00dev->hw->extra_tx_headroom = 0;
1329 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1330 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1331 rt2x00dev->hw->queues = 2;
1332
1333 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1334 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1335 rt2x00_eeprom_addr(rt2x00dev,
1336 EEPROM_MAC_ADDR_0));
1337
1338 /*
1339 * Convert tx_power array in eeprom.
1340 */
1341 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1342 for (i = 0; i < 14; i++)
1343 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1344
1345 /*
1346 * Initialize hw_mode information.
1347 */
31562e80
ID		 1348 spec->supported_bands = SUPPORT_BAND_2GHZ;
1349 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627
ID		 1350 spec->tx_power_a = NULL;
1351 spec->tx_power_bg = txpower;
1352 spec->tx_power_default = DEFAULT_TXPOWER;
1353
1354 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1355 spec->channels = rf_vals_bg;
1356}
1357
1358static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1359{
1360 int retval;
1361
1362 /*
1363 * Allocate eeprom data.
1364 */
1365 retval = rt2400pci_validate_eeprom(rt2x00dev);
1366 if (retval)
1367 return retval;
1368
1369 retval = rt2400pci_init_eeprom(rt2x00dev);
1370 if (retval)
1371 return retval;
1372
1373 /*
1374 * Initialize hw specifications.
1375 */
1376 rt2400pci_probe_hw_mode(rt2x00dev);
1377
1378 /*
181d6902 1379 * This device requires the atim queue
95ea3627 1380 */
181d6902 1381 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1382
1383 /*
1384 * Set the rssi offset.
1385 */
1386 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1387
1388 return 0;
1389}
1390
1391/*
1392 * IEEE80211 stack callback functions.
1393 */
4150c572
JB		 1394static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1395 unsigned int changed_flags,
1396 unsigned int *total_flags,
1397 int mc_count,
1398 struct dev_addr_list *mc_list)
1399{
1400 struct rt2x00_dev *rt2x00dev = hw->priv;
4150c572
JB		 1401 u32 reg;
1402
1403 /*
1404 * Mask off any flags we are going to ignore from
1405 * the total_flags field.
1406 */
1407 *total_flags &=
1408 FIF_ALLMULTI |
1409 FIF_FCSFAIL |
1410 FIF_PLCPFAIL |
1411 FIF_CONTROL |
1412 FIF_OTHER_BSS |
1413 FIF_PROMISC_IN_BSS;
1414
1415 /*
1416 * Apply some rules to the filters:
1417 * - Some filters imply different filters to be set.
1418 * - Some things we can't filter out at all.
4150c572
JB		 1419 */
1420 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1421 if (*total_flags & FIF_OTHER_BSS ||
1422 *total_flags & FIF_PROMISC_IN_BSS)
4150c572 1423 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
4150c572
JB		 1424
1425 /*
1426 * Check if there is any work left for us.
1427 */
3c4f2085 1428 if (rt2x00dev->packet_filter == *total_flags)
4150c572 1429 return;
3c4f2085 1430 rt2x00dev->packet_filter = *total_flags;
4150c572
JB		 1431
1432 /*
1433 * Start configuration steps.
1434 * Note that the version error will always be dropped
1435 * since there is no filter for it at this time.
1436 */
1437 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1438 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1439 !(*total_flags & FIF_FCSFAIL));
1440 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1441 !(*total_flags & FIF_PLCPFAIL));
1442 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1443 !(*total_flags & FIF_CONTROL));
1444 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1445 !(*total_flags & FIF_PROMISC_IN_BSS));
1446 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1447 !(*total_flags & FIF_PROMISC_IN_BSS));
1448 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1449 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1450}
1451
95ea3627
ID		 1452static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1453 u32 short_retry, u32 long_retry)
1454{
1455 struct rt2x00_dev *rt2x00dev = hw->priv;
1456 u32 reg;
1457
1458 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1459 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1460 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1461 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1462
1463 return 0;
1464}
1465
1466static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1467 int queue,
1468 const struct ieee80211_tx_queue_params *params)
1469{
1470 struct rt2x00_dev *rt2x00dev = hw->priv;
1471
1472 /*
1473 * We don't support variating cw_min and cw_max variables
1474 * per queue. So by default we only configure the TX queue,
1475 * and ignore all other configurations.
1476 */
1477 if (queue != IEEE80211_TX_QUEUE_DATA0)
1478 return -EINVAL;
1479
1480 if (rt2x00mac_conf_tx(hw, queue, params))
1481 return -EINVAL;
1482
1483 /*
1484 * Write configuration to register.
1485 */
181d6902
ID		 1486 rt2400pci_config_cw(rt2x00dev,
1487 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1488
1489 return 0;
1490}
1491
1492static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1493{
1494 struct rt2x00_dev *rt2x00dev = hw->priv;
1495 u64 tsf;
1496 u32 reg;
1497
1498 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1499 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1500 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1501 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1502
1503 return tsf;
1504}
1505
5957da4c
ID		 1506static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1507 struct ieee80211_tx_control *control)
1508{
1509 struct rt2x00_dev *rt2x00dev = hw->priv;
1510 struct rt2x00_intf *intf = vif_to_intf(control->vif);
1511 struct queue_entry_priv_pci_tx *priv_tx;
1512 struct skb_frame_desc *skbdesc;
8af244cc 1513 u32 reg;
5957da4c
ID		 1514
1515 if (unlikely(!intf->beacon))
1516 return -ENOBUFS;
5957da4c
ID		 1517 priv_tx = intf->beacon->priv_data;
1518
1519 /*
1520 * Fill in skb descriptor
1521 */
1522 skbdesc = get_skb_frame_desc(skb);
1523 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1524 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
5957da4c
ID		 1525 skbdesc->data = skb->data;
1526 skbdesc->data_len = skb->len;
1527 skbdesc->desc = priv_tx->desc;
1528 skbdesc->desc_len = intf->beacon->queue->desc_size;
1529 skbdesc->entry = intf->beacon;
1530
8af244cc
ID		 1531 /*
1532 * Disable beaconing while we are reloading the beacon data,
1533 * otherwise we might be sending out invalid data.
1534 */
1535 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1536 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1537 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1538 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1539 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1540
5957da4c
ID		 1541 /*
1542 * mac80211 doesn't provide the control->queue variable
1543 * for beacons. Set our own queue identification so
1544 * it can be used during descriptor initialization.
1545 */
1546 control->queue = RT2X00_BCN_QUEUE_BEACON;
1547 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1548
1549 /*
1550 * Enable beacon generation.
1551 * Write entire beacon with descriptor to register,
1552 * and kick the beacon generator.
1553 */
1554 memcpy(priv_tx->data, skb->data, skb->len);
1555 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1556
1557 return 0;
1558}
1559
95ea3627
ID		 1560static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1561{
1562 struct rt2x00_dev *rt2x00dev = hw->priv;
1563 u32 reg;
1564
1565 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1566 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1567}
1568
1569static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1570 .tx = rt2x00mac_tx,
4150c572
JB		 1571 .start = rt2x00mac_start,
1572 .stop = rt2x00mac_stop,
95ea3627
ID		 1573 .add_interface = rt2x00mac_add_interface,
1574 .remove_interface = rt2x00mac_remove_interface,
1575 .config = rt2x00mac_config,
1576 .config_interface = rt2x00mac_config_interface,
4150c572 1577 .configure_filter = rt2400pci_configure_filter,
95ea3627
ID		 1578 .get_stats = rt2x00mac_get_stats,
1579 .set_retry_limit = rt2400pci_set_retry_limit,
471b3efd 1580 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1581 .conf_tx = rt2400pci_conf_tx,
1582 .get_tx_stats = rt2x00mac_get_tx_stats,
1583 .get_tsf = rt2400pci_get_tsf,
5957da4c 1584 .beacon_update = rt2400pci_beacon_update,
95ea3627
ID		 1585 .tx_last_beacon = rt2400pci_tx_last_beacon,
1586};
1587
1588static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1589 .irq_handler = rt2400pci_interrupt,
1590 .probe_hw = rt2400pci_probe_hw,
1591 .initialize = rt2x00pci_initialize,
1592 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1593 .init_rxentry = rt2400pci_init_rxentry,
1594 .init_txentry = rt2400pci_init_txentry,
95ea3627 1595 .set_device_state = rt2400pci_set_device_state,
95ea3627 1596 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1597 .link_stats = rt2400pci_link_stats,
1598 .reset_tuner = rt2400pci_reset_tuner,
1599 .link_tuner = rt2400pci_link_tuner,
a9450b70 1600 .led_brightness = rt2400pci_led_brightness,
95ea3627
ID		 1601 .write_tx_desc = rt2400pci_write_tx_desc,
1602 .write_tx_data = rt2x00pci_write_tx_data,
1603 .kick_tx_queue = rt2400pci_kick_tx_queue,
1604 .fill_rxdone = rt2400pci_fill_rxdone,
6bb40dd1 1605 .config_intf = rt2400pci_config_intf,
72810379 1606 .config_erp = rt2400pci_config_erp,
95ea3627
ID		 1607 .config = rt2400pci_config,
1608};
1609
181d6902
ID		 1610static const struct data_queue_desc rt2400pci_queue_rx = {
1611 .entry_num = RX_ENTRIES,
1612 .data_size = DATA_FRAME_SIZE,
1613 .desc_size = RXD_DESC_SIZE,
1614 .priv_size = sizeof(struct queue_entry_priv_pci_rx),
1615};
1616
1617static const struct data_queue_desc rt2400pci_queue_tx = {
1618 .entry_num = TX_ENTRIES,
1619 .data_size = DATA_FRAME_SIZE,
1620 .desc_size = TXD_DESC_SIZE,
1621 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1622};
1623
1624static const struct data_queue_desc rt2400pci_queue_bcn = {
1625 .entry_num = BEACON_ENTRIES,
1626 .data_size = MGMT_FRAME_SIZE,
1627 .desc_size = TXD_DESC_SIZE,
1628 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1629};
1630
1631static const struct data_queue_desc rt2400pci_queue_atim = {
1632 .entry_num = ATIM_ENTRIES,
1633 .data_size = DATA_FRAME_SIZE,
1634 .desc_size = TXD_DESC_SIZE,
1635 .priv_size = sizeof(struct queue_entry_priv_pci_tx),
1636};
1637
95ea3627 1638static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1639 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1640 .max_sta_intf = 1,
1641 .max_ap_intf = 1,
95ea3627
ID		 1642 .eeprom_size = EEPROM_SIZE,
1643 .rf_size = RF_SIZE,
181d6902
ID		 1644 .rx = &rt2400pci_queue_rx,
1645 .tx = &rt2400pci_queue_tx,
1646 .bcn = &rt2400pci_queue_bcn,
1647 .atim = &rt2400pci_queue_atim,
95ea3627
ID		 1648 .lib = &rt2400pci_rt2x00_ops,
1649 .hw = &rt2400pci_mac80211_ops,
1650#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1651 .debugfs = &rt2400pci_rt2x00debug,
1652#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1653};
1654
1655/*
1656 * RT2400pci module information.
1657 */
1658static struct pci_device_id rt2400pci_device_table[] = {
1659 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1660 { 0, }
1661};
1662
1663MODULE_AUTHOR(DRV_PROJECT);
1664MODULE_VERSION(DRV_VERSION);
1665MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1666MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1667MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1668MODULE_LICENSE("GPL");
1669
1670static struct pci_driver rt2400pci_driver = {
2360157c 1671 .name = KBUILD_MODNAME,
95ea3627
ID		 1672 .id_table = rt2400pci_device_table,
1673 .probe = rt2x00pci_probe,
1674 .remove = __devexit_p(rt2x00pci_remove),
1675 .suspend = rt2x00pci_suspend,
1676 .resume = rt2x00pci_resume,
1677};
1678
1679static int __init rt2400pci_init(void)
1680{
1681 return pci_register_driver(&rt2400pci_driver);
1682}
1683
1684static void __exit rt2400pci_exit(void)
1685{
1686 pci_unregister_driver(&rt2400pci_driver);
1687}
1688
1689module_init(rt2400pci_init);
1690module_exit(rt2400pci_exit);
Linux kernel - Deliverables
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