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mac80211: move TX info into skb->cb
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2400pci.c
CommitLineData
95ea3627 1/*
811aa9ca 2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
95ea3627
ID		 3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2400pci
23 Abstract: rt2400pci device specific routines.
24 Supported chipsets: RT2460.
25 */
26
95ea3627
ID		 27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/init.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/pci.h>
33#include <linux/eeprom_93cx6.h>
34
35#include "rt2x00.h"
36#include "rt2x00pci.h"
37#include "rt2400pci.h"
38
39/*
40 * Register access.
41 * All access to the CSR registers will go through the methods
42 * rt2x00pci_register_read and rt2x00pci_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 */
0e14f6d3 52static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
95ea3627
ID		 53{
54 u32 reg;
55 unsigned int i;
56
57 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
58 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
59 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
60 break;
61 udelay(REGISTER_BUSY_DELAY);
62 }
63
64 return reg;
65}
66
0e14f6d3 67static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 68 const unsigned int word, const u8 value)
69{
70 u32 reg;
71
72 /*
73 * Wait until the BBP becomes ready.
74 */
75 reg = rt2400pci_bbp_check(rt2x00dev);
76 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
77 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
78 return;
79 }
80
81 /*
82 * Write the data into the BBP.
83 */
84 reg = 0;
85 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
86 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
87 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
88 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
89
90 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
91}
92
0e14f6d3 93static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 94 const unsigned int word, u8 *value)
95{
96 u32 reg;
97
98 /*
99 * Wait until the BBP becomes ready.
100 */
101 reg = rt2400pci_bbp_check(rt2x00dev);
102 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
103 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
104 return;
105 }
106
107 /*
108 * Write the request into the BBP.
109 */
110 reg = 0;
111 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
112 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
113 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
114
115 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
116
117 /*
118 * Wait until the BBP becomes ready.
119 */
120 reg = rt2400pci_bbp_check(rt2x00dev);
121 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
122 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
123 *value = 0xff;
124 return;
125 }
126
127 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
128}
129
0e14f6d3 130static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 131 const unsigned int word, const u32 value)
132{
133 u32 reg;
134 unsigned int i;
135
136 if (!word)
137 return;
138
139 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
140 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
141 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
142 goto rf_write;
143 udelay(REGISTER_BUSY_DELAY);
144 }
145
146 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
147 return;
148
149rf_write:
150 reg = 0;
151 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
152 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
153 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
154 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
155
156 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
157 rt2x00_rf_write(rt2x00dev, word, value);
158}
159
160static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
161{
162 struct rt2x00_dev *rt2x00dev = eeprom->data;
163 u32 reg;
164
165 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
166
167 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
168 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
169 eeprom->reg_data_clock =
170 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
171 eeprom->reg_chip_select =
172 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
173}
174
175static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
176{
177 struct rt2x00_dev *rt2x00dev = eeprom->data;
178 u32 reg = 0;
179
180 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
181 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
182 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
183 !!eeprom->reg_data_clock);
184 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
185 !!eeprom->reg_chip_select);
186
187 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
188}
189
190#ifdef CONFIG_RT2X00_LIB_DEBUGFS
191#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
192
0e14f6d3 193static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 194 const unsigned int word, u32 *data)
195{
196 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
197}
198
0e14f6d3 199static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
95ea3627
ID		 200 const unsigned int word, u32 data)
201{
202 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
203}
204
205static const struct rt2x00debug rt2400pci_rt2x00debug = {
206 .owner = THIS_MODULE,
207 .csr = {
208 .read = rt2400pci_read_csr,
209 .write = rt2400pci_write_csr,
210 .word_size = sizeof(u32),
211 .word_count = CSR_REG_SIZE / sizeof(u32),
212 },
213 .eeprom = {
214 .read = rt2x00_eeprom_read,
215 .write = rt2x00_eeprom_write,
216 .word_size = sizeof(u16),
217 .word_count = EEPROM_SIZE / sizeof(u16),
218 },
219 .bbp = {
220 .read = rt2400pci_bbp_read,
221 .write = rt2400pci_bbp_write,
222 .word_size = sizeof(u8),
223 .word_count = BBP_SIZE / sizeof(u8),
224 },
225 .rf = {
226 .read = rt2x00_rf_read,
227 .write = rt2400pci_rf_write,
228 .word_size = sizeof(u32),
229 .word_count = RF_SIZE / sizeof(u32),
230 },
231};
232#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
233
234#ifdef CONFIG_RT2400PCI_RFKILL
235static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
236{
237 u32 reg;
238
239 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
240 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
241}
81873e9c
ID		 242#else
243#define rt2400pci_rfkill_poll NULL
95ea3627
ID		 244#endif /* CONFIG_RT2400PCI_RFKILL */
245
a9450b70 246#ifdef CONFIG_RT2400PCI_LEDS
a2e1d52a 247static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
a9450b70
ID		 248 enum led_brightness brightness)
249{
250 struct rt2x00_led *led =
251 container_of(led_cdev, struct rt2x00_led, led_dev);
252 unsigned int enabled = brightness != LED_OFF;
a9450b70
ID		 253 u32 reg;
254
255 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
256
a2e1d52a 257 if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
a9450b70 258 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
a2e1d52a
ID		 259 else if (led->type == LED_TYPE_ACTIVITY)
260 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
a9450b70
ID		 261
262 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
263}
a2e1d52a
ID		 264
265static int rt2400pci_blink_set(struct led_classdev *led_cdev,
266 unsigned long *delay_on,
267 unsigned long *delay_off)
268{
269 struct rt2x00_led *led =
270 container_of(led_cdev, struct rt2x00_led, led_dev);
271 u32 reg;
272
273 rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
274 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
275 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
276 rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
277
278 return 0;
279}
a9450b70
ID		 280#endif /* CONFIG_RT2400PCI_LEDS */
281
95ea3627
ID		 282/*
283 * Configuration handlers.
284 */
3a643d24
ID		 285static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
286 const unsigned int filter_flags)
287{
288 u32 reg;
289
290 /*
291 * Start configuration steps.
292 * Note that the version error will always be dropped
293 * since there is no filter for it at this time.
294 */
295 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
296 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
297 !(filter_flags & FIF_FCSFAIL));
298 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
299 !(filter_flags & FIF_PLCPFAIL));
300 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
301 !(filter_flags & FIF_CONTROL));
302 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
303 !(filter_flags & FIF_PROMISC_IN_BSS));
304 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
e0b005fa
ID		 305 !(filter_flags & FIF_PROMISC_IN_BSS) &&
306 !rt2x00dev->intf_ap_count);
3a643d24
ID		 307 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
308 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
309}
310
6bb40dd1
ID		 311static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
312 struct rt2x00_intf *intf,
313 struct rt2x00intf_conf *conf,
314 const unsigned int flags)
95ea3627 315{
6bb40dd1
ID		 316 unsigned int bcn_preload;
317 u32 reg;
95ea3627 318
6bb40dd1 319 if (flags & CONFIG_UPDATE_TYPE) {
6bb40dd1
ID		 320 /*
321 * Enable beacon config
322 */
323 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
324 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
325 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
326 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
95ea3627 327
6bb40dd1
ID		 328 /*
329 * Enable synchronisation.
330 */
331 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
fd3c91c5 332 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
6bb40dd1 333 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
fd3c91c5 334 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
6bb40dd1
ID		 335 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
336 }
95ea3627 337
6bb40dd1
ID		 338 if (flags & CONFIG_UPDATE_MAC)
339 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
340 conf->mac, sizeof(conf->mac));
95ea3627 341
6bb40dd1
ID		 342 if (flags & CONFIG_UPDATE_BSSID)
343 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
344 conf->bssid, sizeof(conf->bssid));
95ea3627
ID		 345}
346
3a643d24
ID		 347static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
348 struct rt2x00lib_erp *erp)
95ea3627 349{
5c58ee51 350 int preamble_mask;
95ea3627 351 u32 reg;
95ea3627 352
5c58ee51
ID		 353 /*
354 * When short preamble is enabled, we should set bit 0x08
355 */
72810379 356 preamble_mask = erp->short_preamble << 3;
95ea3627
ID		 357
358 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
72810379
ID		 359 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
360 erp->ack_timeout);
361 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
362 erp->ack_consume_time);
95ea3627
ID		 363 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
364
95ea3627 365 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
44a9809b 366 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
95ea3627
ID		 367 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
368 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
369 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
370
371 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
5c58ee51 372 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
95ea3627
ID		 373 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
374 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
375 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
376
377 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
5c58ee51 378 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
95ea3627
ID		 379 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
380 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
381 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
382
383 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
5c58ee51 384 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
95ea3627
ID		 385 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
386 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
387 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
388}
389
390static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
5c58ee51 391 const int basic_rate_mask)
95ea3627 392{
5c58ee51 393 rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
95ea3627
ID		 394}
395
396static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
5c58ee51 397 struct rf_channel *rf)
95ea3627 398{
95ea3627
ID		 399 /*
400 * Switch on tuning bits.
401 */
5c58ee51
ID		 402 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
403 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
95ea3627 404
5c58ee51
ID		 405 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
406 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
407 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 408
409 /*
410 * RF2420 chipset don't need any additional actions.
411 */
412 if (rt2x00_rf(&rt2x00dev->chip, RF2420))
413 return;
414
415 /*
416 * For the RT2421 chipsets we need to write an invalid
417 * reference clock rate to activate auto_tune.
418 * After that we set the value back to the correct channel.
419 */
5c58ee51 420 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
95ea3627 421 rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
5c58ee51 422 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 423
424 msleep(1);
425
5c58ee51
ID		 426 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
427 rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
428 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 429
430 msleep(1);
431
432 /*
433 * Switch off tuning bits.
434 */
5c58ee51
ID		 435 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
436 rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
95ea3627 437
5c58ee51
ID		 438 rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
439 rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
95ea3627
ID		 440
441 /*
442 * Clear false CRC during channel switch.
443 */
5c58ee51 444 rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
95ea3627
ID		 445}
446
447static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
448{
449 rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
450}
451
452static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
addc81bd 453 struct antenna_setup *ant)
95ea3627
ID		 454{
455 u8 r1;
456 u8 r4;
457
a4fe07d9
ID		 458 /*
459 * We should never come here because rt2x00lib is supposed
460 * to catch this and send us the correct antenna explicitely.
461 */
462 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
463 ant->tx == ANTENNA_SW_DIVERSITY);
464
95ea3627
ID		 465 rt2400pci_bbp_read(rt2x00dev, 4, &r4);
466 rt2400pci_bbp_read(rt2x00dev, 1, &r1);
467
468 /*
469 * Configure the TX antenna.
470 */
addc81bd 471 switch (ant->tx) {
95ea3627
ID		 472 case ANTENNA_HW_DIVERSITY:
473 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
474 break;
475 case ANTENNA_A:
476 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
477 break;
478 case ANTENNA_B:
a4fe07d9 479 default:
95ea3627
ID		 480 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
481 break;
482 }
483
484 /*
485 * Configure the RX antenna.
486 */
addc81bd 487 switch (ant->rx) {
95ea3627
ID		 488 case ANTENNA_HW_DIVERSITY:
489 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
490 break;
491 case ANTENNA_A:
492 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
493 break;
494 case ANTENNA_B:
a4fe07d9 495 default:
95ea3627
ID		 496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
497 break;
498 }
499
500 rt2400pci_bbp_write(rt2x00dev, 4, r4);
501 rt2400pci_bbp_write(rt2x00dev, 1, r1);
502}
503
504static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
5c58ee51 505 struct rt2x00lib_conf *libconf)
95ea3627
ID		 506{
507 u32 reg;
508
509 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
5c58ee51 510 rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
95ea3627
ID		 511 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
512
513 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
5c58ee51
ID		 514 rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
515 rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
95ea3627
ID		 516 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
517
518 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
5c58ee51
ID		 519 rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
520 rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
95ea3627
ID		 521 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
522
523 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
524 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
525 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
526 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
527
528 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
5c58ee51
ID		 529 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
530 libconf->conf->beacon_int * 16);
531 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
532 libconf->conf->beacon_int * 16);
95ea3627
ID		 533 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
534}
535
536static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
6bb40dd1
ID		 537 struct rt2x00lib_conf *libconf,
538 const unsigned int flags)
95ea3627 539{
95ea3627 540 if (flags & CONFIG_UPDATE_PHYMODE)
5c58ee51 541 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
95ea3627 542 if (flags & CONFIG_UPDATE_CHANNEL)
5c58ee51 543 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
95ea3627 544 if (flags & CONFIG_UPDATE_TXPOWER)
5c58ee51
ID		 545 rt2400pci_config_txpower(rt2x00dev,
546 libconf->conf->power_level);
95ea3627 547 if (flags & CONFIG_UPDATE_ANTENNA)
addc81bd 548 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
95ea3627 549 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
5c58ee51 550 rt2400pci_config_duration(rt2x00dev, libconf);
95ea3627
ID		 551}
552
553static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
181d6902 554 const int cw_min, const int cw_max)
95ea3627
ID		 555{
556 u32 reg;
557
558 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
181d6902
ID		 559 rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
560 rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
95ea3627
ID		 561 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
562}
563
95ea3627
ID		 564/*
565 * Link tuning
566 */
ebcf26da
ID		 567static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
568 struct link_qual *qual)
95ea3627
ID		 569{
570 u32 reg;
571 u8 bbp;
572
573 /*
574 * Update FCS error count from register.
575 */
576 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
ebcf26da 577 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
95ea3627
ID		 578
579 /*
580 * Update False CCA count from register.
581 */
582 rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
ebcf26da 583 qual->false_cca = bbp;
95ea3627
ID		 584}
585
586static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
587{
588 rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
589 rt2x00dev->link.vgc_level = 0x08;
590}
591
592static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
593{
594 u8 reg;
595
596 /*
597 * The link tuner should not run longer then 60 seconds,
598 * and should run once every 2 seconds.
599 */
600 if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
601 return;
602
603 /*
604 * Base r13 link tuning on the false cca count.
605 */
606 rt2400pci_bbp_read(rt2x00dev, 13, &reg);
607
ebcf26da 608 if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
95ea3627
ID		 609 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
610 rt2x00dev->link.vgc_level = reg;
ebcf26da 611 } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
95ea3627
ID		 612 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
613 rt2x00dev->link.vgc_level = reg;
614 }
615}
616
617/*
618 * Initialization functions.
619 */
837e7f24 620static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
181d6902 621 struct queue_entry *entry)
95ea3627 622{
b8be63ff 623 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 624 u32 word;
625
b8be63ff 626 rt2x00_desc_read(entry_priv->desc, 2, &word);
30b3a23c
ID		 627 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
628 entry->queue->data_size);
b8be63ff 629 rt2x00_desc_write(entry_priv->desc, 2, word);
95ea3627 630
b8be63ff
ID		 631 rt2x00_desc_read(entry_priv->desc, 1, &word);
632 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
633 rt2x00_desc_write(entry_priv->desc, 1, word);
95ea3627 634
b8be63ff 635 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24 636 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
b8be63ff 637 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 638}
639
837e7f24 640static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
181d6902 641 struct queue_entry *entry)
95ea3627 642{
b8be63ff 643 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 644 u32 word;
645
b8be63ff 646 rt2x00_desc_read(entry_priv->desc, 0, &word);
837e7f24
ID		 647 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
648 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
b8be63ff 649 rt2x00_desc_write(entry_priv->desc, 0, word);
95ea3627
ID		 650}
651
181d6902 652static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
95ea3627 653{
b8be63ff 654 struct queue_entry_priv_pci *entry_priv;
95ea3627
ID		 655 u32 reg;
656
95ea3627
ID		 657 /*
658 * Initialize registers.
659 */
660 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
181d6902
ID		 661 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
662 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
663 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
664 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
95ea3627
ID		 665 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
666
b8be63ff 667 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
95ea3627 668 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
30b3a23c 669 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
b8be63ff 670 entry_priv->desc_dma);
95ea3627
ID		 671 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
672
b8be63ff 673 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
95ea3627 674 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
30b3a23c 675 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
b8be63ff 676 entry_priv->desc_dma);
95ea3627
ID		 677 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
678
b8be63ff 679 entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
95ea3627 680 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
30b3a23c 681 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
b8be63ff 682 entry_priv->desc_dma);
95ea3627
ID		 683 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
684
b8be63ff 685 entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
95ea3627 686 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
30b3a23c 687 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
b8be63ff 688 entry_priv->desc_dma);
95ea3627
ID		 689 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
690
691 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
692 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
181d6902 693 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
95ea3627
ID		 694 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
695
b8be63ff 696 entry_priv = rt2x00dev->rx->entries[0].priv_data;
95ea3627 697 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
b8be63ff
ID		 698 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
699 entry_priv->desc_dma);
95ea3627
ID		 700 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
701
702 return 0;
703}
704
705static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
706{
707 u32 reg;
708
709 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
710 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
711 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
712 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
713
714 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
715 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
716 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
717 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
718 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
719
720 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
721 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
722 (rt2x00dev->rx->data_size / 128));
723 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
724
725 rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
726
727 rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
728 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
729 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
730 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
731 rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
732 rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
733
734 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
735 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
736 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
737 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
738 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
739 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
740 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
741 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
742
743 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
744
745 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
746 return -EBUSY;
747
748 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
749 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
750
751 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
752 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
753 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
754
755 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
756 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
757 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
758 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
759 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
760 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
761
762 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
763 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
764 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
765 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
766 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
767
768 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
769 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
770 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
771 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
772
773 /*
774 * We must clear the FCS and FIFO error count.
775 * These registers are cleared on read,
776 * so we may pass a useless variable to store the value.
777 */
778 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
779 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
780
781 return 0;
782}
783
784static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
785{
786 unsigned int i;
787 u16 eeprom;
788 u8 reg_id;
789 u8 value;
790
791 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
792 rt2400pci_bbp_read(rt2x00dev, 0, &value);
793 if ((value != 0xff) && (value != 0x00))
794 goto continue_csr_init;
795 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
796 udelay(REGISTER_BUSY_DELAY);
797 }
798
799 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
800 return -EACCES;
801
802continue_csr_init:
803 rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
804 rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
805 rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
806 rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
807 rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
808 rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
809 rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
810 rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
811 rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
812 rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
813 rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
814 rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
815 rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
816 rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
817
95ea3627
ID		 818 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
819 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
820
821 if (eeprom != 0xffff && eeprom != 0x0000) {
822 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
823 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
95ea3627
ID		 824 rt2400pci_bbp_write(rt2x00dev, reg_id, value);
825 }
826 }
95ea3627
ID		 827
828 return 0;
829}
830
831/*
832 * Device state switch handlers.
833 */
834static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
835 enum dev_state state)
836{
837 u32 reg;
838
839 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
840 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
841 state == STATE_RADIO_RX_OFF);
842 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
843}
844
845static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
846 enum dev_state state)
847{
848 int mask = (state == STATE_RADIO_IRQ_OFF);
849 u32 reg;
850
851 /*
852 * When interrupts are being enabled, the interrupt registers
853 * should clear the register to assure a clean state.
854 */
855 if (state == STATE_RADIO_IRQ_ON) {
856 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
857 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
858 }
859
860 /*
861 * Only toggle the interrupts bits we are going to use.
862 * Non-checked interrupt bits are disabled by default.
863 */
864 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
865 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
866 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
867 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
868 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
869 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
870 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
871}
872
873static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
874{
875 /*
876 * Initialize all registers.
877 */
181d6902 878 if (rt2400pci_init_queues(rt2x00dev) ||
95ea3627
ID		 879 rt2400pci_init_registers(rt2x00dev) ||
880 rt2400pci_init_bbp(rt2x00dev)) {
881 ERROR(rt2x00dev, "Register initialization failed.\n");
882 return -EIO;
883 }
884
885 /*
886 * Enable interrupts.
887 */
888 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
889
95ea3627
ID		 890 return 0;
891}
892
893static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
894{
895 u32 reg;
896
95ea3627
ID		 897 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
898
899 /*
900 * Disable synchronisation.
901 */
902 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
903
904 /*
905 * Cancel RX and TX.
906 */
907 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
908 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
909 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
910
911 /*
912 * Disable interrupts.
913 */
914 rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
915}
916
917static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
918 enum dev_state state)
919{
920 u32 reg;
921 unsigned int i;
922 char put_to_sleep;
923 char bbp_state;
924 char rf_state;
925
926 put_to_sleep = (state != STATE_AWAKE);
927
928 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
929 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
930 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
931 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
932 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
933 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
934
935 /*
936 * Device is not guaranteed to be in the requested state yet.
937 * We must wait until the register indicates that the
938 * device has entered the correct state.
939 */
940 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
941 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
942 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
943 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
944 if (bbp_state == state && rf_state == state)
945 return 0;
946 msleep(10);
947 }
948
949 NOTICE(rt2x00dev, "Device failed to enter state %d, "
950 "current device state: bbp %d and rf %d.\n",
951 state, bbp_state, rf_state);
952
953 return -EBUSY;
954}
955
956static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
957 enum dev_state state)
958{
959 int retval = 0;
960
961 switch (state) {
962 case STATE_RADIO_ON:
963 retval = rt2400pci_enable_radio(rt2x00dev);
964 break;
965 case STATE_RADIO_OFF:
966 rt2400pci_disable_radio(rt2x00dev);
967 break;
968 case STATE_RADIO_RX_ON:
61667d8d
ID		 969 case STATE_RADIO_RX_ON_LINK:
970 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
971 break;
95ea3627 972 case STATE_RADIO_RX_OFF:
61667d8d
ID		 973 case STATE_RADIO_RX_OFF_LINK:
974 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
95ea3627
ID		 975 break;
976 case STATE_DEEP_SLEEP:
977 case STATE_SLEEP:
978 case STATE_STANDBY:
979 case STATE_AWAKE:
980 retval = rt2400pci_set_state(rt2x00dev, state);
981 break;
982 default:
983 retval = -ENOTSUPP;
984 break;
985 }
986
987 return retval;
988}
989
990/*
991 * TX descriptor initialization
992 */
993static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
dd3193e1 994 struct sk_buff *skb,
61486e0f 995 struct txentry_desc *txdesc)
95ea3627 996{
181d6902 997 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
b8be63ff 998 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
dd3193e1 999 __le32 *txd = skbdesc->desc;
95ea3627 1000 u32 word;
95ea3627
ID		 1001
1002 /*
1003 * Start writing the descriptor words.
1004 */
4de36fe5
GW		 1005 rt2x00_desc_read(entry_priv->desc, 1, &word);
1006 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
1007 rt2x00_desc_write(entry_priv->desc, 1, word);
1008
95ea3627 1009 rt2x00_desc_read(txd, 2, &word);
4de36fe5 1010 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skbdesc->data_len);
dd3193e1 1011 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
95ea3627
ID		 1012 rt2x00_desc_write(txd, 2, word);
1013
1014 rt2x00_desc_read(txd, 3, &word);
181d6902 1015 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
49da2605
ID		 1016 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1017 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
181d6902 1018 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
49da2605
ID		 1019 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1020 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
95ea3627
ID		 1021 rt2x00_desc_write(txd, 3, word);
1022
1023 rt2x00_desc_read(txd, 4, &word);
181d6902 1024 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
49da2605
ID		 1025 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1026 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
181d6902 1027 rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
49da2605
ID		 1028 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1029 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
95ea3627
ID		 1030 rt2x00_desc_write(txd, 4, word);
1031
1032 rt2x00_desc_read(txd, 0, &word);
1033 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1034 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1035 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
181d6902 1036 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
95ea3627 1037 rt2x00_set_field32(&word, TXD_W0_ACK,
181d6902 1038 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
95ea3627 1039 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
181d6902 1040 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
95ea3627 1041 rt2x00_set_field32(&word, TXD_W0_RTS,
181d6902
ID		 1042 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1043 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
95ea3627 1044 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
aade5102 1045 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
95ea3627
ID		 1046 rt2x00_desc_write(txd, 0, word);
1047}
1048
1049/*
1050 * TX data initialization
1051 */
1052static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
e58c6aca 1053 const enum data_queue_qid queue)
95ea3627
ID		 1054{
1055 u32 reg;
1056
e58c6aca 1057 if (queue == QID_BEACON) {
95ea3627
ID		 1058 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1059 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
8af244cc
ID		 1060 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1061 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627
ID		 1062 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1063 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1064 }
1065 return;
1066 }
1067
1068 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
e58c6aca
ID		 1069 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1070 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1071 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
95ea3627
ID		 1072 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1073}
1074
1075/*
1076 * RX control handlers
1077 */
181d6902
ID		 1078static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1079 struct rxdone_entry_desc *rxdesc)
95ea3627 1080{
b8be63ff 1081 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
95ea3627
ID		 1082 u32 word0;
1083 u32 word2;
89993890 1084 u32 word3;
95ea3627 1085
b8be63ff
ID		 1086 rt2x00_desc_read(entry_priv->desc, 0, &word0);
1087 rt2x00_desc_read(entry_priv->desc, 2, &word2);
1088 rt2x00_desc_read(entry_priv->desc, 3, &word3);
95ea3627 1089
4150c572 1090 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
181d6902 1091 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
4150c572 1092 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
181d6902 1093 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627
ID		 1094
1095 /*
1096 * Obtain the status about this packet.
8ed09854
ID		 1097 * The signal is the PLCP value, and needs to be stripped
1098 * of the preamble bit (0x08).
95ea3627 1099 */
8ed09854 1100 rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
89993890 1101 rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
181d6902 1102 entry->queue->rt2x00dev->rssi_offset;
181d6902 1103 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
19d30e02 1104
dec13b6b 1105 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
19d30e02
ID		 1106 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1107 rxdesc->dev_flags |= RXDONE_MY_BSS;
95ea3627
ID		 1108}
1109
1110/*
1111 * Interrupt functions.
1112 */
181d6902 1113static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
e58c6aca 1114 const enum data_queue_qid queue_idx)
95ea3627 1115{
181d6902 1116 struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
b8be63ff 1117 struct queue_entry_priv_pci *entry_priv;
181d6902
ID		 1118 struct queue_entry *entry;
1119 struct txdone_entry_desc txdesc;
95ea3627 1120 u32 word;
95ea3627 1121
181d6902
ID		 1122 while (!rt2x00queue_empty(queue)) {
1123 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
b8be63ff
ID		 1124 entry_priv = entry->priv_data;
1125 rt2x00_desc_read(entry_priv->desc, 0, &word);
95ea3627
ID		 1126
1127 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1128 !rt2x00_get_field32(word, TXD_W0_VALID))
1129 break;
1130
1131 /*
1132 * Obtain the status about this packet.
1133 */
fb55f4d1
ID		 1134 txdesc.flags = 0;
1135 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1136 case 0: /* Success */
1137 case 1: /* Success with retry */
1138 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1139 break;
1140 case 2: /* Failure, excessive retries */
1141 __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1142 /* Don't break, this is a failed frame! */
1143 default: /* Failure */
1144 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1145 }
181d6902 1146 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
95ea3627 1147
181d6902 1148 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
95ea3627 1149 }
95ea3627
ID		 1150}
1151
1152static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1153{
1154 struct rt2x00_dev *rt2x00dev = dev_instance;
1155 u32 reg;
1156
1157 /*
1158 * Get the interrupt sources & saved to local variable.
1159 * Write register value back to clear pending interrupts.
1160 */
1161 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1162 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1163
1164 if (!reg)
1165 return IRQ_NONE;
1166
1167 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1168 return IRQ_HANDLED;
1169
1170 /*
1171 * Handle interrupts, walk through all bits
1172 * and run the tasks, the bits are checked in order of
1173 * priority.
1174 */
1175
1176 /*
1177 * 1 - Beacon timer expired interrupt.
1178 */
1179 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1180 rt2x00lib_beacondone(rt2x00dev);
1181
1182 /*
1183 * 2 - Rx ring done interrupt.
1184 */
1185 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1186 rt2x00pci_rxdone(rt2x00dev);
1187
1188 /*
1189 * 3 - Atim ring transmit done interrupt.
1190 */
1191 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
e58c6aca 1192 rt2400pci_txdone(rt2x00dev, QID_ATIM);
95ea3627
ID		 1193
1194 /*
1195 * 4 - Priority ring transmit done interrupt.
1196 */
1197 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
e58c6aca 1198 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
95ea3627
ID		 1199
1200 /*
1201 * 5 - Tx ring transmit done interrupt.
1202 */
1203 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
e58c6aca 1204 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
95ea3627
ID		 1205
1206 return IRQ_HANDLED;
1207}
1208
1209/*
1210 * Device probe functions.
1211 */
1212static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1213{
1214 struct eeprom_93cx6 eeprom;
1215 u32 reg;
1216 u16 word;
1217 u8 *mac;
1218
1219 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1220
1221 eeprom.data = rt2x00dev;
1222 eeprom.register_read = rt2400pci_eepromregister_read;
1223 eeprom.register_write = rt2400pci_eepromregister_write;
1224 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1225 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1226 eeprom.reg_data_in = 0;
1227 eeprom.reg_data_out = 0;
1228 eeprom.reg_data_clock = 0;
1229 eeprom.reg_chip_select = 0;
1230
1231 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1232 EEPROM_SIZE / sizeof(u16));
1233
1234 /*
1235 * Start validation of the data that has been read.
1236 */
1237 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1238 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1239 DECLARE_MAC_BUF(macbuf);
1240
95ea3627 1241 random_ether_addr(mac);
0795af57 1242 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
95ea3627
ID		 1243 }
1244
1245 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1246 if (word == 0xffff) {
1247 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1248 return -EINVAL;
1249 }
1250
1251 return 0;
1252}
1253
1254static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1255{
1256 u32 reg;
1257 u16 value;
1258 u16 eeprom;
1259
1260 /*
1261 * Read EEPROM word for configuration.
1262 */
1263 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1264
1265 /*
1266 * Identify RF chipset.
1267 */
1268 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1269 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1270 rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1271
1272 if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1273 !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1274 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1275 return -ENODEV;
1276 }
1277
1278 /*
1279 * Identify default antenna configuration.
1280 */
addc81bd 1281 rt2x00dev->default_ant.tx =
95ea3627 1282 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
addc81bd 1283 rt2x00dev->default_ant.rx =
95ea3627
ID		 1284 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1285
addc81bd
ID		 1286 /*
1287 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1288 * I am not 100% sure about this, but the legacy drivers do not
1289 * indicate antenna swapping in software is required when
1290 * diversity is enabled.
1291 */
1292 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1293 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1294 if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1295 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1296
95ea3627
ID		 1297 /*
1298 * Store led mode, for correct led behaviour.
1299 */
a9450b70
ID		 1300#ifdef CONFIG_RT2400PCI_LEDS
1301 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1302
a2e1d52a
ID		 1303 rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1304 rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1305 rt2x00dev->led_radio.led_dev.brightness_set =
1306 rt2400pci_brightness_set;
1307 rt2x00dev->led_radio.led_dev.blink_set =
1308 rt2400pci_blink_set;
1309 rt2x00dev->led_radio.flags = LED_INITIALIZED;
1310
1311 if (value == LED_MODE_TXRX_ACTIVITY) {
1312 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
61c2b682 1313 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
a2e1d52a
ID		 1314 rt2x00dev->led_qual.led_dev.brightness_set =
1315 rt2400pci_brightness_set;
1316 rt2x00dev->led_qual.led_dev.blink_set =
1317 rt2400pci_blink_set;
1318 rt2x00dev->led_qual.flags = LED_INITIALIZED;
a9450b70
ID		 1319 }
1320#endif /* CONFIG_RT2400PCI_LEDS */
95ea3627
ID		 1321
1322 /*
1323 * Detect if this device has an hardware controlled radio.
1324 */
81873e9c 1325#ifdef CONFIG_RT2400PCI_RFKILL
95ea3627 1326 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1327 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
81873e9c 1328#endif /* CONFIG_RT2400PCI_RFKILL */
95ea3627
ID		 1329
1330 /*
1331 * Check if the BBP tuning should be enabled.
1332 */
1333 if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1334 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1335
1336 return 0;
1337}
1338
1339/*
1340 * RF value list for RF2420 & RF2421
1341 * Supports: 2.4 GHz
1342 */
1343static const struct rf_channel rf_vals_bg[] = {
1344 { 1, 0x00022058, 0x000c1fda, 0x00000101, 0 },
1345 { 2, 0x00022058, 0x000c1fee, 0x00000101, 0 },
1346 { 3, 0x00022058, 0x000c2002, 0x00000101, 0 },
1347 { 4, 0x00022058, 0x000c2016, 0x00000101, 0 },
1348 { 5, 0x00022058, 0x000c202a, 0x00000101, 0 },
1349 { 6, 0x00022058, 0x000c203e, 0x00000101, 0 },
1350 { 7, 0x00022058, 0x000c2052, 0x00000101, 0 },
1351 { 8, 0x00022058, 0x000c2066, 0x00000101, 0 },
1352 { 9, 0x00022058, 0x000c207a, 0x00000101, 0 },
1353 { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1354 { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1355 { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1356 { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1357 { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1358};
1359
1360static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1361{
1362 struct hw_mode_spec *spec = &rt2x00dev->spec;
1363 u8 *txpower;
1364 unsigned int i;
1365
1366 /*
1367 * Initialize all hw fields.
1368 */
566bfe5a
BR		 1369 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1370 IEEE80211_HW_SIGNAL_DBM;
95ea3627 1371 rt2x00dev->hw->extra_tx_headroom = 0;
95ea3627
ID		 1372
1373 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1374 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1375 rt2x00_eeprom_addr(rt2x00dev,
1376 EEPROM_MAC_ADDR_0));
1377
1378 /*
1379 * Convert tx_power array in eeprom.
1380 */
1381 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1382 for (i = 0; i < 14; i++)
1383 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1384
1385 /*
1386 * Initialize hw_mode information.
1387 */
31562e80
ID		 1388 spec->supported_bands = SUPPORT_BAND_2GHZ;
1389 spec->supported_rates = SUPPORT_RATE_CCK;
95ea3627
ID		 1390 spec->tx_power_a = NULL;
1391 spec->tx_power_bg = txpower;
1392 spec->tx_power_default = DEFAULT_TXPOWER;
1393
1394 spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1395 spec->channels = rf_vals_bg;
1396}
1397
1398static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1399{
1400 int retval;
1401
1402 /*
1403 * Allocate eeprom data.
1404 */
1405 retval = rt2400pci_validate_eeprom(rt2x00dev);
1406 if (retval)
1407 return retval;
1408
1409 retval = rt2400pci_init_eeprom(rt2x00dev);
1410 if (retval)
1411 return retval;
1412
1413 /*
1414 * Initialize hw specifications.
1415 */
1416 rt2400pci_probe_hw_mode(rt2x00dev);
1417
1418 /*
181d6902 1419 * This device requires the atim queue
95ea3627 1420 */
181d6902 1421 __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
95ea3627
ID		 1422
1423 /*
1424 * Set the rssi offset.
1425 */
1426 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1427
1428 return 0;
1429}
1430
1431/*
1432 * IEEE80211 stack callback functions.
1433 */
1434static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1435 u32 short_retry, u32 long_retry)
1436{
1437 struct rt2x00_dev *rt2x00dev = hw->priv;
1438 u32 reg;
1439
1440 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1441 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1442 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1443 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1444
1445 return 0;
1446}
1447
e100bb64 1448static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
95ea3627
ID		 1449 const struct ieee80211_tx_queue_params *params)
1450{
1451 struct rt2x00_dev *rt2x00dev = hw->priv;
1452
1453 /*
1454 * We don't support variating cw_min and cw_max variables
1455 * per queue. So by default we only configure the TX queue,
1456 * and ignore all other configurations.
1457 */
e100bb64 1458 if (queue != 0)
95ea3627
ID		 1459 return -EINVAL;
1460
1461 if (rt2x00mac_conf_tx(hw, queue, params))
1462 return -EINVAL;
1463
1464 /*
1465 * Write configuration to register.
1466 */
181d6902
ID		 1467 rt2400pci_config_cw(rt2x00dev,
1468 rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
95ea3627
ID		 1469
1470 return 0;
1471}
1472
1473static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1474{
1475 struct rt2x00_dev *rt2x00dev = hw->priv;
1476 u64 tsf;
1477 u32 reg;
1478
1479 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1480 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1481 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1482 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1483
1484 return tsf;
1485}
1486
e039fa4a 1487static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
5957da4c
ID		 1488{
1489 struct rt2x00_dev *rt2x00dev = hw->priv;
e039fa4a
JB		 1490 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1491 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
b8be63ff 1492 struct queue_entry_priv_pci *entry_priv;
5957da4c 1493 struct skb_frame_desc *skbdesc;
7050ec82 1494 struct txentry_desc txdesc;
8af244cc 1495 u32 reg;
5957da4c
ID		 1496
1497 if (unlikely(!intf->beacon))
1498 return -ENOBUFS;
b8be63ff 1499 entry_priv = intf->beacon->priv_data;
5957da4c 1500
7050ec82
ID		 1501 /*
1502 * Copy all TX descriptor information into txdesc,
1503 * after that we are free to use the skb->cb array
1504 * for our information.
1505 */
1506 intf->beacon->skb = skb;
e039fa4a 1507 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
7050ec82 1508
5957da4c
ID		 1509 /*
1510 * Fill in skb descriptor
1511 */
1512 skbdesc = get_skb_frame_desc(skb);
1513 memset(skbdesc, 0, sizeof(*skbdesc));
baf26a7e 1514 skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
5957da4c
ID		 1515 skbdesc->data = skb->data;
1516 skbdesc->data_len = skb->len;
b8be63ff 1517 skbdesc->desc = entry_priv->desc;
5957da4c
ID		 1518 skbdesc->desc_len = intf->beacon->queue->desc_size;
1519 skbdesc->entry = intf->beacon;
1520
8af244cc
ID		 1521 /*
1522 * Disable beaconing while we are reloading the beacon data,
1523 * otherwise we might be sending out invalid data.
1524 */
1525 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1526 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1527 rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1528 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1529 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1530
5957da4c
ID		 1531 /*
1532 * Enable beacon generation.
1533 * Write entire beacon with descriptor to register,
1534 * and kick the beacon generator.
1535 */
b8be63ff 1536 memcpy(entry_priv->data, skb->data, skb->len);
7050ec82 1537 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
e58c6aca 1538 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
5957da4c
ID		 1539
1540 return 0;
1541}
1542
95ea3627
ID		 1543static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1544{
1545 struct rt2x00_dev *rt2x00dev = hw->priv;
1546 u32 reg;
1547
1548 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1549 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1550}
1551
1552static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1553 .tx = rt2x00mac_tx,
4150c572
JB		 1554 .start = rt2x00mac_start,
1555 .stop = rt2x00mac_stop,
95ea3627
ID		 1556 .add_interface = rt2x00mac_add_interface,
1557 .remove_interface = rt2x00mac_remove_interface,
1558 .config = rt2x00mac_config,
1559 .config_interface = rt2x00mac_config_interface,
3a643d24 1560 .configure_filter = rt2x00mac_configure_filter,
95ea3627
ID		 1561 .get_stats = rt2x00mac_get_stats,
1562 .set_retry_limit = rt2400pci_set_retry_limit,
471b3efd 1563 .bss_info_changed = rt2x00mac_bss_info_changed,
95ea3627
ID		 1564 .conf_tx = rt2400pci_conf_tx,
1565 .get_tx_stats = rt2x00mac_get_tx_stats,
1566 .get_tsf = rt2400pci_get_tsf,
5957da4c 1567 .beacon_update = rt2400pci_beacon_update,
95ea3627
ID		 1568 .tx_last_beacon = rt2400pci_tx_last_beacon,
1569};
1570
1571static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1572 .irq_handler = rt2400pci_interrupt,
1573 .probe_hw = rt2400pci_probe_hw,
1574 .initialize = rt2x00pci_initialize,
1575 .uninitialize = rt2x00pci_uninitialize,
837e7f24
ID		 1576 .init_rxentry = rt2400pci_init_rxentry,
1577 .init_txentry = rt2400pci_init_txentry,
95ea3627 1578 .set_device_state = rt2400pci_set_device_state,
95ea3627 1579 .rfkill_poll = rt2400pci_rfkill_poll,
95ea3627
ID		 1580 .link_stats = rt2400pci_link_stats,
1581 .reset_tuner = rt2400pci_reset_tuner,
1582 .link_tuner = rt2400pci_link_tuner,
1583 .write_tx_desc = rt2400pci_write_tx_desc,
1584 .write_tx_data = rt2x00pci_write_tx_data,
1585 .kick_tx_queue = rt2400pci_kick_tx_queue,
1586 .fill_rxdone = rt2400pci_fill_rxdone,
3a643d24 1587 .config_filter = rt2400pci_config_filter,
6bb40dd1 1588 .config_intf = rt2400pci_config_intf,
72810379 1589 .config_erp = rt2400pci_config_erp,
95ea3627
ID		 1590 .config = rt2400pci_config,
1591};
1592
181d6902
ID		 1593static const struct data_queue_desc rt2400pci_queue_rx = {
1594 .entry_num = RX_ENTRIES,
1595 .data_size = DATA_FRAME_SIZE,
1596 .desc_size = RXD_DESC_SIZE,
b8be63ff 1597 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1598};
1599
1600static const struct data_queue_desc rt2400pci_queue_tx = {
1601 .entry_num = TX_ENTRIES,
1602 .data_size = DATA_FRAME_SIZE,
1603 .desc_size = TXD_DESC_SIZE,
b8be63ff 1604 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1605};
1606
1607static const struct data_queue_desc rt2400pci_queue_bcn = {
1608 .entry_num = BEACON_ENTRIES,
1609 .data_size = MGMT_FRAME_SIZE,
1610 .desc_size = TXD_DESC_SIZE,
b8be63ff 1611 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1612};
1613
1614static const struct data_queue_desc rt2400pci_queue_atim = {
1615 .entry_num = ATIM_ENTRIES,
1616 .data_size = DATA_FRAME_SIZE,
1617 .desc_size = TXD_DESC_SIZE,
b8be63ff 1618 .priv_size = sizeof(struct queue_entry_priv_pci),
181d6902
ID		 1619};
1620
95ea3627 1621static const struct rt2x00_ops rt2400pci_ops = {
2360157c 1622 .name = KBUILD_MODNAME,
6bb40dd1
ID		 1623 .max_sta_intf = 1,
1624 .max_ap_intf = 1,
95ea3627
ID		 1625 .eeprom_size = EEPROM_SIZE,
1626 .rf_size = RF_SIZE,
61448f88 1627 .tx_queues = NUM_TX_QUEUES,
181d6902
ID		 1628 .rx = &rt2400pci_queue_rx,
1629 .tx = &rt2400pci_queue_tx,
1630 .bcn = &rt2400pci_queue_bcn,
1631 .atim = &rt2400pci_queue_atim,
95ea3627
ID		 1632 .lib = &rt2400pci_rt2x00_ops,
1633 .hw = &rt2400pci_mac80211_ops,
1634#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1635 .debugfs = &rt2400pci_rt2x00debug,
1636#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1637};
1638
1639/*
1640 * RT2400pci module information.
1641 */
1642static struct pci_device_id rt2400pci_device_table[] = {
1643 { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1644 { 0, }
1645};
1646
1647MODULE_AUTHOR(DRV_PROJECT);
1648MODULE_VERSION(DRV_VERSION);
1649MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1650MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1651MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1652MODULE_LICENSE("GPL");
1653
1654static struct pci_driver rt2400pci_driver = {
2360157c 1655 .name = KBUILD_MODNAME,
95ea3627
ID		 1656 .id_table = rt2400pci_device_table,
1657 .probe = rt2x00pci_probe,
1658 .remove = __devexit_p(rt2x00pci_remove),
1659 .suspend = rt2x00pci_suspend,
1660 .resume = rt2x00pci_resume,
1661};
1662
1663static int __init rt2400pci_init(void)
1664{
1665 return pci_register_driver(&rt2400pci_driver);
1666}
1667
1668static void __exit rt2400pci_exit(void)
1669{
1670 pci_unregister_driver(&rt2400pci_driver);
1671}
1672
1673module_init(rt2400pci_init);
1674module_exit(rt2400pci_exit);
Linux kernel - Deliverables
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