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[PATCH] rt2x00: Don't use changed_flags inside configure_packet_filter
[deliverable/linux.git] / drivers / net / wireless / rt2x00 / rt2500pci.c
CommitLineData
95ea3627
ID		 1/*
2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21/*
22 Module: rt2500pci
23 Abstract: rt2500pci device specific routines.
24 Supported chipsets: RT2560.
25 */
26
27/*
28 * Set enviroment defines for rt2x00.h
29 */
30#define DRV_NAME "rt2500pci"
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/eeprom_93cx6.h>
39
40#include "rt2x00.h"
41#include "rt2x00pci.h"
42#include "rt2500pci.h"
43
44/*
45 * Register access.
46 * All access to the CSR registers will go through the methods
47 * rt2x00pci_register_read and rt2x00pci_register_write.
48 * BBP and RF register require indirect register access,
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
50 * These indirect registers work with busy bits,
51 * and we will try maximal REGISTER_BUSY_COUNT times to access
52 * the register while taking a REGISTER_BUSY_DELAY us delay
53 * between each attampt. When the busy bit is still set at that time,
54 * the access attempt is considered to have failed,
55 * and we will print an error.
56 */
57static u32 rt2500pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
58{
59 u32 reg;
60 unsigned int i;
61
62 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
63 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
64 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
65 break;
66 udelay(REGISTER_BUSY_DELAY);
67 }
68
69 return reg;
70}
71
72static void rt2500pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
73 const unsigned int word, const u8 value)
74{
75 u32 reg;
76
77 /*
78 * Wait until the BBP becomes ready.
79 */
80 reg = rt2500pci_bbp_check(rt2x00dev);
81 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
82 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
83 return;
84 }
85
86 /*
87 * Write the data into the BBP.
88 */
89 reg = 0;
90 rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
91 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
92 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
93 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
94
95 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
96}
97
98static void rt2500pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
99 const unsigned int word, u8 *value)
100{
101 u32 reg;
102
103 /*
104 * Wait until the BBP becomes ready.
105 */
106 reg = rt2500pci_bbp_check(rt2x00dev);
107 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
108 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
109 return;
110 }
111
112 /*
113 * Write the request into the BBP.
114 */
115 reg = 0;
116 rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
117 rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
118 rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
119
120 rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
121
122 /*
123 * Wait until the BBP becomes ready.
124 */
125 reg = rt2500pci_bbp_check(rt2x00dev);
126 if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
127 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
128 *value = 0xff;
129 return;
130 }
131
132 *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
133}
134
135static void rt2500pci_rf_write(const struct rt2x00_dev *rt2x00dev,
136 const unsigned int word, const u32 value)
137{
138 u32 reg;
139 unsigned int i;
140
141 if (!word)
142 return;
143
144 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
145 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
146 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
147 goto rf_write;
148 udelay(REGISTER_BUSY_DELAY);
149 }
150
151 ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
152 return;
153
154rf_write:
155 reg = 0;
156 rt2x00_set_field32(&reg, RFCSR_VALUE, value);
157 rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
158 rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
159 rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
160
161 rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
162 rt2x00_rf_write(rt2x00dev, word, value);
163}
164
165static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
166{
167 struct rt2x00_dev *rt2x00dev = eeprom->data;
168 u32 reg;
169
170 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
171
172 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
173 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
174 eeprom->reg_data_clock =
175 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
176 eeprom->reg_chip_select =
177 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
178}
179
180static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
181{
182 struct rt2x00_dev *rt2x00dev = eeprom->data;
183 u32 reg = 0;
184
185 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
186 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
187 rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
188 !!eeprom->reg_data_clock);
189 rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
190 !!eeprom->reg_chip_select);
191
192 rt2x00pci_register_write(rt2x00dev, CSR21, reg);
193}
194
195#ifdef CONFIG_RT2X00_LIB_DEBUGFS
196#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
197
198static void rt2500pci_read_csr(const struct rt2x00_dev *rt2x00dev,
199 const unsigned int word, u32 *data)
200{
201 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
202}
203
204static void rt2500pci_write_csr(const struct rt2x00_dev *rt2x00dev,
205 const unsigned int word, u32 data)
206{
207 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
208}
209
210static const struct rt2x00debug rt2500pci_rt2x00debug = {
211 .owner = THIS_MODULE,
212 .csr = {
213 .read = rt2500pci_read_csr,
214 .write = rt2500pci_write_csr,
215 .word_size = sizeof(u32),
216 .word_count = CSR_REG_SIZE / sizeof(u32),
217 },
218 .eeprom = {
219 .read = rt2x00_eeprom_read,
220 .write = rt2x00_eeprom_write,
221 .word_size = sizeof(u16),
222 .word_count = EEPROM_SIZE / sizeof(u16),
223 },
224 .bbp = {
225 .read = rt2500pci_bbp_read,
226 .write = rt2500pci_bbp_write,
227 .word_size = sizeof(u8),
228 .word_count = BBP_SIZE / sizeof(u8),
229 },
230 .rf = {
231 .read = rt2x00_rf_read,
232 .write = rt2500pci_rf_write,
233 .word_size = sizeof(u32),
234 .word_count = RF_SIZE / sizeof(u32),
235 },
236};
237#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
238
239#ifdef CONFIG_RT2500PCI_RFKILL
240static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
241{
242 u32 reg;
243
244 rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
245 return rt2x00_get_field32(reg, GPIOCSR_BIT0);
246}
dcf5475b 247#endif /* CONFIG_RT2500PCI_RFKILL */
95ea3627
ID		 248
249/*
250 * Configuration handlers.
251 */
4abee4bb
ID		 252static void rt2500pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
253 __le32 *mac)
95ea3627 254{
4abee4bb
ID		 255 rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
256 (2 * sizeof(__le32)));
95ea3627
ID		 257}
258
4abee4bb
ID		 259static void rt2500pci_config_bssid(struct rt2x00_dev *rt2x00dev,
260 __le32 *bssid)
95ea3627 261{
4abee4bb
ID		 262 rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
263 (2 * sizeof(__le32)));
95ea3627
ID		 264}
265
95ea3627
ID		 266static void rt2500pci_config_type(struct rt2x00_dev *rt2x00dev, const int type)
267{
4150c572 268 struct interface *intf = &rt2x00dev->interface;
95ea3627
ID		 269 u32 reg;
270
271 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
272
95ea3627
ID		 273 /*
274 * Enable beacon config
275 */
276 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
277 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
278 PREAMBLE + get_duration(IEEE80211_HEADER, 2));
279 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN,
280 rt2x00lib_get_ring(rt2x00dev,
281 IEEE80211_TX_QUEUE_BEACON)
282 ->tx_params.cw_min);
283 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
284
285 /*
286 * Enable synchronisation.
287 */
288 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
4150c572
JB		 289 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
290 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
95ea3627 291 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
4150c572
JB		 292 if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
293 is_interface_type(intf, IEEE80211_IF_TYPE_AP))
95ea3627 294 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
4150c572 295 else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
95ea3627 296 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
4150c572 297 else
95ea3627 298 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
95ea3627
ID		 299 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
300}
301
302static void rt2500pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
303{
304 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
305 u32 reg;
306 u32 preamble;
307 u16 value;
308
309 if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
310 preamble = SHORT_PREAMBLE;
311 else
312 preamble = PREAMBLE;
313
314 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
315 rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
316
317 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
318 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
319 SHORT_DIFS : DIFS) +
320 PLCP + preamble + get_duration(ACK_SIZE, 10);
321 rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
322 value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
323 rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
324 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
325
326 preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
327
328 rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
329 rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
330 rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
331 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
332 rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
333
334 rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
335 rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
336 rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
337 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
338 rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
339
340 rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
341 rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
342 rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
343 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
344 rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
345
346 rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
347 rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
348 rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
349 rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
350 rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
351}
352
353static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
354 const int phymode)
355{
356 struct ieee80211_hw_mode *mode;
357 struct ieee80211_rate *rate;
358
359 if (phymode == MODE_IEEE80211A)
360 rt2x00dev->curr_hwmode = HWMODE_A;
361 else if (phymode == MODE_IEEE80211B)
362 rt2x00dev->curr_hwmode = HWMODE_B;
363 else
364 rt2x00dev->curr_hwmode = HWMODE_G;
365
366 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
367 rate = &mode->rates[mode->num_rates - 1];
368
369 rt2500pci_config_rate(rt2x00dev, rate->val2);
370}
371
372static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
373 const int index, const int channel,
374 const int txpower)
375{
376 struct rf_channel reg;
377 u8 r70;
378
379 /*
380 * Fill rf_reg structure.
381 */
382 memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
383
384 /*
385 * Set TXpower.
386 */
387 rt2x00_set_field32(&reg.rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
388
389 /*
390 * Switch on tuning bits.
391 * For RT2523 devices we do not need to update the R1 register.
392 */
393 if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
394 rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
395 rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
396
397 /*
398 * For RT2525 we should first set the channel to half band higher.
399 */
400 if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
401 static const u32 vals[] = {
402 0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
403 0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
404 0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
405 0x00080d2e, 0x00080d3a
406 };
407
408 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
409 rt2500pci_rf_write(rt2x00dev, 2, vals[channel - 1]);
410 rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
411 if (reg.rf4)
412 rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
413 }
414
415 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
416 rt2500pci_rf_write(rt2x00dev, 2, reg.rf2);
417 rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
418 if (reg.rf4)
419 rt2500pci_rf_write(rt2x00dev, 4, reg.rf4);
420
421 /*
422 * Channel 14 requires the Japan filter bit to be set.
423 */
424 r70 = 0x46;
425 rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, channel == 14);
426 rt2500pci_bbp_write(rt2x00dev, 70, r70);
427
428 msleep(1);
429
430 /*
431 * Switch off tuning bits.
432 * For RT2523 devices we do not need to update the R1 register.
433 */
434 if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
435 rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
436 rt2500pci_rf_write(rt2x00dev, 1, reg.rf1);
437 }
438
439 rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
440 rt2500pci_rf_write(rt2x00dev, 3, reg.rf3);
441
442 /*
443 * Clear false CRC during channel switch.
444 */
445 rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
446}
447
448static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
449 const int txpower)
450{
451 u32 rf3;
452
453 rt2x00_rf_read(rt2x00dev, 3, &rf3);
454 rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
455 rt2500pci_rf_write(rt2x00dev, 3, rf3);
456}
457
458static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
459 const int antenna_tx, const int antenna_rx)
460{
461 u32 reg;
462 u8 r14;
463 u8 r2;
464
465 rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
466 rt2500pci_bbp_read(rt2x00dev, 14, &r14);
467 rt2500pci_bbp_read(rt2x00dev, 2, &r2);
468
469 /*
470 * Configure the TX antenna.
471 */
472 switch (antenna_tx) {
473 case ANTENNA_SW_DIVERSITY:
474 case ANTENNA_HW_DIVERSITY:
475 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
476 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
477 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
478 break;
479 case ANTENNA_A:
480 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
481 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
482 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
483 break;
484 case ANTENNA_B:
485 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
486 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
487 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
488 break;
489 }
490
491 /*
492 * Configure the RX antenna.
493 */
494 switch (antenna_rx) {
495 case ANTENNA_SW_DIVERSITY:
496 case ANTENNA_HW_DIVERSITY:
497 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
498 break;
499 case ANTENNA_A:
500 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
501 break;
502 case ANTENNA_B:
503 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
504 break;
505 }
506
507 /*
508 * RT2525E and RT5222 need to flip TX I/Q
509 */
510 if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
511 rt2x00_rf(&rt2x00dev->chip, RF5222)) {
512 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
513 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
514 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
515
516 /*
517 * RT2525E does not need RX I/Q Flip.
518 */
519 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
520 rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
521 } else {
522 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
523 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
524 }
525
526 rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
527 rt2500pci_bbp_write(rt2x00dev, 14, r14);
528 rt2500pci_bbp_write(rt2x00dev, 2, r2);
529}
530
531static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
532 const int short_slot_time,
533 const int beacon_int)
534{
535 u32 reg;
536
537 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
538 rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
539 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
540 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
541
542 rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
543 rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
544 rt2x00_set_field32(&reg, CSR18_PIFS,
545 short_slot_time ? SHORT_PIFS : PIFS);
546 rt2x00pci_register_write(rt2x00dev, CSR18, reg);
547
548 rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
549 rt2x00_set_field32(&reg, CSR19_DIFS,
550 short_slot_time ? SHORT_DIFS : DIFS);
551 rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
552 rt2x00pci_register_write(rt2x00dev, CSR19, reg);
553
554 rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
555 rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
556 rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
557 rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
558
559 rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
560 rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
561 rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
562 rt2x00pci_register_write(rt2x00dev, CSR12, reg);
563}
564
565static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
566 const unsigned int flags,
567 struct ieee80211_conf *conf)
568{
569 int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
570
571 if (flags & CONFIG_UPDATE_PHYMODE)
572 rt2500pci_config_phymode(rt2x00dev, conf->phymode);
573 if (flags & CONFIG_UPDATE_CHANNEL)
574 rt2500pci_config_channel(rt2x00dev, conf->channel_val,
575 conf->channel, conf->power_level);
576 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
577 rt2500pci_config_txpower(rt2x00dev, conf->power_level);
578 if (flags & CONFIG_UPDATE_ANTENNA)
579 rt2500pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
580 conf->antenna_sel_rx);
581 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
582 rt2500pci_config_duration(rt2x00dev, short_slot_time,
583 conf->beacon_int);
584}
585
586/*
587 * LED functions.
588 */
589static void rt2500pci_enable_led(struct rt2x00_dev *rt2x00dev)
590{
591 u32 reg;
592
593 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
594
595 rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
596 rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
597
598 if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
599 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
600 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
601 } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
602 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
603 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
604 } else {
605 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
606 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
607 }
608
609 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
610}
611
612static void rt2500pci_disable_led(struct rt2x00_dev *rt2x00dev)
613{
614 u32 reg;
615
616 rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
617 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
618 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
619 rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
620}
621
622/*
623 * Link tuning
624 */
625static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev)
626{
627 u32 reg;
628
629 /*
630 * Update FCS error count from register.
631 */
632 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
633 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
634
635 /*
636 * Update False CCA count from register.
637 */
638 rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
639 rt2x00dev->link.false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
640}
641
642static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
643{
644 rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
645 rt2x00dev->link.vgc_level = 0x48;
646}
647
648static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
649{
650 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
651 u8 r17;
652
653 /*
654 * To prevent collisions with MAC ASIC on chipsets
655 * up to version C the link tuning should halt after 20
656 * seconds.
657 */
658 if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
659 rt2x00dev->link.count > 20)
660 return;
661
662 rt2500pci_bbp_read(rt2x00dev, 17, &r17);
663
664 /*
665 * Chipset versions C and lower should directly continue
666 * to the dynamic CCA tuning.
667 */
668 if (rt2x00_get_rev(&rt2x00dev->chip) < RT2560_VERSION_D)
669 goto dynamic_cca_tune;
670
671 /*
672 * A too low RSSI will cause too much false CCA which will
673 * then corrupt the R17 tuning. To remidy this the tuning should
674 * be stopped (While making sure the R17 value will not exceed limits)
675 */
676 if (rssi < -80 && rt2x00dev->link.count > 20) {
677 if (r17 >= 0x41) {
678 r17 = rt2x00dev->link.vgc_level;
679 rt2500pci_bbp_write(rt2x00dev, 17, r17);
680 }
681 return;
682 }
683
684 /*
685 * Special big-R17 for short distance
686 */
687 if (rssi >= -58) {
688 if (r17 != 0x50)
689 rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
690 return;
691 }
692
693 /*
694 * Special mid-R17 for middle distance
695 */
696 if (rssi >= -74) {
697 if (r17 != 0x41)
698 rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
699 return;
700 }
701
702 /*
703 * Leave short or middle distance condition, restore r17
704 * to the dynamic tuning range.
705 */
706 if (r17 >= 0x41) {
707 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
708 return;
709 }
710
711dynamic_cca_tune:
712
713 /*
714 * R17 is inside the dynamic tuning range,
715 * start tuning the link based on the false cca counter.
716 */
717 if (rt2x00dev->link.false_cca > 512 && r17 < 0x40) {
718 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
719 rt2x00dev->link.vgc_level = r17;
720 } else if (rt2x00dev->link.false_cca < 100 && r17 > 0x32) {
721 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
722 rt2x00dev->link.vgc_level = r17;
723 }
724}
725
726/*
727 * Initialization functions.
728 */
729static void rt2500pci_init_rxring(struct rt2x00_dev *rt2x00dev)
730{
731 struct data_ring *ring = rt2x00dev->rx;
732 struct data_desc *rxd;
733 unsigned int i;
734 u32 word;
735
736 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
737
738 for (i = 0; i < ring->stats.limit; i++) {
739 rxd = ring->entry[i].priv;
740
741 rt2x00_desc_read(rxd, 1, &word);
742 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
743 ring->entry[i].data_dma);
744 rt2x00_desc_write(rxd, 1, word);
745
746 rt2x00_desc_read(rxd, 0, &word);
747 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
748 rt2x00_desc_write(rxd, 0, word);
749 }
750
751 rt2x00_ring_index_clear(rt2x00dev->rx);
752}
753
754static void rt2500pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
755{
756 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
757 struct data_desc *txd;
758 unsigned int i;
759 u32 word;
760
761 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
762
763 for (i = 0; i < ring->stats.limit; i++) {
764 txd = ring->entry[i].priv;
765
766 rt2x00_desc_read(txd, 1, &word);
767 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
768 ring->entry[i].data_dma);
769 rt2x00_desc_write(txd, 1, word);
770
771 rt2x00_desc_read(txd, 0, &word);
772 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
773 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
774 rt2x00_desc_write(txd, 0, word);
775 }
776
777 rt2x00_ring_index_clear(ring);
778}
779
780static int rt2500pci_init_rings(struct rt2x00_dev *rt2x00dev)
781{
782 u32 reg;
783
784 /*
785 * Initialize rings.
786 */
787 rt2500pci_init_rxring(rt2x00dev);
788 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
789 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
790 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
791 rt2500pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
792
793 /*
794 * Initialize registers.
795 */
796 rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
797 rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
798 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
799 rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
800 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
801 rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
802 rt2x00dev->bcn[1].stats.limit);
803 rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
804 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
805 rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
806
807 rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
808 rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
809 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
810 rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
811
812 rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
813 rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
814 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
815 rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
816
817 rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
818 rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
819 rt2x00dev->bcn[1].data_dma);
820 rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
821
822 rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
823 rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
824 rt2x00dev->bcn[0].data_dma);
825 rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
826
827 rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
828 rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
829 rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
830 rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
831
832 rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
833 rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
834 rt2x00dev->rx->data_dma);
835 rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
836
837 return 0;
838}
839
840static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
841{
842 u32 reg;
843
844 rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
845 rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
846 rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
847 rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
848
849 rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
850 rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
851 rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
852 rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
853 rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
854
855 rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
856 rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
857 rt2x00dev->rx->data_size / 128);
858 rt2x00pci_register_write(rt2x00dev, CSR9, reg);
859
860 /*
861 * Always use CWmin and CWmax set in descriptor.
862 */
863 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
864 rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
865 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
866
867 rt2x00pci_register_write(rt2x00dev, CNT3, 0);
868
869 rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
870 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
871 rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
872 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
873 rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
874 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
875 rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
876 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
877 rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
878 rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
879
880 rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
881 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
882 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
883 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
884 rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
885 rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
886
887 rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
888 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
889 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
890 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
891 rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
892 rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
893
894 rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
895 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
896 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
897 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
898 rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
899 rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
900
901 rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
902 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
903 rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
904 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
905 rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
906 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
907 rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
908 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
909 rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
910 rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
911
912 rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
913 rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
914 rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
915 rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
916 rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
917 rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
918 rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
919 rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
920 rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
921
922 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
923
924 rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
925 rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
926
927 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
928 return -EBUSY;
929
930 rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
931 rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
932
933 rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
934 rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
935 rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
936
937 rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
938 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
939 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
940 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
941 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
942 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
943 rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
944 rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
945
946 rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
947
948 rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
949
950 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
951 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
952 rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
953 rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
954 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
955
956 rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
957 rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
958 rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
959 rt2x00pci_register_write(rt2x00dev, CSR1, reg);
960
961 /*
962 * We must clear the FCS and FIFO error count.
963 * These registers are cleared on read,
964 * so we may pass a useless variable to store the value.
965 */
966 rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
967 rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
968
969 return 0;
970}
971
972static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
973{
974 unsigned int i;
975 u16 eeprom;
976 u8 reg_id;
977 u8 value;
978
979 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
980 rt2500pci_bbp_read(rt2x00dev, 0, &value);
981 if ((value != 0xff) && (value != 0x00))
982 goto continue_csr_init;
983 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
984 udelay(REGISTER_BUSY_DELAY);
985 }
986
987 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
988 return -EACCES;
989
990continue_csr_init:
991 rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
992 rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
993 rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
994 rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
995 rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
996 rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
997 rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
998 rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
999 rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
1000 rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
1001 rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
1002 rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
1003 rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
1004 rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
1005 rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
1006 rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
1007 rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
1008 rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
1009 rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
1010 rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
1011 rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
1012 rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
1013 rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
1014 rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
1015 rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
1016 rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
1017 rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
1018 rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
1019 rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
1020 rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
1021
1022 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1023 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1024 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1025
1026 if (eeprom != 0xffff && eeprom != 0x0000) {
1027 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1028 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1029 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1030 reg_id, value);
1031 rt2500pci_bbp_write(rt2x00dev, reg_id, value);
1032 }
1033 }
1034 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1035
1036 return 0;
1037}
1038
1039/*
1040 * Device state switch handlers.
1041 */
1042static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1043 enum dev_state state)
1044{
1045 u32 reg;
1046
1047 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1048 rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1049 state == STATE_RADIO_RX_OFF);
1050 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1051}
1052
1053static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1054 enum dev_state state)
1055{
1056 int mask = (state == STATE_RADIO_IRQ_OFF);
1057 u32 reg;
1058
1059 /*
1060 * When interrupts are being enabled, the interrupt registers
1061 * should clear the register to assure a clean state.
1062 */
1063 if (state == STATE_RADIO_IRQ_ON) {
1064 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1065 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1066 }
1067
1068 /*
1069 * Only toggle the interrupts bits we are going to use.
1070 * Non-checked interrupt bits are disabled by default.
1071 */
1072 rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1073 rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1074 rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1075 rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1076 rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1077 rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1078 rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1079}
1080
1081static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1082{
1083 /*
1084 * Initialize all registers.
1085 */
1086 if (rt2500pci_init_rings(rt2x00dev) ||
1087 rt2500pci_init_registers(rt2x00dev) ||
1088 rt2500pci_init_bbp(rt2x00dev)) {
1089 ERROR(rt2x00dev, "Register initialization failed.\n");
1090 return -EIO;
1091 }
1092
1093 /*
1094 * Enable interrupts.
1095 */
1096 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1097
1098 /*
1099 * Enable LED
1100 */
1101 rt2500pci_enable_led(rt2x00dev);
1102
1103 return 0;
1104}
1105
1106static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1107{
1108 u32 reg;
1109
1110 /*
1111 * Disable LED
1112 */
1113 rt2500pci_disable_led(rt2x00dev);
1114
1115 rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1116
1117 /*
1118 * Disable synchronisation.
1119 */
1120 rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1121
1122 /*
1123 * Cancel RX and TX.
1124 */
1125 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1126 rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1127 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1128
1129 /*
1130 * Disable interrupts.
1131 */
1132 rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1133}
1134
1135static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1136 enum dev_state state)
1137{
1138 u32 reg;
1139 unsigned int i;
1140 char put_to_sleep;
1141 char bbp_state;
1142 char rf_state;
1143
1144 put_to_sleep = (state != STATE_AWAKE);
1145
1146 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1147 rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1148 rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1149 rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1150 rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1151 rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1152
1153 /*
1154 * Device is not guaranteed to be in the requested state yet.
1155 * We must wait until the register indicates that the
1156 * device has entered the correct state.
1157 */
1158 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1159 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1160 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1161 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1162 if (bbp_state == state && rf_state == state)
1163 return 0;
1164 msleep(10);
1165 }
1166
1167 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1168 "current device state: bbp %d and rf %d.\n",
1169 state, bbp_state, rf_state);
1170
1171 return -EBUSY;
1172}
1173
1174static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1175 enum dev_state state)
1176{
1177 int retval = 0;
1178
1179 switch (state) {
1180 case STATE_RADIO_ON:
1181 retval = rt2500pci_enable_radio(rt2x00dev);
1182 break;
1183 case STATE_RADIO_OFF:
1184 rt2500pci_disable_radio(rt2x00dev);
1185 break;
1186 case STATE_RADIO_RX_ON:
1187 case STATE_RADIO_RX_OFF:
1188 rt2500pci_toggle_rx(rt2x00dev, state);
1189 break;
1190 case STATE_DEEP_SLEEP:
1191 case STATE_SLEEP:
1192 case STATE_STANDBY:
1193 case STATE_AWAKE:
1194 retval = rt2500pci_set_state(rt2x00dev, state);
1195 break;
1196 default:
1197 retval = -ENOTSUPP;
1198 break;
1199 }
1200
1201 return retval;
1202}
1203
1204/*
1205 * TX descriptor initialization
1206 */
1207static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1208 struct data_desc *txd,
4150c572 1209 struct txdata_entry_desc *desc,
95ea3627
ID		 1210 struct ieee80211_hdr *ieee80211hdr,
1211 unsigned int length,
1212 struct ieee80211_tx_control *control)
1213{
1214 u32 word;
1215
1216 /*
1217 * Start writing the descriptor words.
1218 */
1219 rt2x00_desc_read(txd, 2, &word);
1220 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1221 rt2x00_set_field32(&word, TXD_W2_AIFS, desc->aifs);
1222 rt2x00_set_field32(&word, TXD_W2_CWMIN, desc->cw_min);
1223 rt2x00_set_field32(&word, TXD_W2_CWMAX, desc->cw_max);
1224 rt2x00_desc_write(txd, 2, word);
1225
1226 rt2x00_desc_read(txd, 3, &word);
1227 rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, desc->signal);
1228 rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, desc->service);
1229 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, desc->length_low);
1230 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, desc->length_high);
1231 rt2x00_desc_write(txd, 3, word);
1232
1233 rt2x00_desc_read(txd, 10, &word);
1234 rt2x00_set_field32(&word, TXD_W10_RTS,
1235 test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1236 rt2x00_desc_write(txd, 10, word);
1237
1238 rt2x00_desc_read(txd, 0, &word);
1239 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1240 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1241 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1242 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1243 rt2x00_set_field32(&word, TXD_W0_ACK,
1244 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1245 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1246 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1247 rt2x00_set_field32(&word, TXD_W0_OFDM,
1248 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1249 rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1250 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1251 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1252 !!(control->flags &
1253 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1254 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1255 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1256 rt2x00_desc_write(txd, 0, word);
1257}
1258
1259/*
1260 * TX data initialization
1261 */
1262static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1263 unsigned int queue)
1264{
1265 u32 reg;
1266
1267 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1268 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1269 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1270 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1271 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1272 }
1273 return;
1274 }
1275
1276 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1277 if (queue == IEEE80211_TX_QUEUE_DATA0)
1278 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1279 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1280 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1281 else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1282 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1283 rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1284}
1285
1286/*
1287 * RX control handlers
1288 */
4150c572
JB		 1289static void rt2500pci_fill_rxdone(struct data_entry *entry,
1290 struct rxdata_entry_desc *desc)
95ea3627
ID		 1291{
1292 struct data_desc *rxd = entry->priv;
1293 u32 word0;
1294 u32 word2;
1295
1296 rt2x00_desc_read(rxd, 0, &word0);
1297 rt2x00_desc_read(rxd, 2, &word2);
1298
4150c572
JB		 1299 desc->flags = 0;
1300 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1301 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1302 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1303 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
95ea3627 1304
4150c572
JB		 1305 desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1306 desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
95ea3627 1307 entry->ring->rt2x00dev->rssi_offset;
4150c572
JB		 1308 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1309 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
95ea3627
ID		 1310}
1311
1312/*
1313 * Interrupt functions.
1314 */
1315static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1316{
1317 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1318 struct data_entry *entry;
1319 struct data_desc *txd;
1320 u32 word;
1321 int tx_status;
1322 int retry;
1323
1324 while (!rt2x00_ring_empty(ring)) {
1325 entry = rt2x00_get_data_entry_done(ring);
1326 txd = entry->priv;
1327 rt2x00_desc_read(txd, 0, &word);
1328
1329 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1330 !rt2x00_get_field32(word, TXD_W0_VALID))
1331 break;
1332
1333 /*
1334 * Obtain the status about this packet.
1335 */
1336 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1337 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1338
1339 rt2x00lib_txdone(entry, tx_status, retry);
1340
1341 /*
1342 * Make this entry available for reuse.
1343 */
1344 entry->flags = 0;
1345 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1346 rt2x00_desc_write(txd, 0, word);
1347 rt2x00_ring_index_done_inc(ring);
1348 }
1349
1350 /*
1351 * If the data ring was full before the txdone handler
1352 * we must make sure the packet queue in the mac80211 stack
1353 * is reenabled when the txdone handler has finished.
1354 */
1355 entry = ring->entry;
1356 if (!rt2x00_ring_full(ring))
1357 ieee80211_wake_queue(rt2x00dev->hw,
1358 entry->tx_status.control.queue);
1359}
1360
1361static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1362{
1363 struct rt2x00_dev *rt2x00dev = dev_instance;
1364 u32 reg;
1365
1366 /*
1367 * Get the interrupt sources & saved to local variable.
1368 * Write register value back to clear pending interrupts.
1369 */
1370 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1371 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1372
1373 if (!reg)
1374 return IRQ_NONE;
1375
1376 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1377 return IRQ_HANDLED;
1378
1379 /*
1380 * Handle interrupts, walk through all bits
1381 * and run the tasks, the bits are checked in order of
1382 * priority.
1383 */
1384
1385 /*
1386 * 1 - Beacon timer expired interrupt.
1387 */
1388 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1389 rt2x00lib_beacondone(rt2x00dev);
1390
1391 /*
1392 * 2 - Rx ring done interrupt.
1393 */
1394 if (rt2x00_get_field32(reg, CSR7_RXDONE))
1395 rt2x00pci_rxdone(rt2x00dev);
1396
1397 /*
1398 * 3 - Atim ring transmit done interrupt.
1399 */
1400 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1401 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1402
1403 /*
1404 * 4 - Priority ring transmit done interrupt.
1405 */
1406 if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1407 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1408
1409 /*
1410 * 5 - Tx ring transmit done interrupt.
1411 */
1412 if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1413 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1414
1415 return IRQ_HANDLED;
1416}
1417
1418/*
1419 * Device probe functions.
1420 */
1421static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1422{
1423 struct eeprom_93cx6 eeprom;
1424 u32 reg;
1425 u16 word;
1426 u8 *mac;
1427
1428 rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1429
1430 eeprom.data = rt2x00dev;
1431 eeprom.register_read = rt2500pci_eepromregister_read;
1432 eeprom.register_write = rt2500pci_eepromregister_write;
1433 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1434 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1435 eeprom.reg_data_in = 0;
1436 eeprom.reg_data_out = 0;
1437 eeprom.reg_data_clock = 0;
1438 eeprom.reg_chip_select = 0;
1439
1440 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1441 EEPROM_SIZE / sizeof(u16));
1442
1443 /*
1444 * Start validation of the data that has been read.
1445 */
1446 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1447 if (!is_valid_ether_addr(mac)) {
0795af57
JP		 1448 DECLARE_MAC_BUF(macbuf);
1449
95ea3627 1450 random_ether_addr(mac);
0795af57
JP		 1451 EEPROM(rt2x00dev, "MAC: %s\n",
1452 print_mac(macbuf, mac));
95ea3627
ID		 1453 }
1454
1455 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1456 if (word == 0xffff) {
1457 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1458 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 0);
1459 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 0);
1460 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE, 0);
1461 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1462 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1463 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1464 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1465 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1466 }
1467
1468 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1469 if (word == 0xffff) {
1470 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1471 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1472 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1473 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1474 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1475 }
1476
1477 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1478 if (word == 0xffff) {
1479 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1480 DEFAULT_RSSI_OFFSET);
1481 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1482 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1483 }
1484
1485 return 0;
1486}
1487
1488static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1489{
1490 u32 reg;
1491 u16 value;
1492 u16 eeprom;
1493
1494 /*
1495 * Read EEPROM word for configuration.
1496 */
1497 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1498
1499 /*
1500 * Identify RF chipset.
1501 */
1502 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1503 rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1504 rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1505
1506 if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1507 !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1508 !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1509 !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1510 !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1511 !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1512 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1513 return -ENODEV;
1514 }
1515
1516 /*
1517 * Identify default antenna configuration.
1518 */
1519 rt2x00dev->hw->conf.antenna_sel_tx =
1520 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1521 rt2x00dev->hw->conf.antenna_sel_rx =
1522 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1523
1524 /*
1525 * Store led mode, for correct led behaviour.
1526 */
1527 rt2x00dev->led_mode =
1528 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1529
1530 /*
1531 * Detect if this device has an hardware controlled radio.
1532 */
1533 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
066cb637 1534 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
95ea3627
ID		 1535
1536 /*
1537 * Check if the BBP tuning should be enabled.
1538 */
1539 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1540
1541 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1542 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1543
1544 /*
1545 * Read the RSSI <-> dBm offset information.
1546 */
1547 rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1548 rt2x00dev->rssi_offset =
1549 rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1550
1551 return 0;
1552}
1553
1554/*
1555 * RF value list for RF2522
1556 * Supports: 2.4 GHz
1557 */
1558static const struct rf_channel rf_vals_bg_2522[] = {
1559 { 1, 0x00002050, 0x000c1fda, 0x00000101, 0 },
1560 { 2, 0x00002050, 0x000c1fee, 0x00000101, 0 },
1561 { 3, 0x00002050, 0x000c2002, 0x00000101, 0 },
1562 { 4, 0x00002050, 0x000c2016, 0x00000101, 0 },
1563 { 5, 0x00002050, 0x000c202a, 0x00000101, 0 },
1564 { 6, 0x00002050, 0x000c203e, 0x00000101, 0 },
1565 { 7, 0x00002050, 0x000c2052, 0x00000101, 0 },
1566 { 8, 0x00002050, 0x000c2066, 0x00000101, 0 },
1567 { 9, 0x00002050, 0x000c207a, 0x00000101, 0 },
1568 { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1569 { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1570 { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1571 { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1572 { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1573};
1574
1575/*
1576 * RF value list for RF2523
1577 * Supports: 2.4 GHz
1578 */
1579static const struct rf_channel rf_vals_bg_2523[] = {
1580 { 1, 0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1581 { 2, 0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1582 { 3, 0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1583 { 4, 0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1584 { 5, 0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1585 { 6, 0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1586 { 7, 0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1587 { 8, 0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1588 { 9, 0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1589 { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1590 { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1591 { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1592 { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1593 { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1594};
1595
1596/*
1597 * RF value list for RF2524
1598 * Supports: 2.4 GHz
1599 */
1600static const struct rf_channel rf_vals_bg_2524[] = {
1601 { 1, 0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1602 { 2, 0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1603 { 3, 0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1604 { 4, 0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1605 { 5, 0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1606 { 6, 0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1607 { 7, 0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1608 { 8, 0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1609 { 9, 0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1610 { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1611 { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1612 { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1613 { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1614 { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1615};
1616
1617/*
1618 * RF value list for RF2525
1619 * Supports: 2.4 GHz
1620 */
1621static const struct rf_channel rf_vals_bg_2525[] = {
1622 { 1, 0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1623 { 2, 0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1624 { 3, 0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1625 { 4, 0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1626 { 5, 0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1627 { 6, 0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1628 { 7, 0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1629 { 8, 0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1630 { 9, 0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1631 { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1632 { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1633 { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1634 { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1635 { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1636};
1637
1638/*
1639 * RF value list for RF2525e
1640 * Supports: 2.4 GHz
1641 */
1642static const struct rf_channel rf_vals_bg_2525e[] = {
1643 { 1, 0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1644 { 2, 0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1645 { 3, 0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1646 { 4, 0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1647 { 5, 0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1648 { 6, 0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1649 { 7, 0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1650 { 8, 0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1651 { 9, 0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1652 { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1653 { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1654 { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1655 { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1656 { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1657};
1658
1659/*
1660 * RF value list for RF5222
1661 * Supports: 2.4 GHz & 5.2 GHz
1662 */
1663static const struct rf_channel rf_vals_5222[] = {
1664 { 1, 0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1665 { 2, 0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1666 { 3, 0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1667 { 4, 0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1668 { 5, 0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1669 { 6, 0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1670 { 7, 0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1671 { 8, 0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1672 { 9, 0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1673 { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1674 { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1675 { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1676 { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1677 { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1678
1679 /* 802.11 UNI / HyperLan 2 */
1680 { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1681 { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1682 { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1683 { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1684 { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1685 { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1686 { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1687 { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1688
1689 /* 802.11 HyperLan 2 */
1690 { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1691 { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1692 { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1693 { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1694 { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1695 { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1696 { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1697 { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1698 { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1699 { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1700
1701 /* 802.11 UNII */
1702 { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1703 { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1704 { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1705 { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1706 { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1707};
1708
1709static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1710{
1711 struct hw_mode_spec *spec = &rt2x00dev->spec;
1712 u8 *txpower;
1713 unsigned int i;
1714
1715 /*
1716 * Initialize all hw fields.
1717 */
4150c572 1718 rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
95ea3627
ID		 1719 rt2x00dev->hw->extra_tx_headroom = 0;
1720 rt2x00dev->hw->max_signal = MAX_SIGNAL;
1721 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1722 rt2x00dev->hw->queues = 2;
1723
1724 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1725 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1726 rt2x00_eeprom_addr(rt2x00dev,
1727 EEPROM_MAC_ADDR_0));
1728
1729 /*
1730 * Convert tx_power array in eeprom.
1731 */
1732 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1733 for (i = 0; i < 14; i++)
1734 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1735
1736 /*
1737 * Initialize hw_mode information.
1738 */
1739 spec->num_modes = 2;
1740 spec->num_rates = 12;
1741 spec->tx_power_a = NULL;
1742 spec->tx_power_bg = txpower;
1743 spec->tx_power_default = DEFAULT_TXPOWER;
1744
1745 if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1746 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1747 spec->channels = rf_vals_bg_2522;
1748 } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1749 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1750 spec->channels = rf_vals_bg_2523;
1751 } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1752 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1753 spec->channels = rf_vals_bg_2524;
1754 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1755 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1756 spec->channels = rf_vals_bg_2525;
1757 } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1758 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1759 spec->channels = rf_vals_bg_2525e;
1760 } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1761 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1762 spec->channels = rf_vals_5222;
1763 spec->num_modes = 3;
1764 }
1765}
1766
1767static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1768{
1769 int retval;
1770
1771 /*
1772 * Allocate eeprom data.
1773 */
1774 retval = rt2500pci_validate_eeprom(rt2x00dev);
1775 if (retval)
1776 return retval;
1777
1778 retval = rt2500pci_init_eeprom(rt2x00dev);
1779 if (retval)
1780 return retval;
1781
1782 /*
1783 * Initialize hw specifications.
1784 */
1785 rt2500pci_probe_hw_mode(rt2x00dev);
1786
1787 /*
1788 * This device requires the beacon ring
1789 */
066cb637 1790 __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
95ea3627
ID		 1791
1792 /*
1793 * Set the rssi offset.
1794 */
1795 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1796
1797 return 0;
1798}
1799
1800/*
1801 * IEEE80211 stack callback functions.
1802 */
4150c572
JB		 1803static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1804 unsigned int changed_flags,
1805 unsigned int *total_flags,
1806 int mc_count,
1807 struct dev_addr_list *mc_list)
1808{
1809 struct rt2x00_dev *rt2x00dev = hw->priv;
1810 struct interface *intf = &rt2x00dev->interface;
1811 u32 reg;
1812
1813 /*
1814 * Mask off any flags we are going to ignore from
1815 * the total_flags field.
1816 */
1817 *total_flags &=
1818 FIF_ALLMULTI |
1819 FIF_FCSFAIL |
1820 FIF_PLCPFAIL |
1821 FIF_CONTROL |
1822 FIF_OTHER_BSS |
1823 FIF_PROMISC_IN_BSS;
1824
1825 /*
1826 * Apply some rules to the filters:
1827 * - Some filters imply different filters to be set.
1828 * - Some things we can't filter out at all.
1829 * - Some filters are set based on interface type.
1830 */
1831 if (mc_count)
1832 *total_flags |= FIF_ALLMULTI;
5886d0db
ID		 1833 if (*total_flags & FIF_OTHER_BSS ||
1834 *total_flags & FIF_PROMISC_IN_BSS)
4150c572
JB		 1835 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1836 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1837 *total_flags |= FIF_PROMISC_IN_BSS;
1838
1839 /*
1840 * Check if there is any work left for us.
1841 */
1842 if (intf->filter == *total_flags)
1843 return;
1844 intf->filter = *total_flags;
1845
1846 /*
1847 * Start configuration steps.
1848 * Note that the version error will always be dropped
1849 * and broadcast frames will always be accepted since
1850 * there is no filter for it at this time.
1851 */
1852 rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1853 rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1854 !(*total_flags & FIF_FCSFAIL));
1855 rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1856 !(*total_flags & FIF_PLCPFAIL));
1857 rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1858 !(*total_flags & FIF_CONTROL));
1859 rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1860 !(*total_flags & FIF_PROMISC_IN_BSS));
1861 rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1862 !(*total_flags & FIF_PROMISC_IN_BSS));
1863 rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1864 rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1865 !(*total_flags & FIF_ALLMULTI));
1866 rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1867 rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1868}
1869
95ea3627
ID		 1870static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1871 u32 short_retry, u32 long_retry)
1872{
1873 struct rt2x00_dev *rt2x00dev = hw->priv;
1874 u32 reg;
1875
1876 rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1877 rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1878 rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1879 rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1880
1881 return 0;
1882}
1883
1884static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1885{
1886 struct rt2x00_dev *rt2x00dev = hw->priv;
1887 u64 tsf;
1888 u32 reg;
1889
1890 rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1891 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1892 rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1893 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1894
1895 return tsf;
1896}
1897
1898static void rt2500pci_reset_tsf(struct ieee80211_hw *hw)
1899{
1900 struct rt2x00_dev *rt2x00dev = hw->priv;
1901
1902 rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1903 rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1904}
1905
1906static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1907{
1908 struct rt2x00_dev *rt2x00dev = hw->priv;
1909 u32 reg;
1910
1911 rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1912 return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1913}
1914
1915static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1916 .tx = rt2x00mac_tx,
4150c572
JB		 1917 .start = rt2x00mac_start,
1918 .stop = rt2x00mac_stop,
95ea3627
ID		 1919 .add_interface = rt2x00mac_add_interface,
1920 .remove_interface = rt2x00mac_remove_interface,
1921 .config = rt2x00mac_config,
1922 .config_interface = rt2x00mac_config_interface,
4150c572 1923 .configure_filter = rt2500pci_configure_filter,
95ea3627
ID		 1924 .get_stats = rt2x00mac_get_stats,
1925 .set_retry_limit = rt2500pci_set_retry_limit,
1926 .conf_tx = rt2x00mac_conf_tx,
1927 .get_tx_stats = rt2x00mac_get_tx_stats,
1928 .get_tsf = rt2500pci_get_tsf,
1929 .reset_tsf = rt2500pci_reset_tsf,
1930 .beacon_update = rt2x00pci_beacon_update,
1931 .tx_last_beacon = rt2500pci_tx_last_beacon,
1932};
1933
1934static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1935 .irq_handler = rt2500pci_interrupt,
1936 .probe_hw = rt2500pci_probe_hw,
1937 .initialize = rt2x00pci_initialize,
1938 .uninitialize = rt2x00pci_uninitialize,
1939 .set_device_state = rt2500pci_set_device_state,
1940#ifdef CONFIG_RT2500PCI_RFKILL
1941 .rfkill_poll = rt2500pci_rfkill_poll,
1942#endif /* CONFIG_RT2500PCI_RFKILL */
1943 .link_stats = rt2500pci_link_stats,
1944 .reset_tuner = rt2500pci_reset_tuner,
1945 .link_tuner = rt2500pci_link_tuner,
1946 .write_tx_desc = rt2500pci_write_tx_desc,
1947 .write_tx_data = rt2x00pci_write_tx_data,
1948 .kick_tx_queue = rt2500pci_kick_tx_queue,
1949 .fill_rxdone = rt2500pci_fill_rxdone,
1950 .config_mac_addr = rt2500pci_config_mac_addr,
1951 .config_bssid = rt2500pci_config_bssid,
95ea3627
ID		 1952 .config_type = rt2500pci_config_type,
1953 .config = rt2500pci_config,
1954};
1955
1956static const struct rt2x00_ops rt2500pci_ops = {
1957 .name = DRV_NAME,
1958 .rxd_size = RXD_DESC_SIZE,
1959 .txd_size = TXD_DESC_SIZE,
1960 .eeprom_size = EEPROM_SIZE,
1961 .rf_size = RF_SIZE,
1962 .lib = &rt2500pci_rt2x00_ops,
1963 .hw = &rt2500pci_mac80211_ops,
1964#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1965 .debugfs = &rt2500pci_rt2x00debug,
1966#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1967};
1968
1969/*
1970 * RT2500pci module information.
1971 */
1972static struct pci_device_id rt2500pci_device_table[] = {
1973 { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1974 { 0, }
1975};
1976
1977MODULE_AUTHOR(DRV_PROJECT);
1978MODULE_VERSION(DRV_VERSION);
1979MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1980MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1981MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1982MODULE_LICENSE("GPL");
1983
1984static struct pci_driver rt2500pci_driver = {
1985 .name = DRV_NAME,
1986 .id_table = rt2500pci_device_table,
1987 .probe = rt2x00pci_probe,
1988 .remove = __devexit_p(rt2x00pci_remove),
1989 .suspend = rt2x00pci_suspend,
1990 .resume = rt2x00pci_resume,
1991};
1992
1993static int __init rt2500pci_init(void)
1994{
1995 return pci_register_driver(&rt2500pci_driver);
1996}
1997
1998static void __exit rt2500pci_exit(void)
1999{
2000 pci_unregister_driver(&rt2500pci_driver);
2001}
2002
2003module_init(rt2500pci_init);
2004module_exit(rt2500pci_exit);
Linux kernel - Deliverables
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